drm/amd/powerplay: move the function of is_dpm_running to asic file
authorKevin Wang <kevin1.wang@amd.com>
Tue, 5 Mar 2019 07:42:16 +0000 (15:42 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 21 Jun 2019 23:59:25 +0000 (18:59 -0500)
the function os is_dpm_running is aisc related function,
so move them to asic file.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
drivers/gpu/drm/amd/powerplay/smu_v11_0.c
drivers/gpu/drm/amd/powerplay/vega20_ppt.c

index f467767482f5dbba3dc7590cd1511a3c7c9a3481..73d70eaa837e6d42e3d9727283658b2bd040b3ad 100644 (file)
@@ -474,6 +474,7 @@ struct pptable_funcs {
        int (*set_cpu_power_state)(struct smu_context *smu);
        int (*set_ppfeature_status)(struct smu_context *smu, uint64_t ppfeatures);
        int (*get_ppfeature_status)(struct smu_context *smu, char *buf);
+       bool (*is_dpm_running)(struct smu_context *smu);
 };
 
 struct smu_funcs
@@ -505,7 +506,6 @@ struct smu_funcs
        int (*init_display)(struct smu_context *smu);
        int (*set_allowed_mask)(struct smu_context *smu);
        int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
-       bool (*is_dpm_running)(struct smu_context *smu);
        int (*update_feature_enable_state)(struct smu_context *smu, uint32_t feature_id, bool enabled);
        int (*notify_display_change)(struct smu_context *smu);
        int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool def);
@@ -623,7 +623,7 @@ struct smu_funcs
 #define smu_feature_get_enabled_mask(smu, mask, num) \
        ((smu)->funcs->get_enabled_mask? (smu)->funcs->get_enabled_mask((smu), (mask), (num)) : 0)
 #define smu_is_dpm_running(smu) \
-       ((smu)->funcs->is_dpm_running ? (smu)->funcs->is_dpm_running((smu)) : 0)
+       ((smu)->ppt_funcs->is_dpm_running ? (smu)->ppt_funcs->is_dpm_running((smu)) : 0)
 #define smu_feature_update_enable_state(smu, feature_id, enabled) \
        ((smu)->funcs->update_feature_enable_state? (smu)->funcs->update_feature_enable_state((smu), (feature_id), (enabled)) : 0)
 #define smu_notify_display_change(smu) \
index 664de88f7f432c964a11156f5c42849452e71231..a358bbd8159cc3b6d96c1b2f175d5a63cd95ed10 100644 (file)
@@ -52,16 +52,6 @@ MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
 #define SMU11_TEMPERATURE_UNITS_PER_CENTIGRADES 1000
 #define SMU11_VOLTAGE_SCALE 4
 
-#define SMC_DPM_FEATURE (FEATURE_DPM_PREFETCHER_MASK | \
-                        FEATURE_DPM_GFXCLK_MASK | \
-                        FEATURE_DPM_UCLK_MASK | \
-                        FEATURE_DPM_SOCCLK_MASK | \
-                        FEATURE_DPM_UVD_MASK | \
-                        FEATURE_DPM_VCE_MASK | \
-                        FEATURE_DPM_MP0CLK_MASK | \
-                        FEATURE_DPM_LINK_MASK | \
-                        FEATURE_DPM_DCEFCLK_MASK)
-
 static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
                                              uint16_t msg)
 {
@@ -848,17 +838,6 @@ static int smu_v11_0_get_enabled_mask(struct smu_context *smu,
        return ret;
 }
 
-static bool smu_v11_0_is_dpm_running(struct smu_context *smu)
-{
-       int ret = 0;
-       uint32_t feature_mask[2];
-       unsigned long feature_enabled;
-       ret = smu_v11_0_get_enabled_mask(smu, feature_mask, 2);
-       feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
-                          ((uint64_t)feature_mask[1] << 32));
-       return !!(feature_enabled & SMC_DPM_FEATURE);
-}
-
 static int smu_v11_0_system_features_control(struct smu_context *smu,
                                             bool en)
 {
@@ -1876,7 +1855,6 @@ static const struct smu_funcs smu_v11_0_funcs = {
        .init_display = smu_v11_0_init_display,
        .set_allowed_mask = smu_v11_0_set_allowed_mask,
        .get_enabled_mask = smu_v11_0_get_enabled_mask,
-       .is_dpm_running = smu_v11_0_is_dpm_running,
        .system_features_control = smu_v11_0_system_features_control,
        .update_feature_enable_state = smu_v11_0_update_feature_enable_state,
        .notify_display_change = smu_v11_0_notify_display_change,
index 06f91969cf76b903a11511b0ebd4fa37753defc0..e070c7e7cdb7fb8171d2c5db1cb2240a020608ac 100644 (file)
 #define MSG_MAP(msg) \
        [SMU_MSG_##msg] = PPSMC_MSG_##msg
 
+#define SMC_DPM_FEATURE (FEATURE_DPM_PREFETCHER_MASK | \
+                        FEATURE_DPM_GFXCLK_MASK | \
+                        FEATURE_DPM_UCLK_MASK | \
+                        FEATURE_DPM_SOCCLK_MASK | \
+                        FEATURE_DPM_UVD_MASK | \
+                        FEATURE_DPM_VCE_MASK | \
+                        FEATURE_DPM_MP0CLK_MASK | \
+                        FEATURE_DPM_LINK_MASK | \
+                        FEATURE_DPM_DCEFCLK_MASK)
+
 static int vega20_message_map[SMU_MSG_MAX_COUNT] = {
        MSG_MAP(TestMessage),
        MSG_MAP(GetSmuVersion),
@@ -2794,6 +2804,17 @@ static int vega20_read_sensor(struct smu_context *smu,
        return ret;
 }
 
+static bool vega20_is_dpm_running(struct smu_context *smu)
+{
+       int ret = 0;
+       uint32_t feature_mask[2];
+       unsigned long feature_enabled;
+       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
+       feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
+                          ((uint64_t)feature_mask[1] << 32));
+       return !!(feature_enabled & SMC_DPM_FEATURE);
+}
+
 static const struct pptable_funcs vega20_ppt_funcs = {
        .alloc_dpm_context = vega20_allocate_dpm_context,
        .store_powerplay_table = vega20_store_powerplay_table,
@@ -2832,6 +2853,7 @@ static const struct pptable_funcs vega20_ppt_funcs = {
        .get_profiling_clk_mask = vega20_get_profiling_clk_mask,
        .set_ppfeature_status = vega20_set_ppfeature_status,
        .get_ppfeature_status = vega20_get_ppfeature_status,
+       .is_dpm_running = vega20_is_dpm_running,
 };
 
 void vega20_set_ppt_funcs(struct smu_context *smu)