drm/i915/gvt: do not let TRTTE and 0x4dfc write passthrough to hardware
authorYan Zhao <yan.y.zhao@intel.com>
Wed, 8 May 2019 02:16:44 +0000 (22:16 -0400)
committerZhenyu Wang <zhenyuw@linux.intel.com>
Tue, 21 May 2019 02:58:07 +0000 (10:58 +0800)
the vGPU write on TRTTE and 0x4dfc is now write to vreg first. their
values all be restored hardware when context switching.

Fixes: e39c5add3221 ("drm/i915/gvt: vGPU MMIO virtualization")
Acked-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Yan Zhao <yan.y.zhao@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
drivers/gpu/drm/i915/gvt/handlers.c

index 90673fca792f3a888b508d77f5f8688a9128ce92..e09bd6e0cc4d6d85b21ebc22f5ff0bdbf8cf601d 100644 (file)
@@ -1364,7 +1364,6 @@ static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset,
 static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset,
                void *p_data, unsigned int bytes)
 {
-       struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
        u32 trtte = *(u32 *)p_data;
 
        if ((trtte & 1) && (trtte & (1 << 1)) == 0) {
@@ -1373,11 +1372,6 @@ static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset,
                return -EINVAL;
        }
        write_vreg(vgpu, offset, p_data, bytes);
-       /* TRTTE is not per-context */
-
-       mmio_hw_access_pre(dev_priv);
-       I915_WRITE(_MMIO(offset), vgpu_vreg(vgpu, offset));
-       mmio_hw_access_post(dev_priv);
 
        return 0;
 }
@@ -1385,15 +1379,6 @@ static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset,
 static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset,
                void *p_data, unsigned int bytes)
 {
-       struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
-       u32 val = *(u32 *)p_data;
-
-       if (val & 1) {
-               /* unblock hw logic */
-               mmio_hw_access_pre(dev_priv);
-               I915_WRITE(_MMIO(offset), val);
-               mmio_hw_access_post(dev_priv);
-       }
        write_vreg(vgpu, offset, p_data, bytes);
        return 0;
 }