Tegra: init normal/crash console for platforms

The BL2 fills in the UART controller ID to be used as the normal as
well as the crash console on Tegra platforms. The controller ID to
UART controller base address mapping is handled by each Tegra SoC
the base addresses might change across Tegra chips.

This patch adds the handler to parse the platform params to get the
UART ID for the per-soc handlers.

Change-Id: I4d167b20a59aaf52a31e2a8edf94d8d6f89598fa
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

diff --git a/docs/plat/nvidia-tegra.md b/docs/plat/nvidia-tegra.md
index e6ec462280cd9caa92897a7d7abf7c8dad0e25eb..f82085b1369ac0c5524b427dbbf19529b3874f09 100644 (file)
--- a/docs/plat/nvidia-tegra.md
+++ b/docs/plat/nvidia-tegra.md
@@ -65,14 +65,17 @@ to the build command line.
 The Tegra platform code expects a pointer to the following platform specific
 structure via 'x1' register from the BL2 layer which is used by the
 bl31_early_platform_setup() handler to extract the TZDRAM carveout base and
-size for loading the Trusted OS. The Tegra memory controller driver programs
-this base/size in order to restrict NS accesses.
+size for loading the Trusted OS and the UART port ID to be used. The Tegra
+memory controller driver programs this base/size in order to restrict NS
+accesses.
 
 typedef struct plat_params_from_bl2 {
        /* TZ memory size */
        uint64_t tzdram_size;
        /* TZ memory base */
        uint64_t tzdram_base;
+       /* UART port ID */
+       int uart_id;
 } plat_params_from_bl2_t;
 
 Power Management

diff --git a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S
index b2fc9a75bc6284ccc760838fa26082e18d01f330..6851b1502ffd614527288137e36aee762a86dbf1 100644 (file)
--- a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S
+++ b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S
@@ -66,6 +66,7 @@
        .globl  tegra_sec_entry_point
        .globl  ns_image_entrypoint
        .globl  tegra_bl31_phys_base
+       .globl  tegra_console_base
 
        /* ---------------------
         * Common CPU init code
@@ -226,7 +227,8 @@ endfunc platform_mem_init
         * ---------------------------------------------
         */
 func plat_crash_console_init
-       mov_imm x0, TEGRA_BOOT_UART_BASE
+       adr     x0, tegra_console_base
+       ldr     x0, [x0]
        mov_imm x1, TEGRA_BOOT_UART_CLK_IN_HZ
        mov_imm x2, TEGRA_CONSOLE_BAUDRATE
        b       console_core_init
@@ -240,7 +242,8 @@ endfunc plat_crash_console_init
         * ---------------------------------------------
         */
 func plat_crash_console_putc
-       mov_imm x1, TEGRA_BOOT_UART_BASE
+       adr     x1, tegra_console_base
+       ldr     x1, [x1]
        b       console_core_putc
 endfunc plat_crash_console_putc
 
@@ -402,3 +405,10 @@ ns_image_entrypoint:
         */
 tegra_bl31_phys_base:
        .quad   0
+
+       /* --------------------------------------------------
+        * UART controller base for console init
+        * --------------------------------------------------
+        */
+tegra_console_base:
+       .quad   0

diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c
index f762d6a06a1e741e94e4119ee915be557103d1f0..3a9514bda92e9b86c311c680268c783ae315c4c7 100644 (file)
--- a/plat/nvidia/tegra/common/tegra_bl31_setup.c
+++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c
@@ -55,6 +55,7 @@ extern unsigned long __RO_END__;
 extern unsigned long __BL31_END__;
 
 extern uint64_t tegra_bl31_phys_base;
+extern uint64_t tegra_console_base;
 
 /*
  * The next 3 constants identify the extents of the code, RO data region and the
@@ -114,17 +115,6 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
 #if DEBUG
        int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
 #endif
-       /*
-        * Configure the UART port to be used as the console
-        */
-       console_init(TEGRA_BOOT_UART_BASE, TEGRA_BOOT_UART_CLK_IN_HZ,
-                       TEGRA_CONSOLE_BAUDRATE);
-
-       /* Initialise crash console */
-       plat_crash_console_init();
-
-       INFO("BL3-1: Boot CPU: %s Processor [%lx]\n", (impl == DENVER_IMPL) ?
-               "Denver" : "ARM", read_mpidr());
 
        /*
         * Copy BL3-3, BL3-2 entry point information.
@@ -142,6 +132,27 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
        assert(plat_params);
        plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base;
        plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size;
+       plat_bl31_params_from_bl2.uart_id = plat_params->uart_id;
+
+       /*
+        * Get the base address of the UART controller to be used for the
+        * console
+        */
+       assert(plat_params->uart_id);
+       tegra_console_base = plat_get_console_from_id(plat_params->uart_id);
+
+       /*
+        * Configure the UART port to be used as the console
+        */
+       assert(tegra_console_base);
+       console_init(tegra_console_base, TEGRA_BOOT_UART_CLK_IN_HZ,
+               TEGRA_CONSOLE_BAUDRATE);
+
+       /* Initialise crash console */
+       plat_crash_console_init();
+
+       INFO("BL3-1: Boot CPU: %s Processor [%lx]\n", (impl == DENVER_IMPL) ?
+               "Denver" : "ARM", read_mpidr());
 }
 
 /*******************************************************************************

diff --git a/plat/nvidia/tegra/include/t132/tegra_def.h b/plat/nvidia/tegra/include/t132/tegra_def.h
index 683c903815082b637c1da24de7bdcaf8eaa93932..09d9b74290ae3466fda1fa97574b17978f1250a9 100644 (file)
--- a/plat/nvidia/tegra/include/t132/tegra_def.h
+++ b/plat/nvidia/tegra/include/t132/tegra_def.h
@@ -70,6 +70,15 @@
  ******************************************************************************/
 #define TEGRA_EVP_BASE                 0x6000F000
 
+/*******************************************************************************
+ * Tegra UART controller base addresses
+ ******************************************************************************/
+#define TEGRA_UARTA_BASE               0x70006000
+#define TEGRA_UARTB_BASE               0x70006040
+#define TEGRA_UARTC_BASE               0x70006200
+#define TEGRA_UARTD_BASE               0x70006300
+#define TEGRA_UARTE_BASE               0x70006400
+
 /*******************************************************************************
  * Tegra Power Mgmt Controller constants
  ******************************************************************************/

diff --git a/plat/nvidia/tegra/include/t210/tegra_def.h b/plat/nvidia/tegra/include/t210/tegra_def.h
index ca78d50e6cc0cff22b3e926d585ddc4eec52d294..8be39bb32b763fa3d515c121a73d08fd77161600 100644 (file)
--- a/plat/nvidia/tegra/include/t210/tegra_def.h
+++ b/plat/nvidia/tegra/include/t210/tegra_def.h
@@ -95,6 +95,15 @@
  ******************************************************************************/
 #define TEGRA_EVP_BASE                 0x6000F000
 
+/*******************************************************************************
+ * Tegra UART controller base addresses
+ ******************************************************************************/
+#define TEGRA_UARTA_BASE               0x70006000
+#define TEGRA_UARTB_BASE               0x70006040
+#define TEGRA_UARTC_BASE               0x70006200
+#define TEGRA_UARTD_BASE               0x70006300
+#define TEGRA_UARTE_BASE               0x70006400
+
 /*******************************************************************************
  * Tegra Power Mgmt Controller constants
  ******************************************************************************/

diff --git a/plat/nvidia/tegra/include/tegra_private.h b/plat/nvidia/tegra/include/tegra_private.h
index 9e6602338478be39f20df7a5cf257e25d2cc96da..75416ec3c001b3d6b857204c26accb7d9feeaf9b 100644 (file)
--- a/plat/nvidia/tegra/include/tegra_private.h
+++ b/plat/nvidia/tegra/include/tegra_private.h
@@ -47,6 +47,8 @@ typedef struct plat_params_from_bl2 {
        uint64_t tzdram_size;
        /* TZ memory base */
        uint64_t tzdram_base;
+       /* UART port ID */
+       int uart_id;
 } plat_params_from_bl2_t;
 
 /* Declarations for plat_psci_handlers.c */
@@ -55,6 +57,7 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state,
 
 /* Declarations for plat_setup.c */
 const mmap_region_t *plat_get_mmio_map(void);
+uint32_t plat_get_console_from_id(int id);
 
 /* Declarations for plat_secondary.c */
 void plat_secondary_setup(void);

diff --git a/plat/nvidia/tegra/soc/t132/plat_setup.c b/plat/nvidia/tegra/soc/t132/plat_setup.c
index 0d66413757c847eb006330b3a6628ac20a97d647..337a2c59ff8780fa59a6ac0ba7ab52068a0d2f57 100644 (file)
--- a/plat/nvidia/tegra/soc/t132/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t132/plat_setup.c
@@ -78,3 +78,31 @@ unsigned int plat_get_syscnt_freq2(void)
 {
        return 12000000;
 }
+
+/*******************************************************************************
+ * Maximum supported UART controllers
+ ******************************************************************************/
+#define TEGRA132_MAX_UART_PORTS                5
+
+/*******************************************************************************
+ * This variable holds the UART port base addresses
+ ******************************************************************************/
+static uint32_t tegra132_uart_addresses[TEGRA132_MAX_UART_PORTS + 1] = {
+       0,      /* undefined - treated as an error case */
+       TEGRA_UARTA_BASE,
+       TEGRA_UARTB_BASE,
+       TEGRA_UARTC_BASE,
+       TEGRA_UARTD_BASE,
+       TEGRA_UARTE_BASE,
+};
+
+/*******************************************************************************
+ * Retrieve the UART controller base to be used as the console
+ ******************************************************************************/
+uint32_t plat_get_console_from_id(int id)
+{
+       if (id > TEGRA132_MAX_UART_PORTS)
+               return 0;
+
+       return tegra132_uart_addresses[id];
+}

diff --git a/plat/nvidia/tegra/soc/t132/platform_t132.mk b/plat/nvidia/tegra/soc/t132/platform_t132.mk
index 466e7cd3600bebd6c3b51800a63efe7bfe71d9f4..6b9fce3b4fb4081cbc28b573ff8498acc8934be7 100644 (file)
--- a/plat/nvidia/tegra/soc/t132/platform_t132.mk
+++ b/plat/nvidia/tegra/soc/t132/platform_t132.mk
@@ -28,9 +28,6 @@
 # POSSIBILITY OF SUCH DAMAGE.
 #
 
-TEGRA_BOOT_UART_BASE           := 0x70006300
-$(eval $(call add_define,TEGRA_BOOT_UART_BASE))
-
 TZDRAM_BASE                    := 0xF5C00000
 $(eval $(call add_define,TZDRAM_BASE))
 

diff --git a/plat/nvidia/tegra/soc/t210/plat_setup.c b/plat/nvidia/tegra/soc/t210/plat_setup.c
index 70a55c696d283c8035dfe597818a73a9e034d41c..246faf8741f6b4cdaf5283d4159448d4b9e06d2b 100644 (file)
--- a/plat/nvidia/tegra/soc/t210/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t210/plat_setup.c
@@ -84,3 +84,31 @@ unsigned int plat_get_syscnt_freq2(void)
 {
        return 19200000;
 }
+
+/*******************************************************************************
+ * Maximum supported UART controllers
+ ******************************************************************************/
+#define TEGRA210_MAX_UART_PORTS                5
+
+/*******************************************************************************
+ * This variable holds the UART port base addresses
+ ******************************************************************************/
+static uint32_t tegra210_uart_addresses[TEGRA210_MAX_UART_PORTS + 1] = {
+       0,      /* undefined - treated as an error case */
+       TEGRA_UARTA_BASE,
+       TEGRA_UARTB_BASE,
+       TEGRA_UARTC_BASE,
+       TEGRA_UARTD_BASE,
+       TEGRA_UARTE_BASE,
+};
+
+/*******************************************************************************
+ * Retrieve the UART controller base to be used as the console
+ ******************************************************************************/
+uint32_t plat_get_console_from_id(int id)
+{
+       if (id > TEGRA210_MAX_UART_PORTS)
+               return 0;
+
+       return tegra210_uart_addresses[id];
+}

diff --git a/plat/nvidia/tegra/soc/t210/platform_t210.mk b/plat/nvidia/tegra/soc/t210/platform_t210.mk
index 76bc113d4f199829df7ff3ec5833f5ef88193e62..d83c54db0d33b13cfe9fc51efcc6093303e2d7ba 100644 (file)
--- a/plat/nvidia/tegra/soc/t210/platform_t210.mk
+++ b/plat/nvidia/tegra/soc/t210/platform_t210.mk
@@ -28,9 +28,6 @@
 # POSSIBILITY OF SUCH DAMAGE.
 #
 
-TEGRA_BOOT_UART_BASE                   := 0x70006000
-$(eval $(call add_define,TEGRA_BOOT_UART_BASE))
-
 TZDRAM_BASE                            := 0xFDC00000
 $(eval $(call add_define,TZDRAM_BASE))