Add macros for retention control in Cortex-A53/A57

This patch adds macros suitable for programming the Advanced
SIMD/Floating-point (only Cortex-A53), CPU and L2 dynamic
retention control policy in the CPUECTLR_EL1 and L2ECTLR
registers.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

diff --git a/include/lib/cpus/aarch64/cortex_a53.h b/include/lib/cpus/aarch64/cortex_a53.h
index 6e71f9ca59fe01891fbbd2ba534d6e1adcf99bde..169d8f4b6985d6714ac1f3911e6df5d860d38011 100644 (file)
--- a/include/lib/cpus/aarch64/cortex_a53.h
+++ b/include/lib/cpus/aarch64/cortex_a53.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -34,6 +34,15 @@
 /* Cortex-A53 midr for revision 0 */
 #define CORTEX_A53_MIDR 0x410FD030
 
+/* Retention timer tick definitions */
+#define RETENTION_ENTRY_TICKS_2                0x1
+#define RETENTION_ENTRY_TICKS_8                0x2
+#define RETENTION_ENTRY_TICKS_32       0x3
+#define RETENTION_ENTRY_TICKS_64       0x4
+#define RETENTION_ENTRY_TICKS_128      0x5
+#define RETENTION_ENTRY_TICKS_256      0x6
+#define RETENTION_ENTRY_TICKS_512      0x7
+
 /*******************************************************************************
  * CPU Extended Control register specific definitions.
  ******************************************************************************/
@@ -41,6 +50,12 @@
 
 #define CPUECTLR_SMP_BIT               (1 << 6)
 
+#define CPUECTLR_CPU_RET_CTRL_SHIFT    0
+#define CPUECTLR_CPU_RET_CTRL_MASK     (0x7 << CPUECTLR_CPU_RET_CTRL_SHIFT)
+
+#define CPUECTLR_FPU_RET_CTRL_SHIFT    3
+#define CPUECTLR_FPU_RET_CTRL_MASK     (0x7 << CPUECTLR_FPU_RET_CTRL_SHIFT)
+
 /*******************************************************************************
  * CPU Auxiliary Control register specific definitions.
  ******************************************************************************/
@@ -56,4 +71,12 @@
 #define L2ACTLR_ENABLE_UNIQUECLEAN     (1 << 14)
 #define L2ACTLR_DISABLE_CLEAN_PUSH     (1 << 3)
 
+/*******************************************************************************
+ * L2 Extended Control register specific definitions.
+ ******************************************************************************/
+#define L2ECTLR_EL1                    S3_1_C11_C0_3   /* Instruction def. */
+
+#define L2ECTLR_RET_CTRL_SHIFT         0
+#define L2ECTLR_RET_CTRL_MASK          (0x7 << L2ECTLR_RET_CTRL_SHIFT)
+
 #endif /* __CORTEX_A53_H__ */

diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h
index 6128b1694e17ddabc4cc181695f227b712cf5f76..c81259c8940c871a3eb92eb91af6c5f33c27605b 100644 (file)
--- a/include/lib/cpus/aarch64/cortex_a57.h
+++ b/include/lib/cpus/aarch64/cortex_a57.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -34,6 +34,15 @@
 /* Cortex-A57 midr for revision 0 */
 #define CORTEX_A57_MIDR 0x410FD070
 
+/* Retention timer tick definitions */
+#define RETENTION_ENTRY_TICKS_2                0x1
+#define RETENTION_ENTRY_TICKS_8                0x2
+#define RETENTION_ENTRY_TICKS_32       0x3
+#define RETENTION_ENTRY_TICKS_64       0x4
+#define RETENTION_ENTRY_TICKS_128      0x5
+#define RETENTION_ENTRY_TICKS_256      0x6
+#define RETENTION_ENTRY_TICKS_512      0x7
+
 /*******************************************************************************
  * CPU Extended Control register specific definitions.
  ******************************************************************************/
@@ -44,6 +53,9 @@
 #define CPUECTLR_L2_IPFTCH_DIST_MASK   (0x3 << 35)
 #define CPUECTLR_L2_DPFTCH_DIST_MASK   (0x3 << 32)
 
+#define CPUECTLR_CPU_RET_CTRL_SHIFT    0
+#define CPUECTLR_CPU_RET_CTRL_MASK     (0x7 << CPUECTLR_CPU_RET_CTRL_SHIFT)
+
 /*******************************************************************************
  * CPU Auxiliary Control register specific definitions.
  ******************************************************************************/
@@ -63,4 +75,12 @@
 #define L2_DATA_RAM_LATENCY_3_CYCLES   0x2
 #define L2_TAG_RAM_LATENCY_3_CYCLES    0x2
 
+/*******************************************************************************
+ * L2 Extended Control register specific definitions.
+ ******************************************************************************/
+#define L2ECTLR_EL1                    S3_1_C11_C0_3   /* Instruction def. */
+
+#define L2ECTLR_RET_CTRL_SHIFT         0
+#define L2ECTLR_RET_CTRL_MASK          (0x7 << L2ECTLR_RET_CTRL_SHIFT)
+
 #endif /* __CORTEX_A57_H__ */