+++ /dev/null
-if ADM5120
-
-menu "ADM5120 Board selection"
-
-config ADM5120_MACH_CAS_771
- bool "Cellvision CAS-771/771W support"
- depends on CPU_LITTLE_ENDIAN
- select ADM5120_SOC_BGA
- select ADM5120_OEM_CELLVISION
- default y
-
-config ADM5120_MACH_NFS_101
- bool "Cellvision NFS-101U/101WU support"
- depends on CPU_LITTLE_ENDIAN
- select ADM5120_SOC_BGA
- select ADM5120_OEM_CELLVISION
- default y
-
-config ADM5120_MACH_NP27G
- bool "Compex NP27G support"
- depends on CPU_LITTLE_ENDIAN
- select ADM5120_SOC_BGA
- select ADM5120_OEM_COMPEX
- default y
-
-config ADM5120_MACH_NP28G
- bool "Compex NP28G support"
- depends on CPU_LITTLE_ENDIAN
- select ADM5120_SOC_BGA
- select ADM5120_OEM_COMPEX
- default y
-
-config ADM5120_MACH_WP54
- bool "Compex WP54 family support"
- depends on CPU_LITTLE_ENDIAN
- select ADM5120_SOC_BGA
- select ADM5120_OEM_COMPEX
- default y
-
-config ADM5120_MACH_BR_6104K
- bool "Edimax BR-6104K support"
- depends on CPU_LITTLE_ENDIAN
- select ADM5120_OEM_EDIMAX
- default y
-
-config ADM5120_MACH_BR_6104KP
- bool "Edimax BR-6104KP support"
- depends on CPU_LITTLE_ENDIAN
- select ADM5120_OEM_EDIMAX
- default y
-
-config ADM5120_MACH_BR_61X4WG
- bool "Edimax BR-6104WG/6114WG support"
- depends on CPU_LITTLE_ENDIAN
- select ADM5120_SOC_BGA
- select ADM5120_OEM_EDIMAX
- default y
-
-config ADM5120_MACH_EASY5120_RT
- bool "Infineon EASY 5120-RT Reference Board support"
- depends on CPU_LITTLE_ENDIAN
- select ADM5120_SOC_BGA
- select ADM5120_OEM_INFINEON
- default y
-
-config ADM5120_MACH_EASY5120_WVOIP
- bool "Infineon EASY 5120-WVoIP Reference Board support"
- depends on CPU_LITTLE_ENDIAN
- select ADM5120_SOC_BGA
- select ADM5120_OEM_INFINEON
- default y
-
-config ADM5120_MACH_EASY5120P_ATA
- bool "Infineon EASY 5120P-ATA Reference Board support"
- depends on CPU_LITTLE_ENDIAN
- select ADM5120_OEM_INFINEON
- default y
-
-config ADM5120_MACH_EASY83000
- bool "Infineon EASY 83000 Reference Board support"
- depends on CPU_LITTLE_ENDIAN
- select ADM5120_OEM_INFINEON
- default y
-
-config ADM5120_MACH_RB_11X
- bool "MikroTik RouterBOARD 111/112 support"
- depends on CPU_LITTLE_ENDIAN
- select ADM5120_SOC_BGA
- select ADM5120_OEM_MIKROTIK
- default y
-
-config ADM5120_MACH_RB_133
- bool "MikroTik RouterBOARD 133 support"
- depends on CPU_LITTLE_ENDIAN
- select ADM5120_SOC_BGA
- select ADM5120_OEM_MIKROTIK
- default y
-
-config ADM5120_MACH_RB_133C
- bool "MikroTik RouterBOARD 133C support"
- depends on CPU_LITTLE_ENDIAN
- select ADM5120_SOC_BGA
- select ADM5120_OEM_MIKROTIK
- default y
-
-config ADM5120_MACH_RB_150
- bool "MikroTik RouterBOARD 150 support"
- depends on CPU_LITTLE_ENDIAN
- select ADM5120_OEM_MIKROTIK
- default y
-
-config ADM5120_MACH_RB_153
- bool "MikroTik RouterBOARD 153 support"
- depends on CPU_LITTLE_ENDIAN
- select ADM5120_SOC_BGA
- select ADM5120_OEM_MIKROTIK
- default y
-
-config ADM5120_MACH_RB_192
- bool "MikroTik RouterBOARD 192 support"
- depends on CPU_LITTLE_ENDIAN
- select ADM5120_SOC_BGA
- select ADM5120_OEM_MIKROTIK
- default y
-
-config ADM5120_MACH_PMUGW
- bool "Motorola Powerline MU Gateway"
- depends on CPU_LITTLE_ENDIAN
- select ADM5120_SOC_BGA
- select ADM5120_OEM_MOTOROLA
- default y
-
-config ADM5120_MACH_P_334WT
- bool "ZyXEL Prestige 334WT"
- depends on CPU_BIG_ENDIAN
- select ADM5120_SOC_BGA
- select ADM5120_OEM_ZYXEL
- default y
-
-config ADM5120_MACH_P_335
- bool "ZyXEL Prestige 335/335WT"
- depends on CPU_BIG_ENDIAN
- select ADM5120_SOC_BGA
- select ADM5120_OEM_ZYXEL
- default y
-
-endmenu
-
-config ADM5120_SOC_BGA
- select HW_HAS_PCI
- def_bool n
-
-config ADM5120_OEM_CELLVISION
- def_bool n
-
-config ADM5120_OEM_COMPEX
- def_bool n
-
-config ADM5120_OEM_EDIMAX
- def_bool n
-
-config ADM5120_OEM_INFINEON
- def_bool n
-
-config ADM5120_OEM_MIKROTIK
- def_bool n
-
-config ADM5120_OEM_MOTOROLA
- def_bool n
-
-config ADM5120_OEM_ZYXEL
- def_bool n
-
-config ARM_AMBA
- def_bool y
-
-endif
+++ /dev/null
-obj-y += cellvision.o
-
-obj-$(CONFIG_ADM5120_MACH_CAS_771) += cas-771.o
-obj-$(CONFIG_ADM5120_MACH_NFS_101) += nfs-101.o
+++ /dev/null
-/*
- * Cellvision/SparkLAN CAS-771/771W support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "cellvision.h"
-
-static struct adm5120_pci_irq cas771_pci_irqs[] __initdata = {
- PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI0),
- PCIIRQ(3, 0, 1, ADM5120_IRQ_PCI1),
- PCIIRQ(3, 2, 3, ADM5120_IRQ_PCI2)
-};
-
-static struct gpio_led cas771_gpio_leds[] __initdata = {
- GPIO_LED_STD(ADM5120_GPIO_PIN0, "cam_flash", NULL),
- /* GPIO PIN3 is the reset */
- GPIO_LED_STD(ADM5120_GPIO_PIN6, "access", NULL),
- GPIO_LED_STD(ADM5120_GPIO_P0L1, "status", NULL),
- GPIO_LED_STD(ADM5120_GPIO_P0L2, "diag", NULL),
-};
-
-static void __init cas771_setup(void)
-{
- cas7xx_setup();
- adm5120_add_device_gpio_leds(ARRAY_SIZE(cas771_gpio_leds),
- cas771_gpio_leds);
- adm5120_pci_set_irq_map(ARRAY_SIZE(cas771_pci_irqs), cas771_pci_irqs);
-}
-
-ADM5120_BOARD(MACH_ADM5120_CAS771, "Cellvision CAS-771/771W", cas771_setup);
+++ /dev/null
-/*
- * Cellvision/SparkLAN boards
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "cellvision.h"
-
-#include <prom/admboot.h>
-
-#define CELLVISION_GPIO_FLASH_A20 ADM5120_GPIO_PIN5
-#define CELLVISION_GPIO_DEV_MASK (1 << CELLVISION_GPIO_FLASH_A20)
-
-#define CELLVISION_CONFIG_OFFSET 0x8000
-#define CELLVISION_CONFIG_SIZE 0x1000
-
-#ifdef CONFIG_MTD_PARTITIONS
-static struct mtd_partition cas6xx_partitions[] = {
- {
- .name = "admboot",
- .offset = 0,
- .size = 32*1024,
- .mask_flags = MTD_WRITEABLE,
- } , {
- .name = "config",
- .offset = MTDPART_OFS_APPEND,
- .size = 32*1024,
- } , {
- .name = "nvfs1",
- .offset = MTDPART_OFS_APPEND,
- .size = 64*1024,
- } , {
- .name = "nvfs2",
- .offset = MTDPART_OFS_APPEND,
- .size = 64*1024,
- } , {
- .name = "firmware",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- }
-};
-
-static struct mtd_partition cas7xx_partitions[] = {
- {
- .name = "admboot",
- .offset = 0,
- .size = 32*1024,
- .mask_flags = MTD_WRITEABLE,
- } , {
- .name = "config",
- .offset = MTDPART_OFS_APPEND,
- .size = 32*1024,
- } , {
- .name = "nvfs",
- .offset = MTDPART_OFS_APPEND,
- .size = 128*1024,
- } , {
- .name = "firmware",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- }
-};
-#endif /* CONFIG_MTD_PARTITIONS */
-
-static void switch_bank_gpio5(unsigned bank)
-{
- switch (bank) {
- case 0:
- gpio_set_value(CELLVISION_GPIO_FLASH_A20, 0);
- break;
- case 1:
- gpio_set_value(CELLVISION_GPIO_FLASH_A20, 1);
- break;
- }
-}
-
-static void __init cellvision_flash_setup(void)
-{
- /* setup flash A20 line */
- gpio_request(CELLVISION_GPIO_FLASH_A20, NULL);
- gpio_direction_output(CELLVISION_GPIO_FLASH_A20, 0);
-
- adm5120_flash0_data.switch_bank = switch_bank_gpio5;
- adm5120_add_device_flash(0);
-}
-
-void __init cellvision_mac_setup(void)
-{
- u8 mac_base[6];
- int err;
-
- err = admboot_get_mac_base(CELLVISION_CONFIG_OFFSET,
- CELLVISION_CONFIG_SIZE, mac_base);
-
- if ((err) || !is_valid_ether_addr(mac_base))
- random_ether_addr(mac_base);
-
- adm5120_setup_eth_macs(mac_base);
-}
-
-void __init cas6xx_flash_setup(void)
-{
-#ifdef CONFIG_MTD_PARTITIONS
- adm5120_flash0_data.nr_parts = ARRAY_SIZE(cas6xx_partitions);
- adm5120_flash0_data.parts = cas6xx_partitions;
-#endif /* CONFIG_MTD_PARTITIONS */
-
- cellvision_flash_setup();
-}
-
-void __init cas7xx_flash_setup(void)
-{
-#ifdef CONFIG_MTD_PARTITIONS
- adm5120_flash0_data.nr_parts = ARRAY_SIZE(cas7xx_partitions);
- adm5120_flash0_data.parts = cas7xx_partitions;
-#endif /* CONFIG_MTD_PARTITIONS */
-
- cellvision_flash_setup();
-}
-
-#if 0
-void __init cas6xx_setup(void)
-{
- cas6xx_flash_setup();
- adm5120_add_device_uart(0);
- adm5120_add_device_uart(1);
- adm5120_add_device_switch(1, NULL);
-}
-
-ADM5120_BOARD(MACH_ADM5120_CAS630, "Cellvision CAS-630/630W", cas6xx_setup);
-ADM5120_BOARD(MACH_ADM5120_CAS670, "Cellvision CAS-670/670W", cas6xx_setup);
-#endif
-
-void __init cas7xx_setup(void)
-{
- cas7xx_flash_setup();
- cellvision_mac_setup();
- adm5120_add_device_uart(0);
- adm5120_add_device_uart(1);
- adm5120_add_device_switch(1, NULL);
-}
-
-#if 0
-ADM5120_BOARD(MACH_ADM5120_CAS700, "Cellvision CAS-700/700W", cas7xx_setup);
-ADM5120_BOARD(MACH_ADM5120_CAS790, "Cellvision CAS-790", cas7xx_setup);
-ADM5120_BOARD(MACH_ADM5120_CAS861, "Cellvision CAS-861/861W", cas7xx_setup);
-#endif
+++ /dev/null
-/*
- * Cellvision/SparkLAN boards
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <linux/etherdevice.h>
-
-#include <asm/bootinfo.h>
-
-#include <asm/mach-adm5120/adm5120_info.h>
-#include <asm/mach-adm5120/adm5120_board.h>
-#include <asm/mach-adm5120/adm5120_platform.h>
-
-extern void cellvision_mac_setup(void) __init;
-
-extern void cas6xx_flash_setup(void) __init;
-extern void cas7xx_flash_setup(void) __init;
-extern void cas6xx_setup(void) __init;
-extern void cas7xx_setup(void) __init;
+++ /dev/null
-/*
- * Cellvision/SparkLAN NFS-101U/WU support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "cellvision.h"
-
-static u8 nfs101_vlans[6] __initdata = { /* TODO: not tested */
- 0x41, 0x42, 0x44, 0x48, 0x50, 0x00
-};
-
-static void __init nfs101_setup(void)
-{
- cas6xx_flash_setup();
- cellvision_mac_setup();
-
- adm5120_add_device_uart(0);
- adm5120_add_device_uart(1);
- adm5120_add_device_switch(5, nfs101_vlans);
-}
-
-ADM5120_BOARD(MACH_ADM5120_NFS101U, "Cellvision NFS-101U/101WU", nfs101_setup);
+++ /dev/null
-#
-# Makefile for the Infineon/ADMtek ADM5120 SoC specific parts of the kernel
-#
-
-obj-y := adm5120.o setup.o prom.o irq.o memory.o board.o clock.o \
- gpio.o platform.o
+++ /dev/null
-/*
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-
-#include <asm/bootinfo.h>
-#include <asm/addrspace.h>
-
-#include <asm/mach-adm5120/adm5120_info.h>
-#include <asm/mach-adm5120/adm5120_defs.h>
-#include <asm/mach-adm5120/adm5120_switch.h>
-
-unsigned int adm5120_product_code;
-unsigned int adm5120_revision;
-unsigned int adm5120_package;
-unsigned int adm5120_nand_boot;
-unsigned long adm5120_speed;
-
-/*
- * CPU settings detection
- */
-#define CODE_GET_PC(c) ((c) & CODE_PC_MASK)
-#define CODE_GET_REV(c) (((c) >> CODE_REV_SHIFT) & CODE_REV_MASK)
-#define CODE_GET_PK(c) (((c) >> CODE_PK_SHIFT) & CODE_PK_MASK)
-#define CODE_GET_CLKS(c) (((c) >> CODE_CLKS_SHIFT) & CODE_CLKS_MASK)
-#define CODE_GET_NAB(c) (((c) & CODE_NAB) != 0)
-
-void adm5120_ndelay(u32 ns)
-{
- u32 t;
-
- SW_WRITE_REG(SWITCH_REG_TIMER, TIMER_PERIOD_DEFAULT);
- SW_WRITE_REG(SWITCH_REG_TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM));
-
- t = (ns+640) / 640;
- t &= TIMER_PERIOD_MASK;
- SW_WRITE_REG(SWITCH_REG_TIMER, t | TIMER_TE);
-
- /* wait until the timer expires */
- do {
- t = SW_READ_REG(SWITCH_REG_TIMER_INT);
- } while ((t & TIMER_INT_TOS) == 0);
-
- /* leave the timer disabled */
- SW_WRITE_REG(SWITCH_REG_TIMER, TIMER_PERIOD_DEFAULT);
- SW_WRITE_REG(SWITCH_REG_TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM));
-}
-
-void __init adm5120_soc_init(void)
-{
- u32 code;
- u32 clks;
-
- code = SW_READ_REG(SWITCH_REG_CODE);
-
- adm5120_product_code = CODE_GET_PC(code);
- adm5120_revision = CODE_GET_REV(code);
- adm5120_package = (CODE_GET_PK(code) == CODE_PK_BGA) ?
- ADM5120_PACKAGE_BGA : ADM5120_PACKAGE_PQFP;
- adm5120_nand_boot = CODE_GET_NAB(code);
-
- clks = CODE_GET_CLKS(code);
- adm5120_speed = ADM5120_SPEED_175;
- if (clks & 1)
- adm5120_speed += 25000000;
- if (clks & 2)
- adm5120_speed += 50000000;
-}
+++ /dev/null
-/*
- * ADM5120 generic board code
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/string.h>
-#include <linux/device.h>
-#include <linux/platform_device.h>
-
-#include <asm/bootinfo.h>
-
-#include <asm/mach-adm5120/adm5120_info.h>
-#include <asm/mach-adm5120/adm5120_defs.h>
-#include <asm/mach-adm5120/adm5120_board.h>
-#include <asm/mach-adm5120/adm5120_platform.h>
-
-#define PFX "ADM5120: "
-
-static struct list_head adm5120_boards __initdata =
- LIST_HEAD_INIT(adm5120_boards);
-
-static char adm5120_board_name[ADM5120_BOARD_NAMELEN] = "Unknown board";
-
-const char *get_system_type(void)
-{
- return adm5120_board_name;
-}
-
-static struct adm5120_board * __init adm5120_board_find(unsigned long machtype)
-{
- struct list_head *this;
-
- list_for_each(this, &adm5120_boards) {
- struct adm5120_board *board;
-
- board = list_entry(this, struct adm5120_board, list);
- if (board->mach_type == machtype)
- return board;
- }
-
- return NULL;
-}
-
-static int __init adm5120_board_setup(void)
-{
- struct adm5120_board *board;
-
- board = adm5120_board_find(mips_machtype);
- if (board == NULL)
- panic(PFX "no board registered for machtype %lu\n",
- mips_machtype);
-
- if (board->name[0])
- strlcpy(adm5120_board_name, board->name, ADM5120_BOARD_NAMELEN);
-
- printk(KERN_INFO PFX "board is '%s'\n", adm5120_board_name);
-
- adm5120_gpio_init();
-
- if (board->board_setup)
- board->board_setup();
-
- return 0;
-}
-arch_initcall(adm5120_board_setup);
-
-void __init adm5120_board_register(struct adm5120_board *board)
-{
- list_add_tail(&board->list, &adm5120_boards);
-}
-
-static void __init adm5120_generic_board_setup(void)
-{
- adm5120_add_device_uart(0);
- adm5120_add_device_uart(1);
-
- adm5120_add_device_flash(0);
- adm5120_add_device_switch(6, NULL);
-}
-
-ADM5120_BOARD(MACH_ADM5120_GENERIC, "Generic ADM5120 board",
- adm5120_generic_board_setup);
+++ /dev/null
-/*
- * ADM5120 minimal CLK API implementation
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This file was based on the CLK API implementation in:
- * arch/mips/tx4938/toshiba_rbtx4938/setup.c
- * Copyright (C) 2000-2001 Toshiba Corporation
- * 2003-2005 (c) MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <linux/module.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-
-#include <asm/mach-adm5120/adm5120_defs.h>
-
-struct clk {
- unsigned long rate;
-};
-
-static struct clk uart_clk = {
- .rate = ADM5120_UART_CLOCK
-};
-
-struct clk *clk_get(struct device *dev, const char *id)
-{
- if (!strcmp(id, "UARTCLK"))
- return &uart_clk;
-
- return ERR_PTR(-ENOENT);
-}
-EXPORT_SYMBOL(clk_get);
-
-int clk_enable(struct clk *clk)
-{
- return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_disable);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
- return clk->rate;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-void clk_put(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_put);
+++ /dev/null
-/*
- * ADM5120 generic GPIO API support via GPIOLIB
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/autoconf.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-
-#include <asm/addrspace.h>
-
-#include <asm/mach-adm5120/adm5120_defs.h>
-#include <asm/mach-adm5120/adm5120_info.h>
-#include <asm/mach-adm5120/adm5120_switch.h>
-
-#define GPIO_REG(r) (void __iomem *)(KSEG1ADDR(ADM5120_SWITCH_BASE) + r)
-
-struct gpio1_desc {
- void __iomem *reg; /* register address */
- u8 iv_shift; /* shift amount for input bit */
- u8 mode_shift; /* shift amount for mode bits */
-};
-
-#define GPIO1_DESC(p, l) { \
- .reg = GPIO_REG(SWITCH_REG_PORT0_LED + ((p) * 4)), \
- .iv_shift = LED0_IV_SHIFT + (l), \
- .mode_shift = (l) * 4 \
- }
-
-static struct gpio1_desc gpio1_table[15] = {
- GPIO1_DESC(0, 0), GPIO1_DESC(0, 1), GPIO1_DESC(0, 2),
- GPIO1_DESC(1, 0), GPIO1_DESC(1, 1), GPIO1_DESC(1, 2),
- GPIO1_DESC(2, 0), GPIO1_DESC(2, 1), GPIO1_DESC(2, 2),
- GPIO1_DESC(3, 0), GPIO1_DESC(3, 1), GPIO1_DESC(3, 2),
- GPIO1_DESC(4, 0), GPIO1_DESC(4, 1), GPIO1_DESC(4, 2)
-};
-
-static u32 gpio_conf2;
-
-int adm5120_gpio_to_irq(unsigned gpio)
-{
- int ret;
-
- switch (gpio) {
- case ADM5120_GPIO_PIN2:
- ret = ADM5120_IRQ_GPIO2;
- break;
- case ADM5120_GPIO_PIN4:
- ret = ADM5120_IRQ_GPIO4;
- break;
- default:
- ret = -EINVAL;
- break;
- }
-
- return ret;
-}
-EXPORT_SYMBOL(adm5120_gpio_to_irq);
-
-int adm5120_irq_to_gpio(unsigned irq)
-{
- int ret;
-
- switch (irq) {
- case ADM5120_IRQ_GPIO2:
- ret = ADM5120_GPIO_PIN2;
- break;
- case ADM5120_IRQ_GPIO4:
- ret = ADM5120_GPIO_PIN4;
- break;
- default:
- ret = -EINVAL;
- break;
- }
-
- return ret;
-}
-EXPORT_SYMBOL(adm5120_irq_to_gpio);
-
-/*
- * Helpers for GPIO lines in GPIO_CONF0 register
- */
-#define PIN_IM(p) ((1 << GPIO_CONF0_IM_SHIFT) << p)
-#define PIN_IV(p) ((1 << GPIO_CONF0_IV_SHIFT) << p)
-#define PIN_OE(p) ((1 << GPIO_CONF0_OE_SHIFT) << p)
-#define PIN_OV(p) ((1 << GPIO_CONF0_OV_SHIFT) << p)
-
-int __adm5120_gpio0_get_value(unsigned offset)
-{
- void __iomem **reg;
- u32 t;
-
- reg = GPIO_REG(SWITCH_REG_GPIO_CONF0);
-
- t = __raw_readl(reg);
- if ((t & PIN_IM(offset)) != 0)
- t &= PIN_IV(offset);
- else
- t &= PIN_OV(offset);
-
- return (t) ? 1 : 0;
-}
-EXPORT_SYMBOL(__adm5120_gpio0_get_value);
-
-void __adm5120_gpio0_set_value(unsigned offset, int value)
-{
- void __iomem **reg;
- u32 t;
-
- reg = GPIO_REG(SWITCH_REG_GPIO_CONF0);
-
- t = __raw_readl(reg);
- if (value == 0)
- t &= ~(PIN_OV(offset));
- else
- t |= PIN_OV(offset);
-
- __raw_writel(t, reg);
-}
-EXPORT_SYMBOL(__adm5120_gpio0_set_value);
-
-static int adm5120_gpio0_get_value(struct gpio_chip *chip, unsigned offset)
-{
- return __adm5120_gpio0_get_value(offset);
-}
-
-static void adm5120_gpio0_set_value(struct gpio_chip *chip,
- unsigned offset, int value)
-{
- __adm5120_gpio0_set_value(offset, value);
-}
-
-static int adm5120_gpio0_direction_input(struct gpio_chip *chip,
- unsigned offset)
-{
- void __iomem **reg;
- u32 t;
-
- reg = GPIO_REG(SWITCH_REG_GPIO_CONF0);
-
- t = __raw_readl(reg);
- t &= ~(PIN_OE(offset));
- t |= PIN_IM(offset);
- __raw_writel(t, reg);
-
- return 0;
-}
-
-static int adm5120_gpio0_direction_output(struct gpio_chip *chip,
- unsigned offset, int value)
-{
- void __iomem **reg;
- u32 t;
-
- reg = GPIO_REG(SWITCH_REG_GPIO_CONF0);
-
- t = __raw_readl(reg);
- t &= ~(PIN_IM(offset) | PIN_OV(offset));
- t |= PIN_OE(offset);
-
- if (value)
- t |= PIN_OV(offset);
-
- __raw_writel(t, reg);
-
- return 0;
-}
-
-static struct gpio_chip adm5120_gpio0_chip = {
- .label = "adm5120 gpio0",
- .get = adm5120_gpio0_get_value,
- .set = adm5120_gpio0_set_value,
- .direction_input = adm5120_gpio0_direction_input,
- .direction_output = adm5120_gpio0_direction_output,
- .base = ADM5120_GPIO_PIN0,
- .ngpio = ADM5120_GPIO_PIN7 - ADM5120_GPIO_PIN0 + 1,
-};
-
-int __adm5120_gpio1_get_value(unsigned offset)
-{
- void __iomem **reg;
- u32 t, m;
-
- reg = gpio1_table[offset].reg;
-
- t = __raw_readl(reg);
- m = (t >> gpio1_table[offset].mode_shift) & LED_MODE_MASK;
- if (m == LED_MODE_INPUT)
- return (t >> gpio1_table[offset].iv_shift) & 1;
-
- if (m == LED_MODE_OUT_LOW)
- return 0;
-
- return 1;
-}
-EXPORT_SYMBOL(__adm5120_gpio1_get_value);
-
-void __adm5120_gpio1_set_value(unsigned offset, int value)
-{
- void __iomem **reg;
- u32 t, s;
-
- reg = gpio1_table[offset].reg;
- s = gpio1_table[offset].mode_shift;
-
- t = __raw_readl(reg);
- t &= ~(LED_MODE_MASK << s);
-
- switch (value) {
- case ADM5120_GPIO_LOW:
- t |= (LED_MODE_OUT_LOW << s);
- break;
- case ADM5120_GPIO_FLASH:
- case ADM5120_GPIO_LINK:
- case ADM5120_GPIO_SPEED:
- case ADM5120_GPIO_DUPLEX:
- case ADM5120_GPIO_ACT:
- case ADM5120_GPIO_COLL:
- case ADM5120_GPIO_LINK_ACT:
- case ADM5120_GPIO_DUPLEX_COLL:
- case ADM5120_GPIO_10M_ACT:
- case ADM5120_GPIO_100M_ACT:
- t |= ((value & LED_MODE_MASK) << s);
- break;
- default:
- t |= (LED_MODE_OUT_HIGH << s);
- break;
- }
-
- __raw_writel(t, reg);
-}
-EXPORT_SYMBOL(__adm5120_gpio1_set_value);
-
-static int adm5120_gpio1_get_value(struct gpio_chip *chip, unsigned offset)
-{
- return __adm5120_gpio1_get_value(offset);
-}
-
-static void adm5120_gpio1_set_value(struct gpio_chip *chip,
- unsigned offset, int value)
-{
- __adm5120_gpio1_set_value(offset, value);
-}
-
-static int adm5120_gpio1_direction_input(struct gpio_chip *chip,
- unsigned offset)
-{
- void __iomem **reg;
- u32 t;
-
- reg = gpio1_table[offset].reg;
- t = __raw_readl(reg);
- t &= ~(LED_MODE_MASK << gpio1_table[offset].mode_shift);
- __raw_writel(t, reg);
-
- return 0;
-}
-
-static int adm5120_gpio1_direction_output(struct gpio_chip *chip,
- unsigned offset, int value)
-{
- __adm5120_gpio1_set_value(offset, value);
- return 0;
-}
-
-static struct gpio_chip adm5120_gpio1_chip = {
- .label = "adm5120 gpio1",
- .get = adm5120_gpio1_get_value,
- .set = adm5120_gpio1_set_value,
- .direction_input = adm5120_gpio1_direction_input,
- .direction_output = adm5120_gpio1_direction_output,
- .base = ADM5120_GPIO_P0L0,
- .ngpio = ADM5120_GPIO_P4L2 - ADM5120_GPIO_P0L0 + 1,
-};
-
-void __init adm5120_gpio_csx0_enable(void)
-{
- gpio_conf2 |= GPIO_CONF2_CSX0;
- SW_WRITE_REG(SWITCH_REG_GPIO_CONF2, gpio_conf2);
-
- gpio_request(ADM5120_GPIO_PIN1, "CSX0");
-}
-
-void __init adm5120_gpio_csx1_enable(void)
-{
- gpio_conf2 |= GPIO_CONF2_CSX1;
- SW_WRITE_REG(SWITCH_REG_GPIO_CONF2, gpio_conf2);
-
- gpio_request(ADM5120_GPIO_PIN3, "CSX1");
-}
-
-void __init adm5120_gpio_ew_enable(void)
-{
- gpio_conf2 |= GPIO_CONF2_EW;
- SW_WRITE_REG(SWITCH_REG_GPIO_CONF2, gpio_conf2);
-
- gpio_request(ADM5120_GPIO_PIN0, "EW");
-}
-
-void __init adm5120_gpio_init(void)
-{
- int err;
-
- SW_WRITE_REG(SWITCH_REG_GPIO_CONF2, gpio_conf2);
-
- if (adm5120_package_pqfp()) {
- gpiochip_reserve(ADM5120_GPIO_PIN4, 4);
- adm5120_gpio0_chip.ngpio = 4;
- }
-
- err = gpiochip_add(&adm5120_gpio0_chip);
- if (err)
- panic("cannot add ADM5120 GPIO0 chip, error=%d", err);
-
- err = gpiochip_add(&adm5120_gpio1_chip);
- if (err)
- panic("cannot add ADM5120 GPIO1 chip, error=%d", err);
-
-}
+++ /dev/null
-/*
- * ADM5120 specific interrupt handlers
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/version.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/io.h>
-
-#include <asm/irq_cpu.h>
-#include <asm/mipsregs.h>
-#include <asm/bitops.h>
-
-#include <asm/mach-adm5120/adm5120_defs.h>
-
-static void adm5120_intc_irq_unmask(unsigned int irq);
-static void adm5120_intc_irq_mask(unsigned int irq);
-static int adm5120_intc_irq_set_type(unsigned int irq, unsigned int flow_type);
-
-static inline void intc_write_reg(unsigned int reg, u32 val)
-{
- void __iomem *base = (void __iomem *)KSEG1ADDR(ADM5120_INTC_BASE);
-
- __raw_writel(val, base + reg);
-}
-
-static inline u32 intc_read_reg(unsigned int reg)
-{
- void __iomem *base = (void __iomem *)KSEG1ADDR(ADM5120_INTC_BASE);
-
- return __raw_readl(base + reg);
-}
-
-static struct irq_chip adm5120_intc_irq_chip = {
- .name = "INTC",
- .unmask = adm5120_intc_irq_unmask,
- .mask = adm5120_intc_irq_mask,
- .mask_ack = adm5120_intc_irq_mask,
- .set_type = adm5120_intc_irq_set_type
-};
-
-static struct irqaction adm5120_intc_irq_action = {
- .handler = no_action,
- .name = "cascade [INTC]"
-};
-
-static void adm5120_intc_irq_unmask(unsigned int irq)
-{
- irq -= ADM5120_INTC_IRQ_BASE;
- intc_write_reg(INTC_REG_IRQ_ENABLE, 1 << irq);
-}
-
-static void adm5120_intc_irq_mask(unsigned int irq)
-{
- irq -= ADM5120_INTC_IRQ_BASE;
- intc_write_reg(INTC_REG_IRQ_DISABLE, 1 << irq);
-}
-
-static int adm5120_intc_irq_set_type(unsigned int irq, unsigned int flow_type)
-{
- unsigned int sense;
- unsigned long mode;
- int err = 0;
-
- sense = flow_type & (IRQ_TYPE_SENSE_MASK);
- switch (sense) {
- case IRQ_TYPE_NONE:
- case IRQ_TYPE_LEVEL_HIGH:
- break;
- case IRQ_TYPE_LEVEL_LOW:
- switch (irq) {
- case ADM5120_IRQ_GPIO2:
- case ADM5120_IRQ_GPIO4:
- break;
- default:
- err = -EINVAL;
- break;
- }
- break;
- default:
- err = -EINVAL;
- break;
- }
-
- if (err)
- return err;
-
- switch (irq) {
- case ADM5120_IRQ_GPIO2:
- case ADM5120_IRQ_GPIO4:
- mode = intc_read_reg(INTC_REG_INT_MODE);
- if (sense == IRQ_TYPE_LEVEL_LOW)
- mode |= (1 << (irq - ADM5120_INTC_IRQ_BASE));
- else
- mode &= ~(1 << (irq - ADM5120_INTC_IRQ_BASE));
-
- intc_write_reg(INTC_REG_INT_MODE, mode);
- /* fallthrough */
- default:
- irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
- irq_desc[irq].status |= sense;
- break;
- }
-
- return 0;
-}
-
-static void adm5120_intc_irq_dispatch(void)
-{
- unsigned long status;
- int irq;
-
- status = intc_read_reg(INTC_REG_IRQ_STATUS) & INTC_INT_ALL;
- if (status) {
- irq = ADM5120_INTC_IRQ_BASE + fls(status) - 1;
- do_IRQ(irq);
- } else
- spurious_interrupt();
-}
-
-asmlinkage void plat_irq_dispatch(void)
-{
- unsigned long pending;
-
- pending = read_c0_status() & read_c0_cause() & ST0_IM;
-
- if (pending & STATUSF_IP7)
- do_IRQ(ADM5120_IRQ_COUNTER);
- else if (pending & STATUSF_IP2)
- adm5120_intc_irq_dispatch();
- else
- spurious_interrupt();
-}
-
-#define INTC_IRQ_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED)
-static void __init adm5120_intc_irq_init(void)
-{
- int i;
-
- /* disable all interrupts */
- intc_write_reg(INTC_REG_IRQ_DISABLE, INTC_INT_ALL);
-
- /* setup all interrupts to generate IRQ instead of FIQ */
- intc_write_reg(INTC_REG_INT_MODE, 0);
-
- /* set active level for all external interrupts to HIGH */
- intc_write_reg(INTC_REG_INT_LEVEL, 0);
-
- /* disable usage of the TEST_SOURCE register */
- intc_write_reg(INTC_REG_IRQ_SOURCE_SELECT, 0);
-
- for (i = ADM5120_INTC_IRQ_BASE;
- i <= ADM5120_INTC_IRQ_BASE + INTC_IRQ_LAST;
- i++) {
- irq_desc[i].status = INTC_IRQ_STATUS;
- set_irq_chip_and_handler(i, &adm5120_intc_irq_chip,
- handle_level_irq);
- }
-
- setup_irq(ADM5120_IRQ_INTC, &adm5120_intc_irq_action);
-}
-
-void __init arch_init_irq(void) {
- mips_cpu_irq_init();
- adm5120_intc_irq_init();
-}
+++ /dev/null
-/*
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/io.h>
-
-#include <asm/bootinfo.h>
-#include <asm/addrspace.h>
-
-#include <asm/mach-adm5120/adm5120_info.h>
-#include <asm/mach-adm5120/adm5120_defs.h>
-#include <asm/mach-adm5120/adm5120_switch.h>
-#include <asm/mach-adm5120/adm5120_mpmc.h>
-
-#ifdef DEBUG
-# define mem_dbg(f, a...) printk(KERN_INFO "mem_detect: " f, ## a)
-#else
-# define mem_dbg(f, a...)
-#endif
-
-unsigned long adm5120_memsize;
-
-#define MEM_READL(a) __raw_readl((void __iomem *)(a))
-#define MEM_WRITEL(a, v) __raw_writel((v), (void __iomem *)(a))
-
-static int __init mem_check_pattern(u8 *addr, unsigned long offs)
-{
- u32 *p1 = (u32 *)addr;
- u32 *p2 = (u32 *)(addr+offs);
- u32 t, u, v;
-
- /* save original value */
- t = MEM_READL(p1);
-
- u = MEM_READL(p2);
- if (t != u)
- return 0;
-
- v = 0x55555555;
- if (u == v)
- v = 0xAAAAAAAA;
-
- mem_dbg("write 0x%08X to 0x%08lX\n", v, (unsigned long)p1);
-
- MEM_WRITEL(p1, v);
- adm5120_ndelay(1000);
- u = MEM_READL(p2);
-
- mem_dbg("pattern at 0x%08lX is 0x%08X\n", (unsigned long)p2, u);
-
- /* restore original value */
- MEM_WRITEL(p1, t);
-
- return (v == u);
-}
-
-static void __init adm5120_detect_memsize(void)
-{
- u32 memctrl;
- u32 size, maxsize;
- u8 *p;
-
- memctrl = SW_READ_REG(SWITCH_REG_MEMCTRL);
- switch (memctrl & MEMCTRL_SDRS_MASK) {
- case MEMCTRL_SDRS_4M:
- maxsize = 4 << 20;
- break;
- case MEMCTRL_SDRS_8M:
- maxsize = 8 << 20;
- break;
- case MEMCTRL_SDRS_16M:
- maxsize = 16 << 20;
- break;
- default:
- maxsize = 64 << 20;
- break;
- }
-
- mem_dbg("checking for %uMB chip in 1st bank\n", maxsize >> 20);
-
- /* detect size of the 1st SDRAM bank */
- p = (u8 *)KSEG1ADDR(0);
- for (size = 2<<20; size <= (maxsize >> 1); size <<= 1) {
- if (mem_check_pattern(p, size)) {
- /* mirrored address */
- mem_dbg("mirrored data found at offset 0x%08X\n", size);
- break;
- }
- }
-
- mem_dbg("chip size in 1st bank is %uMB\n", size >> 20);
- adm5120_memsize = size;
-
- if (size != maxsize)
- /* 2nd bank is not supported */
- goto out;
-
- if ((memctrl & MEMCTRL_SDR1_ENABLE) == 0)
- /* 2nd bank is disabled */
- goto out;
-
- /*
- * some bootloaders enable 2nd bank, even if the 2nd SDRAM chip
- * are missing.
- */
- mem_dbg("check presence of 2nd bank\n");
-
- p = (u8 *)KSEG1ADDR(maxsize+size-4);
- if (mem_check_pattern(p, 0))
- adm5120_memsize += size;
-
- if (maxsize != size) {
- /* adjusting MECTRL register */
- memctrl &= ~(MEMCTRL_SDRS_MASK);
- switch (size>>20) {
- case 4:
- memctrl |= MEMCTRL_SDRS_4M;
- break;
- case 8:
- memctrl |= MEMCTRL_SDRS_8M;
- break;
- case 16:
- memctrl |= MEMCTRL_SDRS_16M;
- break;
- default:
- memctrl |= MEMCTRL_SDRS_64M;
- break;
- }
- SW_WRITE_REG(SWITCH_REG_MEMCTRL, memctrl);
- }
-
-out:
- mem_dbg("%dx%uMB memory found\n", (adm5120_memsize == size) ? 1 : 2 ,
- size>>20);
-}
-
-void __init adm5120_mem_init(void)
-{
- adm5120_detect_memsize();
- add_memory_region(0, adm5120_memsize, BOOT_MEM_RAM);
-}
+++ /dev/null
-/*
- * ADM5120 generic platform devices
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/device.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/irq.h>
-
-#include <asm/bootinfo.h>
-
-#include <asm/mach-adm5120/adm5120_defs.h>
-#include <asm/mach-adm5120/adm5120_info.h>
-#include <asm/mach-adm5120/adm5120_switch.h>
-#include <asm/mach-adm5120/adm5120_nand.h>
-#include <asm/mach-adm5120/adm5120_platform.h>
-
-#if 1
-/*
- * TODO:remove global adm5120_eth* variables when the switch driver will be
- * converted into a real platform driver
- */
-unsigned int adm5120_eth_num_ports = 6;
-EXPORT_SYMBOL_GPL(adm5120_eth_num_ports);
-
-unsigned char adm5120_eth_macs[6][6] = {
- {'\00', 'A', 'D', 'M', '\x51', '\x20' },
- {'\00', 'A', 'D', 'M', '\x51', '\x21' },
- {'\00', 'A', 'D', 'M', '\x51', '\x22' },
- {'\00', 'A', 'D', 'M', '\x51', '\x23' },
- {'\00', 'A', 'D', 'M', '\x51', '\x24' },
- {'\00', 'A', 'D', 'M', '\x51', '\x25' }
-};
-EXPORT_SYMBOL_GPL(adm5120_eth_macs);
-
-unsigned char adm5120_eth_vlans[6] = {
- 0x41, 0x42, 0x44, 0x48, 0x50, 0x60
-};
-EXPORT_SYMBOL_GPL(adm5120_eth_vlans);
-#endif
-
-void __init adm5120_setup_eth_macs(u8 *mac_base)
-{
- u32 t;
- int i, j;
-
- t = ((u32) mac_base[3] << 16) | ((u32) mac_base[4] << 8)
- | ((u32) mac_base[5]);
-
- for (i = 0; i < ARRAY_SIZE(adm5120_eth_macs); i++) {
- for (j = 0; j < 3; j++)
- adm5120_eth_macs[i][j] = mac_base[j];
-
- adm5120_eth_macs[i][3] = (t >> 16) & 0xff;
- adm5120_eth_macs[i][4] = (t >> 8) & 0xff;
- adm5120_eth_macs[i][5] = t & 0xff;
-
- t++;
- }
-}
-
-/*
- * Built-in ethernet switch
- */
-struct resource adm5120_switch_resources[] = {
- [0] = {
- .start = ADM5120_SWITCH_BASE,
- .end = ADM5120_SWITCH_BASE+ADM5120_SWITCH_SIZE-1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = ADM5120_IRQ_SWITCH,
- .end = ADM5120_IRQ_SWITCH,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct adm5120_switch_platform_data adm5120_switch_data;
-struct platform_device adm5120_switch_device = {
- .name = "adm5120-switch",
- .id = -1,
- .num_resources = ARRAY_SIZE(adm5120_switch_resources),
- .resource = adm5120_switch_resources,
- .dev.platform_data = &adm5120_switch_data,
-};
-
-void __init adm5120_add_device_switch(unsigned num_ports, u8 *vlan_map)
-{
- if (num_ports > 0)
- adm5120_eth_num_ports = num_ports;
-
- if (vlan_map)
- memcpy(adm5120_eth_vlans, vlan_map, sizeof(adm5120_eth_vlans));
-
- platform_device_register(&adm5120_switch_device);
-}
-
-/*
- * USB Host Controller
- */
-struct resource adm5120_hcd_resources[] = {
- [0] = {
- .start = ADM5120_USBC_BASE,
- .end = ADM5120_USBC_BASE+ADM5120_USBC_SIZE-1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = ADM5120_IRQ_USBC,
- .end = ADM5120_IRQ_USBC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static u64 adm5120_hcd_dma_mask = DMA_BIT_MASK(24);
-struct platform_device adm5120_hcd_device = {
- .name = "adm5120-hcd",
- .id = -1,
- .num_resources = ARRAY_SIZE(adm5120_hcd_resources),
- .resource = adm5120_hcd_resources,
- .dev = {
- .dma_mask = &adm5120_hcd_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(24),
- }
-};
-
-void __init adm5120_add_device_usb(void)
-{
- platform_device_register(&adm5120_hcd_device);
-}
-
-/*
- * NOR flash devices
- */
-struct adm5120_flash_platform_data adm5120_flash0_data;
-struct platform_device adm5120_flash0_device = {
- .name = "adm5120-flash",
- .id = 0,
- .dev.platform_data = &adm5120_flash0_data,
-};
-
-struct adm5120_flash_platform_data adm5120_flash1_data;
-struct platform_device adm5120_flash1_device = {
- .name = "adm5120-flash",
- .id = 1,
- .dev.platform_data = &adm5120_flash1_data,
-};
-
-void __init adm5120_add_device_flash(unsigned id)
-{
- struct platform_device *pdev;
-
- switch (id) {
- case 0:
- pdev = &adm5120_flash0_device;
- break;
- case 1:
- pdev = &adm5120_flash1_device;
- break;
- default:
- pdev = NULL;
- break;
- }
-
- if (pdev)
- platform_device_register(pdev);
-}
-
-/*
- * built-in UARTs
- */
-static void adm5120_uart_set_mctrl(struct amba_device *dev, void __iomem *base,
- unsigned int mctrl)
-{
-}
-
-struct amba_pl010_data adm5120_uart0_data = {
- .set_mctrl = adm5120_uart_set_mctrl
-};
-
-struct amba_device adm5120_uart0_device = {
- .dev = {
- .bus_id = "APB:UART0",
- .platform_data = &adm5120_uart0_data,
- },
- .res = {
- .start = ADM5120_UART0_BASE,
- .end = ADM5120_UART0_BASE + ADM5120_UART_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- .irq = { ADM5120_IRQ_UART0, -1 },
- .periphid = 0x0041010,
-};
-
-struct amba_pl010_data adm5120_uart1_data = {
- .set_mctrl = adm5120_uart_set_mctrl
-};
-
-struct amba_device adm5120_uart1_device = {
- .dev = {
- .bus_id = "APB:UART1",
- .platform_data = &adm5120_uart1_data,
- },
- .res = {
- .start = ADM5120_UART1_BASE,
- .end = ADM5120_UART1_BASE + ADM5120_UART_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- .irq = { ADM5120_IRQ_UART1, -1 },
- .periphid = 0x0041010,
-};
-
-void __init adm5120_add_device_uart(unsigned id)
-{
- struct amba_device *dev;
-
- switch (id) {
- case 0:
- dev = &adm5120_uart0_device;
- break;
- case 1:
- dev = &adm5120_uart1_device;
- break;
- default:
- dev = NULL;
- break;
- }
-
- if (dev)
- amba_device_register(dev, &iomem_resource);
-}
-
-/*
- * GPIO buttons
- */
-#define ADM5120_BUTTON_INTERVAL 20
-struct gpio_buttons_platform_data adm5120_gpio_buttons_data = {
- .poll_interval = ADM5120_BUTTON_INTERVAL,
-};
-
-struct platform_device adm5120_gpio_buttons_device = {
- .name = "gpio-buttons",
- .id = -1,
- .dev.platform_data = &adm5120_gpio_buttons_data,
-};
-
-void __init adm5120_add_device_gpio_buttons(unsigned nbuttons,
- struct gpio_button *buttons)
-{
- struct gpio_button *p;
-
- p = kmalloc(nbuttons * sizeof(*p), GFP_KERNEL);
- if (!p)
- return;
-
- memcpy(p, buttons, nbuttons * sizeof(*p));
- adm5120_gpio_buttons_data.nbuttons = nbuttons;
- adm5120_gpio_buttons_data.buttons = p;
-
- platform_device_register(&adm5120_gpio_buttons_device);
-}
-
-/*
- * GPIO LEDS
- */
-struct gpio_led_platform_data adm5120_gpio_leds_data;
-struct platform_device adm5120_gpio_leds_device = {
- .name = "leds-gpio",
- .id = -1,
- .dev.platform_data = &adm5120_gpio_leds_data,
-};
-
-void __init adm5120_add_device_gpio_leds(unsigned num_leds,
- struct gpio_led *leds)
-{
- struct gpio_led *p;
-
- p = kmalloc(num_leds * sizeof(*p), GFP_KERNEL);
- if (!p)
- return;
-
- memcpy(p, leds, num_leds * sizeof(*p));
- adm5120_gpio_leds_data.num_leds = num_leds;
- adm5120_gpio_leds_data.leds = p;
-
- platform_device_register(&adm5120_gpio_leds_device);
-}
-
-/*
- * GPIO device
- */
-static struct resource adm5120_gpio_resource[] __initdata = {
- {
- .start = 0x3fffff,
- },
-};
-
-void __init adm5120_add_device_gpio(u32 disable_mask)
-{
- if (adm5120_package_pqfp())
- disable_mask |= 0xf0;
-
- adm5120_gpio_resource[0].start &= ~disable_mask;
- platform_device_register_simple("GPIODEV", -1,
- adm5120_gpio_resource,
- ARRAY_SIZE(adm5120_gpio_resource));
-}
-
-/*
- * NAND flash
- */
-struct resource adm5120_nand_resources[] = {
- [0] = {
- .start = ADM5120_NAND_BASE,
- .end = ADM5120_NAND_BASE + ADM5120_NAND_SIZE-1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static int adm5120_nand_ready(struct mtd_info *mtd)
-{
- return ((adm5120_nand_get_status() & ADM5120_NAND_STATUS_READY) != 0);
-}
-
-static void adm5120_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
- unsigned int ctrl)
-{
- if (ctrl & NAND_CTRL_CHANGE) {
- adm5120_nand_set_cle(ctrl & NAND_CLE);
- adm5120_nand_set_ale(ctrl & NAND_ALE);
- adm5120_nand_set_cen(ctrl & NAND_NCE);
- }
-
- if (cmd != NAND_CMD_NONE)
- NAND_WRITE_REG(NAND_REG_DATA, cmd);
-}
-
-void __init adm5120_add_device_nand(struct platform_nand_data *pdata)
-{
- struct platform_device *pdev;
- int err;
-
- pdev = platform_device_alloc("gen_nand", -1);
- if (!pdev)
- goto err_out;
-
- err = platform_device_add_resources(pdev, adm5120_nand_resources,
- ARRAY_SIZE(adm5120_nand_resources));
- if (err)
- goto err_put;
-
- err = platform_device_add_data(pdev, pdata, sizeof(*pdata));
- if (err)
- goto err_put;
-
- pdata = pdev->dev.platform_data;
- pdata->ctrl.dev_ready = adm5120_nand_ready;
- pdata->ctrl.cmd_ctrl = adm5120_nand_cmd_ctrl;
-
- err = platform_device_add(pdev);
- if (err)
- goto err_put;
-
- return;
-
-err_put:
- platform_device_put(pdev);
-err_out:
- return;
-}
+++ /dev/null
-/*
- * ADM5120 specific prom routines
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <linux/mm.h>
-#include <linux/io.h>
-
-#include <asm/bootinfo.h>
-#include <asm/addrspace.h>
-
-#include <asm/mach-adm5120/adm5120_info.h>
-#include <asm/mach-adm5120/adm5120_defs.h>
-#include <asm/mach-adm5120/adm5120_uart.h>
-
-#include <prom/cfe.h>
-#include <prom/generic.h>
-#include <prom/routerboot.h>
-#include <prom/myloader.h>
-#include <prom/zynos.h>
-
-unsigned int adm5120_prom_type = ADM5120_PROM_GENERIC;
-
-struct board_desc {
- unsigned long mach_type;
- char *name;
-};
-
-#define DEFBOARD(n, mt) { .mach_type = (mt), .name = (n)}
-static struct board_desc common_boards[] __initdata = {
- /* Cellvision/SparkLAN boards */
- DEFBOARD("CAS-630", MACH_ADM5120_CAS630),
- DEFBOARD("CAS-670", MACH_ADM5120_CAS670),
- DEFBOARD("CAS-700", MACH_ADM5120_CAS700),
- DEFBOARD("CAS-771", MACH_ADM5120_CAS771),
- DEFBOARD("CAS-790", MACH_ADM5120_CAS790),
- DEFBOARD("CAS-861", MACH_ADM5120_CAS861),
- DEFBOARD("NFS-101U", MACH_ADM5120_NFS101U),
- /* Compex boards */
- DEFBOARD("WP54G-WRT", MACH_ADM5120_WP54G_WRT),
- /* Edimax boards */
- DEFBOARD("BR-6104K", MACH_ADM5120_BR6104K),
- DEFBOARD("BR-6104KP", MACH_ADM5120_BR6104KP),
- DEFBOARD("BR-6104WG", MACH_ADM5120_BR61X4WG),
- DEFBOARD("BR-6114WG", MACH_ADM5120_BR61X4WG),
- /* Infineon boards */
- DEFBOARD("EASY 5120P-ATA", MACH_ADM5120_EASY5120PATA),
- DEFBOARD("EASY 5120-RT", MACH_ADM5120_EASY5120RT),
- DEFBOARD("EASY 5120-WVoIP", MACH_ADM5120_EASY5120WVOIP),
- DEFBOARD("EASY 83000", MACH_ADM5120_EASY83000),
- /* Mikrotik RouterBOARDs */
- DEFBOARD("111", MACH_ADM5120_RB_11X),
- DEFBOARD("112", MACH_ADM5120_RB_11X),
- DEFBOARD("133", MACH_ADM5120_RB_133),
- DEFBOARD("133C", MACH_ADM5120_RB_133C),
- DEFBOARD("133C3", MACH_ADM5120_RB_133C),
- DEFBOARD("150", MACH_ADM5120_RB_153), /* it's intentional */
- DEFBOARD("153", MACH_ADM5120_RB_153),
- DEFBOARD("192", MACH_ADM5120_RB_192),
- DEFBOARD("miniROUTER", MACH_ADM5120_RB_150),
- /* Motorola boards */
- DEFBOARD("Powerline MU Gateway",MACH_ADM5120_PMUGW),
-};
-
-static unsigned long __init find_machtype_byname(char *name)
-{
- unsigned long ret;
- int i;
-
- ret = MACH_ADM5120_GENERIC;
- if (name == NULL)
- goto out;
-
- if (*name == '\0')
- goto out;
-
- for (i = 0; i < ARRAY_SIZE(common_boards); i++) {
- if (strcmp(common_boards[i].name, name) == 0) {
- ret = common_boards[i].mach_type;
- break;
- }
- }
-
-out:
- return ret;
-}
-
-static unsigned long __init detect_machtype_routerboot(void)
-{
- char *name;
-
- name = routerboot_get_boardname();
- return find_machtype_byname(name);
-}
-
-static unsigned long __init detect_machtype_generic(void)
-{
- char *name;
-
- name = generic_prom_getenv("board_name");
- return find_machtype_byname(name);
-}
-
-unsigned long __init detect_machtype_cfe(void)
-{
- char *name;
-
- name = cfe_getenv("BOARD_NAME");
- return find_machtype_byname(name);
-}
-
-static struct {
- unsigned long mach_type;
- u16 vendor_id;
- u16 board_id;
-} zynos_boards[] __initdata = {
-#define ZYNOS_BOARD(vi, bi, mt) \
- {.vendor_id = (vi), .board_id = (bi), .mach_type = (mt)}
-
-#define ZYXEL_BOARD(bi, mt) ZYNOS_BOARD(ZYNOS_VENDOR_ID_ZYXEL, bi, mt)
-#define DLINK_BOARD(bi, mt) ZYNOS_BOARD(ZYNOS_VENDOR_ID_DLINK, bi, mt)
-#define LUCENT_BOARD(bi, mt) ZYNOS_BOARD(ZYNOS_VENDOR_ID_LUCENT, bi, mt)
- ZYXEL_BOARD(ZYNOS_BOARD_HS100, MACH_ADM5120_HS100),
- ZYXEL_BOARD(ZYNOS_BOARD_P334U, MACH_ADM5120_P334U),
- ZYXEL_BOARD(ZYNOS_BOARD_P334W, MACH_ADM5120_P334W),
- ZYXEL_BOARD(ZYNOS_BOARD_P334WH, MACH_ADM5120_P334WH),
- ZYXEL_BOARD(ZYNOS_BOARD_P334WHD, MACH_ADM5120_P334WHD),
- ZYXEL_BOARD(ZYNOS_BOARD_P334WT, MACH_ADM5120_P334WT),
- ZYXEL_BOARD(ZYNOS_BOARD_P334WT_ALT, MACH_ADM5120_P334WT),
- ZYXEL_BOARD(ZYNOS_BOARD_P335, MACH_ADM5120_P335),
- ZYXEL_BOARD(ZYNOS_BOARD_P335PLUS, MACH_ADM5120_P335PLUS),
- ZYXEL_BOARD(ZYNOS_BOARD_P335U, MACH_ADM5120_P335U)
-};
-
-static unsigned long __init detect_machtype_bootbase(void)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(zynos_boards); i++) {
- if (zynos_boards[i].vendor_id == bootbase_info.vendor_id &&
- zynos_boards[i].board_id == bootbase_info.board_id) {
- return zynos_boards[i].mach_type;
- break;
- }
- }
-
- printk(KERN_WARNING "Unknown ZyXEL model (%u)\n",
- bootbase_info.board_id);
- return MACH_ADM5120_GENERIC;
-}
-
-static struct {
- unsigned long mach_type;
- u16 vid;
- u16 did;
- u16 svid;
- u16 sdid;
-} mylo_boards[] __initdata = {
-#define MYLO_BOARD(v, d, sv, sd, mt) \
- {.vid = (v), .did = (d), .svid = (sv), .sdid = (sd), .mach_type = (mt)}
-#define COMPEX_BOARD(d, mt) \
- MYLO_BOARD(VENID_COMPEX, (d), VENID_COMPEX, (d), (mt))
-
- COMPEX_BOARD(DEVID_COMPEX_NP27G, MACH_ADM5120_NP27G),
- COMPEX_BOARD(DEVID_COMPEX_NP28G, MACH_ADM5120_NP28G),
- COMPEX_BOARD(DEVID_COMPEX_NP28GHS, MACH_ADM5120_NP28GHS),
- COMPEX_BOARD(DEVID_COMPEX_WP54G, MACH_ADM5120_WP54),
- COMPEX_BOARD(DEVID_COMPEX_WP54Gv1C, MACH_ADM5120_WP54Gv1C),
- COMPEX_BOARD(DEVID_COMPEX_WP54AG, MACH_ADM5120_WP54),
- COMPEX_BOARD(DEVID_COMPEX_WPP54G, MACH_ADM5120_WP54),
- COMPEX_BOARD(DEVID_COMPEX_WPP54AG, MACH_ADM5120_WP54),
-};
-
-static unsigned long __init detect_machtype_myloader(void)
-{
- unsigned long ret;
- int i;
-
- ret = MACH_ADM5120_GENERIC;
- for (i = 0; i < ARRAY_SIZE(mylo_boards); i++) {
- if (mylo_boards[i].vid == myloader_info.vid &&
- mylo_boards[i].did == myloader_info.did &&
- mylo_boards[i].svid == myloader_info.svid &&
- mylo_boards[i].sdid == myloader_info.sdid) {
- ret = mylo_boards[i].mach_type;
- break;
- }
- }
-
- return ret;
-}
-
-static void __init prom_detect_machtype(void)
-{
- if (bootbase_present()) {
- adm5120_prom_type = ADM5120_PROM_BOOTBASE;
- mips_machtype = detect_machtype_bootbase();
- return;
- }
-
- if (cfe_present()) {
- adm5120_prom_type = ADM5120_PROM_CFE;
- mips_machtype = detect_machtype_cfe();
- return;
- }
-
- if (myloader_present()) {
- adm5120_prom_type = ADM5120_PROM_MYLOADER;
- mips_machtype = detect_machtype_myloader();
- return;
- }
-
- if (routerboot_present()) {
- adm5120_prom_type = ADM5120_PROM_ROUTERBOOT;
- mips_machtype = detect_machtype_routerboot();
- return;
- }
-
- if (generic_prom_present()) {
- adm5120_prom_type = ADM5120_PROM_GENERIC;
- mips_machtype = detect_machtype_generic();
- return;
- }
-
- mips_machtype = MACH_ADM5120_GENERIC;
-}
-
-/* TODO: this is an ugly hack for RouterBOARDS */
-extern char _image_cmdline;
-static void __init prom_init_cmdline(void)
-{
- char *cmd;
-
- /* init command line, register a default kernel command line */
- cmd = &_image_cmdline + 8;
- if (strlen(cmd) > 0)
- strlcpy(arcs_cmdline, cmd, sizeof(arcs_cmdline));
-
-}
-
-#define UART_READ(r) \
- __raw_readl((void __iomem *)(KSEG1ADDR(ADM5120_UART0_BASE)+(r)))
-#define UART_WRITE(r, v) \
- __raw_writel((v), (void __iomem *)(KSEG1ADDR(ADM5120_UART0_BASE)+(r)))
-
-void __init prom_putchar(char ch)
-{
- while ((UART_READ(UART_REG_FLAG) & UART_FLAG_TXFE) == 0);
- UART_WRITE(UART_REG_DATA, ch);
- while ((UART_READ(UART_REG_FLAG) & UART_FLAG_TXFE) == 0);
-}
-
-void __init prom_init(void)
-{
- prom_detect_machtype();
- prom_init_cmdline();
-}
-
-void __init prom_free_prom_memory(void)
-{
- /* We do not have to prom memory to free */
-}
+++ /dev/null
-/*
- * ADM5120 specific setup
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This code was based on the ADM5120 specific port of the Linux 2.6.10 kernel
- * done by Jeroen Vreeken
- * Copyright (C) 2005 Jeroen Vreeken (pe1rxq@amsat.org)
- *
- * Jeroen's code was based on the Linux 2.4.xx source codes found in various
- * tarballs released by Edimax for it's ADM5120 based devices
- * Copyright (C) ADMtek Incorporated
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/io.h>
-
-#include <asm/reboot.h>
-#include <asm/time.h>
-
-#include <asm/mach-adm5120/adm5120_info.h>
-#include <asm/mach-adm5120/adm5120_defs.h>
-#include <asm/mach-adm5120/adm5120_switch.h>
-#include <asm/mach-adm5120/adm5120_board.h>
-
-void (*adm5120_board_reset)(void);
-
-static char *prom_names[ADM5120_PROM_LAST+1] __initdata = {
- [ADM5120_PROM_GENERIC] = "Generic",
- [ADM5120_PROM_CFE] = "CFE",
- [ADM5120_PROM_UBOOT] = "U-Boot",
- [ADM5120_PROM_MYLOADER] = "MyLoader",
- [ADM5120_PROM_ROUTERBOOT] = "RouterBOOT",
- [ADM5120_PROM_BOOTBASE] = "Bootbase"
-};
-
-static void __init adm5120_report(void)
-{
- printk(KERN_INFO "SoC : ADM%04X%s revision %d, running "
- "at %ldMHz\n",
- adm5120_product_code,
- adm5120_package_bga() ? "" : "P",
- adm5120_revision, (adm5120_speed / 1000000));
- printk(KERN_INFO "Bootdev : %s flash\n",
- adm5120_nand_boot ? "NAND":"NOR");
- printk(KERN_INFO "Prom : %s\n", prom_names[adm5120_prom_type]);
-}
-
-static void adm5120_restart(char *command)
-{
- /* TODO: stop switch before reset */
-
- if (adm5120_board_reset)
- adm5120_board_reset();
-
- SW_WRITE_REG(SWITCH_REG_SOFT_RESET, 1);
-}
-
-static void adm5120_halt(void)
-{
- local_irq_disable();
-
- while (1) {
- if (cpu_wait)
- cpu_wait();
- }
-}
-
-void __init plat_time_init(void)
-{
- mips_hpt_frequency = adm5120_speed / 2;
-}
-
-void __init plat_mem_setup(void)
-{
- adm5120_soc_init();
- adm5120_mem_init();
- adm5120_report();
-
- _machine_restart = adm5120_restart;
- _machine_halt = adm5120_halt;
- pm_power_off = adm5120_halt;
-
- set_io_port_base(KSEG1);
-}
+++ /dev/null
-obj-y += compex.o
-
-obj-$(CONFIG_ADM5120_MACH_NP27G) += np27g.o
-obj-$(CONFIG_ADM5120_MACH_NP28G) += np28g.o
-obj-$(CONFIG_ADM5120_MACH_WP54) += wp54.o
+++ /dev/null
-/*
- * Compex boards
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "compex.h"
-
-#include <asm/mach-adm5120/prom/myloader.h>
-
-#define COMPEX_GPIO_DEV_MASK (1 << ADM5120_GPIO_PIN5)
-
-static void switch_bank_gpio5(unsigned bank)
-{
- switch (bank) {
- case 0:
- gpio_set_value(ADM5120_GPIO_PIN5, 0);
- break;
- case 1:
- gpio_set_value(ADM5120_GPIO_PIN5, 1);
- break;
- }
-}
-
-void __init compex_mac_setup(void)
-{
- if (myloader_present()) {
- int i;
-
- for (i = 0; i < 6; i++) {
- if (is_valid_ether_addr(myloader_info.macs[i]))
- memcpy(adm5120_eth_macs[i],
- myloader_info.macs[i], ETH_ALEN);
- else
- random_ether_addr(adm5120_eth_macs[i]);
- }
- } else {
- u8 mac[ETH_ALEN];
-
- random_ether_addr(mac);
- adm5120_setup_eth_macs(mac);
- }
-}
-
-void __init compex_generic_setup(void)
-{
- gpio_request(ADM5120_GPIO_PIN5, NULL); /* for flash A20 line */
- gpio_direction_output(ADM5120_GPIO_PIN5, 0);
-
- adm5120_flash0_data.switch_bank = switch_bank_gpio5;
- adm5120_add_device_flash(0);
-
- adm5120_add_device_uart(0);
- adm5120_add_device_uart(1);
-
- adm5120_add_device_gpio(COMPEX_GPIO_DEV_MASK);
-
- compex_mac_setup();
-}
+++ /dev/null
-/*
- * Compex boards
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <linux/etherdevice.h>
-
-#include <asm/bootinfo.h>
-
-#include <asm/mach-adm5120/adm5120_info.h>
-#include <asm/mach-adm5120/adm5120_board.h>
-#include <asm/mach-adm5120/adm5120_platform.h>
-
-extern void compex_generic_setup(void) __init;
+++ /dev/null
-/*
- * Compex NP27G board support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "compex.h"
-
-static u8 np27g_vlans[6] __initdata = {
- /* FIXME: untested */
- 0x41, 0x42, 0x44, 0x48, 0x50, 0x00
-};
-
-static void __init np27g_setup(void)
-{
- compex_generic_setup();
- adm5120_add_device_switch(5, np27g_vlans);
- adm5120_add_device_usb();
-
- /* TODO: add PCI IRQ map */
-}
-
-ADM5120_BOARD(MACH_ADM5120_NP27G, "Compex NetPassage 27G", np27g_setup);
+++ /dev/null
-/*
- * Compex NP28G board support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "compex.h"
-
-static struct adm5120_pci_irq np28g_pci_irqs[] __initdata = {
- PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI0),
- PCIIRQ(3, 0, 1, ADM5120_IRQ_PCI0),
- PCIIRQ(3, 1, 2, ADM5120_IRQ_PCI1),
- PCIIRQ(3, 2, 3, ADM5120_IRQ_PCI2)
-};
-
-static struct gpio_led np28g_gpio_leds[] __initdata = {
- GPIO_LED_INV(ADM5120_GPIO_PIN2, "diag", NULL),
- GPIO_LED_INV(ADM5120_GPIO_PIN3, "power", NULL),
- GPIO_LED_INV(ADM5120_GPIO_PIN6, "wan_cond", NULL),
- GPIO_LED_INV(ADM5120_GPIO_PIN7, "wifi", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P0L2, "usb1", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan1", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P1L2, "usb2", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan2", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P2L2, "usb3", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P3L0, "lan3", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P3L2, "usb4", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P4L0, "wan", NULL),
-};
-
-static u8 np28g_vlans[6] __initdata = {
- 0x50, 0x42, 0x44, 0x48, 0x00, 0x00
-};
-
-static void np28g_reset(void)
-{
- gpio_set_value(ADM5120_GPIO_PIN4, 0);
-}
-
-static void __init np28g_setup(void)
-{
- compex_generic_setup();
-
- /* setup reset line */
- gpio_request(ADM5120_GPIO_PIN4, NULL);
- gpio_direction_output(ADM5120_GPIO_PIN4, 1);
- adm5120_board_reset = np28g_reset;
-
- adm5120_add_device_switch(4, np28g_vlans);
- adm5120_add_device_usb();
-
- adm5120_add_device_gpio_leds(ARRAY_SIZE(np28g_gpio_leds),
- np28g_gpio_leds);
-
- adm5120_pci_set_irq_map(ARRAY_SIZE(np28g_pci_irqs), np28g_pci_irqs);
-}
-
-ADM5120_BOARD(MACH_ADM5120_NP28G, "Compex NetPassage 28G", np28g_setup);
+++ /dev/null
-/*
- * Compex WP54 board support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "compex.h"
-
-#ifdef CONFIG_MTD_PARTITIONS
-static struct mtd_partition wp54g_wrt_partitions[] = {
- {
- .name = "cfe",
- .offset = 0,
- .size = 0x050000,
- .mask_flags = MTD_WRITEABLE,
- } , {
- .name = "trx",
- .offset = MTDPART_OFS_APPEND,
- .size = 0x3A0000,
- } , {
- .name = "nvram",
- .offset = MTDPART_OFS_APPEND,
- .size = 0x010000,
- }
-};
-#endif /* CONFIG_MTD_PARTITIONS */
-
-static struct adm5120_pci_irq wp54_pci_irqs[] __initdata = {
- PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI0),
-};
-
-static struct gpio_button wp54_gpio_buttons[] __initdata = {
- {
- .desc = "reset_button",
- .type = EV_KEY,
- .code = BTN_0,
- .threshold = 5,
- .gpio = ADM5120_GPIO_PIN4,
- }
-};
-
-static struct gpio_led wp54_gpio_leds[] __initdata = {
- GPIO_LED_INV(ADM5120_GPIO_PIN2, "diag", NULL),
- GPIO_LED_INV(ADM5120_GPIO_PIN6, "wlan", NULL),
- GPIO_LED_INV(ADM5120_GPIO_PIN7, "wan", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P0L0, "lan1", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan2", NULL),
-};
-
-static u8 wp54_vlans[6] __initdata = {
- 0x41, 0x42, 0x00, 0x00, 0x00, 0x00
-};
-
-static void wp54_reset(void)
-{
- gpio_set_value(ADM5120_GPIO_PIN3, 0);
-}
-
-static void __init wp54_setup(void)
-{
- compex_generic_setup();
-
- /* setup reset line */
- gpio_request(ADM5120_GPIO_PIN3, NULL);
- gpio_direction_output(ADM5120_GPIO_PIN3, 1);
- adm5120_board_reset = wp54_reset;
-
- adm5120_add_device_switch(2, wp54_vlans);
- adm5120_add_device_gpio_buttons(ARRAY_SIZE(wp54_gpio_buttons),
- wp54_gpio_buttons);
- adm5120_add_device_gpio_leds(ARRAY_SIZE(wp54_gpio_leds),
- wp54_gpio_leds);
-
- adm5120_pci_set_irq_map(ARRAY_SIZE(wp54_pci_irqs), wp54_pci_irqs);
-}
-
-ADM5120_BOARD(MACH_ADM5120_WP54, "Compex WP54 family", wp54_setup);
-
-static void __init wp54_wrt_setup(void)
-{
-#ifdef CONFIG_MTD_PARTITIONS
- adm5120_flash0_data.nr_parts = ARRAY_SIZE(wp54g_wrt_partitions);
- adm5120_flash0_data.parts = wp54g_wrt_partitions;
-#endif
-
- wp54_setup();
-}
-
-ADM5120_BOARD(MACH_ADM5120_WP54G_WRT, "Compex WP54G-WRT", wp54_wrt_setup);
+++ /dev/null
-obj-y := br-61xx.o
-
-obj-$(CONFIG_ADM5120_MACH_BR_6104K) += br-6104k.o
-obj-$(CONFIG_ADM5120_MACH_BR_6104KP) += br-6104kp.o
-obj-$(CONFIG_ADM5120_MACH_BR_61X4WG) += br-61x4wg.o
+++ /dev/null
-/*
- * Edimax BR-6104K board support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "br-61xx.h"
-
-static struct gpio_led br6104k_gpio_leds[] __initdata = {
- GPIO_LED_STD(ADM5120_GPIO_PIN0, "power", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P0L1, "wan_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P0L0, "wan_lnkact", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P1L1, "lan1_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan1_lnkact", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P2L1, "lan2_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan2_lnkact", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P3L1, "lan3_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P3L0, "lan3_lnkact", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P4L1, "lan4_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P4L0, "lan4_lnkact", NULL),
-};
-
-static void __init br6104k_setup(void)
-{
- br61xx_generic_setup();
- adm5120_add_device_gpio_leds(ARRAY_SIZE(br6104k_gpio_leds),
- br6104k_gpio_leds);
-}
-
-ADM5120_BOARD(MACH_ADM5120_BR6104K, "Edimax BR-6104K", br6104k_setup);
+++ /dev/null
-/*
- * Edimax BR-6104KP board support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "br-61xx.h"
-
-static struct gpio_led br6104kp_gpio_leds[] __initdata = {
- GPIO_LED_STD(ADM5120_GPIO_PIN0, "power", NULL),
- GPIO_LED_STD(ADM5120_GPIO_PIN1, "usb1", NULL),
- GPIO_LED_INV(ADM5120_GPIO_PIN3, "usb2", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P0L1, "wan_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P0L0, "wan_lnkact", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P1L1, "lan1_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan1_lnkact", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P2L1, "lan2_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan2_lnkact", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P3L1, "lan3_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P3L0, "lan3_lnkact", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P4L1, "lan4_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P4L0, "lan4_lnkact", NULL),
-};
-
-static void __init br6104kp_setup(void)
-{
- br61xx_generic_setup();
- adm5120_add_device_gpio_leds(ARRAY_SIZE(br6104kp_gpio_leds),
- br6104kp_gpio_leds);
- adm5120_add_device_usb();
-}
-
-ADM5120_BOARD(MACH_ADM5120_BR6104KP, "Edimax BR-6104KP", br6104kp_setup);
+++ /dev/null
-/*
- * Edimax BR-6104Wg/6114WG board support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "br-61xx.h"
-
-static struct adm5120_pci_irq br61x4wg_pci_irqs[] __initdata = {
- PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI0),
-};
-
-static struct gpio_led br61x4wg_gpio_leds[] __initdata = {
- GPIO_LED_STD(ADM5120_GPIO_PIN0, "power", NULL),
- GPIO_LED_STD(ADM5120_GPIO_PIN5, "wlan", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P0L1, "wan_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P0L0, "wan_lnkact", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P1L1, "lan1_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan1_lnkact", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P2L1, "lan2_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan2_lnkact", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P3L1, "lan3_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P3L0, "lan3_lnkact", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P4L1, "lan4_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P4L0, "lan4_lnkact", NULL),
-};
-
-static void __init br61x4wg_setup(void)
-{
- br61xx_generic_setup();
- adm5120_add_device_gpio_leds(ARRAY_SIZE(br61x4wg_gpio_leds),
- br61x4wg_gpio_leds);
- adm5120_pci_set_irq_map(ARRAY_SIZE(br61x4wg_pci_irqs),
- br61x4wg_pci_irqs);
-}
-
-ADM5120_BOARD(MACH_ADM5120_BR61X4WG, "Edimax BR-6104WG/6114WG", br61x4wg_setup);
+++ /dev/null
-/*
- * Edimax BR-61xx support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "br-61xx.h"
-
-#include <prom/admboot.h>
-
-#define BR61XX_GPIO_DEV_MASK 0
-
-#define BR61XX_CONFIG_OFFSET 0x8000
-#define BR61XX_CONFIG_SIZE 0x1000
-
-#ifdef CONFIG_MTD_PARTITIONS
-static struct mtd_partition br61xx_partitions[] = {
- {
- .name = "admboot",
- .offset = 0,
- .size = 32*1024,
- .mask_flags = MTD_WRITEABLE,
- } , {
- .name = "config",
- .offset = MTDPART_OFS_APPEND,
- .size = 32*1024,
- } , {
- .name = "firmware",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- }
-};
-#endif /* CONFIG_MTD_PARTITIONS */
-
-static struct gpio_button br61xx_gpio_buttons[] __initdata = {
- {
- .desc = "reset_button",
- .type = EV_KEY,
- .code = BTN_0,
- .threshold = 5,
- .gpio = ADM5120_GPIO_PIN2,
- }
-};
-
-static u8 br61xx_vlans[6] __initdata = {
- 0x41, 0x42, 0x44, 0x48, 0x50, 0x00
-};
-
-static void __init br61xx_mac_setup(void)
-{
- u8 mac_base[6];
- int err;
-
- err = admboot_get_mac_base(BR61XX_CONFIG_OFFSET,
- BR61XX_CONFIG_SIZE, mac_base);
-
- if ((err) || !is_valid_ether_addr(mac_base))
- random_ether_addr(mac_base);
-
- adm5120_setup_eth_macs(mac_base);
-}
-
-void __init br61xx_generic_setup(void)
-{
-
-#ifdef CONFIG_MTD_PARTITIONS
- adm5120_flash0_data.nr_parts = ARRAY_SIZE(br61xx_partitions);
- adm5120_flash0_data.parts = br61xx_partitions;
-#endif /* CONFIG_MTD_PARTITIONS */
- adm5120_add_device_flash(0);
-
- adm5120_add_device_gpio(BR61XX_GPIO_DEV_MASK);
-
- adm5120_add_device_uart(0);
- adm5120_add_device_uart(1);
-
- adm5120_add_device_switch(5, br61xx_vlans);
- adm5120_add_device_gpio_buttons(ARRAY_SIZE(br61xx_gpio_buttons),
- br61xx_gpio_buttons);
-
- br61xx_mac_setup();
-}
+++ /dev/null
-/*
- * Edimax BR-61xx board support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <linux/etherdevice.h>
-
-#include <asm/bootinfo.h>
-
-#include <asm/mach-adm5120/adm5120_board.h>
-#include <asm/mach-adm5120/adm5120_platform.h>
-
-extern void __init br61xx_generic_setup(void) __init;
+++ /dev/null
-obj-y += infineon.o
-
-obj-$(CONFIG_ADM5120_MACH_EASY5120_RT) += easy5120-rt.o
-obj-$(CONFIG_ADM5120_MACH_EASY5120_WVOIP) += easy5120-wvoip.o
-obj-$(CONFIG_ADM5120_MACH_EASY5120P_ATA) += easy5120p-ata.o
-obj-$(CONFIG_ADM5120_MACH_EASY83000) += easy83000.o
+++ /dev/null
-/*
- * Infineon EASY 5120-RT Reference Board support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "infineon.h"
-
-static struct gpio_led easy5120_rt_gpio_leds[] __initdata = {
- GPIO_LED_INV(ADM5120_GPIO_PIN6, "user", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P0L0, "lan0_led1", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P0L1, "lan0_led2", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan1_led1", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P1L1, "lan1_led2", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan2_led1", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P2L1, "lan2_led2", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P3L0, "lan3_led1", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P3L1, "lan3_led2", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P4L0, "wan", NULL),
-};
-
-static struct adm5120_pci_irq easy5120_rt_pci_irqs[] __initdata = {
- PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI0),
-};
-
-static u8 easy5120_rt_vlans[6] __initdata = {
- 0x41, 0x42, 0x44, 0x48, 0x50, 0x00
-};
-
-static void __init easy5120_rt_setup(void)
-{
- easy_setup_bga();
-
- adm5120_add_device_switch(5, easy5120_rt_vlans);
- adm5120_add_device_usb();
- adm5120_add_device_gpio_leds(ARRAY_SIZE(easy5120_rt_gpio_leds),
- easy5120_rt_gpio_leds);
- adm5120_pci_set_irq_map(ARRAY_SIZE(easy5120_rt_pci_irqs),
- easy5120_rt_pci_irqs);
-}
-
-ADM5120_BOARD(MACH_ADM5120_EASY5120RT,
- "Infineon EASY 5120-RT Reference Board",
- easy5120_rt_setup);
+++ /dev/null
-/*
- * Infineon EASY 5120-WVoIP Reference Board support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "infineon.h"
-
-static void __init easy5120wvoip_setup(void)
-{
- easy_setup_bga();
- adm5120_add_device_switch(6, NULL);
-
- /* TODO: add VINETIC2 device */
- /* TODO: setup PCI IRQ map */
-}
-
-ADM5120_BOARD(MACH_ADM5120_EASY5120WVOIP,
- "Infineon EASY 5120-WVoIP Reference Board",
- easy5120wvoip_setup);
+++ /dev/null
-/*
- * Infineon EASY 5120P-ATA Reference Board support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "infineon.h"
-
-static void __init easy5120pata_setup(void)
-{
- easy_setup_pqfp();
-
- adm5120_add_device_switch(6, NULL);
-}
-
-ADM5120_BOARD(MACH_ADM5120_EASY5120PATA,
- "Infineon EASY 5120P-ATA Reference Board",
- easy5120pata_setup);
+++ /dev/null
-/*
- * Infineon EASY 83000 Reference Board support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "infineon.h"
-
-static void __init easy83000_setup(void)
-{
- easy_setup_pqfp();
- adm5120_add_device_switch(6, NULL);
-
- /* TODO: add VINAX device */
-}
-
-ADM5120_BOARD(MACH_ADM5120_EASY83000,
- "Infineon EASY 83000 Reference Board",
- easy83000_setup);
+++ /dev/null
-/*
- * Infineon Reference Boards
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "infineon.h"
-
-#include <prom/admboot.h>
-
-#define EASY_CONFIG_OFFSET 0x10000
-#define EASY_CONFIG_SIZE 0x1000
-
-#ifdef CONFIG_MTD_PARTITIONS
-static struct mtd_partition easy_partitions[] = {
- {
- .name = "admboot",
- .offset = 0,
- .size = 64*1024,
- .mask_flags = MTD_WRITEABLE,
- } , {
- .name = "boardcfg",
- .offset = MTDPART_OFS_APPEND,
- .size = 64*1024,
- } , {
- .name = "firmware",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- }
-};
-#endif /* CONFIG_MTD_PARTITIONS */
-
-static __init void easy_setup_mac(void)
-{
- u8 mac_base[6];
- int err;
-
- err = admboot_get_mac_base(EASY_CONFIG_OFFSET,
- EASY_CONFIG_SIZE, mac_base);
-
- if ((err) || !is_valid_ether_addr(mac_base))
- random_ether_addr(mac_base);
-
- adm5120_setup_eth_macs(mac_base);
-}
-
-static void switch_bank_gpio3(unsigned bank)
-{
- switch (bank) {
- case 0:
- gpio_set_value(ADM5120_GPIO_PIN3, 0);
- break;
- case 1:
- gpio_set_value(ADM5120_GPIO_PIN3, 1);
- break;
- }
-}
-
-void __init easy_setup_pqfp(void)
-{
- /* setup flash A20 line */
- gpio_request(ADM5120_GPIO_PIN3, NULL);
- gpio_direction_output(ADM5120_GPIO_PIN3, 0);
- adm5120_flash0_data.switch_bank = switch_bank_gpio3;
-
-#ifdef CONFIG_MTD_PARTITIONS
- adm5120_flash0_data.nr_parts = ARRAY_SIZE(easy_partitions);
- adm5120_flash0_data.parts = easy_partitions;
-#endif /* CONFIG_MTD_PARTITIONS */
-
- adm5120_add_device_uart(0);
- adm5120_add_device_uart(1);
-
- adm5120_add_device_flash(0);
-
- easy_setup_mac();
-}
-
-static void switch_bank_gpio5(unsigned bank)
-{
- switch (bank) {
- case 0:
- gpio_set_value(ADM5120_GPIO_PIN5, 0);
- break;
- case 1:
- gpio_set_value(ADM5120_GPIO_PIN5, 1);
- break;
- }
-}
-
-void __init easy_setup_bga(void)
-{
- /* setup flash A20 line */
- gpio_request(ADM5120_GPIO_PIN5, NULL);
- gpio_direction_output(ADM5120_GPIO_PIN5, 0);
- adm5120_flash0_data.switch_bank = switch_bank_gpio5;
-
-#ifdef CONFIG_MTD_PARTITIONS
- adm5120_flash0_data.nr_parts = ARRAY_SIZE(easy_partitions);
- adm5120_flash0_data.parts = easy_partitions;
-#endif /* CONFIG_MTD_PARTITIONS */
-
- adm5120_add_device_uart(0);
- adm5120_add_device_uart(1);
-
- adm5120_add_device_flash(0);
-
- easy_setup_mac();
-}
+++ /dev/null
-/*
- * Infineon Reference Boards
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <linux/etherdevice.h>
-
-#include <asm/bootinfo.h>
-
-#include <asm/mach-adm5120/adm5120_defs.h>
-#include <asm/mach-adm5120/adm5120_board.h>
-#include <asm/mach-adm5120/adm5120_platform.h>
-#include <asm/mach-adm5120/adm5120_info.h>
-
-extern void easy_setup_pqfp(void) __init;
-extern void easy_setup_bga(void) __init;
+++ /dev/null
-obj-y += rb-1xx.o
-
-obj-${CONFIG_ADM5120_MACH_RB_11X} += rb-11x.o
-obj-${CONFIG_ADM5120_MACH_RB_133} += rb-133.o
-obj-${CONFIG_ADM5120_MACH_RB_133C} += rb-133c.o
-obj-${CONFIG_ADM5120_MACH_RB_150} += rb-150.o
-obj-${CONFIG_ADM5120_MACH_RB_153} += rb-153.o
-obj-${CONFIG_ADM5120_MACH_RB_192} += rb-192.o
+++ /dev/null
-/*
- * Mikrotik RouterBOARD 111/112 support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "rb-1xx.h"
-
-static struct gpio_led rb11x_gpio_leds[] __initdata = {
- GPIO_LED_STD(ADM5120_GPIO_PIN3, "user", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P0L1, "lan_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P0L0, "lan_lnkact", NULL),
-};
-
-static u8 rb11x_vlans[6] __initdata = {
- 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00
-};
-
-static void __init rb11x_setup(void)
-{
- rb1xx_generic_setup();
- rb1xx_add_device_nand();
-
- adm5120_add_device_switch(1, rb11x_vlans);
- adm5120_add_device_gpio(0);
- adm5120_add_device_gpio_leds(ARRAY_SIZE(rb11x_gpio_leds),
- rb11x_gpio_leds);
-}
-
-ADM5120_BOARD(MACH_ADM5120_RB_11X, "Mikrotik RouterBOARD 111/112", rb11x_setup);
+++ /dev/null
-/*
- * Mikrotik RouterBOARD 133 support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "rb-1xx.h"
-
-static struct gpio_led rb133_gpio_leds[] __initdata = {
- GPIO_LED_STD(ADM5120_GPIO_PIN6, "power", NULL),
- GPIO_LED_STD(ADM5120_GPIO_PIN5, "user", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P2L1, "lan1_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan1_lnkact", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P1L1, "lan2_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan2_lnkact", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P0L1, "lan3_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P0L0, "lan3_lnkact", NULL),
-};
-
-static u8 rb133_vlans[6] __initdata = {
- 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00
-};
-
-static void __init rb133_setup(void)
-{
- rb1xx_generic_setup();
- rb1xx_add_device_nand();
-
- adm5120_add_device_switch(3, rb133_vlans);
- adm5120_add_device_gpio(0);
- adm5120_add_device_gpio_leds(ARRAY_SIZE(rb133_gpio_leds),
- rb133_gpio_leds);
-}
-
-ADM5120_BOARD(MACH_ADM5120_RB_133, "Mikrotik RouterBOARD 133", rb133_setup);
+++ /dev/null
-/*
- * Mikrotik RouterBOARD 133C support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "rb-1xx.h"
-
-static struct gpio_led rb133c_gpio_leds[] __initdata = {
- GPIO_LED_STD(ADM5120_GPIO_PIN6, "power", NULL),
- GPIO_LED_STD(ADM5120_GPIO_PIN5, "user", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P2L1, "lan1_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan1_lnkact", NULL),
-};
-
-static u8 rb133c_vlans[6] __initdata = {
- 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00
-};
-
-static void __init rb133c_setup(void)
-{
- rb1xx_generic_setup();
- rb1xx_add_device_nand();
-
- adm5120_add_device_switch(1, rb133c_vlans);
- adm5120_add_device_gpio(0);
- adm5120_add_device_gpio_leds(ARRAY_SIZE(rb133c_gpio_leds),
- rb133c_gpio_leds);
-}
-
-ADM5120_BOARD(MACH_ADM5120_RB_133C, "Mikrotik RouterBOARD 133C", rb133c_setup);
+++ /dev/null
-/*
- * Mikrotik RouterBOARD 150 support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "rb-1xx.h"
-
-#define RB150_NAND_BASE 0x1FC80000
-#define RB150_NAND_SIZE 1
-
-#define RB150_GPIO_NAND_READY ADM5120_GPIO_PIN0
-#define RB150_GPIO_NAND_NCE ADM5120_GPIO_PIN1
-#define RB150_GPIO_NAND_CLE ADM5120_GPIO_P2L2
-#define RB150_GPIO_NAND_ALE ADM5120_GPIO_P3L2
-#define RB150_GPIO_RESET_BUTTON ADM5120_GPIO_PIN1 /* FIXME */
-
-#define RB150_GPIO_DEV_MASK ( 1 << RB150_GPIO_NAND_READY \
- | 1 << RB150_GPIO_NAND_NCE \
- | 1 << RB150_GPIO_NAND_CLE \
- | 1 << RB150_GPIO_NAND_ALE)
-
-#define RB150_NAND_DELAY 100
-
-#define RB150_NAND_WRITE(v) \
- writeb((v), (void __iomem *)KSEG1ADDR(RB150_NAND_BASE))
-
-static struct resource rb150_nand_resources[] __initdata = {
- [0] = {
- .start = RB150_NAND_BASE,
- .end = RB150_NAND_BASE + RB150_NAND_SIZE-1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct gpio_led rb150_gpio_leds[] __initdata = {
- GPIO_LED_STD(ADM5120_GPIO_P0L2, "user", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P0L1, "lan1_led1", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P0L0, "lan1_led2", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P1L1, "lan5_led1", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan5_led2", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P2L1, "lan4_led1", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan4_led2", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P3L1, "lan3_led1", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P3L0, "lan3_led2", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P4L1, "lan2_led1", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P4L0, "lan2_led2", NULL),
-};
-
-static u8 rb150_vlans[6] __initdata = {
- 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00
-};
-
-static int rb150_nand_dev_ready(struct mtd_info *mtd)
-{
- return gpio_get_value(RB150_GPIO_NAND_READY);
-}
-
-static void rb150_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
- unsigned int ctrl)
-{
- if (ctrl & NAND_CTRL_CHANGE) {
- gpio_set_value(RB150_GPIO_NAND_CLE, (ctrl & NAND_CLE) ? 1 : 0);
- gpio_set_value(RB150_GPIO_NAND_ALE, (ctrl & NAND_ALE) ? 1 : 0);
- gpio_set_value(RB150_GPIO_NAND_NCE, (ctrl & NAND_NCE) ? 0 : 1);
- }
-
- udelay(RB150_NAND_DELAY);
-
- if (cmd != NAND_CMD_NONE)
- RB150_NAND_WRITE(cmd);
-}
-
-static void __init rb150_add_device_nand(void)
-{
- struct platform_device *pdev;
- int err;
-
- /* setup GPIO pins for NAND flash chip */
- gpio_request(RB150_GPIO_NAND_READY, "nand-ready");
- gpio_direction_input(RB150_GPIO_NAND_READY);
- gpio_request(RB150_GPIO_NAND_NCE, "nand-nce");
- gpio_direction_output(RB150_GPIO_NAND_NCE, 1);
- gpio_request(RB150_GPIO_NAND_CLE, "nand-cle");
- gpio_direction_output(RB150_GPIO_NAND_CLE, 0);
- gpio_request(RB150_GPIO_NAND_ALE, "nand-ale");
- gpio_direction_output(RB150_GPIO_NAND_ALE, 0);
-
- pdev = platform_device_alloc("gen_nand", -1);
- if (!pdev)
- goto err_out;
-
- err = platform_device_add_resources(pdev, rb150_nand_resources,
- ARRAY_SIZE(rb150_nand_resources));
- if (err)
- goto err_put;
-
-
- rb1xx_nand_data.ctrl.cmd_ctrl = rb150_nand_cmd_ctrl;
- rb1xx_nand_data.ctrl.dev_ready = rb150_nand_dev_ready;
-
- err = platform_device_add_data(pdev, &rb1xx_nand_data,
- sizeof(rb1xx_nand_data));
- if (err)
- goto err_put;
-
- err = platform_device_add(pdev);
- if (err)
- goto err_put;
-
- return;
-
-err_put:
- platform_device_put(pdev);
-err_out:
- return;
-}
-
-static void __init rb150_setup(void)
-{
- rb1xx_gpio_buttons[0].gpio = RB150_GPIO_RESET_BUTTON;
- rb1xx_generic_setup();
- rb150_add_device_nand();
-
- adm5120_add_device_gpio(RB150_GPIO_DEV_MASK);
- adm5120_add_device_gpio_leds(ARRAY_SIZE(rb150_gpio_leds),
- rb150_gpio_leds);
- adm5120_add_device_switch(5, rb150_vlans);
-}
-
-ADM5120_BOARD(MACH_ADM5120_RB_150, "Mikrotik RouterBOARD 150", rb150_setup);
+++ /dev/null
-/*
- * Mikrotik RouterBOARD 153 support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "rb-1xx.h"
-
-#define RB153_GPIO_DEV_MASK ( 1 << ADM5120_GPIO_PIN0 \
- | 1 << ADM5120_GPIO_PIN3 \
- | 1 << ADM5120_GPIO_PIN4 )
-
-static struct resource rb153_cf_resources[] __initdata = {
- {
- .name = "cf_membase",
- .start = ADM5120_EXTIO1_BASE,
- .end = ADM5120_EXTIO1_BASE + ADM5120_EXTIO1_SIZE-1 ,
- .flags = IORESOURCE_MEM
- }, {
- .name = "cf_irq",
- .start = ADM5120_IRQ_GPIO4,
- .end = ADM5120_IRQ_GPIO4,
- .flags = IORESOURCE_IRQ
- }
-};
-
-static struct gpio_led rb153_gpio_leds[] __initdata = {
- GPIO_LED_STD(ADM5120_GPIO_PIN5, "user", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P0L1, "lan1_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P0L0, "lan1_lnkact", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P1L1, "lan5_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan5_lnkact", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P2L1, "lan4_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan4_lnkact", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P3L1, "lan3_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P3L0, "lan3_lnkact", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P4L1, "lan2_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P4L0, "lan2_lnkact", NULL),
-};
-
-static u8 rb153_vlans[6] __initdata = {
- 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00
-};
-
-static void __init rb153_add_device_cf(void)
-{
- /* enable CSX1:INTX1 on GPIO[3:4] for the CF slot */
- adm5120_gpio_csx1_enable();
-
- /* enable the wait state pin GPIO[0] for external I/O control */
- adm5120_gpio_ew_enable();
-
- platform_device_register_simple("pata-rb153-cf", -1,
- rb153_cf_resources, ARRAY_SIZE(rb153_cf_resources));
-}
-
-static void __init rb153_setup(void)
-{
- rb1xx_generic_setup();
- rb1xx_add_device_nand();
- rb153_add_device_cf();
-
- adm5120_add_device_gpio(RB153_GPIO_DEV_MASK);
- adm5120_add_device_gpio_leds(ARRAY_SIZE(rb153_gpio_leds),
- rb153_gpio_leds);
- adm5120_add_device_switch(5, rb153_vlans);
-}
-
-ADM5120_BOARD(MACH_ADM5120_RB_153, "Mikrotik RouterBOARD 153", rb153_setup);
+++ /dev/null
-/*
- * Mikrotik RouterBOARD 192 support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "rb-1xx.h"
-
-static u8 rb192_vlans[6] __initdata = {
- 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00
-};
-
-static void __init rb192_setup(void)
-{
- rb1xx_generic_setup();
- rb1xx_add_device_nand();
-
- adm5120_add_device_gpio(0);
- adm5120_add_device_switch(6, rb192_vlans);
-}
-
-ADM5120_BOARD(MACH_ADM5120_RB_192, "Mikrotik RouterBOARD 192", rb192_setup);
+++ /dev/null
-/*
- * Mikrotik RouterBOARD 1xx series support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * NAND initialization code was based on a driver for Linux 2.6.19+ which
- * was derived from the driver for Linux 2.4.xx published by Mikrotik for
- * their RouterBoard 1xx and 5xx series boards.
- * Copyright (C) 2007 David Goodenough <david.goodenough@linkchoose.co.uk>
- * Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "rb-1xx.h"
-
-#define RB1XX_NAND_CHIP_DELAY 25
-
-static struct adm5120_pci_irq rb1xx_pci_irqs[] __initdata = {
- PCIIRQ(1, 0, 1, ADM5120_IRQ_PCI0),
- PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI1),
- PCIIRQ(3, 0, 1, ADM5120_IRQ_PCI2)
-};
-
-#ifdef CONFIG_MTD_PARTITIONS
-static struct mtd_partition rb1xx_nor_parts[] = {
- {
- .name = "booter",
- .offset = 0,
- .size = 64*1024,
- .mask_flags = MTD_WRITEABLE,
- } , {
- .name = "firmware",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- }
-};
-
-static struct mtd_partition rb1xx_nand_parts[] = {
- {
- .name = "kernel",
- .offset = 0,
- .size = 4 * 1024 * 1024,
- } , {
- .name = "rootfs",
- .offset = MTDPART_OFS_NXTBLK,
- .size = MTDPART_SIZ_FULL
- }
-};
-#endif /* CONFIG_MTD_PARTITIONS */
-
-/*
- * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader
- * will not be able to find the kernel that we load. So set the oobinfo
- * when creating the partitions
- */
-static struct nand_ecclayout rb1xx_nand_ecclayout = {
- .eccbytes = 6,
- .eccpos = { 8, 9, 10, 13, 14, 15 },
- .oobavail = 9,
- .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
-};
-
-/*--------------------------------------------------------------------------*/
-
-static int rb1xx_nand_fixup(struct mtd_info *mtd)
-{
- struct nand_chip *chip = mtd->priv;
-
- if (mtd->writesize == 512)
- chip->ecc.layout = &rb1xx_nand_ecclayout;
-
- return 0;
-}
-
-struct platform_nand_data rb1xx_nand_data __initdata = {
- .chip = {
- .nr_chips = 1,
-#ifdef CONFIG_MTD_PARTITIONS
- .nr_partitions = ARRAY_SIZE(rb1xx_nand_parts),
- .partitions = rb1xx_nand_parts,
-#endif /* CONFIG_MTD_PARTITIONS */
- .chip_delay = RB1XX_NAND_CHIP_DELAY,
- .options = NAND_NO_AUTOINCR,
- .chip_fixup = rb1xx_nand_fixup,
- },
-};
-
-struct gpio_button rb1xx_gpio_buttons[] __initdata = {
- {
- .desc = "reset_button",
- .type = EV_KEY,
- .code = BTN_0,
- .threshold = 5,
- .gpio = ADM5120_GPIO_PIN7,
- }
-};
-
-static void __init rb1xx_mac_setup(void)
-{
- if (rb_hs.mac_base != NULL && is_valid_ether_addr(rb_hs.mac_base)) {
- adm5120_setup_eth_macs(rb_hs.mac_base);
- } else {
- u8 mac[ETH_ALEN];
-
- random_ether_addr(mac);
- adm5120_setup_eth_macs(mac);
- }
-}
-
-void __init rb1xx_add_device_flash(void)
-{
- /* setup data for flash0 device */
-#ifdef CONFIG_MTD_PARTITIONS
- adm5120_flash0_data.nr_parts = ARRAY_SIZE(rb1xx_nor_parts);
- adm5120_flash0_data.parts = rb1xx_nor_parts;
-#endif /* CONFIG_MTD_PARTITIONS */
- adm5120_flash0_data.window_size = 128*1024;
-
- adm5120_add_device_flash(0);
-}
-
-void __init rb1xx_add_device_nand(void)
-{
- /* enable NAND flash interface */
- adm5120_nand_enable();
-
- /* initialize NAND chip */
- adm5120_nand_set_spn(1);
- adm5120_nand_set_wpn(0);
-
- adm5120_add_device_nand(&rb1xx_nand_data);
-}
-
-void __init rb1xx_generic_setup(void)
-{
- if (adm5120_package_bga())
- adm5120_pci_set_irq_map(ARRAY_SIZE(rb1xx_pci_irqs),
- rb1xx_pci_irqs);
-
- adm5120_add_device_uart(0);
- adm5120_add_device_uart(1);
-
- adm5120_add_device_gpio_buttons(ARRAY_SIZE(rb1xx_gpio_buttons),
- rb1xx_gpio_buttons);
-
- rb1xx_add_device_flash();
- rb1xx_mac_setup();
-}
+++ /dev/null
-/*
- * Mikrotik RouterBOARD 1xx series support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <linux/etherdevice.h>
-
-#include <asm/bootinfo.h>
-
-#include <asm/mach-adm5120/adm5120_defs.h>
-#include <asm/mach-adm5120/adm5120_nand.h>
-#include <asm/mach-adm5120/adm5120_board.h>
-#include <asm/mach-adm5120/adm5120_platform.h>
-#include <asm/mach-adm5120/adm5120_info.h>
-
-#include <prom/routerboot.h>
-
-extern struct platform_nand_data rb1xx_nand_data __initdata;
-extern struct gpio_button rb1xx_gpio_buttons[] __initdata;
-
-extern void rb1xx_add_device_flash(void) __init;
-extern void rb1xx_add_device_nand(void) __init;
-extern void rb1xx_generic_setup(void) __init;
+++ /dev/null
-obj-$(CONFIG_ADM5120_MACH_PMUGW) += pmugw.o
+++ /dev/null
-/*
- * Motorola Powerline MU Gateway board
- *
- * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <linux/etherdevice.h>
-
-#include <asm/bootinfo.h>
-
-#include <asm/mach-adm5120/adm5120_defs.h>
-#include <asm/mach-adm5120/adm5120_board.h>
-#include <asm/mach-adm5120/adm5120_platform.h>
-#include <asm/mach-adm5120/adm5120_info.h>
-
-#include <prom/admboot.h>
-
-#define PMUGW_CONFIG_OFFSET 0x10000
-#define PMUGW_CONFIG_SIZE 0x1000
-
-#ifdef CONFIG_MTD_PARTITIONS
-static struct mtd_partition pmugw_partitions[] = {
- {
- .name = "admboot",
- .offset = 0,
- .size = 64*1024,
- .mask_flags = MTD_WRITEABLE,
- } , {
- .name = "boardcfg",
- .offset = MTDPART_OFS_APPEND,
- .size = 64*1024,
- } , {
- .name = "firmware",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- }
-};
-#endif /* CONFIG_MTD_PARTITIONS */
-
-static u8 pmugw_vlans[6] __initdata = {
- 0x41, 0x42, 0x44, 0x48, 0x50, 0x00
-};
-
-static __init void pmugw_setup_mac(void)
-{
- u8 mac_base[6];
- int err;
-
- err = admboot_get_mac_base(PMUGW_CONFIG_OFFSET,
- PMUGW_CONFIG_SIZE, mac_base);
-
- if ((err) || !is_valid_ether_addr(mac_base))
- random_ether_addr(mac_base);
-
- adm5120_setup_eth_macs(mac_base);
-}
-
-static void switch_bank_gpio5(unsigned bank)
-{
- switch (bank) {
- case 0:
- gpio_set_value(ADM5120_GPIO_PIN5, 0);
- break;
- case 1:
- gpio_set_value(ADM5120_GPIO_PIN5, 1);
- break;
- }
-}
-
-void __init pmugw_setup(void)
-{
- /* setup flash A20 line */
- gpio_request(ADM5120_GPIO_PIN5, NULL);
- gpio_direction_output(ADM5120_GPIO_PIN5, 0);
- adm5120_flash0_data.switch_bank = switch_bank_gpio5;
-
-#ifdef CONFIG_MTD_PARTITIONS
- adm5120_flash0_data.nr_parts = ARRAY_SIZE(pmugw_partitions);
- adm5120_flash0_data.parts = pmugw_partitions;
-#endif /* CONFIG_MTD_PARTITIONS */
-
- adm5120_add_device_uart(1); /* ttyS0 */
- adm5120_add_device_uart(0); /* ttyS1 */
-
- adm5120_add_device_flash(0);
-
- pmugw_setup_mac();
- adm5120_add_device_switch(5, pmugw_vlans);
-}
-
-ADM5120_BOARD(MACH_ADM5120_PMUGW,
- "Motorola Powerline MU Gateway",
- pmugw_setup);
+++ /dev/null
-#
-# Makefile for the ADMtek ADM5120 SoC specific parts of the kernel
-#
-
-lib-y += admboot.o
-lib-y += bootbase.o
-lib-y += cfe.o
-lib-y += generic.o
-lib-y += myloader.o
-lib-y += routerboot.o
+++ /dev/null
-/*
- * ADMBoot specific prom routines
- *
- * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/errno.h>
-
-#include <asm/addrspace.h>
-#include <asm/byteorder.h>
-
-#include <asm/mach-adm5120/adm5120_defs.h>
-#include <prom/admboot.h>
-#include "prom_read.h"
-
-#define ADMBOOT_MAGIC_MAC_BASE 0x636D676D /* 'mgmc' */
-
-int __init admboot_get_mac_base(u32 offset, u32 len, u8 *mac)
-{
- u8 *cfg;
- int i;
-
- cfg = (u8 *) KSEG1ADDR(ADM5120_SRAM0_BASE + offset);
- for (i = 0; i < len; i += 4) {
- u32 magic;
-
- magic = prom_read_le32(cfg + i);
- if (magic == ADMBOOT_MAGIC_MAC_BASE) {
- int j;
-
- for (j = 0; j < 6; j++)
- mac[j] = cfg[i + 4 + j];
-
- return 0;
- }
- }
-
- return -ENXIO;
-}
+++ /dev/null
-/*
- * ZyXEL's Bootbase specific prom routines
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/types.h>
-#include <linux/autoconf.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/string.h>
-
-#include <asm/bootinfo.h>
-#include <asm/addrspace.h>
-#include <asm/byteorder.h>
-
-#include <asm/mach-adm5120/adm5120_defs.h>
-#include <prom/zynos.h>
-#include "prom_read.h"
-
-#define ZYNOS_INFO_ADDR KSEG1ADDR(ADM5120_SRAM0_BASE+0x3F90)
-#define ZYNOS_HDBG_ADDR KSEG1ADDR(ADM5120_SRAM0_BASE+0x4000)
-#define BOOTEXT_ADDR_MIN KSEG1ADDR(ADM5120_SRAM0_BASE)
-#define BOOTEXT_ADDR_MAX (BOOTEXT_ADDR_MIN + (2*1024*1024))
-
-static int bootbase_found;
-static struct zynos_board_info *board_info;
-
-struct bootbase_info bootbase_info;
-
-static inline int bootbase_dbgarea_present(u8 *data)
-{
- u32 t;
-
- t = prom_read_be32(data+5);
- if (t != ZYNOS_MAGIC_DBGAREA1)
- return 0;
-
- t = prom_read_be32(data+9);
- if (t != ZYNOS_MAGIC_DBGAREA2)
- return 0;
-
- return 1;
-}
-
-static inline u32 bootbase_get_bootext_addr(void)
-{
- return prom_read_be32(&board_info->bootext_addr);
-}
-
-static inline void bootbase_get_mac(u8 *mac)
-{
- int i;
-
- for (i = 0; i < 6; i++)
- mac[i] = board_info->mac[i];
-}
-
-static inline u16 bootbase_get_vendor_id(void)
-{
-#define CHECK_VENDOR(n) (strnicmp(board_info->vendor, (n), strlen(n)) == 0)
- unsigned char vendor[ZYNOS_NAME_LEN];
- int i;
-
- for (i = 0; i < ZYNOS_NAME_LEN; i++)
- vendor[i] = board_info->vendor[i];
-
- if CHECK_VENDOR(ZYNOS_VENDOR_ZYXEL)
- return ZYNOS_VENDOR_ID_ZYXEL;
-
- if CHECK_VENDOR(ZYNOS_VENDOR_DLINK)
- return ZYNOS_VENDOR_ID_DLINK;
-
- if CHECK_VENDOR(ZYNOS_VENDOR_LUCENT)
- return ZYNOS_VENDOR_ID_LUCENT;
-
- if CHECK_VENDOR(ZYNOS_VENDOR_NETGEAR)
- return ZYNOS_VENDOR_ID_NETGEAR;
-
- return ZYNOS_VENDOR_ID_OTHER;
-}
-
-static inline u16 bootbase_get_board_id(void)
-{
- return prom_read_be16(&board_info->board_id);
-}
-
-int __init bootbase_present(void)
-{
- u32 t;
-
- if (bootbase_found)
- goto out;
-
- /* check presence of the dbgarea */
- if (bootbase_dbgarea_present((u8 *)ZYNOS_HDBG_ADDR) == 0)
- goto out;
-
- board_info = (struct zynos_board_info *)(ZYNOS_INFO_ADDR);
-
- /* check for a valid BootExt address */
- t = bootbase_get_bootext_addr();
- if ((t < BOOTEXT_ADDR_MIN) || (t > BOOTEXT_ADDR_MAX))
- goto out;
-
- bootbase_info.vendor_id = bootbase_get_vendor_id();
- bootbase_info.board_id = bootbase_get_board_id();
- bootbase_get_mac(bootbase_info.mac);
-
- bootbase_found = 1;
-
-out:
- return bootbase_found;
-}
-
+++ /dev/null
-/*
- * Broadcom's CFE specific prom routines
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/types.h>
-#include <linux/init.h>
-
-#include <asm/bootinfo.h>
-#include <asm/addrspace.h>
-
-#include <prom/cfe.h>
-#include "prom_read.h"
-
-/*
- * CFE based boards
- */
-#define CFE_EPTSEAL 0x43464531 /* CFE1 is the magic number to recognize CFE
-from other bootloaders */
-
-static int cfe_found;
-
-static u32 cfe_handle;
-static u32 cfe_entry;
-static u32 cfe_seal;
-
-int __init cfe_present(void)
-{
- /*
- * This method only works, when we are booted directly from the CFE.
- */
- u32 a1 = (u32) fw_arg1;
-
- if (cfe_found)
- return 1;
-
- cfe_handle = (u32) fw_arg0;
- cfe_entry = (u32) fw_arg2;
- cfe_seal = (u32) fw_arg3;
-
- /* Check for CFE by finding the CFE magic number */
- if (cfe_seal != CFE_EPTSEAL)
- return 0;
-
- /* cfe_a1_val must be 0, because only one CPU present in the ADM5120 */
- if (a1 != 0)
- return 0;
-
- /* The cfe_handle, and the cfe_entry must be kernel mode addresses */
- if ((cfe_handle < KSEG0) || (cfe_entry < KSEG0))
- return 0;
-
- cfe_found = 1;
- return 1;
-}
-
-char *cfe_getenv(char *envname)
-{
- if (cfe_found == 0)
- return NULL;
-
- return NULL;
-}
+++ /dev/null
-/*
- * Generic PROM routines
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/string.h>
-
-#include <asm/bootinfo.h>
-
-#include <prom/generic.h>
-
-static int *_prom_argc;
-static char **_prom_argv;
-static char **_prom_envp;
-
-char *generic_prom_getenv(char *envname)
-{
- char **env;
- char *ret;
-
- ret = NULL;
- for (env = _prom_envp; *env != NULL; env++) {
- if (strcmp(envname, *env++) == 0) {
- ret = *env;
- break;
- }
- }
-
- return ret;
-}
-
-int generic_prom_present(void)
-{
- _prom_argc = (int *)fw_arg0;
- _prom_argv = (char **)fw_arg1;
- _prom_envp = (char **)fw_arg2;
-
- return 1;
-}
+++ /dev/null
-/*
- * Compex's MyLoader specific prom routines
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/types.h>
-#include <linux/autoconf.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/string.h>
-
-#include <asm/bootinfo.h>
-#include <asm/addrspace.h>
-#include <asm/byteorder.h>
-
-#include <asm/mach-adm5120/adm5120_defs.h>
-#include <prom/myloader.h>
-#include "prom_read.h"
-
-#define SYS_PARAMS_ADDR KSEG1ADDR(ADM5120_SRAM0_BASE+0x0F000)
-#define BOARD_PARAMS_ADDR KSEG1ADDR(ADM5120_SRAM0_BASE+0x0F800)
-#define PART_TABLE_ADDR KSEG1ADDR(ADM5120_SRAM0_BASE+0x10000)
-
-static int myloader_found;
-
-struct myloader_info myloader_info;
-
-int __init myloader_present(void)
-{
- struct mylo_system_params *sysp;
- struct mylo_board_params *boardp;
- struct mylo_partition_table *parts;
- int i;
-
- if (myloader_found)
- goto out;
-
- sysp = (struct mylo_system_params *)(SYS_PARAMS_ADDR);
- boardp = (struct mylo_board_params *)(BOARD_PARAMS_ADDR);
- parts = (struct mylo_partition_table *)(PART_TABLE_ADDR);
-
- /* Check for some magic numbers */
- if ((le32_to_cpu(sysp->magic) != MYLO_MAGIC_SYS_PARAMS) ||
- (le32_to_cpu(boardp->magic) != MYLO_MAGIC_BOARD_PARAMS) ||
- (le32_to_cpu(parts->magic) != MYLO_MAGIC_PARTITIONS))
- goto out;
-
- myloader_info.vid = le32_to_cpu(sysp->vid);
- myloader_info.did = le32_to_cpu(sysp->did);
- myloader_info.svid = le32_to_cpu(sysp->svid);
- myloader_info.sdid = le32_to_cpu(sysp->sdid);
-
- for (i = 0; i < MYLO_ETHADDR_COUNT; i++) {
- int j;
- for (j = 0; j < 6; j++)
- myloader_info.macs[i][j] = boardp->addr[i].mac[j];
- }
-
- myloader_found = 1;
-
-out:
- return myloader_found;
-}
+++ /dev/null
-/*
- * Generic prom definitions
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#ifndef _ADM5120_PROM_H_
-#define _ADM5120_PROM_H_
-
-/*
- * Helper routines
- */
-static inline u16 prom_read_le16(void *buf)
-{
- u8 *p = buf;
-
- return ((u16)p[0] + ((u16)p[1] << 8));
-}
-
-static inline u32 prom_read_le32(void *buf)
-{
- u8 *p = buf;
-
- return ((u32)p[0] + ((u32)p[1] << 8) + ((u32)p[2] << 16) +
- ((u32)p[3] << 24));
-}
-
-static inline u16 prom_read_be16(void *buf)
-{
- u8 *p = buf;
-
- return (((u16)p[0] << 8) + (u16)p[1]);
-}
-
-static inline u32 prom_read_be32(void *buf)
-{
- u8 *p = buf;
-
- return (((u32)p[0] << 24) + ((u32)p[1] << 16) + ((u32)p[2] << 8) +
- ((u32)p[3]));
-}
-
-#endif /* _ADM5120_PROM_H_ */
-
-
+++ /dev/null
-/*
- * Mikrotik's RouterBOOT specific prom routines
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/types.h>
-#include <linux/autoconf.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/string.h>
-#include <linux/module.h>
-
-#include <asm/bootinfo.h>
-#include <asm/addrspace.h>
-
-#include <asm/mach-adm5120/adm5120_defs.h>
-#include <prom/routerboot.h>
-#include "prom_read.h"
-
-struct rb_hard_settings rb_hs;
-static int rb_found;
-
-static int __init routerboot_load_hs(u8 *buf, u16 buflen)
-{
- u16 id, len;
-
- memset(&rb_hs, 0, sizeof(rb_hs));
-
- if (buflen < 4)
- return -1;
-
- if (prom_read_le32(buf) != RB_MAGIC_HARD)
- return -1;
-
- /* skip magic value */
- buf += 4;
- buflen -= 4;
-
- while (buflen > 2) {
- id = prom_read_le16(buf);
- buf += 2;
- buflen -= 2;
- if (id == RB_ID_TERMINATOR || buflen < 2)
- break;
-
- len = prom_read_le16(buf);
- buf += 2;
- buflen -= 2;
-
- if (buflen < len)
- break;
-
- switch (id) {
- case RB_ID_BIOS_VERSION:
- rb_hs.bios_ver = (char *)buf;
- break;
- case RB_ID_BOARD_NAME:
- rb_hs.name = (char *)buf;
- break;
- case RB_ID_MEMORY_SIZE:
- rb_hs.mem_size = prom_read_le32(buf);
- break;
- case RB_ID_MAC_ADDRESS_COUNT:
- rb_hs.mac_count = prom_read_le32(buf);
- break;
- case RB_ID_MAC_ADDRESS_PACK:
- if ((len / RB_MAC_SIZE) > 0)
- rb_hs.mac_base = buf;
- break;
- }
-
- buf += len;
- buflen -= len;
-
- }
-
- return 0;
-}
-
-#define RB_BS_OFFS 0x14
-#define RB_OFFS_MAX (128*1024)
-
-int __init routerboot_present(void)
-{
- struct rb_bios_settings *bs;
- u8 *base;
- u32 off, len;
-
- if (rb_found)
- goto out;
-
- base = (u8 *)KSEG1ADDR(ADM5120_SRAM0_BASE);
- bs = (struct rb_bios_settings *)(base + RB_BS_OFFS);
-
- off = prom_read_le32(&bs->hs_offs);
- len = prom_read_le32(&bs->hs_size);
- if (off > RB_OFFS_MAX)
- goto out;
-
- if (routerboot_load_hs(base+off, len) != 0)
- goto out;
-
- rb_found = 1;
-
-out:
- return rb_found;
-}
-
-char *routerboot_get_boardname(void)
-{
- if (rb_found == 0)
- return NULL;
-
- return rb_hs.name;
-}
+++ /dev/null
-obj-y += p-33x.o
-
-obj-${CONFIG_ADM5120_MACH_P_334WT} += p-334wt.o
-obj-${CONFIG_ADM5120_MACH_P_335} += p-335.o
\ No newline at end of file
+++ /dev/null
-/*
- * ZyXEL Prestige P-334WT support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "p-33x.h"
-
-static struct gpio_led p334wt_gpio_leds[] __initdata = {
- GPIO_LED_INV(ADM5120_GPIO_PIN2, "power", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P3L0, "lan1", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan2", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan3", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P0L0, "lan4", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P4L0, "wan", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P4L2, "wlan", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P2L2, "otist", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P1L2, "hidden", NULL),
-};
-
-static void __init p334wt_setup(void)
-{
- p33x_generic_setup();
- adm5120_add_device_gpio_leds(ARRAY_SIZE(p334wt_gpio_leds),
- p334wt_gpio_leds);
-}
-
-ADM5120_BOARD(MACH_ADM5120_P334WT, "ZyXEL Prestige 334WT", p334wt_setup);
+++ /dev/null
-/*
- * ZyXEL Prestige P-335/335WT support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "p-33x.h"
-
-static void __init p335_setup(void)
-{
- p33x_generic_setup();
- adm5120_add_device_usb();
-}
-
-ADM5120_BOARD(MACH_ADM5120_P335, "ZyXEL Prestige 335/335WT", p335_setup);
+++ /dev/null
-/*
- * ZyXEL Prestige P-33x boards support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "p-33x.h"
-
-#include <prom/zynos.h>
-
-#define P33X_GPIO_FLASH_A20 ADM5120_GPIO_PIN5
-#define P33X_GPIO_DEV_MASK (1 << P33X_GPIO_FLASH_A20)
-
-#ifdef CONFIG_MTD_PARTITIONS
-static struct mtd_partition p33x_partitions[] = {
- {
- .name = "bootbase",
- .offset = 0,
- .size = 16*1024,
- .mask_flags = MTD_WRITEABLE,
- } , {
- .name = "rom",
- .offset = MTDPART_OFS_APPEND,
- .size = 16*1024,
- } , {
- .name = "bootext",
- .offset = MTDPART_OFS_APPEND,
- .size = 96*1024,
- .mask_flags = MTD_WRITEABLE,
- } , {
- .name = "trx",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- } , {
- .name = "firmware",
- .offset = 32*1024,
- .size = MTDPART_SIZ_FULL,
- }
-};
-#endif /* CONFIG_MTD_PARTITIONS */
-
-static struct adm5120_pci_irq p33x_pci_irqs[] __initdata = {
- PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI0),
-};
-
-static u8 p33x_vlans[6] __initdata = {
- /* FIXME: untested */
- 0x50, 0x48, 0x44, 0x42, 0x41, 0x00
-};
-
-static void switch_bank_gpio5(unsigned bank)
-{
- switch (bank) {
- case 0:
- gpio_set_value(P33X_GPIO_FLASH_A20, 0);
- break;
- case 1:
- gpio_set_value(P33X_GPIO_FLASH_A20, 1);
- break;
- }
-}
-
-void __init p33x_generic_setup(void)
-{
- /* setup data for flash0 device */
- gpio_request(P33X_GPIO_FLASH_A20, NULL); /* for flash A20 line */
- gpio_direction_output(P33X_GPIO_FLASH_A20, 0);
- adm5120_flash0_data.switch_bank = switch_bank_gpio5;
-#ifdef CONFIG_MTD_PARTITIONS
- adm5120_flash0_data.nr_parts = ARRAY_SIZE(p33x_partitions);
- adm5120_flash0_data.parts = p33x_partitions;
-#endif /* CONFIG_MTD_PARTITIONS */
- adm5120_add_device_flash(0);
-
- adm5120_add_device_uart(0);
- adm5120_add_device_uart(1);
-
- adm5120_add_device_gpio(P33X_GPIO_DEV_MASK);
-
- adm5120_setup_eth_macs(bootbase_info.mac);
- adm5120_add_device_switch(5, p33x_vlans);
-
- adm5120_pci_set_irq_map(ARRAY_SIZE(p33x_pci_irqs), p33x_pci_irqs);
-}
+++ /dev/null
-/*
- * ZyXEL Prestige P-33x boards support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/gpio.h>
-#include <linux/irq.h>
-
-#include <asm/bootinfo.h>
-
-#include <asm/mach-adm5120/adm5120_board.h>
-#include <asm/mach-adm5120/adm5120_platform.h>
-
-extern void p33x_generic_setup(void) __init;
+++ /dev/null
-/*
- * ADM5120 PCI Host Controller driver
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This code was based on the ADM5120 specific port of the Linux 2.6.10 kernel
- * done by Jeroen Vreeken
- * Copyright (C) 2005 Jeroen Vreeken (pe1rxq@amsat.org)
- *
- * Jeroen's code was based on the Linux 2.4.xx source codes found in various
- * tarballs released by Edimax for it's ADM5120 based devices
- * Copyright (C) ADMtek Incorporated
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/io.h>
-
-#include <linux/pci.h>
-#include <linux/pci_ids.h>
-#include <linux/pci_regs.h>
-
-#include <asm/delay.h>
-#include <asm/bootinfo.h>
-
-#include <asm/mach-adm5120/adm5120_defs.h>
-#include <asm/mach-adm5120/adm5120_info.h>
-#include <asm/mach-adm5120/adm5120_defs.h>
-#include <asm/mach-adm5120/adm5120_platform.h>
-
-#undef DEBUG
-
-#ifdef DEBUG
-#define DBG(f, a...) printk(KERN_DEBUG f, ## a)
-#else
-#define DBG(f, a...) do {} while (0)
-#endif
-
-#define PCI_ENABLE 0x80000000
-
-/* -------------------------------------------------------------------------*/
-
-static unsigned int adm5120_pci_nr_irqs __initdata;
-static struct adm5120_pci_irq *adm5120_pci_irq_map __initdata;
-
-static spinlock_t pci_lock = SPIN_LOCK_UNLOCKED;
-
-/* -------------------------------------------------------------------------*/
-
-static inline void write_cfgaddr(u32 addr)
-{
- __raw_writel((addr | PCI_ENABLE),
- (void __iomem *)(KSEG1ADDR(ADM5120_PCICFG_ADDR)));
-}
-
-static inline void write_cfgdata(u32 data)
-{
- __raw_writel(data, (void __iomem *)KSEG1ADDR(ADM5120_PCICFG_DATA));
-}
-
-static inline u32 read_cfgdata(void)
-{
- return __raw_readl((void __iomem *)KSEG1ADDR(ADM5120_PCICFG_DATA));
-}
-
-static inline u32 mkaddr(struct pci_bus *bus, unsigned int devfn, int where)
-{
- return (((bus->number & 0xFF) << 16) | ((devfn & 0xFF) << 8) | \
- (where & 0xFC));
-}
-
-/* -------------------------------------------------------------------------*/
-
-static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
- int size, u32 *val)
-{
- unsigned long flags;
- u32 data;
-
- spin_lock_irqsave(&pci_lock, flags);
-
- write_cfgaddr(mkaddr(bus, devfn, where));
- data = read_cfgdata();
-
- DBG("PCI: cfg_read %02u.%02u.%01u/%02X:%01d, cfg:0x%08X",
- bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
- where, size, data);
-
- switch (size) {
- case 1:
- if (where & 1)
- data >>= 8;
- if (where & 2)
- data >>= 16;
- data &= 0xFF;
- break;
- case 2:
- if (where & 2)
- data >>= 16;
- data &= 0xFFFF;
- break;
- }
-
- *val = data;
- DBG(", 0x%08X returned\n", data);
-
- spin_unlock_irqrestore(&pci_lock, flags);
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,
- int size, u32 val)
-{
- unsigned long flags;
- u32 data;
- int s;
-
- spin_lock_irqsave(&pci_lock, flags);
-
- write_cfgaddr(mkaddr(bus, devfn, where));
- data = read_cfgdata();
-
- DBG("PCI: cfg_write %02u.%02u.%01u/%02X:%01d, cfg:0x%08X",
- bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
- where, size, data);
-
- switch (size) {
- case 1:
- s = ((where & 3) << 3);
- data &= ~(0xFF << s);
- data |= ((val & 0xFF) << s);
- break;
- case 2:
- s = ((where & 2) << 4);
- data &= ~(0xFFFF << s);
- data |= ((val & 0xFFFF) << s);
- break;
- case 4:
- data = val;
- break;
- }
-
- write_cfgdata(data);
- DBG(", 0x%08X written\n", data);
-
- spin_unlock_irqrestore(&pci_lock, flags);
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-struct pci_ops adm5120_pci_ops = {
- .read = pci_config_read,
- .write = pci_config_write,
-};
-
-/* -------------------------------------------------------------------------*/
-
-static void adm5120_pci_fixup(struct pci_dev *dev)
-{
- if (dev->devfn != 0)
- return;
-
- /* setup COMMAND register */
- pci_write_config_word(dev, PCI_COMMAND,
- (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
-
- /* setup CACHE_LINE_SIZE register */
- pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 4);
-
- /* setup BARS */
- pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0);
- pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0);
-}
-
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADMTEK, PCI_DEVICE_ID_ADMTEK_ADM5120,
- adm5120_pci_fixup);
-
-/* -------------------------------------------------------------------------*/
-
-void __init adm5120_pci_set_irq_map(unsigned int nr_irqs,
- struct adm5120_pci_irq *map)
-{
- adm5120_pci_nr_irqs = nr_irqs;
- adm5120_pci_irq_map = map;
-}
-
-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- int irq = -1;
- int i;
-
- if ((!adm5120_pci_nr_irqs) || (!adm5120_pci_irq_map)) {
- printk(KERN_ALERT "PCI: pci_irq_map is not initialized\n");
- goto out;
- }
-
- if (slot < 1 || slot > 3) {
- printk(KERN_ALERT "PCI: slot number %u is not supported\n",
- slot);
- goto out;
- }
-
- for (i = 0; i < adm5120_pci_nr_irqs; i++) {
- if ((adm5120_pci_irq_map[i].slot == slot)
- && (adm5120_pci_irq_map[i].func == PCI_FUNC(dev->devfn))
- && (adm5120_pci_irq_map[i].pin == pin)) {
- irq = adm5120_pci_irq_map[i].irq;
- break;
- }
- }
-
- if (irq < 0) {
- printk(KERN_ALERT "PCI: no irq found for %s pin:%u\n",
- pci_name((struct pci_dev *)dev), pin);
- } else {
- printk(KERN_INFO "PCI: mapping irq for %s pin:%u, irq:%d\n",
- pci_name((struct pci_dev *)dev), pin, irq);
- }
-
-out:
- return irq;
-}
-
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
- return 0;
-}
-
-/* -------------------------------------------------------------------------*/
-
-static struct resource pci_io_resource = {
- .name = "ADM5120 PCI I/O",
- .start = ADM5120_PCIIO_BASE,
- .end = ADM5120_PCICFG_ADDR-1,
- .flags = IORESOURCE_IO
-};
-
-static struct resource pci_mem_resource = {
- .name = "ADM5120 PCI MEM",
- .start = ADM5120_PCIMEM_BASE,
- .end = ADM5120_PCIIO_BASE-1,
- .flags = IORESOURCE_MEM
-};
-
-static struct pci_controller adm5120_controller = {
- .pci_ops = &adm5120_pci_ops,
- .io_resource = &pci_io_resource,
- .mem_resource = &pci_mem_resource,
-};
-
-static int __init adm5120_pci_setup(void)
-{
- if (adm5120_package_pqfp()) {
- printk(KERN_INFO "PCI: not available on ADM5120P\n");
- return -1;
- }
-
- /* Avoid ISA compat ranges. */
- PCIBIOS_MIN_IO = 0x00000000;
- PCIBIOS_MIN_MEM = 0x00000000;
-
- /* Set I/O resource limits. */
- ioport_resource.end = 0x1fffffff;
- iomem_resource.end = 0xffffffff;
-
- register_pci_controller(&adm5120_controller);
- return 0;
-}
-
-arch_initcall(adm5120_pci_setup);
+++ /dev/null
-/*
- * A low-level PATA driver to handle a Compact Flash connected on the
- * Mikrotik's RouterBoard 153 board.
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This file was based on: drivers/ata/pata_ixp4xx_cf.c
- * Copyright (C) 2006-07 Tower Technologies
- * Author: Alessandro Zummo <a.zummo@towertech.it>
- *
- * Also was based on the driver for Linux 2.4.xx published by Mikrotik for
- * their RouterBoard 1xx and 5xx series devices. The original Mikrotik code
- * seems not to have a license.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/io.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <linux/platform_device.h>
-
-#include <linux/libata.h>
-#include <scsi/scsi_host.h>
-
-#define DRV_NAME "pata-rb153-cf"
-#define DRV_VERSION "0.5.0"
-#define DRV_DESC "PATA driver for RouterBOARD 153 Compact Flash"
-
-#define RB153_CF_MAXPORTS 1
-#define RB153_CF_IO_DELAY 100
-
-#define RB153_CF_REG_CMD 0x0800
-#define RB153_CF_REG_CTRL 0x080E
-#define RB153_CF_REG_DATA 0x0C00
-
-struct rb153_cf_info {
- void __iomem *iobase;
- unsigned int gpio_line;
- int frozen;
- unsigned int irq;
-};
-
-static inline void rb153_pata_finish_io(struct ata_port *ap)
-{
- struct rb153_cf_info *info = ap->host->private_data;
-
- /* FIXME: Keep previous delay. If this is merely a fence then
- * ata_sff_sync might be sufficient. */
- ata_sff_dma_pause(ap);
- ndelay(RB153_CF_IO_DELAY);
-
- set_irq_type(info->irq, IRQ_TYPE_LEVEL_HIGH);
-}
-
-static void rb153_pata_exec_command(struct ata_port *ap,
- const struct ata_taskfile *tf)
-{
- writeb(tf->command, ap->ioaddr.command_addr);
- rb153_pata_finish_io(ap);
-}
-
-static unsigned int rb153_pata_data_xfer(struct ata_device *adev,
- unsigned char *buf,
- unsigned int buflen,
- int write_data)
-{
- void __iomem *ioaddr = adev->link->ap->ioaddr.data_addr;
- unsigned int t;
-
- t = buflen;
- if (write_data) {
- for (; t > 0; t--, buf++)
- writeb(*buf, ioaddr);
- } else {
- for (; t > 0; t--, buf++)
- *buf = readb(ioaddr);
- }
-
- rb153_pata_finish_io(adev->link->ap);
- return buflen;
-}
-
-static void rb153_pata_freeze(struct ata_port *ap)
-{
- struct rb153_cf_info *info = ap->host->private_data;
-
- info->frozen = 1;
-}
-
-static void rb153_pata_thaw(struct ata_port *ap)
-{
- struct rb153_cf_info *info = ap->host->private_data;
-
- info->frozen = 0;
-}
-
-static irqreturn_t rb153_pata_irq_handler(int irq, void *dev_instance)
-{
- struct ata_host *ah = dev_instance;
- struct rb153_cf_info *info = ah->private_data;
-
- if (gpio_get_value(info->gpio_line)) {
- set_irq_type(info->irq, IRQ_TYPE_LEVEL_LOW);
- if (!info->frozen)
- ata_sff_interrupt(irq, dev_instance);
- } else {
- set_irq_type(info->irq, IRQ_TYPE_LEVEL_HIGH);
- }
-
- return IRQ_HANDLED;
-}
-
-static struct ata_port_operations rb153_pata_port_ops = {
- .inherits = &ata_sff_port_ops,
- .sff_exec_command = rb153_pata_exec_command,
- .sff_data_xfer = rb153_pata_data_xfer,
- .freeze = rb153_pata_freeze,
- .thaw = rb153_pata_thaw,
-};
-
-static struct scsi_host_template rb153_pata_sht = {
- ATA_PIO_SHT(DRV_NAME),
-};
-
-static void rb153_pata_setup_port(struct ata_host *ah)
-{
- struct rb153_cf_info *info = ah->private_data;
- struct ata_port *ap;
-
- ap = ah->ports[0];
-
- ap->ops = &rb153_pata_port_ops;
- ap->pio_mask = 0x1f; /* PIO4 */
- ap->flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO;
-
- ap->ioaddr.cmd_addr = info->iobase + RB153_CF_REG_CMD;
- ap->ioaddr.ctl_addr = info->iobase + RB153_CF_REG_CTRL;
- ap->ioaddr.altstatus_addr = info->iobase + RB153_CF_REG_CTRL;
-
- ata_sff_std_ports(&ap->ioaddr);
-
- ap->ioaddr.data_addr = info->iobase + RB153_CF_REG_DATA;
-}
-
-static __devinit int rb153_pata_driver_probe(struct platform_device *pdev)
-{
- unsigned int irq;
- int gpio;
- struct resource *res;
- struct ata_host *ah;
- struct rb153_cf_info *info;
- int ret;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!res) {
- dev_err(&pdev->dev, "no IOMEM resource found\n");
- return -EINVAL;
- }
-
- irq = platform_get_irq(pdev, 0);
- if (irq <= 0) {
- dev_err(&pdev->dev, "no IRQ resource found\n");
- return -ENOENT;
- }
-
- gpio = irq_to_gpio(irq);
- if (gpio < 0) {
- dev_err(&pdev->dev, "no GPIO found for irq%d\n", irq);
- return -ENOENT;
- }
-
- ret = gpio_request(gpio, DRV_NAME);
- if (ret) {
- dev_err(&pdev->dev, "GPIO request failed\n");
- return ret;
- }
-
- ah = ata_host_alloc(&pdev->dev, RB153_CF_MAXPORTS);
- if (!ah)
- return -ENOMEM;
-
- platform_set_drvdata(pdev, ah);
-
- info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
- if (!info)
- return -ENOMEM;
-
- ah->private_data = info;
- info->gpio_line = gpio;
- info->irq = irq;
-
- info->iobase = devm_ioremap_nocache(&pdev->dev, res->start,
- res->end - res->start + 1);
- if (!info->iobase)
- return -ENOMEM;
-
- ret = gpio_direction_input(gpio);
- if (ret) {
- dev_err(&pdev->dev, "unable to set GPIO direction, err=%d\n",
- ret);
- goto err_free_gpio;
- }
-
- rb153_pata_setup_port(ah);
-
- ret = ata_host_activate(ah, irq, rb153_pata_irq_handler,
- IRQF_TRIGGER_LOW, &rb153_pata_sht);
- if (ret)
- goto err_free_gpio;
-
- return 0;
-
-err_free_gpio:
- gpio_free(gpio);
-
- return ret;
-}
-
-static __devexit int rb153_pata_driver_remove(struct platform_device *pdev)
-{
- struct ata_host *ah = platform_get_drvdata(pdev);
- struct rb153_cf_info *info = ah->private_data;
-
- ata_host_detach(ah);
- gpio_free(info->gpio_line);
-
- return 0;
-}
-
-static struct platform_driver rb153_pata_platform_driver = {
- .probe = rb153_pata_driver_probe,
- .remove = __devexit_p(rb153_pata_driver_remove),
- .driver = {
- .name = DRV_NAME,
- .owner = THIS_MODULE,
- },
-};
-
-/* ------------------------------------------------------------------------ */
-
-#define DRV_INFO DRV_DESC " version " DRV_VERSION
-
-static int __init rb153_pata_module_init(void)
-{
- printk(KERN_INFO DRV_INFO "\n");
-
- return platform_driver_register(&rb153_pata_platform_driver);
-}
-
-static void __exit rb153_pata_module_exit(void)
-{
- platform_driver_unregister(&rb153_pata_platform_driver);
-}
-
-MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
-MODULE_DESCRIPTION(DRV_DESC);
-MODULE_VERSION(DRV_VERSION);
-MODULE_LICENSE("GPL v2");
-
-module_init(rb153_pata_module_init);
-module_exit(rb153_pata_module_exit);
+++ /dev/null
-/*
- * LED ADM5120 Switch Port State Trigger
- *
- * Copyright (C) 2007 Bernhard Held <bernhard at bernhardheld.de>
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This file was based on: drivers/leds/ledtrig-timer.c
- * Copyright 2005-2006 Openedhand Ltd.
- * Author: Richard Purdie
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/device.h>
-
-#include <linux/gpio.h>
-
-#include "leds.h"
-
-#define DRV_NAME "port_state"
-#define DRV_DESC "LED ADM5120 Switch Port State Trigger"
-
-struct port_state {
- char *name;
- unsigned int value;
-};
-
-#define PORT_STATE(n,v) {.name = (n), .value = (v)}
-
-static struct port_state port_states[] = {
- PORT_STATE("off", LED_OFF),
- PORT_STATE("on", LED_FULL),
- PORT_STATE("flash", ADM5120_GPIO_FLASH),
- PORT_STATE("link", ADM5120_GPIO_LINK),
- PORT_STATE("speed", ADM5120_GPIO_SPEED),
- PORT_STATE("duplex", ADM5120_GPIO_DUPLEX),
- PORT_STATE("act", ADM5120_GPIO_ACT),
- PORT_STATE("coll", ADM5120_GPIO_COLL),
- PORT_STATE("link_act", ADM5120_GPIO_LINK_ACT),
- PORT_STATE("duplex_coll", ADM5120_GPIO_DUPLEX_COLL),
- PORT_STATE("10M_act", ADM5120_GPIO_10M_ACT),
- PORT_STATE("100M_act", ADM5120_GPIO_100M_ACT),
-};
-
-static ssize_t led_port_state_show(struct device *dev,
- struct device_attribute *attr, char *buf)
-{
- struct led_classdev *led_cdev = dev_get_drvdata(dev);
- struct port_state *state = led_cdev->trigger_data;
- int len = 0;
- int i;
-
- *buf = '\0';
- for (i = 0; i < ARRAY_SIZE(port_states); i++) {
- if (&port_states[i] == state)
- len += sprintf(buf+len, "[%s] ", port_states[i].name);
- else
- len += sprintf(buf+len, "%s ", port_states[i].name);
- }
- len += sprintf(buf+len, "\n");
-
- return len;
-}
-
-static ssize_t led_port_state_store(struct device *dev,
- struct device_attribute *attr, const char *buf, size_t size)
-{
- struct led_classdev *led_cdev = dev_get_drvdata(dev);
- size_t len;
- int i;
-
- for (i = 0; i < ARRAY_SIZE(port_states); i++) {
- len = strlen(port_states[i].name);
- if (strncmp(port_states[i].name, buf, len) != 0)
- continue;
-
- if (buf[len] != '\0' && buf[len] != '\n')
- continue;
-
- led_cdev->trigger_data = &port_states[i];
- led_set_brightness(led_cdev, port_states[i].value);
- return size;
- }
-
- return -EINVAL;
-}
-
-static DEVICE_ATTR(port_state, 0644, led_port_state_show,
- led_port_state_store);
-
-static void adm5120_switch_trig_activate(struct led_classdev *led_cdev)
-{
- struct port_state *state = port_states;
- int rc;
-
- led_cdev->trigger_data = state;
-
- rc = device_create_file(led_cdev->dev, &dev_attr_port_state);
- if (rc)
- goto err;
-
- led_set_brightness(led_cdev, state->value);
-
- return;
-err:
- led_cdev->trigger_data = NULL;
-}
-
-static void adm5120_switch_trig_deactivate(struct led_classdev *led_cdev)
-{
- struct port_state *state = led_cdev->trigger_data;
-
- if (!state)
- return;
-
- device_remove_file(led_cdev->dev, &dev_attr_port_state);
-
-}
-
-static struct led_trigger adm5120_switch_led_trigger = {
- .name = DRV_NAME,
- .activate = adm5120_switch_trig_activate,
- .deactivate = adm5120_switch_trig_deactivate,
-};
-
-static int __init adm5120_switch_trig_init(void)
-{
- led_trigger_register(&adm5120_switch_led_trigger);
- return 0;
-}
-
-static void __exit adm5120_switch_trig_exit(void)
-{
- led_trigger_unregister(&adm5120_switch_led_trigger);
-}
-
-module_init(adm5120_switch_trig_init);
-module_exit(adm5120_switch_trig_exit);
-
-MODULE_AUTHOR("Bernhard Held <bernhard at bernhardheld.de>, "
- "Gabor Juhos <juhosg@openwrt.org>");
-MODULE_DESCRIPTION(DRV_DESC);
-MODULE_LICENSE("GPL v2");
+++ /dev/null
-/*
- * Platform driver for NOR flash devices on ADM5120 based boards
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This file was derived from: drivers/mtd/map/physmap.c
- * Copyright (C) 2003 MontaVista Software Inc.
- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/slab.h>
-#include <linux/io.h>
-#include <linux/device.h>
-#include <linux/platform_device.h>
-
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/map.h>
-#include <linux/mtd/partitions.h>
-
-#include <asm/mach-adm5120/adm5120_defs.h>
-#include <asm/mach-adm5120/adm5120_switch.h>
-#include <asm/mach-adm5120/adm5120_mpmc.h>
-#include <asm/mach-adm5120/adm5120_platform.h>
-
-#define DRV_NAME "adm5120-flash"
-#define DRV_DESC "ADM5120 flash MAP driver"
-#define MAX_PARSED_PARTS 8
-
-#ifdef ADM5120_FLASH_DEBUG
-#define MAP_DBG(m, f, a...) printk(KERN_INFO "%s: " f, (m->name) , ## a)
-#else
-#define MAP_DBG(m, f, a...) do {} while (0)
-#endif
-#define MAP_ERR(m, f, a...) printk(KERN_ERR "%s: " f, (m->name) , ## a)
-#define MAP_INFO(m, f, a...) printk(KERN_INFO "%s: " f, (m->name) , ## a)
-
-struct adm5120_map_info {
- struct map_info map;
- void (*switch_bank)(unsigned);
- unsigned long window_size;
-};
-
-struct adm5120_flash_info {
- struct mtd_info *mtd;
- struct resource *res;
- struct platform_device *dev;
- struct adm5120_map_info amap;
-#ifdef CONFIG_MTD_PARTITIONS
- int nr_parts;
- struct mtd_partition *parts[MAX_PARSED_PARTS];
-#endif
-};
-
-struct flash_desc {
- u32 phys;
- u32 srs_shift;
-};
-
-/*
- * Globals
- */
-static DEFINE_SPINLOCK(adm5120_flash_spin);
-#define FLASH_LOCK() spin_lock(&adm5120_flash_spin)
-#define FLASH_UNLOCK() spin_unlock(&adm5120_flash_spin)
-
-static u32 flash_bankwidths[4] = { 1, 2, 4, 0 };
-
-static u32 flash_sizes[8] = {
- 0, 512*1024, 1024*1024, 2*1024*1024,
- 4*1024*1024, 0, 0, 0
-};
-
-static struct flash_desc flash_descs[2] = {
- {
- .phys = ADM5120_SRAM0_BASE,
- .srs_shift = MEMCTRL_SRS0_SHIFT,
- }, {
- .phys = ADM5120_SRAM1_BASE,
- .srs_shift = MEMCTRL_SRS1_SHIFT,
- }
-};
-
-static const char *probe_types[] = {
- "cfi_probe",
- "jedec_probe",
- "map_rom",
- NULL
-};
-
-#ifdef CONFIG_MTD_PARTITIONS
-static const char *parse_types[] = {
- "cmdlinepart",
-#ifdef CONFIG_MTD_REDBOOT_PARTS
- "RedBoot",
-#endif
-#ifdef CONFIG_MTD_MYLOADER_PARTS
- "MyLoader",
-#endif
-};
-#endif
-
-#define BANK_SIZE (2<<20)
-#define BANK_SIZE_MAX (4<<20)
-#define BANK_OFFS_MASK (BANK_SIZE-1)
-#define BANK_START_MASK (~BANK_OFFS_MASK)
-
-static inline struct adm5120_map_info *map_to_amap(struct map_info *map)
-{
- return (struct adm5120_map_info *)map;
-}
-
-static void adm5120_flash_switchbank(struct map_info *map,
- unsigned long ofs)
-{
- struct adm5120_map_info *amap = map_to_amap(map);
- unsigned bank;
-
- if (amap->switch_bank == NULL)
- return;
-
- bank = (ofs & BANK_START_MASK) >> 21;
- if (bank > 1)
- BUG();
-
- MAP_DBG(map, "switching to bank %u, ofs=%lX\n", bank, ofs);
- amap->switch_bank(bank);
-}
-
-static map_word adm5120_flash_read(struct map_info *map, unsigned long ofs)
-{
- struct adm5120_map_info *amap = map_to_amap(map);
- map_word ret;
-
- MAP_DBG(map, "reading from ofs %lX\n", ofs);
-
- if (ofs >= amap->window_size)
- return map_word_ff(map);
-
- FLASH_LOCK();
- adm5120_flash_switchbank(map, ofs);
- ret = inline_map_read(map, (ofs & (amap->window_size-1)));
- FLASH_UNLOCK();
-
- return ret;
-}
-
-static void adm5120_flash_write(struct map_info *map, const map_word datum,
- unsigned long ofs)
-{
- struct adm5120_map_info *amap = map_to_amap(map);
-
- MAP_DBG(map, "writing to ofs %lX\n", ofs);
-
- if (ofs > amap->window_size)
- return;
-
- FLASH_LOCK();
- adm5120_flash_switchbank(map, ofs);
- inline_map_write(map, datum, (ofs & (amap->window_size-1)));
- FLASH_UNLOCK();
-}
-
-static void adm5120_flash_copy_from(struct map_info *map, void *to,
- unsigned long from, ssize_t len)
-{
- struct adm5120_map_info *amap = map_to_amap(map);
- char *p;
- ssize_t t;
-
- MAP_DBG(map, "copy_from, to=%lX, from=%lX, len=%lX\n",
- (unsigned long)to, from, (unsigned long)len);
-
- if (from > amap->window_size)
- return;
-
- p = (char *)to;
- while (len > 0) {
- t = len;
- if ((from < BANK_SIZE) && ((from+len) > BANK_SIZE))
- t = BANK_SIZE-from;
-
- FLASH_LOCK();
- MAP_DBG(map, "copying %lu byte(s) from %lX to %lX\n",
- (unsigned long)t, (from & (amap->window_size-1)),
- (unsigned long)p);
- adm5120_flash_switchbank(map, from);
- inline_map_copy_from(map, p, (from & (amap->window_size-1)), t);
- FLASH_UNLOCK();
- p += t;
- from += t;
- len -= t;
- }
-}
-
-static int adm5120_flash_initres(struct adm5120_flash_info *info)
-{
- struct map_info *map = &info->amap.map;
- int err = 0;
-
- info->res = request_mem_region(map->phys, info->amap.window_size,
- map->name);
- if (info->res == NULL) {
- MAP_ERR(map, "could not reserve memory region\n");
- err = -ENOMEM;
- goto out;
- }
-
- map->virt = ioremap_nocache(map->phys, info->amap.window_size);
- if (map->virt == NULL) {
- MAP_ERR(map, "failed to ioremap flash region\n");
- err = -ENOMEM;
- goto out;
- }
-
-out:
- return err;
-}
-
-static int adm5120_flash_initinfo(struct adm5120_flash_info *info,
- struct platform_device *dev)
-{
- struct map_info *map = &info->amap.map;
- struct adm5120_flash_platform_data *pdata = dev->dev.platform_data;
- struct flash_desc *fdesc;
- u32 t = 0;
-
- map->name = dev->dev.bus_id;
-
- if (dev->id > 1) {
- MAP_ERR(map, "invalid flash id\n");
- goto err_out;
- }
-
- fdesc = &flash_descs[dev->id];
-
- if (pdata)
- info->amap.window_size = pdata->window_size;
-
- if (info->amap.window_size == 0) {
- /* get memory window size */
- t = SW_READ_REG(SWITCH_REG_MEMCTRL) >> fdesc->srs_shift;
- t &= MEMCTRL_SRS_MASK;
- info->amap.window_size = flash_sizes[t];
- }
-
- if (info->amap.window_size == 0) {
- MAP_ERR(map, "unable to determine window size\n");
- goto err_out;
- }
-
- /* get flash bus width */
- switch (dev->id) {
- case 0:
- t = MPMC_READ_REG(SC1) & SC_MW_MASK;
- break;
- case 1:
- t = MPMC_READ_REG(SC0) & SC_MW_MASK;
- break;
- }
- map->bankwidth = flash_bankwidths[t];
- if (map->bankwidth == 0) {
- MAP_ERR(map, "invalid bus width detected\n");
- goto err_out;
- }
-
- map->phys = fdesc->phys;
- map->size = BANK_SIZE_MAX;
-
- simple_map_init(map);
- map->read = adm5120_flash_read;
- map->write = adm5120_flash_write;
- map->copy_from = adm5120_flash_copy_from;
-
- if (pdata) {
- map->set_vpp = pdata->set_vpp;
- info->amap.switch_bank = pdata->switch_bank;
- }
-
- info->dev = dev;
-
- MAP_INFO(map, "probing at 0x%lX, size:%ldKiB, width:%d bits\n",
- (unsigned long)map->phys,
- (unsigned long)info->amap.window_size >> 10,
- map->bankwidth*8);
-
- return 0;
-
-err_out:
- return -ENODEV;
-}
-
-static void adm5120_flash_initbanks(struct adm5120_flash_info *info)
-{
- struct map_info *map = &info->amap.map;
-
- if (info->mtd->size <= BANK_SIZE)
- /* no bank switching needed */
- return;
-
- if (info->amap.switch_bank) {
- info->amap.window_size = info->mtd->size;
- return;
- }
-
- MAP_ERR(map, "reduce visibility from %ldKiB to %ldKiB\n",
- (unsigned long)map->size >> 10,
- (unsigned long)info->mtd->size >> 10);
-
- info->mtd->size = info->amap.window_size;
-}
-
-#ifdef CONFIG_MTD_PARTITIONS
-static int adm5120_flash_initparts(struct adm5120_flash_info *info)
-{
- struct adm5120_flash_platform_data *pdata;
- struct map_info *map = &info->amap.map;
- int num_parsers;
- const char *parser[2];
- int err = 0;
- int nr_parts;
- int i;
-
- info->nr_parts = 0;
-
- pdata = info->dev->dev.platform_data;
- if (pdata == NULL)
- goto out;
-
- if (pdata->nr_parts) {
- MAP_INFO(map, "adding static partitions\n");
- err = add_mtd_partitions(info->mtd, pdata->parts,
- pdata->nr_parts);
- if (err == 0) {
- info->nr_parts += pdata->nr_parts;
- goto out;
- }
- }
-
- num_parsers = ARRAY_SIZE(parse_types);
- if (num_parsers > MAX_PARSED_PARTS)
- num_parsers = MAX_PARSED_PARTS;
-
- parser[1] = NULL;
- for (i = 0; i < num_parsers; i++) {
- parser[0] = parse_types[i];
-
- MAP_INFO(map, "parsing \"%s\" partitions\n",
- parser[0]);
- nr_parts = parse_mtd_partitions(info->mtd, parser,
- &info->parts[i], 0);
-
- if (nr_parts <= 0)
- continue;
-
- MAP_INFO(map, "adding \"%s\" partitions\n",
- parser[0]);
-
- err = add_mtd_partitions(info->mtd, info->parts[i], nr_parts);
- if (err)
- break;
-
- info->nr_parts += nr_parts;
- }
-out:
- return err;
-}
-#else
-static int adm5120_flash_initparts(struct adm5120_flash_info *info)
-{
- return 0;
-}
-#endif /* CONFIG_MTD_PARTITIONS */
-
-#ifdef CONFIG_MTD_PARTITIONS
-static void adm5120_flash_remove_mtd(struct adm5120_flash_info *info)
-{
- int i;
-
- if (info->nr_parts) {
- del_mtd_partitions(info->mtd);
- for (i = 0; i < MAX_PARSED_PARTS; i++)
- if (info->parts[i] != NULL)
- kfree(info->parts[i]);
- } else {
- del_mtd_device(info->mtd);
- }
-}
-#else
-static void adm5120_flash_remove_mtd(struct adm5120_flash_info *info)
-{
- del_mtd_device(info->mtd);
-}
-#endif
-
-static int adm5120_flash_remove(struct platform_device *dev)
-{
- struct adm5120_flash_info *info;
-
- info = platform_get_drvdata(dev);
- if (info == NULL)
- return 0;
-
- platform_set_drvdata(dev, NULL);
-
- if (info->mtd != NULL) {
- adm5120_flash_remove_mtd(info);
- map_destroy(info->mtd);
- }
-
- if (info->amap.map.virt != NULL)
- iounmap(info->amap.map.virt);
-
- if (info->res != NULL) {
- release_resource(info->res);
- kfree(info->res);
- }
-
- return 0;
-}
-
-static int adm5120_flash_probe(struct platform_device *dev)
-{
- struct adm5120_flash_info *info;
- struct map_info *map;
- const char **probe_type;
- int err;
-
- info = kzalloc(sizeof(*info), GFP_KERNEL);
- if (info == NULL) {
- err = -ENOMEM;
- goto err_out;
- }
-
- platform_set_drvdata(dev, info);
-
- err = adm5120_flash_initinfo(info, dev);
- if (err)
- goto err_out;
-
- err = adm5120_flash_initres(info);
- if (err)
- goto err_out;
-
- map = &info->amap.map;
- for (probe_type = probe_types; info->mtd == NULL && *probe_type != NULL;
- probe_type++)
- info->mtd = do_map_probe(*probe_type, map);
-
- if (info->mtd == NULL) {
- MAP_ERR(map, "map_probe failed\n");
- err = -ENXIO;
- goto err_out;
- }
-
- adm5120_flash_initbanks(info);
-
- if (info->mtd->size < info->amap.window_size) {
- /* readjust resources */
- iounmap(map->virt);
- release_resource(info->res);
- kfree(info->res);
-
- info->amap.window_size = info->mtd->size;
- map->size = info->mtd->size;
- MAP_INFO(map, "reducing map size to %ldKiB\n",
- (unsigned long)map->size >> 10);
- err = adm5120_flash_initres(info);
- if (err)
- goto err_out;
- }
-
- MAP_INFO(map, "found at 0x%lX, size:%ldKiB, width:%d bits\n",
- (unsigned long)map->phys, (unsigned long)info->mtd->size >> 10,
- map->bankwidth*8);
-
- info->mtd->owner = THIS_MODULE;
-
- err = adm5120_flash_initparts(info);
- if (err)
- goto err_out;
-
- if (info->nr_parts == 0) {
- MAP_INFO(map, "no partitions available, registering "
- "whole flash\n");
- add_mtd_device(info->mtd);
- }
-
- return 0;
-
-err_out:
- adm5120_flash_remove(dev);
- return err;
-}
-
-#ifdef CONFIG_PM
-static int adm5120_flash_suspend(struct platform_device *dev,
- pm_message_t state)
-{
- struct adm5120_flash_info *info = platform_get_drvdata(dev);
- int ret = 0;
-
- if (info)
- ret = info->mtd->suspend(info->mtd);
-
- return ret;
-}
-
-static int adm5120_flash_resume(struct platform_device *dev)
-{
- struct adm5120_flash_info *info = platform_get_drvdata(dev);
-
- if (info)
- info->mtd->resume(info->mtd);
-
- return 0;
-}
-
-static void adm5120_flash_shutdown(struct platform_device *dev)
-{
- struct adm5120_flash_info *info = platform_get_drvdata(dev);
-
- if (info && info->mtd->suspend(info->mtd) == 0)
- info->mtd->resume(info->mtd);
-}
-#endif
-
-static struct platform_driver adm5120_flash_driver = {
- .probe = adm5120_flash_probe,
- .remove = adm5120_flash_remove,
-#ifdef CONFIG_PM
- .suspend = adm5120_flash_suspend,
- .resume = adm5120_flash_resume,
- .shutdown = adm5120_flash_shutdown,
-#endif
- .driver = {
- .name = DRV_NAME,
- },
-};
-
-static int __init adm5120_flash_init(void)
-{
- int err;
-
- err = platform_driver_register(&adm5120_flash_driver);
-
- return err;
-}
-
-static void __exit adm5120_flash_exit(void)
-{
- platform_driver_unregister(&adm5120_flash_driver);
-}
-
-module_init(adm5120_flash_init);
-module_exit(adm5120_flash_exit);
-
-MODULE_LICENSE("GPL v2");
-MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
-MODULE_DESCRIPTION(DRV_DESC);
+++ /dev/null
-/*
- * Parse MyLoader-style flash partition tables and produce a Linux partition
- * array to match.
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This file was based on drivers/mtd/redboot.c
- * Author: Red Hat, Inc. - David Woodhouse <dwmw2@cambridge.redhat.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/init.h>
-#include <linux/vmalloc.h>
-
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-
-#include <linux/byteorder/generic.h>
-
-#include <prom/myloader.h>
-
-#define NAME_LEN_MAX 20
-#define NAME_MYLOADER "MyLoader"
-#define NAME_PARTITION_TABLE "Partition Table"
-#define BLOCK_LEN_MIN 0x10000
-
-int parse_myloader_partitions(struct mtd_info *master,
- struct mtd_partition **pparts,
- unsigned long origin)
-{
- struct mylo_partition_table *tab;
- struct mylo_partition *part;
- struct mtd_partition *mtd_parts;
- struct mtd_partition *mtd_part;
- int num_parts;
- int ret, i;
- size_t retlen;
- char *names;
- unsigned long offset;
- unsigned long blocklen;
-
- tab = vmalloc(sizeof(*tab));
- if (!tab) {
- return -ENOMEM;
- goto out;
- }
-
- blocklen = master->erasesize;
- if (blocklen < BLOCK_LEN_MIN)
- blocklen = BLOCK_LEN_MIN;
-
- /* Partition Table is always located on the second erase block */
- offset = blocklen;
- printk(KERN_NOTICE "%s: searching for MyLoader partition table at "
- "offset 0x%lx\n", master->name, offset);
-
- ret = master->read(master, offset, sizeof(*tab), &retlen, (void *)tab);
- if (ret)
- goto out;
-
- if (retlen != sizeof(*tab)) {
- ret = -EIO;
- goto out_free_buf;
- }
-
- /* Check for Partition Table magic number */
- if (tab->magic != le32_to_cpu(MYLO_MAGIC_PARTITIONS)) {
- printk(KERN_NOTICE "%s: no MyLoader partition table found\n",
- master->name);
- ret = 0;
- goto out_free_buf;
- }
-
- /* The MyLoader and the Partition Table is always present */
- num_parts = 2;
-
- /* Detect number of used partitions */
- for (i = 0; i < MYLO_MAX_PARTITIONS; i++) {
- part = &tab->partitions[i];
-
- if (le16_to_cpu(part->type) == PARTITION_TYPE_FREE)
- continue;
-
- num_parts++;
- }
-
- mtd_parts = kzalloc((num_parts * sizeof(*mtd_part) +
- num_parts * NAME_LEN_MAX), GFP_KERNEL);
-
- if (!mtd_parts) {
- ret = -ENOMEM;
- goto out_free_buf;
- }
-
- mtd_part = mtd_parts;
- names = (char *)&mtd_parts[num_parts];
-
- strncpy(names, NAME_MYLOADER, NAME_LEN_MAX-1);
- mtd_part->name = names;
- mtd_part->offset = 0;
- mtd_part->size = blocklen;
- mtd_part->mask_flags = MTD_WRITEABLE;
- mtd_part++;
- names += NAME_LEN_MAX;
-
- strncpy(names, NAME_PARTITION_TABLE, NAME_LEN_MAX-1);
- mtd_part->name = names;
- mtd_part->offset = blocklen;
- mtd_part->size = blocklen;
- mtd_part->mask_flags = MTD_WRITEABLE;
- mtd_part++;
- names += NAME_LEN_MAX;
-
- for (i = 0; i < MYLO_MAX_PARTITIONS; i++) {
- part = &tab->partitions[i];
-
- if (le16_to_cpu(part->type) == PARTITION_TYPE_FREE)
- continue;
-
- sprintf(names, "partition%d", i);
- mtd_part->offset = le32_to_cpu(part->addr);
- mtd_part->size = le32_to_cpu(part->size);
- mtd_part->name = names;
- mtd_part++;
- names += NAME_LEN_MAX;
- }
-
- *pparts = mtd_parts;
- ret = num_parts;
-
-out_free_buf:
- vfree(tab);
-out:
- return ret;
-}
-
-static struct mtd_part_parser mylo_mtd_parser = {
- .owner = THIS_MODULE,
- .parse_fn = parse_myloader_partitions,
- .name = NAME_MYLOADER,
-};
-
-static int __init mylo_mtd_parser_init(void)
-{
- return register_mtd_parser(&mylo_mtd_parser);
-}
-
-static void __exit mylo_mtd_parser_exit(void)
-{
- deregister_mtd_parser(&mylo_mtd_parser);
-}
-
-module_init(mylo_mtd_parser_init);
-module_exit(mylo_mtd_parser_exit);
-
-MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
-MODULE_DESCRIPTION("Parsing code for MyLoader partition tables");
-MODULE_LICENSE("GPL v2");
+++ /dev/null
-/*
- * Copyright (C) Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/list.h>
-#include <linux/kmod.h>
-#include <linux/root_dev.h>
-
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-
-#include <linux/byteorder/generic.h>
-
-#define PFX "trxsplit: "
-
-#define TRX_MAGIC 0x30524448 /* "HDR0" */
-#define TRX_VERSION 1
-#define TRX_MAX_LEN 0x3A0000
-#define TRX_NO_HEADER 0x1 /* do not write TRX header */
-#define TRX_GZ_FILES 0x2 /* contains individual gzip files */
-#define TRX_MAX_OFFSET 3
-#define TRX_MIN_KERNEL_SIZE 256*1024
-
-struct trx_header {
- u32 magic; /* "HDR0" */
- u32 len; /* Length of file including header */
- u32 crc32; /* 32-bit CRC from flag_version to end of file */
- u32 flag_version; /* 0:15 flags, 16:31 version */
- u32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions */
-};
-
-#define TRX_ALIGN 0x1000
-
-static int trx_nr_parts;
-static unsigned long trx_offset;
-static struct mtd_info *trx_mtd;
-static struct mtd_partition trx_parts[TRX_MAX_OFFSET];
-static struct trx_header trx_hdr;
-
-static int trxsplit_refresh_partitions(struct mtd_info *mtd);
-
-static int trxsplit_checktrx(struct mtd_info *mtd, unsigned long offset)
-{
- size_t retlen;
- int err;
-
- err = mtd->read(mtd, offset, sizeof(trx_hdr), &retlen,
- (void *)&trx_hdr);
- if (err) {
- printk(KERN_ALERT PFX "unable to read from '%s'\n", mtd->name);
- goto err_out;
- }
-
- if (retlen != sizeof(trx_hdr)) {
- printk(KERN_ALERT PFX "reading failed on '%s'\n", mtd->name);
- goto err_out;
- }
-
- trx_hdr.magic = le32_to_cpu(trx_hdr.magic);
- trx_hdr.len = le32_to_cpu(trx_hdr.len);
- trx_hdr.crc32 = le32_to_cpu(trx_hdr.crc32);
- trx_hdr.flag_version = le32_to_cpu(trx_hdr.flag_version);
- trx_hdr.offsets[0] = le32_to_cpu(trx_hdr.offsets[0]);
- trx_hdr.offsets[1] = le32_to_cpu(trx_hdr.offsets[1]);
- trx_hdr.offsets[2] = le32_to_cpu(trx_hdr.offsets[2]);
-
- /* sanity checks */
- if (trx_hdr.magic != TRX_MAGIC)
- goto err_out;
-
- if (trx_hdr.len > mtd->size - offset)
- goto err_out;
-
- /* TODO: add crc32 checking too? */
-
- return 0;
-
-err_out:
- return -1;
-}
-
-static void trxsplit_findtrx(struct mtd_info *mtd)
-{
- unsigned long offset;
- int err;
-
- printk(KERN_INFO PFX "searching TRX header in '%s'\n", mtd->name);
-
- err = 0;
- for (offset = 0; offset < mtd->size; offset += TRX_ALIGN) {
- err = trxsplit_checktrx(mtd, offset);
- if (err == 0)
- break;
- }
-
- if (err)
- return;
-
- printk(KERN_INFO PFX "TRX header found at 0x%lX\n", offset);
-
- trx_mtd = mtd;
- trx_offset = offset;
-}
-
-static void trxsplit_create_partitions(struct mtd_info *mtd)
-{
- struct mtd_partition *part = trx_parts;
- int err;
- int i;
-
- for (i = 0; i < TRX_MAX_OFFSET; i++) {
- part = &trx_parts[i];
- if (trx_hdr.offsets[i] == 0)
- continue;
- part->offset = trx_offset + trx_hdr.offsets[i];
- trx_nr_parts++;
- }
-
- for (i = 0; i < trx_nr_parts-1; i++)
- trx_parts[i].size = trx_parts[i+1].offset - trx_parts[i].offset;
-
- trx_parts[i].size = mtd->size - trx_parts[i].offset;
-
- i = 0;
- part = &trx_parts[i];
- if (part->size < TRX_MIN_KERNEL_SIZE) {
- part->name = "loader";
- i++;
- }
-
- part = &trx_parts[i];
- part->name = "kernel";
- i++;
-
- part = &trx_parts[i];
- part->name = "rootfs";
-
- err = add_mtd_partitions(mtd, trx_parts, trx_nr_parts);
- if (err) {
- printk(KERN_ALERT PFX "adding TRX partitions failed\n");
- return;
- }
-
- mtd->refresh_device = trxsplit_refresh_partitions;
-}
-
-static int trxsplit_refresh_partitions(struct mtd_info *mtd)
-{
- printk(KERN_INFO PFX "refreshing TRX partitions in '%s' (%d,%d)\n",
- mtd->name, MTD_BLOCK_MAJOR, mtd->index);
-
- /* remove old partitions */
- del_mtd_partitions(mtd);
-
- trxsplit_findtrx(mtd);
- if (!trx_mtd)
- goto err;
-
- trxsplit_create_partitions(trx_mtd);
- return 1;
-
-err:
- return 0;
-}
-
-static void __init trxsplit_add_mtd(struct mtd_info *mtd)
-{
- if (mtd->type != MTD_NORFLASH) {
- printk(KERN_INFO PFX "'%s' is not a NOR flash, skipped\n",
- mtd->name);
- return;
- }
-
- if (!trx_mtd)
- trxsplit_findtrx(mtd);
-}
-
-static void __init trxsplit_remove_mtd(struct mtd_info *mtd)
-{
- /* nothing to do */
-}
-
-static struct mtd_notifier trxsplit_notifier __initdata = {
- .add = trxsplit_add_mtd,
- .remove = trxsplit_remove_mtd,
-};
-
-static void __init trxsplit_scan(void)
-{
- register_mtd_user(&trxsplit_notifier);
- unregister_mtd_user(&trxsplit_notifier);
-}
-
-static int __init trxsplit_init(void)
-{
- trxsplit_scan();
-
- if (trx_mtd) {
- printk(KERN_INFO PFX "creating TRX partitions in '%s' "
- "(%d,%d)\n", trx_mtd->name, MTD_BLOCK_MAJOR,
- trx_mtd->index);
- trxsplit_create_partitions(trx_mtd);
- }
-
- return 0;
-}
-
-late_initcall(trxsplit_init);
+++ /dev/null
-/*
- * ADM5120 built-in ethernet switch driver
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This code was based on a driver for Linux 2.6.xx by Jeroen Vreeken.
- * Copyright Jeroen Vreeken (pe1rxq@amsat.org), 2005
- * NAPI extension for the Jeroen's driver
- * Copyright Thomas Langer (Thomas.Langer@infineon.com), 2007
- * Copyright Friedrich Beckmann (Friedrich.Beckmann@infineon.com), 2007
- * Inspiration for the Jeroen's driver came from the ADMtek 2.4 driver.
- * Copyright ADMtek Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/errno.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/spinlock.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-
-#include <linux/netdevice.h>
-#include <linux/etherdevice.h>
-#include <linux/skbuff.h>
-
-#include <asm/mipsregs.h>
-
-#include <asm/mach-adm5120/adm5120_info.h>
-#include <asm/mach-adm5120/adm5120_defs.h>
-#include <asm/mach-adm5120/adm5120_switch.h>
-
-#include "adm5120sw.h"
-
-#define DRV_NAME "adm5120-switch"
-#define DRV_DESC "ADM5120 built-in ethernet switch driver"
-#define DRV_VERSION "0.1.1"
-
-#define CONFIG_ADM5120_SWITCH_NAPI 1
-#undef CONFIG_ADM5120_SWITCH_DEBUG
-
-/* ------------------------------------------------------------------------ */
-
-#ifdef CONFIG_ADM5120_SWITCH_DEBUG
-#define SW_DBG(f, a...) printk(KERN_DBG "%s: " f, DRV_NAME , ## a)
-#else
-#define SW_DBG(f, a...) do {} while (0)
-#endif
-#define SW_ERR(f, a...) printk(KERN_ERR "%s: " f, DRV_NAME , ## a)
-#define SW_INFO(f, a...) printk(KERN_INFO "%s: " f, DRV_NAME , ## a)
-
-#define SWITCH_NUM_PORTS 6
-#define ETH_CSUM_LEN 4
-
-#define RX_MAX_PKTLEN 1550
-#define RX_RING_SIZE 64
-
-#define TX_RING_SIZE 32
-#define TX_QUEUE_LEN 28 /* Limit ring entries actually used. */
-#define TX_TIMEOUT HZ*400
-
-#define RX_DESCS_SIZE (RX_RING_SIZE * sizeof(struct dma_desc *))
-#define RX_SKBS_SIZE (RX_RING_SIZE * sizeof(struct sk_buff *))
-#define TX_DESCS_SIZE (TX_RING_SIZE * sizeof(struct dma_desc *))
-#define TX_SKBS_SIZE (TX_RING_SIZE * sizeof(struct sk_buff *))
-
-#define SKB_ALLOC_LEN (RX_MAX_PKTLEN + 32)
-#define SKB_RESERVE_LEN (NET_IP_ALIGN + NET_SKB_PAD)
-
-#define SWITCH_INTS_HIGH (SWITCH_INT_SHD | SWITCH_INT_RHD | SWITCH_INT_HDF)
-#define SWITCH_INTS_LOW (SWITCH_INT_SLD | SWITCH_INT_RLD | SWITCH_INT_LDF)
-#define SWITCH_INTS_ERR (SWITCH_INT_RDE | SWITCH_INT_SDE | SWITCH_INT_CPUH)
-#define SWITCH_INTS_Q (SWITCH_INT_P0QF | SWITCH_INT_P1QF | SWITCH_INT_P2QF | \
- SWITCH_INT_P3QF | SWITCH_INT_P4QF | SWITCH_INT_P5QF | \
- SWITCH_INT_CPQF | SWITCH_INT_GQF)
-
-#define SWITCH_INTS_ALL (SWITCH_INTS_HIGH | SWITCH_INTS_LOW | \
- SWITCH_INTS_ERR | SWITCH_INTS_Q | \
- SWITCH_INT_MD | SWITCH_INT_PSC)
-
-#define SWITCH_INTS_USED (SWITCH_INTS_LOW | SWITCH_INT_PSC)
-#define SWITCH_INTS_POLL (SWITCH_INT_RLD | SWITCH_INT_LDF | SWITCH_INT_SLD)
-
-/* ------------------------------------------------------------------------ */
-
-struct adm5120_if_priv {
- struct net_device *dev;
-
- unsigned int vlan_no;
- unsigned int port_mask;
-
-#ifdef CONFIG_ADM5120_SWITCH_NAPI
- struct napi_struct napi;
-#endif
-};
-
-struct dma_desc {
- __u32 buf1;
-#define DESC_OWN (1UL << 31) /* Owned by the switch */
-#define DESC_EOR (1UL << 28) /* End of Ring */
-#define DESC_ADDR_MASK 0x1FFFFFF
-#define DESC_ADDR(x) ((__u32)(x) & DESC_ADDR_MASK)
- __u32 buf2;
-#define DESC_BUF2_EN (1UL << 31) /* Buffer 2 enable */
- __u32 buflen;
- __u32 misc;
-/* definitions for tx/rx descriptors */
-#define DESC_PKTLEN_SHIFT 16
-#define DESC_PKTLEN_MASK 0x7FF
-/* tx descriptor specific part */
-#define DESC_CSUM (1UL << 31) /* Append checksum */
-#define DESC_DSTPORT_SHIFT 8
-#define DESC_DSTPORT_MASK 0x3F
-#define DESC_VLAN_MASK 0x3F
-/* rx descriptor specific part */
-#define DESC_SRCPORT_SHIFT 12
-#define DESC_SRCPORT_MASK 0x7
-#define DESC_DA_MASK 0x3
-#define DESC_DA_SHIFT 4
-#define DESC_IPCSUM_FAIL (1UL << 3) /* IP checksum fail */
-#define DESC_VLAN_TAG (1UL << 2) /* VLAN tag present */
-#define DESC_TYPE_MASK 0x3 /* mask for Packet type */
-#define DESC_TYPE_IP 0x0 /* IP packet */
-#define DESC_TYPE_PPPoE 0x1 /* PPPoE packet */
-} __attribute__ ((aligned(16)));
-
-/* ------------------------------------------------------------------------ */
-
-static int adm5120_nrdevs;
-
-static struct net_device *adm5120_devs[SWITCH_NUM_PORTS];
-/* Lookup table port -> device */
-static struct net_device *adm5120_port[SWITCH_NUM_PORTS];
-
-static struct dma_desc *txl_descs;
-static struct dma_desc *rxl_descs;
-
-static dma_addr_t txl_descs_dma;
-static dma_addr_t rxl_descs_dma;
-
-static struct sk_buff **txl_skbuff;
-static struct sk_buff **rxl_skbuff;
-
-static unsigned int cur_rxl, dirty_rxl; /* producer/consumer ring indices */
-static unsigned int cur_txl, dirty_txl;
-
-static unsigned int sw_used;
-
-static spinlock_t tx_lock = SPIN_LOCK_UNLOCKED;
-
-/* ------------------------------------------------------------------------ */
-
-static inline u32 sw_read_reg(u32 reg)
-{
- return __raw_readl((void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE)+reg);
-}
-
-static inline void sw_write_reg(u32 reg, u32 val)
-{
- __raw_writel(val, (void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE)+reg);
-}
-
-static inline void sw_int_mask(u32 mask)
-{
- u32 t;
-
- t = sw_read_reg(SWITCH_REG_INT_MASK);
- t |= mask;
- sw_write_reg(SWITCH_REG_INT_MASK, t);
-}
-
-static inline void sw_int_unmask(u32 mask)
-{
- u32 t;
-
- t = sw_read_reg(SWITCH_REG_INT_MASK);
- t &= ~mask;
- sw_write_reg(SWITCH_REG_INT_MASK, t);
-}
-
-static inline void sw_int_ack(u32 mask)
-{
- sw_write_reg(SWITCH_REG_INT_STATUS, mask);
-}
-
-static inline u32 sw_int_status(void)
-{
- u32 t;
-
- t = sw_read_reg(SWITCH_REG_INT_STATUS);
- t &= ~sw_read_reg(SWITCH_REG_INT_MASK);
- return t;
-}
-
-static inline u32 desc_get_srcport(struct dma_desc *desc)
-{
- return (desc->misc >> DESC_SRCPORT_SHIFT) & DESC_SRCPORT_MASK;
-}
-
-static inline u32 desc_get_pktlen(struct dma_desc *desc)
-{
- return (desc->misc >> DESC_PKTLEN_SHIFT) & DESC_PKTLEN_MASK;
-}
-
-static inline int desc_ipcsum_fail(struct dma_desc *desc)
-{
- return ((desc->misc & DESC_IPCSUM_FAIL) != 0);
-}
-
-/* ------------------------------------------------------------------------ */
-
-static void sw_dump_desc(char *label, struct dma_desc *desc, int tx)
-{
- u32 t;
-
- SW_DBG("%s %s desc/%p\n", label, tx ? "tx" : "rx", desc);
-
- t = desc->buf1;
- SW_DBG(" buf1 %08X addr=%08X; len=%08X %s%s\n", t,
- t & DESC_ADDR_MASK,
- desc->buflen,
- (t & DESC_OWN) ? "SWITCH" : "CPU",
- (t & DESC_EOR) ? " RE" : "");
-
- t = desc->buf2;
- SW_DBG(" buf2 %08X addr=%08X%s\n", desc->buf2,
- t & DESC_ADDR_MASK,
- (t & DESC_BUF2_EN) ? " EN" : "" );
-
- t = desc->misc;
- if (tx)
- SW_DBG(" misc %08X%s pktlen=%04X ports=%02X vlan=%02X\n", t,
- (t & DESC_CSUM) ? " CSUM" : "",
- (t >> DESC_PKTLEN_SHIFT) & DESC_PKTLEN_MASK,
- (t >> DESC_DSTPORT_SHIFT) & DESC_DSTPORT_MASK,
- t & DESC_VLAN_MASK);
- else
- SW_DBG(" misc %08X pktlen=%04X port=%d DA=%d%s%s type=%d\n",
- t,
- (t >> DESC_PKTLEN_SHIFT) & DESC_PKTLEN_MASK,
- (t >> DESC_SRCPORT_SHIFT) & DESC_SRCPORT_MASK,
- (t >> DESC_DA_SHIFT) & DESC_DA_MASK,
- (t & DESC_IPCSUM_FAIL) ? " IPCF" : "",
- (t & DESC_VLAN_TAG) ? " VLAN" : "",
- (t & DESC_TYPE_MASK));
-}
-
-static void sw_dump_intr_mask(char *label, u32 mask)
-{
- SW_DBG("%s %08X%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
- label, mask,
- (mask & SWITCH_INT_SHD) ? " SHD" : "",
- (mask & SWITCH_INT_SLD) ? " SLD" : "",
- (mask & SWITCH_INT_RHD) ? " RHD" : "",
- (mask & SWITCH_INT_RLD) ? " RLD" : "",
- (mask & SWITCH_INT_HDF) ? " HDF" : "",
- (mask & SWITCH_INT_LDF) ? " LDF" : "",
- (mask & SWITCH_INT_P0QF) ? " P0QF" : "",
- (mask & SWITCH_INT_P1QF) ? " P1QF" : "",
- (mask & SWITCH_INT_P2QF) ? " P2QF" : "",
- (mask & SWITCH_INT_P3QF) ? " P3QF" : "",
- (mask & SWITCH_INT_P4QF) ? " P4QF" : "",
- (mask & SWITCH_INT_CPQF) ? " CPQF" : "",
- (mask & SWITCH_INT_GQF) ? " GQF" : "",
- (mask & SWITCH_INT_MD) ? " MD" : "",
- (mask & SWITCH_INT_BCS) ? " BCS" : "",
- (mask & SWITCH_INT_PSC) ? " PSC" : "",
- (mask & SWITCH_INT_ID) ? " ID" : "",
- (mask & SWITCH_INT_W0TE) ? " W0TE" : "",
- (mask & SWITCH_INT_W1TE) ? " W1TE" : "",
- (mask & SWITCH_INT_RDE) ? " RDE" : "",
- (mask & SWITCH_INT_SDE) ? " SDE" : "",
- (mask & SWITCH_INT_CPUH) ? " CPUH" : "");
-}
-
-static void sw_dump_regs(void)
-{
- u32 t;
-
- t = sw_read_reg(SWITCH_REG_PHY_STATUS);
- SW_DBG("phy_status: %08X\n", t);
-
- t = sw_read_reg(SWITCH_REG_CPUP_CONF);
- SW_DBG("cpup_conf: %08X%s%s%s\n", t,
- (t & CPUP_CONF_DCPUP) ? " DCPUP" : "",
- (t & CPUP_CONF_CRCP) ? " CRCP" : "",
- (t & CPUP_CONF_BTM) ? " BTM" : "");
-
- t = sw_read_reg(SWITCH_REG_PORT_CONF0);
- SW_DBG("port_conf0: %08X\n", t);
- t = sw_read_reg(SWITCH_REG_PORT_CONF1);
- SW_DBG("port_conf1: %08X\n", t);
- t = sw_read_reg(SWITCH_REG_PORT_CONF2);
- SW_DBG("port_conf2: %08X\n", t);
-
- t = sw_read_reg(SWITCH_REG_VLAN_G1);
- SW_DBG("vlan g1: %08X\n", t);
- t = sw_read_reg(SWITCH_REG_VLAN_G2);
- SW_DBG("vlan g2: %08X\n", t);
-
- t = sw_read_reg(SWITCH_REG_BW_CNTL0);
- SW_DBG("bw_cntl0: %08X\n", t);
- t = sw_read_reg(SWITCH_REG_BW_CNTL1);
- SW_DBG("bw_cntl1: %08X\n", t);
-
- t = sw_read_reg(SWITCH_REG_PHY_CNTL0);
- SW_DBG("phy_cntl0: %08X\n", t);
- t = sw_read_reg(SWITCH_REG_PHY_CNTL1);
- SW_DBG("phy_cntl1: %08X\n", t);
- t = sw_read_reg(SWITCH_REG_PHY_CNTL2);
- SW_DBG("phy_cntl2: %08X\n", t);
- t = sw_read_reg(SWITCH_REG_PHY_CNTL3);
- SW_DBG("phy_cntl3: %08X\n", t);
- t = sw_read_reg(SWITCH_REG_PHY_CNTL4);
- SW_DBG("phy_cntl4: %08X\n", t);
-
- t = sw_read_reg(SWITCH_REG_INT_STATUS);
- sw_dump_intr_mask("int_status: ", t);
-
- t = sw_read_reg(SWITCH_REG_INT_MASK);
- sw_dump_intr_mask("int_mask: ", t);
-
- t = sw_read_reg(SWITCH_REG_SHDA);
- SW_DBG("shda: %08X\n", t);
- t = sw_read_reg(SWITCH_REG_SLDA);
- SW_DBG("slda: %08X\n", t);
- t = sw_read_reg(SWITCH_REG_RHDA);
- SW_DBG("rhda: %08X\n", t);
- t = sw_read_reg(SWITCH_REG_RLDA);
- SW_DBG("rlda: %08X\n", t);
-}
-
-/* ------------------------------------------------------------------------ */
-
-static inline void adm5120_rx_dma_update(struct dma_desc *desc,
- struct sk_buff *skb, int end)
-{
- desc->misc = 0;
- desc->buf2 = 0;
- desc->buflen = RX_MAX_PKTLEN;
- desc->buf1 = DESC_ADDR(skb->data) |
- DESC_OWN | (end ? DESC_EOR : 0);
-}
-
-static void adm5120_switch_rx_refill(void)
-{
- unsigned int entry;
-
- for (; cur_rxl - dirty_rxl > 0; dirty_rxl++) {
- struct dma_desc *desc;
- struct sk_buff *skb;
-
- entry = dirty_rxl % RX_RING_SIZE;
- desc = &rxl_descs[entry];
-
- skb = rxl_skbuff[entry];
- if (skb == NULL) {
- skb = alloc_skb(SKB_ALLOC_LEN, GFP_ATOMIC);
- if (skb) {
- skb_reserve(skb, SKB_RESERVE_LEN);
- rxl_skbuff[entry] = skb;
- } else {
- SW_ERR("no memory for skb\n");
- desc->buflen = 0;
- desc->buf2 = 0;
- desc->misc = 0;
- desc->buf1 = (desc->buf1 & DESC_EOR) | DESC_OWN;
- break;
- }
- }
-
- desc->buf2 = 0;
- desc->buflen = RX_MAX_PKTLEN;
- desc->misc = 0;
- desc->buf1 = (desc->buf1 & DESC_EOR) | DESC_OWN |
- DESC_ADDR(skb->data);
- }
-}
-
-static int adm5120_switch_rx(int limit)
-{
- unsigned int done = 0;
-
- SW_DBG("rx start, limit=%d, cur_rxl=%u, dirty_rxl=%u\n",
- limit, cur_rxl, dirty_rxl);
-
- while (done < limit) {
- int entry = cur_rxl % RX_RING_SIZE;
- struct dma_desc *desc = &rxl_descs[entry];
- struct net_device *rdev;
- unsigned int port;
-
- if (desc->buf1 & DESC_OWN)
- break;
-
- if (dirty_rxl + RX_RING_SIZE == cur_rxl)
- break;
-
- port = desc_get_srcport(desc);
- rdev = adm5120_port[port];
-
- SW_DBG("rx descriptor %u, desc=%p, skb=%p\n", entry, desc,
- rxl_skbuff[entry]);
-
- if ((rdev) && netif_running(rdev)) {
- struct sk_buff *skb = rxl_skbuff[entry];
- int pktlen;
-
- pktlen = desc_get_pktlen(desc);
- pktlen -= ETH_CSUM_LEN;
-
- if ((pktlen == 0) || desc_ipcsum_fail(desc)) {
- rdev->stats.rx_errors++;
- if (pktlen == 0)
- rdev->stats.rx_length_errors++;
- if (desc_ipcsum_fail(desc))
- rdev->stats.rx_crc_errors++;
- SW_DBG("rx error, recycling skb %u\n", entry);
- } else {
- skb_put(skb, pktlen);
-
- skb->dev = rdev;
- skb->protocol = eth_type_trans(skb, rdev);
- skb->ip_summed = CHECKSUM_UNNECESSARY;
-
- dma_cache_wback_inv((unsigned long)skb->data,
- skb->len);
-
-#ifdef CONFIG_ADM5120_SWITCH_NAPI
- netif_receive_skb(skb);
-#else
- netif_rx(skb);
-#endif
-
- rdev->last_rx = jiffies;
- rdev->stats.rx_packets++;
- rdev->stats.rx_bytes += pktlen;
-
- rxl_skbuff[entry] = NULL;
- done++;
- }
- } else {
- SW_DBG("no rx device, recycling skb %u\n", entry);
- }
-
- cur_rxl++;
- if (cur_rxl - dirty_rxl > RX_RING_SIZE / 4)
- adm5120_switch_rx_refill();
- }
-
- adm5120_switch_rx_refill();
-
- SW_DBG("rx finished, cur_rxl=%u, dirty_rxl=%u, processed %d\n",
- cur_rxl, dirty_rxl, done);
-
- return done;
-}
-
-static void adm5120_switch_tx(void)
-{
- unsigned int entry;
-
- spin_lock(&tx_lock);
- entry = dirty_txl % TX_RING_SIZE;
- while (dirty_txl != cur_txl) {
- struct dma_desc *desc = &txl_descs[entry];
- struct sk_buff *skb = txl_skbuff[entry];
-
- if (desc->buf1 & DESC_OWN)
- break;
-
- if (netif_running(skb->dev)) {
- skb->dev->stats.tx_bytes += skb->len;
- skb->dev->stats.tx_packets++;
- }
-
- dev_kfree_skb_irq(skb);
- txl_skbuff[entry] = NULL;
- entry = (++dirty_txl) % TX_RING_SIZE;
- }
-
- if ((cur_txl - dirty_txl) < TX_QUEUE_LEN - 4) {
- int i;
- for (i = 0; i < SWITCH_NUM_PORTS; i++) {
- if (!adm5120_devs[i])
- continue;
- netif_wake_queue(adm5120_devs[i]);
- }
- }
- spin_unlock(&tx_lock);
-}
-
-#ifdef CONFIG_ADM5120_SWITCH_NAPI
-static int adm5120_if_poll(struct napi_struct *napi, int limit)
-{
- struct adm5120_if_priv *priv = container_of(napi,
- struct adm5120_if_priv, napi);
- struct net_device *dev = priv->dev;
- int done;
- u32 status;
-
- sw_int_ack(SWITCH_INTS_POLL);
-
- SW_DBG("%s: processing TX ring\n", dev->name);
- adm5120_switch_tx();
-
- SW_DBG("%s: processing RX ring\n", dev->name);
- done = adm5120_switch_rx(limit);
-
- status = sw_int_status() & SWITCH_INTS_POLL;
- if ((done < limit) && (!status)) {
- SW_DBG("disable polling mode for %s\n", dev->name);
- netif_rx_complete(dev, napi);
- sw_int_unmask(SWITCH_INTS_POLL);
- return 0;
- }
-
- SW_DBG("%s still in polling mode, done=%d, status=%x\n",
- dev->name, done, status);
- return 1;
-}
-#endif /* CONFIG_ADM5120_SWITCH_NAPI */
-
-
-static irqreturn_t adm5120_switch_irq(int irq, void *dev_id)
-{
- u32 status;
-
- status = sw_int_status();
- status &= SWITCH_INTS_ALL;
- if (!status)
- return IRQ_NONE;
-
-#ifdef CONFIG_ADM5120_SWITCH_NAPI
- sw_int_ack(status & ~SWITCH_INTS_POLL);
-
- if (status & SWITCH_INTS_POLL) {
- struct net_device *dev = dev_id;
- struct adm5120_if_priv *priv = netdev_priv(dev);
-
- sw_dump_intr_mask("poll ints", status);
- SW_DBG("enable polling mode for %s\n", dev->name);
- sw_int_mask(SWITCH_INTS_POLL);
- netif_rx_schedule(dev, &priv->napi);
- }
-#else
- sw_int_ack(status);
-
- if (status & (SWITCH_INT_RLD | SWITCH_INT_LDF)) {
- adm5120_switch_rx(RX_RING_SIZE);
- }
-
- if (status & SWITCH_INT_SLD) {
- adm5120_switch_tx();
- }
-#endif
-
- return IRQ_HANDLED;
-}
-
-static void adm5120_set_bw(char *matrix)
-{
- unsigned long val;
-
- /* Port 0 to 3 are set using the bandwidth control 0 register */
- val = matrix[0] + (matrix[1]<<8) + (matrix[2]<<16) + (matrix[3]<<24);
- sw_write_reg(SWITCH_REG_BW_CNTL0, val);
-
- /* Port 4 and 5 are set using the bandwidth control 1 register */
- val = matrix[4];
- if (matrix[5] == 1)
- sw_write_reg(SWITCH_REG_BW_CNTL1, val | 0x80000000);
- else
- sw_write_reg(SWITCH_REG_BW_CNTL1, val & ~0x8000000);
-
- SW_DBG("D: ctl0 0x%ux, ctl1 0x%ux\n", sw_read_reg(SWITCH_REG_BW_CNTL0),
- sw_read_reg(SWITCH_REG_BW_CNTL1));
-}
-
-static void adm5120_switch_tx_ring_reset(struct dma_desc *desc,
- struct sk_buff **skbl, int num)
-{
- memset(desc, 0, num * sizeof(*desc));
- desc[num-1].buf1 |= DESC_EOR;
- memset(skbl, 0, sizeof(struct skb*)*num);
-
- cur_txl = 0;
- dirty_txl = 0;
-}
-
-static void adm5120_switch_rx_ring_reset(struct dma_desc *desc,
- struct sk_buff **skbl, int num)
-{
- int i;
-
- memset(desc, 0, num * sizeof(*desc));
- for (i = 0; i < num; i++) {
- skbl[i] = dev_alloc_skb(SKB_ALLOC_LEN);
- if (!skbl[i]) {
- i = num;
- break;
- }
- skb_reserve(skbl[i], SKB_RESERVE_LEN);
- adm5120_rx_dma_update(&desc[i], skbl[i], (num-1==i));
- }
-
- cur_rxl = 0;
- dirty_rxl = 0;
-}
-
-static int adm5120_switch_tx_ring_alloc(void)
-{
- int err;
-
- txl_descs = dma_alloc_coherent(NULL, TX_DESCS_SIZE, &txl_descs_dma,
- GFP_ATOMIC);
- if (!txl_descs) {
- err = -ENOMEM;
- goto err;
- }
-
- txl_skbuff = kzalloc(TX_SKBS_SIZE, GFP_KERNEL);
- if (!txl_skbuff) {
- err = -ENOMEM;
- goto err;
- }
-
- return 0;
-
-err:
- return err;
-}
-
-static void adm5120_switch_tx_ring_free(void)
-{
- int i;
-
- if (txl_skbuff) {
- for (i = 0; i < TX_RING_SIZE; i++)
- if (txl_skbuff[i])
- kfree_skb(txl_skbuff[i]);
- kfree(txl_skbuff);
- }
-
- if (txl_descs)
- dma_free_coherent(NULL, TX_DESCS_SIZE, txl_descs,
- txl_descs_dma);
-}
-
-static int adm5120_switch_rx_ring_alloc(void)
-{
- int err;
- int i;
-
- /* init RX ring */
- rxl_descs = dma_alloc_coherent(NULL, RX_DESCS_SIZE, &rxl_descs_dma,
- GFP_ATOMIC);
- if (!rxl_descs) {
- err = -ENOMEM;
- goto err;
- }
-
- rxl_skbuff = kzalloc(RX_SKBS_SIZE, GFP_KERNEL);
- if (!rxl_skbuff) {
- err = -ENOMEM;
- goto err;
- }
-
- for (i = 0; i < RX_RING_SIZE; i++) {
- struct sk_buff *skb;
- skb = alloc_skb(SKB_ALLOC_LEN, GFP_ATOMIC);
- if (!skb) {
- err = -ENOMEM;
- goto err;
- }
- rxl_skbuff[i] = skb;
- skb_reserve(skb, SKB_RESERVE_LEN);
- }
-
- return 0;
-
-err:
- return err;
-}
-
-static void adm5120_switch_rx_ring_free(void)
-{
- int i;
-
- if (rxl_skbuff) {
- for (i = 0; i < RX_RING_SIZE; i++)
- if (rxl_skbuff[i])
- kfree_skb(rxl_skbuff[i]);
- kfree(rxl_skbuff);
- }
-
- if (rxl_descs)
- dma_free_coherent(NULL, RX_DESCS_SIZE, rxl_descs,
- rxl_descs_dma);
-}
-
-static void adm5120_write_mac(struct net_device *dev)
-{
- struct adm5120_if_priv *priv = netdev_priv(dev);
- unsigned char *mac = dev->dev_addr;
- u32 t;
-
- t = mac[2] | (mac[3] << MAC_WT1_MAC3_SHIFT) |
- (mac[4] << MAC_WT1_MAC4_SHIFT) | (mac[5] << MAC_WT1_MAC5_SHIFT);
- sw_write_reg(SWITCH_REG_MAC_WT1, t);
-
- t = (mac[0] << MAC_WT0_MAC0_SHIFT) | (mac[1] << MAC_WT0_MAC1_SHIFT) |
- MAC_WT0_MAWC | MAC_WT0_WVE | (priv->vlan_no<<3);
-
- sw_write_reg(SWITCH_REG_MAC_WT0, t);
-
- while (!(sw_read_reg(SWITCH_REG_MAC_WT0) & MAC_WT0_MWD));
-}
-
-static void adm5120_set_vlan(char *matrix)
-{
- unsigned long val;
- int vlan_port, port;
-
- val = matrix[0] + (matrix[1]<<8) + (matrix[2]<<16) + (matrix[3]<<24);
- sw_write_reg(SWITCH_REG_VLAN_G1, val);
- val = matrix[4] + (matrix[5]<<8);
- sw_write_reg(SWITCH_REG_VLAN_G2, val);
-
- /* Now set/update the port vs. device lookup table */
- for (port=0; port<SWITCH_NUM_PORTS; port++) {
- for (vlan_port=0; vlan_port<SWITCH_NUM_PORTS && !(matrix[vlan_port] & (0x00000001 << port)); vlan_port++);
- if (vlan_port <SWITCH_NUM_PORTS)
- adm5120_port[port] = adm5120_devs[vlan_port];
- else
- adm5120_port[port] = NULL;
- }
-}
-
-static void adm5120_switch_set_vlan_mac(unsigned int vlan, unsigned char *mac)
-{
- u32 t;
-
- t = mac[2] | (mac[3] << MAC_WT1_MAC3_SHIFT)
- | (mac[4] << MAC_WT1_MAC4_SHIFT)
- | (mac[5] << MAC_WT1_MAC5_SHIFT);
- sw_write_reg(SWITCH_REG_MAC_WT1, t);
-
- t = (mac[0] << MAC_WT0_MAC0_SHIFT) | (mac[1] << MAC_WT0_MAC1_SHIFT) |
- MAC_WT0_MAWC | MAC_WT0_WVE | (vlan << MAC_WT0_WVN_SHIFT) |
- (MAC_WT0_WAF_STATIC << MAC_WT0_WAF_SHIFT);
- sw_write_reg(SWITCH_REG_MAC_WT0, t);
-
- do {
- t = sw_read_reg(SWITCH_REG_MAC_WT0);
- } while ((t & MAC_WT0_MWD) == 0);
-}
-
-static void adm5120_switch_set_vlan_ports(unsigned int vlan, u32 ports)
-{
- unsigned int reg;
- u32 t;
-
- if (vlan < 4)
- reg = SWITCH_REG_VLAN_G1;
- else {
- vlan -= 4;
- reg = SWITCH_REG_VLAN_G2;
- }
-
- t = sw_read_reg(reg);
- t &= ~(0xFF << (vlan*8));
- t |= (ports << (vlan*8));
- sw_write_reg(reg, t);
-}
-
-/* ------------------------------------------------------------------------ */
-
-#ifdef CONFIG_ADM5120_SWITCH_NAPI
-static inline void adm5120_if_napi_enable(struct net_device *dev)
-{
- struct adm5120_if_priv *priv = netdev_priv(dev);
- napi_enable(&priv->napi);
-}
-
-static inline void adm5120_if_napi_disable(struct net_device *dev)
-{
- struct adm5120_if_priv *priv = netdev_priv(dev);
- napi_disable(&priv->napi);
-}
-#else
-static inline void adm5120_if_napi_enable(struct net_device *dev) {}
-static inline void adm5120_if_napi_disable(struct net_device *dev) {}
-#endif /* CONFIG_ADM5120_SWITCH_NAPI */
-
-static int adm5120_if_open(struct net_device *dev)
-{
- u32 t;
- int err;
- int i;
-
- adm5120_if_napi_enable(dev);
-
- err = request_irq(dev->irq, adm5120_switch_irq,
- (IRQF_SHARED | IRQF_DISABLED), dev->name, dev);
- if (err) {
- SW_ERR("unable to get irq for %s\n", dev->name);
- goto err;
- }
-
- if (!sw_used++)
- /* enable interrupts on first open */
- sw_int_unmask(SWITCH_INTS_USED);
-
- /* enable (additional) port */
- t = sw_read_reg(SWITCH_REG_PORT_CONF0);
- for (i = 0; i < SWITCH_NUM_PORTS; i++) {
- if (dev == adm5120_devs[i])
- t &= ~adm5120_eth_vlans[i];
- }
- sw_write_reg(SWITCH_REG_PORT_CONF0, t);
-
- netif_start_queue(dev);
-
- return 0;
-
-err:
- adm5120_if_napi_disable(dev);
- return err;
-}
-
-static int adm5120_if_stop(struct net_device *dev)
-{
- u32 t;
- int i;
-
- netif_stop_queue(dev);
- adm5120_if_napi_disable(dev);
-
- /* disable port if not assigned to other devices */
- t = sw_read_reg(SWITCH_REG_PORT_CONF0);
- t |= SWITCH_PORTS_NOCPU;
- for (i = 0; i < SWITCH_NUM_PORTS; i++) {
- if ((dev != adm5120_devs[i]) && netif_running(adm5120_devs[i]))
- t &= ~adm5120_eth_vlans[i];
- }
- sw_write_reg(SWITCH_REG_PORT_CONF0, t);
-
- if (!--sw_used)
- sw_int_mask(SWITCH_INTS_USED);
-
- free_irq(dev->irq, dev);
-
- return 0;
-}
-
-static int adm5120_if_hard_start_xmit(struct sk_buff *skb,
- struct net_device *dev)
-{
- struct dma_desc *desc;
- struct adm5120_if_priv *priv = netdev_priv(dev);
- unsigned int entry;
- unsigned long data;
- int i;
-
- /* lock switch irq */
- spin_lock_irq(&tx_lock);
-
- /* calculate the next TX descriptor entry. */
- entry = cur_txl % TX_RING_SIZE;
-
- desc = &txl_descs[entry];
- if (desc->buf1 & DESC_OWN) {
- /* We want to write a packet but the TX queue is still
- * occupied by the DMA. We are faster than the DMA... */
- SW_DBG("%s unable to transmit, packet dopped\n", dev->name);
- dev_kfree_skb(skb);
- dev->stats.tx_dropped++;
- return 0;
- }
-
- txl_skbuff[entry] = skb;
- data = (desc->buf1 & DESC_EOR);
- data |= DESC_ADDR(skb->data);
-
- desc->misc =
- ((skb->len<ETH_ZLEN?ETH_ZLEN:skb->len) << DESC_PKTLEN_SHIFT) |
- (0x1 << priv->vlan_no);
-
- desc->buflen = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
-
- desc->buf1 = data | DESC_OWN;
- sw_write_reg(SWITCH_REG_SEND_TRIG, SEND_TRIG_STL);
-
- cur_txl++;
- if (cur_txl == dirty_txl + TX_QUEUE_LEN) {
- for (i = 0; i < SWITCH_NUM_PORTS; i++) {
- if (!adm5120_devs[i])
- continue;
- netif_stop_queue(adm5120_devs[i]);
- }
- }
-
- dev->trans_start = jiffies;
-
- spin_unlock_irq(&tx_lock);
-
- return 0;
-}
-
-static void adm5120_if_tx_timeout(struct net_device *dev)
-{
- SW_INFO("TX timeout on %s\n",dev->name);
-}
-
-static void adm5120_if_set_multicast_list(struct net_device *dev)
-{
- struct adm5120_if_priv *priv = netdev_priv(dev);
- u32 ports;
- u32 t;
-
- ports = adm5120_eth_vlans[priv->vlan_no] & SWITCH_PORTS_NOCPU;
-
- t = sw_read_reg(SWITCH_REG_CPUP_CONF);
- if (dev->flags & IFF_PROMISC)
- /* enable unknown packets */
- t &= ~(ports << CPUP_CONF_DUNP_SHIFT);
- else
- /* disable unknown packets */
- t |= (ports << CPUP_CONF_DUNP_SHIFT);
-
- if (dev->flags & IFF_PROMISC || dev->flags & IFF_ALLMULTI ||
- dev->mc_count)
- /* enable multicast packets */
- t &= ~(ports << CPUP_CONF_DMCP_SHIFT);
- else
- /* disable multicast packets */
- t |= (ports << CPUP_CONF_DMCP_SHIFT);
-
- /* If there is any port configured to be in promiscuous mode, then the */
- /* Bridge Test Mode has to be activated. This will result in */
- /* transporting also packets learned in another VLAN to be forwarded */
- /* to the CPU. */
- /* The difficult scenario is when we want to build a bridge on the CPU.*/
- /* Assume we have port0 and the CPU port in VLAN0 and port1 and the */
- /* CPU port in VLAN1. Now we build a bridge on the CPU between */
- /* VLAN0 and VLAN1. Both ports of the VLANs are set in promisc mode. */
- /* Now assume a packet with ethernet source address 99 enters port 0 */
- /* It will be forwarded to the CPU because it is unknown. Then the */
- /* bridge in the CPU will send it to VLAN1 and it goes out at port 1. */
- /* When now a packet with ethernet destination address 99 comes in at */
- /* port 1 in VLAN1, then the switch has learned that this address is */
- /* located at port 0 in VLAN0. Therefore the switch will drop */
- /* this packet. In order to avoid this and to send the packet still */
- /* to the CPU, the Bridge Test Mode has to be activated. */
-
- /* Check if there is any vlan in promisc mode. */
- if (t & (SWITCH_PORTS_NOCPU << CPUP_CONF_DUNP_SHIFT))
- t &= ~CPUP_CONF_BTM; /* Disable Bridge Testing Mode */
- else
- t |= CPUP_CONF_BTM; /* Enable Bridge Testing Mode */
-
- sw_write_reg(SWITCH_REG_CPUP_CONF, t);
-
-}
-
-static int adm5120_if_set_mac_address(struct net_device *dev, void *p)
-{
- struct sockaddr *addr = p;
-
- memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
- adm5120_write_mac(dev);
- return 0;
-}
-
-static int adm5120_if_do_ioctl(struct net_device *dev, struct ifreq *rq,
- int cmd)
-{
- int err;
- struct adm5120_sw_info info;
- struct adm5120_if_priv *priv = netdev_priv(dev);
-
- switch(cmd) {
- case SIOCGADMINFO:
- info.magic = 0x5120;
- info.ports = adm5120_nrdevs;
- info.vlan = priv->vlan_no;
- err = copy_to_user(rq->ifr_data, &info, sizeof(info));
- if (err)
- return -EFAULT;
- break;
- case SIOCSMATRIX:
- if (!capable(CAP_NET_ADMIN))
- return -EPERM;
- err = copy_from_user(adm5120_eth_vlans, rq->ifr_data,
- sizeof(adm5120_eth_vlans));
- if (err)
- return -EFAULT;
- adm5120_set_vlan(adm5120_eth_vlans);
- break;
- case SIOCGMATRIX:
- err = copy_to_user(rq->ifr_data, adm5120_eth_vlans,
- sizeof(adm5120_eth_vlans));
- if (err)
- return -EFAULT;
- break;
- default:
- return -EOPNOTSUPP;
- }
- return 0;
-}
-
-static struct net_device *adm5120_if_alloc(void)
-{
- struct net_device *dev;
- struct adm5120_if_priv *priv;
-
- dev = alloc_etherdev(sizeof(*priv));
- if (!dev)
- return NULL;
-
- priv = netdev_priv(dev);
- priv->dev = dev;
-
- dev->irq = ADM5120_IRQ_SWITCH;
- dev->open = adm5120_if_open;
- dev->hard_start_xmit = adm5120_if_hard_start_xmit;
- dev->stop = adm5120_if_stop;
- dev->set_multicast_list = adm5120_if_set_multicast_list;
- dev->do_ioctl = adm5120_if_do_ioctl;
- dev->tx_timeout = adm5120_if_tx_timeout;
- dev->watchdog_timeo = TX_TIMEOUT;
- dev->set_mac_address = adm5120_if_set_mac_address;
-
-#ifdef CONFIG_ADM5120_SWITCH_NAPI
- netif_napi_add(dev, &priv->napi, adm5120_if_poll, 64);
-#endif
-
- return dev;
-}
-
-/* ------------------------------------------------------------------------ */
-
-static void adm5120_switch_cleanup(void)
-{
- int i;
-
- /* disable interrupts */
- sw_int_mask(SWITCH_INTS_ALL);
-
- for (i = 0; i < SWITCH_NUM_PORTS; i++) {
- struct net_device *dev = adm5120_devs[i];
- if (dev) {
- unregister_netdev(dev);
- free_netdev(dev);
- }
- }
-
- adm5120_switch_tx_ring_free();
- adm5120_switch_rx_ring_free();
-}
-
-static int __init adm5120_switch_probe(struct platform_device *pdev)
-{
- u32 t;
- int i, err;
-
- adm5120_nrdevs = adm5120_eth_num_ports;
-
- t = CPUP_CONF_DCPUP | CPUP_CONF_CRCP |
- SWITCH_PORTS_NOCPU << CPUP_CONF_DUNP_SHIFT |
- SWITCH_PORTS_NOCPU << CPUP_CONF_DMCP_SHIFT ;
- sw_write_reg(SWITCH_REG_CPUP_CONF, t);
-
- t = (SWITCH_PORTS_NOCPU << PORT_CONF0_EMCP_SHIFT) |
- (SWITCH_PORTS_NOCPU << PORT_CONF0_BP_SHIFT) |
- (SWITCH_PORTS_NOCPU);
- sw_write_reg(SWITCH_REG_PORT_CONF0, t);
-
- /* setup ports to Autoneg/100M/Full duplex/Auto MDIX */
- t = SWITCH_PORTS_PHY |
- (SWITCH_PORTS_PHY << PHY_CNTL2_SC_SHIFT) |
- (SWITCH_PORTS_PHY << PHY_CNTL2_DC_SHIFT) |
- (SWITCH_PORTS_PHY << PHY_CNTL2_PHYR_SHIFT) |
- (SWITCH_PORTS_PHY << PHY_CNTL2_AMDIX_SHIFT) |
- PHY_CNTL2_RMAE;
- sw_write_reg(SWITCH_REG_PHY_CNTL2, t);
-
- t = sw_read_reg(SWITCH_REG_PHY_CNTL3);
- t |= PHY_CNTL3_RNT;
- sw_write_reg(SWITCH_REG_PHY_CNTL3, t);
-
- /* Force all the packets from all ports are low priority */
- sw_write_reg(SWITCH_REG_PRI_CNTL, 0);
-
- sw_int_mask(SWITCH_INTS_ALL);
- sw_int_ack(SWITCH_INTS_ALL);
-
- err = adm5120_switch_rx_ring_alloc();
- if (err)
- goto err;
-
- err = adm5120_switch_tx_ring_alloc();
- if (err)
- goto err;
-
- adm5120_switch_tx_ring_reset(txl_descs, txl_skbuff, TX_RING_SIZE);
- adm5120_switch_rx_ring_reset(rxl_descs, rxl_skbuff, RX_RING_SIZE);
-
- sw_write_reg(SWITCH_REG_SHDA, 0);
- sw_write_reg(SWITCH_REG_SLDA, KSEG1ADDR(txl_descs));
- sw_write_reg(SWITCH_REG_RHDA, 0);
- sw_write_reg(SWITCH_REG_RLDA, KSEG1ADDR(rxl_descs));
-
- for (i = 0; i < SWITCH_NUM_PORTS; i++) {
- struct net_device *dev;
- struct adm5120_if_priv *priv;
-
- dev = adm5120_if_alloc();
- if (!dev) {
- err = -ENOMEM;
- goto err;
- }
-
- adm5120_devs[i] = dev;
- priv = netdev_priv(dev);
-
- priv->vlan_no = i;
- priv->port_mask = adm5120_eth_vlans[i];
-
- memcpy(dev->dev_addr, adm5120_eth_macs[i], 6);
- adm5120_write_mac(dev);
-
- err = register_netdev(dev);
- if (err) {
- SW_INFO("%s register failed, error=%d\n",
- dev->name, err);
- goto err;
- }
- }
-
- /* setup vlan/port mapping after devs are filled up */
- adm5120_set_vlan(adm5120_eth_vlans);
-
- /* enable CPU port */
- t = sw_read_reg(SWITCH_REG_CPUP_CONF);
- t &= ~CPUP_CONF_DCPUP;
- sw_write_reg(SWITCH_REG_CPUP_CONF, t);
-
- return 0;
-
-err:
- adm5120_switch_cleanup();
-
- SW_ERR("init failed\n");
- return err;
-}
-
-static int adm5120_switch_remove(struct platform_device *dev)
-{
- adm5120_switch_cleanup();
- return 0;
-}
-
-static struct platform_driver adm5120_switch_driver = {
- .probe = adm5120_switch_probe,
- .remove = adm5120_switch_remove,
- .driver = {
- .name = DRV_NAME,
- },
-};
-
-/* -------------------------------------------------------------------------- */
-
-static int __init adm5120_switch_mod_init(void)
-{
- int err;
-
- pr_info(DRV_DESC " version " DRV_VERSION "\n");
- err = platform_driver_register(&adm5120_switch_driver);
-
- return err;
-}
-
-static void __exit adm5120_switch_mod_exit(void)
-{
- platform_driver_unregister(&adm5120_switch_driver);
-}
-
-module_init(adm5120_switch_mod_init);
-module_exit(adm5120_switch_mod_exit);
-
-MODULE_LICENSE("GPL v2");
-MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
-MODULE_DESCRIPTION(DRV_DESC);
-MODULE_VERSION(DRV_VERSION);
+++ /dev/null
-/*
- * Defines for ADM5120 built in ethernet switch driver
- *
- * Copyright Jeroen Vreeken (pe1rxq@amsat.org), 2005
- *
- * Values come from ADM5120 datasheet and original ADMtek 2.4 driver,
- * Copyright ADMtek Inc.
- */
-
-#ifndef _INCLUDE_ADM5120SW_H_
-#define _INCLUDE_ADM5120SW_H_
-
-#define SIOCSMATRIX SIOCDEVPRIVATE
-#define SIOCGMATRIX SIOCDEVPRIVATE+1
-#define SIOCGADMINFO SIOCDEVPRIVATE+2
-
-struct adm5120_sw_info {
- u16 magic;
- u16 ports;
- u16 vlan;
-};
-
-#endif /* _INCLUDE_ADM5120SW_H_ */
+++ /dev/null
-/*
- * ADM5120 HCD (Host Controller Driver) for USB
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This file was derived from: drivers/usb/host/ohci-dbg.c
- * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
- * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-/*-------------------------------------------------------------------------*/
-
-static inline char *ed_typestring(int ed_type)
-{
- switch (ed_type) {
- case PIPE_CONTROL:
- return "ctrl";
- case PIPE_BULK:
- return "bulk";
- case PIPE_INTERRUPT:
- return "intr";
- case PIPE_ISOCHRONOUS:
- return "isoc";
- }
- return "(bad ed_type)";
-}
-
-static inline char *ed_statestring(int state)
-{
- switch (state) {
- case ED_IDLE:
- return "IDLE";
- case ED_UNLINK:
- return "UNLINK";
- case ED_OPER:
- return "OPER";
- }
- return "?STATE";
-}
-
-static inline char *pipestring(int pipe)
-{
- return ed_typestring(usb_pipetype(pipe));
-}
-
-static inline char *td_pidstring(u32 info)
-{
- switch (info & TD_DP) {
- case TD_DP_SETUP:
- return "SETUP";
- case TD_DP_IN:
- return "IN";
- case TD_DP_OUT:
- return "OUT";
- }
- return "?PID";
-}
-
-static inline char *td_togglestring(u32 info)
-{
- switch (info & TD_T) {
- case TD_T_DATA0:
- return "DATA0";
- case TD_T_DATA1:
- return "DATA1";
- case TD_T_CARRY:
- return "CARRY";
- }
- return "?TOGGLE";
-}
-
-/*-------------------------------------------------------------------------*/
-
-#ifdef DEBUG
-
-/* debug| print the main components of an URB
- * small: 0) header + data packets 1) just header
- */
-static void __attribute__((unused))
-urb_print(struct admhcd *ahcd, struct urb *urb, char *str, int small, int status)
-{
- unsigned int pipe = urb->pipe;
-
- if (!urb->dev || !urb->dev->bus) {
- admhc_dbg(ahcd, "%s URB: no dev", str);
- return;
- }
-
-#ifndef ADMHC_VERBOSE_DEBUG
- if (status != 0)
-#endif
- admhc_dbg(ahcd, "URB-%s %p dev=%d ep=%d%s-%s flags=%x len=%d/%d "
- "stat=%d\n",
- str,
- urb,
- usb_pipedevice (pipe),
- usb_pipeendpoint (pipe),
- usb_pipeout(pipe)? "out" : "in",
- pipestring(pipe),
- urb->transfer_flags,
- urb->actual_length,
- urb->transfer_buffer_length,
- status);
-
-#ifdef ADMHC_VERBOSE_DEBUG
- if (!small) {
- int i, len;
-
- if (usb_pipecontrol(pipe)) {
- admhc_dbg(ahcd, "setup(8):");
- for (i = 0; i < 8 ; i++)
- printk (" %02x", ((__u8 *) urb->setup_packet) [i]);
- printk ("\n");
- }
- if (urb->transfer_buffer_length > 0 && urb->transfer_buffer) {
- admhc_dbg(ahcd, "data(%d/%d):",
- urb->actual_length,
- urb->transfer_buffer_length);
- len = usb_pipeout(pipe)?
- urb->transfer_buffer_length: urb->actual_length;
- for (i = 0; i < 16 && i < len; i++)
- printk(" %02x", ((__u8 *)urb->transfer_buffer)[i]);
- printk("%s stat:%d\n", i < len? "...": "", status);
- }
- }
-#endif /* ADMHC_VERBOSE_DEBUG */
-}
-
-#define admhc_dbg_sw(ahcd, next, size, format, arg...) \
- do { \
- if (next) { \
- unsigned s_len; \
- s_len = scnprintf(*next, *size, format, ## arg ); \
- *size -= s_len; *next += s_len; \
- } else \
- admhc_dbg(ahcd,format, ## arg ); \
- } while (0);
-
-
-static void admhc_dump_intr_mask(struct admhcd *ahcd, char *label, u32 mask,
- char **next, unsigned *size)
-{
- admhc_dbg_sw(ahcd, next, size, "%s 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s\n",
- label,
- mask,
- (mask & ADMHC_INTR_INTA) ? " INTA" : "",
- (mask & ADMHC_INTR_FATI) ? " FATI" : "",
- (mask & ADMHC_INTR_SWI) ? " SWI" : "",
- (mask & ADMHC_INTR_TDC) ? " TDC" : "",
- (mask & ADMHC_INTR_FNO) ? " FNO" : "",
- (mask & ADMHC_INTR_SO) ? " SO" : "",
- (mask & ADMHC_INTR_INSM) ? " INSM" : "",
- (mask & ADMHC_INTR_BABI) ? " BABI" : "",
- (mask & ADMHC_INTR_7) ? " !7!" : "",
- (mask & ADMHC_INTR_6) ? " !6!" : "",
- (mask & ADMHC_INTR_RESI) ? " RESI" : "",
- (mask & ADMHC_INTR_SOFI) ? " SOFI" : ""
- );
-}
-
-static void maybe_print_eds(struct admhcd *ahcd, char *label, u32 value,
- char **next, unsigned *size)
-{
- if (value)
- admhc_dbg_sw(ahcd, next, size, "%s %08x\n", label, value);
-}
-
-static char *buss2string (int state)
-{
- switch (state) {
- case ADMHC_BUSS_RESET:
- return "reset";
- case ADMHC_BUSS_RESUME:
- return "resume";
- case ADMHC_BUSS_OPER:
- return "operational";
- case ADMHC_BUSS_SUSPEND:
- return "suspend";
- }
- return "?state";
-}
-
-static void
-admhc_dump_status(struct admhcd *ahcd, char **next, unsigned *size)
-{
- struct admhcd_regs __iomem *regs = ahcd->regs;
- u32 temp;
-
- temp = admhc_readl(ahcd, ®s->gencontrol);
- admhc_dbg_sw(ahcd, next, size,
- "gencontrol 0x%08x%s%s%s%s\n",
- temp,
- (temp & ADMHC_CTRL_UHFE) ? " UHFE" : "",
- (temp & ADMHC_CTRL_SIR) ? " SIR" : "",
- (temp & ADMHC_CTRL_DMAA) ? " DMAA" : "",
- (temp & ADMHC_CTRL_SR) ? " SR" : ""
- );
-
- temp = admhc_readl(ahcd, ®s->host_control);
- admhc_dbg_sw(ahcd, next, size,
- "host_control 0x%08x BUSS=%s%s\n",
- temp,
- buss2string(temp & ADMHC_HC_BUSS),
- (temp & ADMHC_HC_DMAE) ? " DMAE" : ""
- );
-
- admhc_dump_intr_mask(ahcd, "int_status",
- admhc_readl(ahcd, ®s->int_status),
- next, size);
- admhc_dump_intr_mask(ahcd, "int_enable",
- admhc_readl(ahcd, ®s->int_enable),
- next, size);
-
- maybe_print_eds(ahcd, "hosthead",
- admhc_readl(ahcd, ®s->hosthead), next, size);
-}
-
-#define dbg_port_sw(hc,num,value,next,size) \
- admhc_dbg_sw(hc, next, size, \
- "portstatus [%d] " \
- "0x%08x%s%s%s%s%s%s%s%s%s%s%s%s\n", \
- num, temp, \
- (temp & ADMHC_PS_PRSC) ? " PRSC" : "", \
- (temp & ADMHC_PS_OCIC) ? " OCIC" : "", \
- (temp & ADMHC_PS_PSSC) ? " PSSC" : "", \
- (temp & ADMHC_PS_PESC) ? " PESC" : "", \
- (temp & ADMHC_PS_CSC) ? " CSC" : "", \
- \
- (temp & ADMHC_PS_LSDA) ? " LSDA" : "", \
- (temp & ADMHC_PS_PPS) ? " PPS" : "", \
- (temp & ADMHC_PS_PRS) ? " PRS" : "", \
- (temp & ADMHC_PS_POCI) ? " POCI" : "", \
- (temp & ADMHC_PS_PSS) ? " PSS" : "", \
- \
- (temp & ADMHC_PS_PES) ? " PES" : "", \
- (temp & ADMHC_PS_CCS) ? " CCS" : "" \
- );
-
-
-static void
-admhc_dump_roothub(
- struct admhcd *ahcd,
- int verbose,
- char **next,
- unsigned *size)
-{
- u32 temp, i;
-
- temp = admhc_read_rhdesc(ahcd);
- if (temp == ~(u32)0)
- return;
-
- if (verbose) {
- admhc_dbg_sw(ahcd, next, size,
- "rhdesc %08x%s%s%s%s%s%s PPCM=%02x%s%s%s%s NUMP=%d(%d)\n",
- temp,
- (temp & ADMHC_RH_CRWE) ? " CRWE" : "",
- (temp & ADMHC_RH_OCIC) ? " OCIC" : "",
- (temp & ADMHC_RH_LPSC) ? " LPSC" : "",
- (temp & ADMHC_RH_LPSC) ? " DRWE" : "",
- (temp & ADMHC_RH_LPSC) ? " OCI" : "",
- (temp & ADMHC_RH_LPSC) ? " LPS" : "",
- ((temp & ADMHC_RH_PPCM) >> 16),
- (temp & ADMHC_RH_NOCP) ? " NOCP" : "",
- (temp & ADMHC_RH_OCPM) ? " OCPM" : "",
- (temp & ADMHC_RH_NPS) ? " NPS" : "",
- (temp & ADMHC_RH_PSM) ? " PSM" : "",
- (temp & ADMHC_RH_NUMP), ahcd->num_ports
- );
- }
-
- for (i = 0; i < ahcd->num_ports; i++) {
- temp = admhc_read_portstatus(ahcd, i);
- dbg_port_sw(ahcd, i, temp, next, size);
- }
-}
-
-static void admhc_dump(struct admhcd *ahcd, int verbose)
-{
- admhc_dbg(ahcd, "ADMHC ahcd state\n");
-
- /* dumps some of the state we know about */
- admhc_dump_status(ahcd, NULL, NULL);
- admhc_dbg(ahcd,"current frame #%04x\n",
- admhc_frame_no(ahcd));
-
- admhc_dump_roothub(ahcd, verbose, NULL, NULL);
-}
-
-static const char data0[] = "DATA0";
-static const char data1[] = "DATA1";
-
-static void admhc_dump_td(const struct admhcd *ahcd, const char *label,
- const struct td *td)
-{
- u32 tmp;
-
- admhc_dbg(ahcd, "%s td %p; urb %p index %d; hwNextTD %08x\n",
- label, td,
- td->urb, td->index,
- hc32_to_cpup(ahcd, &td->hwNextTD));
-
- tmp = hc32_to_cpup(ahcd, &td->hwINFO);
- admhc_dbg(ahcd, " status %08x%s CC=%x EC=%d %s %s ISI=%x FN=%x\n",
- tmp,
- (tmp & TD_OWN) ? " OWN" : "",
- TD_CC_GET(tmp),
- TD_EC_GET(tmp),
- td_togglestring(tmp),
- td_pidstring(tmp),
- TD_ISI_GET(tmp),
- TD_FN_GET(tmp));
-
- tmp = hc32_to_cpup(ahcd, &td->hwCBL);
- admhc_dbg(ahcd, " dbp %08x; cbl %08x; LEN=%d%s\n",
- hc32_to_cpup(ahcd, &td->hwDBP),
- tmp,
- TD_BL_GET(tmp),
- (tmp & TD_IE) ? " IE" : "");
-}
-
-/* caller MUST own hcd spinlock if verbose is set! */
-static void __attribute__((unused))
-admhc_dump_ed(const struct admhcd *ahcd, const char *label,
- const struct ed *ed, int verbose)
-{
- u32 tmp = hc32_to_cpu(ahcd, ed->hwINFO);
-
- admhc_dbg(ahcd, "%s ed %p %s type %s; next ed %08x\n",
- label,
- ed, ed_statestring(ed->state), ed_typestring(ed->type),
- hc32_to_cpup(ahcd, &ed->hwNextED));
-
- admhc_dbg(ahcd, " info %08x MAX=%d%s%s%s%s EP=%d DEV=%d\n", tmp,
- ED_MPS_GET(tmp),
- (tmp & ED_ISO) ? " ISO" : "",
- (tmp & ED_SKIP) ? " SKIP" : "",
- (tmp & ED_SPEED_FULL) ? " FULL" : " LOW",
- (tmp & ED_INT) ? " INT" : "",
- ED_EN_GET(tmp),
- ED_FA_GET(tmp));
-
- tmp = hc32_to_cpup(ahcd, &ed->hwHeadP);
- admhc_dbg(ahcd, " tds: head %08x tail %08x %s%s%s\n",
- tmp & TD_MASK,
- hc32_to_cpup (ahcd, &ed->hwTailP),
- (tmp & ED_C) ? data1 : data0,
- (tmp & ED_H) ? " HALT" : "",
- verbose ? " td list follows" : " (not listing)");
-
- if (verbose) {
- struct list_head *tmp;
-
- /* use ed->td_list because HC concurrently modifies
- * hwNextTD as it accumulates ed_donelist.
- */
- list_for_each(tmp, &ed->td_list) {
- struct td *td;
- td = list_entry(tmp, struct td, td_list);
- admhc_dump_td (ahcd, " ->", td);
- }
- }
-}
-
-#else /* ifdef DEBUG */
-
-static inline void urb_print(struct admhcd *ahcd, struct urb * urb, char * str,
- int small) {}
-static inline void admhc_dump_ed(const struct admhcd *ahcd, const char *label,
- const struct ed *ed, int verbose) {}
-static inline void admhc_dump_td(const struct admhcd *ahcd, const char *label,
- const struct td *td) {}
-static inline void admhc_dump(struct admhcd *ahcd, int verbose) {}
-
-#undef ADMHC_VERBOSE_DEBUG
-
-#endif /* DEBUG */
-
-/*-------------------------------------------------------------------------*/
-
-#ifdef STUB_DEBUG_FILES
-
-static inline void create_debug_files(struct admhcd *bus) { }
-static inline void remove_debug_files(struct admhcd *bus) { }
-
-#else
-
-static int debug_async_open(struct inode *, struct file *);
-static int debug_periodic_open(struct inode *, struct file *);
-static int debug_registers_open(struct inode *, struct file *);
-static ssize_t debug_output(struct file*, char __user*, size_t, loff_t*);
-static int debug_close(struct inode *, struct file *);
-
-static const struct file_operations debug_async_fops = {
- .owner = THIS_MODULE,
- .open = debug_async_open,
- .read = debug_output,
- .release = debug_close,
-};
-static const struct file_operations debug_periodic_fops = {
- .owner = THIS_MODULE,
- .open = debug_periodic_open,
- .read = debug_output,
- .release = debug_close,
-};
-static const struct file_operations debug_registers_fops = {
- .owner = THIS_MODULE,
- .open = debug_registers_open,
- .read = debug_output,
- .release = debug_close,
-};
-
-static struct dentry *admhc_debug_root;
-
-struct debug_buffer {
- ssize_t (*fill_func)(struct debug_buffer *); /* fill method */
- struct device *dev;
- struct mutex mutex; /* protect filling of buffer */
- size_t count; /* number of characters filled into buffer */
- char *page;
-};
-
-static ssize_t
-show_list(struct admhcd *ahcd, char *buf, size_t count, struct ed *ed)
-{
- unsigned temp;
- unsigned size = count;
-
- if (!ed)
- return 0;
-
- /* dump a snapshot of the bulk or control schedule */
- while (ed) {
- u32 info = hc32_to_cpu(ahcd, ed->hwINFO);
- u32 headp = hc32_to_cpu(ahcd, ed->hwHeadP);
- u32 tailp = hc32_to_cpu(ahcd, ed->hwTailP);
- struct list_head *entry;
- struct td *td;
-
- temp = scnprintf(buf, size,
- "ed/%p %s %s %cs dev%d ep%d %s%smax %d %08x%s%s %s"
- " h:%08x t:%08x",
- ed,
- ed_statestring(ed->state),
- ed_typestring (ed->type),
- (info & ED_SPEED_FULL) ? 'f' : 'l',
- info & ED_FA_MASK,
- (info >> ED_EN_SHIFT) & ED_EN_MASK,
- (info & ED_INT) ? "INT " : "",
- (info & ED_ISO) ? "ISO " : "",
- (info >> ED_MPS_SHIFT) & ED_MPS_MASK ,
- info,
- (info & ED_SKIP) ? " S" : "",
- (headp & ED_H) ? " H" : "",
- (headp & ED_C) ? data1 : data0,
- headp & ED_MASK,tailp);
- size -= temp;
- buf += temp;
-
- list_for_each(entry, &ed->td_list) {
- u32 dbp, cbl;
-
- td = list_entry(entry, struct td, td_list);
- info = hc32_to_cpup (ahcd, &td->hwINFO);
- dbp = hc32_to_cpup (ahcd, &td->hwDBP);
- cbl = hc32_to_cpup (ahcd, &td->hwCBL);
-
- temp = scnprintf(buf, size,
- "\n\ttd/%p %s %d %s%scc=%x urb %p (%08x,%08x)",
- td,
- td_pidstring(info),
- TD_BL_GET(cbl),
- (info & TD_OWN) ? "" : "DONE ",
- (cbl & TD_IE) ? "IE " : "",
- TD_CC_GET (info), td->urb, info, cbl);
- size -= temp;
- buf += temp;
- }
-
- temp = scnprintf(buf, size, "\n");
- size -= temp;
- buf += temp;
-
- ed = ed->ed_next;
- }
-
- return count - size;
-}
-
-static ssize_t fill_async_buffer(struct debug_buffer *buf)
-{
- struct usb_bus *bus;
- struct usb_hcd *hcd;
- struct admhcd *ahcd;
- size_t temp;
- unsigned long flags;
-
- bus = dev_get_drvdata(buf->dev);
- hcd = bus_to_hcd(bus);
- ahcd = hcd_to_admhcd(hcd);
-
- spin_lock_irqsave(&ahcd->lock, flags);
- temp = show_list(ahcd, buf->page, PAGE_SIZE, ahcd->ed_head);
- spin_unlock_irqrestore(&ahcd->lock, flags);
-
- return temp;
-}
-
-
-#define DBG_SCHED_LIMIT 64
-
-static ssize_t fill_periodic_buffer(struct debug_buffer *buf)
-{
- struct usb_bus *bus;
- struct usb_hcd *hcd;
- struct admhcd *ahcd;
- struct ed **seen, *ed;
- unsigned long flags;
- unsigned temp, size, seen_count;
- char *next;
- unsigned i;
-
- if (!(seen = kmalloc(DBG_SCHED_LIMIT * sizeof *seen, GFP_ATOMIC)))
- return 0;
- seen_count = 0;
-
- bus = dev_get_drvdata(buf->dev);
- hcd = bus_to_hcd(bus);
- ahcd = hcd_to_admhcd(hcd);
- next = buf->page;
- size = PAGE_SIZE;
-
- temp = scnprintf(next, size, "size = %d\n", NUM_INTS);
- size -= temp;
- next += temp;
-
- /* dump a snapshot of the periodic schedule (and load) */
- spin_lock_irqsave(&ahcd->lock, flags);
- for (i = 0; i < NUM_INTS; i++) {
- if (!(ed = ahcd->periodic [i]))
- continue;
-
- temp = scnprintf(next, size, "%2d [%3d]:", i, ahcd->load [i]);
- size -= temp;
- next += temp;
-
- do {
- temp = scnprintf(next, size, " ed%d/%p",
- ed->interval, ed);
- size -= temp;
- next += temp;
- for (temp = 0; temp < seen_count; temp++) {
- if (seen [temp] == ed)
- break;
- }
-
- /* show more info the first time around */
- if (temp == seen_count) {
- u32 info = hc32_to_cpu (ahcd, ed->hwINFO);
- struct list_head *entry;
- unsigned qlen = 0;
-
- /* qlen measured here in TDs, not urbs */
- list_for_each (entry, &ed->td_list)
- qlen++;
- temp = scnprintf(next, size,
- " (%cs dev%d ep%d%s qlen %u"
- " max %d %08x%s%s)",
- (info & ED_SPEED_FULL) ? 'f' : 'l',
- ED_FA_GET(info),
- ED_EN_GET(info),
- (info & ED_ISO) ? "iso" : "int",
- qlen,
- ED_MPS_GET(info),
- info,
- (info & ED_SKIP) ? " K" : "",
- (ed->hwHeadP &
- cpu_to_hc32(ahcd, ED_H)) ?
- " H" : "");
- size -= temp;
- next += temp;
-
- if (seen_count < DBG_SCHED_LIMIT)
- seen [seen_count++] = ed;
-
- ed = ed->ed_next;
-
- } else {
- /* we've seen it and what's after */
- temp = 0;
- ed = NULL;
- }
-
- } while (ed);
-
- temp = scnprintf(next, size, "\n");
- size -= temp;
- next += temp;
- }
- spin_unlock_irqrestore(&ahcd->lock, flags);
- kfree (seen);
-
- return PAGE_SIZE - size;
-}
-
-
-#undef DBG_SCHED_LIMIT
-
-static ssize_t fill_registers_buffer(struct debug_buffer *buf)
-{
- struct usb_bus *bus;
- struct usb_hcd *hcd;
- struct admhcd *ahcd;
- struct admhcd_regs __iomem *regs;
- unsigned long flags;
- unsigned temp, size;
- char *next;
- u32 rdata;
-
- bus = dev_get_drvdata(buf->dev);
- hcd = bus_to_hcd(bus);
- ahcd = hcd_to_admhcd(hcd);
- regs = ahcd->regs;
- next = buf->page;
- size = PAGE_SIZE;
-
- spin_lock_irqsave(&ahcd->lock, flags);
-
- /* dump driver info, then registers in spec order */
-
- admhc_dbg_sw(ahcd, &next, &size,
- "bus %s, device %s\n"
- "%s\n"
- "%s version " DRIVER_VERSION "\n",
- hcd->self.controller->bus->name,
- hcd->self.controller->bus_id,
- hcd->product_desc,
- hcd_name);
-
- if (bus->controller->power.power_state.event) {
- size -= scnprintf(next, size,
- "SUSPENDED (no register access)\n");
- goto done;
- }
-
- admhc_dump_status(ahcd, &next, &size);
-
- /* other registers mostly affect frame timings */
- rdata = admhc_readl(ahcd, ®s->fminterval);
- temp = scnprintf(next, size,
- "fmintvl 0x%08x %sFSLDP=0x%04x FI=0x%04x\n",
- rdata, (rdata & ADMHC_SFI_FIT) ? "FIT " : "",
- (rdata >> ADMHC_SFI_FSLDP_SHIFT) & ADMHC_SFI_FSLDP_MASK,
- rdata & ADMHC_SFI_FI_MASK);
- size -= temp;
- next += temp;
-
- rdata = admhc_readl(ahcd, ®s->fmnumber);
- temp = scnprintf(next, size, "fmnumber 0x%08x %sFR=0x%04x FN=%04x\n",
- rdata, (rdata & ADMHC_SFN_FRT) ? "FRT " : "",
- (rdata >> ADMHC_SFN_FR_SHIFT) & ADMHC_SFN_FR_MASK,
- rdata & ADMHC_SFN_FN_MASK);
- size -= temp;
- next += temp;
-
- /* TODO: use predefined bitmask */
- rdata = admhc_readl(ahcd, ®s->lsthresh);
- temp = scnprintf(next, size, "lsthresh 0x%04x\n",
- rdata & 0x3fff);
- size -= temp;
- next += temp;
-
- temp = scnprintf(next, size, "hub poll timer: %s\n",
- admhcd_to_hcd(ahcd)->poll_rh ? "ON" : "OFF");
- size -= temp;
- next += temp;
-
- /* roothub */
- admhc_dump_roothub(ahcd, 1, &next, &size);
-
-done:
- spin_unlock_irqrestore(&ahcd->lock, flags);
- return PAGE_SIZE - size;
-}
-
-
-static struct debug_buffer *alloc_buffer(struct device *dev,
- ssize_t (*fill_func)(struct debug_buffer *))
-{
- struct debug_buffer *buf;
-
- buf = kzalloc(sizeof(struct debug_buffer), GFP_KERNEL);
-
- if (buf) {
- buf->dev = dev;
- buf->fill_func = fill_func;
- mutex_init(&buf->mutex);
- }
-
- return buf;
-}
-
-static int fill_buffer(struct debug_buffer *buf)
-{
- int ret = 0;
-
- if (!buf->page)
- buf->page = (char *)get_zeroed_page(GFP_KERNEL);
-
- if (!buf->page) {
- ret = -ENOMEM;
- goto out;
- }
-
- ret = buf->fill_func(buf);
-
- if (ret >= 0) {
- buf->count = ret;
- ret = 0;
- }
-
-out:
- return ret;
-}
-
-static ssize_t debug_output(struct file *file, char __user *user_buf,
- size_t len, loff_t *offset)
-{
- struct debug_buffer *buf = file->private_data;
- int ret = 0;
-
- mutex_lock(&buf->mutex);
- if (buf->count == 0) {
- ret = fill_buffer(buf);
- if (ret != 0) {
- mutex_unlock(&buf->mutex);
- goto out;
- }
- }
- mutex_unlock(&buf->mutex);
-
- ret = simple_read_from_buffer(user_buf, len, offset,
- buf->page, buf->count);
-
-out:
- return ret;
-}
-
-static int debug_close(struct inode *inode, struct file *file)
-{
- struct debug_buffer *buf = file->private_data;
-
- if (buf) {
- if (buf->page)
- free_page((unsigned long)buf->page);
- kfree(buf);
- }
-
- return 0;
-}
-
-static int debug_async_open(struct inode *inode, struct file *file)
-{
- file->private_data = alloc_buffer(inode->i_private, fill_async_buffer);
-
- return file->private_data ? 0 : -ENOMEM;
-}
-
-static int debug_periodic_open(struct inode *inode, struct file *file)
-{
- file->private_data = alloc_buffer(inode->i_private,
- fill_periodic_buffer);
-
- return file->private_data ? 0 : -ENOMEM;
-}
-
-static int debug_registers_open(struct inode *inode, struct file *file)
-{
- file->private_data = alloc_buffer(inode->i_private,
- fill_registers_buffer);
-
- return file->private_data ? 0 : -ENOMEM;
-}
-
-static inline void create_debug_files(struct admhcd *ahcd)
-{
- struct usb_bus *bus = &admhcd_to_hcd(ahcd)->self;
- struct device *dev = bus->dev;
-
- ahcd->debug_dir = debugfs_create_dir(bus->bus_name, admhc_debug_root);
- if (!ahcd->debug_dir)
- goto dir_error;
-
- ahcd->debug_async = debugfs_create_file("async", S_IRUGO,
- ahcd->debug_dir, dev,
- &debug_async_fops);
- if (!ahcd->debug_async)
- goto async_error;
-
- ahcd->debug_periodic = debugfs_create_file("periodic", S_IRUGO,
- ahcd->debug_dir, dev,
- &debug_periodic_fops);
- if (!ahcd->debug_periodic)
- goto periodic_error;
-
- ahcd->debug_registers = debugfs_create_file("registers", S_IRUGO,
- ahcd->debug_dir, dev,
- &debug_registers_fops);
- if (!ahcd->debug_registers)
- goto registers_error;
-
- admhc_dbg(ahcd, "created debug files\n");
- return;
-
-registers_error:
- debugfs_remove(ahcd->debug_periodic);
-periodic_error:
- debugfs_remove(ahcd->debug_async);
-async_error:
- debugfs_remove(ahcd->debug_dir);
-dir_error:
- ahcd->debug_periodic = NULL;
- ahcd->debug_async = NULL;
- ahcd->debug_dir = NULL;
-}
-
-static inline void remove_debug_files(struct admhcd *ahcd)
-{
- debugfs_remove(ahcd->debug_registers);
- debugfs_remove(ahcd->debug_periodic);
- debugfs_remove(ahcd->debug_async);
- debugfs_remove(ahcd->debug_dir);
-}
-
-#endif
-
-/*-------------------------------------------------------------------------*/
+++ /dev/null
-/*
- * ADM5120 HCD (Host Controller Driver) for USB
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This file was derived from: drivers/usb/host/ohci-au1xxx.c
- * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
- * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
- * (C) Copyright 2002 Hewlett-Packard Company
- *
- * Written by Christopher Hoover <ch@hpl.hp.com>
- * Based on fragments of previous driver by Rusell King et al.
- *
- * Modified for LH7A404 from ahcd-sa1111.c
- * by Durgesh Pattamatta <pattamattad@sharpsec.com>
- * Modified for AMD Alchemy Au1xxx
- * by Matt Porter <mporter@kernel.crashing.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/platform_device.h>
-#include <linux/signal.h>
-
-#include <asm/bootinfo.h>
-#include <asm/mach-adm5120/adm5120_defs.h>
-
-#ifdef DEBUG
-#define HCD_DBG(f, a...) printk(KERN_DEBUG "%s: " f, hcd_name, ## a)
-#else
-#define HCD_DBG(f, a...) do {} while (0)
-#endif
-#define HCD_ERR(f, a...) printk(KERN_ERR "%s: " f, hcd_name, ## a)
-#define HCD_INFO(f, a...) printk(KERN_INFO "%s: " f, hcd_name, ## a)
-
-/*-------------------------------------------------------------------------*/
-
-static int admhc_adm5120_probe(const struct hc_driver *driver,
- struct platform_device *dev)
-{
- int retval;
- struct usb_hcd *hcd;
- int irq;
- struct resource *regs;
-
- /* sanity checks */
- regs = platform_get_resource(dev, IORESOURCE_MEM, 0);
- if (!regs) {
- HCD_DBG("no IOMEM resource found\n");
- return -ENODEV;
- }
-
- irq = platform_get_irq(dev, 0);
- if (irq < 0) {
- HCD_DBG("no IRQ resource found\n");
- return -ENODEV;
- }
-
- hcd = usb_create_hcd(driver, &dev->dev, "ADM5120");
- if (!hcd)
- return -ENOMEM;
-
- hcd->rsrc_start = regs->start;
- hcd->rsrc_len = regs->end - regs->start + 1;
-
- if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
- HCD_DBG("request_mem_region failed\n");
- retval = -EBUSY;
- goto err_dev;
- }
-
- hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
- if (!hcd->regs) {
- HCD_DBG("ioremap failed\n");
- retval = -ENOMEM;
- goto err_mem;
- }
-
- admhc_hcd_init(hcd_to_admhcd(hcd));
-
- retval = usb_add_hcd(hcd, irq, IRQF_DISABLED);
- if (retval)
- goto err_io;
-
- return 0;
-
-err_io:
- iounmap(hcd->regs);
-err_mem:
- release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
-err_dev:
- usb_put_hcd(hcd);
- return retval;
-}
-
-
-/* may be called without controller electrically present */
-/* may be called with controller, bus, and devices active */
-
-static void admhc_adm5120_remove(struct usb_hcd *hcd,
- struct platform_device *dev)
-{
- usb_remove_hcd(hcd);
- iounmap(hcd->regs);
- release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
- usb_put_hcd(hcd);
-}
-
-/*-------------------------------------------------------------------------*/
-
-static int __devinit
-admhc_adm5120_start(struct usb_hcd *hcd)
-{
- struct admhcd *ahcd = hcd_to_admhcd (hcd);
- int ret;
-
- ret = admhc_init(ahcd);
- if (ret < 0) {
- HCD_ERR("unable to init %s\n", hcd->self.bus_name);
- goto err;
- }
-
- ret = admhc_run(ahcd);
- if (ret < 0) {
- HCD_ERR("unable to run %s\n", hcd->self.bus_name);
- goto err_stop;
- }
-
- return 0;
-
-err_stop:
- admhc_stop(hcd);
-err:
- return ret;
-}
-
-/*-------------------------------------------------------------------------*/
-
-static const struct hc_driver adm5120_hc_driver = {
- .description = hcd_name,
- .product_desc = "ADM5120 built-in USB 1.1 Host Controller",
- .hcd_priv_size = sizeof(struct admhcd),
-
- /*
- * generic hardware linkage
- */
- .irq = admhc_irq,
- .flags = HCD_USB11 | HCD_MEMORY,
-
- /*
- * basic lifecycle operations
- */
- .start = admhc_adm5120_start,
- .stop = admhc_stop,
- .shutdown = admhc_shutdown,
-
- /*
- * managing i/o requests and associated device resources
- */
- .urb_enqueue = admhc_urb_enqueue,
- .urb_dequeue = admhc_urb_dequeue,
- .endpoint_disable = admhc_endpoint_disable,
-
- /*
- * scheduling support
- */
- .get_frame_number = admhc_get_frame_number,
-
- /*
- * root hub support
- */
- .hub_status_data = admhc_hub_status_data,
- .hub_control = admhc_hub_control,
- .hub_irq_enable = admhc_hub_irq_enable,
-#ifdef CONFIG_PM
- .bus_suspend = admhc_bus_suspend,
- .bus_resume = admhc_bus_resume,
-#endif
- .start_port_reset = admhc_start_port_reset,
-};
-
-/*-------------------------------------------------------------------------*/
-
-static int usb_hcd_adm5120_probe(struct platform_device *pdev)
-{
- int ret;
-
- ret = admhc_adm5120_probe(&adm5120_hc_driver, pdev);
-
- return ret;
-}
-
-static int usb_hcd_adm5120_remove(struct platform_device *pdev)
-{
- struct usb_hcd *hcd = platform_get_drvdata(pdev);
-
- admhc_adm5120_remove(hcd, pdev);
-
- return 0;
-}
-
-#ifdef CONFIG_PM
-/* TODO */
-static int usb_hcd_adm5120_suspend(struct platform_device *dev)
-{
- struct usb_hcd *hcd = platform_get_drvdata(dev);
-
- return 0;
-}
-
-static int usb_hcd_adm5120_resume(struct platform_device *dev)
-{
- struct usb_hcd *hcd = platform_get_drvdata(dev);
-
- return 0;
-}
-#else
-#define usb_hcd_adm5120_suspend NULL
-#define usb_hcd_adm5120_resume NULL
-#endif /* CONFIG_PM */
-
-static struct platform_driver usb_hcd_adm5120_driver = {
- .probe = usb_hcd_adm5120_probe,
- .remove = usb_hcd_adm5120_remove,
- .shutdown = usb_hcd_platform_shutdown,
- .suspend = usb_hcd_adm5120_suspend,
- .resume = usb_hcd_adm5120_resume,
- .driver = {
- .name = "adm5120-hcd",
- .owner = THIS_MODULE,
- },
-};
-
+++ /dev/null
-/*
- * ADM5120 HCD (Host Controller Driver) for USB
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This file was derived from: drivers/usb/host/ohci-hcd.c
- * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
- * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
- *
- * [ Initialisation is based on Linus' ]
- * [ uhci code and gregs ahcd fragments ]
- * [ (C) Copyright 1999 Linus Torvalds ]
- * [ (C) Copyright 1999 Gregory P. Smith]
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-#include <linux/delay.h>
-#include <linux/ioport.h>
-#include <linux/sched.h>
-#include <linux/slab.h>
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/timer.h>
-#include <linux/list.h>
-#include <linux/usb.h>
-#include <linux/usb/otg.h>
-#include <linux/dma-mapping.h>
-#include <linux/dmapool.h>
-#include <linux/reboot.h>
-#include <linux/debugfs.h>
-
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/system.h>
-#include <asm/unaligned.h>
-#include <asm/byteorder.h>
-
-#include "../core/hcd.h"
-#include "../core/hub.h"
-
-#define DRIVER_VERSION "0.25.0"
-#define DRIVER_AUTHOR "Gabor Juhos <juhosg@openwrt.org>"
-#define DRIVER_DESC "ADMtek USB 1.1 Host Controller Driver"
-
-/*-------------------------------------------------------------------------*/
-
-#undef ADMHC_VERBOSE_DEBUG /* not always helpful */
-
-/* For initializing controller (mask in an HCFS mode too) */
-#define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
-
-#define ADMHC_INTR_INIT \
- ( ADMHC_INTR_MIE | ADMHC_INTR_INSM | ADMHC_INTR_FATI \
- | ADMHC_INTR_RESI | ADMHC_INTR_TDC | ADMHC_INTR_BABI )
-
-/*-------------------------------------------------------------------------*/
-
-static const char hcd_name [] = "admhc-hcd";
-
-#define STATECHANGE_DELAY msecs_to_jiffies(300)
-
-#include "adm5120.h"
-
-static void admhc_dump(struct admhcd *ahcd, int verbose);
-static int admhc_init(struct admhcd *ahcd);
-static void admhc_stop(struct usb_hcd *hcd);
-
-#include "adm5120-dbg.c"
-#include "adm5120-mem.c"
-#include "adm5120-pm.c"
-#include "adm5120-hub.c"
-#include "adm5120-q.c"
-
-/*-------------------------------------------------------------------------*/
-
-/*
- * queue up an urb for anything except the root hub
- */
-static int admhc_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
- gfp_t mem_flags)
-{
- struct admhcd *ahcd = hcd_to_admhcd(hcd);
- struct ed *ed;
- struct urb_priv *urb_priv;
- unsigned int pipe = urb->pipe;
- int td_cnt = 0;
- unsigned long flags;
- int ret = 0;
-
-#ifdef ADMHC_VERBOSE_DEBUG
- spin_lock_irqsave(&ahcd->lock, flags);
- urb_print(ahcd, urb, "ENQEUE", usb_pipein(pipe), -EINPROGRESS);
- spin_unlock_irqrestore(&ahcd->lock, flags);
-#endif
-
- /* every endpoint has an ed, locate and maybe (re)initialize it */
- ed = ed_get(ahcd, urb->ep, urb->dev, pipe, urb->interval);
- if (!ed)
- return -ENOMEM;
-
- /* for the private part of the URB we need the number of TDs */
- switch (ed->type) {
- case PIPE_CONTROL:
- if (urb->transfer_buffer_length > TD_DATALEN_MAX)
- /* td_submit_urb() doesn't yet handle these */
- return -EMSGSIZE;
-
- /* 1 TD for setup, 1 for ACK, plus ... */
- td_cnt = 2;
- /* FALLTHROUGH */
- case PIPE_BULK:
- /* one TD for every 4096 Bytes (can be upto 8K) */
- td_cnt += urb->transfer_buffer_length / TD_DATALEN_MAX;
- /* ... and for any remaining bytes ... */
- if ((urb->transfer_buffer_length % TD_DATALEN_MAX) != 0)
- td_cnt++;
- /* ... and maybe a zero length packet to wrap it up */
- if (td_cnt == 0)
- td_cnt++;
- else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
- && (urb->transfer_buffer_length
- % usb_maxpacket(urb->dev, pipe,
- usb_pipeout (pipe))) == 0)
- td_cnt++;
- break;
- case PIPE_INTERRUPT:
- /*
- * for Interrupt IN/OUT transactions, each ED contains
- * only 1 TD.
- * TODO: check transfer_buffer_length?
- */
- td_cnt = 1;
- break;
- case PIPE_ISOCHRONOUS:
- /* number of packets from URB */
- td_cnt = urb->number_of_packets;
- break;
- }
-
- urb_priv = urb_priv_alloc(ahcd, td_cnt, mem_flags);
- if (!urb_priv)
- return -ENOMEM;
-
- urb_priv->ed = ed;
-
- spin_lock_irqsave(&ahcd->lock, flags);
- /* don't submit to a dead HC */
- if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
- ret = -ENODEV;
- goto fail;
- }
- if (!HC_IS_RUNNING(hcd->state)) {
- ret = -ENODEV;
- goto fail;
- }
-
- ret = usb_hcd_link_urb_to_ep(hcd, urb);
- if (ret)
- goto fail;
-
- /* schedule the ed if needed */
- if (ed->state == ED_IDLE) {
- ret = ed_schedule(ahcd, ed);
- if (ret < 0) {
- usb_hcd_unlink_urb_from_ep(hcd, urb);
- goto fail;
- }
- if (ed->type == PIPE_ISOCHRONOUS) {
- u16 frame = admhc_frame_no(ahcd);
-
- /* delay a few frames before the first TD */
- frame += max_t (u16, 8, ed->interval);
- frame &= ~(ed->interval - 1);
- frame |= ed->branch;
- urb->start_frame = frame;
-
- /* yes, only URB_ISO_ASAP is supported, and
- * urb->start_frame is never used as input.
- */
- }
- } else if (ed->type == PIPE_ISOCHRONOUS)
- urb->start_frame = ed->last_iso + ed->interval;
-
- /* fill the TDs and link them to the ed; and
- * enable that part of the schedule, if needed
- * and update count of queued periodic urbs
- */
- urb->hcpriv = urb_priv;
- td_submit_urb(ahcd, urb);
-
-#ifdef ADMHC_VERBOSE_DEBUG
- admhc_dump_ed(ahcd, "admhc_urb_enqueue", urb_priv->ed, 1);
-#endif
-
-fail:
- if (ret)
- urb_priv_free(ahcd, urb_priv);
-
- spin_unlock_irqrestore(&ahcd->lock, flags);
- return ret;
-}
-
-/*
- * decouple the URB from the HC queues (TDs, urb_priv);
- * reporting is always done
- * asynchronously, and we might be dealing with an urb that's
- * partially transferred, or an ED with other urbs being unlinked.
- */
-static int admhc_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
- int status)
-{
- struct admhcd *ahcd = hcd_to_admhcd(hcd);
- unsigned long flags;
- int ret;
-
- spin_lock_irqsave(&ahcd->lock, flags);
-
-#ifdef ADMHC_VERBOSE_DEBUG
- urb_print(ahcd, urb, "DEQUEUE", 1, status);
-#endif
- ret = usb_hcd_check_unlink_urb(hcd, urb, status);
- if (ret) {
- /* Do nothing */
- ;
- } else if (HC_IS_RUNNING(hcd->state)) {
- struct urb_priv *urb_priv;
-
- /* Unless an IRQ completed the unlink while it was being
- * handed to us, flag it for unlink and giveback, and force
- * some upcoming INTR_SF to call finish_unlinks()
- */
- urb_priv = urb->hcpriv;
- if (urb_priv) {
- if (urb_priv->ed->state == ED_OPER)
- start_ed_unlink(ahcd, urb_priv->ed);
- }
- } else {
- /*
- * with HC dead, we won't respect hc queue pointers
- * any more ... just clean up every urb's memory.
- */
- if (urb->hcpriv)
- finish_urb(ahcd, urb, status);
- }
- spin_unlock_irqrestore(&ahcd->lock, flags);
-
- return ret;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* frees config/altsetting state for endpoints,
- * including ED memory, dummy TD, and bulk/intr data toggle
- */
-
-static void admhc_endpoint_disable(struct usb_hcd *hcd,
- struct usb_host_endpoint *ep)
-{
- struct admhcd *ahcd = hcd_to_admhcd(hcd);
- unsigned long flags;
- struct ed *ed = ep->hcpriv;
- unsigned limit = 1000;
-
- /* ASSERT: any requests/urbs are being unlinked */
- /* ASSERT: nobody can be submitting urbs for this any more */
-
- if (!ed)
- return;
-
-#ifdef ADMHC_VERBOSE_DEBUG
- spin_lock_irqsave(&ahcd->lock, flags);
- admhc_dump_ed(ahcd, "EP-DISABLE", ed, 1);
- spin_unlock_irqrestore(&ahcd->lock, flags);
-#endif
-
-rescan:
- spin_lock_irqsave(&ahcd->lock, flags);
-
- if (!HC_IS_RUNNING(hcd->state)) {
-sanitize:
- ed->state = ED_IDLE;
- finish_unlinks(ahcd, 0);
- }
-
- switch (ed->state) {
- case ED_UNLINK: /* wait for hw to finish? */
- /* major IRQ delivery trouble loses INTR_SOFI too... */
- if (limit-- == 0) {
- admhc_warn(ahcd, "IRQ INTR_SOFI lossage\n");
- goto sanitize;
- }
- spin_unlock_irqrestore(&ahcd->lock, flags);
- schedule_timeout_uninterruptible(1);
- goto rescan;
- case ED_IDLE: /* fully unlinked */
- if (list_empty(&ed->td_list)) {
- td_free (ahcd, ed->dummy);
- ed_free (ahcd, ed);
- break;
- }
- /* else FALL THROUGH */
- default:
- /* caller was supposed to have unlinked any requests;
- * that's not our job. can't recover; must leak ed.
- */
- admhc_err(ahcd, "leak ed %p (#%02x) state %d%s\n",
- ed, ep->desc.bEndpointAddress, ed->state,
- list_empty(&ed->td_list) ? "" : " (has tds)");
- td_free(ahcd, ed->dummy);
- break;
- }
-
- ep->hcpriv = NULL;
-
- spin_unlock_irqrestore(&ahcd->lock, flags);
- return;
-}
-
-static int admhc_get_frame_number(struct usb_hcd *hcd)
-{
- struct admhcd *ahcd = hcd_to_admhcd(hcd);
-
- return admhc_frame_no(ahcd);
-}
-
-static void admhc_usb_reset(struct admhcd *ahcd)
-{
-#if 0
- ahcd->hc_control = admhc_readl(ahcd, &ahcd->regs->control);
- ahcd->hc_control &= OHCI_CTRL_RWC;
- admhc_writel(ahcd, ahcd->hc_control, &ahcd->regs->control);
-#else
- /* FIXME */
- ahcd->host_control = ADMHC_BUSS_RESET;
- admhc_writel(ahcd, ahcd->host_control ,&ahcd->regs->host_control);
-#endif
-}
-
-/* admhc_shutdown forcibly disables IRQs and DMA, helping kexec and
- * other cases where the next software may expect clean state from the
- * "firmware". this is bus-neutral, unlike shutdown() methods.
- */
-static void
-admhc_shutdown(struct usb_hcd *hcd)
-{
- struct admhcd *ahcd;
-
- ahcd = hcd_to_admhcd(hcd);
- admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
- admhc_dma_disable(ahcd);
- admhc_usb_reset(ahcd);
- /* flush the writes */
- admhc_writel_flush(ahcd);
-}
-
-/*-------------------------------------------------------------------------*
- * HC functions
- *-------------------------------------------------------------------------*/
-
-static void admhc_eds_cleanup(struct admhcd *ahcd)
-{
- if (ahcd->ed_tails[PIPE_INTERRUPT]) {
- ed_free(ahcd, ahcd->ed_tails[PIPE_INTERRUPT]);
- ahcd->ed_tails[PIPE_INTERRUPT] = NULL;
- }
-
- if (ahcd->ed_tails[PIPE_ISOCHRONOUS]) {
- ed_free(ahcd, ahcd->ed_tails[PIPE_ISOCHRONOUS]);
- ahcd->ed_tails[PIPE_ISOCHRONOUS] = NULL;
- }
-
- if (ahcd->ed_tails[PIPE_CONTROL]) {
- ed_free(ahcd, ahcd->ed_tails[PIPE_CONTROL]);
- ahcd->ed_tails[PIPE_CONTROL] = NULL;
- }
-
- if (ahcd->ed_tails[PIPE_BULK]) {
- ed_free(ahcd, ahcd->ed_tails[PIPE_BULK]);
- ahcd->ed_tails[PIPE_BULK] = NULL;
- }
-
- ahcd->ed_head = NULL;
-}
-
-#define ED_DUMMY_INFO (ED_SPEED_FULL | ED_SKIP)
-
-static int admhc_eds_init(struct admhcd *ahcd)
-{
- struct ed *ed;
-
- ed = ed_create(ahcd, PIPE_INTERRUPT, ED_DUMMY_INFO);
- if (!ed)
- goto err;
-
- ahcd->ed_tails[PIPE_INTERRUPT] = ed;
-
- ed = ed_create(ahcd, PIPE_ISOCHRONOUS, ED_DUMMY_INFO);
- if (!ed)
- goto err;
-
- ahcd->ed_tails[PIPE_ISOCHRONOUS] = ed;
- ed->ed_prev = ahcd->ed_tails[PIPE_INTERRUPT];
- ahcd->ed_tails[PIPE_INTERRUPT]->ed_next = ed;
- ahcd->ed_tails[PIPE_INTERRUPT]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
-
- ed = ed_create(ahcd, PIPE_CONTROL, ED_DUMMY_INFO);
- if (!ed)
- goto err;
-
- ahcd->ed_tails[PIPE_CONTROL] = ed;
- ed->ed_prev = ahcd->ed_tails[PIPE_ISOCHRONOUS];
- ahcd->ed_tails[PIPE_ISOCHRONOUS]->ed_next = ed;
- ahcd->ed_tails[PIPE_ISOCHRONOUS]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
-
- ed = ed_create(ahcd, PIPE_BULK, ED_DUMMY_INFO);
- if (!ed)
- goto err;
-
- ahcd->ed_tails[PIPE_BULK] = ed;
- ed->ed_prev = ahcd->ed_tails[PIPE_CONTROL];
- ahcd->ed_tails[PIPE_CONTROL]->ed_next = ed;
- ahcd->ed_tails[PIPE_CONTROL]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
-
- ahcd->ed_head = ahcd->ed_tails[PIPE_INTERRUPT];
-
-#ifdef ADMHC_VERBOSE_DEBUG
- admhc_dump_ed(ahcd, "ed intr", ahcd->ed_tails[PIPE_INTERRUPT], 1);
- admhc_dump_ed(ahcd, "ed isoc", ahcd->ed_tails[PIPE_ISOCHRONOUS], 1);
- admhc_dump_ed(ahcd, "ed ctrl", ahcd->ed_tails[PIPE_CONTROL], 1);
- admhc_dump_ed(ahcd, "ed bulk", ahcd->ed_tails[PIPE_BULK], 1);
-#endif
-
- return 0;
-
-err:
- admhc_eds_cleanup(ahcd);
- return -ENOMEM;
-}
-
-/* init memory, and kick BIOS/SMM off */
-
-static int admhc_init(struct admhcd *ahcd)
-{
- struct usb_hcd *hcd = admhcd_to_hcd(ahcd);
- int ret;
-
- admhc_disable(ahcd);
- ahcd->regs = hcd->regs;
-
- /* Disable HC interrupts */
- admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
-
- /* Read the number of ports unless overridden */
- if (ahcd->num_ports == 0)
- ahcd->num_ports = admhc_read_rhdesc(ahcd) & ADMHC_RH_NUMP;
-
- ret = admhc_mem_init(ahcd);
- if (ret)
- goto err;
-
- /* init dummy endpoints */
- ret = admhc_eds_init(ahcd);
- if (ret)
- goto err;
-
- create_debug_files(ahcd);
-
- return 0;
-
-err:
- admhc_stop(hcd);
- return ret;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* Start an OHCI controller, set the BUS operational
- * resets USB and controller
- * enable interrupts
- */
-static int admhc_run(struct admhcd *ahcd)
-{
- u32 temp;
- int first = ahcd->fminterval == 0;
- struct usb_hcd *hcd = admhcd_to_hcd(ahcd);
-
- admhc_disable(ahcd);
-
- /* boot firmware should have set this up (5.1.1.3.1) */
- if (first) {
- temp = admhc_readl(ahcd, &ahcd->regs->fminterval);
- ahcd->fminterval = temp & ADMHC_SFI_FI_MASK;
- if (ahcd->fminterval != FI)
- admhc_dbg(ahcd, "fminterval delta %d\n",
- ahcd->fminterval - FI);
- ahcd->fminterval |=
- (FSLDP(ahcd->fminterval) << ADMHC_SFI_FSLDP_SHIFT);
- /* also: power/overcurrent flags in rhdesc */
- }
-
-#if 0 /* TODO: not applicable */
- /* Reset USB nearly "by the book". RemoteWakeupConnected was
- * saved if boot firmware (BIOS/SMM/...) told us it's connected,
- * or if bus glue did the same (e.g. for PCI add-in cards with
- * PCI PM support).
- */
- if ((ahcd->hc_control & OHCI_CTRL_RWC) != 0
- && !device_may_wakeup(hcd->self.controller))
- device_init_wakeup(hcd->self.controller, 1);
-#endif
-
- switch (ahcd->host_control & ADMHC_HC_BUSS) {
- case ADMHC_BUSS_OPER:
- temp = 0;
- break;
- case ADMHC_BUSS_SUSPEND:
- /* FALLTHROUGH ? */
- case ADMHC_BUSS_RESUME:
- ahcd->host_control = ADMHC_BUSS_RESUME;
- temp = 10 /* msec wait */;
- break;
- /* case ADMHC_BUSS_RESET: */
- default:
- ahcd->host_control = ADMHC_BUSS_RESET;
- temp = 50 /* msec wait */;
- break;
- }
- admhc_writel(ahcd, ahcd->host_control, &ahcd->regs->host_control);
-
- /* flush the writes */
- admhc_writel_flush(ahcd);
-
- msleep(temp);
- temp = admhc_read_rhdesc(ahcd);
- if (!(temp & ADMHC_RH_NPS)) {
- /* power down each port */
- for (temp = 0; temp < ahcd->num_ports; temp++)
- admhc_write_portstatus(ahcd, temp, ADMHC_PS_CPP);
- }
- /* flush those writes */
- admhc_writel_flush(ahcd);
-
- /* 2msec timelimit here means no irqs/preempt */
- spin_lock_irq(&ahcd->lock);
-
- admhc_writel(ahcd, ADMHC_CTRL_SR, &ahcd->regs->gencontrol);
- temp = 30; /* ... allow extra time */
- while ((admhc_readl(ahcd, &ahcd->regs->gencontrol) & ADMHC_CTRL_SR) != 0) {
- if (--temp == 0) {
- spin_unlock_irq(&ahcd->lock);
- admhc_err(ahcd, "USB HC reset timed out!\n");
- return -1;
- }
- udelay(1);
- }
-
- /* enable HOST mode, before access any host specific register */
- admhc_writel(ahcd, ADMHC_CTRL_UHFE, &ahcd->regs->gencontrol);
-
- /* Tell the controller where the descriptor list is */
- admhc_writel(ahcd, (u32)ahcd->ed_head->dma, &ahcd->regs->hosthead);
-
- periodic_reinit(ahcd);
-
- /* use rhsc irqs after khubd is fully initialized */
- hcd->poll_rh = 1;
- hcd->uses_new_polling = 1;
-
-#if 0
- /* wake on ConnectStatusChange, matching external hubs */
- admhc_writel(ahcd, RH_HS_DRWE, &ahcd->regs->roothub.status);
-#else
- /* FIXME roothub_write_status (ahcd, ADMHC_RH_DRWE); */
-#endif
-
- /* Choose the interrupts we care about now, others later on demand */
- admhc_intr_ack(ahcd, ~0);
- admhc_intr_enable(ahcd, ADMHC_INTR_INIT);
-
- admhc_writel(ahcd, ADMHC_RH_NPS | ADMHC_RH_LPSC, &ahcd->regs->rhdesc);
-
- /* flush those writes */
- admhc_writel_flush(ahcd);
-
- /* start controller operations */
- ahcd->host_control = ADMHC_BUSS_OPER;
- admhc_writel(ahcd, ahcd->host_control, &ahcd->regs->host_control);
-
- temp = 20;
- while ((admhc_readl(ahcd, &ahcd->regs->host_control)
- & ADMHC_HC_BUSS) != ADMHC_BUSS_OPER) {
- if (--temp == 0) {
- spin_unlock_irq(&ahcd->lock);
- admhc_err(ahcd, "unable to setup operational mode!\n");
- return -1;
- }
- mdelay(1);
- }
-
- hcd->state = HC_STATE_RUNNING;
-
- ahcd->next_statechange = jiffies + STATECHANGE_DELAY;
-
-#if 0
- /* FIXME: enabling DMA is always failed here for an unknown reason */
- admhc_dma_enable(ahcd);
-
- temp = 200;
- while ((admhc_readl(ahcd, &ahcd->regs->host_control)
- & ADMHC_HC_DMAE) != ADMHC_HC_DMAE) {
- if (--temp == 0) {
- spin_unlock_irq(&ahcd->lock);
- admhc_err(ahcd, "unable to enable DMA!\n");
- admhc_dump(ahcd, 1);
- return -1;
- }
- mdelay(1);
- }
-
-#endif
-
- spin_unlock_irq(&ahcd->lock);
-
- mdelay(ADMHC_POTPGT);
-
- return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* an interrupt happens */
-
-static irqreturn_t admhc_irq(struct usb_hcd *hcd)
-{
- struct admhcd *ahcd = hcd_to_admhcd(hcd);
- struct admhcd_regs __iomem *regs = ahcd->regs;
- u32 ints;
-
- ints = admhc_readl(ahcd, ®s->int_status);
- if ((ints & ADMHC_INTR_INTA) == 0) {
- /* no unmasked interrupt status is set */
- return IRQ_NONE;
- }
-
- ints &= admhc_readl(ahcd, ®s->int_enable);
-
- if (ints & ADMHC_INTR_FATI) {
- /* e.g. due to PCI Master/Target Abort */
- admhc_disable(ahcd);
- admhc_err(ahcd, "Fatal Error, controller disabled\n");
- admhc_dump(ahcd, 1);
- admhc_usb_reset(ahcd);
- }
-
- if (ints & ADMHC_INTR_BABI) {
- admhc_intr_disable(ahcd, ADMHC_INTR_BABI);
- admhc_intr_ack(ahcd, ADMHC_INTR_BABI);
- admhc_err(ahcd, "Babble Detected\n");
- }
-
- if (ints & ADMHC_INTR_INSM) {
- admhc_vdbg(ahcd, "Root Hub Status Change\n");
- ahcd->next_statechange = jiffies + STATECHANGE_DELAY;
- admhc_intr_ack(ahcd, ADMHC_INTR_RESI | ADMHC_INTR_INSM);
-
- /* NOTE: Vendors didn't always make the same implementation
- * choices for RHSC. Many followed the spec; RHSC triggers
- * on an edge, like setting and maybe clearing a port status
- * change bit. With others it's level-triggered, active
- * until khubd clears all the port status change bits. We'll
- * always disable it here and rely on polling until khubd
- * re-enables it.
- */
- admhc_intr_disable(ahcd, ADMHC_INTR_INSM);
- usb_hcd_poll_rh_status(hcd);
- } else if (ints & ADMHC_INTR_RESI) {
- /* For connect and disconnect events, we expect the controller
- * to turn on RHSC along with RD. But for remote wakeup events
- * this might not happen.
- */
- admhc_vdbg(ahcd, "Resume Detect\n");
- admhc_intr_ack(ahcd, ADMHC_INTR_RESI);
- hcd->poll_rh = 1;
- if (ahcd->autostop) {
- spin_lock(&ahcd->lock);
- admhc_rh_resume(ahcd);
- spin_unlock(&ahcd->lock);
- } else
- usb_hcd_resume_root_hub(hcd);
- }
-
- if (ints & ADMHC_INTR_TDC) {
- admhc_vdbg(ahcd, "Transfer Descriptor Complete\n");
- admhc_intr_ack(ahcd, ADMHC_INTR_TDC);
- if (HC_IS_RUNNING(hcd->state))
- admhc_intr_disable(ahcd, ADMHC_INTR_TDC);
- spin_lock(&ahcd->lock);
- admhc_td_complete(ahcd);
- spin_unlock(&ahcd->lock);
- if (HC_IS_RUNNING(hcd->state))
- admhc_intr_enable(ahcd, ADMHC_INTR_TDC);
- }
-
- if (ints & ADMHC_INTR_SO) {
- /* could track INTR_SO to reduce available PCI/... bandwidth */
- admhc_vdbg(ahcd, "Schedule Overrun\n");
- }
-
-#if 1
- spin_lock(&ahcd->lock);
- if (ahcd->ed_rm_list)
- finish_unlinks(ahcd, admhc_frame_no(ahcd));
-
- if ((ints & ADMHC_INTR_SOFI) != 0 && !ahcd->ed_rm_list
- && HC_IS_RUNNING(hcd->state))
- admhc_intr_disable(ahcd, ADMHC_INTR_SOFI);
- spin_unlock(&ahcd->lock);
-#else
- if (ints & ADMHC_INTR_SOFI) {
- admhc_vdbg(ahcd, "Start Of Frame\n");
- spin_lock(&ahcd->lock);
-
- /* handle any pending ED removes */
- finish_unlinks(ahcd, admhc_frameno(ahcd));
-
- /* leaving INTR_SOFI enabled when there's still unlinking
- * to be done in the (next frame).
- */
- if ((ahcd->ed_rm_list == NULL) ||
- HC_IS_RUNNING(hcd->state) == 0)
- /*
- * disable INTR_SOFI if there are no unlinking to be
- * done (in the next frame)
- */
- admhc_intr_disable(ahcd, ADMHC_INTR_SOFI);
-
- spin_unlock(&ahcd->lock);
- }
-#endif
-
- if (HC_IS_RUNNING(hcd->state)) {
- admhc_intr_ack(ahcd, ints);
- admhc_intr_enable(ahcd, ADMHC_INTR_MIE);
- admhc_writel_flush(ahcd);
- }
-
- return IRQ_HANDLED;
-}
-
-/*-------------------------------------------------------------------------*/
-
-static void admhc_stop(struct usb_hcd *hcd)
-{
- struct admhcd *ahcd = hcd_to_admhcd(hcd);
-
- admhc_dump(ahcd, 1);
-
- flush_scheduled_work();
-
- admhc_usb_reset(ahcd);
- admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
-
- free_irq(hcd->irq, hcd);
- hcd->irq = -1;
-
- remove_debug_files(ahcd);
- admhc_eds_cleanup(ahcd);
- admhc_mem_cleanup(ahcd);
-}
-
-/*-------------------------------------------------------------------------*/
-
-#ifdef CONFIG_ADM5120
-#include "adm5120-drv.c"
-#define PLATFORM_DRIVER usb_hcd_adm5120_driver
-#endif
-
-#if !defined(PLATFORM_DRIVER)
-#error "missing bus glue for admhc-hcd"
-#endif
-
-#define DRIVER_INFO DRIVER_DESC " version " DRIVER_VERSION
-
-static int __init admhc_hcd_mod_init(void)
-{
- int ret = 0;
-
- if (usb_disabled())
- return -ENODEV;
-
- pr_info("%s: " DRIVER_INFO "\n", hcd_name);
- pr_info("%s: block sizes: ed %Zd td %Zd\n", hcd_name,
- sizeof (struct ed), sizeof (struct td));
-
-#ifdef DEBUG
- admhc_debug_root = debugfs_create_dir("admhc", NULL);
- if (!admhc_debug_root) {
- ret = -ENOENT;
- goto error_debug;
- }
-#endif
-
-#ifdef PLATFORM_DRIVER
- ret = platform_driver_register(&PLATFORM_DRIVER);
- if (ret < 0)
- goto error_platform;
-#endif
-
- return ret;
-
-#ifdef PLATFORM_DRIVER
- platform_driver_unregister(&PLATFORM_DRIVER);
-error_platform:
-#endif
-
-#ifdef DEBUG
- debugfs_remove(admhc_debug_root);
- admhc_debug_root = NULL;
-error_debug:
-#endif
- return ret;
-}
-module_init(admhc_hcd_mod_init);
-
-static void __exit admhc_hcd_mod_exit(void)
-{
- platform_driver_unregister(&PLATFORM_DRIVER);
-#ifdef DEBUG
- debugfs_remove(admhc_debug_root);
-#endif
-}
-module_exit(admhc_hcd_mod_exit);
-
-MODULE_AUTHOR(DRIVER_AUTHOR);
-MODULE_DESCRIPTION(DRIVER_INFO);
-MODULE_VERSION(DRIVER_VERSION);
-MODULE_LICENSE("GPL v2");
+++ /dev/null
-/*
- * ADM5120 HCD (Host Controller Driver) for USB
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This file was derived from: drivers/usb/host/ohci-hub.c
- * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
- * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-/*-------------------------------------------------------------------------*/
-
-/*
- * ADM5120 Root Hub ... the nonsharable stuff
- */
-
-#define dbg_port(hc,label,num,value) \
- admhc_dbg(hc, \
- "%s port%d " \
- "= 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s\n", \
- label, num, value, \
- (value & ADMHC_PS_PRSC) ? " PRSC" : "", \
- (value & ADMHC_PS_OCIC) ? " OCIC" : "", \
- (value & ADMHC_PS_PSSC) ? " PSSC" : "", \
- (value & ADMHC_PS_PESC) ? " PESC" : "", \
- (value & ADMHC_PS_CSC) ? " CSC" : "", \
- \
- (value & ADMHC_PS_LSDA) ? " LSDA" : "", \
- (value & ADMHC_PS_PPS) ? " PPS" : "", \
- (value & ADMHC_PS_PRS) ? " PRS" : "", \
- (value & ADMHC_PS_POCI) ? " POCI" : "", \
- (value & ADMHC_PS_PSS) ? " PSS" : "", \
- \
- (value & ADMHC_PS_PES) ? " PES" : "", \
- (value & ADMHC_PS_CCS) ? " CCS" : "" \
- );
-
-#define dbg_port_write(hc,label,num,value) \
- admhc_dbg(hc, \
- "%s port%d " \
- "= 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s\n", \
- label, num, value, \
- (value & ADMHC_PS_PRSC) ? " PRSC" : "", \
- (value & ADMHC_PS_OCIC) ? " OCIC" : "", \
- (value & ADMHC_PS_PSSC) ? " PSSC" : "", \
- (value & ADMHC_PS_PESC) ? " PESC" : "", \
- (value & ADMHC_PS_CSC) ? " CSC" : "", \
- \
- (value & ADMHC_PS_CPP) ? " CPP" : "", \
- (value & ADMHC_PS_SPP) ? " SPP" : "", \
- (value & ADMHC_PS_SPR) ? " SPR" : "", \
- (value & ADMHC_PS_CPS) ? " CPS" : "", \
- (value & ADMHC_PS_SPS) ? " SPS" : "", \
- \
- (value & ADMHC_PS_SPE) ? " SPE" : "", \
- (value & ADMHC_PS_CPE) ? " CPE" : "" \
- );
-
-/*-------------------------------------------------------------------------*/
-
-/* hcd->hub_irq_enable() */
-static void admhc_hub_irq_enable(struct usb_hcd *hcd)
-{
- struct admhcd *ahcd = hcd_to_admhcd(hcd);
-
- spin_lock_irq(&ahcd->lock);
- if (!ahcd->autostop)
- del_timer(&hcd->rh_timer); /* Prevent next poll */
- admhc_intr_enable(ahcd, ADMHC_INTR_INSM);
- spin_unlock_irq(&ahcd->lock);
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* build "status change" packet (one or two bytes) from HC registers */
-
-static int
-admhc_hub_status_data(struct usb_hcd *hcd, char *buf)
-{
- struct admhcd *ahcd = hcd_to_admhcd(hcd);
- int i, changed = 0, length = 1;
- int any_connected = 0;
- unsigned long flags;
- u32 status;
-
- spin_lock_irqsave(&ahcd->lock, flags);
- if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags))
- goto done;
-
- /* init status */
- status = admhc_read_rhdesc(ahcd);
- if (status & (ADMHC_RH_LPSC | ADMHC_RH_OCIC))
- buf [0] = changed = 1;
- else
- buf [0] = 0;
- if (ahcd->num_ports > 7) {
- buf [1] = 0;
- length++;
- }
-
- /* look at each port */
- for (i = 0; i < ahcd->num_ports; i++) {
- status = admhc_read_portstatus(ahcd, i);
-
- /* can't autostop if ports are connected */
- any_connected |= (status & ADMHC_PS_CCS);
-
- if (status & (ADMHC_PS_CSC | ADMHC_PS_PESC | ADMHC_PS_PSSC
- | ADMHC_PS_OCIC | ADMHC_PS_PRSC)) {
- changed = 1;
- if (i < 7)
- buf [0] |= 1 << (i + 1);
- else
- buf [1] |= 1 << (i - 7);
- }
- }
-
- hcd->poll_rh = admhc_root_hub_state_changes(ahcd, changed,
- any_connected);
-
-done:
- spin_unlock_irqrestore(&ahcd->lock, flags);
-
- return changed ? length : 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-static int admhc_get_hub_descriptor(struct admhcd *ahcd, char *buf)
-{
- struct usb_hub_descriptor *desc = (struct usb_hub_descriptor *)buf;
- u32 rh = admhc_read_rhdesc(ahcd);
- u16 temp;
-
- desc->bDescriptorType = USB_DT_HUB; /* Hub-descriptor */
- desc->bPwrOn2PwrGood = ADMHC_POTPGT/2; /* use default value */
- desc->bHubContrCurrent = 0x00; /* 0mA */
-
- desc->bNbrPorts = ahcd->num_ports;
- temp = 1 + (ahcd->num_ports / 8);
- desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
-
- /* FIXME */
- temp = 0;
- if (rh & ADMHC_RH_NPS) /* no power switching? */
- temp |= 0x0002;
- if (rh & ADMHC_RH_PSM) /* per-port power switching? */
- temp |= 0x0001;
- if (rh & ADMHC_RH_NOCP) /* no overcurrent reporting? */
- temp |= 0x0010;
- else if (rh & ADMHC_RH_OCPM) /* per-port overcurrent reporting? */
- temp |= 0x0008;
- desc->wHubCharacteristics = (__force __u16)cpu_to_hc16(ahcd, temp);
-
- /* two bitmaps: ports removable, and usb 1.0 legacy PortPwrCtrlMask */
- desc->bitmap[0] = 0;
- desc->bitmap[0] = ~0;
-
- return 0;
-}
-
-static int admhc_get_hub_status(struct admhcd *ahcd, char *buf)
-{
- struct usb_hub_status *hs = (struct usb_hub_status *)buf;
- u32 t = admhc_read_rhdesc(ahcd);
- u16 status, change;
-
- status = 0;
- status |= (t & ADMHC_RH_LPS) ? HUB_STATUS_LOCAL_POWER : 0;
- status |= (t & ADMHC_RH_OCI) ? HUB_STATUS_OVERCURRENT : 0;
-
- change = 0;
- change |= (t & ADMHC_RH_LPSC) ? HUB_CHANGE_LOCAL_POWER : 0;
- change |= (t & ADMHC_RH_OCIC) ? HUB_CHANGE_OVERCURRENT : 0;
-
- hs->wHubStatus = (__force __u16)cpu_to_hc16(ahcd, status);
- hs->wHubChange = (__force __u16)cpu_to_hc16(ahcd, change);
-
- return 0;
-}
-
-static int admhc_get_port_status(struct admhcd *ahcd, unsigned port, char *buf)
-{
- struct usb_port_status *ps = (struct usb_port_status *)buf;
- u32 t = admhc_read_portstatus(ahcd, port);
- u16 status, change;
-
- status = 0;
- status |= (t & ADMHC_PS_CCS) ? USB_PORT_STAT_CONNECTION : 0;
- status |= (t & ADMHC_PS_PES) ? USB_PORT_STAT_ENABLE : 0;
- status |= (t & ADMHC_PS_PSS) ? USB_PORT_STAT_SUSPEND : 0;
- status |= (t & ADMHC_PS_POCI) ? USB_PORT_STAT_OVERCURRENT : 0;
- status |= (t & ADMHC_PS_PRS) ? USB_PORT_STAT_RESET : 0;
- status |= (t & ADMHC_PS_PPS) ? USB_PORT_STAT_POWER : 0;
- status |= (t & ADMHC_PS_LSDA) ? USB_PORT_STAT_LOW_SPEED : 0;
-
- change = 0;
- change |= (t & ADMHC_PS_CSC) ? USB_PORT_STAT_C_CONNECTION : 0;
- change |= (t & ADMHC_PS_PESC) ? USB_PORT_STAT_C_ENABLE : 0;
- change |= (t & ADMHC_PS_PSSC) ? USB_PORT_STAT_C_SUSPEND : 0;
- change |= (t & ADMHC_PS_OCIC) ? USB_PORT_STAT_C_OVERCURRENT : 0;
- change |= (t & ADMHC_PS_PRSC) ? USB_PORT_STAT_C_RESET : 0;
-
- ps->wPortStatus = (__force __u16)cpu_to_hc16(ahcd, status);
- ps->wPortChange = (__force __u16)cpu_to_hc16(ahcd, change);
-
- return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-#ifdef CONFIG_USB_OTG
-
-static int admhc_start_port_reset(struct usb_hcd *hcd, unsigned port)
-{
- struct admhcd *ahcd = hcd_to_admhcd(hcd);
- u32 status;
-
- if (!port)
- return -EINVAL;
- port--;
-
- /* start port reset before HNP protocol times out */
- status = admhc_read_portstatus(ahcd, port);
- if (!(status & ADMHC_PS_CCS))
- return -ENODEV;
-
- /* khubd will finish the reset later */
- admhc_write_portstatus(ahcd, port, ADMHC_PS_PRS);
- return 0;
-}
-
-static void start_hnp(struct admhcd *ahcd);
-
-#else
-
-#define admhc_start_port_reset NULL
-
-#endif
-
-/*-------------------------------------------------------------------------*/
-
-
-/* See usb 7.1.7.5: root hubs must issue at least 50 msec reset signaling,
- * not necessarily continuous ... to guard against resume signaling.
- * The short timeout is safe for non-root hubs, and is backward-compatible
- * with earlier Linux hosts.
- */
-#ifdef CONFIG_USB_SUSPEND
-#define PORT_RESET_MSEC 50
-#else
-#define PORT_RESET_MSEC 10
-#endif
-
-/* this timer value might be vendor-specific ... */
-#define PORT_RESET_HW_MSEC 10
-
-/* wrap-aware logic morphed from <linux/jiffies.h> */
-#define tick_before(t1,t2) ((s16)(((s16)(t1))-((s16)(t2))) < 0)
-
-/* called from some task, normally khubd */
-static inline int admhc_port_reset(struct admhcd *ahcd, unsigned port)
-{
- u32 t;
-
- admhc_vdbg(ahcd, "reset port%d\n", port);
- t = admhc_read_portstatus(ahcd, port);
- if (!(t & ADMHC_PS_CCS))
- return -ENODEV;
-
- admhc_write_portstatus(ahcd, port, ADMHC_PS_SPR);
- mdelay(10);
- admhc_write_portstatus(ahcd, port, (ADMHC_PS_SPE | ADMHC_PS_CSC));
- mdelay(100);
-
- return 0;
-}
-
-static inline int admhc_port_enable(struct admhcd *ahcd, unsigned port)
-{
- u32 t;
-
- admhc_vdbg(ahcd, "enable port%d\n", port);
- t = admhc_read_portstatus(ahcd, port);
- if (!(t & ADMHC_PS_CCS))
- return -ENODEV;
-
- admhc_write_portstatus(ahcd, port, ADMHC_PS_SPE);
-
- return 0;
-}
-
-static inline int admhc_port_disable(struct admhcd *ahcd, unsigned port)
-{
- u32 t;
-
- admhc_vdbg(ahcd, "disable port%d\n", port);
- t = admhc_read_portstatus(ahcd, port);
- if (!(t & ADMHC_PS_CCS))
- return -ENODEV;
-
- admhc_write_portstatus(ahcd, port, ADMHC_PS_CPE);
-
- return 0;
-}
-
-static inline int admhc_port_write(struct admhcd *ahcd, unsigned port,
- u32 val)
-{
-#ifdef ADMHC_VERBOSE_DEBUG
- dbg_port_write(ahcd, "write", port, val);
-#endif
- admhc_write_portstatus(ahcd, port, val);
-
- return 0;
-}
-
-static int admhc_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
- u16 wIndex, char *buf, u16 wLength)
-{
- struct admhcd *ahcd = hcd_to_admhcd(hcd);
- int ports = hcd_to_bus(hcd)->root_hub->maxchild;
- int ret = 0;
-
- if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)))
- return -ESHUTDOWN;
-
- switch (typeReq) {
- case ClearHubFeature:
- switch (wValue) {
- case C_HUB_OVER_CURRENT:
-#if 0 /* FIXME */
- admhc_writel(ahcd, ADMHC_RH_OCIC,
- &ahcd->regs->roothub.status);
-#endif
- case C_HUB_LOCAL_POWER:
- break;
- default:
- goto error;
- }
- break;
- case ClearPortFeature:
- if (!wIndex || wIndex > ports)
- goto error;
- wIndex--;
-
- switch (wValue) {
- case USB_PORT_FEAT_ENABLE:
- ret = admhc_port_disable(ahcd, wIndex);
- break;
- case USB_PORT_FEAT_SUSPEND:
- ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_CPS);
- break;
- case USB_PORT_FEAT_POWER:
- ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_CPP);
- break;
- case USB_PORT_FEAT_C_CONNECTION:
- ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_CSC);
- break;
- case USB_PORT_FEAT_C_ENABLE:
- ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_PESC);
- break;
- case USB_PORT_FEAT_C_SUSPEND:
- ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_PSSC);
- break;
- case USB_PORT_FEAT_C_OVER_CURRENT:
- ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_OCIC);
- break;
- case USB_PORT_FEAT_C_RESET:
- ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_PRSC);
- break;
- default:
- goto error;
- }
- break;
- case GetHubDescriptor:
- ret = admhc_get_hub_descriptor(ahcd, buf);
- break;
- case GetHubStatus:
- ret = admhc_get_hub_status(ahcd, buf);
- break;
- case GetPortStatus:
- if (!wIndex || wIndex > ports)
- goto error;
- wIndex--;
-
- ret = admhc_get_port_status(ahcd, wIndex, buf);
- break;
- case SetHubFeature:
- switch (wValue) {
- case C_HUB_OVER_CURRENT:
- /* FIXME: this can be cleared, yes? */
- case C_HUB_LOCAL_POWER:
- break;
- default:
- goto error;
- }
- break;
- case SetPortFeature:
- if (!wIndex || wIndex > ports)
- goto error;
- wIndex--;
-
- switch (wValue) {
- case USB_PORT_FEAT_ENABLE:
- ret = admhc_port_enable(ahcd, wIndex);
- break;
- case USB_PORT_FEAT_RESET:
- ret = admhc_port_reset(ahcd, wIndex);
- break;
- case USB_PORT_FEAT_SUSPEND:
-#ifdef CONFIG_USB_OTG
- if (hcd->self.otg_port == (wIndex + 1)
- && hcd->self.b_hnp_enable)
- start_hnp(ahcd);
- else
-#endif
- ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_SPS);
- break;
- case USB_PORT_FEAT_POWER:
- ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_SPP);
- break;
- default:
- goto error;
- }
- break;
-
- default:
-error:
- /* "protocol stall" on error */
- ret = -EPIPE;
- }
-
- return ret;
-}
-
+++ /dev/null
-/*
- * ADM5120 HCD (Host Controller Driver) for USB
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This file was derived from: drivers/usb/host/ohci-mem.c
- * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
- * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-/*-------------------------------------------------------------------------*/
-
-/*
- * OHCI deals with three types of memory:
- * - data used only by the HCD ... kmalloc is fine
- * - async and periodic schedules, shared by HC and HCD ... these
- * need to use dma_pool or dma_alloc_coherent
- * - driver buffers, read/written by HC ... the hcd glue or the
- * device driver provides us with dma addresses
- *
- * There's also "register" data, which is memory mapped.
- * No memory seen by this driver (or any HCD) may be paged out.
- */
-
-/*-------------------------------------------------------------------------*/
-
-static void admhc_hcd_init(struct admhcd *ahcd)
-{
- ahcd->next_statechange = jiffies;
- spin_lock_init(&ahcd->lock);
- INIT_LIST_HEAD(&ahcd->pending);
-}
-
-/*-------------------------------------------------------------------------*/
-
-static int admhc_mem_init(struct admhcd *ahcd)
-{
- ahcd->td_cache = dma_pool_create("admhc_td",
- admhcd_to_hcd(ahcd)->self.controller,
- sizeof(struct td),
- TD_ALIGN, /* byte alignment */
- 0 /* no page-crossing issues */
- );
- if (!ahcd->td_cache)
- goto err;
-
- ahcd->ed_cache = dma_pool_create("admhc_ed",
- admhcd_to_hcd(ahcd)->self.controller,
- sizeof(struct ed),
- ED_ALIGN, /* byte alignment */
- 0 /* no page-crossing issues */
- );
- if (!ahcd->ed_cache)
- goto err_td_cache;
-
- return 0;
-
-err_td_cache:
- dma_pool_destroy(ahcd->td_cache);
- ahcd->td_cache = NULL;
-err:
- return -ENOMEM;
-}
-
-static void admhc_mem_cleanup(struct admhcd *ahcd)
-{
- if (ahcd->td_cache) {
- dma_pool_destroy(ahcd->td_cache);
- ahcd->td_cache = NULL;
- }
-
- if (ahcd->ed_cache) {
- dma_pool_destroy(ahcd->ed_cache);
- ahcd->ed_cache = NULL;
- }
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* ahcd "done list" processing needs this mapping */
-static inline struct td *dma_to_td(struct admhcd *ahcd, dma_addr_t td_dma)
-{
- struct td *td;
-
- td_dma &= TD_MASK;
- td = ahcd->td_hash[TD_HASH_FUNC(td_dma)];
- while (td && td->td_dma != td_dma)
- td = td->td_hash;
-
- return td;
-}
-
-/* TDs ... */
-static struct td *td_alloc(struct admhcd *ahcd, gfp_t mem_flags)
-{
- dma_addr_t dma;
- struct td *td;
-
- td = dma_pool_alloc(ahcd->td_cache, mem_flags, &dma);
- if (!td)
- return NULL;
-
- /* in case ahcd fetches it, make it look dead */
- memset(td, 0, sizeof *td);
- td->hwNextTD = cpu_to_hc32(ahcd, dma);
- td->td_dma = dma;
- /* hashed in td_fill */
-
- return td;
-}
-
-static void td_free(struct admhcd *ahcd, struct td *td)
-{
- struct td **prev = &ahcd->td_hash[TD_HASH_FUNC(td->td_dma)];
-
- while (*prev && *prev != td)
- prev = &(*prev)->td_hash;
- if (*prev)
- *prev = td->td_hash;
-#if 0
- /* TODO: remove */
- else if ((td->hwINFO & cpu_to_hc32(ahcd, TD_DONE)) != 0)
- admhc_dbg (ahcd, "no hash for td %p\n", td);
-#else
- else if ((td->flags & TD_FLAG_DONE) != 0)
- admhc_dbg (ahcd, "no hash for td %p\n", td);
-#endif
- dma_pool_free(ahcd->td_cache, td, td->td_dma);
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* EDs ... */
-static struct ed *ed_alloc(struct admhcd *ahcd, gfp_t mem_flags)
-{
- dma_addr_t dma;
- struct ed *ed;
-
- ed = dma_pool_alloc(ahcd->ed_cache, mem_flags, &dma);
- if (!ed)
- return NULL;
-
- memset(ed, 0, sizeof(*ed));
- ed->dma = dma;
-
- INIT_LIST_HEAD(&ed->td_list);
- INIT_LIST_HEAD(&ed->urb_list);
-
- return ed;
-}
-
-static void ed_free(struct admhcd *ahcd, struct ed *ed)
-{
- dma_pool_free(ahcd->ed_cache, ed, ed->dma);
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* URB priv ... */
-static void urb_priv_free(struct admhcd *ahcd, struct urb_priv *urb_priv)
-{
- int i;
-
- for (i = 0; i < urb_priv->td_cnt; i++)
- if (urb_priv->td[i])
- td_free(ahcd, urb_priv->td[i]);
-
- list_del(&urb_priv->pending);
- kfree(urb_priv);
-}
-
-static struct urb_priv *urb_priv_alloc(struct admhcd *ahcd, int num_tds,
- gfp_t mem_flags)
-{
- struct urb_priv *priv;
-
- /* allocate the private part of the URB */
- priv = kzalloc(sizeof(*priv) + sizeof(struct td) * num_tds, mem_flags);
- if (!priv)
- goto err;
-
- /* allocate the TDs (deferring hash chain updates) */
- for (priv->td_cnt = 0; priv->td_cnt < num_tds; priv->td_cnt++) {
- priv->td[priv->td_cnt] = td_alloc(ahcd, mem_flags);
- if (priv->td[priv->td_cnt] == NULL)
- goto err_free;
- }
-
- INIT_LIST_HEAD(&priv->pending);
-
- return priv;
-
-err_free:
- urb_priv_free(ahcd, priv);
-err:
- return NULL;
-}
+++ /dev/null
-/*
- * ADM5120 HCD (Host Controller Driver) for USB
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This file was derived from fragments of the OHCI driver.
- * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
- * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#define OHCI_SCHED_ENABLES \
- (OHCI_CTRL_CLE|OHCI_CTRL_BLE|OHCI_CTRL_PLE|OHCI_CTRL_IE)
-
-#ifdef CONFIG_PM
-static int admhc_restart(struct admhcd *ahcd);
-
-static int admhc_rh_suspend(struct admhcd *ahcd, int autostop)
-__releases(ahcd->lock)
-__acquires(ahcd->lock)
-{
- int status = 0;
-
- ahcd->hc_control = admhc_readl(ahcd, &ahcd->regs->control);
- switch (ahcd->hc_control & OHCI_CTRL_HCFS) {
- case OHCI_USB_RESUME:
- admhc_dbg(ahcd, "resume/suspend?\n");
- ahcd->hc_control &= ~OHCI_CTRL_HCFS;
- ahcd->hc_control |= OHCI_USB_RESET;
- admhc_writel(ahcd, ahcd->hc_control, &ahcd->ahcd->regs->control);
- (void) admhc_readl(ahcd, &ahcd->regs->control);
- /* FALL THROUGH */
- case OHCI_USB_RESET:
- status = -EBUSY;
- admhc_dbg(ahcd, "needs reinit!\n");
- goto done;
- case OHCI_USB_SUSPEND:
- if (!ahcd->autostop) {
- admhc_dbg(ahcd, "already suspended\n");
- goto done;
- }
- }
- admhc_dbg(ahcd, "%s root hub\n",
- autostop ? "auto-stop" : "suspend");
-
- /* First stop any processing */
- if (!autostop && (ahcd->hc_control & OHCI_SCHED_ENABLES)) {
- ahcd->hc_control &= ~OHCI_SCHED_ENABLES;
- admhc_writel(ahcd, ahcd->hc_control, &ahcd->ahcd->regs->control);
- ahcd->hc_control = admhc_readl(ahcd, &ahcd->regs->control);
- admhc_writel(ahcd, OHCI_INTR_SF, &ahcd->regs->intrstatus);
-
- /* sched disables take effect on the next frame,
- * then the last WDH could take 6+ msec
- */
- admhc_dbg(ahcd, "stopping schedules ...\n");
- ahcd->autostop = 0;
- spin_unlock_irq (&ahcd->lock);
- msleep (8);
- spin_lock_irq(&ahcd->lock);
- }
- dl_done_list (ahcd);
- finish_unlinks (ahcd, admhc_frame_no(ahcd));
-
- /* maybe resume can wake root hub */
- if (device_may_wakeup(&admhcd_to_hcd(ahcd)->self.root_hub->dev) ||
- autostop)
- ahcd->hc_control |= OHCI_CTRL_RWE;
- else {
- admhc_writel(ahcd, OHCI_INTR_RHSC, &ahcd->regs->intrdisable);
- ahcd->hc_control &= ~OHCI_CTRL_RWE;
- }
-
- /* Suspend hub ... this is the "global (to this bus) suspend" mode,
- * which doesn't imply ports will first be individually suspended.
- */
- ahcd->hc_control &= ~OHCI_CTRL_HCFS;
- ahcd->hc_control |= OHCI_USB_SUSPEND;
- admhc_writel(ahcd, ahcd->hc_control, &ahcd->ahcd->regs->control);
- (void) admhc_readl(ahcd, &ahcd->regs->control);
-
- /* no resumes until devices finish suspending */
- if (!autostop) {
- ahcd->next_statechange = jiffies + msecs_to_jiffies (5);
- ahcd->autostop = 0;
- }
-
-done:
- return status;
-}
-
-static inline struct ed *find_head(struct ed *ed)
-{
- /* for bulk and control lists */
- while (ed->ed_prev)
- ed = ed->ed_prev;
- return ed;
-}
-
-/* caller has locked the root hub */
-static int admhc_rh_resume(struct admhcd *ahcd)
-__releases(ahcd->lock)
-__acquires(ahcd->lock)
-{
- struct usb_hcd *hcd = admhcd_to_hcd (ahcd);
- u32 temp, enables;
- int status = -EINPROGRESS;
- int autostopped = ahcd->autostop;
-
- ahcd->autostop = 0;
- ahcd->hc_control = admhc_readl(ahcd, &ahcd->regs->control);
-
- if (ahcd->hc_control & (OHCI_CTRL_IR | OHCI_SCHED_ENABLES)) {
- /* this can happen after resuming a swsusp snapshot */
- if (hcd->state == HC_STATE_RESUMING) {
- admhc_dbg(ahcd, "BIOS/SMM active, control %03x\n",
- ahcd->hc_control);
- status = -EBUSY;
- /* this happens when pmcore resumes HC then root */
- } else {
- admhc_dbg(ahcd, "duplicate resume\n");
- status = 0;
- }
- } else switch (ahcd->hc_control & OHCI_CTRL_HCFS) {
- case OHCI_USB_SUSPEND:
- ahcd->hc_control &= ~(OHCI_CTRL_HCFS|OHCI_SCHED_ENABLES);
- ahcd->hc_control |= OHCI_USB_RESUME;
- admhc_writel(ahcd, ahcd->hc_control, &ahcd->ahcd->regs->control);
- (void) admhc_readl(ahcd, &ahcd->regs->control);
- admhc_dbg(ahcd, "%s root hub\n",
- autostopped ? "auto-start" : "resume");
- break;
- case OHCI_USB_RESUME:
- /* HCFS changes sometime after INTR_RD */
- admhc_dbg(ahcd, "%swakeup root hub\n",
- autostopped ? "auto-" : "");
- break;
- case OHCI_USB_OPER:
- /* this can happen after resuming a swsusp snapshot */
- admhc_dbg(ahcd, "snapshot resume? reinit\n");
- status = -EBUSY;
- break;
- default: /* RESET, we lost power */
- admhc_dbg(ahcd, "lost power\n");
- status = -EBUSY;
- }
- if (status == -EBUSY) {
- if (!autostopped) {
- spin_unlock_irq (&ahcd->lock);
- (void) ahcd_init (ahcd);
- status = admhc_restart (ahcd);
- spin_lock_irq(&ahcd->lock);
- }
- return status;
- }
- if (status != -EINPROGRESS)
- return status;
- if (autostopped)
- goto skip_resume;
- spin_unlock_irq (&ahcd->lock);
-
- /* Some controllers (lucent erratum) need extra-long delays */
- msleep (20 /* usb 11.5.1.10 */ + 12 /* 32 msec counter */ + 1);
-
- temp = admhc_readl(ahcd, &ahcd->regs->control);
- temp &= OHCI_CTRL_HCFS;
- if (temp != OHCI_USB_RESUME) {
- admhc_err (ahcd, "controller won't resume\n");
- spin_lock_irq(&ahcd->lock);
- return -EBUSY;
- }
-
- /* disable old schedule state, reinit from scratch */
- admhc_writel(ahcd, 0, &ahcd->regs->ed_controlhead);
- admhc_writel(ahcd, 0, &ahcd->regs->ed_controlcurrent);
- admhc_writel(ahcd, 0, &ahcd->regs->ed_bulkhead);
- admhc_writel(ahcd, 0, &ahcd->regs->ed_bulkcurrent);
- admhc_writel(ahcd, 0, &ahcd->regs->ed_periodcurrent);
- admhc_writel(ahcd, (u32) ahcd->hcca_dma, &ahcd->ahcd->regs->hcca);
-
- /* Sometimes PCI D3 suspend trashes frame timings ... */
- periodic_reinit(ahcd);
-
- /* the following code is executed with ahcd->lock held and
- * irqs disabled if and only if autostopped is true
- */
-
-skip_resume:
- /* interrupts might have been disabled */
- admhc_writel(ahcd, OHCI_INTR_INIT, &ahcd->regs->int_enable);
- if (ahcd->ed_rm_list)
- admhc_writel(ahcd, OHCI_INTR_SF, &ahcd->regs->int_enable);
-
- /* Then re-enable operations */
- admhc_writel(ahcd, OHCI_USB_OPER, &ahcd->regs->control);
- (void) admhc_readl(ahcd, &ahcd->regs->control);
- if (!autostopped)
- msleep (3);
-
- temp = ahcd->hc_control;
- temp &= OHCI_CTRL_RWC;
- temp |= OHCI_CONTROL_INIT | OHCI_USB_OPER;
- ahcd->hc_control = temp;
- admhc_writel(ahcd, temp, &ahcd->regs->control);
- (void) admhc_readl(ahcd, &ahcd->regs->control);
-
- /* TRSMRCY */
- if (!autostopped) {
- msleep (10);
- spin_lock_irq(&ahcd->lock);
- }
- /* now ahcd->lock is always held and irqs are always disabled */
-
- /* keep it alive for more than ~5x suspend + resume costs */
- ahcd->next_statechange = jiffies + STATECHANGE_DELAY;
-
- /* maybe turn schedules back on */
- enables = 0;
- temp = 0;
- if (!ahcd->ed_rm_list) {
- if (ahcd->ed_controltail) {
- admhc_writel(ahcd,
- find_head (ahcd->ed_controltail)->dma,
- &ahcd->regs->ed_controlhead);
- enables |= OHCI_CTRL_CLE;
- temp |= OHCI_CLF;
- }
- if (ahcd->ed_bulktail) {
- admhc_writel(ahcd, find_head (ahcd->ed_bulktail)->dma,
- &ahcd->regs->ed_bulkhead);
- enables |= OHCI_CTRL_BLE;
- temp |= OHCI_BLF;
- }
- }
- if (hcd->self.bandwidth_isoc_reqs || hcd->self.bandwidth_int_reqs)
- enables |= OHCI_CTRL_PLE|OHCI_CTRL_IE;
- if (enables) {
- admhc_dbg(ahcd, "restarting schedules ... %08x\n", enables);
- ahcd->hc_control |= enables;
- admhc_writel(ahcd, ahcd->hc_control, &ahcd->ahcd->regs->control);
- if (temp)
- admhc_writel(ahcd, temp, &ahcd->regs->cmdstatus);
- (void) admhc_readl(ahcd, &ahcd->regs->control);
- }
-
- return 0;
-}
-
-static int admhc_bus_suspend(struct usb_hcd *hcd)
-{
- struct admhcd *ahcd = hcd_to_admhcd(hcd);
- int rc;
-
- spin_lock_irq(&ahcd->lock);
-
- if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)))
- rc = -ESHUTDOWN;
- else
- rc = admhc_rh_suspend(ahcd, 0);
- spin_unlock_irq(&ahcd->lock);
- return rc;
-}
-
-static int admhc_bus_resume(struct usb_hcd *hcd)
-{
- struct admhcd *ahcd = hcd_to_admhcd(hcd);
- int rc;
-
- if (time_before(jiffies, ahcd->next_statechange))
- msleep(5);
-
- spin_lock_irq(&ahcd->lock);
-
- if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)))
- rc = -ESHUTDOWN;
- else
- rc = admhc_rh_resume(ahcd);
- spin_unlock_irq(&ahcd->lock);
-
- /* poll until we know a device is connected or we autostop */
- if (rc == 0)
- usb_hcd_poll_rh_status(hcd);
- return rc;
-}
-
-/* Carry out polling-, autostop-, and autoresume-related state changes */
-static int admhc_root_hub_state_changes(struct admhcd *ahcd, int changed,
- int any_connected)
-{
- int poll_rh = 1;
-
- switch (ahcd->hc_control & OHCI_CTRL_HCFS) {
-
- case OHCI_USB_OPER:
- /* keep on polling until we know a device is connected
- * and RHSC is enabled */
- if (!ahcd->autostop) {
- if (any_connected ||
- !device_may_wakeup(&admhcd_to_hcd(ahcd)
- ->self.root_hub->dev)) {
- if (admhc_readl(ahcd, &ahcd->regs->int_enable) &
- OHCI_INTR_RHSC)
- poll_rh = 0;
- } else {
- ahcd->autostop = 1;
- ahcd->next_statechange = jiffies + HZ;
- }
-
- /* if no devices have been attached for one second, autostop */
- } else {
- if (changed || any_connected) {
- ahcd->autostop = 0;
- ahcd->next_statechange = jiffies +
- STATECHANGE_DELAY;
- } else if (time_after_eq(jiffies,
- ahcd->next_statechange)
- && !ahcd->ed_rm_list
- && !(ahcd->hc_control &
- OHCI_SCHED_ENABLES)) {
- ahcd_rh_suspend(ahcd, 1);
- }
- }
- break;
-
- /* if there is a port change, autostart or ask to be resumed */
- case OHCI_USB_SUSPEND:
- case OHCI_USB_RESUME:
- if (changed) {
- if (ahcd->autostop)
- admhc_rh_resume(ahcd);
- else
- usb_hcd_resume_root_hub(admhcd_to_hcd(ahcd));
- } else {
- /* everything is idle, no need for polling */
- poll_rh = 0;
- }
- break;
- }
- return poll_rh;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* must not be called from interrupt context */
-static int admhc_restart(struct admhcd *ahcd)
-{
- int temp;
- int i;
- struct urb_priv *priv;
-
- /* mark any devices gone, so they do nothing till khubd disconnects.
- * recycle any "live" eds/tds (and urbs) right away.
- * later, khubd disconnect processing will recycle the other state,
- * (either as disconnect/reconnect, or maybe someday as a reset).
- */
- spin_lock_irq(&ahcd->lock);
- admhc_disable(ahcd);
- usb_root_hub_lost_power(admhcd_to_hcd(ahcd)->self.root_hub);
- if (!list_empty(&ahcd->pending))
- admhc_dbg(ahcd, "abort schedule...\n");
- list_for_each_entry(priv, &ahcd->pending, pending) {
- struct urb *urb = priv->td[0]->urb;
- struct ed *ed = priv->ed;
-
- switch (ed->state) {
- case ED_OPER:
- ed->state = ED_UNLINK;
- ed->hwINFO |= cpu_to_hc32(ahcd, ED_DEQUEUE);
- ed_deschedule (ahcd, ed);
-
- ed->ed_next = ahcd->ed_rm_list;
- ed->ed_prev = NULL;
- ahcd->ed_rm_list = ed;
- /* FALLTHROUGH */
- case ED_UNLINK:
- break;
- default:
- admhc_dbg(ahcd, "bogus ed %p state %d\n",
- ed, ed->state);
- }
-
- if (!urb->unlinked)
- urb->unlinked = -ESHUTDOWN;
- }
- finish_unlinks(ahcd, 0);
- spin_unlock_irq(&ahcd->lock);
-
- /* paranoia, in case that didn't work: */
-
- /* empty the interrupt branches */
- for (i = 0; i < NUM_INTS; i++) ahcd->load[i] = 0;
- for (i = 0; i < NUM_INTS; i++) ahcd->hcca->int_table[i] = 0;
-
- /* no EDs to remove */
- ahcd->ed_rm_list = NULL;
-
- /* empty control and bulk lists */
- ahcd->ed_controltail = NULL;
- ahcd->ed_bulktail = NULL;
-
- if ((temp = admhc_run(ahcd)) < 0) {
- admhc_err(ahcd, "can't restart, %d\n", temp);
- return temp;
- } else {
- /* here we "know" root ports should always stay powered,
- * and that if we try to turn them back on the root hub
- * will respond to CSC processing.
- */
- i = ahcd->num_ports;
- while (i--)
- admhc_writel(ahcd, RH_PS_PSS,
- &ahcd->regs->portstatus[i]);
- admhc_dbg(ahcd, "restart complete\n");
- }
- return 0;
-}
-
-#else /* CONFIG_PM */
-
-static inline int admhc_rh_resume(struct admhcd *ahcd)
-{
- return 0;
-}
-
-/* Carry out polling-related state changes.
- * autostop isn't used when CONFIG_PM is turned off.
- */
-static int admhc_root_hub_state_changes(struct admhcd *ahcd, int changed,
- int any_connected)
-{
- int poll_rh = 1;
-
- /* keep on polling until RHSC is enabled */
- if (admhc_readl(ahcd, &ahcd->regs->int_enable) & ADMHC_INTR_INSM)
- poll_rh = 0;
-
- return poll_rh;
-}
-
-#endif /* CONFIG_PM */
-
+++ /dev/null
-/*
- * ADM5120 HCD (Host Controller Driver) for USB
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This file was derived from: drivers/usb/host/ohci-q.c
- * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
- * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/irq.h>
-
-/*-------------------------------------------------------------------------*/
-
-/*
- * URB goes back to driver, and isn't reissued.
- * It's completely gone from HC data structures.
- * PRECONDITION: ahcd lock held, irqs blocked.
- */
-static void
-finish_urb(struct admhcd *ahcd, struct urb *urb, int status)
-__releases(ahcd->lock)
-__acquires(ahcd->lock)
-{
- urb_priv_free(ahcd, urb->hcpriv);
-
- if (likely(status == -EINPROGRESS))
- status = 0;
-
- switch (usb_pipetype(urb->pipe)) {
- case PIPE_ISOCHRONOUS:
- admhcd_to_hcd(ahcd)->self.bandwidth_isoc_reqs--;
- break;
- case PIPE_INTERRUPT:
- admhcd_to_hcd(ahcd)->self.bandwidth_int_reqs--;
- break;
- }
-
-#ifdef ADMHC_VERBOSE_DEBUG
- urb_print(ahcd, urb, "RET", usb_pipeout (urb->pipe), status);
-#endif
-
- /* urb->complete() can reenter this HCD */
- usb_hcd_unlink_urb_from_ep(admhcd_to_hcd(ahcd), urb);
- spin_unlock(&ahcd->lock);
- usb_hcd_giveback_urb(admhcd_to_hcd(ahcd), urb, status);
- spin_lock(&ahcd->lock);
-}
-
-
-/*-------------------------------------------------------------------------*
- * ED handling functions
- *-------------------------------------------------------------------------*/
-
-#if 0 /* FIXME */
-/* search for the right schedule branch to use for a periodic ed.
- * does some load balancing; returns the branch, or negative errno.
- */
-static int balance(struct admhcd *ahcd, int interval, int load)
-{
- int i, branch = -ENOSPC;
-
- /* iso periods can be huge; iso tds specify frame numbers */
- if (interval > NUM_INTS)
- interval = NUM_INTS;
-
- /* search for the least loaded schedule branch of that period
- * that has enough bandwidth left unreserved.
- */
- for (i = 0; i < interval ; i++) {
- if (branch < 0 || ahcd->load [branch] > ahcd->load [i]) {
- int j;
-
- /* usb 1.1 says 90% of one frame */
- for (j = i; j < NUM_INTS; j += interval) {
- if ((ahcd->load [j] + load) > 900)
- break;
- }
- if (j < NUM_INTS)
- continue;
- branch = i;
- }
- }
- return branch;
-}
-#endif
-
-/*-------------------------------------------------------------------------*/
-
-#if 0 /* FIXME */
-/* both iso and interrupt requests have periods; this routine puts them
- * into the schedule tree in the apppropriate place. most iso devices use
- * 1msec periods, but that's not required.
- */
-static void periodic_link (struct admhcd *ahcd, struct ed *ed)
-{
- unsigned i;
-
- admhc_vdbg (ahcd, "link %sed %p branch %d [%dus.], interval %d\n",
- (ed->hwINFO & cpu_to_hc32(ahcd, ED_ISO)) ? "iso " : "",
- ed, ed->branch, ed->load, ed->interval);
-
- for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
- struct ed **prev = &ahcd->periodic [i];
- __hc32 *prev_p = &ahcd->hcca->int_table [i];
- struct ed *here = *prev;
-
- /* sorting each branch by period (slow before fast)
- * lets us share the faster parts of the tree.
- * (plus maybe: put interrupt eds before iso)
- */
- while (here && ed != here) {
- if (ed->interval > here->interval)
- break;
- prev = &here->ed_next;
- prev_p = &here->hwNextED;
- here = *prev;
- }
- if (ed != here) {
- ed->ed_next = here;
- if (here)
- ed->hwNextED = *prev_p;
- wmb ();
- *prev = ed;
- *prev_p = cpu_to_hc32(ahcd, ed->dma);
- wmb();
- }
- ahcd->load [i] += ed->load;
- }
- admhcd_to_hcd(ahcd)->self.bandwidth_allocated += ed->load / ed->interval;
-}
-#endif
-
-/* link an ed into the HC chain */
-
-static int ed_schedule(struct admhcd *ahcd, struct ed *ed)
-{
- struct ed *old_tail;
-
- if (admhcd_to_hcd(ahcd)->state == HC_STATE_QUIESCING)
- return -EAGAIN;
-
- ed->state = ED_OPER;
-
- old_tail = ahcd->ed_tails[ed->type];
-
- ed->ed_next = old_tail->ed_next;
- if (ed->ed_next) {
- ed->ed_next->ed_prev = ed;
- ed->hwNextED = cpu_to_hc32(ahcd, ed->ed_next->dma);
- }
- ed->ed_prev = old_tail;
-
- old_tail->ed_next = ed;
- old_tail->hwNextED = cpu_to_hc32(ahcd, ed->dma);
-
- ahcd->ed_tails[ed->type] = ed;
-
- admhc_dma_enable(ahcd);
-
- return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-#if 0 /* FIXME */
-/* scan the periodic table to find and unlink this ED */
-static void periodic_unlink (struct admhcd *ahcd, struct ed *ed)
-{
- int i;
-
- for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
- struct ed *temp;
- struct ed **prev = &ahcd->periodic [i];
- __hc32 *prev_p = &ahcd->hcca->int_table [i];
-
- while (*prev && (temp = *prev) != ed) {
- prev_p = &temp->hwNextED;
- prev = &temp->ed_next;
- }
- if (*prev) {
- *prev_p = ed->hwNextED;
- *prev = ed->ed_next;
- }
- ahcd->load [i] -= ed->load;
- }
-
- admhcd_to_hcd(ahcd)->self.bandwidth_allocated -= ed->load / ed->interval;
- admhc_vdbg (ahcd, "unlink %sed %p branch %d [%dus.], interval %d\n",
- (ed->hwINFO & cpu_to_hc32(ahcd, ED_ISO)) ? "iso " : "",
- ed, ed->branch, ed->load, ed->interval);
-}
-#endif
-
-/* unlink an ed from the HC chain.
- * just the link to the ed is unlinked.
- * the link from the ed still points to another operational ed or 0
- * so the HC can eventually finish the processing of the unlinked ed
- * (assuming it already started that, which needn't be true).
- *
- * ED_UNLINK is a transient state: the HC may still see this ED, but soon
- * it won't. ED_SKIP means the HC will finish its current transaction,
- * but won't start anything new. The TD queue may still grow; device
- * drivers don't know about this HCD-internal state.
- *
- * When the HC can't see the ED, something changes ED_UNLINK to one of:
- *
- * - ED_OPER: when there's any request queued, the ED gets rescheduled
- * immediately. HC should be working on them.
- *
- * - ED_IDLE: when there's no TD queue. there's no reason for the HC
- * to care about this ED; safe to disable the endpoint.
- *
- * When finish_unlinks() runs later, after SOF interrupt, it will often
- * complete one or more URB unlinks before making that state change.
- */
-static void ed_deschedule(struct admhcd *ahcd, struct ed *ed)
-{
-
-#ifdef ADMHC_VERBOSE_DEBUG
- admhc_dump_ed(ahcd, "ED-DESCHED", ed, 1);
-#endif
-
- ed->hwINFO |= cpu_to_hc32(ahcd, ED_SKIP);
- wmb();
- ed->state = ED_UNLINK;
-
- /* remove this ED from the HC list */
- ed->ed_prev->hwNextED = ed->hwNextED;
-
- /* and remove it from our list also */
- ed->ed_prev->ed_next = ed->ed_next;
-
- if (ed->ed_next)
- ed->ed_next->ed_prev = ed->ed_prev;
-
- if (ahcd->ed_tails[ed->type] == ed)
- ahcd->ed_tails[ed->type] = ed->ed_prev;
-}
-
-/*-------------------------------------------------------------------------*/
-
-static struct ed *ed_create(struct admhcd *ahcd, unsigned int type, u32 info)
-{
- struct ed *ed;
- struct td *td;
-
- ed = ed_alloc(ahcd, GFP_ATOMIC);
- if (!ed)
- goto err;
-
- /* dummy td; end of td list for this ed */
- td = td_alloc(ahcd, GFP_ATOMIC);
- if (!td)
- goto err_free_ed;
-
- switch (type) {
- case PIPE_INTERRUPT:
- info |= ED_INT;
- break;
- case PIPE_ISOCHRONOUS:
- info |= ED_ISO;
- break;
- }
-
- ed->dummy = td;
- ed->state = ED_IDLE;
- ed->type = type;
-
- ed->hwINFO = cpu_to_hc32(ahcd, info);
- ed->hwTailP = cpu_to_hc32(ahcd, td->td_dma);
- ed->hwHeadP = ed->hwTailP; /* ED_C, ED_H zeroed */
-
- return ed;
-
-err_free_ed:
- ed_free(ahcd, ed);
-err:
- return NULL;
-}
-
-/* get and maybe (re)init an endpoint. init _should_ be done only as part
- * of enumeration, usb_set_configuration() or usb_set_interface().
- */
-static struct ed *ed_get(struct admhcd *ahcd, struct usb_host_endpoint *ep,
- struct usb_device *udev, unsigned int pipe, int interval)
-{
- struct ed *ed;
- unsigned long flags;
-
- spin_lock_irqsave(&ahcd->lock, flags);
-
- ed = ep->hcpriv;
- if (!ed) {
- u32 info;
-
- /* FIXME: usbcore changes dev->devnum before SET_ADDRESS
- * suceeds ... otherwise we wouldn't need "pipe".
- */
- info = usb_pipedevice(pipe);
- info |= (ep->desc.bEndpointAddress & ~USB_DIR_IN) << ED_EN_SHIFT;
- info |= le16_to_cpu(ep->desc.wMaxPacketSize) << ED_MPS_SHIFT;
- if (udev->speed == USB_SPEED_FULL)
- info |= ED_SPEED_FULL;
-
- ed = ed_create(ahcd, usb_pipetype(pipe), info);
- if (ed)
- ep->hcpriv = ed;
- }
-
- spin_unlock_irqrestore(&ahcd->lock, flags);
-
- return ed;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* request unlinking of an endpoint from an operational HC.
- * put the ep on the rm_list
- * real work is done at the next start frame (SOFI) hardware interrupt
- * caller guarantees HCD is running, so hardware access is safe,
- * and that ed->state is ED_OPER
- */
-static void start_ed_unlink(struct admhcd *ahcd, struct ed *ed)
-{
-
-#ifdef ADMHC_VERBOSE_DEBUG
- admhc_dump_ed(ahcd, "ED-UNLINK", ed, 1);
-#endif
-
- ed->hwINFO |= cpu_to_hc32(ahcd, ED_DEQUEUE);
- ed_deschedule(ahcd, ed);
-
- /* add this ED into the remove list */
- ed->ed_rm_next = ahcd->ed_rm_list;
- ahcd->ed_rm_list = ed;
-
- /* enable SOF interrupt */
- admhc_intr_ack(ahcd, ADMHC_INTR_SOFI);
- admhc_intr_enable(ahcd, ADMHC_INTR_SOFI);
- /* flush those writes */
- admhc_writel_flush(ahcd);
-
- /* SOF interrupt might get delayed; record the frame counter value that
- * indicates when the HC isn't looking at it, so concurrent unlinks
- * behave. frame_no wraps every 2^16 msec, and changes right before
- * SOF is triggered.
- */
- ed->tick = admhc_frame_no(ahcd) + 1;
-}
-
-/*-------------------------------------------------------------------------*
- * TD handling functions
- *-------------------------------------------------------------------------*/
-
-/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
-
-static void
-td_fill(struct admhcd *ahcd, u32 info, dma_addr_t data, int len,
- struct urb *urb, int index)
-{
- struct td *td, *td_pt;
- struct urb_priv *urb_priv = urb->hcpriv;
- int hash;
- u32 cbl = 0;
-
-#if 1
- if (index == (urb_priv->td_cnt - 1) &&
- ((urb->transfer_flags & URB_NO_INTERRUPT) == 0))
- cbl |= TD_IE;
-#else
- if (index == (urb_priv->td_cnt - 1))
- cbl |= TD_IE;
-#endif
-
- /* use this td as the next dummy */
- td_pt = urb_priv->td[index];
-
- /* fill the old dummy TD */
- td = urb_priv->td[index] = urb_priv->ed->dummy;
- urb_priv->ed->dummy = td_pt;
-
- td->ed = urb_priv->ed;
- td->next_dl_td = NULL;
- td->index = index;
- td->urb = urb;
- td->data_dma = data;
- if (!len)
- data = 0;
-
- if (data)
- cbl |= (len & TD_BL_MASK);
-
- info |= TD_OWN;
-
- /* setup hardware specific fields */
- td->hwINFO = cpu_to_hc32(ahcd, info);
- td->hwDBP = cpu_to_hc32(ahcd, data);
- td->hwCBL = cpu_to_hc32(ahcd, cbl);
- td->hwNextTD = cpu_to_hc32(ahcd, td_pt->td_dma);
-
- /* append to queue */
- list_add_tail(&td->td_list, &td->ed->td_list);
-
- /* hash it for later reverse mapping */
- hash = TD_HASH_FUNC(td->td_dma);
- td->td_hash = ahcd->td_hash[hash];
- ahcd->td_hash[hash] = td;
-
- /* HC might read the TD (or cachelines) right away ... */
- wmb();
- td->ed->hwTailP = td->hwNextTD;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* Prepare all TDs of a transfer, and queue them onto the ED.
- * Caller guarantees HC is active.
- * Usually the ED is already on the schedule, so TDs might be
- * processed as soon as they're queued.
- */
-static void td_submit_urb(struct admhcd *ahcd, struct urb *urb)
-{
- struct urb_priv *urb_priv = urb->hcpriv;
- dma_addr_t data;
- int data_len = urb->transfer_buffer_length;
- int cnt = 0;
- u32 info = 0;
- int is_out = usb_pipeout(urb->pipe);
- u32 toggle = 0;
-
- /* OHCI handles the bulk/interrupt data toggles itself. We just
- * use the device toggle bits for resetting, and rely on the fact
- * that resetting toggle is meaningless if the endpoint is active.
- */
-
- if (usb_gettoggle(urb->dev, usb_pipeendpoint(urb->pipe), is_out)) {
- toggle = TD_T_CARRY;
- } else {
- toggle = TD_T_DATA0;
- usb_settoggle(urb->dev, usb_pipeendpoint (urb->pipe),
- is_out, 1);
- }
-
- urb_priv->td_idx = 0;
- list_add(&urb_priv->pending, &ahcd->pending);
-
- if (data_len)
- data = urb->transfer_dma;
- else
- data = 0;
-
- /* NOTE: TD_CC is set so we can tell which TDs the HC processed by
- * using TD_CC_GET, as well as by seeing them on the done list.
- * (CC = NotAccessed ... 0x0F, or 0x0E in PSWs for ISO.)
- */
- switch (urb_priv->ed->type) {
- case PIPE_INTERRUPT:
- info = is_out
- ? TD_T_CARRY | TD_SCC_NOTACCESSED | TD_DP_OUT
- : TD_T_CARRY | TD_SCC_NOTACCESSED | TD_DP_IN;
-
- /* setup service interval and starting frame number */
- info |= (urb->start_frame & TD_FN_MASK);
- info |= (urb->interval & TD_ISI_MASK) << TD_ISI_SHIFT;
-
- td_fill(ahcd, info, data, data_len, urb, cnt);
- cnt++;
-
- admhcd_to_hcd(ahcd)->self.bandwidth_int_reqs++;
- break;
-
- case PIPE_BULK:
- info = is_out
- ? TD_SCC_NOTACCESSED | TD_DP_OUT
- : TD_SCC_NOTACCESSED | TD_DP_IN;
-
- /* TDs _could_ transfer up to 8K each */
- while (data_len > TD_DATALEN_MAX) {
- td_fill(ahcd, info | ((cnt) ? TD_T_CARRY : toggle),
- data, TD_DATALEN_MAX, urb, cnt);
- data += TD_DATALEN_MAX;
- data_len -= TD_DATALEN_MAX;
- cnt++;
- }
-
- td_fill(ahcd, info | ((cnt) ? TD_T_CARRY : toggle), data,
- data_len, urb, cnt);
- cnt++;
-
- if ((urb->transfer_flags & URB_ZERO_PACKET)
- && (cnt < urb_priv->td_cnt)) {
- td_fill(ahcd, info | ((cnt) ? TD_T_CARRY : toggle),
- 0, 0, urb, cnt);
- cnt++;
- }
- break;
-
- /* control manages DATA0/DATA1 toggle per-request; SETUP resets it,
- * any DATA phase works normally, and the STATUS ack is special.
- */
- case PIPE_CONTROL:
- /* fill a TD for the setup */
- info = TD_SCC_NOTACCESSED | TD_DP_SETUP | TD_T_DATA0;
- td_fill(ahcd, info, urb->setup_dma, 8, urb, cnt++);
-
- if (data_len > 0) {
- /* fill a TD for the data */
- info = TD_SCC_NOTACCESSED | TD_T_DATA1;
- info |= is_out ? TD_DP_OUT : TD_DP_IN;
- /* NOTE: mishandles transfers >8K, some >4K */
- td_fill(ahcd, info, data, data_len, urb, cnt++);
- }
-
- /* fill a TD for the ACK */
- info = (is_out || data_len == 0)
- ? TD_SCC_NOTACCESSED | TD_DP_IN | TD_T_DATA1
- : TD_SCC_NOTACCESSED | TD_DP_OUT | TD_T_DATA1;
- td_fill(ahcd, info, data, 0, urb, cnt++);
-
- break;
-
- /* ISO has no retransmit, so no toggle;
- * Each TD could handle multiple consecutive frames (interval 1);
- * we could often reduce the number of TDs here.
- */
- case PIPE_ISOCHRONOUS:
- info = is_out
- ? TD_T_CARRY | TD_SCC_NOTACCESSED | TD_DP_OUT
- : TD_T_CARRY | TD_SCC_NOTACCESSED | TD_DP_IN;
-
- for (cnt = 0; cnt < urb->number_of_packets; cnt++) {
- int frame = urb->start_frame;
-
- frame += cnt * urb->interval;
- frame &= TD_FN_MASK;
- td_fill(ahcd, info | frame,
- data + urb->iso_frame_desc[cnt].offset,
- urb->iso_frame_desc[cnt].length, urb, cnt);
- }
- admhcd_to_hcd(ahcd)->self.bandwidth_isoc_reqs++;
- break;
- }
-
- if (urb_priv->td_cnt != cnt)
- admhc_err(ahcd, "bad number of tds created for urb %p\n", urb);
-}
-
-/*-------------------------------------------------------------------------*
- * Done List handling functions
- *-------------------------------------------------------------------------*/
-
-/* calculate transfer length/status and update the urb */
-static int td_done(struct admhcd *ahcd, struct urb *urb, struct td *td)
-{
- struct urb_priv *urb_priv = urb->hcpriv;
- u32 info;
- u32 bl;
- u32 tdDBP;
- int type = usb_pipetype(urb->pipe);
- int cc;
- int status = -EINPROGRESS;
-
- info = hc32_to_cpup(ahcd, &td->hwINFO);
- tdDBP = hc32_to_cpup(ahcd, &td->hwDBP);
- bl = TD_BL_GET(hc32_to_cpup(ahcd, &td->hwCBL));
- cc = TD_CC_GET(info);
-
- /* ISO ... drivers see per-TD length/status */
- if (type == PIPE_ISOCHRONOUS) {
- /* TODO */
- int dlen = 0;
-
- /* NOTE: assumes FC in tdINFO == 0, and that
- * only the first of 0..MAXPSW psws is used.
- */
- if (info & TD_CC) /* hc didn't touch? */
- return status;
-
- if (usb_pipeout(urb->pipe))
- dlen = urb->iso_frame_desc[td->index].length;
- else {
- /* short reads are always OK for ISO */
- if (cc == TD_CC_DATAUNDERRUN)
- cc = TD_CC_NOERROR;
- dlen = tdDBP - td->data_dma + bl;
- }
-
- urb->actual_length += dlen;
- urb->iso_frame_desc[td->index].actual_length = dlen;
- urb->iso_frame_desc[td->index].status = cc_to_error[cc];
-
- if (cc != TD_CC_NOERROR)
- admhc_vdbg (ahcd,
- "urb %p iso td %p (%d) len %d cc %d\n",
- urb, td, 1 + td->index, dlen, cc);
-
- /* BULK, INT, CONTROL ... drivers see aggregate length/status,
- * except that "setup" bytes aren't counted and "short" transfers
- * might not be reported as errors.
- */
- } else {
- /* update packet status if needed (short is normally ok) */
- if (cc == TD_CC_DATAUNDERRUN
- && !(urb->transfer_flags & URB_SHORT_NOT_OK))
- cc = TD_CC_NOERROR;
-
- if (cc != TD_CC_NOERROR && cc < TD_CC_HCD0)
- status = cc_to_error[cc];
-
-
- /* count all non-empty packets except control SETUP packet */
- if ((type != PIPE_CONTROL || td->index != 0) && tdDBP != 0) {
- urb->actual_length += tdDBP - td->data_dma + bl;
- }
-
- if (cc != TD_CC_NOERROR && cc < TD_CC_HCD0)
- admhc_vdbg(ahcd,
- "urb %p td %p (%d) cc %d, len=%d/%d\n",
- urb, td, td->index, cc,
- urb->actual_length,
- urb->transfer_buffer_length);
- }
-
- list_del(&td->td_list);
- urb_priv->td_idx++;
-
- return status;
-}
-
-/*-------------------------------------------------------------------------*/
-
-static inline void
-ed_halted(struct admhcd *ahcd, struct td *td, int cc, struct td *rev)
-{
- struct urb *urb = td->urb;
- struct urb_priv *urb_priv = urb->hcpriv;
- struct ed *ed = td->ed;
- struct list_head *tmp = td->td_list.next;
- __hc32 toggle = ed->hwHeadP & cpu_to_hc32(ahcd, ED_C);
-
- admhc_dump_ed(ahcd, "ed halted", td->ed, 1);
- /* clear ed halt; this is the td that caused it, but keep it inactive
- * until its urb->complete() has a chance to clean up.
- */
- ed->hwINFO |= cpu_to_hc32(ahcd, ED_SKIP);
- wmb();
- ed->hwHeadP &= ~cpu_to_hc32(ahcd, ED_H);
-
- /* Get rid of all later tds from this urb. We don't have
- * to be careful: no errors and nothing was transferred.
- * Also patch the ed so it looks as if those tds completed normally.
- */
- while (tmp != &ed->td_list) {
- struct td *next;
-
- next = list_entry(tmp, struct td, td_list);
- tmp = next->td_list.next;
-
- if (next->urb != urb)
- break;
-
- /* NOTE: if multi-td control DATA segments get supported,
- * this urb had one of them, this td wasn't the last td
- * in that segment (TD_R clear), this ed halted because
- * of a short read, _and_ URB_SHORT_NOT_OK is clear ...
- * then we need to leave the control STATUS packet queued
- * and clear ED_SKIP.
- */
- list_del(&next->td_list);
- urb_priv->td_cnt++;
- ed->hwHeadP = next->hwNextTD | toggle;
- }
-
- /* help for troubleshooting: report anything that
- * looks odd ... that doesn't include protocol stalls
- * (or maybe some other things)
- */
- switch (cc) {
- case TD_CC_DATAUNDERRUN:
- if ((urb->transfer_flags & URB_SHORT_NOT_OK) == 0)
- break;
- /* fallthrough */
- case TD_CC_STALL:
- if (usb_pipecontrol(urb->pipe))
- break;
- /* fallthrough */
- default:
- admhc_dbg (ahcd,
- "urb %p path %s ep%d%s %08x cc %d --> status %d\n",
- urb, urb->dev->devpath,
- usb_pipeendpoint (urb->pipe),
- usb_pipein (urb->pipe) ? "in" : "out",
- hc32_to_cpu(ahcd, td->hwINFO),
- cc, cc_to_error [cc]);
- }
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* there are some urbs/eds to unlink; called in_irq(), with HCD locked */
-static void
-finish_unlinks(struct admhcd *ahcd, u16 tick)
-{
- struct ed *ed, **last;
-
-rescan_all:
- for (last = &ahcd->ed_rm_list, ed = *last; ed != NULL; ed = *last) {
- struct list_head *entry, *tmp;
- int completed, modified;
- __hc32 *prev;
-
- /* only take off EDs that the HC isn't using, accounting for
- * frame counter wraps and EDs with partially retired TDs
- */
- if (likely(HC_IS_RUNNING(admhcd_to_hcd(ahcd)->state))) {
- if (tick_before (tick, ed->tick)) {
-skip_ed:
- last = &ed->ed_rm_next;
- continue;
- }
-#if 0
- if (!list_empty(&ed->td_list)) {
- struct td *td;
- u32 head;
-
- td = list_entry(ed->td_list.next, struct td,
- td_list);
- head = hc32_to_cpu(ahcd, ed->hwHeadP) &
- TD_MASK;
-
- /* INTR_WDH may need to clean up first */
- if (td->td_dma != head)
- goto skip_ed;
- }
-#endif
- }
-
- /* reentrancy: if we drop the schedule lock, someone might
- * have modified this list. normally it's just prepending
- * entries (which we'd ignore), but paranoia won't hurt.
- */
- *last = ed->ed_rm_next;
- ed->ed_rm_next = NULL;
- modified = 0;
-
- /* unlink urbs as requested, but rescan the list after
- * we call a completion since it might have unlinked
- * another (earlier) urb
- *
- * When we get here, the HC doesn't see this ed. But it
- * must not be rescheduled until all completed URBs have
- * been given back to the driver.
- */
-rescan_this:
- completed = 0;
- prev = &ed->hwHeadP;
- list_for_each_safe(entry, tmp, &ed->td_list) {
- struct td *td;
- struct urb *urb;
- struct urb_priv *urb_priv;
- __hc32 savebits;
- int status;
-
- td = list_entry(entry, struct td, td_list);
- urb = td->urb;
- urb_priv = td->urb->hcpriv;
-
- if (!urb->unlinked) {
- prev = &td->hwNextTD;
- continue;
- }
-
- if ((urb_priv) == NULL)
- continue;
-
- /* patch pointer hc uses */
- savebits = *prev & ~cpu_to_hc32(ahcd, TD_MASK);
- *prev = td->hwNextTD | savebits;
-
- /* HC may have partly processed this TD */
-#ifdef ADMHC_VERBOSE_DEBUG
- urb_print(ahcd, urb, "PARTIAL", 0);
-#endif
- status = td_done(ahcd, urb, td);
-
- /* if URB is done, clean up */
- if (urb_priv->td_idx == urb_priv->td_cnt) {
- modified = completed = 1;
- finish_urb(ahcd, urb, status);
- }
- }
- if (completed && !list_empty(&ed->td_list))
- goto rescan_this;
-
- /* ED's now officially unlinked, hc doesn't see */
- ed->state = ED_IDLE;
- ed->hwHeadP &= ~cpu_to_hc32(ahcd, ED_H);
- ed->hwNextED = 0;
- wmb();
- ed->hwINFO &= ~cpu_to_hc32(ahcd, ED_SKIP | ED_DEQUEUE);
-
- /* but if there's work queued, reschedule */
- if (!list_empty(&ed->td_list)) {
- if (HC_IS_RUNNING(admhcd_to_hcd(ahcd)->state))
- ed_schedule(ahcd, ed);
- }
-
- if (modified)
- goto rescan_all;
- }
-}
-
-/*-------------------------------------------------------------------------*/
-
-/*
- * Process normal completions (error or success) and clean the schedules.
- *
- * This is the main path for handing urbs back to drivers. The only other
- * path is finish_unlinks(), which unlinks URBs using ed_rm_list, instead of
- * scanning the (re-reversed) donelist as this does.
- */
-
-static void ed_unhalt(struct admhcd *ahcd, struct ed *ed, struct urb *urb)
-{
- struct list_head *entry,*tmp;
- __hc32 toggle = ed->hwHeadP & cpu_to_hc32(ahcd, ED_C);
-
-#ifdef ADMHC_VERBOSE_DEBUG
- admhc_dump_ed(ahcd, "UNHALT", ed, 0);
-#endif
- /* clear ed halt; this is the td that caused it, but keep it inactive
- * until its urb->complete() has a chance to clean up.
- */
- ed->hwINFO |= cpu_to_hc32(ahcd, ED_SKIP);
- wmb();
- ed->hwHeadP &= ~cpu_to_hc32(ahcd, ED_H);
-
- list_for_each_safe(entry, tmp, &ed->td_list) {
- struct td *td = list_entry(entry, struct td, td_list);
- __hc32 info;
-
- if (td->urb != urb)
- break;
-
- info = td->hwINFO;
- info &= ~cpu_to_hc32(ahcd, TD_CC | TD_OWN);
- td->hwINFO = info;
-
- ed->hwHeadP = td->hwNextTD | toggle;
- wmb();
- }
-
-}
-
-static void ed_intr_refill(struct admhcd *ahcd, struct ed *ed)
-{
- __hc32 toggle = ed->hwHeadP & cpu_to_hc32(ahcd, ED_C);
-
- ed->hwHeadP = ed->hwTailP | toggle;
-}
-
-
-static inline int is_ed_halted(struct admhcd *ahcd, struct ed *ed)
-{
- return ((hc32_to_cpup(ahcd, &ed->hwHeadP) & ED_H) == ED_H);
-}
-
-static inline int is_td_halted(struct admhcd *ahcd, struct ed *ed,
- struct td *td)
-{
- return ((hc32_to_cpup(ahcd, &ed->hwHeadP) & TD_MASK) ==
- (hc32_to_cpup(ahcd, &td->hwNextTD) & TD_MASK));
-}
-
-static void ed_update(struct admhcd *ahcd, struct ed *ed)
-{
- struct list_head *entry,*tmp;
-
-#ifdef ADMHC_VERBOSE_DEBUG
- admhc_dump_ed(ahcd, "UPDATE", ed, 1);
-#endif
-
- list_for_each_safe(entry, tmp, &ed->td_list) {
- struct td *td = list_entry(entry, struct td, td_list);
- struct urb *urb = td->urb;
- struct urb_priv *urb_priv = urb->hcpriv;
- int status;
-
- if (hc32_to_cpup(ahcd, &td->hwINFO) & TD_OWN)
- break;
-
- /* update URB's length and status from TD */
- status = td_done(ahcd, urb, td);
- if (is_ed_halted(ahcd, ed) && is_td_halted(ahcd, ed, td))
- ed_unhalt(ahcd, ed, urb);
-
- if (ed->type == PIPE_INTERRUPT)
- ed_intr_refill(ahcd,ed);
-
- /* If all this urb's TDs are done, call complete() */
- if (urb_priv->td_idx == urb_priv->td_cnt)
- finish_urb(ahcd, urb, status);
-
- /* clean schedule: unlink EDs that are no longer busy */
- if (list_empty(&ed->td_list)) {
- if (ed->state == ED_OPER)
- start_ed_unlink(ahcd, ed);
-
- /* ... reenabling halted EDs only after fault cleanup */
- } else if ((ed->hwINFO & cpu_to_hc32(ahcd,
- ED_SKIP | ED_DEQUEUE))
- == cpu_to_hc32(ahcd, ED_SKIP)) {
- td = list_entry(ed->td_list.next, struct td, td_list);
-#if 0
- if (!(td->hwINFO & cpu_to_hc32(ahcd, TD_DONE))) {
- ed->hwINFO &= ~cpu_to_hc32(ahcd, ED_SKIP);
- /* ... hc may need waking-up */
- switch (ed->type) {
- case PIPE_CONTROL:
- admhc_writel (ahcd, OHCI_CLF,
- &ahcd->regs->cmdstatus);
- break;
- case PIPE_BULK:
- admhc_writel (ahcd, OHCI_BLF,
- &ahcd->regs->cmdstatus);
- break;
- }
- }
-#else
- if ((td->hwINFO & cpu_to_hc32(ahcd, TD_OWN)))
- ed->hwINFO &= ~cpu_to_hc32(ahcd, ED_SKIP);
-#endif
- }
-
- }
-}
-
-/* there are some tds completed; called in_irq(), with HCD locked */
-static void admhc_td_complete(struct admhcd *ahcd)
-{
- struct ed *ed;
-
- for (ed = ahcd->ed_head; ed; ed = ed->ed_next) {
- if (ed->state != ED_OPER)
- continue;
-
- ed_update(ahcd, ed);
- }
-}
+++ /dev/null
-/*
- * ADM5120 HCD (Host Controller Driver) for USB
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This file was derived from: drivers/usb/host/ohci.h
- * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
- * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-/*
- * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
- * __leXX (normally) or __beXX (given OHCI_BIG_ENDIAN), depending on the
- * host controller implementation.
- */
-typedef __u32 __bitwise __hc32;
-typedef __u16 __bitwise __hc16;
-
-/*
- * OHCI Endpoint Descriptor (ED) ... holds TD queue
- * See OHCI spec, section 4.2
- *
- * This is a "Queue Head" for those transfers, which is why
- * both EHCI and UHCI call similar structures a "QH".
- */
-
-#define TD_DATALEN_MAX 4096
-
-#define ED_ALIGN 16
-#define ED_MASK ((u32)~(ED_ALIGN-1)) /* strip hw status in low addr bits */
-
-struct ed {
- /* first fields are hardware-specified */
- __hc32 hwINFO; /* endpoint config bitmap */
- /* info bits defined by hcd */
-#define ED_DEQUEUE (1 << 27)
- /* info bits defined by the hardware */
-#define ED_MPS_SHIFT 16
-#define ED_MPS_MASK ((1 << 11)-1)
-#define ED_MPS_GET(x) (((x) >> ED_MPS_SHIFT) & ED_MPS_MASK)
-#define ED_ISO (1 << 15) /* isochronous endpoint */
-#define ED_SKIP (1 << 14)
-#define ED_SPEED_FULL (1 << 13) /* fullspeed device */
-#define ED_INT (1 << 11) /* interrupt endpoint */
-#define ED_EN_SHIFT 7 /* endpoint shift */
-#define ED_EN_MASK ((1 << 4)-1) /* endpoint mask */
-#define ED_EN_GET(x) (((x) >> ED_EN_SHIFT) & ED_EN_MASK)
-#define ED_FA_MASK ((1 << 7)-1) /* function address mask */
-#define ED_FA_GET(x) ((x) & ED_FA_MASK)
- __hc32 hwTailP; /* tail of TD list */
- __hc32 hwHeadP; /* head of TD list (hc r/w) */
-#define ED_C (0x02) /* toggle carry */
-#define ED_H (0x01) /* halted */
- __hc32 hwNextED; /* next ED in list */
-
- /* rest are purely for the driver's use */
- dma_addr_t dma; /* addr of ED */
- struct td *dummy; /* next TD to activate */
-
- struct list_head urb_list; /* list of our URBs */
-
- /* host's view of schedule */
- struct ed *ed_next; /* on schedule list */
- struct ed *ed_prev; /* for non-interrupt EDs */
- struct ed *ed_rm_next; /* on rm list */
- struct list_head td_list; /* "shadow list" of our TDs */
-
- /* create --> IDLE --> OPER --> ... --> IDLE --> destroy
- * usually: OPER --> UNLINK --> (IDLE | OPER) --> ...
- */
- u8 state; /* ED_{IDLE,UNLINK,OPER} */
-#define ED_IDLE 0x00 /* NOT linked to HC */
-#define ED_UNLINK 0x01 /* being unlinked from hc */
-#define ED_OPER 0x02 /* IS linked to hc */
-
- u8 type; /* PIPE_{BULK,...} */
-
- /* periodic scheduling params (for intr and iso) */
- u8 branch;
- u16 interval;
- u16 load;
- u16 last_iso; /* iso only */
-
- /* HC may see EDs on rm_list until next frame (frame_no == tick) */
- u16 tick;
-} __attribute__ ((aligned(ED_ALIGN)));
-
-/*
- * OHCI Transfer Descriptor (TD) ... one per transfer segment
- * See OHCI spec, sections 4.3.1 (general = control/bulk/interrupt)
- * and 4.3.2 (iso)
- */
-
-#define TD_ALIGN 32
-#define TD_MASK ((u32)~(TD_ALIGN-1)) /* strip hw status in low addr bits */
-
-struct td {
- /* first fields are hardware-specified */
- __hc32 hwINFO; /* transfer info bitmask */
-
- /* hwINFO bits */
-#define TD_OWN (1 << 31) /* owner of the descriptor */
-#define TD_CC_SHIFT 27 /* condition code */
-#define TD_CC_MASK 0xf
-#define TD_CC (TD_CC_MASK << TD_CC_SHIFT)
-#define TD_CC_GET(x) (((x) >> TD_CC_SHIFT) & TD_CC_MASK)
-
-#define TD_EC_SHIFT 25 /* error count */
-#define TD_EC_MASK 0x3
-#define TD_EC (TD_EC_MASK << TD_EC_SHIFT)
-#define TD_EC_GET(x) ((x >> TD_EC_SHIFT) & TD_EC_MASK)
-#define TD_T_SHIFT 23 /* data toggle state */
-#define TD_T_MASK 0x3
-#define TD_T (TD_T_MASK << TD_T_SHIFT)
-#define TD_T_DATA0 (0x2 << TD_T_SHIFT) /* DATA0 */
-#define TD_T_DATA1 (0x3 << TD_T_SHIFT) /* DATA1 */
-#define TD_T_CARRY (0x0 << TD_T_SHIFT) /* uses ED_C */
-#define TD_T_GET(x) (((x) >> TD_T_SHIFT) & TD_T_MASK)
-#define TD_DP_SHIFT 21 /* direction/pid */
-#define TD_DP_MASK 0x3
-#define TD_DP (TD_DP_MASK << TD_DP_SHIFT)
-#define TD_DP_GET (((x) >> TD_DP_SHIFT) & TD_DP_MASK)
-#define TD_DP_SETUP (0x0 << TD_DP_SHIFT) /* SETUP pid */
-#define TD_DP_OUT (0x1 << TD_DP_SHIFT) /* OUT pid */
-#define TD_DP_IN (0x2 << TD_DP_SHIFT) /* IN pid */
-#define TD_ISI_SHIFT 8 /* Interrupt Service Interval */
-#define TD_ISI_MASK 0x3f
-#define TD_ISI_GET(x) (((x) >> TD_ISI_SHIFT) & TD_ISI_MASK)
-#define TD_FN_MASK 0x3f /* frame number */
-#define TD_FN_GET(x) ((x) & TD_FN_MASK)
-
- __hc32 hwDBP; /* Data Buffer Pointer (or 0) */
- __hc32 hwCBL; /* Controller/Buffer Length */
-
- /* hwCBL bits */
-#define TD_BL_MASK 0xffff /* buffer length */
-#define TD_BL_GET(x) ((x) & TD_BL_MASK)
-#define TD_IE (1 << 16) /* interrupt enable */
- __hc32 hwNextTD; /* Next TD Pointer */
-
- /* rest are purely for the driver's use */
- __u8 index;
- struct ed *ed;
- struct td *td_hash; /* dma-->td hashtable */
- struct td *next_dl_td;
- struct urb *urb;
-
- dma_addr_t td_dma; /* addr of this TD */
- dma_addr_t data_dma; /* addr of data it points to */
-
- struct list_head td_list; /* "shadow list", TDs on same ED */
-
- u32 flags;
-#define TD_FLAG_DONE (1 << 17) /* retired to done list */
-#define TD_FLAG_ISO (1 << 16) /* copy of ED_ISO */
-} __attribute__ ((aligned(TD_ALIGN))); /* c/b/i need 16; only iso needs 32 */
-
-/*
- * Hardware transfer status codes -- CC from td->hwINFO
- */
-#define TD_CC_NOERROR 0x00
-#define TD_CC_CRC 0x01
-#define TD_CC_BITSTUFFING 0x02
-#define TD_CC_DATATOGGLEM 0x03
-#define TD_CC_STALL 0x04
-#define TD_CC_DEVNOTRESP 0x05
-#define TD_CC_PIDCHECKFAIL 0x06
-#define TD_CC_UNEXPECTEDPID 0x07
-#define TD_CC_DATAOVERRUN 0x08
-#define TD_CC_DATAUNDERRUN 0x09
- /* 0x0A, 0x0B reserved for hardware */
-#define TD_CC_BUFFEROVERRUN 0x0C
-#define TD_CC_BUFFERUNDERRUN 0x0D
- /* 0x0E, 0x0F reserved for HCD */
-#define TD_CC_HCD0 0x0E
-#define TD_CC_NOTACCESSED 0x0F
-
-/*
- * preshifted status codes
- */
-#define TD_SCC_NOTACCESSED (TD_CC_NOTACCESSED << TD_CC_SHIFT)
-
-
-/* map OHCI TD status codes (CC) to errno values */
-static const int cc_to_error [16] = {
- /* No Error */ 0,
- /* CRC Error */ -EILSEQ,
- /* Bit Stuff */ -EPROTO,
- /* Data Togg */ -EILSEQ,
- /* Stall */ -EPIPE,
- /* DevNotResp */ -ETIME,
- /* PIDCheck */ -EPROTO,
- /* UnExpPID */ -EPROTO,
- /* DataOver */ -EOVERFLOW,
- /* DataUnder */ -EREMOTEIO,
- /* (for hw) */ -EIO,
- /* (for hw) */ -EIO,
- /* BufferOver */ -ECOMM,
- /* BuffUnder */ -ENOSR,
- /* (for HCD) */ -EALREADY,
- /* (for HCD) */ -EALREADY
-};
-
-#define NUM_INTS 32
-
-/*
- * This is the structure of the OHCI controller's memory mapped I/O region.
- * You must use readl() and writel() (in <asm/io.h>) to access these fields!!
- * Layout is in section 7 (and appendix B) of the spec.
- */
-struct admhcd_regs {
- __hc32 gencontrol; /* General Control */
- __hc32 int_status; /* Interrupt Status */
- __hc32 int_enable; /* Interrupt Enable */
- __hc32 reserved00;
- __hc32 host_control; /* Host General Control */
- __hc32 reserved01;
- __hc32 fminterval; /* Frame Interval */
- __hc32 fmnumber; /* Frame Number */
- __hc32 reserved02;
- __hc32 reserved03;
- __hc32 reserved04;
- __hc32 reserved05;
- __hc32 reserved06;
- __hc32 reserved07;
- __hc32 reserved08;
- __hc32 reserved09;
- __hc32 reserved10;
- __hc32 reserved11;
- __hc32 reserved12;
- __hc32 reserved13;
- __hc32 reserved14;
- __hc32 reserved15;
- __hc32 reserved16;
- __hc32 reserved17;
- __hc32 reserved18;
- __hc32 reserved19;
- __hc32 reserved20;
- __hc32 reserved21;
- __hc32 lsthresh; /* Low Speed Threshold */
- __hc32 rhdesc; /* Root Hub Descriptor */
-#define MAX_ROOT_PORTS 2
- __hc32 portstatus[MAX_ROOT_PORTS]; /* Port Status */
- __hc32 hosthead; /* Host Descriptor Head */
-} __attribute__ ((aligned(32)));
-
-/*
- * General Control register bits
- */
-#define ADMHC_CTRL_UHFE (1 << 0) /* USB Host Function Enable */
-#define ADMHC_CTRL_SIR (1 << 1) /* Software Interrupt request */
-#define ADMHC_CTRL_DMAA (1 << 2) /* DMA Arbitration Control */
-#define ADMHC_CTRL_SR (1 << 3) /* Software Reset */
-
-/*
- * Host General Control register bits
- */
-#define ADMHC_HC_BUSS 0x3 /* USB bus state */
-#define ADMHC_BUSS_RESET 0x0
-#define ADMHC_BUSS_RESUME 0x1
-#define ADMHC_BUSS_OPER 0x2
-#define ADMHC_BUSS_SUSPEND 0x3
-#define ADMHC_HC_DMAE (1 << 2) /* DMA enable */
-
-/*
- * Interrupt Status/Enable register bits
- */
-#define ADMHC_INTR_SOFI (1 << 4) /* start of frame */
-#define ADMHC_INTR_RESI (1 << 5) /* resume detected */
-#define ADMHC_INTR_6 (1 << 6) /* unknown */
-#define ADMHC_INTR_7 (1 << 7) /* unknown */
-#define ADMHC_INTR_BABI (1 << 8) /* babble detected */
-#define ADMHC_INTR_INSM (1 << 9) /* root hub status change */
-#define ADMHC_INTR_SO (1 << 10) /* scheduling overrun */
-#define ADMHC_INTR_FNO (1 << 11) /* frame number overflow */
-#define ADMHC_INTR_TDC (1 << 20) /* transfer descriptor completed */
-#define ADMHC_INTR_SWI (1 << 29) /* software interrupt */
-#define ADMHC_INTR_FATI (1 << 30) /* fatal error */
-#define ADMHC_INTR_INTA (1 << 31) /* interrupt active */
-
-#define ADMHC_INTR_MIE (1 << 31) /* master interrupt enable */
-
-/*
- * SOF Frame Interval register bits
- */
-#define ADMHC_SFI_FI_MASK ((1 << 14)-1) /* Frame Interval value */
-#define ADMHC_SFI_FSLDP_SHIFT 16
-#define ADMHC_SFI_FSLDP_MASK ((1 << 15)-1)
-#define ADMHC_SFI_FIT (1 << 31) /* Frame Interval Toggle */
-
-/*
- * SOF Frame Number register bits
- */
-#define ADMHC_SFN_FN_MASK ((1 << 16)-1) /* Frame Number Mask */
-#define ADMHC_SFN_FR_SHIFT 16 /* Frame Remaining Shift */
-#define ADMHC_SFN_FR_MASK ((1 << 14)-1) /* Frame Remaining Mask */
-#define ADMHC_SFN_FRT (1 << 31) /* Frame Remaining Toggle */
-
-/*
- * Root Hub Descriptor register bits
- */
-#define ADMHC_RH_NUMP 0xff /* number of ports */
-#define ADMHC_RH_PSM (1 << 8) /* power switching mode */
-#define ADMHC_RH_NPS (1 << 9) /* no power switching */
-#define ADMHC_RH_OCPM (1 << 10) /* over current protection mode */
-#define ADMHC_RH_NOCP (1 << 11) /* no over current protection */
-#define ADMHC_RH_PPCM (0xff << 16) /* port power control */
-
-#define ADMHC_RH_LPS (1 << 24) /* local power switch */
-#define ADMHC_RH_OCI (1 << 25) /* over current indicator */
-
-/* status change bits */
-#define ADMHC_RH_LPSC (1 << 26) /* local power switch change */
-#define ADMHC_RH_OCIC (1 << 27) /* over current indicator change */
-
-#define ADMHC_RH_DRWE (1 << 28) /* device remote wakeup enable */
-#define ADMHC_RH_CRWE (1 << 29) /* clear remote wakeup enable */
-
-#define ADMHC_RH_CGP (1 << 24) /* clear global power */
-#define ADMHC_RH_SGP (1 << 26) /* set global power */
-
-/*
- * Port Status register bits
- */
-#define ADMHC_PS_CCS (1 << 0) /* current connect status */
-#define ADMHC_PS_PES (1 << 1) /* port enable status */
-#define ADMHC_PS_PSS (1 << 2) /* port suspend status */
-#define ADMHC_PS_POCI (1 << 3) /* port over current indicator */
-#define ADMHC_PS_PRS (1 << 4) /* port reset status */
-#define ADMHC_PS_PPS (1 << 8) /* port power status */
-#define ADMHC_PS_LSDA (1 << 9) /* low speed device attached */
-
-/* status change bits */
-#define ADMHC_PS_CSC (1 << 16) /* connect status change */
-#define ADMHC_PS_PESC (1 << 17) /* port enable status change */
-#define ADMHC_PS_PSSC (1 << 18) /* port suspend status change */
-#define ADMHC_PS_OCIC (1 << 19) /* over current indicator change */
-#define ADMHC_PS_PRSC (1 << 20) /* port reset status change */
-
-/* port feature bits */
-#define ADMHC_PS_CPE (1 << 0) /* clear port enable */
-#define ADMHC_PS_SPE (1 << 1) /* set port enable */
-#define ADMHC_PS_SPS (1 << 2) /* set port suspend */
-#define ADMHC_PS_CPS (1 << 3) /* clear suspend status */
-#define ADMHC_PS_SPR (1 << 4) /* set port reset */
-#define ADMHC_PS_SPP (1 << 8) /* set port power */
-#define ADMHC_PS_CPP (1 << 9) /* clear port power */
-
-/*
- * the POTPGT value is not defined in the ADMHC, so define a dummy value
- */
-#define ADMHC_POTPGT 2 /* in ms */
-
-/* hcd-private per-urb state */
-struct urb_priv {
- struct ed *ed;
- struct list_head pending; /* URBs on the same ED */
-
- u32 td_cnt; /* # tds in this request */
- u32 td_idx; /* index of the current td */
- struct td *td[0]; /* all TDs in this request */
-};
-
-#define TD_HASH_SIZE 64 /* power'o'two */
-/* sizeof (struct td) ~= 64 == 2^6 ... */
-#define TD_HASH_FUNC(td_dma) ((td_dma ^ (td_dma >> 6)) % TD_HASH_SIZE)
-
-/*
- * This is the full ADMHCD controller description
- *
- * Note how the "proper" USB information is just
- * a subset of what the full implementation needs. (Linus)
- */
-
-struct admhcd {
- spinlock_t lock;
-
- /*
- * I/O memory used to communicate with the HC (dma-consistent)
- */
- struct admhcd_regs __iomem *regs;
-
- /*
- * hcd adds to schedule for a live hc any time, but removals finish
- * only at the start of the next frame.
- */
-
- struct ed *ed_head;
- struct ed *ed_tails[4];
-
- struct ed *ed_rm_list; /* to be removed */
-
- struct ed *periodic[NUM_INTS]; /* shadow int_table */
-
-#if 0 /* TODO: remove? */
- /*
- * OTG controllers and transceivers need software interaction;
- * other external transceivers should be software-transparent
- */
- struct otg_transceiver *transceiver;
-#endif
-
- /*
- * memory management for queue data structures
- */
- struct dma_pool *td_cache;
- struct dma_pool *ed_cache;
- struct td *td_hash[TD_HASH_SIZE];
- struct list_head pending;
-
- /*
- * driver state
- */
- int num_ports;
- int load[NUM_INTS];
- u32 host_control; /* copy of the host_control reg */
- unsigned long next_statechange; /* suspend/resume */
- u32 fminterval; /* saved register */
- unsigned autostop:1; /* rh auto stopping/stopped */
-
- unsigned long flags; /* for HC bugs */
-#define OHCI_QUIRK_AMD756 0x01 /* erratum #4 */
-#define OHCI_QUIRK_SUPERIO 0x02 /* natsemi */
-#define OHCI_QUIRK_INITRESET 0x04 /* SiS, OPTi, ... */
-#define OHCI_QUIRK_BE_DESC 0x08 /* BE descriptors */
-#define OHCI_QUIRK_BE_MMIO 0x10 /* BE registers */
-#define OHCI_QUIRK_ZFMICRO 0x20 /* Compaq ZFMicro chipset*/
- // there are also chip quirks/bugs in init logic
-
-#ifdef DEBUG
- struct dentry *debug_dir;
- struct dentry *debug_async;
- struct dentry *debug_periodic;
- struct dentry *debug_registers;
-#endif
-};
-
-/* convert between an hcd pointer and the corresponding ahcd_hcd */
-static inline struct admhcd *hcd_to_admhcd(struct usb_hcd *hcd)
-{
- return (struct admhcd *)(hcd->hcd_priv);
-}
-static inline struct usb_hcd *admhcd_to_hcd(const struct admhcd *ahcd)
-{
- return container_of((void *)ahcd, struct usb_hcd, hcd_priv);
-}
-
-/*-------------------------------------------------------------------------*/
-
-#ifndef DEBUG
-#define STUB_DEBUG_FILES
-#endif /* DEBUG */
-
-#ifdef DEBUG
-# define admhc_dbg(ahcd, fmt, args...) \
- printk(KERN_DEBUG "adm5120-hcd: " fmt , ## args )
-#else
-# define admhc_dbg(ahcd, fmt, args...) do { } while (0)
-#endif
-
-#define admhc_err(ahcd, fmt, args...) \
- printk(KERN_ERR "adm5120-hcd: " fmt , ## args )
-#define admhc_info(ahcd, fmt, args...) \
- printk(KERN_INFO "adm5120-hcd: " fmt , ## args )
-#define admhc_warn(ahcd, fmt, args...) \
- printk(KERN_WARNING "adm5120-hcd: " fmt , ## args )
-
-#ifdef ADMHC_VERBOSE_DEBUG
-# define admhc_vdbg admhc_dbg
-#else
-# define admhc_vdbg(ahcd, fmt, args...) do { } while (0)
-#endif
-
-/*-------------------------------------------------------------------------*/
-
-/*
- * While most USB host controllers implement their registers and
- * in-memory communication descriptors in little-endian format,
- * a minority (notably the IBM STB04XXX and the Motorola MPC5200
- * processors) implement them in big endian format.
- *
- * In addition some more exotic implementations like the Toshiba
- * Spider (aka SCC) cell southbridge are "mixed" endian, that is,
- * they have a different endianness for registers vs. in-memory
- * descriptors.
- *
- * This attempts to support either format at compile time without a
- * runtime penalty, or both formats with the additional overhead
- * of checking a flag bit.
- *
- * That leads to some tricky Kconfig rules howevber. There are
- * different defaults based on some arch/ppc platforms, though
- * the basic rules are:
- *
- * Controller type Kconfig options needed
- * --------------- ----------------------
- * little endian CONFIG_USB_ADMHC_LITTLE_ENDIAN
- *
- * fully big endian CONFIG_USB_ADMHC_BIG_ENDIAN_DESC _and_
- * CONFIG_USB_ADMHC_BIG_ENDIAN_MMIO
- *
- * mixed endian CONFIG_USB_ADMHC_LITTLE_ENDIAN _and_
- * CONFIG_USB_OHCI_BIG_ENDIAN_{MMIO,DESC}
- *
- * (If you have a mixed endian controller, you -must- also define
- * CONFIG_USB_ADMHC_LITTLE_ENDIAN or things will not work when building
- * both your mixed endian and a fully big endian controller support in
- * the same kernel image).
- */
-
-#ifdef CONFIG_USB_ADMHC_BIG_ENDIAN_DESC
-#ifdef CONFIG_USB_ADMHC_LITTLE_ENDIAN
-#define big_endian_desc(ahcd) (ahcd->flags & OHCI_QUIRK_BE_DESC)
-#else
-#define big_endian_desc(ahcd) 1 /* only big endian */
-#endif
-#else
-#define big_endian_desc(ahcd) 0 /* only little endian */
-#endif
-
-#ifdef CONFIG_USB_ADMHC_BIG_ENDIAN_MMIO
-#ifdef CONFIG_USB_ADMHC_LITTLE_ENDIAN
-#define big_endian_mmio(ahcd) (ahcd->flags & OHCI_QUIRK_BE_MMIO)
-#else
-#define big_endian_mmio(ahcd) 1 /* only big endian */
-#endif
-#else
-#define big_endian_mmio(ahcd) 0 /* only little endian */
-#endif
-
-/*
- * Big-endian read/write functions are arch-specific.
- * Other arches can be added if/when they're needed.
- *
- * REVISIT: arch/powerpc now has readl/writel_be, so the
- * definition below can die once the STB04xxx support is
- * finally ported over.
- */
-#if defined(CONFIG_PPC) && !defined(CONFIG_PPC_MERGE)
-#define readl_be(addr) in_be32((__force unsigned *)addr)
-#define writel_be(val, addr) out_be32((__force unsigned *)addr, val)
-#endif
-
-static inline unsigned int admhc_readl(const struct admhcd *ahcd,
- __hc32 __iomem *regs)
-{
-#ifdef CONFIG_USB_ADMHC_BIG_ENDIAN_MMIO
- return big_endian_mmio(ahcd) ?
- readl_be(regs) :
- readl(regs);
-#else
- return readl(regs);
-#endif
-}
-
-static inline void admhc_writel(const struct admhcd *ahcd,
- const unsigned int val, __hc32 __iomem *regs)
-{
-#ifdef CONFIG_USB_ADMHC_BIG_ENDIAN_MMIO
- big_endian_mmio(ahcd) ?
- writel_be(val, regs) :
- writel(val, regs);
-#else
- writel(val, regs);
-#endif
-}
-
-static inline void admhc_writel_flush(const struct admhcd *ahcd)
-{
-#if 0
- /* TODO: remove? */
- (void) admhc_readl(ahcd, &ahcd->regs->gencontrol);
-#endif
-}
-
-
-/*-------------------------------------------------------------------------*/
-
-/* cpu to ahcd */
-static inline __hc16 cpu_to_hc16(const struct admhcd *ahcd, const u16 x)
-{
- return big_endian_desc(ahcd) ?
- (__force __hc16)cpu_to_be16(x) :
- (__force __hc16)cpu_to_le16(x);
-}
-
-static inline __hc16 cpu_to_hc16p(const struct admhcd *ahcd, const u16 *x)
-{
- return big_endian_desc(ahcd) ?
- cpu_to_be16p(x) :
- cpu_to_le16p(x);
-}
-
-static inline __hc32 cpu_to_hc32(const struct admhcd *ahcd, const u32 x)
-{
- return big_endian_desc(ahcd) ?
- (__force __hc32)cpu_to_be32(x) :
- (__force __hc32)cpu_to_le32(x);
-}
-
-static inline __hc32 cpu_to_hc32p(const struct admhcd *ahcd, const u32 *x)
-{
- return big_endian_desc(ahcd) ?
- cpu_to_be32p(x) :
- cpu_to_le32p(x);
-}
-
-/* ahcd to cpu */
-static inline u16 hc16_to_cpu(const struct admhcd *ahcd, const __hc16 x)
-{
- return big_endian_desc(ahcd) ?
- be16_to_cpu((__force __be16)x) :
- le16_to_cpu((__force __le16)x);
-}
-
-static inline u16 hc16_to_cpup(const struct admhcd *ahcd, const __hc16 *x)
-{
- return big_endian_desc(ahcd) ?
- be16_to_cpup((__force __be16 *)x) :
- le16_to_cpup((__force __le16 *)x);
-}
-
-static inline u32 hc32_to_cpu(const struct admhcd *ahcd, const __hc32 x)
-{
- return big_endian_desc(ahcd) ?
- be32_to_cpu((__force __be32)x) :
- le32_to_cpu((__force __le32)x);
-}
-
-static inline u32 hc32_to_cpup(const struct admhcd *ahcd, const __hc32 *x)
-{
- return big_endian_desc(ahcd) ?
- be32_to_cpup((__force __be32 *)x) :
- le32_to_cpup((__force __le32 *)x);
-}
-
-/*-------------------------------------------------------------------------*/
-
-static inline u16 admhc_frame_no(const struct admhcd *ahcd)
-{
- u32 t;
-
- t = admhc_readl(ahcd, &ahcd->regs->fmnumber) & ADMHC_SFN_FN_MASK;
- return (u16)t;
-}
-
-static inline u16 admhc_frame_remain(const struct admhcd *ahcd)
-{
- u32 t;
-
- t = admhc_readl(ahcd, &ahcd->regs->fmnumber) >> ADMHC_SFN_FR_SHIFT;
- t &= ADMHC_SFN_FR_MASK;
- return (u16)t;
-}
-
-/*-------------------------------------------------------------------------*/
-
-static inline void admhc_disable(struct admhcd *ahcd)
-{
- admhcd_to_hcd(ahcd)->state = HC_STATE_HALT;
-}
-
-#define FI 0x2edf /* 12000 bits per frame (-1) */
-#define FSLDP(fi) (0x7fff & ((6 * ((fi) - 1200)) / 7))
-#define FIT ADMHC_SFI_FIT
-#define LSTHRESH 0x628 /* lowspeed bit threshold */
-
-static inline void periodic_reinit(struct admhcd *ahcd)
-{
-#if 0
- u32 fi = ahcd->fminterval & ADMHC_SFI_FI_MASK;
- u32 fit = admhc_readl(ahcd, &ahcd->regs->fminterval) & FIT;
-
- /* TODO: adjust FSLargestDataPacket value too? */
- admhc_writel(ahcd, (fit ^ FIT) | ahcd->fminterval,
- &ahcd->regs->fminterval);
-#else
- u32 fit = admhc_readl(ahcd, &ahcd->regs->fminterval) & FIT;
-
- /* TODO: adjust FSLargestDataPacket value too? */
- admhc_writel(ahcd, (fit ^ FIT) | ahcd->fminterval,
- &ahcd->regs->fminterval);
-#endif
-}
-
-static inline u32 admhc_read_rhdesc(struct admhcd *ahcd)
-{
- return admhc_readl(ahcd, &ahcd->regs->rhdesc);
-}
-
-static inline u32 admhc_read_portstatus(struct admhcd *ahcd, int port)
-{
- return admhc_readl(ahcd, &ahcd->regs->portstatus[port]);
-}
-
-static inline void admhc_write_portstatus(struct admhcd *ahcd, int port,
- u32 value)
-{
- admhc_writel(ahcd, value, &ahcd->regs->portstatus[port]);
-}
-
-static inline void roothub_write_status(struct admhcd *ahcd, u32 value)
-{
- /* FIXME: read-only bits must be masked out */
- admhc_writel(ahcd, value, &ahcd->regs->rhdesc);
-}
-
-static inline void admhc_intr_disable(struct admhcd *ahcd, u32 ints)
-{
- u32 t;
-
- t = admhc_readl(ahcd, &ahcd->regs->int_enable);
- t &= ~(ints);
- admhc_writel(ahcd, t, &ahcd->regs->int_enable);
- /* TODO: flush writes ?*/
-}
-
-static inline void admhc_intr_enable(struct admhcd *ahcd, u32 ints)
-{
- u32 t;
-
- t = admhc_readl(ahcd, &ahcd->regs->int_enable);
- t |= ints;
- admhc_writel(ahcd, t, &ahcd->regs->int_enable);
- /* TODO: flush writes ?*/
-}
-
-static inline void admhc_intr_ack(struct admhcd *ahcd, u32 ints)
-{
- admhc_writel(ahcd, ints, &ahcd->regs->int_status);
-}
-
-static inline void admhc_dma_enable(struct admhcd *ahcd)
-{
- u32 t;
-
- t = admhc_readl(ahcd, &ahcd->regs->host_control);
- if (t & ADMHC_HC_DMAE)
- return;
-
- t |= ADMHC_HC_DMAE;
- admhc_writel(ahcd, t, &ahcd->regs->host_control);
- admhc_vdbg(ahcd,"DMA enabled\n");
-}
-
-static inline void admhc_dma_disable(struct admhcd *ahcd)
-{
- u32 t;
-
- t = admhc_readl(ahcd, &ahcd->regs->host_control);
- if (!(t & ADMHC_HC_DMAE))
- return;
-
- t &= ~ADMHC_HC_DMAE;
- admhc_writel(ahcd, t, &ahcd->regs->host_control);
- admhc_vdbg(ahcd,"DMA disabled\n");
-}
+++ /dev/null
-/*
- * ADM5120_WDT 0.01: Infineon ADM5120 SoC watchdog driver
- * Copyright (c) Ondrej Zajicek <santiago@crfreenet.org>, 2007
- *
- * based on
- *
- * RC32434_WDT 0.01: IDT Interprise 79RC32434 watchdog driver
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- */
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/fs.h>
-#include <linux/miscdevice.h>
-#include <linux/watchdog.h>
-#include <linux/irq.h>
-
-#include <asm/bootinfo.h>
-
-#include <asm/mach-adm5120/adm5120_info.h>
-#include <asm/mach-adm5120/adm5120_defs.h>
-#include <asm/mach-adm5120/adm5120_switch.h>
-
-#define DEFAULT_TIMEOUT 15 /* (secs) Default is 15 seconds */
-#define MAX_TIMEOUT 327
-/* Max is 327 seconds, counter is 15-bit integer, step is 10 ms */
-
-#define NAME "adm5120_wdt"
-#define VERSION "0.1"
-
-static int expect_close = 0;
-static int access = 0;
-static unsigned int timeout = DEFAULT_TIMEOUT;
-
-static int nowayout = WATCHDOG_NOWAYOUT;
-module_param(nowayout, int, 0);
-MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
-MODULE_LICENSE("GPL");
-
-
-static inline void wdt_set_timeout(void)
-{
- u32 val = (1 << 31) | (((timeout * 100) & 0x7FFF) << 16);
- SW_WRITE_REG(SWITCH_REG_WDOG0, val);
-}
-
-/*
- It looks like WDOG0-register-write don't modify counter,
- but WDOG0-register-read resets counter.
-*/
-
-static inline void wdt_reset_counter(void)
-{
- SW_READ_REG(SWITCH_REG_WDOG0);
-}
-
-static inline void wdt_disable(void)
-{
- SW_WRITE_REG(SWITCH_REG_WDOG0, 0x7FFF0000);
-}
-
-
-
-static int wdt_open(struct inode *inode, struct file *file)
-{
- /* Allow only one person to hold it open */
- if (access)
- return -EBUSY;
-
- if (nowayout) {
- __module_get(THIS_MODULE);
- }
-
- /* Activate timer */
- wdt_reset_counter();
- wdt_set_timeout();
- printk(KERN_INFO NAME ": enabling watchdog timer\n");
- access = 1;
- return 0;
-}
-
-static int wdt_release(struct inode *inode, struct file *file)
-{
- /*
- * Shut off the timer.
- * Lock it in if it's a module and we set nowayout
- */
- if (expect_close && (nowayout == 0)) {
- wdt_disable();
- printk(KERN_INFO NAME ": disabling watchdog timer\n");
- module_put(THIS_MODULE);
- } else {
- printk(KERN_CRIT NAME ": device closed unexpectedly. WDT will not stop!\n");
- }
- access = 0;
- return 0;
-}
-
-static ssize_t wdt_write(struct file *file, const char *data, size_t len, loff_t *ppos)
-{
- /* Refresh the timer. */
- if (len) {
- if (!nowayout) {
- size_t i;
-
- /* In case it was set long ago */
- expect_close = 0;
-
- for (i = 0; i != len; i++) {
- char c;
- if (get_user(c, data + i))
- return -EFAULT;
- if (c == 'V')
- expect_close = 1;
- }
- }
- wdt_reset_counter();
- return len;
- }
- return 0;
-}
-
-static int wdt_ioctl(struct inode *inode, struct file *file,
- unsigned int cmd, unsigned long arg)
-{
- int new_timeout;
- static struct watchdog_info ident = {
- .options = WDIOF_SETTIMEOUT |
- WDIOF_KEEPALIVEPING |
- WDIOF_MAGICCLOSE,
- .firmware_version = 0,
- .identity = "ADM5120_WDT Watchdog",
- };
- switch (cmd) {
- default:
- return -ENOTTY;
- case WDIOC_GETSUPPORT:
- if(copy_to_user((struct watchdog_info *)arg, &ident, sizeof(ident)))
- return -EFAULT;
- return 0;
- case WDIOC_GETSTATUS:
- case WDIOC_GETBOOTSTATUS:
- return put_user(0,(int *)arg);
- case WDIOC_KEEPALIVE:
- wdt_reset_counter();
- return 0;
- case WDIOC_SETTIMEOUT:
- if (get_user(new_timeout, (int *)arg))
- return -EFAULT;
- if (new_timeout < 1)
- return -EINVAL;
- if (new_timeout > MAX_TIMEOUT)
- return -EINVAL;
- timeout = new_timeout;
- wdt_set_timeout();
- /* Fall */
- case WDIOC_GETTIMEOUT:
- return put_user(timeout, (int *)arg);
- }
-}
-
-static struct file_operations wdt_fops = {
- owner: THIS_MODULE,
- llseek: no_llseek,
- write: wdt_write,
- ioctl: wdt_ioctl,
- open: wdt_open,
- release: wdt_release,
-};
-
-static struct miscdevice wdt_miscdev = {
- minor: WATCHDOG_MINOR,
- name: "watchdog",
- fops: &wdt_fops,
-};
-
-static char banner[] __initdata = KERN_INFO NAME ": Watchdog Timer version " VERSION "\n";
-
-static int __init watchdog_init(void)
-{
- int ret;
-
- ret = misc_register(&wdt_miscdev);
-
- if (ret)
- return ret;
-
- wdt_disable();
- printk(banner);
-
- return 0;
-}
-
-static void __exit watchdog_exit(void)
-{
- misc_deregister(&wdt_miscdev);
-}
-
-module_init(watchdog_init);
-module_exit(watchdog_exit);
+++ /dev/null
-/*
- * ADM5120 board definitions
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#ifndef _ASM_MIPS_MACH_ADM5120_BOARD_H
-#define _ASM_MIPS_MACH_ADM5120_BOARD_H
-
-#include <linux/init.h>
-#include <linux/list.h>
-
-#define ADM5120_BOARD_NAMELEN 64
-
-struct adm5120_board {
- unsigned long mach_type;
- char name[ADM5120_BOARD_NAMELEN];
-
- void (*board_setup)(void);
- struct list_head list;
-};
-
-extern void adm5120_board_register(struct adm5120_board *) __init;
-
-#define ADM5120_BOARD(_type, _name, _setup) \
-static struct adm5120_board adm5120_board_##_type __initdata = { \
- .mach_type = _type, \
- .name = _name, \
- .board_setup = _setup, \
-}; \
- \
-static __init int adm5120_board_##_type##_register(void) \
-{ \
- adm5120_board_register(&adm5120_board_##_type); \
- return 0; \
-} \
-pure_initcall(adm5120_board_##_type##_register)
-
-#endif /* _ASM_MIPS_MACH_ADM5120_BOARD_H */
+++ /dev/null
-/*
- * ADM5120 SoC definitions
- *
- * This file defines some constants specific to the ADM5120 SoC
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-#ifndef _ASM_MIPS_MACH_ADM5120_DEFS_H
-#define _ASM_MIPS_MACH_ADM5120_DEFS_H
-
-#define ADM5120_SDRAM0_BASE 0x00000000
-#define ADM5120_SDRAM1_BASE 0x01000000
-#define ADM5120_SRAM1_BASE 0x10000000
-#define ADM5120_EXTIO0_BASE 0x10C00000
-#define ADM5120_EXTIO0_SIZE 0x00200000
-#define ADM5120_EXTIO1_BASE 0x10E00000
-#define ADM5120_EXTIO1_SIZE 0x00200000
-#define ADM5120_MPMC_BASE 0x11000000
-#define ADM5120_MPMC_SIZE 0x00200000
-#define ADM5120_USBC_BASE 0x11200000
-#define ADM5120_USBC_SIZE 0x00200000
-#define ADM5120_PCIMEM_BASE 0x11400000
-#define ADM5120_PCIMEM_SIZE 0x00100000
-#define ADM5120_PCIIO_BASE 0x11500000
-#define ADM5120_PCIIO_SIZE 0x000FFFF0
-#define ADM5120_PCICFG_ADDR 0x115FFFF0
-#define ADM5120_PCICFG_DATA 0x115FFFF8
-#define ADM5120_PCICFG_SIZE 0x00000010
-#define ADM5120_SWITCH_BASE 0x12000000
-#define ADM5120_SWITCH_SIZE 0x00200000
-#define ADM5120_INTC_BASE 0x12200000
-#define ADM5120_INTC_SIZE 0x00200000
-#define ADM5120_UART0_BASE 0x12600000
-#define ADM5120_UART1_BASE 0x12800000
-#define ADM5120_UART_SIZE 0x00200000
-#define ADM5120_SRAM0_BASE 0x1FC00000
-
-#define ADM5120_NAND_BASE ADM5120_SRAM1_BASE
-#define ADM5120_NAND_SIZE 0xB
-
-#define ADM5120_CLK_175 175000000
-#define ADM5120_CLK_200 200000000
-#define ADM5120_CLK_225 225000000
-#define ADM5120_CLK_250 250000000
-
-#define ADM5120_UART_CLOCK 62500000
-
-#endif /* _ASM_MIPS_MACH_ADM5120_DEFS_H */
+++ /dev/null
-/*
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#ifndef _MACH_ADM5120_INFO_H
-#define _MACH_ADM5120_INFO_H
-
-#include <linux/types.h>
-
-extern unsigned int adm5120_prom_type;
-#define ADM5120_PROM_GENERIC 0
-#define ADM5120_PROM_CFE 1
-#define ADM5120_PROM_MYLOADER 2
-#define ADM5120_PROM_ROUTERBOOT 3
-#define ADM5120_PROM_BOOTBASE 4
-#define ADM5120_PROM_UBOOT 5
-#define ADM5120_PROM_LAST 5
-
-extern unsigned int adm5120_product_code;
-extern unsigned int adm5120_revision;
-extern unsigned int adm5120_nand_boot;
-
-extern unsigned long adm5120_speed;
-#define ADM5120_SPEED_175 175000000
-#define ADM5120_SPEED_200 200000000
-#define ADM5120_SPEED_225 225000000
-#define ADM5120_SPEED_250 250000000
-
-extern unsigned int adm5120_package;
-#define ADM5120_PACKAGE_PQFP 0
-#define ADM5120_PACKAGE_BGA 1
-
-extern unsigned long adm5120_memsize;
-
-/*
- * TODO:remove adm5120_eth* variables when the switch driver will be
- * converted into a real platform driver
- */
-extern unsigned int adm5120_eth_num_ports;
-extern unsigned char adm5120_eth_macs[6][6];
-extern unsigned char adm5120_eth_vlans[6];
-
-extern void adm5120_soc_init(void) __init;
-extern void adm5120_mem_init(void) __init;
-extern void adm5120_ndelay(u32 ns);
-
-extern void (*adm5120_board_reset)(void);
-
-extern void adm5120_gpio_init(void) __init;
-extern void adm5120_gpio_csx0_enable(void) __init;
-extern void adm5120_gpio_csx1_enable(void) __init;
-extern void adm5120_gpio_ew_enable(void) __init;
-
-static inline int adm5120_package_pqfp(void)
-{
- return (adm5120_package == ADM5120_PACKAGE_PQFP);
-}
-
-static inline int adm5120_package_bga(void)
-{
- return (adm5120_package == ADM5120_PACKAGE_BGA);
-}
-
-static inline int adm5120_has_pci(void)
-{
- return (adm5120_package == ADM5120_PACKAGE_BGA);
-}
-
-static inline int adm5120_has_gmii(void)
-{
- return (adm5120_package == ADM5120_PACKAGE_BGA);
-}
-
-#endif /* _MACH_ADM5120_INFO_H */
+++ /dev/null
-/*
- * ADM5120 interrupt controller definitions
- *
- * This header file defines the hardware registers of the ADM5120 SoC
- * built-in interrupt controller.
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#ifndef _MACH_ADM5120_INTC_H
-#define _MACH_ADM5120_INTC_H
-
-/*
- * INTC register offsets
- */
-#define INTC_REG_IRQ_STATUS 0x00 /* Interrupt status after masking */
-#define INTC_REG_IRQ_RAW_STATUS 0x04 /* Interrupt status before masking */
-#define INTC_REG_IRQ_ENABLE 0x08 /* Used to enable the interrupt sources */
-#define INTC_REG_IRQ_ENABLE_CLEAR 0x0C /* Used to disable the interrupt sources */
-#define INTC_REG_IRQ_DISABLE INTC_REG_IRQ_ENABLE_CLEAR
-#define INTC_REG_INT_MODE 0x14 /* The interrupt mode of the sources */
-#define INTC_REG_FIQ_STATUS 0x18 /* FIQ status */
-#define INTC_REG_IRQ_TEST_SOURCE 0x1C
-#define INTC_REG_IRQ_SOURCE_SELECT 0x20
-#define INTC_REG_INT_LEVEL 0x24
-
-/*
- * INTC IRQ numbers
- */
-#define INTC_IRQ_TIMER 0 /* built in timer */
-#define INTC_IRQ_UART0 1 /* built-in UART0 */
-#define INTC_IRQ_UART1 2 /* built-in UART1 */
-#define INTC_IRQ_USBC 3 /* USB Host Controller */
-#define INTC_IRQ_GPIO2 4 /* GPIO line 2 */
-#define INTC_IRQ_GPIO4 5 /* GPIO line 4 */
-#define INTC_IRQ_PCI0 6 /* PCI slot 2 */
-#define INTC_IRQ_PCI1 7 /* PCI slot 3 */
-#define INTC_IRQ_PCI2 8 /* PCI slot 4 */
-#define INTC_IRQ_SWITCH 9 /* built-in ethernet switch */
-#define INTC_IRQ_LAST INTC_IRQ_SWITCH
-#define INTC_IRQ_COUNT 10
-
-/*
- * INTC register bits
- */
-#define INTC_INT_TIMER ( 1 << INTC_IRQ_TIMER )
-#define INTC_INT_UART0 ( 1 << INTC_IRQ_UART0 )
-#define INTC_INT_UART1 ( 1 << INTC_IRQ_UART1 )
-#define INTC_INT_USBC ( 1 << INTC_IRQ_USBC )
-#define INTC_INT_INTX0 ( 1 << INTC_IRQ_INTX0 )
-#define INTC_INT_INTX1 ( 1 << INTC_IRQ_INTX1 )
-#define INTC_INT_PCI0 ( 1 << INTC_IRQ_PCI0 )
-#define INTC_INT_PCI1 ( 1 << INTC_IRQ_PCI1 )
-#define INTC_INT_PCI2 ( 1 << INTC_IRQ_PCI2 )
-#define INTC_INT_SWITCH ( 1 << INTC_IRQ_SWITCH )
-#define INTC_INT_ALL (( 1 << INTC_IRQ_COUNT)-1)
-
-#endif /* _MACH_ADM5120_INTC_H */
+++ /dev/null
-/*
- * ADM5120 MPMC (Multiport Memory Controller) register definitions
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#ifndef _MACH_ADM5120_MPMC_H
-#define _MACH_ADM5120_MPMC_H
-
-#define MPMC_READ_REG(r) __raw_readl( \
- (void __iomem *)KSEG1ADDR(ADM5120_MPMC_BASE) + MPMC_REG_ ## r)
-#define MPMC_WRITE_REG(r, v) __raw_writel((v), \
- (void __iomem *)KSEG1ADDR(ADM5120_MPMC_BASE) + MPMC_REG_ ## r)
-
-#define MPMC_REG_CTRL 0x0000
-#define MPMC_REG_STATUS 0x0004
-#define MPMC_REG_CONF 0x0008
-#define MPMC_REG_DC 0x0020
-#define MPMC_REG_DR 0x0024
-#define MPMC_REG_DRP 0x0030
-
-#define MPMC_REG_DC0 0x0100
-#define MPMC_REG_DRC0 0x0104
-#define MPMC_REG_DC1 0x0120
-#define MPMC_REG_DRC1 0x0124
-#define MPMC_REG_DC2 0x0140
-#define MPMC_REG_DRC2 0x0144
-#define MPMC_REG_DC3 0x0160
-#define MPMC_REG_DRC3 0x0164
-#define MPMC_REG_SC0 0x0200 /* for F_CS1_N */
-#define MPMC_REG_SC1 0x0220 /* for F_CS0_N */
-#define MPMC_REG_SC2 0x0240
-#define MPMC_REG_WEN2 0x0244
-#define MPMC_REG_OEN2 0x0248
-#define MPMC_REG_RD2 0x024C
-#define MPMC_REG_PG2 0x0250
-#define MPMC_REG_WR2 0x0254
-#define MPMC_REG_TN2 0x0258
-#define MPMC_REG_SC3 0x0260
-
-/* Control register bits */
-#define MPMC_CTRL_AM ( 1 << 1 ) /* Address Mirror */
-#define MPMC_CTRL_LPM ( 1 << 2 ) /* Low Power Mode */
-#define MPMC_CTRL_DWB ( 1 << 3 ) /* Drain Write Buffers */
-
-/* Status register bits */
-#define MPMC_STATUS_BUSY ( 1 << 0 ) /* Busy */
-#define MPMC_STATUS_WBS ( 1 << 1 ) /* Write Buffer Status */
-#define MPMC_STATUS_SRA ( 1 << 2 ) /* Self-Refresh Acknowledge*/
-
-/* Dynamic Control register bits */
-#define MPMC_DC_CE ( 1 << 0 )
-#define MPMC_DC_DMC ( 1 << 1 )
-#define MPMC_DC_SRR ( 1 << 2 )
-#define MPMC_DC_SI_SHIFT 7
-#define MPMC_DC_SI_MASK ( 3 << 7 )
-#define MPMC_DC_SI_NORMAL ( 0 << 7 )
-#define MPMC_DC_SI_MODE ( 1 << 7 )
-#define MPMC_DC_SI_PALL ( 2 << 7 )
-#define MPMC_DC_SI_NOP ( 3 << 7 )
-
-#define SRAM_REG_CONF 0x00
-#define SRAM_REG_WWE 0x04
-#define SRAM_REG_WOE 0x08
-#define SRAM_REG_WRD 0x0C
-#define SRAM_REG_WPG 0x10
-#define SRAM_REG_WWR 0x14
-#define SRAM_REG_WTR 0x18
-
-/* Dynamic Configuration register bits */
-#define DC_BE (1 << 19) /* buffer enable */
-#define DC_RW_SHIFT 28 /* shift for number of rows */
-#define DC_RW_MASK 0x03
-#define DC_NB_SHIFT 26 /* shift for number of banks */
-#define DC_NB_MASK 0x01
-#define DC_CW_SHIFT 22 /* shift for number of columns */
-#define DC_CW_MASK 0x07
-#define DC_DW_SHIFT 7 /* shift for device width */
-#define DC_DW_MASK 0x03
-
-/* Static Configuration register bits */
-#define SC_MW_MASK 0x03 /* memory width mask */
-#define SC_MW_8 0x00 /* 8 bit memory width */
-#define SC_MW_16 0x01 /* 16 bit memory width */
-#define SC_MW_32 0x02 /* 32 bit memory width */
-
-#endif /* _MACH_ADM5120_MPMC_H */
+++ /dev/null
-/*
- * ADM5120 NAND interface definitions
- *
- * This header file defines the hardware registers of the ADM5120 SoC
- * built-in NAND interface.
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * NAND interface routines was based on a driver for Linux 2.6.19+ which
- * was derived from the driver for Linux 2.4.xx published by Mikrotik for
- * their RouterBoard 1xx and 5xx series boards.
- * Copyright (C) 2007 David Goodenough <david.goodenough@linkchoose.co.uk>
- * Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#ifndef _MACH_ADM5120_NAND_H
-#define _MACH_ADM5120_NAND_H
-
-#include <linux/types.h>
-#include <linux/io.h>
-
-#include <asm/mach-adm5120/adm5120_defs.h>
-#include <asm/mach-adm5120/adm5120_switch.h>
-
-/* NAND control registers */
-#define NAND_REG_DATA 0x0 /* data register */
-#define NAND_REG_SET_CEn 0x1 /* CE# low */
-#define NAND_REG_CLR_CEn 0x2 /* CE# high */
-#define NAND_REG_CLR_CLE 0x3 /* CLE low */
-#define NAND_REG_SET_CLE 0x4 /* CLE high */
-#define NAND_REG_CLR_ALE 0x5 /* ALE low */
-#define NAND_REG_SET_ALE 0x6 /* ALE high */
-#define NAND_REG_SET_SPn 0x7 /* SP# low (use spare area) */
-#define NAND_REG_CLR_SPn 0x8 /* SP# high (do not use spare area) */
-#define NAND_REG_SET_WPn 0x9 /* WP# low */
-#define NAND_REG_CLR_WPn 0xA /* WP# high */
-#define NAND_REG_STATUS 0xB /* Status register */
-
-#define ADM5120_NAND_STATUS_READY 0x80
-
-#define NAND_READ_REG(r) \
- readb((void __iomem *)KSEG1ADDR(ADM5120_NAND_BASE) + (r))
-#define NAND_WRITE_REG(r, v) \
- writeb((v),(void __iomem *)KSEG1ADDR(ADM5120_NAND_BASE) + (r))
-
-/*-------------------------------------------------------------------------*/
-
-static inline void adm5120_nand_enable(void)
-{
- SW_WRITE_REG(SWITCH_REG_BW_CNTL1, BW_CNTL1_NAND_ENABLE);
- SW_WRITE_REG(SWITCH_REG_BOOT_DONE, 1);
-}
-
-static inline void adm5120_nand_set_wpn(unsigned int set)
-{
- NAND_WRITE_REG((set) ? NAND_REG_SET_WPn : NAND_REG_CLR_WPn, 1);
-}
-
-static inline void adm5120_nand_set_spn(unsigned int set)
-{
- NAND_WRITE_REG((set) ? NAND_REG_SET_SPn : NAND_REG_CLR_SPn, 1);
-}
-
-static inline void adm5120_nand_set_cle(unsigned int set)
-{
- NAND_WRITE_REG((set) ? NAND_REG_SET_CLE : NAND_REG_CLR_CLE, 1);
-}
-
-static inline void adm5120_nand_set_ale(unsigned int set)
-{
- NAND_WRITE_REG((set) ? NAND_REG_SET_ALE : NAND_REG_CLR_ALE, 1);
-}
-
-static inline void adm5120_nand_set_cen(unsigned int set)
-{
- NAND_WRITE_REG((set) ? NAND_REG_SET_CEn : NAND_REG_CLR_CEn, 1);
-}
-
-static inline u8 adm5120_nand_get_status(void)
-{
- return NAND_READ_REG(NAND_REG_STATUS);
-}
-
-#endif /* _MACH_ADM5120_NAND_H */
+++ /dev/null
-/*
- * ADM5120 specific platform definitions
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#ifndef _ASM_MIPS_MACH_ADM5120_PLATFORM_H
-#define _ASM_MIPS_MACH_ADM5120_PLATFORM_H
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/leds.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/map.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/nand.h>
-#include <linux/gpio_buttons.h>
-#include <linux/amba/bus.h>
-#include <linux/amba/serial.h>
-
-struct adm5120_flash_platform_data {
- void (*set_vpp)(struct map_info *, int);
- void (*switch_bank)(unsigned);
- u32 window_size;
-#ifdef CONFIG_MTD_PARTITIONS
- unsigned int nr_parts;
- struct mtd_partition *parts;
-#endif
-};
-
-struct adm5120_switch_platform_data {
- /* TODO: not yet implemented */
-};
-
-struct adm5120_pci_irq {
- u8 slot;
- u8 func;
- u8 pin;
- unsigned irq;
-};
-
-#define PCIIRQ(s,f,p,i) {.slot = (s), .func = (f), .pin = (p), .irq = (i)}
-
-#ifdef CONFIG_PCI
-extern void adm5120_pci_set_irq_map(unsigned int nr_irqs,
- struct adm5120_pci_irq *map) __init;
-#else
-static inline void adm5120_pci_set_irq_map(unsigned int nr_irqs,
- struct adm5120_pci_irq *map)
-{
-}
-#endif
-
-extern void adm5120_setup_eth_macs(u8 *mac_base) __init;
-
-extern struct adm5120_flash_platform_data adm5120_flash0_data;
-extern struct adm5120_flash_platform_data adm5120_flash1_data;
-
-extern void adm5120_add_device_flash(unsigned id) __init;
-extern void adm5120_add_device_usb(void) __init;
-extern void adm5120_add_device_uart(unsigned id) __init;
-extern void adm5120_add_device_nand(struct platform_nand_data *pdata) __init;
-extern void adm5120_add_device_switch(unsigned num_ports, u8 *vlan_map) __init;
-extern void adm5120_add_device_gpio(u32 disable_mask) __init;
-extern void adm5120_add_device_gpio_buttons(unsigned nbuttons,
- struct gpio_button *buttons) __init;
-
-#define GPIO_LED_DEF(g, n, t, a) { \
- .name = (n), \
- .default_trigger = (t), \
- .gpio = (g), \
- .active_low = (a) \
-}
-
-#define GPIO_LED_STD(g, n, t) GPIO_LED_DEF((g), (n), (t), 0)
-#define GPIO_LED_INV(g, n, t) GPIO_LED_DEF((g), (n), (t), 1)
-
-extern void adm5120_add_device_gpio_leds(unsigned num_leds,
- struct gpio_led *leds) __init;
-
-#endif /* _ASM_MIPS_MACH_ADM5120_PLATFORM_H */
+++ /dev/null
-/*
- * ADM5120 ethernet switch definitions
- *
- * This header file defines the hardware registers of the ADM5120 SoC
- * built-in Ethernet switch.
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#ifndef _MACH_ADM5120_SWITCH_H
-#define _MACH_ADM5120_SWITCH_H
-
-#ifndef BIT
-# define BIT(at) (1 << (at))
-#endif
-#define BITMASK(len) (BIT(len)-1)
-
-#define SW_READ_REG(r) __raw_readl( \
- (void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE) + r)
-#define SW_WRITE_REG(r, v) __raw_writel((v), \
- (void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE) + r)
-
-/* Switch register offsets */
-#define SWITCH_REG_CODE 0x0000
-#define SWITCH_REG_SOFT_RESET 0x0004 /* Soft Reset */
-#define SWITCH_REG_BOOT_DONE 0x0008 /* Boot Done */
-#define SWITCH_REG_SW_RESET 0x000C /* Switch Reset */
-#define SWITCH_REG_PHY_STATUS 0x0014 /* PHY Status */
-#define SWITCH_REG_MEMCTRL 0x001C /* Memory Control */
-#define SWITCH_REG_CPUP_CONF 0x0024 /* CPU Port Configuration */
-#define SWITCH_REG_PORT_CONF0 0x0028 /* Port Configuration 0 */
-#define SWITCH_REG_PORT_CONF1 0x002C /* Port Configuration 1 */
-#define SWITCH_REG_PORT_CONF2 0x0030 /* Port Configuration 2 */
-#define SWITCH_REG_VLAN_G1 0x0040 /* VLAN group 1 */
-#define SWITCH_REG_VLAN_G2 0x0044 /* VLAN group 2 */
-#define SWITCH_REG_SEND_TRIG 0x0048 /* Send Trigger */
-#define SWITCH_REG_MAC_WT0 0x0058 /* MAC Write Address 0 */
-#define SWITCH_REG_MAC_WT1 0x005C /* MAC Write Address 1 */
-#define SWITCH_REG_BW_CNTL0 0x0060 /* Bandwidth Control 0 */
-#define SWITCH_REG_BW_CNTL1 0x0064 /* Bandwidth Control 1 */
-#define SWITCH_REG_PHY_CNTL0 0x0068 /* PHY Control 0 */
-#define SWITCH_REG_PHY_CNTL1 0x006C /* PHY Control 1 */
-#define SWITCH_REG_PORT_TH 0x0078 /* Port Threshold */
-#define SWITCH_REG_PHY_CNTL2 0x007C /* PHY Control 2 */
-#define SWITCH_REG_PHY_CNTL3 0x0080 /* PHY Control 3 */
-#define SWITCH_REG_PRI_CNTL 0x0084 /* Priority Control */
-#define SWITCH_REG_PHY_CNTL4 0x00A0 /* PHY Control 4 */
-#define SWITCH_REG_EMPTY_CNT 0x00A4 /* Empty Count */
-#define SWITCH_REG_PORT_CNTLS 0x00A8 /* Port Control Select */
-#define SWITCH_REG_PORT_CNTL 0x00AC /* Port Control */
-#define SWITCH_REG_INT_STATUS 0x00B0 /* Interrupt Status */
-#define SWITCH_REG_INT_MASK 0x00B4 /* Interrupt Mask */
-#define SWITCH_REG_GPIO_CONF0 0x00B8 /* GPIO Configuration 0 */
-#define SWITCH_REG_GPIO_CONF2 0x00BC /* GPIO Configuration 1 */
-#define SWITCH_REG_WDOG0 0x00C0 /* Watchdog 0 */
-#define SWITCH_REG_WDOG1 0x00C4 /* Watchdog 1 */
-
-#define SWITCH_REG_SHDA 0x00D0 /* Send High Descriptors Address */
-#define SWITCH_REG_SLDA 0x00D4 /* Send Low Descriptors Address */
-#define SWITCH_REG_RHDA 0x00D8 /* Receive High Descriptor Address */
-#define SWITCH_REG_RLDA 0x00DC /* Receive Low Descriptor Address */
-#define SWITCH_REG_SHWA 0x00E0 /* Send High Working Address */
-#define SWITCH_REG_SLWA 0x00E4 /* Send Low Working Address */
-#define SWITCH_REG_RHWA 0x00E8 /* Receive High Working Address */
-#define SWITCH_REG_RLWA 0x00EC /* Receive Low Working Address */
-
-#define SWITCH_REG_TIMER_INT 0x00F0 /* Timer */
-#define SWITCH_REG_TIMER 0x00F4 /* Timer Interrupt */
-
-#define SWITCH_REG_PORT0_LED 0x0100
-#define SWITCH_REG_PORT1_LED 0x0104
-#define SWITCH_REG_PORT2_LED 0x0108
-#define SWITCH_REG_PORT3_LED 0x010C
-#define SWITCH_REG_PORT4_LED 0x0110
-
-/* CODE register bits */
-#define CODE_PC_MASK BITMASK(16) /* Product Code */
-#define CODE_REV_SHIFT 16
-#define CODE_REV_MASK BITMASK(4) /* Product Revision */
-#define CODE_CLKS_SHIFT 20
-#define CODE_CLKS_MASK BITMASK(2) /* Clock Speed */
-#define CODE_CLKS_175 0 /* 175 MHz */
-#define CODE_CLKS_200 1 /* 200 MHz */
-#define CODE_CLKS_225 2 /* 225 MHz */
-#define CODE_CLKS_250 3 /* 250 MHz */
-#define CODE_NAB BIT(24) /* NAND boot */
-#define CODE_PK_MASK BITMASK(1) /* Package type */
-#define CODE_PK_SHIFT 29
-#define CODE_PK_BGA 0 /* BGA package */
-#define CODE_PK_PQFP 1 /* PQFP package */
-
-/* MEMCTRL register bits */
-#define MEMCTRL_SDRS_MASK BITMASK(3) /* SDRAM bank size */
-#define MEMCTRL_SDRS_4M 0x01
-#define MEMCTRL_SDRS_8M 0x02
-#define MEMCTRL_SDRS_16M 0x03
-#define MEMCTRL_SDRS_64M 0x04
-#define MEMCTRL_SDRS_128M 0x05
-#define MEMCTRL_SDR1_ENABLE BIT(5) /* enable SDRAM bank 1 */
-
-#define MEMCTRL_SRS0_SHIFT 8 /* shift for SRAM0 size */
-#define MEMCTRL_SRS1_SHIFT 16 /* shift for SRAM1 size */
-#define MEMCTRL_SRS_MASK BITMASK(3) /* SRAM size mask */
-#define MEMCTRL_SRS_DISABLED 0x00 /* Disabled */
-#define MEMCTRL_SRS_512K 0x01 /* 512KB*/
-#define MEMCTRL_SRS_1M 0x02 /* 1MB */
-#define MEMCTRL_SRS_2M 0x03 /* 2MB */
-#define MEMCTRL_SRS_4M 0x04 /* 4MB */
-
-/* Port bits used in various registers */
-#define SWITCH_PORT_PHY0 BIT(0)
-#define SWITCH_PORT_PHY1 BIT(1)
-#define SWITCH_PORT_PHY2 BIT(2)
-#define SWITCH_PORT_PHY3 BIT(3)
-#define SWITCH_PORT_PHY4 BIT(4)
-#define SWITCH_PORT_MII BIT(5)
-#define SWITCH_PORT_CPU BIT(6)
-
-/* Port bit shorthands */
-#define SWITCH_PORTS_PHY 0x1F /* phy ports */
-#define SWITCH_PORTS_NOCPU 0x3F /* physical ports */
-#define SWITCH_PORTS_ALL 0x7F /* all ports */
-
-/* CPUP_CONF register bits */
-#define CPUP_CONF_DCPUP BIT(0) /* Disable CPU port */
-#define CPUP_CONF_CRCP BIT(1) /* CRC padding from CPU */
-#define CPUP_CONF_BTM BIT(2) /* Bridge Testing Mode */
-#define CPUP_CONF_DUNP_SHIFT 9 /* Disable Unknown Packets for portX */
-#define CPUP_CONF_DMCP_SHIFT 16 /* Disable Mcast Packets form portX */
-#define CPUP_CONF_DBCP_SHIFT 24 /* Disable Bcast Packets form portX */
-
-/* PORT_CONF0 register bits */
-#define PORT_CONF0_DP_SHIFT 0 /* Disable Port */
-#define PORT_CONF0_EMCP_SHIFT 8 /* Enable All MC Packets */
-#define PORT_CONF0_BP_SHIFT 16 /* Enable Back Pressure */
-
-/* PORT_CONF1 register bits */
-#define PORT_CONF1_DISL_SHIFT 0 /* Disable Learning */
-#define PORT_CONF1_BS_SHIFT 6 /* Blocking State */
-#define PORT_CONF1_BM_SHIFT 12 /* Blocking Mode */
-
-/* SEND_TRIG register bits */
-#define SEND_TRIG_STL BIT(0) /* Send Trigger Low */
-#define SEND_TRIG_STH BIT(1) /* Send Trigger High */
-
-/* MAC_WT0 register bits */
-#define MAC_WT0_MAWC BIT(0) /* MAC address write command */
-#define MAC_WT0_MWD_SHIFT 1
-#define MAC_WT0_MWD BIT(1) /* MAC write done */
-#define MAC_WT0_WFB BIT(2) /* Write Filter Bit */
-#define MAC_WT0_WVN_SHIFT 3 /* Write Vlan Number shift */
-#define MAC_WT0_WVE BIT(6) /* Write VLAN enable */
-#define MAC_WT0_WPMN_SHIFT 7
-#define MAC_WT0_WAF_SHIFT 13 /* Write Age Field shift */
-#define MAC_WT0_WAF_EMPTY 0
-#define MAC_WT0_WAF_STATIC 7 /* age: static */
-#define MAC_WT0_MAC0_SHIFT 16
-#define MAC_WT0_MAC1_SHIFT 24
-
-/* MAC_WT1 register bits */
-#define MAC_WT1_MAC2_SHIFT 0
-#define MAC_WT1_MAC3_SHIFT 8
-#define MAC_WT1_MAC4_SHIFT 16
-#define MAC_WT1_MAC5_SHIFT 24
-
-/* BW_CNTL0/BW_CNTL1 register bits */
-#define BW_CNTL_DISABLE 0x00
-#define BW_CNTL_64K 0x01
-#define BW_CNTL_128K 0x02
-#define BW_CNTL_256K 0x03
-#define BW_CNTL_512K 0x04
-#define BW_CNTL_1M 0x05
-#define BW_CNTL_4M 0x06
-#define BW_CNTL_10M 0x07
-
-#define P4TBC_SHIFT 0
-#define P4RBC_SHIFT 4
-#define P5TBC_SHIFT 8
-#define P5RBC_SHIFT 12
-
-#define BW_CNTL1_NAND_ENABLE 0x100
-
-/* PHY_CNTL0 register bits */
-#define PHY_CNTL0_PHYA_MASK BITMASK(5)
-#define PHY_CNTL0_PHYR_MASK BITMASK(5)
-#define PHY_CNTL0_PHYR_SHIFT 8
-#define PHY_CNTL0_WC BIT(13) /* Write Command */
-#define PHY_CNTL0_RC BIT(14) /* Read Command */
-#define PHY_CNTL0_WTD_MASK BIT(16) /* Read Command */
-#define PHY_CNTL0_WTD_SHIFT 16
-
-/* PHY_CNTL1 register bits */
-#define PHY_CNTL1_WOD BIT(0) /* Write Operation Done */
-#define PHY_CNTL1_ROD BIT(1) /* Read Operation Done */
-#define PHY_CNTL1_RD_MASK BITMASK(16)
-#define PHY_CNTL1_RD_SHIFT 16
-
-/* PHY_CNTL2 register bits */
-#define PHY_CNTL2_ANE_SHIFT 0 /* Auto Negotiation Enable */
-#define PHY_CNTL2_SC_SHIFT 5 /* Speed Control */
-#define PHY_CNTL2_DC_SHIFT 10 /* Duplex Control */
-#define PHY_CNTL2_FNCV_SHIFT 15 /* Recommended FC Value */
-#define PHY_CNTL2_PHYR_SHIFT 20 /* PHY reset */
-#define PHY_CNTL2_AMDIX_SHIFT 25 /* Auto MDIX enable */
-/* PHY_CNTL2_RMAE is bad in datasheet */
-#define PHY_CNTL2_RMAE BIT(31) /* Recommended MCC Average enable */
-
-/* PHY_CNTL3 register bits */
-#define PHY_CNTL3_RNT BIT(10) /* Recommend Normal Threshold */
-
-/* PORT_TH register bits */
-#define PORT_TH_PPT_MASK BITMASK(8) /* Per Port Threshold */
-#define PORT_TH_CPUT_SHIFT 8 /* CPU Port Buffer Threshold */
-#define PORT_TH_CPUT_MASK BITMASK(8)
-#define PORT_TH_CPUHT_SHIFT 16 /* CPU Hold Threshold */
-#define PORT_TH_CPUHT_MASK BITMASK(8)
-#define PORT_TH_CPURT_SHIFT 24 /* CPU Release Threshold */
-#define PORT_TH_CPURT_MASK BITMASK(8)
-
-/* EMPTY_CNT register bits */
-#define EMPTY_CNT_EBGB_MASK BITMASK(9) /* Empty Blocks in the Global Buffer */
-
-/* GPIO_CONF0 register bits */
-#define GPIO_CONF0_MASK BITMASK(8)
-#define GPIO_CONF0_IM_SHIFT 0
-#define GPIO_CONF0_IV_SHIFT 8
-#define GPIO_CONF0_OE_SHIFT 16
-#define GPIO_CONF0_OV_SHIFT 24
-#define GPIO_CONF0_IM_MASK (0xFF << GPIO_CONF0_IM_SHIFT)
-#define GPIO_CONF0_IV_MASK (0xFF << GPIO_CONF0_IV_SHIFT)
-#define GPIO_CONF0_OE_MASK (0xFF << GPIO_CONF0_OE_SHIFT)
-#define GPIO_CONF0_OV_MASK (0xFF << GPIO_CONF0_OV_SHIFT)
-
-/* GPIO_CONF2 register bits */
-#define GPIO_CONF2_CSX0 BIT(4) /* enable CSX0:INTX0 on GPIO 1:2 */
-#define GPIO_CONF2_CSX1 BIT(5) /* enable CSX1:INTX1 on GPIO 3:4 */
-#define GPIO_CONF2_EW BIT(6) /* enable wait state pin for CSX0/1 */
-
-/* INT_STATUS/INT_MASK register bits */
-#define SWITCH_INT_SHD BIT(0) /* Send High Done */
-#define SWITCH_INT_SLD BIT(1) /* Send Low Done */
-#define SWITCH_INT_RHD BIT(2) /* Receive High Done */
-#define SWITCH_INT_RLD BIT(3) /* Receive Low Done */
-#define SWITCH_INT_HDF BIT(4) /* High Descriptor Full */
-#define SWITCH_INT_LDF BIT(5) /* Low Descriptor Full */
-#define SWITCH_INT_P0QF BIT(6) /* Port0 Queue Full */
-#define SWITCH_INT_P1QF BIT(7) /* Port1 Queue Full */
-#define SWITCH_INT_P2QF BIT(8) /* Port2 Queue Full */
-#define SWITCH_INT_P3QF BIT(9) /* Port3 Queue Full */
-#define SWITCH_INT_P4QF BIT(10) /* Port4 Queue Full */
-#define SWITCH_INT_P5QF BIT(11) /* Port5 Queue Full */
-#define SWITCH_INT_CPQF BIT(13) /* CPU Queue Full */
-#define SWITCH_INT_GQF BIT(14) /* Global Queue Full */
-#define SWITCH_INT_MD BIT(15) /* Must Drop */
-#define SWITCH_INT_BCS BIT(16) /* BC Storm */
-#define SWITCH_INT_PSC BIT(18) /* Port Status Change */
-#define SWITCH_INT_ID BIT(19) /* Intruder Detected */
-#define SWITCH_INT_W0TE BIT(20) /* Watchdog 0 Timer Expired */
-#define SWITCH_INT_W1TE BIT(21) /* Watchdog 1 Timer Expired */
-#define SWITCH_INT_RDE BIT(22) /* Receive Descriptor Error */
-#define SWITCH_INT_SDE BIT(23) /* Send Descriptor Error */
-#define SWITCH_INT_CPUH BIT(24) /* CPU Hold */
-
-/* TIMER_INT register bits */
-#define TIMER_INT_TOS BIT(0) /* time-out status */
-#define TIMER_INT_TOM BIT(16) /* mask time-out interrupt */
-
-/* TIMER register bits */
-#define TIMER_PERIOD_MASK BITMASK(16) /* mask for timer period */
-#define TIMER_PERIOD_DEFAULT 0xFFFF /* default timer period */
-#define TIMER_TE BIT(16) /* timer enable bit */
-
-/* PORTx_LED register bits */
-#define LED_MODE_MASK BITMASK(4)
-#define LED_MODE_INPUT 0
-#define LED_MODE_FLASH 1
-#define LED_MODE_OUT_HIGH 2
-#define LED_MODE_OUT_LOW 3
-#define LED_MODE_LINK 4
-#define LED_MODE_SPEED 5
-#define LED_MODE_DUPLEX 6
-#define LED_MODE_ACT 7
-#define LED_MODE_COLL 8
-#define LED_MODE_LINK_ACT 9
-#define LED_MODE_DUPLEX_COLL 10
-#define LED_MODE_10M_ACT 11
-#define LED_MODE_100M_ACT 12
-#define LED0_MODE_SHIFT 0 /* LED0 mode shift */
-#define LED1_MODE_SHIFT 4 /* LED1 mode shift */
-#define LED2_MODE_SHIFT 8 /* LED2 mode shift */
-#define LED0_IV_SHIFT 12 /* LED0 input value shift */
-#define LED1_IV_SHIFT 13 /* LED1 input value shift */
-#define LED2_IV_SHIFT 14 /* LED2 input value shift */
-
-#endif /* _MACH_ADM5120_SWITCH_H */
+++ /dev/null
-/*
- * ADM5120 UART definitions
- *
- * This header file defines the hardware registers of the ADM5120 SoC
- * built-in UARTs.
- *
- * Copyright (C) 2007 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#ifndef _MACH_ADM5120_UART_H
-#define _MACH_ADM5120_UART_H
-
-#define UART_BAUDDIV(clk, baud) ((clk/(16 * (baud)))-1)
-
-#define UART_REG_DATA 0x00
-#define UART_REG_RSR 0x04
-#define UART_REG_ECR UART_REG_RSR
-#define UART_REG_LCRH 0x08
-#define UART_REG_LCRM 0x0C
-#define UART_REG_LCRL 0x10
-#define UART_REG_CTRL 0x14
-#define UART_REG_FLAG 0x18
-
-/* Receive Status Register bits */
-#define UART_RSR_FE ( 1 << 0 )
-#define UART_RSR_PE ( 1 << 1 )
-#define UART_RSR_BE ( 1 << 2 )
-#define UART_RSR_OE ( 1 << 3 )
-#define UART_RSR_ERR ( UART_RSR_FE | UART_RSR_PE | UART_RSR_BE )
-
-#define UART_ECR_ALL 0xFF
-
-/* Line Control High register bits */
-#define UART_LCRH_BRK ( 1 << 0 ) /* send break */
-#define UART_LCRH_PEN ( 1 << 1 ) /* parity enable */
-#define UART_LCRH_EPS ( 1 << 2 ) /* even parity select */
-#define UART_LCRH_STP1 ( 0 << 3 ) /* one stop bits select */
-#define UART_LCRH_STP2 ( 1 << 3 ) /* two stop bits select */
-#define UART_LCRH_FEN ( 1 << 4 ) /* FIFO enable */
-
-#define UART_LCRH_WLEN5 ( 0 << 5 )
-#define UART_LCRH_WLEN6 ( 1 << 5 )
-#define UART_LCRH_WLEN7 ( 2 << 5 )
-#define UART_LCRH_WLEN8 ( 3 << 5 )
-
-/* Control register bits */
-#define UART_CTRL_EN ( 1 << 0 )
-
-/* Flag register bits */
-#define UART_FLAG_CTS ( 1 << 0 )
-#define UART_FLAG_DSR ( 1 << 1 )
-#define UART_FLAG_DCD ( 1 << 2 )
-#define UART_FLAG_BUSY ( 1 << 3 )
-#define UART_FLAG_RXFE ( 1 << 4 )
-#define UART_FLAG_TXFF ( 1 << 5 )
-#define UART_FLAG_RXFF ( 1 << 6 )
-#define UART_FLAG_TXFE ( 1 << 7 )
-
-#endif /* _MACH_ADM5120_UART_H */
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-/* DO NOT EDIT!! - this file automatically generated
- * from .s file by awk -f s2h.awk
- */
-/* Size definitions
- * Copyright (C) ARM Limited 1998. All rights reserved.
- */
-
-#ifndef __sizes_h
-#define __sizes_h 1
-
-/* handy sizes */
-#define SZ_16 0x00000010
-#define SZ_256 0x00000100
-#define SZ_512 0x00000200
-
-#define SZ_1K 0x00000400
-#define SZ_4K 0x00001000
-#define SZ_8K 0x00002000
-#define SZ_16K 0x00004000
-#define SZ_64K 0x00010000
-#define SZ_128K 0x00020000
-#define SZ_256K 0x00040000
-#define SZ_512K 0x00080000
-
-#define SZ_1M 0x00100000
-#define SZ_2M 0x00200000
-#define SZ_4M 0x00400000
-#define SZ_8M 0x00800000
-#define SZ_16M 0x01000000
-#define SZ_32M 0x02000000
-#define SZ_64M 0x04000000
-#define SZ_128M 0x08000000
-#define SZ_256M 0x10000000
-#define SZ_512M 0x20000000
-
-#define SZ_1G 0x40000000
-#define SZ_2G 0x80000000
-
-#endif
-
-/* END */
+++ /dev/null
-/*
- * ADM5120 specific CPU feature overrides
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This file was derived from: include/asm-mips/cpu-features.h
- * Copyright (C) 2003, 2004 Ralf Baechle
- * Copyright (C) 2004 Maciej W. Rozycki
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-#ifndef __ASM_MACH_ADM5120_CPU_FEATURE_OVERRIDES_H
-#define __ASM_MACH_ADM5120_CPU_FEATURE_OVERRIDES_H
-
-/*
- * The ADM5120 SOC has a built-in MIPS 4Kc core.
- */
-#define cpu_has_tlb 1
-#define cpu_has_4kex 1
-#define cpu_has_3k_cache 0
-#define cpu_has_4k_cache 1
-#define cpu_has_tx39_cache 0
-#define cpu_has_sb1_cache 0
-#define cpu_has_fpu 0
-#define cpu_has_32fpr 0
-#define cpu_has_counter 1
-#define cpu_has_watch 1
-#define cpu_has_divec 1
-/* #define cpu_has_vce ? */
-/* #define cpu_has_cache_cdex_p ? */
-/* #define cpu_has_cache_cdex_s ? */
-#define cpu_has_prefetch 1
-/* #define cpu_has_mcheck ? */
-#define cpu_has_ejtag 1
-#define cpu_has_llsc 1
-
-#define cpu_has_mips16 0
-#define cpu_has_mdmx 0
-#define cpu_has_mips3d 0
-#define cpu_has_smartmips 0
-
-/* #define cpu_has_vtag_icache ? */
-/* #define cpu_has_dc_aliases ? */
-/* #define cpu_has_ic_fills_f_dc ? */
-/* #define cpu_has_pindexed_dcache ? */
-
-/* #define cpu_icache_snoops_remote_store ? */
-
-#define cpu_has_mips32r1 1
-#define cpu_has_mips32r2 0
-#define cpu_has_mips64r1 0
-#define cpu_has_mips64r2 0
-
-#define cpu_has_dsp 0
-#define cpu_has_mipsmt 0
-
-/* #define cpu_has_nofpuex ? */
-#define cpu_has_64bits 0
-#define cpu_has_64bit_zero_reg 0
-#define cpu_has_64bit_gp_regs 0
-#define cpu_has_64bit_addresses 0
-
-/* #define cpu_has_inclusive_pcaches ? */
-
-#define cpu_dcache_line_size() 16
-#define cpu_icache_line_size() 16
-
-#endif /* __ASM_MACH_ADM5120_CPU_FEATURE_OVERRIDES_H */
+++ /dev/null
-/*
- * ADM5120 GPIO wrappers for arch-neutral GPIO calls
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#ifndef _ASM_MIPS_MACH_ADM5120_GPIO_H
-#define _ASM_MIPS_MACH_ADM5120_GPIO_H
-
-#define ARCH_NR_GPIOS 64
-
-#include <asm-generic/gpio.h>
-
-#include <asm/mach-adm5120/adm5120_switch.h>
-
-#define ADM5120_GPIO_PIN0 0
-#define ADM5120_GPIO_PIN1 1
-#define ADM5120_GPIO_PIN2 2
-#define ADM5120_GPIO_PIN3 3
-#define ADM5120_GPIO_PIN4 4
-#define ADM5120_GPIO_PIN5 5
-#define ADM5120_GPIO_PIN6 6
-#define ADM5120_GPIO_PIN7 7
-#define ADM5120_GPIO_P0L0 8
-#define ADM5120_GPIO_P0L1 9
-#define ADM5120_GPIO_P0L2 10
-#define ADM5120_GPIO_P1L0 11
-#define ADM5120_GPIO_P1L1 12
-#define ADM5120_GPIO_P1L2 13
-#define ADM5120_GPIO_P2L0 14
-#define ADM5120_GPIO_P2L1 15
-#define ADM5120_GPIO_P2L2 16
-#define ADM5120_GPIO_P3L0 17
-#define ADM5120_GPIO_P3L1 18
-#define ADM5120_GPIO_P3L2 19
-#define ADM5120_GPIO_P4L0 20
-#define ADM5120_GPIO_P4L1 21
-#define ADM5120_GPIO_P4L2 22
-#define ADM5120_GPIO_MAX 22
-#define ADM5120_GPIO_COUNT ADM5120_GPIO_MAX+1
-
-#define ADM5120_GPIO_LOW 0
-#define ADM5120_GPIO_HIGH 1
-
-#define ADM5120_GPIO_SWITCH 0x10
-#define ADM5120_GPIO_FLASH (ADM5120_GPIO_SWITCH | LED_MODE_FLASH)
-#define ADM5120_GPIO_LINK (ADM5120_GPIO_SWITCH | LED_MODE_LINK)
-#define ADM5120_GPIO_SPEED (ADM5120_GPIO_SWITCH | LED_MODE_SPEED)
-#define ADM5120_GPIO_DUPLEX (ADM5120_GPIO_SWITCH | LED_MODE_DUPLEX)
-#define ADM5120_GPIO_ACT (ADM5120_GPIO_SWITCH | LED_MODE_ACT)
-#define ADM5120_GPIO_COLL (ADM5120_GPIO_SWITCH | LED_MODE_COLL)
-#define ADM5120_GPIO_LINK_ACT (ADM5120_GPIO_SWITCH | LED_MODE_LINK_ACT)
-#define ADM5120_GPIO_DUPLEX_COLL (ADM5120_GPIO_SWITCH | LED_MODE_DUPLEX_COLL)
-#define ADM5120_GPIO_10M_ACT (ADM5120_GPIO_SWITCH | LED_MODE_10M_ACT)
-#define ADM5120_GPIO_100M_ACT (ADM5120_GPIO_SWITCH | LED_MODE_100M_ACT)
-
-extern int __adm5120_gpio0_get_value(unsigned gpio);
-extern void __adm5120_gpio0_set_value(unsigned gpio, int value);
-extern int __adm5120_gpio1_get_value(unsigned gpio);
-extern void __adm5120_gpio1_set_value(unsigned gpio, int value);
-extern int adm5120_gpio_to_irq(unsigned gpio);
-extern int adm5120_irq_to_gpio(unsigned irq);
-
-static inline int gpio_get_value(unsigned gpio)
-{
- int ret;
-
- switch (gpio) {
- case ADM5120_GPIO_PIN0 ... ADM5120_GPIO_PIN7:
- ret = __adm5120_gpio0_get_value(gpio);
- break;
- case ADM5120_GPIO_P0L0 ... ADM5120_GPIO_P4L2:
- ret = __adm5120_gpio1_get_value(gpio - ADM5120_GPIO_P0L0);
- break;
- default:
- ret = __gpio_get_value(gpio);
- break;
- }
-
- return ret;
-}
-
-static inline void gpio_set_value(unsigned gpio, int value)
-{
- switch (gpio) {
- case ADM5120_GPIO_PIN0 ... ADM5120_GPIO_PIN7:
- __adm5120_gpio0_set_value(gpio, value);
- break;
- case ADM5120_GPIO_P0L0 ... ADM5120_GPIO_P4L2:
- __adm5120_gpio1_set_value(gpio - ADM5120_GPIO_P0L0, value);
- break;
- default:
- __gpio_set_value(gpio, value);
- break;
- }
-}
-
-static inline int gpio_to_irq(unsigned gpio)
-{
- return adm5120_gpio_to_irq(gpio);
-}
-
-static inline int irq_to_gpio(unsigned irq)
-{
- return adm5120_irq_to_gpio(irq);
-}
-
-#define gpio_cansleep __gpio_cansleep
-
-#endif /* _ASM_MIPS_MACH_ADM5120_GPIO_H */
+++ /dev/null
-/*
- * ADM5120 specific IRQ numbers
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-#ifndef _ASM_MIPS_MACH_ADM5120_IRQ_H
-#define _ASM_MIPS_MACH_ADM5120_IRQ_H
-
-#define MIPS_CPU_IRQ_BASE 0
-#define NR_IRQS 24
-
-#include_next <irq.h>
-
-#include <asm/mach-adm5120/adm5120_intc.h>
-
-#define NO_IRQ (-1)
-
-#define MIPS_CPU_IRQ_COUNT 8
-#define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x))
-
-#define ADM5120_INTC_IRQ_BASE (MIPS_CPU_IRQ_BASE + MIPS_CPU_IRQ_COUNT)
-#define ADM5120_INTC_IRQ(x) (ADM5120_INTC_IRQ_BASE + (x))
-
-#define ADM5120_IRQ_INTC MIPS_CPU_IRQ(2)
-#define ADM5120_IRQ_COUNTER MIPS_CPU_IRQ(7)
-
-#define ADM5120_IRQ_TIMER ADM5120_INTC_IRQ(INTC_IRQ_TIMER)
-#define ADM5120_IRQ_UART0 ADM5120_INTC_IRQ(INTC_IRQ_UART0)
-#define ADM5120_IRQ_UART1 ADM5120_INTC_IRQ(INTC_IRQ_UART1)
-#define ADM5120_IRQ_USBC ADM5120_INTC_IRQ(INTC_IRQ_USBC)
-#define ADM5120_IRQ_GPIO2 ADM5120_INTC_IRQ(INTC_IRQ_GPIO2)
-#define ADM5120_IRQ_GPIO4 ADM5120_INTC_IRQ(INTC_IRQ_GPIO4)
-#define ADM5120_IRQ_PCI0 ADM5120_INTC_IRQ(INTC_IRQ_PCI0)
-#define ADM5120_IRQ_PCI1 ADM5120_INTC_IRQ(INTC_IRQ_PCI1)
-#define ADM5120_IRQ_PCI2 ADM5120_INTC_IRQ(INTC_IRQ_PCI2)
-#define ADM5120_IRQ_SWITCH ADM5120_INTC_IRQ(INTC_IRQ_SWITCH)
-
-#endif /* _ASM_MIPS_MACH_ADM5120_IRQ_H */
+++ /dev/null
-/*
- * ADMBoot specific definitions
- *
- * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#ifndef _ADMBOOT_H
-#define _ADMBOOT_H
-
-extern int admboot_get_mac_base(u32 offset, u32 len, u8 *mac) __init;
-
-#endif /* _ADMBOOT_H */
+++ /dev/null
-/*
- * Broadcom's CFE definitions
- *
- * Copyright (C) 2006-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#ifndef _PROM_CFE_H_
-#define _PROM_CFE_H_
-
-extern int cfe_present(void) __init;
-extern char *cfe_getenv(char *);
-
-#endif /*_PROM_CFE_H_*/
+++ /dev/null
-/*
- * Generic prom definitions
- *
- * Copyright (C) 2006-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#ifndef _PROM_GENERIC_H_
-#define _PROM_GENERIC_H_
-
-extern int generic_prom_present(void) __init;
-extern char *generic_prom_getenv(char *);
-
-#endif /*_PROM_GENERIC_H_*/
+++ /dev/null
-/*
- * Compex's MyLoader specific definitions
- *
- * Copyright (C) 2006-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#ifndef _MYLOADER_H_
-#define _MYLOADER_H_
-
-/*
- * Firmware file format:
- *
- * <header>
- * [<block descriptor 0>]
- * ...
- * [<block descriptor n>]
- * <null block descriptor>
- * [<block data 0>]
- * ...
- * [<block data n>]
- *
- *
- */
-
-/* Myloader specific magic numbers */
-#define MYLO_MAGIC_FIRMWARE 0x4C594D00
-#define MYLO_MAGIC_20021103 0x20021103
-#define MYLO_MAGIC_20021107 0x20021107
-
-#define MYLO_MAGIC_SYS_PARAMS MYLO_MAGIC_20021107
-#define MYLO_MAGIC_PARTITIONS MYLO_MAGIC_20021103
-#define MYLO_MAGIC_BOARD_PARAMS MYLO_MAGIC_20021103
-
-/*
- * Addresses of the data structures provided by MyLoader
- */
-#define MYLO_MIPS_SYS_PARAMS 0x80000800 /* System Parameters */
-#define MYLO_MIPS_BOARD_PARAMS 0x80000A00 /* Board Parameters */
-#define MYLO_MIPS_PARTITIONS 0x80000C00 /* Partition Table */
-#define MYLO_MIPS_BOOT_PARAMS 0x80000E00 /* Boot Parameters */
-
-/* Vendor ID's (seems to be same as the PCI vendor ID's) */
-#define VENID_COMPEX 0x11F6
-
-/* Devices based on the ADM5120 */
-#define DEVID_COMPEX_NP27G 0x0078
-#define DEVID_COMPEX_NP28G 0x044C
-#define DEVID_COMPEX_NP28GHS 0x044E
-#define DEVID_COMPEX_WP54Gv1C 0x0514
-#define DEVID_COMPEX_WP54G 0x0515
-#define DEVID_COMPEX_WP54AG 0x0546
-#define DEVID_COMPEX_WPP54AG 0x0550
-#define DEVID_COMPEX_WPP54G 0x0555
-
-/* Devices based on the IXP422 */
-#define DEVID_COMPEX_WP18 0x047E
-#define DEVID_COMPEX_NP18A 0x0489
-
-/* Other devices */
-#define DEVID_COMPEX_NP26G8M 0x03E8
-#define DEVID_COMPEX_NP26G16M 0x03E9
-
-struct mylo_fw_header {
- uint32_t magic; /* must be MYLO_MAGIC_FIRMWARE */
- uint32_t crc; /* CRC of the whole firmware */
- uint32_t res0; /* unknown/unused */
- uint32_t res1; /* unknown/unused */
- uint16_t vid; /* vendor ID */
- uint16_t did; /* device ID */
- uint16_t svid; /* sub vendor ID */
- uint16_t sdid; /* sub device ID */
- uint32_t rev; /* device revision */
- uint32_t fwhi; /* FIXME: firmware version high? */
- uint32_t fwlo; /* FIXME: firmware version low? */
- uint32_t flags; /* firmware flags */
-};
-
-#define FW_FLAG_BOARD_PARAMS_WP 0x01 /* board parameters are write protected */
-#define FW_FLAG_BOOT_SECTOR_WE 0x02 /* enable of write boot sectors (below 64K) */
-
-struct mylo_fw_blockdesc {
- uint32_t type; /* block type */
- uint32_t addr; /* relative address to flash start */
- uint32_t dlen; /* size of block data in bytes */
- uint32_t blen; /* total size of block in bytes */
-};
-
-#define FW_DESC_TYPE_UNUSED 0
-#define FW_DESC_TYPE_USED 1
-
-struct mylo_partition {
- uint16_t flags; /* partition flags */
- uint16_t type; /* type of the partition */
- uint32_t addr; /* relative address of the partition from the
- flash start */
- uint32_t size; /* size of the partition in bytes */
- uint32_t param; /* if this is the active partition, the
- MyLoader load code to this address */
-};
-
-#define PARTITION_FLAG_ACTIVE 0x8000 /* this is the active partition,
- * MyLoader loads firmware from here */
-#define PARTITION_FLAG_ISRAM 0x2000 /* FIXME: this is a RAM partition? */
-#define PARTIIION_FLAG_RAMLOAD 0x1000 /* FIXME: load this partition into the RAM? */
-#define PARTITION_FLAG_PRELOAD 0x0800 /* the partition data preloaded to RAM
- * before decompression */
-#define PARTITION_FLAG_HAVEHDR 0x0002 /* the partition data have a header */
-
-#define PARTITION_TYPE_FREE 0
-#define PARTITION_TYPE_USED 1
-
-#define MYLO_MAX_PARTITIONS 8 /* maximum number of partitions in the
- partition table */
-
-struct mylo_partition_table {
- uint32_t magic; /* must be MYLO_MAGIC_PARTITIONS */
- uint32_t res0; /* unknown/unused */
- uint32_t res1; /* unknown/unused */
- uint32_t res2; /* unknown/unused */
- struct mylo_partition partitions[MYLO_MAX_PARTITIONS];
-};
-
-struct mylo_partition_header {
- uint32_t len; /* length of the partition data */
- uint32_t crc; /* CRC value of the partition data */
-};
-
-struct mylo_system_params {
- uint32_t magic; /* must be MYLO_MAGIC_SYS_PARAMS */
- uint32_t res0;
- uint32_t res1;
- uint32_t mylo_ver;
- uint16_t vid; /* Vendor ID */
- uint16_t did; /* Device ID */
- uint16_t svid; /* Sub Vendor ID */
- uint16_t sdid; /* Sub Device ID */
- uint32_t rev; /* device revision */
- uint32_t fwhi;
- uint32_t fwlo;
- uint32_t tftp_addr;
- uint32_t prog_start;
- uint32_t flash_size; /* Size of boot FLASH in bytes */
- uint32_t dram_size; /* Size of onboard RAM in bytes */
-};
-
-
-struct mylo_eth_addr {
- uint8_t mac[6];
- uint8_t csum[2];
-};
-
-#define MYLO_ETHADDR_COUNT 8 /* maximum number of ethernet address
- in the board parameters */
-
-struct mylo_board_params {
- uint32_t magic; /* must be MYLO_MAGIC_BOARD_PARAMS */
- uint32_t res0;
- uint32_t res1;
- uint32_t res2;
- struct mylo_eth_addr addr[MYLO_ETHADDR_COUNT];
-};
-
-struct myloader_info {
- u32 vid;
- u32 did;
- u32 svid;
- u32 sdid;
- uint8_t macs[MYLO_ETHADDR_COUNT][6];
-};
-
-extern struct myloader_info myloader_info;
-extern int myloader_present(void) __init;
-
-#endif /* _MYLOADER_H_*/
+++ /dev/null
-/*
- * Mikrotik's RouterBOOT definitions
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#ifndef _ROUTERBOOT_H
-#define _ROUTERBOOT_H
-
-#define RB_MAC_SIZE 6
-
-struct rb_bios_settings {
- u32 hs_offs; /* hard settings offset */
- u32 hs_size; /* hard settings size */
- u32 fw_offs; /* firmware offset */
- u32 ss_offs; /* soft settings offset */
- u32 ss_size; /* soft settings size */
-};
-
-struct rb_hard_settings {
- char *name; /* board name */
- char *bios_ver; /* BIOS version */
- u32 mem_size; /* memory size in bytes */
- u32 mac_count; /* number of mac addresses */
- u8 *mac_base; /* mac address base */
-};
-
-/*
- * Magic numbers
- */
-#define RB_MAGIC_HARD 0x64726148 /* "Hard" */
-#define RB_MAGIC_SOFT 0x74666F53 /* "Soft" */
-#define RB_MAGIC_DAWN 0x6E776144 /* "Dawn" */
-
-#define RB_ID_TERMINATOR 0
-
-/*
- * ID values for Hardware settings
- */
-#define RB_ID_HARD_01 1
-#define RB_ID_HARD_02 2
-#define RB_ID_FLASH_INFO 3
-#define RB_ID_MAC_ADDRESS_PACK 4
-#define RB_ID_BOARD_NAME 5
-#define RB_ID_BIOS_VERSION 6
-#define RB_ID_HARD_07 7
-#define RB_ID_SDRAM_TIMINGS 8
-#define RB_ID_DEVICE_TIMINGS 9
-#define RB_ID_SOFTWARE_ID 10
-#define RB_ID_SERIAL_NUMBER 11
-#define RB_ID_HARD_12 12
-#define RB_ID_MEMORY_SIZE 13
-#define RB_ID_MAC_ADDRESS_COUNT 14
-
-/*
- * ID values for Software settings
- */
-#define RB_ID_UART_SPEED 1
-#define RB_ID_BOOT_DELAY 2
-#define RB_ID_BOOT_DEVICE 3
-#define RB_ID_BOOT_KEY 4
-#define RB_ID_CPU_MODE 5
-#define RB_ID_FW_VERSION 6
-#define RB_ID_SOFT_07 7
-#define RB_ID_SOFT_08 8
-#define RB_ID_BOOT_PROTOCOL 9
-#define RB_ID_SOFT_10 10
-#define RB_ID_SOFT_11 11
-
-/*
- * UART_SPEED values
- */
-#define RB_UART_SPEED_115200 0
-#define RB_UART_SPEED_57600 1
-#define RB_UART_SPEED_38400 2
-#define RB_UART_SPEED_19200 3
-#define RB_UART_SPEED_9600 4
-#define RB_UART_SPEED_4800 5
-#define RB_UART_SPEED_2400 6
-#define RB_UART_SPEED_1200 7
-
-/*
- * BOOT_DELAY values
- */
-#define RB_BOOT_DELAY_0SEC 0
-#define RB_BOOT_DELAY_1SEC 1
-#define RB_BOOT_DELAY_2SEC 2
-
-/*
- * BOOT_DEVICE values
- */
-#define RB_BOOT_DEVICE_ETHER 0
-#define RB_BOOT_DEVICE_NANDETH 1
-#define RB_BOOT_DEVICE_ETHONCE 2
-#define RB_BOOT_DEVICE_NANDONLY 3
-
-/*
- * BOOT_KEY values
- */
-#define RB_BOOT_KEY_ANY 0
-#define RB_BOOT_KEY_DEL 1
-
-/*
- * CPU_MODE values
- */
-#define RB_CPU_MODE_POWERSAVE 0
-#define RB_CPU_MODE_REGULAR 1
-
-/*
- * BOOT_PROTOCOL values
- */
-#define RB_BOOT_PROTOCOL_BOOTP 0
-#define RB_BOOT_PROTOCOL_DHCP 1
-
-extern int routerboot_present(void) __init;
-extern char *routerboot_get_boardname(void);
-
-extern struct rb_hard_settings rb_hs;
-
-#endif /* _ROUTERBOOT_H */
+++ /dev/null
-/*
- * ZyNOS (ZyXEL's Networking OS) definitions
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#ifndef _ZYNOS_H
-#define _ZYNOS_H
-
-#define ZYNOS_NAME_LEN 32
-#define ZYNOS_FEAT_BYTES 22
-#define ZYNOS_MAC_LEN 6
-
-struct zynos_board_info {
- unsigned char vendor[ZYNOS_NAME_LEN];
- unsigned char product[ZYNOS_NAME_LEN];
- u32 bootext_addr;
- u32 res0;
- u16 board_id;
- u8 res1[6];
- u8 feat_other[ZYNOS_FEAT_BYTES];
- u8 feat_main;
- u8 res2;
- u8 mac[ZYNOS_MAC_LEN];
- u8 country;
- u8 dbgflag;
-} __attribute__ ((packed));
-
-/*
- * Vendor IDs
- */
-#define ZYNOS_VENDOR_ID_ZYXEL 0
-#define ZYNOS_VENDOR_ID_NETGEAR 1
-#define ZYNOS_VENDOR_ID_DLINK 2
-#define ZYNOS_VENDOR_ID_OTHER 3
-#define ZYNOS_VENDOR_ID_LUCENT 4
-
-/*
- * Vendor names
- */
-#define ZYNOS_VENDOR_DLINK "D-Link"
-#define ZYNOS_VENDOR_LUCENT "LUCENT"
-#define ZYNOS_VENDOR_NETGEAR "NetGear"
-#define ZYNOS_VENDOR_ZYXEL "ZyXEL"
-
-/*
- * Board IDs (big-endian)
- */
-#define ZYNOS_BOARD_ES2108 0x00F2 /* Ethernet Switch 2108 */
-#define ZYNOS_BOARD_ES2108F 0x01AF /* Ethernet Switch 2108-F */
-#define ZYNOS_BOARD_ES2108G 0x00F3 /* Ethernet Switch 2108-G */
-#define ZYNOS_BOARD_ES2108LC 0x00FC /* Ethernet Switch 2108-LC */
-#define ZYNOS_BOARD_ES2108PWR 0x00F4 /* Ethernet Switch 2108PWR */
-#define ZYNOS_BOARD_HS100 0x9FF1 /* HomeSafe 100/100W */
-#define ZYNOS_BOARD_P334 0x9FF5 /* Prestige 334 */
-#define ZYNOS_BOARD_P334U 0x9FDD /* Prestige 334U */
-#define ZYNOS_BOARD_P334W 0x9FF3 /* Prestige 334W */
-#define ZYNOS_BOARD_P334WH 0x00E0 /* Prestige 334WH */
-#define ZYNOS_BOARD_P334WHD 0x00E1 /* Prestige 334WHD */
-#define ZYNOS_BOARD_P334WT 0x9FEF /* Prestige 334WT */
-#define ZYNOS_BOARD_P334WT_ALT 0x9F02 /* Prestige 334WT alternative*/
-#define ZYNOS_BOARD_P335 0x9FED /* Prestige 335/335WT */
-#define ZYNOS_BOARD_P335PLUS 0x0025 /* Prestige 335Plus */
-#define ZYNOS_BOARD_P335U 0x9FDC /* Prestige 335U */
-
-/*
- * Some magic numbers (big-endian)
- */
-#define ZYNOS_MAGIC_DBGAREA1 0x48646267 /* "Hdbg" */
-#define ZYNOS_MAGIC_DBGAREA2 0x61726561 /* "area" */
-
-struct bootbase_info {
- u16 vendor_id;
- u16 board_id;
- u8 mac[6];
-};
-
-extern struct bootbase_info bootbase_info;
-extern int bootbase_present(void) __init;
-
-#endif /* _ZYNOS_H */
+++ /dev/null
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_ADM5120_WAR_H
-#define __ASM_MIPS_MACH_ADM5120_WAR_H
-
-#define R4600_V1_INDEX_ICACHEOP_WAR 0
-#define R4600_V1_HIT_CACHEOP_WAR 0
-#define R4600_V2_HIT_CACHEOP_WAR 0
-#define R5432_CP0_INTERRUPT_WAR 0
-#define BCM1250_M3_WAR 0
-#define SIBYTE_1956_WAR 0
-#define MIPS4K_ICACHE_REFILL_WAR 0
-#define MIPS_CACHE_SYNC_WAR 0
-#define TX49XX_ICACHE_INDEX_INV_WAR 0
-#define RM9000_CDEX_SMP_WAR 0
-#define ICACHE_REFILLS_WORKAROUND_WAR 0
-#define R10000_LLSC_WAR 0
-#define MIPS34K_MISSED_ITLB_WAR 0
-
-#endif /* __ASM_MIPS_MACH_ADM5120_WAR_H */
--- /dev/null
+if ADM5120
+
+menu "ADM5120 Board selection"
+
+config ADM5120_MACH_CAS_771
+ bool "Cellvision CAS-771/771W support"
+ depends on CPU_LITTLE_ENDIAN
+ select ADM5120_SOC_BGA
+ select ADM5120_OEM_CELLVISION
+ default y
+
+config ADM5120_MACH_NFS_101
+ bool "Cellvision NFS-101U/101WU support"
+ depends on CPU_LITTLE_ENDIAN
+ select ADM5120_SOC_BGA
+ select ADM5120_OEM_CELLVISION
+ default y
+
+config ADM5120_MACH_NP27G
+ bool "Compex NP27G support"
+ depends on CPU_LITTLE_ENDIAN
+ select ADM5120_SOC_BGA
+ select ADM5120_OEM_COMPEX
+ default y
+
+config ADM5120_MACH_NP28G
+ bool "Compex NP28G support"
+ depends on CPU_LITTLE_ENDIAN
+ select ADM5120_SOC_BGA
+ select ADM5120_OEM_COMPEX
+ default y
+
+config ADM5120_MACH_WP54
+ bool "Compex WP54 family support"
+ depends on CPU_LITTLE_ENDIAN
+ select ADM5120_SOC_BGA
+ select ADM5120_OEM_COMPEX
+ default y
+
+config ADM5120_MACH_BR_6104K
+ bool "Edimax BR-6104K support"
+ depends on CPU_LITTLE_ENDIAN
+ select ADM5120_OEM_EDIMAX
+ default y
+
+config ADM5120_MACH_BR_6104KP
+ bool "Edimax BR-6104KP support"
+ depends on CPU_LITTLE_ENDIAN
+ select ADM5120_OEM_EDIMAX
+ default y
+
+config ADM5120_MACH_BR_61X4WG
+ bool "Edimax BR-6104WG/6114WG support"
+ depends on CPU_LITTLE_ENDIAN
+ select ADM5120_SOC_BGA
+ select ADM5120_OEM_EDIMAX
+ default y
+
+config ADM5120_MACH_EASY5120_RT
+ bool "Infineon EASY 5120-RT Reference Board support"
+ depends on CPU_LITTLE_ENDIAN
+ select ADM5120_SOC_BGA
+ select ADM5120_OEM_INFINEON
+ default y
+
+config ADM5120_MACH_EASY5120_WVOIP
+ bool "Infineon EASY 5120-WVoIP Reference Board support"
+ depends on CPU_LITTLE_ENDIAN
+ select ADM5120_SOC_BGA
+ select ADM5120_OEM_INFINEON
+ default y
+
+config ADM5120_MACH_EASY5120P_ATA
+ bool "Infineon EASY 5120P-ATA Reference Board support"
+ depends on CPU_LITTLE_ENDIAN
+ select ADM5120_OEM_INFINEON
+ default y
+
+config ADM5120_MACH_EASY83000
+ bool "Infineon EASY 83000 Reference Board support"
+ depends on CPU_LITTLE_ENDIAN
+ select ADM5120_OEM_INFINEON
+ default y
+
+config ADM5120_MACH_RB_11X
+ bool "MikroTik RouterBOARD 111/112 support"
+ depends on CPU_LITTLE_ENDIAN
+ select ADM5120_SOC_BGA
+ select ADM5120_OEM_MIKROTIK
+ default y
+
+config ADM5120_MACH_RB_133
+ bool "MikroTik RouterBOARD 133 support"
+ depends on CPU_LITTLE_ENDIAN
+ select ADM5120_SOC_BGA
+ select ADM5120_OEM_MIKROTIK
+ default y
+
+config ADM5120_MACH_RB_133C
+ bool "MikroTik RouterBOARD 133C support"
+ depends on CPU_LITTLE_ENDIAN
+ select ADM5120_SOC_BGA
+ select ADM5120_OEM_MIKROTIK
+ default y
+
+config ADM5120_MACH_RB_150
+ bool "MikroTik RouterBOARD 150 support"
+ depends on CPU_LITTLE_ENDIAN
+ select ADM5120_OEM_MIKROTIK
+ default y
+
+config ADM5120_MACH_RB_153
+ bool "MikroTik RouterBOARD 153 support"
+ depends on CPU_LITTLE_ENDIAN
+ select ADM5120_SOC_BGA
+ select ADM5120_OEM_MIKROTIK
+ default y
+
+config ADM5120_MACH_RB_192
+ bool "MikroTik RouterBOARD 192 support"
+ depends on CPU_LITTLE_ENDIAN
+ select ADM5120_SOC_BGA
+ select ADM5120_OEM_MIKROTIK
+ default y
+
+config ADM5120_MACH_PMUGW
+ bool "Motorola Powerline MU Gateway"
+ depends on CPU_LITTLE_ENDIAN
+ select ADM5120_SOC_BGA
+ select ADM5120_OEM_MOTOROLA
+ default y
+
+config ADM5120_MACH_P_334WT
+ bool "ZyXEL Prestige 334WT"
+ depends on CPU_BIG_ENDIAN
+ select ADM5120_SOC_BGA
+ select ADM5120_OEM_ZYXEL
+ default y
+
+config ADM5120_MACH_P_335
+ bool "ZyXEL Prestige 335/335WT"
+ depends on CPU_BIG_ENDIAN
+ select ADM5120_SOC_BGA
+ select ADM5120_OEM_ZYXEL
+ default y
+
+endmenu
+
+config ADM5120_SOC_BGA
+ select HW_HAS_PCI
+ def_bool n
+
+config ADM5120_OEM_CELLVISION
+ def_bool n
+
+config ADM5120_OEM_COMPEX
+ def_bool n
+
+config ADM5120_OEM_EDIMAX
+ def_bool n
+
+config ADM5120_OEM_INFINEON
+ def_bool n
+
+config ADM5120_OEM_MIKROTIK
+ def_bool n
+
+config ADM5120_OEM_MOTOROLA
+ def_bool n
+
+config ADM5120_OEM_ZYXEL
+ def_bool n
+
+config ARM_AMBA
+ def_bool y
+
+endif
--- /dev/null
+obj-y += cellvision.o
+
+obj-$(CONFIG_ADM5120_MACH_CAS_771) += cas-771.o
+obj-$(CONFIG_ADM5120_MACH_NFS_101) += nfs-101.o
--- /dev/null
+/*
+ * Cellvision/SparkLAN CAS-771/771W support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "cellvision.h"
+
+static struct adm5120_pci_irq cas771_pci_irqs[] __initdata = {
+ PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI0),
+ PCIIRQ(3, 0, 1, ADM5120_IRQ_PCI1),
+ PCIIRQ(3, 2, 3, ADM5120_IRQ_PCI2)
+};
+
+static struct gpio_led cas771_gpio_leds[] __initdata = {
+ GPIO_LED_STD(ADM5120_GPIO_PIN0, "cam_flash", NULL),
+ /* GPIO PIN3 is the reset */
+ GPIO_LED_STD(ADM5120_GPIO_PIN6, "access", NULL),
+ GPIO_LED_STD(ADM5120_GPIO_P0L1, "status", NULL),
+ GPIO_LED_STD(ADM5120_GPIO_P0L2, "diag", NULL),
+};
+
+static void __init cas771_setup(void)
+{
+ cas7xx_setup();
+ adm5120_add_device_gpio_leds(ARRAY_SIZE(cas771_gpio_leds),
+ cas771_gpio_leds);
+ adm5120_pci_set_irq_map(ARRAY_SIZE(cas771_pci_irqs), cas771_pci_irqs);
+}
+
+ADM5120_BOARD(MACH_ADM5120_CAS771, "Cellvision CAS-771/771W", cas771_setup);
--- /dev/null
+/*
+ * Cellvision/SparkLAN boards
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "cellvision.h"
+
+#include <prom/admboot.h>
+
+#define CELLVISION_GPIO_FLASH_A20 ADM5120_GPIO_PIN5
+#define CELLVISION_GPIO_DEV_MASK (1 << CELLVISION_GPIO_FLASH_A20)
+
+#define CELLVISION_CONFIG_OFFSET 0x8000
+#define CELLVISION_CONFIG_SIZE 0x1000
+
+#ifdef CONFIG_MTD_PARTITIONS
+static struct mtd_partition cas6xx_partitions[] = {
+ {
+ .name = "admboot",
+ .offset = 0,
+ .size = 32*1024,
+ .mask_flags = MTD_WRITEABLE,
+ } , {
+ .name = "config",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 32*1024,
+ } , {
+ .name = "nvfs1",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 64*1024,
+ } , {
+ .name = "nvfs2",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 64*1024,
+ } , {
+ .name = "firmware",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+
+static struct mtd_partition cas7xx_partitions[] = {
+ {
+ .name = "admboot",
+ .offset = 0,
+ .size = 32*1024,
+ .mask_flags = MTD_WRITEABLE,
+ } , {
+ .name = "config",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 32*1024,
+ } , {
+ .name = "nvfs",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 128*1024,
+ } , {
+ .name = "firmware",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+#endif /* CONFIG_MTD_PARTITIONS */
+
+static void switch_bank_gpio5(unsigned bank)
+{
+ switch (bank) {
+ case 0:
+ gpio_set_value(CELLVISION_GPIO_FLASH_A20, 0);
+ break;
+ case 1:
+ gpio_set_value(CELLVISION_GPIO_FLASH_A20, 1);
+ break;
+ }
+}
+
+static void __init cellvision_flash_setup(void)
+{
+ /* setup flash A20 line */
+ gpio_request(CELLVISION_GPIO_FLASH_A20, NULL);
+ gpio_direction_output(CELLVISION_GPIO_FLASH_A20, 0);
+
+ adm5120_flash0_data.switch_bank = switch_bank_gpio5;
+ adm5120_add_device_flash(0);
+}
+
+void __init cellvision_mac_setup(void)
+{
+ u8 mac_base[6];
+ int err;
+
+ err = admboot_get_mac_base(CELLVISION_CONFIG_OFFSET,
+ CELLVISION_CONFIG_SIZE, mac_base);
+
+ if ((err) || !is_valid_ether_addr(mac_base))
+ random_ether_addr(mac_base);
+
+ adm5120_setup_eth_macs(mac_base);
+}
+
+void __init cas6xx_flash_setup(void)
+{
+#ifdef CONFIG_MTD_PARTITIONS
+ adm5120_flash0_data.nr_parts = ARRAY_SIZE(cas6xx_partitions);
+ adm5120_flash0_data.parts = cas6xx_partitions;
+#endif /* CONFIG_MTD_PARTITIONS */
+
+ cellvision_flash_setup();
+}
+
+void __init cas7xx_flash_setup(void)
+{
+#ifdef CONFIG_MTD_PARTITIONS
+ adm5120_flash0_data.nr_parts = ARRAY_SIZE(cas7xx_partitions);
+ adm5120_flash0_data.parts = cas7xx_partitions;
+#endif /* CONFIG_MTD_PARTITIONS */
+
+ cellvision_flash_setup();
+}
+
+#if 0
+void __init cas6xx_setup(void)
+{
+ cas6xx_flash_setup();
+ adm5120_add_device_uart(0);
+ adm5120_add_device_uart(1);
+ adm5120_add_device_switch(1, NULL);
+}
+
+ADM5120_BOARD(MACH_ADM5120_CAS630, "Cellvision CAS-630/630W", cas6xx_setup);
+ADM5120_BOARD(MACH_ADM5120_CAS670, "Cellvision CAS-670/670W", cas6xx_setup);
+#endif
+
+void __init cas7xx_setup(void)
+{
+ cas7xx_flash_setup();
+ cellvision_mac_setup();
+ adm5120_add_device_uart(0);
+ adm5120_add_device_uart(1);
+ adm5120_add_device_switch(1, NULL);
+}
+
+#if 0
+ADM5120_BOARD(MACH_ADM5120_CAS700, "Cellvision CAS-700/700W", cas7xx_setup);
+ADM5120_BOARD(MACH_ADM5120_CAS790, "Cellvision CAS-790", cas7xx_setup);
+ADM5120_BOARD(MACH_ADM5120_CAS861, "Cellvision CAS-861/861W", cas7xx_setup);
+#endif
--- /dev/null
+/*
+ * Cellvision/SparkLAN boards
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <linux/etherdevice.h>
+
+#include <asm/bootinfo.h>
+
+#include <asm/mach-adm5120/adm5120_info.h>
+#include <asm/mach-adm5120/adm5120_board.h>
+#include <asm/mach-adm5120/adm5120_platform.h>
+
+extern void cellvision_mac_setup(void) __init;
+
+extern void cas6xx_flash_setup(void) __init;
+extern void cas7xx_flash_setup(void) __init;
+extern void cas6xx_setup(void) __init;
+extern void cas7xx_setup(void) __init;
--- /dev/null
+/*
+ * Cellvision/SparkLAN NFS-101U/WU support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "cellvision.h"
+
+static u8 nfs101_vlans[6] __initdata = { /* TODO: not tested */
+ 0x41, 0x42, 0x44, 0x48, 0x50, 0x00
+};
+
+static void __init nfs101_setup(void)
+{
+ cas6xx_flash_setup();
+ cellvision_mac_setup();
+
+ adm5120_add_device_uart(0);
+ adm5120_add_device_uart(1);
+ adm5120_add_device_switch(5, nfs101_vlans);
+}
+
+ADM5120_BOARD(MACH_ADM5120_NFS101U, "Cellvision NFS-101U/101WU", nfs101_setup);
--- /dev/null
+#
+# Makefile for the Infineon/ADMtek ADM5120 SoC specific parts of the kernel
+#
+
+obj-y := adm5120.o setup.o prom.o irq.o memory.o board.o clock.o \
+ gpio.o platform.o
--- /dev/null
+/*
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+
+#include <asm/bootinfo.h>
+#include <asm/addrspace.h>
+
+#include <asm/mach-adm5120/adm5120_info.h>
+#include <asm/mach-adm5120/adm5120_defs.h>
+#include <asm/mach-adm5120/adm5120_switch.h>
+
+unsigned int adm5120_product_code;
+unsigned int adm5120_revision;
+unsigned int adm5120_package;
+unsigned int adm5120_nand_boot;
+unsigned long adm5120_speed;
+
+/*
+ * CPU settings detection
+ */
+#define CODE_GET_PC(c) ((c) & CODE_PC_MASK)
+#define CODE_GET_REV(c) (((c) >> CODE_REV_SHIFT) & CODE_REV_MASK)
+#define CODE_GET_PK(c) (((c) >> CODE_PK_SHIFT) & CODE_PK_MASK)
+#define CODE_GET_CLKS(c) (((c) >> CODE_CLKS_SHIFT) & CODE_CLKS_MASK)
+#define CODE_GET_NAB(c) (((c) & CODE_NAB) != 0)
+
+void adm5120_ndelay(u32 ns)
+{
+ u32 t;
+
+ SW_WRITE_REG(SWITCH_REG_TIMER, TIMER_PERIOD_DEFAULT);
+ SW_WRITE_REG(SWITCH_REG_TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM));
+
+ t = (ns+640) / 640;
+ t &= TIMER_PERIOD_MASK;
+ SW_WRITE_REG(SWITCH_REG_TIMER, t | TIMER_TE);
+
+ /* wait until the timer expires */
+ do {
+ t = SW_READ_REG(SWITCH_REG_TIMER_INT);
+ } while ((t & TIMER_INT_TOS) == 0);
+
+ /* leave the timer disabled */
+ SW_WRITE_REG(SWITCH_REG_TIMER, TIMER_PERIOD_DEFAULT);
+ SW_WRITE_REG(SWITCH_REG_TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM));
+}
+
+void __init adm5120_soc_init(void)
+{
+ u32 code;
+ u32 clks;
+
+ code = SW_READ_REG(SWITCH_REG_CODE);
+
+ adm5120_product_code = CODE_GET_PC(code);
+ adm5120_revision = CODE_GET_REV(code);
+ adm5120_package = (CODE_GET_PK(code) == CODE_PK_BGA) ?
+ ADM5120_PACKAGE_BGA : ADM5120_PACKAGE_PQFP;
+ adm5120_nand_boot = CODE_GET_NAB(code);
+
+ clks = CODE_GET_CLKS(code);
+ adm5120_speed = ADM5120_SPEED_175;
+ if (clks & 1)
+ adm5120_speed += 25000000;
+ if (clks & 2)
+ adm5120_speed += 50000000;
+}
--- /dev/null
+/*
+ * ADM5120 generic board code
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/string.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+
+#include <asm/bootinfo.h>
+
+#include <asm/mach-adm5120/adm5120_info.h>
+#include <asm/mach-adm5120/adm5120_defs.h>
+#include <asm/mach-adm5120/adm5120_board.h>
+#include <asm/mach-adm5120/adm5120_platform.h>
+
+#define PFX "ADM5120: "
+
+static struct list_head adm5120_boards __initdata =
+ LIST_HEAD_INIT(adm5120_boards);
+
+static char adm5120_board_name[ADM5120_BOARD_NAMELEN] = "Unknown board";
+
+const char *get_system_type(void)
+{
+ return adm5120_board_name;
+}
+
+static struct adm5120_board * __init adm5120_board_find(unsigned long machtype)
+{
+ struct list_head *this;
+
+ list_for_each(this, &adm5120_boards) {
+ struct adm5120_board *board;
+
+ board = list_entry(this, struct adm5120_board, list);
+ if (board->mach_type == machtype)
+ return board;
+ }
+
+ return NULL;
+}
+
+static int __init adm5120_board_setup(void)
+{
+ struct adm5120_board *board;
+
+ board = adm5120_board_find(mips_machtype);
+ if (board == NULL)
+ panic(PFX "no board registered for machtype %lu\n",
+ mips_machtype);
+
+ if (board->name[0])
+ strlcpy(adm5120_board_name, board->name, ADM5120_BOARD_NAMELEN);
+
+ printk(KERN_INFO PFX "board is '%s'\n", adm5120_board_name);
+
+ adm5120_gpio_init();
+
+ if (board->board_setup)
+ board->board_setup();
+
+ return 0;
+}
+arch_initcall(adm5120_board_setup);
+
+void __init adm5120_board_register(struct adm5120_board *board)
+{
+ list_add_tail(&board->list, &adm5120_boards);
+}
+
+static void __init adm5120_generic_board_setup(void)
+{
+ adm5120_add_device_uart(0);
+ adm5120_add_device_uart(1);
+
+ adm5120_add_device_flash(0);
+ adm5120_add_device_switch(6, NULL);
+}
+
+ADM5120_BOARD(MACH_ADM5120_GENERIC, "Generic ADM5120 board",
+ adm5120_generic_board_setup);
--- /dev/null
+/*
+ * ADM5120 minimal CLK API implementation
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This file was based on the CLK API implementation in:
+ * arch/mips/tx4938/toshiba_rbtx4938/setup.c
+ * Copyright (C) 2000-2001 Toshiba Corporation
+ * 2003-2005 (c) MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+
+#include <asm/mach-adm5120/adm5120_defs.h>
+
+struct clk {
+ unsigned long rate;
+};
+
+static struct clk uart_clk = {
+ .rate = ADM5120_UART_CLOCK
+};
+
+struct clk *clk_get(struct device *dev, const char *id)
+{
+ if (!strcmp(id, "UARTCLK"))
+ return &uart_clk;
+
+ return ERR_PTR(-ENOENT);
+}
+EXPORT_SYMBOL(clk_get);
+
+int clk_enable(struct clk *clk)
+{
+ return 0;
+}
+EXPORT_SYMBOL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+}
+EXPORT_SYMBOL(clk_disable);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+ return clk->rate;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+void clk_put(struct clk *clk)
+{
+}
+EXPORT_SYMBOL(clk_put);
--- /dev/null
+/*
+ * ADM5120 generic GPIO API support via GPIOLIB
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/autoconf.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/irq.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <asm/addrspace.h>
+
+#include <asm/mach-adm5120/adm5120_defs.h>
+#include <asm/mach-adm5120/adm5120_info.h>
+#include <asm/mach-adm5120/adm5120_switch.h>
+
+#define GPIO_REG(r) (void __iomem *)(KSEG1ADDR(ADM5120_SWITCH_BASE) + r)
+
+struct gpio1_desc {
+ void __iomem *reg; /* register address */
+ u8 iv_shift; /* shift amount for input bit */
+ u8 mode_shift; /* shift amount for mode bits */
+};
+
+#define GPIO1_DESC(p, l) { \
+ .reg = GPIO_REG(SWITCH_REG_PORT0_LED + ((p) * 4)), \
+ .iv_shift = LED0_IV_SHIFT + (l), \
+ .mode_shift = (l) * 4 \
+ }
+
+static struct gpio1_desc gpio1_table[15] = {
+ GPIO1_DESC(0, 0), GPIO1_DESC(0, 1), GPIO1_DESC(0, 2),
+ GPIO1_DESC(1, 0), GPIO1_DESC(1, 1), GPIO1_DESC(1, 2),
+ GPIO1_DESC(2, 0), GPIO1_DESC(2, 1), GPIO1_DESC(2, 2),
+ GPIO1_DESC(3, 0), GPIO1_DESC(3, 1), GPIO1_DESC(3, 2),
+ GPIO1_DESC(4, 0), GPIO1_DESC(4, 1), GPIO1_DESC(4, 2)
+};
+
+static u32 gpio_conf2;
+
+int adm5120_gpio_to_irq(unsigned gpio)
+{
+ int ret;
+
+ switch (gpio) {
+ case ADM5120_GPIO_PIN2:
+ ret = ADM5120_IRQ_GPIO2;
+ break;
+ case ADM5120_GPIO_PIN4:
+ ret = ADM5120_IRQ_GPIO4;
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ return ret;
+}
+EXPORT_SYMBOL(adm5120_gpio_to_irq);
+
+int adm5120_irq_to_gpio(unsigned irq)
+{
+ int ret;
+
+ switch (irq) {
+ case ADM5120_IRQ_GPIO2:
+ ret = ADM5120_GPIO_PIN2;
+ break;
+ case ADM5120_IRQ_GPIO4:
+ ret = ADM5120_GPIO_PIN4;
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ return ret;
+}
+EXPORT_SYMBOL(adm5120_irq_to_gpio);
+
+/*
+ * Helpers for GPIO lines in GPIO_CONF0 register
+ */
+#define PIN_IM(p) ((1 << GPIO_CONF0_IM_SHIFT) << p)
+#define PIN_IV(p) ((1 << GPIO_CONF0_IV_SHIFT) << p)
+#define PIN_OE(p) ((1 << GPIO_CONF0_OE_SHIFT) << p)
+#define PIN_OV(p) ((1 << GPIO_CONF0_OV_SHIFT) << p)
+
+int __adm5120_gpio0_get_value(unsigned offset)
+{
+ void __iomem **reg;
+ u32 t;
+
+ reg = GPIO_REG(SWITCH_REG_GPIO_CONF0);
+
+ t = __raw_readl(reg);
+ if ((t & PIN_IM(offset)) != 0)
+ t &= PIN_IV(offset);
+ else
+ t &= PIN_OV(offset);
+
+ return (t) ? 1 : 0;
+}
+EXPORT_SYMBOL(__adm5120_gpio0_get_value);
+
+void __adm5120_gpio0_set_value(unsigned offset, int value)
+{
+ void __iomem **reg;
+ u32 t;
+
+ reg = GPIO_REG(SWITCH_REG_GPIO_CONF0);
+
+ t = __raw_readl(reg);
+ if (value == 0)
+ t &= ~(PIN_OV(offset));
+ else
+ t |= PIN_OV(offset);
+
+ __raw_writel(t, reg);
+}
+EXPORT_SYMBOL(__adm5120_gpio0_set_value);
+
+static int adm5120_gpio0_get_value(struct gpio_chip *chip, unsigned offset)
+{
+ return __adm5120_gpio0_get_value(offset);
+}
+
+static void adm5120_gpio0_set_value(struct gpio_chip *chip,
+ unsigned offset, int value)
+{
+ __adm5120_gpio0_set_value(offset, value);
+}
+
+static int adm5120_gpio0_direction_input(struct gpio_chip *chip,
+ unsigned offset)
+{
+ void __iomem **reg;
+ u32 t;
+
+ reg = GPIO_REG(SWITCH_REG_GPIO_CONF0);
+
+ t = __raw_readl(reg);
+ t &= ~(PIN_OE(offset));
+ t |= PIN_IM(offset);
+ __raw_writel(t, reg);
+
+ return 0;
+}
+
+static int adm5120_gpio0_direction_output(struct gpio_chip *chip,
+ unsigned offset, int value)
+{
+ void __iomem **reg;
+ u32 t;
+
+ reg = GPIO_REG(SWITCH_REG_GPIO_CONF0);
+
+ t = __raw_readl(reg);
+ t &= ~(PIN_IM(offset) | PIN_OV(offset));
+ t |= PIN_OE(offset);
+
+ if (value)
+ t |= PIN_OV(offset);
+
+ __raw_writel(t, reg);
+
+ return 0;
+}
+
+static struct gpio_chip adm5120_gpio0_chip = {
+ .label = "adm5120 gpio0",
+ .get = adm5120_gpio0_get_value,
+ .set = adm5120_gpio0_set_value,
+ .direction_input = adm5120_gpio0_direction_input,
+ .direction_output = adm5120_gpio0_direction_output,
+ .base = ADM5120_GPIO_PIN0,
+ .ngpio = ADM5120_GPIO_PIN7 - ADM5120_GPIO_PIN0 + 1,
+};
+
+int __adm5120_gpio1_get_value(unsigned offset)
+{
+ void __iomem **reg;
+ u32 t, m;
+
+ reg = gpio1_table[offset].reg;
+
+ t = __raw_readl(reg);
+ m = (t >> gpio1_table[offset].mode_shift) & LED_MODE_MASK;
+ if (m == LED_MODE_INPUT)
+ return (t >> gpio1_table[offset].iv_shift) & 1;
+
+ if (m == LED_MODE_OUT_LOW)
+ return 0;
+
+ return 1;
+}
+EXPORT_SYMBOL(__adm5120_gpio1_get_value);
+
+void __adm5120_gpio1_set_value(unsigned offset, int value)
+{
+ void __iomem **reg;
+ u32 t, s;
+
+ reg = gpio1_table[offset].reg;
+ s = gpio1_table[offset].mode_shift;
+
+ t = __raw_readl(reg);
+ t &= ~(LED_MODE_MASK << s);
+
+ switch (value) {
+ case ADM5120_GPIO_LOW:
+ t |= (LED_MODE_OUT_LOW << s);
+ break;
+ case ADM5120_GPIO_FLASH:
+ case ADM5120_GPIO_LINK:
+ case ADM5120_GPIO_SPEED:
+ case ADM5120_GPIO_DUPLEX:
+ case ADM5120_GPIO_ACT:
+ case ADM5120_GPIO_COLL:
+ case ADM5120_GPIO_LINK_ACT:
+ case ADM5120_GPIO_DUPLEX_COLL:
+ case ADM5120_GPIO_10M_ACT:
+ case ADM5120_GPIO_100M_ACT:
+ t |= ((value & LED_MODE_MASK) << s);
+ break;
+ default:
+ t |= (LED_MODE_OUT_HIGH << s);
+ break;
+ }
+
+ __raw_writel(t, reg);
+}
+EXPORT_SYMBOL(__adm5120_gpio1_set_value);
+
+static int adm5120_gpio1_get_value(struct gpio_chip *chip, unsigned offset)
+{
+ return __adm5120_gpio1_get_value(offset);
+}
+
+static void adm5120_gpio1_set_value(struct gpio_chip *chip,
+ unsigned offset, int value)
+{
+ __adm5120_gpio1_set_value(offset, value);
+}
+
+static int adm5120_gpio1_direction_input(struct gpio_chip *chip,
+ unsigned offset)
+{
+ void __iomem **reg;
+ u32 t;
+
+ reg = gpio1_table[offset].reg;
+ t = __raw_readl(reg);
+ t &= ~(LED_MODE_MASK << gpio1_table[offset].mode_shift);
+ __raw_writel(t, reg);
+
+ return 0;
+}
+
+static int adm5120_gpio1_direction_output(struct gpio_chip *chip,
+ unsigned offset, int value)
+{
+ __adm5120_gpio1_set_value(offset, value);
+ return 0;
+}
+
+static struct gpio_chip adm5120_gpio1_chip = {
+ .label = "adm5120 gpio1",
+ .get = adm5120_gpio1_get_value,
+ .set = adm5120_gpio1_set_value,
+ .direction_input = adm5120_gpio1_direction_input,
+ .direction_output = adm5120_gpio1_direction_output,
+ .base = ADM5120_GPIO_P0L0,
+ .ngpio = ADM5120_GPIO_P4L2 - ADM5120_GPIO_P0L0 + 1,
+};
+
+void __init adm5120_gpio_csx0_enable(void)
+{
+ gpio_conf2 |= GPIO_CONF2_CSX0;
+ SW_WRITE_REG(SWITCH_REG_GPIO_CONF2, gpio_conf2);
+
+ gpio_request(ADM5120_GPIO_PIN1, "CSX0");
+}
+
+void __init adm5120_gpio_csx1_enable(void)
+{
+ gpio_conf2 |= GPIO_CONF2_CSX1;
+ SW_WRITE_REG(SWITCH_REG_GPIO_CONF2, gpio_conf2);
+
+ gpio_request(ADM5120_GPIO_PIN3, "CSX1");
+}
+
+void __init adm5120_gpio_ew_enable(void)
+{
+ gpio_conf2 |= GPIO_CONF2_EW;
+ SW_WRITE_REG(SWITCH_REG_GPIO_CONF2, gpio_conf2);
+
+ gpio_request(ADM5120_GPIO_PIN0, "EW");
+}
+
+void __init adm5120_gpio_init(void)
+{
+ int err;
+
+ SW_WRITE_REG(SWITCH_REG_GPIO_CONF2, gpio_conf2);
+
+ if (adm5120_package_pqfp()) {
+ gpiochip_reserve(ADM5120_GPIO_PIN4, 4);
+ adm5120_gpio0_chip.ngpio = 4;
+ }
+
+ err = gpiochip_add(&adm5120_gpio0_chip);
+ if (err)
+ panic("cannot add ADM5120 GPIO0 chip, error=%d", err);
+
+ err = gpiochip_add(&adm5120_gpio1_chip);
+ if (err)
+ panic("cannot add ADM5120 GPIO1 chip, error=%d", err);
+
+}
--- /dev/null
+/*
+ * ADM5120 specific interrupt handlers
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/version.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/io.h>
+
+#include <asm/irq_cpu.h>
+#include <asm/mipsregs.h>
+#include <asm/bitops.h>
+
+#include <asm/mach-adm5120/adm5120_defs.h>
+
+static void adm5120_intc_irq_unmask(unsigned int irq);
+static void adm5120_intc_irq_mask(unsigned int irq);
+static int adm5120_intc_irq_set_type(unsigned int irq, unsigned int flow_type);
+
+static inline void intc_write_reg(unsigned int reg, u32 val)
+{
+ void __iomem *base = (void __iomem *)KSEG1ADDR(ADM5120_INTC_BASE);
+
+ __raw_writel(val, base + reg);
+}
+
+static inline u32 intc_read_reg(unsigned int reg)
+{
+ void __iomem *base = (void __iomem *)KSEG1ADDR(ADM5120_INTC_BASE);
+
+ return __raw_readl(base + reg);
+}
+
+static struct irq_chip adm5120_intc_irq_chip = {
+ .name = "INTC",
+ .unmask = adm5120_intc_irq_unmask,
+ .mask = adm5120_intc_irq_mask,
+ .mask_ack = adm5120_intc_irq_mask,
+ .set_type = adm5120_intc_irq_set_type
+};
+
+static struct irqaction adm5120_intc_irq_action = {
+ .handler = no_action,
+ .name = "cascade [INTC]"
+};
+
+static void adm5120_intc_irq_unmask(unsigned int irq)
+{
+ irq -= ADM5120_INTC_IRQ_BASE;
+ intc_write_reg(INTC_REG_IRQ_ENABLE, 1 << irq);
+}
+
+static void adm5120_intc_irq_mask(unsigned int irq)
+{
+ irq -= ADM5120_INTC_IRQ_BASE;
+ intc_write_reg(INTC_REG_IRQ_DISABLE, 1 << irq);
+}
+
+static int adm5120_intc_irq_set_type(unsigned int irq, unsigned int flow_type)
+{
+ unsigned int sense;
+ unsigned long mode;
+ int err = 0;
+
+ sense = flow_type & (IRQ_TYPE_SENSE_MASK);
+ switch (sense) {
+ case IRQ_TYPE_NONE:
+ case IRQ_TYPE_LEVEL_HIGH:
+ break;
+ case IRQ_TYPE_LEVEL_LOW:
+ switch (irq) {
+ case ADM5120_IRQ_GPIO2:
+ case ADM5120_IRQ_GPIO4:
+ break;
+ default:
+ err = -EINVAL;
+ break;
+ }
+ break;
+ default:
+ err = -EINVAL;
+ break;
+ }
+
+ if (err)
+ return err;
+
+ switch (irq) {
+ case ADM5120_IRQ_GPIO2:
+ case ADM5120_IRQ_GPIO4:
+ mode = intc_read_reg(INTC_REG_INT_MODE);
+ if (sense == IRQ_TYPE_LEVEL_LOW)
+ mode |= (1 << (irq - ADM5120_INTC_IRQ_BASE));
+ else
+ mode &= ~(1 << (irq - ADM5120_INTC_IRQ_BASE));
+
+ intc_write_reg(INTC_REG_INT_MODE, mode);
+ /* fallthrough */
+ default:
+ irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
+ irq_desc[irq].status |= sense;
+ break;
+ }
+
+ return 0;
+}
+
+static void adm5120_intc_irq_dispatch(void)
+{
+ unsigned long status;
+ int irq;
+
+ status = intc_read_reg(INTC_REG_IRQ_STATUS) & INTC_INT_ALL;
+ if (status) {
+ irq = ADM5120_INTC_IRQ_BASE + fls(status) - 1;
+ do_IRQ(irq);
+ } else
+ spurious_interrupt();
+}
+
+asmlinkage void plat_irq_dispatch(void)
+{
+ unsigned long pending;
+
+ pending = read_c0_status() & read_c0_cause() & ST0_IM;
+
+ if (pending & STATUSF_IP7)
+ do_IRQ(ADM5120_IRQ_COUNTER);
+ else if (pending & STATUSF_IP2)
+ adm5120_intc_irq_dispatch();
+ else
+ spurious_interrupt();
+}
+
+#define INTC_IRQ_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED)
+static void __init adm5120_intc_irq_init(void)
+{
+ int i;
+
+ /* disable all interrupts */
+ intc_write_reg(INTC_REG_IRQ_DISABLE, INTC_INT_ALL);
+
+ /* setup all interrupts to generate IRQ instead of FIQ */
+ intc_write_reg(INTC_REG_INT_MODE, 0);
+
+ /* set active level for all external interrupts to HIGH */
+ intc_write_reg(INTC_REG_INT_LEVEL, 0);
+
+ /* disable usage of the TEST_SOURCE register */
+ intc_write_reg(INTC_REG_IRQ_SOURCE_SELECT, 0);
+
+ for (i = ADM5120_INTC_IRQ_BASE;
+ i <= ADM5120_INTC_IRQ_BASE + INTC_IRQ_LAST;
+ i++) {
+ irq_desc[i].status = INTC_IRQ_STATUS;
+ set_irq_chip_and_handler(i, &adm5120_intc_irq_chip,
+ handle_level_irq);
+ }
+
+ setup_irq(ADM5120_IRQ_INTC, &adm5120_intc_irq_action);
+}
+
+void __init arch_init_irq(void) {
+ mips_cpu_irq_init();
+ adm5120_intc_irq_init();
+}
--- /dev/null
+/*
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+
+#include <asm/bootinfo.h>
+#include <asm/addrspace.h>
+
+#include <asm/mach-adm5120/adm5120_info.h>
+#include <asm/mach-adm5120/adm5120_defs.h>
+#include <asm/mach-adm5120/adm5120_switch.h>
+#include <asm/mach-adm5120/adm5120_mpmc.h>
+
+#ifdef DEBUG
+# define mem_dbg(f, a...) printk(KERN_INFO "mem_detect: " f, ## a)
+#else
+# define mem_dbg(f, a...)
+#endif
+
+unsigned long adm5120_memsize;
+
+#define MEM_READL(a) __raw_readl((void __iomem *)(a))
+#define MEM_WRITEL(a, v) __raw_writel((v), (void __iomem *)(a))
+
+static int __init mem_check_pattern(u8 *addr, unsigned long offs)
+{
+ u32 *p1 = (u32 *)addr;
+ u32 *p2 = (u32 *)(addr+offs);
+ u32 t, u, v;
+
+ /* save original value */
+ t = MEM_READL(p1);
+
+ u = MEM_READL(p2);
+ if (t != u)
+ return 0;
+
+ v = 0x55555555;
+ if (u == v)
+ v = 0xAAAAAAAA;
+
+ mem_dbg("write 0x%08X to 0x%08lX\n", v, (unsigned long)p1);
+
+ MEM_WRITEL(p1, v);
+ adm5120_ndelay(1000);
+ u = MEM_READL(p2);
+
+ mem_dbg("pattern at 0x%08lX is 0x%08X\n", (unsigned long)p2, u);
+
+ /* restore original value */
+ MEM_WRITEL(p1, t);
+
+ return (v == u);
+}
+
+static void __init adm5120_detect_memsize(void)
+{
+ u32 memctrl;
+ u32 size, maxsize;
+ u8 *p;
+
+ memctrl = SW_READ_REG(SWITCH_REG_MEMCTRL);
+ switch (memctrl & MEMCTRL_SDRS_MASK) {
+ case MEMCTRL_SDRS_4M:
+ maxsize = 4 << 20;
+ break;
+ case MEMCTRL_SDRS_8M:
+ maxsize = 8 << 20;
+ break;
+ case MEMCTRL_SDRS_16M:
+ maxsize = 16 << 20;
+ break;
+ default:
+ maxsize = 64 << 20;
+ break;
+ }
+
+ mem_dbg("checking for %uMB chip in 1st bank\n", maxsize >> 20);
+
+ /* detect size of the 1st SDRAM bank */
+ p = (u8 *)KSEG1ADDR(0);
+ for (size = 2<<20; size <= (maxsize >> 1); size <<= 1) {
+ if (mem_check_pattern(p, size)) {
+ /* mirrored address */
+ mem_dbg("mirrored data found at offset 0x%08X\n", size);
+ break;
+ }
+ }
+
+ mem_dbg("chip size in 1st bank is %uMB\n", size >> 20);
+ adm5120_memsize = size;
+
+ if (size != maxsize)
+ /* 2nd bank is not supported */
+ goto out;
+
+ if ((memctrl & MEMCTRL_SDR1_ENABLE) == 0)
+ /* 2nd bank is disabled */
+ goto out;
+
+ /*
+ * some bootloaders enable 2nd bank, even if the 2nd SDRAM chip
+ * are missing.
+ */
+ mem_dbg("check presence of 2nd bank\n");
+
+ p = (u8 *)KSEG1ADDR(maxsize+size-4);
+ if (mem_check_pattern(p, 0))
+ adm5120_memsize += size;
+
+ if (maxsize != size) {
+ /* adjusting MECTRL register */
+ memctrl &= ~(MEMCTRL_SDRS_MASK);
+ switch (size>>20) {
+ case 4:
+ memctrl |= MEMCTRL_SDRS_4M;
+ break;
+ case 8:
+ memctrl |= MEMCTRL_SDRS_8M;
+ break;
+ case 16:
+ memctrl |= MEMCTRL_SDRS_16M;
+ break;
+ default:
+ memctrl |= MEMCTRL_SDRS_64M;
+ break;
+ }
+ SW_WRITE_REG(SWITCH_REG_MEMCTRL, memctrl);
+ }
+
+out:
+ mem_dbg("%dx%uMB memory found\n", (adm5120_memsize == size) ? 1 : 2 ,
+ size>>20);
+}
+
+void __init adm5120_mem_init(void)
+{
+ adm5120_detect_memsize();
+ add_memory_region(0, adm5120_memsize, BOOT_MEM_RAM);
+}
--- /dev/null
+/*
+ * ADM5120 generic platform devices
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+
+#include <asm/bootinfo.h>
+
+#include <asm/mach-adm5120/adm5120_defs.h>
+#include <asm/mach-adm5120/adm5120_info.h>
+#include <asm/mach-adm5120/adm5120_switch.h>
+#include <asm/mach-adm5120/adm5120_nand.h>
+#include <asm/mach-adm5120/adm5120_platform.h>
+
+#if 1
+/*
+ * TODO:remove global adm5120_eth* variables when the switch driver will be
+ * converted into a real platform driver
+ */
+unsigned int adm5120_eth_num_ports = 6;
+EXPORT_SYMBOL_GPL(adm5120_eth_num_ports);
+
+unsigned char adm5120_eth_macs[6][6] = {
+ {'\00', 'A', 'D', 'M', '\x51', '\x20' },
+ {'\00', 'A', 'D', 'M', '\x51', '\x21' },
+ {'\00', 'A', 'D', 'M', '\x51', '\x22' },
+ {'\00', 'A', 'D', 'M', '\x51', '\x23' },
+ {'\00', 'A', 'D', 'M', '\x51', '\x24' },
+ {'\00', 'A', 'D', 'M', '\x51', '\x25' }
+};
+EXPORT_SYMBOL_GPL(adm5120_eth_macs);
+
+unsigned char adm5120_eth_vlans[6] = {
+ 0x41, 0x42, 0x44, 0x48, 0x50, 0x60
+};
+EXPORT_SYMBOL_GPL(adm5120_eth_vlans);
+#endif
+
+void __init adm5120_setup_eth_macs(u8 *mac_base)
+{
+ u32 t;
+ int i, j;
+
+ t = ((u32) mac_base[3] << 16) | ((u32) mac_base[4] << 8)
+ | ((u32) mac_base[5]);
+
+ for (i = 0; i < ARRAY_SIZE(adm5120_eth_macs); i++) {
+ for (j = 0; j < 3; j++)
+ adm5120_eth_macs[i][j] = mac_base[j];
+
+ adm5120_eth_macs[i][3] = (t >> 16) & 0xff;
+ adm5120_eth_macs[i][4] = (t >> 8) & 0xff;
+ adm5120_eth_macs[i][5] = t & 0xff;
+
+ t++;
+ }
+}
+
+/*
+ * Built-in ethernet switch
+ */
+struct resource adm5120_switch_resources[] = {
+ [0] = {
+ .start = ADM5120_SWITCH_BASE,
+ .end = ADM5120_SWITCH_BASE+ADM5120_SWITCH_SIZE-1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = ADM5120_IRQ_SWITCH,
+ .end = ADM5120_IRQ_SWITCH,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct adm5120_switch_platform_data adm5120_switch_data;
+struct platform_device adm5120_switch_device = {
+ .name = "adm5120-switch",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(adm5120_switch_resources),
+ .resource = adm5120_switch_resources,
+ .dev.platform_data = &adm5120_switch_data,
+};
+
+void __init adm5120_add_device_switch(unsigned num_ports, u8 *vlan_map)
+{
+ if (num_ports > 0)
+ adm5120_eth_num_ports = num_ports;
+
+ if (vlan_map)
+ memcpy(adm5120_eth_vlans, vlan_map, sizeof(adm5120_eth_vlans));
+
+ platform_device_register(&adm5120_switch_device);
+}
+
+/*
+ * USB Host Controller
+ */
+struct resource adm5120_hcd_resources[] = {
+ [0] = {
+ .start = ADM5120_USBC_BASE,
+ .end = ADM5120_USBC_BASE+ADM5120_USBC_SIZE-1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = ADM5120_IRQ_USBC,
+ .end = ADM5120_IRQ_USBC,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static u64 adm5120_hcd_dma_mask = DMA_BIT_MASK(24);
+struct platform_device adm5120_hcd_device = {
+ .name = "adm5120-hcd",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(adm5120_hcd_resources),
+ .resource = adm5120_hcd_resources,
+ .dev = {
+ .dma_mask = &adm5120_hcd_dma_mask,
+ .coherent_dma_mask = DMA_BIT_MASK(24),
+ }
+};
+
+void __init adm5120_add_device_usb(void)
+{
+ platform_device_register(&adm5120_hcd_device);
+}
+
+/*
+ * NOR flash devices
+ */
+struct adm5120_flash_platform_data adm5120_flash0_data;
+struct platform_device adm5120_flash0_device = {
+ .name = "adm5120-flash",
+ .id = 0,
+ .dev.platform_data = &adm5120_flash0_data,
+};
+
+struct adm5120_flash_platform_data adm5120_flash1_data;
+struct platform_device adm5120_flash1_device = {
+ .name = "adm5120-flash",
+ .id = 1,
+ .dev.platform_data = &adm5120_flash1_data,
+};
+
+void __init adm5120_add_device_flash(unsigned id)
+{
+ struct platform_device *pdev;
+
+ switch (id) {
+ case 0:
+ pdev = &adm5120_flash0_device;
+ break;
+ case 1:
+ pdev = &adm5120_flash1_device;
+ break;
+ default:
+ pdev = NULL;
+ break;
+ }
+
+ if (pdev)
+ platform_device_register(pdev);
+}
+
+/*
+ * built-in UARTs
+ */
+static void adm5120_uart_set_mctrl(struct amba_device *dev, void __iomem *base,
+ unsigned int mctrl)
+{
+}
+
+struct amba_pl010_data adm5120_uart0_data = {
+ .set_mctrl = adm5120_uart_set_mctrl
+};
+
+struct amba_device adm5120_uart0_device = {
+ .dev = {
+ .bus_id = "APB:UART0",
+ .platform_data = &adm5120_uart0_data,
+ },
+ .res = {
+ .start = ADM5120_UART0_BASE,
+ .end = ADM5120_UART0_BASE + ADM5120_UART_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = { ADM5120_IRQ_UART0, -1 },
+ .periphid = 0x0041010,
+};
+
+struct amba_pl010_data adm5120_uart1_data = {
+ .set_mctrl = adm5120_uart_set_mctrl
+};
+
+struct amba_device adm5120_uart1_device = {
+ .dev = {
+ .bus_id = "APB:UART1",
+ .platform_data = &adm5120_uart1_data,
+ },
+ .res = {
+ .start = ADM5120_UART1_BASE,
+ .end = ADM5120_UART1_BASE + ADM5120_UART_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = { ADM5120_IRQ_UART1, -1 },
+ .periphid = 0x0041010,
+};
+
+void __init adm5120_add_device_uart(unsigned id)
+{
+ struct amba_device *dev;
+
+ switch (id) {
+ case 0:
+ dev = &adm5120_uart0_device;
+ break;
+ case 1:
+ dev = &adm5120_uart1_device;
+ break;
+ default:
+ dev = NULL;
+ break;
+ }
+
+ if (dev)
+ amba_device_register(dev, &iomem_resource);
+}
+
+/*
+ * GPIO buttons
+ */
+#define ADM5120_BUTTON_INTERVAL 20
+struct gpio_buttons_platform_data adm5120_gpio_buttons_data = {
+ .poll_interval = ADM5120_BUTTON_INTERVAL,
+};
+
+struct platform_device adm5120_gpio_buttons_device = {
+ .name = "gpio-buttons",
+ .id = -1,
+ .dev.platform_data = &adm5120_gpio_buttons_data,
+};
+
+void __init adm5120_add_device_gpio_buttons(unsigned nbuttons,
+ struct gpio_button *buttons)
+{
+ struct gpio_button *p;
+
+ p = kmalloc(nbuttons * sizeof(*p), GFP_KERNEL);
+ if (!p)
+ return;
+
+ memcpy(p, buttons, nbuttons * sizeof(*p));
+ adm5120_gpio_buttons_data.nbuttons = nbuttons;
+ adm5120_gpio_buttons_data.buttons = p;
+
+ platform_device_register(&adm5120_gpio_buttons_device);
+}
+
+/*
+ * GPIO LEDS
+ */
+struct gpio_led_platform_data adm5120_gpio_leds_data;
+struct platform_device adm5120_gpio_leds_device = {
+ .name = "leds-gpio",
+ .id = -1,
+ .dev.platform_data = &adm5120_gpio_leds_data,
+};
+
+void __init adm5120_add_device_gpio_leds(unsigned num_leds,
+ struct gpio_led *leds)
+{
+ struct gpio_led *p;
+
+ p = kmalloc(num_leds * sizeof(*p), GFP_KERNEL);
+ if (!p)
+ return;
+
+ memcpy(p, leds, num_leds * sizeof(*p));
+ adm5120_gpio_leds_data.num_leds = num_leds;
+ adm5120_gpio_leds_data.leds = p;
+
+ platform_device_register(&adm5120_gpio_leds_device);
+}
+
+/*
+ * GPIO device
+ */
+static struct resource adm5120_gpio_resource[] __initdata = {
+ {
+ .start = 0x3fffff,
+ },
+};
+
+void __init adm5120_add_device_gpio(u32 disable_mask)
+{
+ if (adm5120_package_pqfp())
+ disable_mask |= 0xf0;
+
+ adm5120_gpio_resource[0].start &= ~disable_mask;
+ platform_device_register_simple("GPIODEV", -1,
+ adm5120_gpio_resource,
+ ARRAY_SIZE(adm5120_gpio_resource));
+}
+
+/*
+ * NAND flash
+ */
+struct resource adm5120_nand_resources[] = {
+ [0] = {
+ .start = ADM5120_NAND_BASE,
+ .end = ADM5120_NAND_BASE + ADM5120_NAND_SIZE-1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static int adm5120_nand_ready(struct mtd_info *mtd)
+{
+ return ((adm5120_nand_get_status() & ADM5120_NAND_STATUS_READY) != 0);
+}
+
+static void adm5120_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
+ unsigned int ctrl)
+{
+ if (ctrl & NAND_CTRL_CHANGE) {
+ adm5120_nand_set_cle(ctrl & NAND_CLE);
+ adm5120_nand_set_ale(ctrl & NAND_ALE);
+ adm5120_nand_set_cen(ctrl & NAND_NCE);
+ }
+
+ if (cmd != NAND_CMD_NONE)
+ NAND_WRITE_REG(NAND_REG_DATA, cmd);
+}
+
+void __init adm5120_add_device_nand(struct platform_nand_data *pdata)
+{
+ struct platform_device *pdev;
+ int err;
+
+ pdev = platform_device_alloc("gen_nand", -1);
+ if (!pdev)
+ goto err_out;
+
+ err = platform_device_add_resources(pdev, adm5120_nand_resources,
+ ARRAY_SIZE(adm5120_nand_resources));
+ if (err)
+ goto err_put;
+
+ err = platform_device_add_data(pdev, pdata, sizeof(*pdata));
+ if (err)
+ goto err_put;
+
+ pdata = pdev->dev.platform_data;
+ pdata->ctrl.dev_ready = adm5120_nand_ready;
+ pdata->ctrl.cmd_ctrl = adm5120_nand_cmd_ctrl;
+
+ err = platform_device_add(pdev);
+ if (err)
+ goto err_put;
+
+ return;
+
+err_put:
+ platform_device_put(pdev);
+err_out:
+ return;
+}
--- /dev/null
+/*
+ * ADM5120 specific prom routines
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/io.h>
+
+#include <asm/bootinfo.h>
+#include <asm/addrspace.h>
+
+#include <asm/mach-adm5120/adm5120_info.h>
+#include <asm/mach-adm5120/adm5120_defs.h>
+#include <asm/mach-adm5120/adm5120_uart.h>
+
+#include <prom/cfe.h>
+#include <prom/generic.h>
+#include <prom/routerboot.h>
+#include <prom/myloader.h>
+#include <prom/zynos.h>
+
+unsigned int adm5120_prom_type = ADM5120_PROM_GENERIC;
+
+struct board_desc {
+ unsigned long mach_type;
+ char *name;
+};
+
+#define DEFBOARD(n, mt) { .mach_type = (mt), .name = (n)}
+static struct board_desc common_boards[] __initdata = {
+ /* Cellvision/SparkLAN boards */
+ DEFBOARD("CAS-630", MACH_ADM5120_CAS630),
+ DEFBOARD("CAS-670", MACH_ADM5120_CAS670),
+ DEFBOARD("CAS-700", MACH_ADM5120_CAS700),
+ DEFBOARD("CAS-771", MACH_ADM5120_CAS771),
+ DEFBOARD("CAS-790", MACH_ADM5120_CAS790),
+ DEFBOARD("CAS-861", MACH_ADM5120_CAS861),
+ DEFBOARD("NFS-101U", MACH_ADM5120_NFS101U),
+ /* Compex boards */
+ DEFBOARD("WP54G-WRT", MACH_ADM5120_WP54G_WRT),
+ /* Edimax boards */
+ DEFBOARD("BR-6104K", MACH_ADM5120_BR6104K),
+ DEFBOARD("BR-6104KP", MACH_ADM5120_BR6104KP),
+ DEFBOARD("BR-6104WG", MACH_ADM5120_BR61X4WG),
+ DEFBOARD("BR-6114WG", MACH_ADM5120_BR61X4WG),
+ /* Infineon boards */
+ DEFBOARD("EASY 5120P-ATA", MACH_ADM5120_EASY5120PATA),
+ DEFBOARD("EASY 5120-RT", MACH_ADM5120_EASY5120RT),
+ DEFBOARD("EASY 5120-WVoIP", MACH_ADM5120_EASY5120WVOIP),
+ DEFBOARD("EASY 83000", MACH_ADM5120_EASY83000),
+ /* Mikrotik RouterBOARDs */
+ DEFBOARD("111", MACH_ADM5120_RB_11X),
+ DEFBOARD("112", MACH_ADM5120_RB_11X),
+ DEFBOARD("133", MACH_ADM5120_RB_133),
+ DEFBOARD("133C", MACH_ADM5120_RB_133C),
+ DEFBOARD("133C3", MACH_ADM5120_RB_133C),
+ DEFBOARD("150", MACH_ADM5120_RB_153), /* it's intentional */
+ DEFBOARD("153", MACH_ADM5120_RB_153),
+ DEFBOARD("192", MACH_ADM5120_RB_192),
+ DEFBOARD("miniROUTER", MACH_ADM5120_RB_150),
+ /* Motorola boards */
+ DEFBOARD("Powerline MU Gateway",MACH_ADM5120_PMUGW),
+};
+
+static unsigned long __init find_machtype_byname(char *name)
+{
+ unsigned long ret;
+ int i;
+
+ ret = MACH_ADM5120_GENERIC;
+ if (name == NULL)
+ goto out;
+
+ if (*name == '\0')
+ goto out;
+
+ for (i = 0; i < ARRAY_SIZE(common_boards); i++) {
+ if (strcmp(common_boards[i].name, name) == 0) {
+ ret = common_boards[i].mach_type;
+ break;
+ }
+ }
+
+out:
+ return ret;
+}
+
+static unsigned long __init detect_machtype_routerboot(void)
+{
+ char *name;
+
+ name = routerboot_get_boardname();
+ return find_machtype_byname(name);
+}
+
+static unsigned long __init detect_machtype_generic(void)
+{
+ char *name;
+
+ name = generic_prom_getenv("board_name");
+ return find_machtype_byname(name);
+}
+
+unsigned long __init detect_machtype_cfe(void)
+{
+ char *name;
+
+ name = cfe_getenv("BOARD_NAME");
+ return find_machtype_byname(name);
+}
+
+static struct {
+ unsigned long mach_type;
+ u16 vendor_id;
+ u16 board_id;
+} zynos_boards[] __initdata = {
+#define ZYNOS_BOARD(vi, bi, mt) \
+ {.vendor_id = (vi), .board_id = (bi), .mach_type = (mt)}
+
+#define ZYXEL_BOARD(bi, mt) ZYNOS_BOARD(ZYNOS_VENDOR_ID_ZYXEL, bi, mt)
+#define DLINK_BOARD(bi, mt) ZYNOS_BOARD(ZYNOS_VENDOR_ID_DLINK, bi, mt)
+#define LUCENT_BOARD(bi, mt) ZYNOS_BOARD(ZYNOS_VENDOR_ID_LUCENT, bi, mt)
+ ZYXEL_BOARD(ZYNOS_BOARD_HS100, MACH_ADM5120_HS100),
+ ZYXEL_BOARD(ZYNOS_BOARD_P334U, MACH_ADM5120_P334U),
+ ZYXEL_BOARD(ZYNOS_BOARD_P334W, MACH_ADM5120_P334W),
+ ZYXEL_BOARD(ZYNOS_BOARD_P334WH, MACH_ADM5120_P334WH),
+ ZYXEL_BOARD(ZYNOS_BOARD_P334WHD, MACH_ADM5120_P334WHD),
+ ZYXEL_BOARD(ZYNOS_BOARD_P334WT, MACH_ADM5120_P334WT),
+ ZYXEL_BOARD(ZYNOS_BOARD_P334WT_ALT, MACH_ADM5120_P334WT),
+ ZYXEL_BOARD(ZYNOS_BOARD_P335, MACH_ADM5120_P335),
+ ZYXEL_BOARD(ZYNOS_BOARD_P335PLUS, MACH_ADM5120_P335PLUS),
+ ZYXEL_BOARD(ZYNOS_BOARD_P335U, MACH_ADM5120_P335U)
+};
+
+static unsigned long __init detect_machtype_bootbase(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(zynos_boards); i++) {
+ if (zynos_boards[i].vendor_id == bootbase_info.vendor_id &&
+ zynos_boards[i].board_id == bootbase_info.board_id) {
+ return zynos_boards[i].mach_type;
+ break;
+ }
+ }
+
+ printk(KERN_WARNING "Unknown ZyXEL model (%u)\n",
+ bootbase_info.board_id);
+ return MACH_ADM5120_GENERIC;
+}
+
+static struct {
+ unsigned long mach_type;
+ u16 vid;
+ u16 did;
+ u16 svid;
+ u16 sdid;
+} mylo_boards[] __initdata = {
+#define MYLO_BOARD(v, d, sv, sd, mt) \
+ {.vid = (v), .did = (d), .svid = (sv), .sdid = (sd), .mach_type = (mt)}
+#define COMPEX_BOARD(d, mt) \
+ MYLO_BOARD(VENID_COMPEX, (d), VENID_COMPEX, (d), (mt))
+
+ COMPEX_BOARD(DEVID_COMPEX_NP27G, MACH_ADM5120_NP27G),
+ COMPEX_BOARD(DEVID_COMPEX_NP28G, MACH_ADM5120_NP28G),
+ COMPEX_BOARD(DEVID_COMPEX_NP28GHS, MACH_ADM5120_NP28GHS),
+ COMPEX_BOARD(DEVID_COMPEX_WP54G, MACH_ADM5120_WP54),
+ COMPEX_BOARD(DEVID_COMPEX_WP54Gv1C, MACH_ADM5120_WP54Gv1C),
+ COMPEX_BOARD(DEVID_COMPEX_WP54AG, MACH_ADM5120_WP54),
+ COMPEX_BOARD(DEVID_COMPEX_WPP54G, MACH_ADM5120_WP54),
+ COMPEX_BOARD(DEVID_COMPEX_WPP54AG, MACH_ADM5120_WP54),
+};
+
+static unsigned long __init detect_machtype_myloader(void)
+{
+ unsigned long ret;
+ int i;
+
+ ret = MACH_ADM5120_GENERIC;
+ for (i = 0; i < ARRAY_SIZE(mylo_boards); i++) {
+ if (mylo_boards[i].vid == myloader_info.vid &&
+ mylo_boards[i].did == myloader_info.did &&
+ mylo_boards[i].svid == myloader_info.svid &&
+ mylo_boards[i].sdid == myloader_info.sdid) {
+ ret = mylo_boards[i].mach_type;
+ break;
+ }
+ }
+
+ return ret;
+}
+
+static void __init prom_detect_machtype(void)
+{
+ if (bootbase_present()) {
+ adm5120_prom_type = ADM5120_PROM_BOOTBASE;
+ mips_machtype = detect_machtype_bootbase();
+ return;
+ }
+
+ if (cfe_present()) {
+ adm5120_prom_type = ADM5120_PROM_CFE;
+ mips_machtype = detect_machtype_cfe();
+ return;
+ }
+
+ if (myloader_present()) {
+ adm5120_prom_type = ADM5120_PROM_MYLOADER;
+ mips_machtype = detect_machtype_myloader();
+ return;
+ }
+
+ if (routerboot_present()) {
+ adm5120_prom_type = ADM5120_PROM_ROUTERBOOT;
+ mips_machtype = detect_machtype_routerboot();
+ return;
+ }
+
+ if (generic_prom_present()) {
+ adm5120_prom_type = ADM5120_PROM_GENERIC;
+ mips_machtype = detect_machtype_generic();
+ return;
+ }
+
+ mips_machtype = MACH_ADM5120_GENERIC;
+}
+
+/* TODO: this is an ugly hack for RouterBOARDS */
+extern char _image_cmdline;
+static void __init prom_init_cmdline(void)
+{
+ char *cmd;
+
+ /* init command line, register a default kernel command line */
+ cmd = &_image_cmdline + 8;
+ if (strlen(cmd) > 0)
+ strlcpy(arcs_cmdline, cmd, sizeof(arcs_cmdline));
+
+}
+
+#define UART_READ(r) \
+ __raw_readl((void __iomem *)(KSEG1ADDR(ADM5120_UART0_BASE)+(r)))
+#define UART_WRITE(r, v) \
+ __raw_writel((v), (void __iomem *)(KSEG1ADDR(ADM5120_UART0_BASE)+(r)))
+
+void __init prom_putchar(char ch)
+{
+ while ((UART_READ(UART_REG_FLAG) & UART_FLAG_TXFE) == 0);
+ UART_WRITE(UART_REG_DATA, ch);
+ while ((UART_READ(UART_REG_FLAG) & UART_FLAG_TXFE) == 0);
+}
+
+void __init prom_init(void)
+{
+ prom_detect_machtype();
+ prom_init_cmdline();
+}
+
+void __init prom_free_prom_memory(void)
+{
+ /* We do not have to prom memory to free */
+}
--- /dev/null
+/*
+ * ADM5120 specific setup
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This code was based on the ADM5120 specific port of the Linux 2.6.10 kernel
+ * done by Jeroen Vreeken
+ * Copyright (C) 2005 Jeroen Vreeken (pe1rxq@amsat.org)
+ *
+ * Jeroen's code was based on the Linux 2.4.xx source codes found in various
+ * tarballs released by Edimax for it's ADM5120 based devices
+ * Copyright (C) ADMtek Incorporated
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+
+#include <asm/reboot.h>
+#include <asm/time.h>
+
+#include <asm/mach-adm5120/adm5120_info.h>
+#include <asm/mach-adm5120/adm5120_defs.h>
+#include <asm/mach-adm5120/adm5120_switch.h>
+#include <asm/mach-adm5120/adm5120_board.h>
+
+void (*adm5120_board_reset)(void);
+
+static char *prom_names[ADM5120_PROM_LAST+1] __initdata = {
+ [ADM5120_PROM_GENERIC] = "Generic",
+ [ADM5120_PROM_CFE] = "CFE",
+ [ADM5120_PROM_UBOOT] = "U-Boot",
+ [ADM5120_PROM_MYLOADER] = "MyLoader",
+ [ADM5120_PROM_ROUTERBOOT] = "RouterBOOT",
+ [ADM5120_PROM_BOOTBASE] = "Bootbase"
+};
+
+static void __init adm5120_report(void)
+{
+ printk(KERN_INFO "SoC : ADM%04X%s revision %d, running "
+ "at %ldMHz\n",
+ adm5120_product_code,
+ adm5120_package_bga() ? "" : "P",
+ adm5120_revision, (adm5120_speed / 1000000));
+ printk(KERN_INFO "Bootdev : %s flash\n",
+ adm5120_nand_boot ? "NAND":"NOR");
+ printk(KERN_INFO "Prom : %s\n", prom_names[adm5120_prom_type]);
+}
+
+static void adm5120_restart(char *command)
+{
+ /* TODO: stop switch before reset */
+
+ if (adm5120_board_reset)
+ adm5120_board_reset();
+
+ SW_WRITE_REG(SWITCH_REG_SOFT_RESET, 1);
+}
+
+static void adm5120_halt(void)
+{
+ local_irq_disable();
+
+ while (1) {
+ if (cpu_wait)
+ cpu_wait();
+ }
+}
+
+void __init plat_time_init(void)
+{
+ mips_hpt_frequency = adm5120_speed / 2;
+}
+
+void __init plat_mem_setup(void)
+{
+ adm5120_soc_init();
+ adm5120_mem_init();
+ adm5120_report();
+
+ _machine_restart = adm5120_restart;
+ _machine_halt = adm5120_halt;
+ pm_power_off = adm5120_halt;
+
+ set_io_port_base(KSEG1);
+}
--- /dev/null
+obj-y += compex.o
+
+obj-$(CONFIG_ADM5120_MACH_NP27G) += np27g.o
+obj-$(CONFIG_ADM5120_MACH_NP28G) += np28g.o
+obj-$(CONFIG_ADM5120_MACH_WP54) += wp54.o
--- /dev/null
+/*
+ * Compex boards
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "compex.h"
+
+#include <asm/mach-adm5120/prom/myloader.h>
+
+#define COMPEX_GPIO_DEV_MASK (1 << ADM5120_GPIO_PIN5)
+
+static void switch_bank_gpio5(unsigned bank)
+{
+ switch (bank) {
+ case 0:
+ gpio_set_value(ADM5120_GPIO_PIN5, 0);
+ break;
+ case 1:
+ gpio_set_value(ADM5120_GPIO_PIN5, 1);
+ break;
+ }
+}
+
+void __init compex_mac_setup(void)
+{
+ if (myloader_present()) {
+ int i;
+
+ for (i = 0; i < 6; i++) {
+ if (is_valid_ether_addr(myloader_info.macs[i]))
+ memcpy(adm5120_eth_macs[i],
+ myloader_info.macs[i], ETH_ALEN);
+ else
+ random_ether_addr(adm5120_eth_macs[i]);
+ }
+ } else {
+ u8 mac[ETH_ALEN];
+
+ random_ether_addr(mac);
+ adm5120_setup_eth_macs(mac);
+ }
+}
+
+void __init compex_generic_setup(void)
+{
+ gpio_request(ADM5120_GPIO_PIN5, NULL); /* for flash A20 line */
+ gpio_direction_output(ADM5120_GPIO_PIN5, 0);
+
+ adm5120_flash0_data.switch_bank = switch_bank_gpio5;
+ adm5120_add_device_flash(0);
+
+ adm5120_add_device_uart(0);
+ adm5120_add_device_uart(1);
+
+ adm5120_add_device_gpio(COMPEX_GPIO_DEV_MASK);
+
+ compex_mac_setup();
+}
--- /dev/null
+/*
+ * Compex boards
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <linux/etherdevice.h>
+
+#include <asm/bootinfo.h>
+
+#include <asm/mach-adm5120/adm5120_info.h>
+#include <asm/mach-adm5120/adm5120_board.h>
+#include <asm/mach-adm5120/adm5120_platform.h>
+
+extern void compex_generic_setup(void) __init;
--- /dev/null
+/*
+ * Compex NP27G board support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "compex.h"
+
+static u8 np27g_vlans[6] __initdata = {
+ /* FIXME: untested */
+ 0x41, 0x42, 0x44, 0x48, 0x50, 0x00
+};
+
+static void __init np27g_setup(void)
+{
+ compex_generic_setup();
+ adm5120_add_device_switch(5, np27g_vlans);
+ adm5120_add_device_usb();
+
+ /* TODO: add PCI IRQ map */
+}
+
+ADM5120_BOARD(MACH_ADM5120_NP27G, "Compex NetPassage 27G", np27g_setup);
--- /dev/null
+/*
+ * Compex NP28G board support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "compex.h"
+
+static struct adm5120_pci_irq np28g_pci_irqs[] __initdata = {
+ PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI0),
+ PCIIRQ(3, 0, 1, ADM5120_IRQ_PCI0),
+ PCIIRQ(3, 1, 2, ADM5120_IRQ_PCI1),
+ PCIIRQ(3, 2, 3, ADM5120_IRQ_PCI2)
+};
+
+static struct gpio_led np28g_gpio_leds[] __initdata = {
+ GPIO_LED_INV(ADM5120_GPIO_PIN2, "diag", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_PIN3, "power", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_PIN6, "wan_cond", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_PIN7, "wifi", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P0L2, "usb1", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan1", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P1L2, "usb2", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan2", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P2L2, "usb3", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P3L0, "lan3", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P3L2, "usb4", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P4L0, "wan", NULL),
+};
+
+static u8 np28g_vlans[6] __initdata = {
+ 0x50, 0x42, 0x44, 0x48, 0x00, 0x00
+};
+
+static void np28g_reset(void)
+{
+ gpio_set_value(ADM5120_GPIO_PIN4, 0);
+}
+
+static void __init np28g_setup(void)
+{
+ compex_generic_setup();
+
+ /* setup reset line */
+ gpio_request(ADM5120_GPIO_PIN4, NULL);
+ gpio_direction_output(ADM5120_GPIO_PIN4, 1);
+ adm5120_board_reset = np28g_reset;
+
+ adm5120_add_device_switch(4, np28g_vlans);
+ adm5120_add_device_usb();
+
+ adm5120_add_device_gpio_leds(ARRAY_SIZE(np28g_gpio_leds),
+ np28g_gpio_leds);
+
+ adm5120_pci_set_irq_map(ARRAY_SIZE(np28g_pci_irqs), np28g_pci_irqs);
+}
+
+ADM5120_BOARD(MACH_ADM5120_NP28G, "Compex NetPassage 28G", np28g_setup);
--- /dev/null
+/*
+ * Compex WP54 board support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "compex.h"
+
+#ifdef CONFIG_MTD_PARTITIONS
+static struct mtd_partition wp54g_wrt_partitions[] = {
+ {
+ .name = "cfe",
+ .offset = 0,
+ .size = 0x050000,
+ .mask_flags = MTD_WRITEABLE,
+ } , {
+ .name = "trx",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 0x3A0000,
+ } , {
+ .name = "nvram",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 0x010000,
+ }
+};
+#endif /* CONFIG_MTD_PARTITIONS */
+
+static struct adm5120_pci_irq wp54_pci_irqs[] __initdata = {
+ PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI0),
+};
+
+static struct gpio_button wp54_gpio_buttons[] __initdata = {
+ {
+ .desc = "reset_button",
+ .type = EV_KEY,
+ .code = BTN_0,
+ .threshold = 5,
+ .gpio = ADM5120_GPIO_PIN4,
+ }
+};
+
+static struct gpio_led wp54_gpio_leds[] __initdata = {
+ GPIO_LED_INV(ADM5120_GPIO_PIN2, "diag", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_PIN6, "wlan", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_PIN7, "wan", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P0L0, "lan1", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan2", NULL),
+};
+
+static u8 wp54_vlans[6] __initdata = {
+ 0x41, 0x42, 0x00, 0x00, 0x00, 0x00
+};
+
+static void wp54_reset(void)
+{
+ gpio_set_value(ADM5120_GPIO_PIN3, 0);
+}
+
+static void __init wp54_setup(void)
+{
+ compex_generic_setup();
+
+ /* setup reset line */
+ gpio_request(ADM5120_GPIO_PIN3, NULL);
+ gpio_direction_output(ADM5120_GPIO_PIN3, 1);
+ adm5120_board_reset = wp54_reset;
+
+ adm5120_add_device_switch(2, wp54_vlans);
+ adm5120_add_device_gpio_buttons(ARRAY_SIZE(wp54_gpio_buttons),
+ wp54_gpio_buttons);
+ adm5120_add_device_gpio_leds(ARRAY_SIZE(wp54_gpio_leds),
+ wp54_gpio_leds);
+
+ adm5120_pci_set_irq_map(ARRAY_SIZE(wp54_pci_irqs), wp54_pci_irqs);
+}
+
+ADM5120_BOARD(MACH_ADM5120_WP54, "Compex WP54 family", wp54_setup);
+
+static void __init wp54_wrt_setup(void)
+{
+#ifdef CONFIG_MTD_PARTITIONS
+ adm5120_flash0_data.nr_parts = ARRAY_SIZE(wp54g_wrt_partitions);
+ adm5120_flash0_data.parts = wp54g_wrt_partitions;
+#endif
+
+ wp54_setup();
+}
+
+ADM5120_BOARD(MACH_ADM5120_WP54G_WRT, "Compex WP54G-WRT", wp54_wrt_setup);
--- /dev/null
+obj-y := br-61xx.o
+
+obj-$(CONFIG_ADM5120_MACH_BR_6104K) += br-6104k.o
+obj-$(CONFIG_ADM5120_MACH_BR_6104KP) += br-6104kp.o
+obj-$(CONFIG_ADM5120_MACH_BR_61X4WG) += br-61x4wg.o
--- /dev/null
+/*
+ * Edimax BR-6104K board support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "br-61xx.h"
+
+static struct gpio_led br6104k_gpio_leds[] __initdata = {
+ GPIO_LED_STD(ADM5120_GPIO_PIN0, "power", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P0L1, "wan_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P0L0, "wan_lnkact", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P1L1, "lan1_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan1_lnkact", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P2L1, "lan2_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan2_lnkact", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P3L1, "lan3_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P3L0, "lan3_lnkact", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P4L1, "lan4_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P4L0, "lan4_lnkact", NULL),
+};
+
+static void __init br6104k_setup(void)
+{
+ br61xx_generic_setup();
+ adm5120_add_device_gpio_leds(ARRAY_SIZE(br6104k_gpio_leds),
+ br6104k_gpio_leds);
+}
+
+ADM5120_BOARD(MACH_ADM5120_BR6104K, "Edimax BR-6104K", br6104k_setup);
--- /dev/null
+/*
+ * Edimax BR-6104KP board support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "br-61xx.h"
+
+static struct gpio_led br6104kp_gpio_leds[] __initdata = {
+ GPIO_LED_STD(ADM5120_GPIO_PIN0, "power", NULL),
+ GPIO_LED_STD(ADM5120_GPIO_PIN1, "usb1", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_PIN3, "usb2", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P0L1, "wan_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P0L0, "wan_lnkact", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P1L1, "lan1_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan1_lnkact", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P2L1, "lan2_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan2_lnkact", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P3L1, "lan3_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P3L0, "lan3_lnkact", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P4L1, "lan4_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P4L0, "lan4_lnkact", NULL),
+};
+
+static void __init br6104kp_setup(void)
+{
+ br61xx_generic_setup();
+ adm5120_add_device_gpio_leds(ARRAY_SIZE(br6104kp_gpio_leds),
+ br6104kp_gpio_leds);
+ adm5120_add_device_usb();
+}
+
+ADM5120_BOARD(MACH_ADM5120_BR6104KP, "Edimax BR-6104KP", br6104kp_setup);
--- /dev/null
+/*
+ * Edimax BR-6104Wg/6114WG board support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "br-61xx.h"
+
+static struct adm5120_pci_irq br61x4wg_pci_irqs[] __initdata = {
+ PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI0),
+};
+
+static struct gpio_led br61x4wg_gpio_leds[] __initdata = {
+ GPIO_LED_STD(ADM5120_GPIO_PIN0, "power", NULL),
+ GPIO_LED_STD(ADM5120_GPIO_PIN5, "wlan", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P0L1, "wan_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P0L0, "wan_lnkact", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P1L1, "lan1_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan1_lnkact", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P2L1, "lan2_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan2_lnkact", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P3L1, "lan3_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P3L0, "lan3_lnkact", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P4L1, "lan4_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P4L0, "lan4_lnkact", NULL),
+};
+
+static void __init br61x4wg_setup(void)
+{
+ br61xx_generic_setup();
+ adm5120_add_device_gpio_leds(ARRAY_SIZE(br61x4wg_gpio_leds),
+ br61x4wg_gpio_leds);
+ adm5120_pci_set_irq_map(ARRAY_SIZE(br61x4wg_pci_irqs),
+ br61x4wg_pci_irqs);
+}
+
+ADM5120_BOARD(MACH_ADM5120_BR61X4WG, "Edimax BR-6104WG/6114WG", br61x4wg_setup);
--- /dev/null
+/*
+ * Edimax BR-61xx support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "br-61xx.h"
+
+#include <prom/admboot.h>
+
+#define BR61XX_GPIO_DEV_MASK 0
+
+#define BR61XX_CONFIG_OFFSET 0x8000
+#define BR61XX_CONFIG_SIZE 0x1000
+
+#ifdef CONFIG_MTD_PARTITIONS
+static struct mtd_partition br61xx_partitions[] = {
+ {
+ .name = "admboot",
+ .offset = 0,
+ .size = 32*1024,
+ .mask_flags = MTD_WRITEABLE,
+ } , {
+ .name = "config",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 32*1024,
+ } , {
+ .name = "firmware",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+#endif /* CONFIG_MTD_PARTITIONS */
+
+static struct gpio_button br61xx_gpio_buttons[] __initdata = {
+ {
+ .desc = "reset_button",
+ .type = EV_KEY,
+ .code = BTN_0,
+ .threshold = 5,
+ .gpio = ADM5120_GPIO_PIN2,
+ }
+};
+
+static u8 br61xx_vlans[6] __initdata = {
+ 0x41, 0x42, 0x44, 0x48, 0x50, 0x00
+};
+
+static void __init br61xx_mac_setup(void)
+{
+ u8 mac_base[6];
+ int err;
+
+ err = admboot_get_mac_base(BR61XX_CONFIG_OFFSET,
+ BR61XX_CONFIG_SIZE, mac_base);
+
+ if ((err) || !is_valid_ether_addr(mac_base))
+ random_ether_addr(mac_base);
+
+ adm5120_setup_eth_macs(mac_base);
+}
+
+void __init br61xx_generic_setup(void)
+{
+
+#ifdef CONFIG_MTD_PARTITIONS
+ adm5120_flash0_data.nr_parts = ARRAY_SIZE(br61xx_partitions);
+ adm5120_flash0_data.parts = br61xx_partitions;
+#endif /* CONFIG_MTD_PARTITIONS */
+ adm5120_add_device_flash(0);
+
+ adm5120_add_device_gpio(BR61XX_GPIO_DEV_MASK);
+
+ adm5120_add_device_uart(0);
+ adm5120_add_device_uart(1);
+
+ adm5120_add_device_switch(5, br61xx_vlans);
+ adm5120_add_device_gpio_buttons(ARRAY_SIZE(br61xx_gpio_buttons),
+ br61xx_gpio_buttons);
+
+ br61xx_mac_setup();
+}
--- /dev/null
+/*
+ * Edimax BR-61xx board support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <linux/etherdevice.h>
+
+#include <asm/bootinfo.h>
+
+#include <asm/mach-adm5120/adm5120_board.h>
+#include <asm/mach-adm5120/adm5120_platform.h>
+
+extern void __init br61xx_generic_setup(void) __init;
--- /dev/null
+obj-y += infineon.o
+
+obj-$(CONFIG_ADM5120_MACH_EASY5120_RT) += easy5120-rt.o
+obj-$(CONFIG_ADM5120_MACH_EASY5120_WVOIP) += easy5120-wvoip.o
+obj-$(CONFIG_ADM5120_MACH_EASY5120P_ATA) += easy5120p-ata.o
+obj-$(CONFIG_ADM5120_MACH_EASY83000) += easy83000.o
--- /dev/null
+/*
+ * Infineon EASY 5120-RT Reference Board support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "infineon.h"
+
+static struct gpio_led easy5120_rt_gpio_leds[] __initdata = {
+ GPIO_LED_INV(ADM5120_GPIO_PIN6, "user", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P0L0, "lan0_led1", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P0L1, "lan0_led2", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan1_led1", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P1L1, "lan1_led2", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan2_led1", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P2L1, "lan2_led2", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P3L0, "lan3_led1", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P3L1, "lan3_led2", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P4L0, "wan", NULL),
+};
+
+static struct adm5120_pci_irq easy5120_rt_pci_irqs[] __initdata = {
+ PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI0),
+};
+
+static u8 easy5120_rt_vlans[6] __initdata = {
+ 0x41, 0x42, 0x44, 0x48, 0x50, 0x00
+};
+
+static void __init easy5120_rt_setup(void)
+{
+ easy_setup_bga();
+
+ adm5120_add_device_switch(5, easy5120_rt_vlans);
+ adm5120_add_device_usb();
+ adm5120_add_device_gpio_leds(ARRAY_SIZE(easy5120_rt_gpio_leds),
+ easy5120_rt_gpio_leds);
+ adm5120_pci_set_irq_map(ARRAY_SIZE(easy5120_rt_pci_irqs),
+ easy5120_rt_pci_irqs);
+}
+
+ADM5120_BOARD(MACH_ADM5120_EASY5120RT,
+ "Infineon EASY 5120-RT Reference Board",
+ easy5120_rt_setup);
--- /dev/null
+/*
+ * Infineon EASY 5120-WVoIP Reference Board support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "infineon.h"
+
+static void __init easy5120wvoip_setup(void)
+{
+ easy_setup_bga();
+ adm5120_add_device_switch(6, NULL);
+
+ /* TODO: add VINETIC2 device */
+ /* TODO: setup PCI IRQ map */
+}
+
+ADM5120_BOARD(MACH_ADM5120_EASY5120WVOIP,
+ "Infineon EASY 5120-WVoIP Reference Board",
+ easy5120wvoip_setup);
--- /dev/null
+/*
+ * Infineon EASY 5120P-ATA Reference Board support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "infineon.h"
+
+static void __init easy5120pata_setup(void)
+{
+ easy_setup_pqfp();
+
+ adm5120_add_device_switch(6, NULL);
+}
+
+ADM5120_BOARD(MACH_ADM5120_EASY5120PATA,
+ "Infineon EASY 5120P-ATA Reference Board",
+ easy5120pata_setup);
--- /dev/null
+/*
+ * Infineon EASY 83000 Reference Board support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "infineon.h"
+
+static void __init easy83000_setup(void)
+{
+ easy_setup_pqfp();
+ adm5120_add_device_switch(6, NULL);
+
+ /* TODO: add VINAX device */
+}
+
+ADM5120_BOARD(MACH_ADM5120_EASY83000,
+ "Infineon EASY 83000 Reference Board",
+ easy83000_setup);
--- /dev/null
+/*
+ * Infineon Reference Boards
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "infineon.h"
+
+#include <prom/admboot.h>
+
+#define EASY_CONFIG_OFFSET 0x10000
+#define EASY_CONFIG_SIZE 0x1000
+
+#ifdef CONFIG_MTD_PARTITIONS
+static struct mtd_partition easy_partitions[] = {
+ {
+ .name = "admboot",
+ .offset = 0,
+ .size = 64*1024,
+ .mask_flags = MTD_WRITEABLE,
+ } , {
+ .name = "boardcfg",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 64*1024,
+ } , {
+ .name = "firmware",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+#endif /* CONFIG_MTD_PARTITIONS */
+
+static __init void easy_setup_mac(void)
+{
+ u8 mac_base[6];
+ int err;
+
+ err = admboot_get_mac_base(EASY_CONFIG_OFFSET,
+ EASY_CONFIG_SIZE, mac_base);
+
+ if ((err) || !is_valid_ether_addr(mac_base))
+ random_ether_addr(mac_base);
+
+ adm5120_setup_eth_macs(mac_base);
+}
+
+static void switch_bank_gpio3(unsigned bank)
+{
+ switch (bank) {
+ case 0:
+ gpio_set_value(ADM5120_GPIO_PIN3, 0);
+ break;
+ case 1:
+ gpio_set_value(ADM5120_GPIO_PIN3, 1);
+ break;
+ }
+}
+
+void __init easy_setup_pqfp(void)
+{
+ /* setup flash A20 line */
+ gpio_request(ADM5120_GPIO_PIN3, NULL);
+ gpio_direction_output(ADM5120_GPIO_PIN3, 0);
+ adm5120_flash0_data.switch_bank = switch_bank_gpio3;
+
+#ifdef CONFIG_MTD_PARTITIONS
+ adm5120_flash0_data.nr_parts = ARRAY_SIZE(easy_partitions);
+ adm5120_flash0_data.parts = easy_partitions;
+#endif /* CONFIG_MTD_PARTITIONS */
+
+ adm5120_add_device_uart(0);
+ adm5120_add_device_uart(1);
+
+ adm5120_add_device_flash(0);
+
+ easy_setup_mac();
+}
+
+static void switch_bank_gpio5(unsigned bank)
+{
+ switch (bank) {
+ case 0:
+ gpio_set_value(ADM5120_GPIO_PIN5, 0);
+ break;
+ case 1:
+ gpio_set_value(ADM5120_GPIO_PIN5, 1);
+ break;
+ }
+}
+
+void __init easy_setup_bga(void)
+{
+ /* setup flash A20 line */
+ gpio_request(ADM5120_GPIO_PIN5, NULL);
+ gpio_direction_output(ADM5120_GPIO_PIN5, 0);
+ adm5120_flash0_data.switch_bank = switch_bank_gpio5;
+
+#ifdef CONFIG_MTD_PARTITIONS
+ adm5120_flash0_data.nr_parts = ARRAY_SIZE(easy_partitions);
+ adm5120_flash0_data.parts = easy_partitions;
+#endif /* CONFIG_MTD_PARTITIONS */
+
+ adm5120_add_device_uart(0);
+ adm5120_add_device_uart(1);
+
+ adm5120_add_device_flash(0);
+
+ easy_setup_mac();
+}
--- /dev/null
+/*
+ * Infineon Reference Boards
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <linux/etherdevice.h>
+
+#include <asm/bootinfo.h>
+
+#include <asm/mach-adm5120/adm5120_defs.h>
+#include <asm/mach-adm5120/adm5120_board.h>
+#include <asm/mach-adm5120/adm5120_platform.h>
+#include <asm/mach-adm5120/adm5120_info.h>
+
+extern void easy_setup_pqfp(void) __init;
+extern void easy_setup_bga(void) __init;
--- /dev/null
+obj-y += rb-1xx.o
+
+obj-${CONFIG_ADM5120_MACH_RB_11X} += rb-11x.o
+obj-${CONFIG_ADM5120_MACH_RB_133} += rb-133.o
+obj-${CONFIG_ADM5120_MACH_RB_133C} += rb-133c.o
+obj-${CONFIG_ADM5120_MACH_RB_150} += rb-150.o
+obj-${CONFIG_ADM5120_MACH_RB_153} += rb-153.o
+obj-${CONFIG_ADM5120_MACH_RB_192} += rb-192.o
--- /dev/null
+/*
+ * Mikrotik RouterBOARD 111/112 support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "rb-1xx.h"
+
+static struct gpio_led rb11x_gpio_leds[] __initdata = {
+ GPIO_LED_STD(ADM5120_GPIO_PIN3, "user", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P0L1, "lan_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P0L0, "lan_lnkact", NULL),
+};
+
+static u8 rb11x_vlans[6] __initdata = {
+ 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+static void __init rb11x_setup(void)
+{
+ rb1xx_generic_setup();
+ rb1xx_add_device_nand();
+
+ adm5120_add_device_switch(1, rb11x_vlans);
+ adm5120_add_device_gpio(0);
+ adm5120_add_device_gpio_leds(ARRAY_SIZE(rb11x_gpio_leds),
+ rb11x_gpio_leds);
+}
+
+ADM5120_BOARD(MACH_ADM5120_RB_11X, "Mikrotik RouterBOARD 111/112", rb11x_setup);
--- /dev/null
+/*
+ * Mikrotik RouterBOARD 133 support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "rb-1xx.h"
+
+static struct gpio_led rb133_gpio_leds[] __initdata = {
+ GPIO_LED_STD(ADM5120_GPIO_PIN6, "power", NULL),
+ GPIO_LED_STD(ADM5120_GPIO_PIN5, "user", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P2L1, "lan1_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan1_lnkact", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P1L1, "lan2_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan2_lnkact", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P0L1, "lan3_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P0L0, "lan3_lnkact", NULL),
+};
+
+static u8 rb133_vlans[6] __initdata = {
+ 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+static void __init rb133_setup(void)
+{
+ rb1xx_generic_setup();
+ rb1xx_add_device_nand();
+
+ adm5120_add_device_switch(3, rb133_vlans);
+ adm5120_add_device_gpio(0);
+ adm5120_add_device_gpio_leds(ARRAY_SIZE(rb133_gpio_leds),
+ rb133_gpio_leds);
+}
+
+ADM5120_BOARD(MACH_ADM5120_RB_133, "Mikrotik RouterBOARD 133", rb133_setup);
--- /dev/null
+/*
+ * Mikrotik RouterBOARD 133C support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "rb-1xx.h"
+
+static struct gpio_led rb133c_gpio_leds[] __initdata = {
+ GPIO_LED_STD(ADM5120_GPIO_PIN6, "power", NULL),
+ GPIO_LED_STD(ADM5120_GPIO_PIN5, "user", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P2L1, "lan1_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan1_lnkact", NULL),
+};
+
+static u8 rb133c_vlans[6] __initdata = {
+ 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+static void __init rb133c_setup(void)
+{
+ rb1xx_generic_setup();
+ rb1xx_add_device_nand();
+
+ adm5120_add_device_switch(1, rb133c_vlans);
+ adm5120_add_device_gpio(0);
+ adm5120_add_device_gpio_leds(ARRAY_SIZE(rb133c_gpio_leds),
+ rb133c_gpio_leds);
+}
+
+ADM5120_BOARD(MACH_ADM5120_RB_133C, "Mikrotik RouterBOARD 133C", rb133c_setup);
--- /dev/null
+/*
+ * Mikrotik RouterBOARD 150 support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "rb-1xx.h"
+
+#define RB150_NAND_BASE 0x1FC80000
+#define RB150_NAND_SIZE 1
+
+#define RB150_GPIO_NAND_READY ADM5120_GPIO_PIN0
+#define RB150_GPIO_NAND_NCE ADM5120_GPIO_PIN1
+#define RB150_GPIO_NAND_CLE ADM5120_GPIO_P2L2
+#define RB150_GPIO_NAND_ALE ADM5120_GPIO_P3L2
+#define RB150_GPIO_RESET_BUTTON ADM5120_GPIO_PIN1 /* FIXME */
+
+#define RB150_GPIO_DEV_MASK ( 1 << RB150_GPIO_NAND_READY \
+ | 1 << RB150_GPIO_NAND_NCE \
+ | 1 << RB150_GPIO_NAND_CLE \
+ | 1 << RB150_GPIO_NAND_ALE)
+
+#define RB150_NAND_DELAY 100
+
+#define RB150_NAND_WRITE(v) \
+ writeb((v), (void __iomem *)KSEG1ADDR(RB150_NAND_BASE))
+
+static struct resource rb150_nand_resources[] __initdata = {
+ [0] = {
+ .start = RB150_NAND_BASE,
+ .end = RB150_NAND_BASE + RB150_NAND_SIZE-1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct gpio_led rb150_gpio_leds[] __initdata = {
+ GPIO_LED_STD(ADM5120_GPIO_P0L2, "user", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P0L1, "lan1_led1", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P0L0, "lan1_led2", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P1L1, "lan5_led1", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan5_led2", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P2L1, "lan4_led1", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan4_led2", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P3L1, "lan3_led1", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P3L0, "lan3_led2", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P4L1, "lan2_led1", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P4L0, "lan2_led2", NULL),
+};
+
+static u8 rb150_vlans[6] __initdata = {
+ 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+static int rb150_nand_dev_ready(struct mtd_info *mtd)
+{
+ return gpio_get_value(RB150_GPIO_NAND_READY);
+}
+
+static void rb150_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
+ unsigned int ctrl)
+{
+ if (ctrl & NAND_CTRL_CHANGE) {
+ gpio_set_value(RB150_GPIO_NAND_CLE, (ctrl & NAND_CLE) ? 1 : 0);
+ gpio_set_value(RB150_GPIO_NAND_ALE, (ctrl & NAND_ALE) ? 1 : 0);
+ gpio_set_value(RB150_GPIO_NAND_NCE, (ctrl & NAND_NCE) ? 0 : 1);
+ }
+
+ udelay(RB150_NAND_DELAY);
+
+ if (cmd != NAND_CMD_NONE)
+ RB150_NAND_WRITE(cmd);
+}
+
+static void __init rb150_add_device_nand(void)
+{
+ struct platform_device *pdev;
+ int err;
+
+ /* setup GPIO pins for NAND flash chip */
+ gpio_request(RB150_GPIO_NAND_READY, "nand-ready");
+ gpio_direction_input(RB150_GPIO_NAND_READY);
+ gpio_request(RB150_GPIO_NAND_NCE, "nand-nce");
+ gpio_direction_output(RB150_GPIO_NAND_NCE, 1);
+ gpio_request(RB150_GPIO_NAND_CLE, "nand-cle");
+ gpio_direction_output(RB150_GPIO_NAND_CLE, 0);
+ gpio_request(RB150_GPIO_NAND_ALE, "nand-ale");
+ gpio_direction_output(RB150_GPIO_NAND_ALE, 0);
+
+ pdev = platform_device_alloc("gen_nand", -1);
+ if (!pdev)
+ goto err_out;
+
+ err = platform_device_add_resources(pdev, rb150_nand_resources,
+ ARRAY_SIZE(rb150_nand_resources));
+ if (err)
+ goto err_put;
+
+
+ rb1xx_nand_data.ctrl.cmd_ctrl = rb150_nand_cmd_ctrl;
+ rb1xx_nand_data.ctrl.dev_ready = rb150_nand_dev_ready;
+
+ err = platform_device_add_data(pdev, &rb1xx_nand_data,
+ sizeof(rb1xx_nand_data));
+ if (err)
+ goto err_put;
+
+ err = platform_device_add(pdev);
+ if (err)
+ goto err_put;
+
+ return;
+
+err_put:
+ platform_device_put(pdev);
+err_out:
+ return;
+}
+
+static void __init rb150_setup(void)
+{
+ rb1xx_gpio_buttons[0].gpio = RB150_GPIO_RESET_BUTTON;
+ rb1xx_generic_setup();
+ rb150_add_device_nand();
+
+ adm5120_add_device_gpio(RB150_GPIO_DEV_MASK);
+ adm5120_add_device_gpio_leds(ARRAY_SIZE(rb150_gpio_leds),
+ rb150_gpio_leds);
+ adm5120_add_device_switch(5, rb150_vlans);
+}
+
+ADM5120_BOARD(MACH_ADM5120_RB_150, "Mikrotik RouterBOARD 150", rb150_setup);
--- /dev/null
+/*
+ * Mikrotik RouterBOARD 153 support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "rb-1xx.h"
+
+#define RB153_GPIO_DEV_MASK ( 1 << ADM5120_GPIO_PIN0 \
+ | 1 << ADM5120_GPIO_PIN3 \
+ | 1 << ADM5120_GPIO_PIN4 )
+
+static struct resource rb153_cf_resources[] __initdata = {
+ {
+ .name = "cf_membase",
+ .start = ADM5120_EXTIO1_BASE,
+ .end = ADM5120_EXTIO1_BASE + ADM5120_EXTIO1_SIZE-1 ,
+ .flags = IORESOURCE_MEM
+ }, {
+ .name = "cf_irq",
+ .start = ADM5120_IRQ_GPIO4,
+ .end = ADM5120_IRQ_GPIO4,
+ .flags = IORESOURCE_IRQ
+ }
+};
+
+static struct gpio_led rb153_gpio_leds[] __initdata = {
+ GPIO_LED_STD(ADM5120_GPIO_PIN5, "user", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P0L1, "lan1_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P0L0, "lan1_lnkact", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P1L1, "lan5_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan5_lnkact", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P2L1, "lan4_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan4_lnkact", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P3L1, "lan3_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P3L0, "lan3_lnkact", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P4L1, "lan2_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P4L0, "lan2_lnkact", NULL),
+};
+
+static u8 rb153_vlans[6] __initdata = {
+ 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+static void __init rb153_add_device_cf(void)
+{
+ /* enable CSX1:INTX1 on GPIO[3:4] for the CF slot */
+ adm5120_gpio_csx1_enable();
+
+ /* enable the wait state pin GPIO[0] for external I/O control */
+ adm5120_gpio_ew_enable();
+
+ platform_device_register_simple("pata-rb153-cf", -1,
+ rb153_cf_resources, ARRAY_SIZE(rb153_cf_resources));
+}
+
+static void __init rb153_setup(void)
+{
+ rb1xx_generic_setup();
+ rb1xx_add_device_nand();
+ rb153_add_device_cf();
+
+ adm5120_add_device_gpio(RB153_GPIO_DEV_MASK);
+ adm5120_add_device_gpio_leds(ARRAY_SIZE(rb153_gpio_leds),
+ rb153_gpio_leds);
+ adm5120_add_device_switch(5, rb153_vlans);
+}
+
+ADM5120_BOARD(MACH_ADM5120_RB_153, "Mikrotik RouterBOARD 153", rb153_setup);
--- /dev/null
+/*
+ * Mikrotik RouterBOARD 192 support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "rb-1xx.h"
+
+static u8 rb192_vlans[6] __initdata = {
+ 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+static void __init rb192_setup(void)
+{
+ rb1xx_generic_setup();
+ rb1xx_add_device_nand();
+
+ adm5120_add_device_gpio(0);
+ adm5120_add_device_switch(6, rb192_vlans);
+}
+
+ADM5120_BOARD(MACH_ADM5120_RB_192, "Mikrotik RouterBOARD 192", rb192_setup);
--- /dev/null
+/*
+ * Mikrotik RouterBOARD 1xx series support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * NAND initialization code was based on a driver for Linux 2.6.19+ which
+ * was derived from the driver for Linux 2.4.xx published by Mikrotik for
+ * their RouterBoard 1xx and 5xx series boards.
+ * Copyright (C) 2007 David Goodenough <david.goodenough@linkchoose.co.uk>
+ * Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "rb-1xx.h"
+
+#define RB1XX_NAND_CHIP_DELAY 25
+
+static struct adm5120_pci_irq rb1xx_pci_irqs[] __initdata = {
+ PCIIRQ(1, 0, 1, ADM5120_IRQ_PCI0),
+ PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI1),
+ PCIIRQ(3, 0, 1, ADM5120_IRQ_PCI2)
+};
+
+#ifdef CONFIG_MTD_PARTITIONS
+static struct mtd_partition rb1xx_nor_parts[] = {
+ {
+ .name = "booter",
+ .offset = 0,
+ .size = 64*1024,
+ .mask_flags = MTD_WRITEABLE,
+ } , {
+ .name = "firmware",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+
+static struct mtd_partition rb1xx_nand_parts[] = {
+ {
+ .name = "kernel",
+ .offset = 0,
+ .size = 4 * 1024 * 1024,
+ } , {
+ .name = "rootfs",
+ .offset = MTDPART_OFS_NXTBLK,
+ .size = MTDPART_SIZ_FULL
+ }
+};
+#endif /* CONFIG_MTD_PARTITIONS */
+
+/*
+ * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader
+ * will not be able to find the kernel that we load. So set the oobinfo
+ * when creating the partitions
+ */
+static struct nand_ecclayout rb1xx_nand_ecclayout = {
+ .eccbytes = 6,
+ .eccpos = { 8, 9, 10, 13, 14, 15 },
+ .oobavail = 9,
+ .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
+};
+
+/*--------------------------------------------------------------------------*/
+
+static int rb1xx_nand_fixup(struct mtd_info *mtd)
+{
+ struct nand_chip *chip = mtd->priv;
+
+ if (mtd->writesize == 512)
+ chip->ecc.layout = &rb1xx_nand_ecclayout;
+
+ return 0;
+}
+
+struct platform_nand_data rb1xx_nand_data __initdata = {
+ .chip = {
+ .nr_chips = 1,
+#ifdef CONFIG_MTD_PARTITIONS
+ .nr_partitions = ARRAY_SIZE(rb1xx_nand_parts),
+ .partitions = rb1xx_nand_parts,
+#endif /* CONFIG_MTD_PARTITIONS */
+ .chip_delay = RB1XX_NAND_CHIP_DELAY,
+ .options = NAND_NO_AUTOINCR,
+ .chip_fixup = rb1xx_nand_fixup,
+ },
+};
+
+struct gpio_button rb1xx_gpio_buttons[] __initdata = {
+ {
+ .desc = "reset_button",
+ .type = EV_KEY,
+ .code = BTN_0,
+ .threshold = 5,
+ .gpio = ADM5120_GPIO_PIN7,
+ }
+};
+
+static void __init rb1xx_mac_setup(void)
+{
+ if (rb_hs.mac_base != NULL && is_valid_ether_addr(rb_hs.mac_base)) {
+ adm5120_setup_eth_macs(rb_hs.mac_base);
+ } else {
+ u8 mac[ETH_ALEN];
+
+ random_ether_addr(mac);
+ adm5120_setup_eth_macs(mac);
+ }
+}
+
+void __init rb1xx_add_device_flash(void)
+{
+ /* setup data for flash0 device */
+#ifdef CONFIG_MTD_PARTITIONS
+ adm5120_flash0_data.nr_parts = ARRAY_SIZE(rb1xx_nor_parts);
+ adm5120_flash0_data.parts = rb1xx_nor_parts;
+#endif /* CONFIG_MTD_PARTITIONS */
+ adm5120_flash0_data.window_size = 128*1024;
+
+ adm5120_add_device_flash(0);
+}
+
+void __init rb1xx_add_device_nand(void)
+{
+ /* enable NAND flash interface */
+ adm5120_nand_enable();
+
+ /* initialize NAND chip */
+ adm5120_nand_set_spn(1);
+ adm5120_nand_set_wpn(0);
+
+ adm5120_add_device_nand(&rb1xx_nand_data);
+}
+
+void __init rb1xx_generic_setup(void)
+{
+ if (adm5120_package_bga())
+ adm5120_pci_set_irq_map(ARRAY_SIZE(rb1xx_pci_irqs),
+ rb1xx_pci_irqs);
+
+ adm5120_add_device_uart(0);
+ adm5120_add_device_uart(1);
+
+ adm5120_add_device_gpio_buttons(ARRAY_SIZE(rb1xx_gpio_buttons),
+ rb1xx_gpio_buttons);
+
+ rb1xx_add_device_flash();
+ rb1xx_mac_setup();
+}
--- /dev/null
+/*
+ * Mikrotik RouterBOARD 1xx series support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <linux/etherdevice.h>
+
+#include <asm/bootinfo.h>
+
+#include <asm/mach-adm5120/adm5120_defs.h>
+#include <asm/mach-adm5120/adm5120_nand.h>
+#include <asm/mach-adm5120/adm5120_board.h>
+#include <asm/mach-adm5120/adm5120_platform.h>
+#include <asm/mach-adm5120/adm5120_info.h>
+
+#include <prom/routerboot.h>
+
+extern struct platform_nand_data rb1xx_nand_data __initdata;
+extern struct gpio_button rb1xx_gpio_buttons[] __initdata;
+
+extern void rb1xx_add_device_flash(void) __init;
+extern void rb1xx_add_device_nand(void) __init;
+extern void rb1xx_generic_setup(void) __init;
--- /dev/null
+obj-$(CONFIG_ADM5120_MACH_PMUGW) += pmugw.o
--- /dev/null
+/*
+ * Motorola Powerline MU Gateway board
+ *
+ * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <linux/etherdevice.h>
+
+#include <asm/bootinfo.h>
+
+#include <asm/mach-adm5120/adm5120_defs.h>
+#include <asm/mach-adm5120/adm5120_board.h>
+#include <asm/mach-adm5120/adm5120_platform.h>
+#include <asm/mach-adm5120/adm5120_info.h>
+
+#include <prom/admboot.h>
+
+#define PMUGW_CONFIG_OFFSET 0x10000
+#define PMUGW_CONFIG_SIZE 0x1000
+
+#ifdef CONFIG_MTD_PARTITIONS
+static struct mtd_partition pmugw_partitions[] = {
+ {
+ .name = "admboot",
+ .offset = 0,
+ .size = 64*1024,
+ .mask_flags = MTD_WRITEABLE,
+ } , {
+ .name = "boardcfg",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 64*1024,
+ } , {
+ .name = "firmware",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+#endif /* CONFIG_MTD_PARTITIONS */
+
+static u8 pmugw_vlans[6] __initdata = {
+ 0x41, 0x42, 0x44, 0x48, 0x50, 0x00
+};
+
+static __init void pmugw_setup_mac(void)
+{
+ u8 mac_base[6];
+ int err;
+
+ err = admboot_get_mac_base(PMUGW_CONFIG_OFFSET,
+ PMUGW_CONFIG_SIZE, mac_base);
+
+ if ((err) || !is_valid_ether_addr(mac_base))
+ random_ether_addr(mac_base);
+
+ adm5120_setup_eth_macs(mac_base);
+}
+
+static void switch_bank_gpio5(unsigned bank)
+{
+ switch (bank) {
+ case 0:
+ gpio_set_value(ADM5120_GPIO_PIN5, 0);
+ break;
+ case 1:
+ gpio_set_value(ADM5120_GPIO_PIN5, 1);
+ break;
+ }
+}
+
+void __init pmugw_setup(void)
+{
+ /* setup flash A20 line */
+ gpio_request(ADM5120_GPIO_PIN5, NULL);
+ gpio_direction_output(ADM5120_GPIO_PIN5, 0);
+ adm5120_flash0_data.switch_bank = switch_bank_gpio5;
+
+#ifdef CONFIG_MTD_PARTITIONS
+ adm5120_flash0_data.nr_parts = ARRAY_SIZE(pmugw_partitions);
+ adm5120_flash0_data.parts = pmugw_partitions;
+#endif /* CONFIG_MTD_PARTITIONS */
+
+ adm5120_add_device_uart(1); /* ttyS0 */
+ adm5120_add_device_uart(0); /* ttyS1 */
+
+ adm5120_add_device_flash(0);
+
+ pmugw_setup_mac();
+ adm5120_add_device_switch(5, pmugw_vlans);
+}
+
+ADM5120_BOARD(MACH_ADM5120_PMUGW,
+ "Motorola Powerline MU Gateway",
+ pmugw_setup);
--- /dev/null
+#
+# Makefile for the ADMtek ADM5120 SoC specific parts of the kernel
+#
+
+lib-y += admboot.o
+lib-y += bootbase.o
+lib-y += cfe.o
+lib-y += generic.o
+lib-y += myloader.o
+lib-y += routerboot.o
--- /dev/null
+/*
+ * ADMBoot specific prom routines
+ *
+ * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+
+#include <asm/addrspace.h>
+#include <asm/byteorder.h>
+
+#include <asm/mach-adm5120/adm5120_defs.h>
+#include <prom/admboot.h>
+#include "prom_read.h"
+
+#define ADMBOOT_MAGIC_MAC_BASE 0x636D676D /* 'mgmc' */
+
+int __init admboot_get_mac_base(u32 offset, u32 len, u8 *mac)
+{
+ u8 *cfg;
+ int i;
+
+ cfg = (u8 *) KSEG1ADDR(ADM5120_SRAM0_BASE + offset);
+ for (i = 0; i < len; i += 4) {
+ u32 magic;
+
+ magic = prom_read_le32(cfg + i);
+ if (magic == ADMBOOT_MAGIC_MAC_BASE) {
+ int j;
+
+ for (j = 0; j < 6; j++)
+ mac[j] = cfg[i + 4 + j];
+
+ return 0;
+ }
+ }
+
+ return -ENXIO;
+}
--- /dev/null
+/*
+ * ZyXEL's Bootbase specific prom routines
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/types.h>
+#include <linux/autoconf.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/string.h>
+
+#include <asm/bootinfo.h>
+#include <asm/addrspace.h>
+#include <asm/byteorder.h>
+
+#include <asm/mach-adm5120/adm5120_defs.h>
+#include <prom/zynos.h>
+#include "prom_read.h"
+
+#define ZYNOS_INFO_ADDR KSEG1ADDR(ADM5120_SRAM0_BASE+0x3F90)
+#define ZYNOS_HDBG_ADDR KSEG1ADDR(ADM5120_SRAM0_BASE+0x4000)
+#define BOOTEXT_ADDR_MIN KSEG1ADDR(ADM5120_SRAM0_BASE)
+#define BOOTEXT_ADDR_MAX (BOOTEXT_ADDR_MIN + (2*1024*1024))
+
+static int bootbase_found;
+static struct zynos_board_info *board_info;
+
+struct bootbase_info bootbase_info;
+
+static inline int bootbase_dbgarea_present(u8 *data)
+{
+ u32 t;
+
+ t = prom_read_be32(data+5);
+ if (t != ZYNOS_MAGIC_DBGAREA1)
+ return 0;
+
+ t = prom_read_be32(data+9);
+ if (t != ZYNOS_MAGIC_DBGAREA2)
+ return 0;
+
+ return 1;
+}
+
+static inline u32 bootbase_get_bootext_addr(void)
+{
+ return prom_read_be32(&board_info->bootext_addr);
+}
+
+static inline void bootbase_get_mac(u8 *mac)
+{
+ int i;
+
+ for (i = 0; i < 6; i++)
+ mac[i] = board_info->mac[i];
+}
+
+static inline u16 bootbase_get_vendor_id(void)
+{
+#define CHECK_VENDOR(n) (strnicmp(board_info->vendor, (n), strlen(n)) == 0)
+ unsigned char vendor[ZYNOS_NAME_LEN];
+ int i;
+
+ for (i = 0; i < ZYNOS_NAME_LEN; i++)
+ vendor[i] = board_info->vendor[i];
+
+ if CHECK_VENDOR(ZYNOS_VENDOR_ZYXEL)
+ return ZYNOS_VENDOR_ID_ZYXEL;
+
+ if CHECK_VENDOR(ZYNOS_VENDOR_DLINK)
+ return ZYNOS_VENDOR_ID_DLINK;
+
+ if CHECK_VENDOR(ZYNOS_VENDOR_LUCENT)
+ return ZYNOS_VENDOR_ID_LUCENT;
+
+ if CHECK_VENDOR(ZYNOS_VENDOR_NETGEAR)
+ return ZYNOS_VENDOR_ID_NETGEAR;
+
+ return ZYNOS_VENDOR_ID_OTHER;
+}
+
+static inline u16 bootbase_get_board_id(void)
+{
+ return prom_read_be16(&board_info->board_id);
+}
+
+int __init bootbase_present(void)
+{
+ u32 t;
+
+ if (bootbase_found)
+ goto out;
+
+ /* check presence of the dbgarea */
+ if (bootbase_dbgarea_present((u8 *)ZYNOS_HDBG_ADDR) == 0)
+ goto out;
+
+ board_info = (struct zynos_board_info *)(ZYNOS_INFO_ADDR);
+
+ /* check for a valid BootExt address */
+ t = bootbase_get_bootext_addr();
+ if ((t < BOOTEXT_ADDR_MIN) || (t > BOOTEXT_ADDR_MAX))
+ goto out;
+
+ bootbase_info.vendor_id = bootbase_get_vendor_id();
+ bootbase_info.board_id = bootbase_get_board_id();
+ bootbase_get_mac(bootbase_info.mac);
+
+ bootbase_found = 1;
+
+out:
+ return bootbase_found;
+}
+
--- /dev/null
+/*
+ * Broadcom's CFE specific prom routines
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+
+#include <asm/bootinfo.h>
+#include <asm/addrspace.h>
+
+#include <prom/cfe.h>
+#include "prom_read.h"
+
+/*
+ * CFE based boards
+ */
+#define CFE_EPTSEAL 0x43464531 /* CFE1 is the magic number to recognize CFE
+from other bootloaders */
+
+static int cfe_found;
+
+static u32 cfe_handle;
+static u32 cfe_entry;
+static u32 cfe_seal;
+
+int __init cfe_present(void)
+{
+ /*
+ * This method only works, when we are booted directly from the CFE.
+ */
+ u32 a1 = (u32) fw_arg1;
+
+ if (cfe_found)
+ return 1;
+
+ cfe_handle = (u32) fw_arg0;
+ cfe_entry = (u32) fw_arg2;
+ cfe_seal = (u32) fw_arg3;
+
+ /* Check for CFE by finding the CFE magic number */
+ if (cfe_seal != CFE_EPTSEAL)
+ return 0;
+
+ /* cfe_a1_val must be 0, because only one CPU present in the ADM5120 */
+ if (a1 != 0)
+ return 0;
+
+ /* The cfe_handle, and the cfe_entry must be kernel mode addresses */
+ if ((cfe_handle < KSEG0) || (cfe_entry < KSEG0))
+ return 0;
+
+ cfe_found = 1;
+ return 1;
+}
+
+char *cfe_getenv(char *envname)
+{
+ if (cfe_found == 0)
+ return NULL;
+
+ return NULL;
+}
--- /dev/null
+/*
+ * Generic PROM routines
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/string.h>
+
+#include <asm/bootinfo.h>
+
+#include <prom/generic.h>
+
+static int *_prom_argc;
+static char **_prom_argv;
+static char **_prom_envp;
+
+char *generic_prom_getenv(char *envname)
+{
+ char **env;
+ char *ret;
+
+ ret = NULL;
+ for (env = _prom_envp; *env != NULL; env++) {
+ if (strcmp(envname, *env++) == 0) {
+ ret = *env;
+ break;
+ }
+ }
+
+ return ret;
+}
+
+int generic_prom_present(void)
+{
+ _prom_argc = (int *)fw_arg0;
+ _prom_argv = (char **)fw_arg1;
+ _prom_envp = (char **)fw_arg2;
+
+ return 1;
+}
--- /dev/null
+/*
+ * Compex's MyLoader specific prom routines
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/types.h>
+#include <linux/autoconf.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/string.h>
+
+#include <asm/bootinfo.h>
+#include <asm/addrspace.h>
+#include <asm/byteorder.h>
+
+#include <asm/mach-adm5120/adm5120_defs.h>
+#include <prom/myloader.h>
+#include "prom_read.h"
+
+#define SYS_PARAMS_ADDR KSEG1ADDR(ADM5120_SRAM0_BASE+0x0F000)
+#define BOARD_PARAMS_ADDR KSEG1ADDR(ADM5120_SRAM0_BASE+0x0F800)
+#define PART_TABLE_ADDR KSEG1ADDR(ADM5120_SRAM0_BASE+0x10000)
+
+static int myloader_found;
+
+struct myloader_info myloader_info;
+
+int __init myloader_present(void)
+{
+ struct mylo_system_params *sysp;
+ struct mylo_board_params *boardp;
+ struct mylo_partition_table *parts;
+ int i;
+
+ if (myloader_found)
+ goto out;
+
+ sysp = (struct mylo_system_params *)(SYS_PARAMS_ADDR);
+ boardp = (struct mylo_board_params *)(BOARD_PARAMS_ADDR);
+ parts = (struct mylo_partition_table *)(PART_TABLE_ADDR);
+
+ /* Check for some magic numbers */
+ if ((le32_to_cpu(sysp->magic) != MYLO_MAGIC_SYS_PARAMS) ||
+ (le32_to_cpu(boardp->magic) != MYLO_MAGIC_BOARD_PARAMS) ||
+ (le32_to_cpu(parts->magic) != MYLO_MAGIC_PARTITIONS))
+ goto out;
+
+ myloader_info.vid = le32_to_cpu(sysp->vid);
+ myloader_info.did = le32_to_cpu(sysp->did);
+ myloader_info.svid = le32_to_cpu(sysp->svid);
+ myloader_info.sdid = le32_to_cpu(sysp->sdid);
+
+ for (i = 0; i < MYLO_ETHADDR_COUNT; i++) {
+ int j;
+ for (j = 0; j < 6; j++)
+ myloader_info.macs[i][j] = boardp->addr[i].mac[j];
+ }
+
+ myloader_found = 1;
+
+out:
+ return myloader_found;
+}
--- /dev/null
+/*
+ * Generic prom definitions
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#ifndef _ADM5120_PROM_H_
+#define _ADM5120_PROM_H_
+
+/*
+ * Helper routines
+ */
+static inline u16 prom_read_le16(void *buf)
+{
+ u8 *p = buf;
+
+ return ((u16)p[0] + ((u16)p[1] << 8));
+}
+
+static inline u32 prom_read_le32(void *buf)
+{
+ u8 *p = buf;
+
+ return ((u32)p[0] + ((u32)p[1] << 8) + ((u32)p[2] << 16) +
+ ((u32)p[3] << 24));
+}
+
+static inline u16 prom_read_be16(void *buf)
+{
+ u8 *p = buf;
+
+ return (((u16)p[0] << 8) + (u16)p[1]);
+}
+
+static inline u32 prom_read_be32(void *buf)
+{
+ u8 *p = buf;
+
+ return (((u32)p[0] << 24) + ((u32)p[1] << 16) + ((u32)p[2] << 8) +
+ ((u32)p[3]));
+}
+
+#endif /* _ADM5120_PROM_H_ */
+
+
--- /dev/null
+/*
+ * Mikrotik's RouterBOOT specific prom routines
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/types.h>
+#include <linux/autoconf.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/string.h>
+#include <linux/module.h>
+
+#include <asm/bootinfo.h>
+#include <asm/addrspace.h>
+
+#include <asm/mach-adm5120/adm5120_defs.h>
+#include <prom/routerboot.h>
+#include "prom_read.h"
+
+struct rb_hard_settings rb_hs;
+static int rb_found;
+
+static int __init routerboot_load_hs(u8 *buf, u16 buflen)
+{
+ u16 id, len;
+
+ memset(&rb_hs, 0, sizeof(rb_hs));
+
+ if (buflen < 4)
+ return -1;
+
+ if (prom_read_le32(buf) != RB_MAGIC_HARD)
+ return -1;
+
+ /* skip magic value */
+ buf += 4;
+ buflen -= 4;
+
+ while (buflen > 2) {
+ id = prom_read_le16(buf);
+ buf += 2;
+ buflen -= 2;
+ if (id == RB_ID_TERMINATOR || buflen < 2)
+ break;
+
+ len = prom_read_le16(buf);
+ buf += 2;
+ buflen -= 2;
+
+ if (buflen < len)
+ break;
+
+ switch (id) {
+ case RB_ID_BIOS_VERSION:
+ rb_hs.bios_ver = (char *)buf;
+ break;
+ case RB_ID_BOARD_NAME:
+ rb_hs.name = (char *)buf;
+ break;
+ case RB_ID_MEMORY_SIZE:
+ rb_hs.mem_size = prom_read_le32(buf);
+ break;
+ case RB_ID_MAC_ADDRESS_COUNT:
+ rb_hs.mac_count = prom_read_le32(buf);
+ break;
+ case RB_ID_MAC_ADDRESS_PACK:
+ if ((len / RB_MAC_SIZE) > 0)
+ rb_hs.mac_base = buf;
+ break;
+ }
+
+ buf += len;
+ buflen -= len;
+
+ }
+
+ return 0;
+}
+
+#define RB_BS_OFFS 0x14
+#define RB_OFFS_MAX (128*1024)
+
+int __init routerboot_present(void)
+{
+ struct rb_bios_settings *bs;
+ u8 *base;
+ u32 off, len;
+
+ if (rb_found)
+ goto out;
+
+ base = (u8 *)KSEG1ADDR(ADM5120_SRAM0_BASE);
+ bs = (struct rb_bios_settings *)(base + RB_BS_OFFS);
+
+ off = prom_read_le32(&bs->hs_offs);
+ len = prom_read_le32(&bs->hs_size);
+ if (off > RB_OFFS_MAX)
+ goto out;
+
+ if (routerboot_load_hs(base+off, len) != 0)
+ goto out;
+
+ rb_found = 1;
+
+out:
+ return rb_found;
+}
+
+char *routerboot_get_boardname(void)
+{
+ if (rb_found == 0)
+ return NULL;
+
+ return rb_hs.name;
+}
--- /dev/null
+obj-y += p-33x.o
+
+obj-${CONFIG_ADM5120_MACH_P_334WT} += p-334wt.o
+obj-${CONFIG_ADM5120_MACH_P_335} += p-335.o
\ No newline at end of file
--- /dev/null
+/*
+ * ZyXEL Prestige P-334WT support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "p-33x.h"
+
+static struct gpio_led p334wt_gpio_leds[] __initdata = {
+ GPIO_LED_INV(ADM5120_GPIO_PIN2, "power", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P3L0, "lan1", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan2", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan3", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P0L0, "lan4", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P4L0, "wan", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P4L2, "wlan", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P2L2, "otist", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P1L2, "hidden", NULL),
+};
+
+static void __init p334wt_setup(void)
+{
+ p33x_generic_setup();
+ adm5120_add_device_gpio_leds(ARRAY_SIZE(p334wt_gpio_leds),
+ p334wt_gpio_leds);
+}
+
+ADM5120_BOARD(MACH_ADM5120_P334WT, "ZyXEL Prestige 334WT", p334wt_setup);
--- /dev/null
+/*
+ * ZyXEL Prestige P-335/335WT support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "p-33x.h"
+
+static void __init p335_setup(void)
+{
+ p33x_generic_setup();
+ adm5120_add_device_usb();
+}
+
+ADM5120_BOARD(MACH_ADM5120_P335, "ZyXEL Prestige 335/335WT", p335_setup);
--- /dev/null
+/*
+ * ZyXEL Prestige P-33x boards support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "p-33x.h"
+
+#include <prom/zynos.h>
+
+#define P33X_GPIO_FLASH_A20 ADM5120_GPIO_PIN5
+#define P33X_GPIO_DEV_MASK (1 << P33X_GPIO_FLASH_A20)
+
+#ifdef CONFIG_MTD_PARTITIONS
+static struct mtd_partition p33x_partitions[] = {
+ {
+ .name = "bootbase",
+ .offset = 0,
+ .size = 16*1024,
+ .mask_flags = MTD_WRITEABLE,
+ } , {
+ .name = "rom",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 16*1024,
+ } , {
+ .name = "bootext",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 96*1024,
+ .mask_flags = MTD_WRITEABLE,
+ } , {
+ .name = "trx",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ } , {
+ .name = "firmware",
+ .offset = 32*1024,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+#endif /* CONFIG_MTD_PARTITIONS */
+
+static struct adm5120_pci_irq p33x_pci_irqs[] __initdata = {
+ PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI0),
+};
+
+static u8 p33x_vlans[6] __initdata = {
+ /* FIXME: untested */
+ 0x50, 0x48, 0x44, 0x42, 0x41, 0x00
+};
+
+static void switch_bank_gpio5(unsigned bank)
+{
+ switch (bank) {
+ case 0:
+ gpio_set_value(P33X_GPIO_FLASH_A20, 0);
+ break;
+ case 1:
+ gpio_set_value(P33X_GPIO_FLASH_A20, 1);
+ break;
+ }
+}
+
+void __init p33x_generic_setup(void)
+{
+ /* setup data for flash0 device */
+ gpio_request(P33X_GPIO_FLASH_A20, NULL); /* for flash A20 line */
+ gpio_direction_output(P33X_GPIO_FLASH_A20, 0);
+ adm5120_flash0_data.switch_bank = switch_bank_gpio5;
+#ifdef CONFIG_MTD_PARTITIONS
+ adm5120_flash0_data.nr_parts = ARRAY_SIZE(p33x_partitions);
+ adm5120_flash0_data.parts = p33x_partitions;
+#endif /* CONFIG_MTD_PARTITIONS */
+ adm5120_add_device_flash(0);
+
+ adm5120_add_device_uart(0);
+ adm5120_add_device_uart(1);
+
+ adm5120_add_device_gpio(P33X_GPIO_DEV_MASK);
+
+ adm5120_setup_eth_macs(bootbase_info.mac);
+ adm5120_add_device_switch(5, p33x_vlans);
+
+ adm5120_pci_set_irq_map(ARRAY_SIZE(p33x_pci_irqs), p33x_pci_irqs);
+}
--- /dev/null
+/*
+ * ZyXEL Prestige P-33x boards support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+
+#include <asm/bootinfo.h>
+
+#include <asm/mach-adm5120/adm5120_board.h>
+#include <asm/mach-adm5120/adm5120_platform.h>
+
+extern void p33x_generic_setup(void) __init;
--- /dev/null
+/*
+ * ADM5120 PCI Host Controller driver
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This code was based on the ADM5120 specific port of the Linux 2.6.10 kernel
+ * done by Jeroen Vreeken
+ * Copyright (C) 2005 Jeroen Vreeken (pe1rxq@amsat.org)
+ *
+ * Jeroen's code was based on the Linux 2.4.xx source codes found in various
+ * tarballs released by Edimax for it's ADM5120 based devices
+ * Copyright (C) ADMtek Incorporated
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+
+#include <linux/pci.h>
+#include <linux/pci_ids.h>
+#include <linux/pci_regs.h>
+
+#include <asm/delay.h>
+#include <asm/bootinfo.h>
+
+#include <asm/mach-adm5120/adm5120_defs.h>
+#include <asm/mach-adm5120/adm5120_info.h>
+#include <asm/mach-adm5120/adm5120_defs.h>
+#include <asm/mach-adm5120/adm5120_platform.h>
+
+#undef DEBUG
+
+#ifdef DEBUG
+#define DBG(f, a...) printk(KERN_DEBUG f, ## a)
+#else
+#define DBG(f, a...) do {} while (0)
+#endif
+
+#define PCI_ENABLE 0x80000000
+
+/* -------------------------------------------------------------------------*/
+
+static unsigned int adm5120_pci_nr_irqs __initdata;
+static struct adm5120_pci_irq *adm5120_pci_irq_map __initdata;
+
+static spinlock_t pci_lock = SPIN_LOCK_UNLOCKED;
+
+/* -------------------------------------------------------------------------*/
+
+static inline void write_cfgaddr(u32 addr)
+{
+ __raw_writel((addr | PCI_ENABLE),
+ (void __iomem *)(KSEG1ADDR(ADM5120_PCICFG_ADDR)));
+}
+
+static inline void write_cfgdata(u32 data)
+{
+ __raw_writel(data, (void __iomem *)KSEG1ADDR(ADM5120_PCICFG_DATA));
+}
+
+static inline u32 read_cfgdata(void)
+{
+ return __raw_readl((void __iomem *)KSEG1ADDR(ADM5120_PCICFG_DATA));
+}
+
+static inline u32 mkaddr(struct pci_bus *bus, unsigned int devfn, int where)
+{
+ return (((bus->number & 0xFF) << 16) | ((devfn & 0xFF) << 8) | \
+ (where & 0xFC));
+}
+
+/* -------------------------------------------------------------------------*/
+
+static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
+ int size, u32 *val)
+{
+ unsigned long flags;
+ u32 data;
+
+ spin_lock_irqsave(&pci_lock, flags);
+
+ write_cfgaddr(mkaddr(bus, devfn, where));
+ data = read_cfgdata();
+
+ DBG("PCI: cfg_read %02u.%02u.%01u/%02X:%01d, cfg:0x%08X",
+ bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
+ where, size, data);
+
+ switch (size) {
+ case 1:
+ if (where & 1)
+ data >>= 8;
+ if (where & 2)
+ data >>= 16;
+ data &= 0xFF;
+ break;
+ case 2:
+ if (where & 2)
+ data >>= 16;
+ data &= 0xFFFF;
+ break;
+ }
+
+ *val = data;
+ DBG(", 0x%08X returned\n", data);
+
+ spin_unlock_irqrestore(&pci_lock, flags);
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,
+ int size, u32 val)
+{
+ unsigned long flags;
+ u32 data;
+ int s;
+
+ spin_lock_irqsave(&pci_lock, flags);
+
+ write_cfgaddr(mkaddr(bus, devfn, where));
+ data = read_cfgdata();
+
+ DBG("PCI: cfg_write %02u.%02u.%01u/%02X:%01d, cfg:0x%08X",
+ bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
+ where, size, data);
+
+ switch (size) {
+ case 1:
+ s = ((where & 3) << 3);
+ data &= ~(0xFF << s);
+ data |= ((val & 0xFF) << s);
+ break;
+ case 2:
+ s = ((where & 2) << 4);
+ data &= ~(0xFFFF << s);
+ data |= ((val & 0xFFFF) << s);
+ break;
+ case 4:
+ data = val;
+ break;
+ }
+
+ write_cfgdata(data);
+ DBG(", 0x%08X written\n", data);
+
+ spin_unlock_irqrestore(&pci_lock, flags);
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+struct pci_ops adm5120_pci_ops = {
+ .read = pci_config_read,
+ .write = pci_config_write,
+};
+
+/* -------------------------------------------------------------------------*/
+
+static void adm5120_pci_fixup(struct pci_dev *dev)
+{
+ if (dev->devfn != 0)
+ return;
+
+ /* setup COMMAND register */
+ pci_write_config_word(dev, PCI_COMMAND,
+ (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
+
+ /* setup CACHE_LINE_SIZE register */
+ pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 4);
+
+ /* setup BARS */
+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0);
+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0);
+}
+
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADMTEK, PCI_DEVICE_ID_ADMTEK_ADM5120,
+ adm5120_pci_fixup);
+
+/* -------------------------------------------------------------------------*/
+
+void __init adm5120_pci_set_irq_map(unsigned int nr_irqs,
+ struct adm5120_pci_irq *map)
+{
+ adm5120_pci_nr_irqs = nr_irqs;
+ adm5120_pci_irq_map = map;
+}
+
+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+ int irq = -1;
+ int i;
+
+ if ((!adm5120_pci_nr_irqs) || (!adm5120_pci_irq_map)) {
+ printk(KERN_ALERT "PCI: pci_irq_map is not initialized\n");
+ goto out;
+ }
+
+ if (slot < 1 || slot > 3) {
+ printk(KERN_ALERT "PCI: slot number %u is not supported\n",
+ slot);
+ goto out;
+ }
+
+ for (i = 0; i < adm5120_pci_nr_irqs; i++) {
+ if ((adm5120_pci_irq_map[i].slot == slot)
+ && (adm5120_pci_irq_map[i].func == PCI_FUNC(dev->devfn))
+ && (adm5120_pci_irq_map[i].pin == pin)) {
+ irq = adm5120_pci_irq_map[i].irq;
+ break;
+ }
+ }
+
+ if (irq < 0) {
+ printk(KERN_ALERT "PCI: no irq found for %s pin:%u\n",
+ pci_name((struct pci_dev *)dev), pin);
+ } else {
+ printk(KERN_INFO "PCI: mapping irq for %s pin:%u, irq:%d\n",
+ pci_name((struct pci_dev *)dev), pin, irq);
+ }
+
+out:
+ return irq;
+}
+
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+ return 0;
+}
+
+/* -------------------------------------------------------------------------*/
+
+static struct resource pci_io_resource = {
+ .name = "ADM5120 PCI I/O",
+ .start = ADM5120_PCIIO_BASE,
+ .end = ADM5120_PCICFG_ADDR-1,
+ .flags = IORESOURCE_IO
+};
+
+static struct resource pci_mem_resource = {
+ .name = "ADM5120 PCI MEM",
+ .start = ADM5120_PCIMEM_BASE,
+ .end = ADM5120_PCIIO_BASE-1,
+ .flags = IORESOURCE_MEM
+};
+
+static struct pci_controller adm5120_controller = {
+ .pci_ops = &adm5120_pci_ops,
+ .io_resource = &pci_io_resource,
+ .mem_resource = &pci_mem_resource,
+};
+
+static int __init adm5120_pci_setup(void)
+{
+ if (adm5120_package_pqfp()) {
+ printk(KERN_INFO "PCI: not available on ADM5120P\n");
+ return -1;
+ }
+
+ /* Avoid ISA compat ranges. */
+ PCIBIOS_MIN_IO = 0x00000000;
+ PCIBIOS_MIN_MEM = 0x00000000;
+
+ /* Set I/O resource limits. */
+ ioport_resource.end = 0x1fffffff;
+ iomem_resource.end = 0xffffffff;
+
+ register_pci_controller(&adm5120_controller);
+ return 0;
+}
+
+arch_initcall(adm5120_pci_setup);
--- /dev/null
+/*
+ * A low-level PATA driver to handle a Compact Flash connected on the
+ * Mikrotik's RouterBoard 153 board.
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This file was based on: drivers/ata/pata_ixp4xx_cf.c
+ * Copyright (C) 2006-07 Tower Technologies
+ * Author: Alessandro Zummo <a.zummo@towertech.it>
+ *
+ * Also was based on the driver for Linux 2.4.xx published by Mikrotik for
+ * their RouterBoard 1xx and 5xx series devices. The original Mikrotik code
+ * seems not to have a license.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+
+#include <linux/libata.h>
+#include <scsi/scsi_host.h>
+
+#define DRV_NAME "pata-rb153-cf"
+#define DRV_VERSION "0.5.0"
+#define DRV_DESC "PATA driver for RouterBOARD 153 Compact Flash"
+
+#define RB153_CF_MAXPORTS 1
+#define RB153_CF_IO_DELAY 100
+
+#define RB153_CF_REG_CMD 0x0800
+#define RB153_CF_REG_CTRL 0x080E
+#define RB153_CF_REG_DATA 0x0C00
+
+struct rb153_cf_info {
+ void __iomem *iobase;
+ unsigned int gpio_line;
+ int frozen;
+ unsigned int irq;
+};
+
+static inline void rb153_pata_finish_io(struct ata_port *ap)
+{
+ struct rb153_cf_info *info = ap->host->private_data;
+
+ /* FIXME: Keep previous delay. If this is merely a fence then
+ * ata_sff_sync might be sufficient. */
+ ata_sff_dma_pause(ap);
+ ndelay(RB153_CF_IO_DELAY);
+
+ set_irq_type(info->irq, IRQ_TYPE_LEVEL_HIGH);
+}
+
+static void rb153_pata_exec_command(struct ata_port *ap,
+ const struct ata_taskfile *tf)
+{
+ writeb(tf->command, ap->ioaddr.command_addr);
+ rb153_pata_finish_io(ap);
+}
+
+static unsigned int rb153_pata_data_xfer(struct ata_device *adev,
+ unsigned char *buf,
+ unsigned int buflen,
+ int write_data)
+{
+ void __iomem *ioaddr = adev->link->ap->ioaddr.data_addr;
+ unsigned int t;
+
+ t = buflen;
+ if (write_data) {
+ for (; t > 0; t--, buf++)
+ writeb(*buf, ioaddr);
+ } else {
+ for (; t > 0; t--, buf++)
+ *buf = readb(ioaddr);
+ }
+
+ rb153_pata_finish_io(adev->link->ap);
+ return buflen;
+}
+
+static void rb153_pata_freeze(struct ata_port *ap)
+{
+ struct rb153_cf_info *info = ap->host->private_data;
+
+ info->frozen = 1;
+}
+
+static void rb153_pata_thaw(struct ata_port *ap)
+{
+ struct rb153_cf_info *info = ap->host->private_data;
+
+ info->frozen = 0;
+}
+
+static irqreturn_t rb153_pata_irq_handler(int irq, void *dev_instance)
+{
+ struct ata_host *ah = dev_instance;
+ struct rb153_cf_info *info = ah->private_data;
+
+ if (gpio_get_value(info->gpio_line)) {
+ set_irq_type(info->irq, IRQ_TYPE_LEVEL_LOW);
+ if (!info->frozen)
+ ata_sff_interrupt(irq, dev_instance);
+ } else {
+ set_irq_type(info->irq, IRQ_TYPE_LEVEL_HIGH);
+ }
+
+ return IRQ_HANDLED;
+}
+
+static struct ata_port_operations rb153_pata_port_ops = {
+ .inherits = &ata_sff_port_ops,
+ .sff_exec_command = rb153_pata_exec_command,
+ .sff_data_xfer = rb153_pata_data_xfer,
+ .freeze = rb153_pata_freeze,
+ .thaw = rb153_pata_thaw,
+};
+
+static struct scsi_host_template rb153_pata_sht = {
+ ATA_PIO_SHT(DRV_NAME),
+};
+
+static void rb153_pata_setup_port(struct ata_host *ah)
+{
+ struct rb153_cf_info *info = ah->private_data;
+ struct ata_port *ap;
+
+ ap = ah->ports[0];
+
+ ap->ops = &rb153_pata_port_ops;
+ ap->pio_mask = 0x1f; /* PIO4 */
+ ap->flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO;
+
+ ap->ioaddr.cmd_addr = info->iobase + RB153_CF_REG_CMD;
+ ap->ioaddr.ctl_addr = info->iobase + RB153_CF_REG_CTRL;
+ ap->ioaddr.altstatus_addr = info->iobase + RB153_CF_REG_CTRL;
+
+ ata_sff_std_ports(&ap->ioaddr);
+
+ ap->ioaddr.data_addr = info->iobase + RB153_CF_REG_DATA;
+}
+
+static __devinit int rb153_pata_driver_probe(struct platform_device *pdev)
+{
+ unsigned int irq;
+ int gpio;
+ struct resource *res;
+ struct ata_host *ah;
+ struct rb153_cf_info *info;
+ int ret;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(&pdev->dev, "no IOMEM resource found\n");
+ return -EINVAL;
+ }
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq <= 0) {
+ dev_err(&pdev->dev, "no IRQ resource found\n");
+ return -ENOENT;
+ }
+
+ gpio = irq_to_gpio(irq);
+ if (gpio < 0) {
+ dev_err(&pdev->dev, "no GPIO found for irq%d\n", irq);
+ return -ENOENT;
+ }
+
+ ret = gpio_request(gpio, DRV_NAME);
+ if (ret) {
+ dev_err(&pdev->dev, "GPIO request failed\n");
+ return ret;
+ }
+
+ ah = ata_host_alloc(&pdev->dev, RB153_CF_MAXPORTS);
+ if (!ah)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, ah);
+
+ info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
+ if (!info)
+ return -ENOMEM;
+
+ ah->private_data = info;
+ info->gpio_line = gpio;
+ info->irq = irq;
+
+ info->iobase = devm_ioremap_nocache(&pdev->dev, res->start,
+ res->end - res->start + 1);
+ if (!info->iobase)
+ return -ENOMEM;
+
+ ret = gpio_direction_input(gpio);
+ if (ret) {
+ dev_err(&pdev->dev, "unable to set GPIO direction, err=%d\n",
+ ret);
+ goto err_free_gpio;
+ }
+
+ rb153_pata_setup_port(ah);
+
+ ret = ata_host_activate(ah, irq, rb153_pata_irq_handler,
+ IRQF_TRIGGER_LOW, &rb153_pata_sht);
+ if (ret)
+ goto err_free_gpio;
+
+ return 0;
+
+err_free_gpio:
+ gpio_free(gpio);
+
+ return ret;
+}
+
+static __devexit int rb153_pata_driver_remove(struct platform_device *pdev)
+{
+ struct ata_host *ah = platform_get_drvdata(pdev);
+ struct rb153_cf_info *info = ah->private_data;
+
+ ata_host_detach(ah);
+ gpio_free(info->gpio_line);
+
+ return 0;
+}
+
+static struct platform_driver rb153_pata_platform_driver = {
+ .probe = rb153_pata_driver_probe,
+ .remove = __devexit_p(rb153_pata_driver_remove),
+ .driver = {
+ .name = DRV_NAME,
+ .owner = THIS_MODULE,
+ },
+};
+
+/* ------------------------------------------------------------------------ */
+
+#define DRV_INFO DRV_DESC " version " DRV_VERSION
+
+static int __init rb153_pata_module_init(void)
+{
+ printk(KERN_INFO DRV_INFO "\n");
+
+ return platform_driver_register(&rb153_pata_platform_driver);
+}
+
+static void __exit rb153_pata_module_exit(void)
+{
+ platform_driver_unregister(&rb153_pata_platform_driver);
+}
+
+MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
+MODULE_DESCRIPTION(DRV_DESC);
+MODULE_VERSION(DRV_VERSION);
+MODULE_LICENSE("GPL v2");
+
+module_init(rb153_pata_module_init);
+module_exit(rb153_pata_module_exit);
--- /dev/null
+/*
+ * LED ADM5120 Switch Port State Trigger
+ *
+ * Copyright (C) 2007 Bernhard Held <bernhard at bernhardheld.de>
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This file was based on: drivers/leds/ledtrig-timer.c
+ * Copyright 2005-2006 Openedhand Ltd.
+ * Author: Richard Purdie
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/device.h>
+
+#include <linux/gpio.h>
+
+#include "leds.h"
+
+#define DRV_NAME "port_state"
+#define DRV_DESC "LED ADM5120 Switch Port State Trigger"
+
+struct port_state {
+ char *name;
+ unsigned int value;
+};
+
+#define PORT_STATE(n,v) {.name = (n), .value = (v)}
+
+static struct port_state port_states[] = {
+ PORT_STATE("off", LED_OFF),
+ PORT_STATE("on", LED_FULL),
+ PORT_STATE("flash", ADM5120_GPIO_FLASH),
+ PORT_STATE("link", ADM5120_GPIO_LINK),
+ PORT_STATE("speed", ADM5120_GPIO_SPEED),
+ PORT_STATE("duplex", ADM5120_GPIO_DUPLEX),
+ PORT_STATE("act", ADM5120_GPIO_ACT),
+ PORT_STATE("coll", ADM5120_GPIO_COLL),
+ PORT_STATE("link_act", ADM5120_GPIO_LINK_ACT),
+ PORT_STATE("duplex_coll", ADM5120_GPIO_DUPLEX_COLL),
+ PORT_STATE("10M_act", ADM5120_GPIO_10M_ACT),
+ PORT_STATE("100M_act", ADM5120_GPIO_100M_ACT),
+};
+
+static ssize_t led_port_state_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct led_classdev *led_cdev = dev_get_drvdata(dev);
+ struct port_state *state = led_cdev->trigger_data;
+ int len = 0;
+ int i;
+
+ *buf = '\0';
+ for (i = 0; i < ARRAY_SIZE(port_states); i++) {
+ if (&port_states[i] == state)
+ len += sprintf(buf+len, "[%s] ", port_states[i].name);
+ else
+ len += sprintf(buf+len, "%s ", port_states[i].name);
+ }
+ len += sprintf(buf+len, "\n");
+
+ return len;
+}
+
+static ssize_t led_port_state_store(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t size)
+{
+ struct led_classdev *led_cdev = dev_get_drvdata(dev);
+ size_t len;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(port_states); i++) {
+ len = strlen(port_states[i].name);
+ if (strncmp(port_states[i].name, buf, len) != 0)
+ continue;
+
+ if (buf[len] != '\0' && buf[len] != '\n')
+ continue;
+
+ led_cdev->trigger_data = &port_states[i];
+ led_set_brightness(led_cdev, port_states[i].value);
+ return size;
+ }
+
+ return -EINVAL;
+}
+
+static DEVICE_ATTR(port_state, 0644, led_port_state_show,
+ led_port_state_store);
+
+static void adm5120_switch_trig_activate(struct led_classdev *led_cdev)
+{
+ struct port_state *state = port_states;
+ int rc;
+
+ led_cdev->trigger_data = state;
+
+ rc = device_create_file(led_cdev->dev, &dev_attr_port_state);
+ if (rc)
+ goto err;
+
+ led_set_brightness(led_cdev, state->value);
+
+ return;
+err:
+ led_cdev->trigger_data = NULL;
+}
+
+static void adm5120_switch_trig_deactivate(struct led_classdev *led_cdev)
+{
+ struct port_state *state = led_cdev->trigger_data;
+
+ if (!state)
+ return;
+
+ device_remove_file(led_cdev->dev, &dev_attr_port_state);
+
+}
+
+static struct led_trigger adm5120_switch_led_trigger = {
+ .name = DRV_NAME,
+ .activate = adm5120_switch_trig_activate,
+ .deactivate = adm5120_switch_trig_deactivate,
+};
+
+static int __init adm5120_switch_trig_init(void)
+{
+ led_trigger_register(&adm5120_switch_led_trigger);
+ return 0;
+}
+
+static void __exit adm5120_switch_trig_exit(void)
+{
+ led_trigger_unregister(&adm5120_switch_led_trigger);
+}
+
+module_init(adm5120_switch_trig_init);
+module_exit(adm5120_switch_trig_exit);
+
+MODULE_AUTHOR("Bernhard Held <bernhard at bernhardheld.de>, "
+ "Gabor Juhos <juhosg@openwrt.org>");
+MODULE_DESCRIPTION(DRV_DESC);
+MODULE_LICENSE("GPL v2");
--- /dev/null
+/*
+ * Platform driver for NOR flash devices on ADM5120 based boards
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This file was derived from: drivers/mtd/map/physmap.c
+ * Copyright (C) 2003 MontaVista Software Inc.
+ * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/mach-adm5120/adm5120_defs.h>
+#include <asm/mach-adm5120/adm5120_switch.h>
+#include <asm/mach-adm5120/adm5120_mpmc.h>
+#include <asm/mach-adm5120/adm5120_platform.h>
+
+#define DRV_NAME "adm5120-flash"
+#define DRV_DESC "ADM5120 flash MAP driver"
+#define MAX_PARSED_PARTS 8
+
+#ifdef ADM5120_FLASH_DEBUG
+#define MAP_DBG(m, f, a...) printk(KERN_INFO "%s: " f, (m->name) , ## a)
+#else
+#define MAP_DBG(m, f, a...) do {} while (0)
+#endif
+#define MAP_ERR(m, f, a...) printk(KERN_ERR "%s: " f, (m->name) , ## a)
+#define MAP_INFO(m, f, a...) printk(KERN_INFO "%s: " f, (m->name) , ## a)
+
+struct adm5120_map_info {
+ struct map_info map;
+ void (*switch_bank)(unsigned);
+ unsigned long window_size;
+};
+
+struct adm5120_flash_info {
+ struct mtd_info *mtd;
+ struct resource *res;
+ struct platform_device *dev;
+ struct adm5120_map_info amap;
+#ifdef CONFIG_MTD_PARTITIONS
+ int nr_parts;
+ struct mtd_partition *parts[MAX_PARSED_PARTS];
+#endif
+};
+
+struct flash_desc {
+ u32 phys;
+ u32 srs_shift;
+};
+
+/*
+ * Globals
+ */
+static DEFINE_SPINLOCK(adm5120_flash_spin);
+#define FLASH_LOCK() spin_lock(&adm5120_flash_spin)
+#define FLASH_UNLOCK() spin_unlock(&adm5120_flash_spin)
+
+static u32 flash_bankwidths[4] = { 1, 2, 4, 0 };
+
+static u32 flash_sizes[8] = {
+ 0, 512*1024, 1024*1024, 2*1024*1024,
+ 4*1024*1024, 0, 0, 0
+};
+
+static struct flash_desc flash_descs[2] = {
+ {
+ .phys = ADM5120_SRAM0_BASE,
+ .srs_shift = MEMCTRL_SRS0_SHIFT,
+ }, {
+ .phys = ADM5120_SRAM1_BASE,
+ .srs_shift = MEMCTRL_SRS1_SHIFT,
+ }
+};
+
+static const char *probe_types[] = {
+ "cfi_probe",
+ "jedec_probe",
+ "map_rom",
+ NULL
+};
+
+#ifdef CONFIG_MTD_PARTITIONS
+static const char *parse_types[] = {
+ "cmdlinepart",
+#ifdef CONFIG_MTD_REDBOOT_PARTS
+ "RedBoot",
+#endif
+#ifdef CONFIG_MTD_MYLOADER_PARTS
+ "MyLoader",
+#endif
+};
+#endif
+
+#define BANK_SIZE (2<<20)
+#define BANK_SIZE_MAX (4<<20)
+#define BANK_OFFS_MASK (BANK_SIZE-1)
+#define BANK_START_MASK (~BANK_OFFS_MASK)
+
+static inline struct adm5120_map_info *map_to_amap(struct map_info *map)
+{
+ return (struct adm5120_map_info *)map;
+}
+
+static void adm5120_flash_switchbank(struct map_info *map,
+ unsigned long ofs)
+{
+ struct adm5120_map_info *amap = map_to_amap(map);
+ unsigned bank;
+
+ if (amap->switch_bank == NULL)
+ return;
+
+ bank = (ofs & BANK_START_MASK) >> 21;
+ if (bank > 1)
+ BUG();
+
+ MAP_DBG(map, "switching to bank %u, ofs=%lX\n", bank, ofs);
+ amap->switch_bank(bank);
+}
+
+static map_word adm5120_flash_read(struct map_info *map, unsigned long ofs)
+{
+ struct adm5120_map_info *amap = map_to_amap(map);
+ map_word ret;
+
+ MAP_DBG(map, "reading from ofs %lX\n", ofs);
+
+ if (ofs >= amap->window_size)
+ return map_word_ff(map);
+
+ FLASH_LOCK();
+ adm5120_flash_switchbank(map, ofs);
+ ret = inline_map_read(map, (ofs & (amap->window_size-1)));
+ FLASH_UNLOCK();
+
+ return ret;
+}
+
+static void adm5120_flash_write(struct map_info *map, const map_word datum,
+ unsigned long ofs)
+{
+ struct adm5120_map_info *amap = map_to_amap(map);
+
+ MAP_DBG(map, "writing to ofs %lX\n", ofs);
+
+ if (ofs > amap->window_size)
+ return;
+
+ FLASH_LOCK();
+ adm5120_flash_switchbank(map, ofs);
+ inline_map_write(map, datum, (ofs & (amap->window_size-1)));
+ FLASH_UNLOCK();
+}
+
+static void adm5120_flash_copy_from(struct map_info *map, void *to,
+ unsigned long from, ssize_t len)
+{
+ struct adm5120_map_info *amap = map_to_amap(map);
+ char *p;
+ ssize_t t;
+
+ MAP_DBG(map, "copy_from, to=%lX, from=%lX, len=%lX\n",
+ (unsigned long)to, from, (unsigned long)len);
+
+ if (from > amap->window_size)
+ return;
+
+ p = (char *)to;
+ while (len > 0) {
+ t = len;
+ if ((from < BANK_SIZE) && ((from+len) > BANK_SIZE))
+ t = BANK_SIZE-from;
+
+ FLASH_LOCK();
+ MAP_DBG(map, "copying %lu byte(s) from %lX to %lX\n",
+ (unsigned long)t, (from & (amap->window_size-1)),
+ (unsigned long)p);
+ adm5120_flash_switchbank(map, from);
+ inline_map_copy_from(map, p, (from & (amap->window_size-1)), t);
+ FLASH_UNLOCK();
+ p += t;
+ from += t;
+ len -= t;
+ }
+}
+
+static int adm5120_flash_initres(struct adm5120_flash_info *info)
+{
+ struct map_info *map = &info->amap.map;
+ int err = 0;
+
+ info->res = request_mem_region(map->phys, info->amap.window_size,
+ map->name);
+ if (info->res == NULL) {
+ MAP_ERR(map, "could not reserve memory region\n");
+ err = -ENOMEM;
+ goto out;
+ }
+
+ map->virt = ioremap_nocache(map->phys, info->amap.window_size);
+ if (map->virt == NULL) {
+ MAP_ERR(map, "failed to ioremap flash region\n");
+ err = -ENOMEM;
+ goto out;
+ }
+
+out:
+ return err;
+}
+
+static int adm5120_flash_initinfo(struct adm5120_flash_info *info,
+ struct platform_device *dev)
+{
+ struct map_info *map = &info->amap.map;
+ struct adm5120_flash_platform_data *pdata = dev->dev.platform_data;
+ struct flash_desc *fdesc;
+ u32 t = 0;
+
+ map->name = dev->dev.bus_id;
+
+ if (dev->id > 1) {
+ MAP_ERR(map, "invalid flash id\n");
+ goto err_out;
+ }
+
+ fdesc = &flash_descs[dev->id];
+
+ if (pdata)
+ info->amap.window_size = pdata->window_size;
+
+ if (info->amap.window_size == 0) {
+ /* get memory window size */
+ t = SW_READ_REG(SWITCH_REG_MEMCTRL) >> fdesc->srs_shift;
+ t &= MEMCTRL_SRS_MASK;
+ info->amap.window_size = flash_sizes[t];
+ }
+
+ if (info->amap.window_size == 0) {
+ MAP_ERR(map, "unable to determine window size\n");
+ goto err_out;
+ }
+
+ /* get flash bus width */
+ switch (dev->id) {
+ case 0:
+ t = MPMC_READ_REG(SC1) & SC_MW_MASK;
+ break;
+ case 1:
+ t = MPMC_READ_REG(SC0) & SC_MW_MASK;
+ break;
+ }
+ map->bankwidth = flash_bankwidths[t];
+ if (map->bankwidth == 0) {
+ MAP_ERR(map, "invalid bus width detected\n");
+ goto err_out;
+ }
+
+ map->phys = fdesc->phys;
+ map->size = BANK_SIZE_MAX;
+
+ simple_map_init(map);
+ map->read = adm5120_flash_read;
+ map->write = adm5120_flash_write;
+ map->copy_from = adm5120_flash_copy_from;
+
+ if (pdata) {
+ map->set_vpp = pdata->set_vpp;
+ info->amap.switch_bank = pdata->switch_bank;
+ }
+
+ info->dev = dev;
+
+ MAP_INFO(map, "probing at 0x%lX, size:%ldKiB, width:%d bits\n",
+ (unsigned long)map->phys,
+ (unsigned long)info->amap.window_size >> 10,
+ map->bankwidth*8);
+
+ return 0;
+
+err_out:
+ return -ENODEV;
+}
+
+static void adm5120_flash_initbanks(struct adm5120_flash_info *info)
+{
+ struct map_info *map = &info->amap.map;
+
+ if (info->mtd->size <= BANK_SIZE)
+ /* no bank switching needed */
+ return;
+
+ if (info->amap.switch_bank) {
+ info->amap.window_size = info->mtd->size;
+ return;
+ }
+
+ MAP_ERR(map, "reduce visibility from %ldKiB to %ldKiB\n",
+ (unsigned long)map->size >> 10,
+ (unsigned long)info->mtd->size >> 10);
+
+ info->mtd->size = info->amap.window_size;
+}
+
+#ifdef CONFIG_MTD_PARTITIONS
+static int adm5120_flash_initparts(struct adm5120_flash_info *info)
+{
+ struct adm5120_flash_platform_data *pdata;
+ struct map_info *map = &info->amap.map;
+ int num_parsers;
+ const char *parser[2];
+ int err = 0;
+ int nr_parts;
+ int i;
+
+ info->nr_parts = 0;
+
+ pdata = info->dev->dev.platform_data;
+ if (pdata == NULL)
+ goto out;
+
+ if (pdata->nr_parts) {
+ MAP_INFO(map, "adding static partitions\n");
+ err = add_mtd_partitions(info->mtd, pdata->parts,
+ pdata->nr_parts);
+ if (err == 0) {
+ info->nr_parts += pdata->nr_parts;
+ goto out;
+ }
+ }
+
+ num_parsers = ARRAY_SIZE(parse_types);
+ if (num_parsers > MAX_PARSED_PARTS)
+ num_parsers = MAX_PARSED_PARTS;
+
+ parser[1] = NULL;
+ for (i = 0; i < num_parsers; i++) {
+ parser[0] = parse_types[i];
+
+ MAP_INFO(map, "parsing \"%s\" partitions\n",
+ parser[0]);
+ nr_parts = parse_mtd_partitions(info->mtd, parser,
+ &info->parts[i], 0);
+
+ if (nr_parts <= 0)
+ continue;
+
+ MAP_INFO(map, "adding \"%s\" partitions\n",
+ parser[0]);
+
+ err = add_mtd_partitions(info->mtd, info->parts[i], nr_parts);
+ if (err)
+ break;
+
+ info->nr_parts += nr_parts;
+ }
+out:
+ return err;
+}
+#else
+static int adm5120_flash_initparts(struct adm5120_flash_info *info)
+{
+ return 0;
+}
+#endif /* CONFIG_MTD_PARTITIONS */
+
+#ifdef CONFIG_MTD_PARTITIONS
+static void adm5120_flash_remove_mtd(struct adm5120_flash_info *info)
+{
+ int i;
+
+ if (info->nr_parts) {
+ del_mtd_partitions(info->mtd);
+ for (i = 0; i < MAX_PARSED_PARTS; i++)
+ if (info->parts[i] != NULL)
+ kfree(info->parts[i]);
+ } else {
+ del_mtd_device(info->mtd);
+ }
+}
+#else
+static void adm5120_flash_remove_mtd(struct adm5120_flash_info *info)
+{
+ del_mtd_device(info->mtd);
+}
+#endif
+
+static int adm5120_flash_remove(struct platform_device *dev)
+{
+ struct adm5120_flash_info *info;
+
+ info = platform_get_drvdata(dev);
+ if (info == NULL)
+ return 0;
+
+ platform_set_drvdata(dev, NULL);
+
+ if (info->mtd != NULL) {
+ adm5120_flash_remove_mtd(info);
+ map_destroy(info->mtd);
+ }
+
+ if (info->amap.map.virt != NULL)
+ iounmap(info->amap.map.virt);
+
+ if (info->res != NULL) {
+ release_resource(info->res);
+ kfree(info->res);
+ }
+
+ return 0;
+}
+
+static int adm5120_flash_probe(struct platform_device *dev)
+{
+ struct adm5120_flash_info *info;
+ struct map_info *map;
+ const char **probe_type;
+ int err;
+
+ info = kzalloc(sizeof(*info), GFP_KERNEL);
+ if (info == NULL) {
+ err = -ENOMEM;
+ goto err_out;
+ }
+
+ platform_set_drvdata(dev, info);
+
+ err = adm5120_flash_initinfo(info, dev);
+ if (err)
+ goto err_out;
+
+ err = adm5120_flash_initres(info);
+ if (err)
+ goto err_out;
+
+ map = &info->amap.map;
+ for (probe_type = probe_types; info->mtd == NULL && *probe_type != NULL;
+ probe_type++)
+ info->mtd = do_map_probe(*probe_type, map);
+
+ if (info->mtd == NULL) {
+ MAP_ERR(map, "map_probe failed\n");
+ err = -ENXIO;
+ goto err_out;
+ }
+
+ adm5120_flash_initbanks(info);
+
+ if (info->mtd->size < info->amap.window_size) {
+ /* readjust resources */
+ iounmap(map->virt);
+ release_resource(info->res);
+ kfree(info->res);
+
+ info->amap.window_size = info->mtd->size;
+ map->size = info->mtd->size;
+ MAP_INFO(map, "reducing map size to %ldKiB\n",
+ (unsigned long)map->size >> 10);
+ err = adm5120_flash_initres(info);
+ if (err)
+ goto err_out;
+ }
+
+ MAP_INFO(map, "found at 0x%lX, size:%ldKiB, width:%d bits\n",
+ (unsigned long)map->phys, (unsigned long)info->mtd->size >> 10,
+ map->bankwidth*8);
+
+ info->mtd->owner = THIS_MODULE;
+
+ err = adm5120_flash_initparts(info);
+ if (err)
+ goto err_out;
+
+ if (info->nr_parts == 0) {
+ MAP_INFO(map, "no partitions available, registering "
+ "whole flash\n");
+ add_mtd_device(info->mtd);
+ }
+
+ return 0;
+
+err_out:
+ adm5120_flash_remove(dev);
+ return err;
+}
+
+#ifdef CONFIG_PM
+static int adm5120_flash_suspend(struct platform_device *dev,
+ pm_message_t state)
+{
+ struct adm5120_flash_info *info = platform_get_drvdata(dev);
+ int ret = 0;
+
+ if (info)
+ ret = info->mtd->suspend(info->mtd);
+
+ return ret;
+}
+
+static int adm5120_flash_resume(struct platform_device *dev)
+{
+ struct adm5120_flash_info *info = platform_get_drvdata(dev);
+
+ if (info)
+ info->mtd->resume(info->mtd);
+
+ return 0;
+}
+
+static void adm5120_flash_shutdown(struct platform_device *dev)
+{
+ struct adm5120_flash_info *info = platform_get_drvdata(dev);
+
+ if (info && info->mtd->suspend(info->mtd) == 0)
+ info->mtd->resume(info->mtd);
+}
+#endif
+
+static struct platform_driver adm5120_flash_driver = {
+ .probe = adm5120_flash_probe,
+ .remove = adm5120_flash_remove,
+#ifdef CONFIG_PM
+ .suspend = adm5120_flash_suspend,
+ .resume = adm5120_flash_resume,
+ .shutdown = adm5120_flash_shutdown,
+#endif
+ .driver = {
+ .name = DRV_NAME,
+ },
+};
+
+static int __init adm5120_flash_init(void)
+{
+ int err;
+
+ err = platform_driver_register(&adm5120_flash_driver);
+
+ return err;
+}
+
+static void __exit adm5120_flash_exit(void)
+{
+ platform_driver_unregister(&adm5120_flash_driver);
+}
+
+module_init(adm5120_flash_init);
+module_exit(adm5120_flash_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
+MODULE_DESCRIPTION(DRV_DESC);
--- /dev/null
+/*
+ * Parse MyLoader-style flash partition tables and produce a Linux partition
+ * array to match.
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This file was based on drivers/mtd/redboot.c
+ * Author: Red Hat, Inc. - David Woodhouse <dwmw2@cambridge.redhat.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/vmalloc.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <linux/byteorder/generic.h>
+
+#include <prom/myloader.h>
+
+#define NAME_LEN_MAX 20
+#define NAME_MYLOADER "MyLoader"
+#define NAME_PARTITION_TABLE "Partition Table"
+#define BLOCK_LEN_MIN 0x10000
+
+int parse_myloader_partitions(struct mtd_info *master,
+ struct mtd_partition **pparts,
+ unsigned long origin)
+{
+ struct mylo_partition_table *tab;
+ struct mylo_partition *part;
+ struct mtd_partition *mtd_parts;
+ struct mtd_partition *mtd_part;
+ int num_parts;
+ int ret, i;
+ size_t retlen;
+ char *names;
+ unsigned long offset;
+ unsigned long blocklen;
+
+ tab = vmalloc(sizeof(*tab));
+ if (!tab) {
+ return -ENOMEM;
+ goto out;
+ }
+
+ blocklen = master->erasesize;
+ if (blocklen < BLOCK_LEN_MIN)
+ blocklen = BLOCK_LEN_MIN;
+
+ /* Partition Table is always located on the second erase block */
+ offset = blocklen;
+ printk(KERN_NOTICE "%s: searching for MyLoader partition table at "
+ "offset 0x%lx\n", master->name, offset);
+
+ ret = master->read(master, offset, sizeof(*tab), &retlen, (void *)tab);
+ if (ret)
+ goto out;
+
+ if (retlen != sizeof(*tab)) {
+ ret = -EIO;
+ goto out_free_buf;
+ }
+
+ /* Check for Partition Table magic number */
+ if (tab->magic != le32_to_cpu(MYLO_MAGIC_PARTITIONS)) {
+ printk(KERN_NOTICE "%s: no MyLoader partition table found\n",
+ master->name);
+ ret = 0;
+ goto out_free_buf;
+ }
+
+ /* The MyLoader and the Partition Table is always present */
+ num_parts = 2;
+
+ /* Detect number of used partitions */
+ for (i = 0; i < MYLO_MAX_PARTITIONS; i++) {
+ part = &tab->partitions[i];
+
+ if (le16_to_cpu(part->type) == PARTITION_TYPE_FREE)
+ continue;
+
+ num_parts++;
+ }
+
+ mtd_parts = kzalloc((num_parts * sizeof(*mtd_part) +
+ num_parts * NAME_LEN_MAX), GFP_KERNEL);
+
+ if (!mtd_parts) {
+ ret = -ENOMEM;
+ goto out_free_buf;
+ }
+
+ mtd_part = mtd_parts;
+ names = (char *)&mtd_parts[num_parts];
+
+ strncpy(names, NAME_MYLOADER, NAME_LEN_MAX-1);
+ mtd_part->name = names;
+ mtd_part->offset = 0;
+ mtd_part->size = blocklen;
+ mtd_part->mask_flags = MTD_WRITEABLE;
+ mtd_part++;
+ names += NAME_LEN_MAX;
+
+ strncpy(names, NAME_PARTITION_TABLE, NAME_LEN_MAX-1);
+ mtd_part->name = names;
+ mtd_part->offset = blocklen;
+ mtd_part->size = blocklen;
+ mtd_part->mask_flags = MTD_WRITEABLE;
+ mtd_part++;
+ names += NAME_LEN_MAX;
+
+ for (i = 0; i < MYLO_MAX_PARTITIONS; i++) {
+ part = &tab->partitions[i];
+
+ if (le16_to_cpu(part->type) == PARTITION_TYPE_FREE)
+ continue;
+
+ sprintf(names, "partition%d", i);
+ mtd_part->offset = le32_to_cpu(part->addr);
+ mtd_part->size = le32_to_cpu(part->size);
+ mtd_part->name = names;
+ mtd_part++;
+ names += NAME_LEN_MAX;
+ }
+
+ *pparts = mtd_parts;
+ ret = num_parts;
+
+out_free_buf:
+ vfree(tab);
+out:
+ return ret;
+}
+
+static struct mtd_part_parser mylo_mtd_parser = {
+ .owner = THIS_MODULE,
+ .parse_fn = parse_myloader_partitions,
+ .name = NAME_MYLOADER,
+};
+
+static int __init mylo_mtd_parser_init(void)
+{
+ return register_mtd_parser(&mylo_mtd_parser);
+}
+
+static void __exit mylo_mtd_parser_exit(void)
+{
+ deregister_mtd_parser(&mylo_mtd_parser);
+}
+
+module_init(mylo_mtd_parser_init);
+module_exit(mylo_mtd_parser_exit);
+
+MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
+MODULE_DESCRIPTION("Parsing code for MyLoader partition tables");
+MODULE_LICENSE("GPL v2");
--- /dev/null
+/*
+ * Copyright (C) Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/list.h>
+#include <linux/kmod.h>
+#include <linux/root_dev.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <linux/byteorder/generic.h>
+
+#define PFX "trxsplit: "
+
+#define TRX_MAGIC 0x30524448 /* "HDR0" */
+#define TRX_VERSION 1
+#define TRX_MAX_LEN 0x3A0000
+#define TRX_NO_HEADER 0x1 /* do not write TRX header */
+#define TRX_GZ_FILES 0x2 /* contains individual gzip files */
+#define TRX_MAX_OFFSET 3
+#define TRX_MIN_KERNEL_SIZE 256*1024
+
+struct trx_header {
+ u32 magic; /* "HDR0" */
+ u32 len; /* Length of file including header */
+ u32 crc32; /* 32-bit CRC from flag_version to end of file */
+ u32 flag_version; /* 0:15 flags, 16:31 version */
+ u32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions */
+};
+
+#define TRX_ALIGN 0x1000
+
+static int trx_nr_parts;
+static unsigned long trx_offset;
+static struct mtd_info *trx_mtd;
+static struct mtd_partition trx_parts[TRX_MAX_OFFSET];
+static struct trx_header trx_hdr;
+
+static int trxsplit_refresh_partitions(struct mtd_info *mtd);
+
+static int trxsplit_checktrx(struct mtd_info *mtd, unsigned long offset)
+{
+ size_t retlen;
+ int err;
+
+ err = mtd->read(mtd, offset, sizeof(trx_hdr), &retlen,
+ (void *)&trx_hdr);
+ if (err) {
+ printk(KERN_ALERT PFX "unable to read from '%s'\n", mtd->name);
+ goto err_out;
+ }
+
+ if (retlen != sizeof(trx_hdr)) {
+ printk(KERN_ALERT PFX "reading failed on '%s'\n", mtd->name);
+ goto err_out;
+ }
+
+ trx_hdr.magic = le32_to_cpu(trx_hdr.magic);
+ trx_hdr.len = le32_to_cpu(trx_hdr.len);
+ trx_hdr.crc32 = le32_to_cpu(trx_hdr.crc32);
+ trx_hdr.flag_version = le32_to_cpu(trx_hdr.flag_version);
+ trx_hdr.offsets[0] = le32_to_cpu(trx_hdr.offsets[0]);
+ trx_hdr.offsets[1] = le32_to_cpu(trx_hdr.offsets[1]);
+ trx_hdr.offsets[2] = le32_to_cpu(trx_hdr.offsets[2]);
+
+ /* sanity checks */
+ if (trx_hdr.magic != TRX_MAGIC)
+ goto err_out;
+
+ if (trx_hdr.len > mtd->size - offset)
+ goto err_out;
+
+ /* TODO: add crc32 checking too? */
+
+ return 0;
+
+err_out:
+ return -1;
+}
+
+static void trxsplit_findtrx(struct mtd_info *mtd)
+{
+ unsigned long offset;
+ int err;
+
+ printk(KERN_INFO PFX "searching TRX header in '%s'\n", mtd->name);
+
+ err = 0;
+ for (offset = 0; offset < mtd->size; offset += TRX_ALIGN) {
+ err = trxsplit_checktrx(mtd, offset);
+ if (err == 0)
+ break;
+ }
+
+ if (err)
+ return;
+
+ printk(KERN_INFO PFX "TRX header found at 0x%lX\n", offset);
+
+ trx_mtd = mtd;
+ trx_offset = offset;
+}
+
+static void trxsplit_create_partitions(struct mtd_info *mtd)
+{
+ struct mtd_partition *part = trx_parts;
+ int err;
+ int i;
+
+ for (i = 0; i < TRX_MAX_OFFSET; i++) {
+ part = &trx_parts[i];
+ if (trx_hdr.offsets[i] == 0)
+ continue;
+ part->offset = trx_offset + trx_hdr.offsets[i];
+ trx_nr_parts++;
+ }
+
+ for (i = 0; i < trx_nr_parts-1; i++)
+ trx_parts[i].size = trx_parts[i+1].offset - trx_parts[i].offset;
+
+ trx_parts[i].size = mtd->size - trx_parts[i].offset;
+
+ i = 0;
+ part = &trx_parts[i];
+ if (part->size < TRX_MIN_KERNEL_SIZE) {
+ part->name = "loader";
+ i++;
+ }
+
+ part = &trx_parts[i];
+ part->name = "kernel";
+ i++;
+
+ part = &trx_parts[i];
+ part->name = "rootfs";
+
+ err = add_mtd_partitions(mtd, trx_parts, trx_nr_parts);
+ if (err) {
+ printk(KERN_ALERT PFX "adding TRX partitions failed\n");
+ return;
+ }
+
+ mtd->refresh_device = trxsplit_refresh_partitions;
+}
+
+static int trxsplit_refresh_partitions(struct mtd_info *mtd)
+{
+ printk(KERN_INFO PFX "refreshing TRX partitions in '%s' (%d,%d)\n",
+ mtd->name, MTD_BLOCK_MAJOR, mtd->index);
+
+ /* remove old partitions */
+ del_mtd_partitions(mtd);
+
+ trxsplit_findtrx(mtd);
+ if (!trx_mtd)
+ goto err;
+
+ trxsplit_create_partitions(trx_mtd);
+ return 1;
+
+err:
+ return 0;
+}
+
+static void __init trxsplit_add_mtd(struct mtd_info *mtd)
+{
+ if (mtd->type != MTD_NORFLASH) {
+ printk(KERN_INFO PFX "'%s' is not a NOR flash, skipped\n",
+ mtd->name);
+ return;
+ }
+
+ if (!trx_mtd)
+ trxsplit_findtrx(mtd);
+}
+
+static void __init trxsplit_remove_mtd(struct mtd_info *mtd)
+{
+ /* nothing to do */
+}
+
+static struct mtd_notifier trxsplit_notifier __initdata = {
+ .add = trxsplit_add_mtd,
+ .remove = trxsplit_remove_mtd,
+};
+
+static void __init trxsplit_scan(void)
+{
+ register_mtd_user(&trxsplit_notifier);
+ unregister_mtd_user(&trxsplit_notifier);
+}
+
+static int __init trxsplit_init(void)
+{
+ trxsplit_scan();
+
+ if (trx_mtd) {
+ printk(KERN_INFO PFX "creating TRX partitions in '%s' "
+ "(%d,%d)\n", trx_mtd->name, MTD_BLOCK_MAJOR,
+ trx_mtd->index);
+ trxsplit_create_partitions(trx_mtd);
+ }
+
+ return 0;
+}
+
+late_initcall(trxsplit_init);
--- /dev/null
+/*
+ * ADM5120 built-in ethernet switch driver
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This code was based on a driver for Linux 2.6.xx by Jeroen Vreeken.
+ * Copyright Jeroen Vreeken (pe1rxq@amsat.org), 2005
+ * NAPI extension for the Jeroen's driver
+ * Copyright Thomas Langer (Thomas.Langer@infineon.com), 2007
+ * Copyright Friedrich Beckmann (Friedrich.Beckmann@infineon.com), 2007
+ * Inspiration for the Jeroen's driver came from the ADMtek 2.4 driver.
+ * Copyright ADMtek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/spinlock.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+
+#include <asm/mipsregs.h>
+
+#include <asm/mach-adm5120/adm5120_info.h>
+#include <asm/mach-adm5120/adm5120_defs.h>
+#include <asm/mach-adm5120/adm5120_switch.h>
+
+#include "adm5120sw.h"
+
+#define DRV_NAME "adm5120-switch"
+#define DRV_DESC "ADM5120 built-in ethernet switch driver"
+#define DRV_VERSION "0.1.1"
+
+#define CONFIG_ADM5120_SWITCH_NAPI 1
+#undef CONFIG_ADM5120_SWITCH_DEBUG
+
+/* ------------------------------------------------------------------------ */
+
+#ifdef CONFIG_ADM5120_SWITCH_DEBUG
+#define SW_DBG(f, a...) printk(KERN_DBG "%s: " f, DRV_NAME , ## a)
+#else
+#define SW_DBG(f, a...) do {} while (0)
+#endif
+#define SW_ERR(f, a...) printk(KERN_ERR "%s: " f, DRV_NAME , ## a)
+#define SW_INFO(f, a...) printk(KERN_INFO "%s: " f, DRV_NAME , ## a)
+
+#define SWITCH_NUM_PORTS 6
+#define ETH_CSUM_LEN 4
+
+#define RX_MAX_PKTLEN 1550
+#define RX_RING_SIZE 64
+
+#define TX_RING_SIZE 32
+#define TX_QUEUE_LEN 28 /* Limit ring entries actually used. */
+#define TX_TIMEOUT HZ*400
+
+#define RX_DESCS_SIZE (RX_RING_SIZE * sizeof(struct dma_desc *))
+#define RX_SKBS_SIZE (RX_RING_SIZE * sizeof(struct sk_buff *))
+#define TX_DESCS_SIZE (TX_RING_SIZE * sizeof(struct dma_desc *))
+#define TX_SKBS_SIZE (TX_RING_SIZE * sizeof(struct sk_buff *))
+
+#define SKB_ALLOC_LEN (RX_MAX_PKTLEN + 32)
+#define SKB_RESERVE_LEN (NET_IP_ALIGN + NET_SKB_PAD)
+
+#define SWITCH_INTS_HIGH (SWITCH_INT_SHD | SWITCH_INT_RHD | SWITCH_INT_HDF)
+#define SWITCH_INTS_LOW (SWITCH_INT_SLD | SWITCH_INT_RLD | SWITCH_INT_LDF)
+#define SWITCH_INTS_ERR (SWITCH_INT_RDE | SWITCH_INT_SDE | SWITCH_INT_CPUH)
+#define SWITCH_INTS_Q (SWITCH_INT_P0QF | SWITCH_INT_P1QF | SWITCH_INT_P2QF | \
+ SWITCH_INT_P3QF | SWITCH_INT_P4QF | SWITCH_INT_P5QF | \
+ SWITCH_INT_CPQF | SWITCH_INT_GQF)
+
+#define SWITCH_INTS_ALL (SWITCH_INTS_HIGH | SWITCH_INTS_LOW | \
+ SWITCH_INTS_ERR | SWITCH_INTS_Q | \
+ SWITCH_INT_MD | SWITCH_INT_PSC)
+
+#define SWITCH_INTS_USED (SWITCH_INTS_LOW | SWITCH_INT_PSC)
+#define SWITCH_INTS_POLL (SWITCH_INT_RLD | SWITCH_INT_LDF | SWITCH_INT_SLD)
+
+/* ------------------------------------------------------------------------ */
+
+struct adm5120_if_priv {
+ struct net_device *dev;
+
+ unsigned int vlan_no;
+ unsigned int port_mask;
+
+#ifdef CONFIG_ADM5120_SWITCH_NAPI
+ struct napi_struct napi;
+#endif
+};
+
+struct dma_desc {
+ __u32 buf1;
+#define DESC_OWN (1UL << 31) /* Owned by the switch */
+#define DESC_EOR (1UL << 28) /* End of Ring */
+#define DESC_ADDR_MASK 0x1FFFFFF
+#define DESC_ADDR(x) ((__u32)(x) & DESC_ADDR_MASK)
+ __u32 buf2;
+#define DESC_BUF2_EN (1UL << 31) /* Buffer 2 enable */
+ __u32 buflen;
+ __u32 misc;
+/* definitions for tx/rx descriptors */
+#define DESC_PKTLEN_SHIFT 16
+#define DESC_PKTLEN_MASK 0x7FF
+/* tx descriptor specific part */
+#define DESC_CSUM (1UL << 31) /* Append checksum */
+#define DESC_DSTPORT_SHIFT 8
+#define DESC_DSTPORT_MASK 0x3F
+#define DESC_VLAN_MASK 0x3F
+/* rx descriptor specific part */
+#define DESC_SRCPORT_SHIFT 12
+#define DESC_SRCPORT_MASK 0x7
+#define DESC_DA_MASK 0x3
+#define DESC_DA_SHIFT 4
+#define DESC_IPCSUM_FAIL (1UL << 3) /* IP checksum fail */
+#define DESC_VLAN_TAG (1UL << 2) /* VLAN tag present */
+#define DESC_TYPE_MASK 0x3 /* mask for Packet type */
+#define DESC_TYPE_IP 0x0 /* IP packet */
+#define DESC_TYPE_PPPoE 0x1 /* PPPoE packet */
+} __attribute__ ((aligned(16)));
+
+/* ------------------------------------------------------------------------ */
+
+static int adm5120_nrdevs;
+
+static struct net_device *adm5120_devs[SWITCH_NUM_PORTS];
+/* Lookup table port -> device */
+static struct net_device *adm5120_port[SWITCH_NUM_PORTS];
+
+static struct dma_desc *txl_descs;
+static struct dma_desc *rxl_descs;
+
+static dma_addr_t txl_descs_dma;
+static dma_addr_t rxl_descs_dma;
+
+static struct sk_buff **txl_skbuff;
+static struct sk_buff **rxl_skbuff;
+
+static unsigned int cur_rxl, dirty_rxl; /* producer/consumer ring indices */
+static unsigned int cur_txl, dirty_txl;
+
+static unsigned int sw_used;
+
+static spinlock_t tx_lock = SPIN_LOCK_UNLOCKED;
+
+/* ------------------------------------------------------------------------ */
+
+static inline u32 sw_read_reg(u32 reg)
+{
+ return __raw_readl((void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE)+reg);
+}
+
+static inline void sw_write_reg(u32 reg, u32 val)
+{
+ __raw_writel(val, (void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE)+reg);
+}
+
+static inline void sw_int_mask(u32 mask)
+{
+ u32 t;
+
+ t = sw_read_reg(SWITCH_REG_INT_MASK);
+ t |= mask;
+ sw_write_reg(SWITCH_REG_INT_MASK, t);
+}
+
+static inline void sw_int_unmask(u32 mask)
+{
+ u32 t;
+
+ t = sw_read_reg(SWITCH_REG_INT_MASK);
+ t &= ~mask;
+ sw_write_reg(SWITCH_REG_INT_MASK, t);
+}
+
+static inline void sw_int_ack(u32 mask)
+{
+ sw_write_reg(SWITCH_REG_INT_STATUS, mask);
+}
+
+static inline u32 sw_int_status(void)
+{
+ u32 t;
+
+ t = sw_read_reg(SWITCH_REG_INT_STATUS);
+ t &= ~sw_read_reg(SWITCH_REG_INT_MASK);
+ return t;
+}
+
+static inline u32 desc_get_srcport(struct dma_desc *desc)
+{
+ return (desc->misc >> DESC_SRCPORT_SHIFT) & DESC_SRCPORT_MASK;
+}
+
+static inline u32 desc_get_pktlen(struct dma_desc *desc)
+{
+ return (desc->misc >> DESC_PKTLEN_SHIFT) & DESC_PKTLEN_MASK;
+}
+
+static inline int desc_ipcsum_fail(struct dma_desc *desc)
+{
+ return ((desc->misc & DESC_IPCSUM_FAIL) != 0);
+}
+
+/* ------------------------------------------------------------------------ */
+
+static void sw_dump_desc(char *label, struct dma_desc *desc, int tx)
+{
+ u32 t;
+
+ SW_DBG("%s %s desc/%p\n", label, tx ? "tx" : "rx", desc);
+
+ t = desc->buf1;
+ SW_DBG(" buf1 %08X addr=%08X; len=%08X %s%s\n", t,
+ t & DESC_ADDR_MASK,
+ desc->buflen,
+ (t & DESC_OWN) ? "SWITCH" : "CPU",
+ (t & DESC_EOR) ? " RE" : "");
+
+ t = desc->buf2;
+ SW_DBG(" buf2 %08X addr=%08X%s\n", desc->buf2,
+ t & DESC_ADDR_MASK,
+ (t & DESC_BUF2_EN) ? " EN" : "" );
+
+ t = desc->misc;
+ if (tx)
+ SW_DBG(" misc %08X%s pktlen=%04X ports=%02X vlan=%02X\n", t,
+ (t & DESC_CSUM) ? " CSUM" : "",
+ (t >> DESC_PKTLEN_SHIFT) & DESC_PKTLEN_MASK,
+ (t >> DESC_DSTPORT_SHIFT) & DESC_DSTPORT_MASK,
+ t & DESC_VLAN_MASK);
+ else
+ SW_DBG(" misc %08X pktlen=%04X port=%d DA=%d%s%s type=%d\n",
+ t,
+ (t >> DESC_PKTLEN_SHIFT) & DESC_PKTLEN_MASK,
+ (t >> DESC_SRCPORT_SHIFT) & DESC_SRCPORT_MASK,
+ (t >> DESC_DA_SHIFT) & DESC_DA_MASK,
+ (t & DESC_IPCSUM_FAIL) ? " IPCF" : "",
+ (t & DESC_VLAN_TAG) ? " VLAN" : "",
+ (t & DESC_TYPE_MASK));
+}
+
+static void sw_dump_intr_mask(char *label, u32 mask)
+{
+ SW_DBG("%s %08X%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
+ label, mask,
+ (mask & SWITCH_INT_SHD) ? " SHD" : "",
+ (mask & SWITCH_INT_SLD) ? " SLD" : "",
+ (mask & SWITCH_INT_RHD) ? " RHD" : "",
+ (mask & SWITCH_INT_RLD) ? " RLD" : "",
+ (mask & SWITCH_INT_HDF) ? " HDF" : "",
+ (mask & SWITCH_INT_LDF) ? " LDF" : "",
+ (mask & SWITCH_INT_P0QF) ? " P0QF" : "",
+ (mask & SWITCH_INT_P1QF) ? " P1QF" : "",
+ (mask & SWITCH_INT_P2QF) ? " P2QF" : "",
+ (mask & SWITCH_INT_P3QF) ? " P3QF" : "",
+ (mask & SWITCH_INT_P4QF) ? " P4QF" : "",
+ (mask & SWITCH_INT_CPQF) ? " CPQF" : "",
+ (mask & SWITCH_INT_GQF) ? " GQF" : "",
+ (mask & SWITCH_INT_MD) ? " MD" : "",
+ (mask & SWITCH_INT_BCS) ? " BCS" : "",
+ (mask & SWITCH_INT_PSC) ? " PSC" : "",
+ (mask & SWITCH_INT_ID) ? " ID" : "",
+ (mask & SWITCH_INT_W0TE) ? " W0TE" : "",
+ (mask & SWITCH_INT_W1TE) ? " W1TE" : "",
+ (mask & SWITCH_INT_RDE) ? " RDE" : "",
+ (mask & SWITCH_INT_SDE) ? " SDE" : "",
+ (mask & SWITCH_INT_CPUH) ? " CPUH" : "");
+}
+
+static void sw_dump_regs(void)
+{
+ u32 t;
+
+ t = sw_read_reg(SWITCH_REG_PHY_STATUS);
+ SW_DBG("phy_status: %08X\n", t);
+
+ t = sw_read_reg(SWITCH_REG_CPUP_CONF);
+ SW_DBG("cpup_conf: %08X%s%s%s\n", t,
+ (t & CPUP_CONF_DCPUP) ? " DCPUP" : "",
+ (t & CPUP_CONF_CRCP) ? " CRCP" : "",
+ (t & CPUP_CONF_BTM) ? " BTM" : "");
+
+ t = sw_read_reg(SWITCH_REG_PORT_CONF0);
+ SW_DBG("port_conf0: %08X\n", t);
+ t = sw_read_reg(SWITCH_REG_PORT_CONF1);
+ SW_DBG("port_conf1: %08X\n", t);
+ t = sw_read_reg(SWITCH_REG_PORT_CONF2);
+ SW_DBG("port_conf2: %08X\n", t);
+
+ t = sw_read_reg(SWITCH_REG_VLAN_G1);
+ SW_DBG("vlan g1: %08X\n", t);
+ t = sw_read_reg(SWITCH_REG_VLAN_G2);
+ SW_DBG("vlan g2: %08X\n", t);
+
+ t = sw_read_reg(SWITCH_REG_BW_CNTL0);
+ SW_DBG("bw_cntl0: %08X\n", t);
+ t = sw_read_reg(SWITCH_REG_BW_CNTL1);
+ SW_DBG("bw_cntl1: %08X\n", t);
+
+ t = sw_read_reg(SWITCH_REG_PHY_CNTL0);
+ SW_DBG("phy_cntl0: %08X\n", t);
+ t = sw_read_reg(SWITCH_REG_PHY_CNTL1);
+ SW_DBG("phy_cntl1: %08X\n", t);
+ t = sw_read_reg(SWITCH_REG_PHY_CNTL2);
+ SW_DBG("phy_cntl2: %08X\n", t);
+ t = sw_read_reg(SWITCH_REG_PHY_CNTL3);
+ SW_DBG("phy_cntl3: %08X\n", t);
+ t = sw_read_reg(SWITCH_REG_PHY_CNTL4);
+ SW_DBG("phy_cntl4: %08X\n", t);
+
+ t = sw_read_reg(SWITCH_REG_INT_STATUS);
+ sw_dump_intr_mask("int_status: ", t);
+
+ t = sw_read_reg(SWITCH_REG_INT_MASK);
+ sw_dump_intr_mask("int_mask: ", t);
+
+ t = sw_read_reg(SWITCH_REG_SHDA);
+ SW_DBG("shda: %08X\n", t);
+ t = sw_read_reg(SWITCH_REG_SLDA);
+ SW_DBG("slda: %08X\n", t);
+ t = sw_read_reg(SWITCH_REG_RHDA);
+ SW_DBG("rhda: %08X\n", t);
+ t = sw_read_reg(SWITCH_REG_RLDA);
+ SW_DBG("rlda: %08X\n", t);
+}
+
+/* ------------------------------------------------------------------------ */
+
+static inline void adm5120_rx_dma_update(struct dma_desc *desc,
+ struct sk_buff *skb, int end)
+{
+ desc->misc = 0;
+ desc->buf2 = 0;
+ desc->buflen = RX_MAX_PKTLEN;
+ desc->buf1 = DESC_ADDR(skb->data) |
+ DESC_OWN | (end ? DESC_EOR : 0);
+}
+
+static void adm5120_switch_rx_refill(void)
+{
+ unsigned int entry;
+
+ for (; cur_rxl - dirty_rxl > 0; dirty_rxl++) {
+ struct dma_desc *desc;
+ struct sk_buff *skb;
+
+ entry = dirty_rxl % RX_RING_SIZE;
+ desc = &rxl_descs[entry];
+
+ skb = rxl_skbuff[entry];
+ if (skb == NULL) {
+ skb = alloc_skb(SKB_ALLOC_LEN, GFP_ATOMIC);
+ if (skb) {
+ skb_reserve(skb, SKB_RESERVE_LEN);
+ rxl_skbuff[entry] = skb;
+ } else {
+ SW_ERR("no memory for skb\n");
+ desc->buflen = 0;
+ desc->buf2 = 0;
+ desc->misc = 0;
+ desc->buf1 = (desc->buf1 & DESC_EOR) | DESC_OWN;
+ break;
+ }
+ }
+
+ desc->buf2 = 0;
+ desc->buflen = RX_MAX_PKTLEN;
+ desc->misc = 0;
+ desc->buf1 = (desc->buf1 & DESC_EOR) | DESC_OWN |
+ DESC_ADDR(skb->data);
+ }
+}
+
+static int adm5120_switch_rx(int limit)
+{
+ unsigned int done = 0;
+
+ SW_DBG("rx start, limit=%d, cur_rxl=%u, dirty_rxl=%u\n",
+ limit, cur_rxl, dirty_rxl);
+
+ while (done < limit) {
+ int entry = cur_rxl % RX_RING_SIZE;
+ struct dma_desc *desc = &rxl_descs[entry];
+ struct net_device *rdev;
+ unsigned int port;
+
+ if (desc->buf1 & DESC_OWN)
+ break;
+
+ if (dirty_rxl + RX_RING_SIZE == cur_rxl)
+ break;
+
+ port = desc_get_srcport(desc);
+ rdev = adm5120_port[port];
+
+ SW_DBG("rx descriptor %u, desc=%p, skb=%p\n", entry, desc,
+ rxl_skbuff[entry]);
+
+ if ((rdev) && netif_running(rdev)) {
+ struct sk_buff *skb = rxl_skbuff[entry];
+ int pktlen;
+
+ pktlen = desc_get_pktlen(desc);
+ pktlen -= ETH_CSUM_LEN;
+
+ if ((pktlen == 0) || desc_ipcsum_fail(desc)) {
+ rdev->stats.rx_errors++;
+ if (pktlen == 0)
+ rdev->stats.rx_length_errors++;
+ if (desc_ipcsum_fail(desc))
+ rdev->stats.rx_crc_errors++;
+ SW_DBG("rx error, recycling skb %u\n", entry);
+ } else {
+ skb_put(skb, pktlen);
+
+ skb->dev = rdev;
+ skb->protocol = eth_type_trans(skb, rdev);
+ skb->ip_summed = CHECKSUM_UNNECESSARY;
+
+ dma_cache_wback_inv((unsigned long)skb->data,
+ skb->len);
+
+#ifdef CONFIG_ADM5120_SWITCH_NAPI
+ netif_receive_skb(skb);
+#else
+ netif_rx(skb);
+#endif
+
+ rdev->last_rx = jiffies;
+ rdev->stats.rx_packets++;
+ rdev->stats.rx_bytes += pktlen;
+
+ rxl_skbuff[entry] = NULL;
+ done++;
+ }
+ } else {
+ SW_DBG("no rx device, recycling skb %u\n", entry);
+ }
+
+ cur_rxl++;
+ if (cur_rxl - dirty_rxl > RX_RING_SIZE / 4)
+ adm5120_switch_rx_refill();
+ }
+
+ adm5120_switch_rx_refill();
+
+ SW_DBG("rx finished, cur_rxl=%u, dirty_rxl=%u, processed %d\n",
+ cur_rxl, dirty_rxl, done);
+
+ return done;
+}
+
+static void adm5120_switch_tx(void)
+{
+ unsigned int entry;
+
+ spin_lock(&tx_lock);
+ entry = dirty_txl % TX_RING_SIZE;
+ while (dirty_txl != cur_txl) {
+ struct dma_desc *desc = &txl_descs[entry];
+ struct sk_buff *skb = txl_skbuff[entry];
+
+ if (desc->buf1 & DESC_OWN)
+ break;
+
+ if (netif_running(skb->dev)) {
+ skb->dev->stats.tx_bytes += skb->len;
+ skb->dev->stats.tx_packets++;
+ }
+
+ dev_kfree_skb_irq(skb);
+ txl_skbuff[entry] = NULL;
+ entry = (++dirty_txl) % TX_RING_SIZE;
+ }
+
+ if ((cur_txl - dirty_txl) < TX_QUEUE_LEN - 4) {
+ int i;
+ for (i = 0; i < SWITCH_NUM_PORTS; i++) {
+ if (!adm5120_devs[i])
+ continue;
+ netif_wake_queue(adm5120_devs[i]);
+ }
+ }
+ spin_unlock(&tx_lock);
+}
+
+#ifdef CONFIG_ADM5120_SWITCH_NAPI
+static int adm5120_if_poll(struct napi_struct *napi, int limit)
+{
+ struct adm5120_if_priv *priv = container_of(napi,
+ struct adm5120_if_priv, napi);
+ struct net_device *dev = priv->dev;
+ int done;
+ u32 status;
+
+ sw_int_ack(SWITCH_INTS_POLL);
+
+ SW_DBG("%s: processing TX ring\n", dev->name);
+ adm5120_switch_tx();
+
+ SW_DBG("%s: processing RX ring\n", dev->name);
+ done = adm5120_switch_rx(limit);
+
+ status = sw_int_status() & SWITCH_INTS_POLL;
+ if ((done < limit) && (!status)) {
+ SW_DBG("disable polling mode for %s\n", dev->name);
+ netif_rx_complete(dev, napi);
+ sw_int_unmask(SWITCH_INTS_POLL);
+ return 0;
+ }
+
+ SW_DBG("%s still in polling mode, done=%d, status=%x\n",
+ dev->name, done, status);
+ return 1;
+}
+#endif /* CONFIG_ADM5120_SWITCH_NAPI */
+
+
+static irqreturn_t adm5120_switch_irq(int irq, void *dev_id)
+{
+ u32 status;
+
+ status = sw_int_status();
+ status &= SWITCH_INTS_ALL;
+ if (!status)
+ return IRQ_NONE;
+
+#ifdef CONFIG_ADM5120_SWITCH_NAPI
+ sw_int_ack(status & ~SWITCH_INTS_POLL);
+
+ if (status & SWITCH_INTS_POLL) {
+ struct net_device *dev = dev_id;
+ struct adm5120_if_priv *priv = netdev_priv(dev);
+
+ sw_dump_intr_mask("poll ints", status);
+ SW_DBG("enable polling mode for %s\n", dev->name);
+ sw_int_mask(SWITCH_INTS_POLL);
+ netif_rx_schedule(dev, &priv->napi);
+ }
+#else
+ sw_int_ack(status);
+
+ if (status & (SWITCH_INT_RLD | SWITCH_INT_LDF)) {
+ adm5120_switch_rx(RX_RING_SIZE);
+ }
+
+ if (status & SWITCH_INT_SLD) {
+ adm5120_switch_tx();
+ }
+#endif
+
+ return IRQ_HANDLED;
+}
+
+static void adm5120_set_bw(char *matrix)
+{
+ unsigned long val;
+
+ /* Port 0 to 3 are set using the bandwidth control 0 register */
+ val = matrix[0] + (matrix[1]<<8) + (matrix[2]<<16) + (matrix[3]<<24);
+ sw_write_reg(SWITCH_REG_BW_CNTL0, val);
+
+ /* Port 4 and 5 are set using the bandwidth control 1 register */
+ val = matrix[4];
+ if (matrix[5] == 1)
+ sw_write_reg(SWITCH_REG_BW_CNTL1, val | 0x80000000);
+ else
+ sw_write_reg(SWITCH_REG_BW_CNTL1, val & ~0x8000000);
+
+ SW_DBG("D: ctl0 0x%ux, ctl1 0x%ux\n", sw_read_reg(SWITCH_REG_BW_CNTL0),
+ sw_read_reg(SWITCH_REG_BW_CNTL1));
+}
+
+static void adm5120_switch_tx_ring_reset(struct dma_desc *desc,
+ struct sk_buff **skbl, int num)
+{
+ memset(desc, 0, num * sizeof(*desc));
+ desc[num-1].buf1 |= DESC_EOR;
+ memset(skbl, 0, sizeof(struct skb*)*num);
+
+ cur_txl = 0;
+ dirty_txl = 0;
+}
+
+static void adm5120_switch_rx_ring_reset(struct dma_desc *desc,
+ struct sk_buff **skbl, int num)
+{
+ int i;
+
+ memset(desc, 0, num * sizeof(*desc));
+ for (i = 0; i < num; i++) {
+ skbl[i] = dev_alloc_skb(SKB_ALLOC_LEN);
+ if (!skbl[i]) {
+ i = num;
+ break;
+ }
+ skb_reserve(skbl[i], SKB_RESERVE_LEN);
+ adm5120_rx_dma_update(&desc[i], skbl[i], (num-1==i));
+ }
+
+ cur_rxl = 0;
+ dirty_rxl = 0;
+}
+
+static int adm5120_switch_tx_ring_alloc(void)
+{
+ int err;
+
+ txl_descs = dma_alloc_coherent(NULL, TX_DESCS_SIZE, &txl_descs_dma,
+ GFP_ATOMIC);
+ if (!txl_descs) {
+ err = -ENOMEM;
+ goto err;
+ }
+
+ txl_skbuff = kzalloc(TX_SKBS_SIZE, GFP_KERNEL);
+ if (!txl_skbuff) {
+ err = -ENOMEM;
+ goto err;
+ }
+
+ return 0;
+
+err:
+ return err;
+}
+
+static void adm5120_switch_tx_ring_free(void)
+{
+ int i;
+
+ if (txl_skbuff) {
+ for (i = 0; i < TX_RING_SIZE; i++)
+ if (txl_skbuff[i])
+ kfree_skb(txl_skbuff[i]);
+ kfree(txl_skbuff);
+ }
+
+ if (txl_descs)
+ dma_free_coherent(NULL, TX_DESCS_SIZE, txl_descs,
+ txl_descs_dma);
+}
+
+static int adm5120_switch_rx_ring_alloc(void)
+{
+ int err;
+ int i;
+
+ /* init RX ring */
+ rxl_descs = dma_alloc_coherent(NULL, RX_DESCS_SIZE, &rxl_descs_dma,
+ GFP_ATOMIC);
+ if (!rxl_descs) {
+ err = -ENOMEM;
+ goto err;
+ }
+
+ rxl_skbuff = kzalloc(RX_SKBS_SIZE, GFP_KERNEL);
+ if (!rxl_skbuff) {
+ err = -ENOMEM;
+ goto err;
+ }
+
+ for (i = 0; i < RX_RING_SIZE; i++) {
+ struct sk_buff *skb;
+ skb = alloc_skb(SKB_ALLOC_LEN, GFP_ATOMIC);
+ if (!skb) {
+ err = -ENOMEM;
+ goto err;
+ }
+ rxl_skbuff[i] = skb;
+ skb_reserve(skb, SKB_RESERVE_LEN);
+ }
+
+ return 0;
+
+err:
+ return err;
+}
+
+static void adm5120_switch_rx_ring_free(void)
+{
+ int i;
+
+ if (rxl_skbuff) {
+ for (i = 0; i < RX_RING_SIZE; i++)
+ if (rxl_skbuff[i])
+ kfree_skb(rxl_skbuff[i]);
+ kfree(rxl_skbuff);
+ }
+
+ if (rxl_descs)
+ dma_free_coherent(NULL, RX_DESCS_SIZE, rxl_descs,
+ rxl_descs_dma);
+}
+
+static void adm5120_write_mac(struct net_device *dev)
+{
+ struct adm5120_if_priv *priv = netdev_priv(dev);
+ unsigned char *mac = dev->dev_addr;
+ u32 t;
+
+ t = mac[2] | (mac[3] << MAC_WT1_MAC3_SHIFT) |
+ (mac[4] << MAC_WT1_MAC4_SHIFT) | (mac[5] << MAC_WT1_MAC5_SHIFT);
+ sw_write_reg(SWITCH_REG_MAC_WT1, t);
+
+ t = (mac[0] << MAC_WT0_MAC0_SHIFT) | (mac[1] << MAC_WT0_MAC1_SHIFT) |
+ MAC_WT0_MAWC | MAC_WT0_WVE | (priv->vlan_no<<3);
+
+ sw_write_reg(SWITCH_REG_MAC_WT0, t);
+
+ while (!(sw_read_reg(SWITCH_REG_MAC_WT0) & MAC_WT0_MWD));
+}
+
+static void adm5120_set_vlan(char *matrix)
+{
+ unsigned long val;
+ int vlan_port, port;
+
+ val = matrix[0] + (matrix[1]<<8) + (matrix[2]<<16) + (matrix[3]<<24);
+ sw_write_reg(SWITCH_REG_VLAN_G1, val);
+ val = matrix[4] + (matrix[5]<<8);
+ sw_write_reg(SWITCH_REG_VLAN_G2, val);
+
+ /* Now set/update the port vs. device lookup table */
+ for (port=0; port<SWITCH_NUM_PORTS; port++) {
+ for (vlan_port=0; vlan_port<SWITCH_NUM_PORTS && !(matrix[vlan_port] & (0x00000001 << port)); vlan_port++);
+ if (vlan_port <SWITCH_NUM_PORTS)
+ adm5120_port[port] = adm5120_devs[vlan_port];
+ else
+ adm5120_port[port] = NULL;
+ }
+}
+
+static void adm5120_switch_set_vlan_mac(unsigned int vlan, unsigned char *mac)
+{
+ u32 t;
+
+ t = mac[2] | (mac[3] << MAC_WT1_MAC3_SHIFT)
+ | (mac[4] << MAC_WT1_MAC4_SHIFT)
+ | (mac[5] << MAC_WT1_MAC5_SHIFT);
+ sw_write_reg(SWITCH_REG_MAC_WT1, t);
+
+ t = (mac[0] << MAC_WT0_MAC0_SHIFT) | (mac[1] << MAC_WT0_MAC1_SHIFT) |
+ MAC_WT0_MAWC | MAC_WT0_WVE | (vlan << MAC_WT0_WVN_SHIFT) |
+ (MAC_WT0_WAF_STATIC << MAC_WT0_WAF_SHIFT);
+ sw_write_reg(SWITCH_REG_MAC_WT0, t);
+
+ do {
+ t = sw_read_reg(SWITCH_REG_MAC_WT0);
+ } while ((t & MAC_WT0_MWD) == 0);
+}
+
+static void adm5120_switch_set_vlan_ports(unsigned int vlan, u32 ports)
+{
+ unsigned int reg;
+ u32 t;
+
+ if (vlan < 4)
+ reg = SWITCH_REG_VLAN_G1;
+ else {
+ vlan -= 4;
+ reg = SWITCH_REG_VLAN_G2;
+ }
+
+ t = sw_read_reg(reg);
+ t &= ~(0xFF << (vlan*8));
+ t |= (ports << (vlan*8));
+ sw_write_reg(reg, t);
+}
+
+/* ------------------------------------------------------------------------ */
+
+#ifdef CONFIG_ADM5120_SWITCH_NAPI
+static inline void adm5120_if_napi_enable(struct net_device *dev)
+{
+ struct adm5120_if_priv *priv = netdev_priv(dev);
+ napi_enable(&priv->napi);
+}
+
+static inline void adm5120_if_napi_disable(struct net_device *dev)
+{
+ struct adm5120_if_priv *priv = netdev_priv(dev);
+ napi_disable(&priv->napi);
+}
+#else
+static inline void adm5120_if_napi_enable(struct net_device *dev) {}
+static inline void adm5120_if_napi_disable(struct net_device *dev) {}
+#endif /* CONFIG_ADM5120_SWITCH_NAPI */
+
+static int adm5120_if_open(struct net_device *dev)
+{
+ u32 t;
+ int err;
+ int i;
+
+ adm5120_if_napi_enable(dev);
+
+ err = request_irq(dev->irq, adm5120_switch_irq,
+ (IRQF_SHARED | IRQF_DISABLED), dev->name, dev);
+ if (err) {
+ SW_ERR("unable to get irq for %s\n", dev->name);
+ goto err;
+ }
+
+ if (!sw_used++)
+ /* enable interrupts on first open */
+ sw_int_unmask(SWITCH_INTS_USED);
+
+ /* enable (additional) port */
+ t = sw_read_reg(SWITCH_REG_PORT_CONF0);
+ for (i = 0; i < SWITCH_NUM_PORTS; i++) {
+ if (dev == adm5120_devs[i])
+ t &= ~adm5120_eth_vlans[i];
+ }
+ sw_write_reg(SWITCH_REG_PORT_CONF0, t);
+
+ netif_start_queue(dev);
+
+ return 0;
+
+err:
+ adm5120_if_napi_disable(dev);
+ return err;
+}
+
+static int adm5120_if_stop(struct net_device *dev)
+{
+ u32 t;
+ int i;
+
+ netif_stop_queue(dev);
+ adm5120_if_napi_disable(dev);
+
+ /* disable port if not assigned to other devices */
+ t = sw_read_reg(SWITCH_REG_PORT_CONF0);
+ t |= SWITCH_PORTS_NOCPU;
+ for (i = 0; i < SWITCH_NUM_PORTS; i++) {
+ if ((dev != adm5120_devs[i]) && netif_running(adm5120_devs[i]))
+ t &= ~adm5120_eth_vlans[i];
+ }
+ sw_write_reg(SWITCH_REG_PORT_CONF0, t);
+
+ if (!--sw_used)
+ sw_int_mask(SWITCH_INTS_USED);
+
+ free_irq(dev->irq, dev);
+
+ return 0;
+}
+
+static int adm5120_if_hard_start_xmit(struct sk_buff *skb,
+ struct net_device *dev)
+{
+ struct dma_desc *desc;
+ struct adm5120_if_priv *priv = netdev_priv(dev);
+ unsigned int entry;
+ unsigned long data;
+ int i;
+
+ /* lock switch irq */
+ spin_lock_irq(&tx_lock);
+
+ /* calculate the next TX descriptor entry. */
+ entry = cur_txl % TX_RING_SIZE;
+
+ desc = &txl_descs[entry];
+ if (desc->buf1 & DESC_OWN) {
+ /* We want to write a packet but the TX queue is still
+ * occupied by the DMA. We are faster than the DMA... */
+ SW_DBG("%s unable to transmit, packet dopped\n", dev->name);
+ dev_kfree_skb(skb);
+ dev->stats.tx_dropped++;
+ return 0;
+ }
+
+ txl_skbuff[entry] = skb;
+ data = (desc->buf1 & DESC_EOR);
+ data |= DESC_ADDR(skb->data);
+
+ desc->misc =
+ ((skb->len<ETH_ZLEN?ETH_ZLEN:skb->len) << DESC_PKTLEN_SHIFT) |
+ (0x1 << priv->vlan_no);
+
+ desc->buflen = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
+
+ desc->buf1 = data | DESC_OWN;
+ sw_write_reg(SWITCH_REG_SEND_TRIG, SEND_TRIG_STL);
+
+ cur_txl++;
+ if (cur_txl == dirty_txl + TX_QUEUE_LEN) {
+ for (i = 0; i < SWITCH_NUM_PORTS; i++) {
+ if (!adm5120_devs[i])
+ continue;
+ netif_stop_queue(adm5120_devs[i]);
+ }
+ }
+
+ dev->trans_start = jiffies;
+
+ spin_unlock_irq(&tx_lock);
+
+ return 0;
+}
+
+static void adm5120_if_tx_timeout(struct net_device *dev)
+{
+ SW_INFO("TX timeout on %s\n",dev->name);
+}
+
+static void adm5120_if_set_multicast_list(struct net_device *dev)
+{
+ struct adm5120_if_priv *priv = netdev_priv(dev);
+ u32 ports;
+ u32 t;
+
+ ports = adm5120_eth_vlans[priv->vlan_no] & SWITCH_PORTS_NOCPU;
+
+ t = sw_read_reg(SWITCH_REG_CPUP_CONF);
+ if (dev->flags & IFF_PROMISC)
+ /* enable unknown packets */
+ t &= ~(ports << CPUP_CONF_DUNP_SHIFT);
+ else
+ /* disable unknown packets */
+ t |= (ports << CPUP_CONF_DUNP_SHIFT);
+
+ if (dev->flags & IFF_PROMISC || dev->flags & IFF_ALLMULTI ||
+ dev->mc_count)
+ /* enable multicast packets */
+ t &= ~(ports << CPUP_CONF_DMCP_SHIFT);
+ else
+ /* disable multicast packets */
+ t |= (ports << CPUP_CONF_DMCP_SHIFT);
+
+ /* If there is any port configured to be in promiscuous mode, then the */
+ /* Bridge Test Mode has to be activated. This will result in */
+ /* transporting also packets learned in another VLAN to be forwarded */
+ /* to the CPU. */
+ /* The difficult scenario is when we want to build a bridge on the CPU.*/
+ /* Assume we have port0 and the CPU port in VLAN0 and port1 and the */
+ /* CPU port in VLAN1. Now we build a bridge on the CPU between */
+ /* VLAN0 and VLAN1. Both ports of the VLANs are set in promisc mode. */
+ /* Now assume a packet with ethernet source address 99 enters port 0 */
+ /* It will be forwarded to the CPU because it is unknown. Then the */
+ /* bridge in the CPU will send it to VLAN1 and it goes out at port 1. */
+ /* When now a packet with ethernet destination address 99 comes in at */
+ /* port 1 in VLAN1, then the switch has learned that this address is */
+ /* located at port 0 in VLAN0. Therefore the switch will drop */
+ /* this packet. In order to avoid this and to send the packet still */
+ /* to the CPU, the Bridge Test Mode has to be activated. */
+
+ /* Check if there is any vlan in promisc mode. */
+ if (t & (SWITCH_PORTS_NOCPU << CPUP_CONF_DUNP_SHIFT))
+ t &= ~CPUP_CONF_BTM; /* Disable Bridge Testing Mode */
+ else
+ t |= CPUP_CONF_BTM; /* Enable Bridge Testing Mode */
+
+ sw_write_reg(SWITCH_REG_CPUP_CONF, t);
+
+}
+
+static int adm5120_if_set_mac_address(struct net_device *dev, void *p)
+{
+ struct sockaddr *addr = p;
+
+ memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
+ adm5120_write_mac(dev);
+ return 0;
+}
+
+static int adm5120_if_do_ioctl(struct net_device *dev, struct ifreq *rq,
+ int cmd)
+{
+ int err;
+ struct adm5120_sw_info info;
+ struct adm5120_if_priv *priv = netdev_priv(dev);
+
+ switch(cmd) {
+ case SIOCGADMINFO:
+ info.magic = 0x5120;
+ info.ports = adm5120_nrdevs;
+ info.vlan = priv->vlan_no;
+ err = copy_to_user(rq->ifr_data, &info, sizeof(info));
+ if (err)
+ return -EFAULT;
+ break;
+ case SIOCSMATRIX:
+ if (!capable(CAP_NET_ADMIN))
+ return -EPERM;
+ err = copy_from_user(adm5120_eth_vlans, rq->ifr_data,
+ sizeof(adm5120_eth_vlans));
+ if (err)
+ return -EFAULT;
+ adm5120_set_vlan(adm5120_eth_vlans);
+ break;
+ case SIOCGMATRIX:
+ err = copy_to_user(rq->ifr_data, adm5120_eth_vlans,
+ sizeof(adm5120_eth_vlans));
+ if (err)
+ return -EFAULT;
+ break;
+ default:
+ return -EOPNOTSUPP;
+ }
+ return 0;
+}
+
+static struct net_device *adm5120_if_alloc(void)
+{
+ struct net_device *dev;
+ struct adm5120_if_priv *priv;
+
+ dev = alloc_etherdev(sizeof(*priv));
+ if (!dev)
+ return NULL;
+
+ priv = netdev_priv(dev);
+ priv->dev = dev;
+
+ dev->irq = ADM5120_IRQ_SWITCH;
+ dev->open = adm5120_if_open;
+ dev->hard_start_xmit = adm5120_if_hard_start_xmit;
+ dev->stop = adm5120_if_stop;
+ dev->set_multicast_list = adm5120_if_set_multicast_list;
+ dev->do_ioctl = adm5120_if_do_ioctl;
+ dev->tx_timeout = adm5120_if_tx_timeout;
+ dev->watchdog_timeo = TX_TIMEOUT;
+ dev->set_mac_address = adm5120_if_set_mac_address;
+
+#ifdef CONFIG_ADM5120_SWITCH_NAPI
+ netif_napi_add(dev, &priv->napi, adm5120_if_poll, 64);
+#endif
+
+ return dev;
+}
+
+/* ------------------------------------------------------------------------ */
+
+static void adm5120_switch_cleanup(void)
+{
+ int i;
+
+ /* disable interrupts */
+ sw_int_mask(SWITCH_INTS_ALL);
+
+ for (i = 0; i < SWITCH_NUM_PORTS; i++) {
+ struct net_device *dev = adm5120_devs[i];
+ if (dev) {
+ unregister_netdev(dev);
+ free_netdev(dev);
+ }
+ }
+
+ adm5120_switch_tx_ring_free();
+ adm5120_switch_rx_ring_free();
+}
+
+static int __init adm5120_switch_probe(struct platform_device *pdev)
+{
+ u32 t;
+ int i, err;
+
+ adm5120_nrdevs = adm5120_eth_num_ports;
+
+ t = CPUP_CONF_DCPUP | CPUP_CONF_CRCP |
+ SWITCH_PORTS_NOCPU << CPUP_CONF_DUNP_SHIFT |
+ SWITCH_PORTS_NOCPU << CPUP_CONF_DMCP_SHIFT ;
+ sw_write_reg(SWITCH_REG_CPUP_CONF, t);
+
+ t = (SWITCH_PORTS_NOCPU << PORT_CONF0_EMCP_SHIFT) |
+ (SWITCH_PORTS_NOCPU << PORT_CONF0_BP_SHIFT) |
+ (SWITCH_PORTS_NOCPU);
+ sw_write_reg(SWITCH_REG_PORT_CONF0, t);
+
+ /* setup ports to Autoneg/100M/Full duplex/Auto MDIX */
+ t = SWITCH_PORTS_PHY |
+ (SWITCH_PORTS_PHY << PHY_CNTL2_SC_SHIFT) |
+ (SWITCH_PORTS_PHY << PHY_CNTL2_DC_SHIFT) |
+ (SWITCH_PORTS_PHY << PHY_CNTL2_PHYR_SHIFT) |
+ (SWITCH_PORTS_PHY << PHY_CNTL2_AMDIX_SHIFT) |
+ PHY_CNTL2_RMAE;
+ sw_write_reg(SWITCH_REG_PHY_CNTL2, t);
+
+ t = sw_read_reg(SWITCH_REG_PHY_CNTL3);
+ t |= PHY_CNTL3_RNT;
+ sw_write_reg(SWITCH_REG_PHY_CNTL3, t);
+
+ /* Force all the packets from all ports are low priority */
+ sw_write_reg(SWITCH_REG_PRI_CNTL, 0);
+
+ sw_int_mask(SWITCH_INTS_ALL);
+ sw_int_ack(SWITCH_INTS_ALL);
+
+ err = adm5120_switch_rx_ring_alloc();
+ if (err)
+ goto err;
+
+ err = adm5120_switch_tx_ring_alloc();
+ if (err)
+ goto err;
+
+ adm5120_switch_tx_ring_reset(txl_descs, txl_skbuff, TX_RING_SIZE);
+ adm5120_switch_rx_ring_reset(rxl_descs, rxl_skbuff, RX_RING_SIZE);
+
+ sw_write_reg(SWITCH_REG_SHDA, 0);
+ sw_write_reg(SWITCH_REG_SLDA, KSEG1ADDR(txl_descs));
+ sw_write_reg(SWITCH_REG_RHDA, 0);
+ sw_write_reg(SWITCH_REG_RLDA, KSEG1ADDR(rxl_descs));
+
+ for (i = 0; i < SWITCH_NUM_PORTS; i++) {
+ struct net_device *dev;
+ struct adm5120_if_priv *priv;
+
+ dev = adm5120_if_alloc();
+ if (!dev) {
+ err = -ENOMEM;
+ goto err;
+ }
+
+ adm5120_devs[i] = dev;
+ priv = netdev_priv(dev);
+
+ priv->vlan_no = i;
+ priv->port_mask = adm5120_eth_vlans[i];
+
+ memcpy(dev->dev_addr, adm5120_eth_macs[i], 6);
+ adm5120_write_mac(dev);
+
+ err = register_netdev(dev);
+ if (err) {
+ SW_INFO("%s register failed, error=%d\n",
+ dev->name, err);
+ goto err;
+ }
+ }
+
+ /* setup vlan/port mapping after devs are filled up */
+ adm5120_set_vlan(adm5120_eth_vlans);
+
+ /* enable CPU port */
+ t = sw_read_reg(SWITCH_REG_CPUP_CONF);
+ t &= ~CPUP_CONF_DCPUP;
+ sw_write_reg(SWITCH_REG_CPUP_CONF, t);
+
+ return 0;
+
+err:
+ adm5120_switch_cleanup();
+
+ SW_ERR("init failed\n");
+ return err;
+}
+
+static int adm5120_switch_remove(struct platform_device *dev)
+{
+ adm5120_switch_cleanup();
+ return 0;
+}
+
+static struct platform_driver adm5120_switch_driver = {
+ .probe = adm5120_switch_probe,
+ .remove = adm5120_switch_remove,
+ .driver = {
+ .name = DRV_NAME,
+ },
+};
+
+/* -------------------------------------------------------------------------- */
+
+static int __init adm5120_switch_mod_init(void)
+{
+ int err;
+
+ pr_info(DRV_DESC " version " DRV_VERSION "\n");
+ err = platform_driver_register(&adm5120_switch_driver);
+
+ return err;
+}
+
+static void __exit adm5120_switch_mod_exit(void)
+{
+ platform_driver_unregister(&adm5120_switch_driver);
+}
+
+module_init(adm5120_switch_mod_init);
+module_exit(adm5120_switch_mod_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
+MODULE_DESCRIPTION(DRV_DESC);
+MODULE_VERSION(DRV_VERSION);
--- /dev/null
+/*
+ * Defines for ADM5120 built in ethernet switch driver
+ *
+ * Copyright Jeroen Vreeken (pe1rxq@amsat.org), 2005
+ *
+ * Values come from ADM5120 datasheet and original ADMtek 2.4 driver,
+ * Copyright ADMtek Inc.
+ */
+
+#ifndef _INCLUDE_ADM5120SW_H_
+#define _INCLUDE_ADM5120SW_H_
+
+#define SIOCSMATRIX SIOCDEVPRIVATE
+#define SIOCGMATRIX SIOCDEVPRIVATE+1
+#define SIOCGADMINFO SIOCDEVPRIVATE+2
+
+struct adm5120_sw_info {
+ u16 magic;
+ u16 ports;
+ u16 vlan;
+};
+
+#endif /* _INCLUDE_ADM5120SW_H_ */
--- /dev/null
+/*
+ * ADM5120 HCD (Host Controller Driver) for USB
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This file was derived from: drivers/usb/host/ohci-dbg.c
+ * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
+ * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+/*-------------------------------------------------------------------------*/
+
+static inline char *ed_typestring(int ed_type)
+{
+ switch (ed_type) {
+ case PIPE_CONTROL:
+ return "ctrl";
+ case PIPE_BULK:
+ return "bulk";
+ case PIPE_INTERRUPT:
+ return "intr";
+ case PIPE_ISOCHRONOUS:
+ return "isoc";
+ }
+ return "(bad ed_type)";
+}
+
+static inline char *ed_statestring(int state)
+{
+ switch (state) {
+ case ED_IDLE:
+ return "IDLE";
+ case ED_UNLINK:
+ return "UNLINK";
+ case ED_OPER:
+ return "OPER";
+ }
+ return "?STATE";
+}
+
+static inline char *pipestring(int pipe)
+{
+ return ed_typestring(usb_pipetype(pipe));
+}
+
+static inline char *td_pidstring(u32 info)
+{
+ switch (info & TD_DP) {
+ case TD_DP_SETUP:
+ return "SETUP";
+ case TD_DP_IN:
+ return "IN";
+ case TD_DP_OUT:
+ return "OUT";
+ }
+ return "?PID";
+}
+
+static inline char *td_togglestring(u32 info)
+{
+ switch (info & TD_T) {
+ case TD_T_DATA0:
+ return "DATA0";
+ case TD_T_DATA1:
+ return "DATA1";
+ case TD_T_CARRY:
+ return "CARRY";
+ }
+ return "?TOGGLE";
+}
+
+/*-------------------------------------------------------------------------*/
+
+#ifdef DEBUG
+
+/* debug| print the main components of an URB
+ * small: 0) header + data packets 1) just header
+ */
+static void __attribute__((unused))
+urb_print(struct admhcd *ahcd, struct urb *urb, char *str, int small, int status)
+{
+ unsigned int pipe = urb->pipe;
+
+ if (!urb->dev || !urb->dev->bus) {
+ admhc_dbg(ahcd, "%s URB: no dev", str);
+ return;
+ }
+
+#ifndef ADMHC_VERBOSE_DEBUG
+ if (status != 0)
+#endif
+ admhc_dbg(ahcd, "URB-%s %p dev=%d ep=%d%s-%s flags=%x len=%d/%d "
+ "stat=%d\n",
+ str,
+ urb,
+ usb_pipedevice (pipe),
+ usb_pipeendpoint (pipe),
+ usb_pipeout(pipe)? "out" : "in",
+ pipestring(pipe),
+ urb->transfer_flags,
+ urb->actual_length,
+ urb->transfer_buffer_length,
+ status);
+
+#ifdef ADMHC_VERBOSE_DEBUG
+ if (!small) {
+ int i, len;
+
+ if (usb_pipecontrol(pipe)) {
+ admhc_dbg(ahcd, "setup(8):");
+ for (i = 0; i < 8 ; i++)
+ printk (" %02x", ((__u8 *) urb->setup_packet) [i]);
+ printk ("\n");
+ }
+ if (urb->transfer_buffer_length > 0 && urb->transfer_buffer) {
+ admhc_dbg(ahcd, "data(%d/%d):",
+ urb->actual_length,
+ urb->transfer_buffer_length);
+ len = usb_pipeout(pipe)?
+ urb->transfer_buffer_length: urb->actual_length;
+ for (i = 0; i < 16 && i < len; i++)
+ printk(" %02x", ((__u8 *)urb->transfer_buffer)[i]);
+ printk("%s stat:%d\n", i < len? "...": "", status);
+ }
+ }
+#endif /* ADMHC_VERBOSE_DEBUG */
+}
+
+#define admhc_dbg_sw(ahcd, next, size, format, arg...) \
+ do { \
+ if (next) { \
+ unsigned s_len; \
+ s_len = scnprintf(*next, *size, format, ## arg ); \
+ *size -= s_len; *next += s_len; \
+ } else \
+ admhc_dbg(ahcd,format, ## arg ); \
+ } while (0);
+
+
+static void admhc_dump_intr_mask(struct admhcd *ahcd, char *label, u32 mask,
+ char **next, unsigned *size)
+{
+ admhc_dbg_sw(ahcd, next, size, "%s 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s\n",
+ label,
+ mask,
+ (mask & ADMHC_INTR_INTA) ? " INTA" : "",
+ (mask & ADMHC_INTR_FATI) ? " FATI" : "",
+ (mask & ADMHC_INTR_SWI) ? " SWI" : "",
+ (mask & ADMHC_INTR_TDC) ? " TDC" : "",
+ (mask & ADMHC_INTR_FNO) ? " FNO" : "",
+ (mask & ADMHC_INTR_SO) ? " SO" : "",
+ (mask & ADMHC_INTR_INSM) ? " INSM" : "",
+ (mask & ADMHC_INTR_BABI) ? " BABI" : "",
+ (mask & ADMHC_INTR_7) ? " !7!" : "",
+ (mask & ADMHC_INTR_6) ? " !6!" : "",
+ (mask & ADMHC_INTR_RESI) ? " RESI" : "",
+ (mask & ADMHC_INTR_SOFI) ? " SOFI" : ""
+ );
+}
+
+static void maybe_print_eds(struct admhcd *ahcd, char *label, u32 value,
+ char **next, unsigned *size)
+{
+ if (value)
+ admhc_dbg_sw(ahcd, next, size, "%s %08x\n", label, value);
+}
+
+static char *buss2string (int state)
+{
+ switch (state) {
+ case ADMHC_BUSS_RESET:
+ return "reset";
+ case ADMHC_BUSS_RESUME:
+ return "resume";
+ case ADMHC_BUSS_OPER:
+ return "operational";
+ case ADMHC_BUSS_SUSPEND:
+ return "suspend";
+ }
+ return "?state";
+}
+
+static void
+admhc_dump_status(struct admhcd *ahcd, char **next, unsigned *size)
+{
+ struct admhcd_regs __iomem *regs = ahcd->regs;
+ u32 temp;
+
+ temp = admhc_readl(ahcd, ®s->gencontrol);
+ admhc_dbg_sw(ahcd, next, size,
+ "gencontrol 0x%08x%s%s%s%s\n",
+ temp,
+ (temp & ADMHC_CTRL_UHFE) ? " UHFE" : "",
+ (temp & ADMHC_CTRL_SIR) ? " SIR" : "",
+ (temp & ADMHC_CTRL_DMAA) ? " DMAA" : "",
+ (temp & ADMHC_CTRL_SR) ? " SR" : ""
+ );
+
+ temp = admhc_readl(ahcd, ®s->host_control);
+ admhc_dbg_sw(ahcd, next, size,
+ "host_control 0x%08x BUSS=%s%s\n",
+ temp,
+ buss2string(temp & ADMHC_HC_BUSS),
+ (temp & ADMHC_HC_DMAE) ? " DMAE" : ""
+ );
+
+ admhc_dump_intr_mask(ahcd, "int_status",
+ admhc_readl(ahcd, ®s->int_status),
+ next, size);
+ admhc_dump_intr_mask(ahcd, "int_enable",
+ admhc_readl(ahcd, ®s->int_enable),
+ next, size);
+
+ maybe_print_eds(ahcd, "hosthead",
+ admhc_readl(ahcd, ®s->hosthead), next, size);
+}
+
+#define dbg_port_sw(hc,num,value,next,size) \
+ admhc_dbg_sw(hc, next, size, \
+ "portstatus [%d] " \
+ "0x%08x%s%s%s%s%s%s%s%s%s%s%s%s\n", \
+ num, temp, \
+ (temp & ADMHC_PS_PRSC) ? " PRSC" : "", \
+ (temp & ADMHC_PS_OCIC) ? " OCIC" : "", \
+ (temp & ADMHC_PS_PSSC) ? " PSSC" : "", \
+ (temp & ADMHC_PS_PESC) ? " PESC" : "", \
+ (temp & ADMHC_PS_CSC) ? " CSC" : "", \
+ \
+ (temp & ADMHC_PS_LSDA) ? " LSDA" : "", \
+ (temp & ADMHC_PS_PPS) ? " PPS" : "", \
+ (temp & ADMHC_PS_PRS) ? " PRS" : "", \
+ (temp & ADMHC_PS_POCI) ? " POCI" : "", \
+ (temp & ADMHC_PS_PSS) ? " PSS" : "", \
+ \
+ (temp & ADMHC_PS_PES) ? " PES" : "", \
+ (temp & ADMHC_PS_CCS) ? " CCS" : "" \
+ );
+
+
+static void
+admhc_dump_roothub(
+ struct admhcd *ahcd,
+ int verbose,
+ char **next,
+ unsigned *size)
+{
+ u32 temp, i;
+
+ temp = admhc_read_rhdesc(ahcd);
+ if (temp == ~(u32)0)
+ return;
+
+ if (verbose) {
+ admhc_dbg_sw(ahcd, next, size,
+ "rhdesc %08x%s%s%s%s%s%s PPCM=%02x%s%s%s%s NUMP=%d(%d)\n",
+ temp,
+ (temp & ADMHC_RH_CRWE) ? " CRWE" : "",
+ (temp & ADMHC_RH_OCIC) ? " OCIC" : "",
+ (temp & ADMHC_RH_LPSC) ? " LPSC" : "",
+ (temp & ADMHC_RH_LPSC) ? " DRWE" : "",
+ (temp & ADMHC_RH_LPSC) ? " OCI" : "",
+ (temp & ADMHC_RH_LPSC) ? " LPS" : "",
+ ((temp & ADMHC_RH_PPCM) >> 16),
+ (temp & ADMHC_RH_NOCP) ? " NOCP" : "",
+ (temp & ADMHC_RH_OCPM) ? " OCPM" : "",
+ (temp & ADMHC_RH_NPS) ? " NPS" : "",
+ (temp & ADMHC_RH_PSM) ? " PSM" : "",
+ (temp & ADMHC_RH_NUMP), ahcd->num_ports
+ );
+ }
+
+ for (i = 0; i < ahcd->num_ports; i++) {
+ temp = admhc_read_portstatus(ahcd, i);
+ dbg_port_sw(ahcd, i, temp, next, size);
+ }
+}
+
+static void admhc_dump(struct admhcd *ahcd, int verbose)
+{
+ admhc_dbg(ahcd, "ADMHC ahcd state\n");
+
+ /* dumps some of the state we know about */
+ admhc_dump_status(ahcd, NULL, NULL);
+ admhc_dbg(ahcd,"current frame #%04x\n",
+ admhc_frame_no(ahcd));
+
+ admhc_dump_roothub(ahcd, verbose, NULL, NULL);
+}
+
+static const char data0[] = "DATA0";
+static const char data1[] = "DATA1";
+
+static void admhc_dump_td(const struct admhcd *ahcd, const char *label,
+ const struct td *td)
+{
+ u32 tmp;
+
+ admhc_dbg(ahcd, "%s td %p; urb %p index %d; hwNextTD %08x\n",
+ label, td,
+ td->urb, td->index,
+ hc32_to_cpup(ahcd, &td->hwNextTD));
+
+ tmp = hc32_to_cpup(ahcd, &td->hwINFO);
+ admhc_dbg(ahcd, " status %08x%s CC=%x EC=%d %s %s ISI=%x FN=%x\n",
+ tmp,
+ (tmp & TD_OWN) ? " OWN" : "",
+ TD_CC_GET(tmp),
+ TD_EC_GET(tmp),
+ td_togglestring(tmp),
+ td_pidstring(tmp),
+ TD_ISI_GET(tmp),
+ TD_FN_GET(tmp));
+
+ tmp = hc32_to_cpup(ahcd, &td->hwCBL);
+ admhc_dbg(ahcd, " dbp %08x; cbl %08x; LEN=%d%s\n",
+ hc32_to_cpup(ahcd, &td->hwDBP),
+ tmp,
+ TD_BL_GET(tmp),
+ (tmp & TD_IE) ? " IE" : "");
+}
+
+/* caller MUST own hcd spinlock if verbose is set! */
+static void __attribute__((unused))
+admhc_dump_ed(const struct admhcd *ahcd, const char *label,
+ const struct ed *ed, int verbose)
+{
+ u32 tmp = hc32_to_cpu(ahcd, ed->hwINFO);
+
+ admhc_dbg(ahcd, "%s ed %p %s type %s; next ed %08x\n",
+ label,
+ ed, ed_statestring(ed->state), ed_typestring(ed->type),
+ hc32_to_cpup(ahcd, &ed->hwNextED));
+
+ admhc_dbg(ahcd, " info %08x MAX=%d%s%s%s%s EP=%d DEV=%d\n", tmp,
+ ED_MPS_GET(tmp),
+ (tmp & ED_ISO) ? " ISO" : "",
+ (tmp & ED_SKIP) ? " SKIP" : "",
+ (tmp & ED_SPEED_FULL) ? " FULL" : " LOW",
+ (tmp & ED_INT) ? " INT" : "",
+ ED_EN_GET(tmp),
+ ED_FA_GET(tmp));
+
+ tmp = hc32_to_cpup(ahcd, &ed->hwHeadP);
+ admhc_dbg(ahcd, " tds: head %08x tail %08x %s%s%s\n",
+ tmp & TD_MASK,
+ hc32_to_cpup (ahcd, &ed->hwTailP),
+ (tmp & ED_C) ? data1 : data0,
+ (tmp & ED_H) ? " HALT" : "",
+ verbose ? " td list follows" : " (not listing)");
+
+ if (verbose) {
+ struct list_head *tmp;
+
+ /* use ed->td_list because HC concurrently modifies
+ * hwNextTD as it accumulates ed_donelist.
+ */
+ list_for_each(tmp, &ed->td_list) {
+ struct td *td;
+ td = list_entry(tmp, struct td, td_list);
+ admhc_dump_td (ahcd, " ->", td);
+ }
+ }
+}
+
+#else /* ifdef DEBUG */
+
+static inline void urb_print(struct admhcd *ahcd, struct urb * urb, char * str,
+ int small) {}
+static inline void admhc_dump_ed(const struct admhcd *ahcd, const char *label,
+ const struct ed *ed, int verbose) {}
+static inline void admhc_dump_td(const struct admhcd *ahcd, const char *label,
+ const struct td *td) {}
+static inline void admhc_dump(struct admhcd *ahcd, int verbose) {}
+
+#undef ADMHC_VERBOSE_DEBUG
+
+#endif /* DEBUG */
+
+/*-------------------------------------------------------------------------*/
+
+#ifdef STUB_DEBUG_FILES
+
+static inline void create_debug_files(struct admhcd *bus) { }
+static inline void remove_debug_files(struct admhcd *bus) { }
+
+#else
+
+static int debug_async_open(struct inode *, struct file *);
+static int debug_periodic_open(struct inode *, struct file *);
+static int debug_registers_open(struct inode *, struct file *);
+static ssize_t debug_output(struct file*, char __user*, size_t, loff_t*);
+static int debug_close(struct inode *, struct file *);
+
+static const struct file_operations debug_async_fops = {
+ .owner = THIS_MODULE,
+ .open = debug_async_open,
+ .read = debug_output,
+ .release = debug_close,
+};
+static const struct file_operations debug_periodic_fops = {
+ .owner = THIS_MODULE,
+ .open = debug_periodic_open,
+ .read = debug_output,
+ .release = debug_close,
+};
+static const struct file_operations debug_registers_fops = {
+ .owner = THIS_MODULE,
+ .open = debug_registers_open,
+ .read = debug_output,
+ .release = debug_close,
+};
+
+static struct dentry *admhc_debug_root;
+
+struct debug_buffer {
+ ssize_t (*fill_func)(struct debug_buffer *); /* fill method */
+ struct device *dev;
+ struct mutex mutex; /* protect filling of buffer */
+ size_t count; /* number of characters filled into buffer */
+ char *page;
+};
+
+static ssize_t
+show_list(struct admhcd *ahcd, char *buf, size_t count, struct ed *ed)
+{
+ unsigned temp;
+ unsigned size = count;
+
+ if (!ed)
+ return 0;
+
+ /* dump a snapshot of the bulk or control schedule */
+ while (ed) {
+ u32 info = hc32_to_cpu(ahcd, ed->hwINFO);
+ u32 headp = hc32_to_cpu(ahcd, ed->hwHeadP);
+ u32 tailp = hc32_to_cpu(ahcd, ed->hwTailP);
+ struct list_head *entry;
+ struct td *td;
+
+ temp = scnprintf(buf, size,
+ "ed/%p %s %s %cs dev%d ep%d %s%smax %d %08x%s%s %s"
+ " h:%08x t:%08x",
+ ed,
+ ed_statestring(ed->state),
+ ed_typestring (ed->type),
+ (info & ED_SPEED_FULL) ? 'f' : 'l',
+ info & ED_FA_MASK,
+ (info >> ED_EN_SHIFT) & ED_EN_MASK,
+ (info & ED_INT) ? "INT " : "",
+ (info & ED_ISO) ? "ISO " : "",
+ (info >> ED_MPS_SHIFT) & ED_MPS_MASK ,
+ info,
+ (info & ED_SKIP) ? " S" : "",
+ (headp & ED_H) ? " H" : "",
+ (headp & ED_C) ? data1 : data0,
+ headp & ED_MASK,tailp);
+ size -= temp;
+ buf += temp;
+
+ list_for_each(entry, &ed->td_list) {
+ u32 dbp, cbl;
+
+ td = list_entry(entry, struct td, td_list);
+ info = hc32_to_cpup (ahcd, &td->hwINFO);
+ dbp = hc32_to_cpup (ahcd, &td->hwDBP);
+ cbl = hc32_to_cpup (ahcd, &td->hwCBL);
+
+ temp = scnprintf(buf, size,
+ "\n\ttd/%p %s %d %s%scc=%x urb %p (%08x,%08x)",
+ td,
+ td_pidstring(info),
+ TD_BL_GET(cbl),
+ (info & TD_OWN) ? "" : "DONE ",
+ (cbl & TD_IE) ? "IE " : "",
+ TD_CC_GET (info), td->urb, info, cbl);
+ size -= temp;
+ buf += temp;
+ }
+
+ temp = scnprintf(buf, size, "\n");
+ size -= temp;
+ buf += temp;
+
+ ed = ed->ed_next;
+ }
+
+ return count - size;
+}
+
+static ssize_t fill_async_buffer(struct debug_buffer *buf)
+{
+ struct usb_bus *bus;
+ struct usb_hcd *hcd;
+ struct admhcd *ahcd;
+ size_t temp;
+ unsigned long flags;
+
+ bus = dev_get_drvdata(buf->dev);
+ hcd = bus_to_hcd(bus);
+ ahcd = hcd_to_admhcd(hcd);
+
+ spin_lock_irqsave(&ahcd->lock, flags);
+ temp = show_list(ahcd, buf->page, PAGE_SIZE, ahcd->ed_head);
+ spin_unlock_irqrestore(&ahcd->lock, flags);
+
+ return temp;
+}
+
+
+#define DBG_SCHED_LIMIT 64
+
+static ssize_t fill_periodic_buffer(struct debug_buffer *buf)
+{
+ struct usb_bus *bus;
+ struct usb_hcd *hcd;
+ struct admhcd *ahcd;
+ struct ed **seen, *ed;
+ unsigned long flags;
+ unsigned temp, size, seen_count;
+ char *next;
+ unsigned i;
+
+ if (!(seen = kmalloc(DBG_SCHED_LIMIT * sizeof *seen, GFP_ATOMIC)))
+ return 0;
+ seen_count = 0;
+
+ bus = dev_get_drvdata(buf->dev);
+ hcd = bus_to_hcd(bus);
+ ahcd = hcd_to_admhcd(hcd);
+ next = buf->page;
+ size = PAGE_SIZE;
+
+ temp = scnprintf(next, size, "size = %d\n", NUM_INTS);
+ size -= temp;
+ next += temp;
+
+ /* dump a snapshot of the periodic schedule (and load) */
+ spin_lock_irqsave(&ahcd->lock, flags);
+ for (i = 0; i < NUM_INTS; i++) {
+ if (!(ed = ahcd->periodic [i]))
+ continue;
+
+ temp = scnprintf(next, size, "%2d [%3d]:", i, ahcd->load [i]);
+ size -= temp;
+ next += temp;
+
+ do {
+ temp = scnprintf(next, size, " ed%d/%p",
+ ed->interval, ed);
+ size -= temp;
+ next += temp;
+ for (temp = 0; temp < seen_count; temp++) {
+ if (seen [temp] == ed)
+ break;
+ }
+
+ /* show more info the first time around */
+ if (temp == seen_count) {
+ u32 info = hc32_to_cpu (ahcd, ed->hwINFO);
+ struct list_head *entry;
+ unsigned qlen = 0;
+
+ /* qlen measured here in TDs, not urbs */
+ list_for_each (entry, &ed->td_list)
+ qlen++;
+ temp = scnprintf(next, size,
+ " (%cs dev%d ep%d%s qlen %u"
+ " max %d %08x%s%s)",
+ (info & ED_SPEED_FULL) ? 'f' : 'l',
+ ED_FA_GET(info),
+ ED_EN_GET(info),
+ (info & ED_ISO) ? "iso" : "int",
+ qlen,
+ ED_MPS_GET(info),
+ info,
+ (info & ED_SKIP) ? " K" : "",
+ (ed->hwHeadP &
+ cpu_to_hc32(ahcd, ED_H)) ?
+ " H" : "");
+ size -= temp;
+ next += temp;
+
+ if (seen_count < DBG_SCHED_LIMIT)
+ seen [seen_count++] = ed;
+
+ ed = ed->ed_next;
+
+ } else {
+ /* we've seen it and what's after */
+ temp = 0;
+ ed = NULL;
+ }
+
+ } while (ed);
+
+ temp = scnprintf(next, size, "\n");
+ size -= temp;
+ next += temp;
+ }
+ spin_unlock_irqrestore(&ahcd->lock, flags);
+ kfree (seen);
+
+ return PAGE_SIZE - size;
+}
+
+
+#undef DBG_SCHED_LIMIT
+
+static ssize_t fill_registers_buffer(struct debug_buffer *buf)
+{
+ struct usb_bus *bus;
+ struct usb_hcd *hcd;
+ struct admhcd *ahcd;
+ struct admhcd_regs __iomem *regs;
+ unsigned long flags;
+ unsigned temp, size;
+ char *next;
+ u32 rdata;
+
+ bus = dev_get_drvdata(buf->dev);
+ hcd = bus_to_hcd(bus);
+ ahcd = hcd_to_admhcd(hcd);
+ regs = ahcd->regs;
+ next = buf->page;
+ size = PAGE_SIZE;
+
+ spin_lock_irqsave(&ahcd->lock, flags);
+
+ /* dump driver info, then registers in spec order */
+
+ admhc_dbg_sw(ahcd, &next, &size,
+ "bus %s, device %s\n"
+ "%s\n"
+ "%s version " DRIVER_VERSION "\n",
+ hcd->self.controller->bus->name,
+ hcd->self.controller->bus_id,
+ hcd->product_desc,
+ hcd_name);
+
+ if (bus->controller->power.power_state.event) {
+ size -= scnprintf(next, size,
+ "SUSPENDED (no register access)\n");
+ goto done;
+ }
+
+ admhc_dump_status(ahcd, &next, &size);
+
+ /* other registers mostly affect frame timings */
+ rdata = admhc_readl(ahcd, ®s->fminterval);
+ temp = scnprintf(next, size,
+ "fmintvl 0x%08x %sFSLDP=0x%04x FI=0x%04x\n",
+ rdata, (rdata & ADMHC_SFI_FIT) ? "FIT " : "",
+ (rdata >> ADMHC_SFI_FSLDP_SHIFT) & ADMHC_SFI_FSLDP_MASK,
+ rdata & ADMHC_SFI_FI_MASK);
+ size -= temp;
+ next += temp;
+
+ rdata = admhc_readl(ahcd, ®s->fmnumber);
+ temp = scnprintf(next, size, "fmnumber 0x%08x %sFR=0x%04x FN=%04x\n",
+ rdata, (rdata & ADMHC_SFN_FRT) ? "FRT " : "",
+ (rdata >> ADMHC_SFN_FR_SHIFT) & ADMHC_SFN_FR_MASK,
+ rdata & ADMHC_SFN_FN_MASK);
+ size -= temp;
+ next += temp;
+
+ /* TODO: use predefined bitmask */
+ rdata = admhc_readl(ahcd, ®s->lsthresh);
+ temp = scnprintf(next, size, "lsthresh 0x%04x\n",
+ rdata & 0x3fff);
+ size -= temp;
+ next += temp;
+
+ temp = scnprintf(next, size, "hub poll timer: %s\n",
+ admhcd_to_hcd(ahcd)->poll_rh ? "ON" : "OFF");
+ size -= temp;
+ next += temp;
+
+ /* roothub */
+ admhc_dump_roothub(ahcd, 1, &next, &size);
+
+done:
+ spin_unlock_irqrestore(&ahcd->lock, flags);
+ return PAGE_SIZE - size;
+}
+
+
+static struct debug_buffer *alloc_buffer(struct device *dev,
+ ssize_t (*fill_func)(struct debug_buffer *))
+{
+ struct debug_buffer *buf;
+
+ buf = kzalloc(sizeof(struct debug_buffer), GFP_KERNEL);
+
+ if (buf) {
+ buf->dev = dev;
+ buf->fill_func = fill_func;
+ mutex_init(&buf->mutex);
+ }
+
+ return buf;
+}
+
+static int fill_buffer(struct debug_buffer *buf)
+{
+ int ret = 0;
+
+ if (!buf->page)
+ buf->page = (char *)get_zeroed_page(GFP_KERNEL);
+
+ if (!buf->page) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ ret = buf->fill_func(buf);
+
+ if (ret >= 0) {
+ buf->count = ret;
+ ret = 0;
+ }
+
+out:
+ return ret;
+}
+
+static ssize_t debug_output(struct file *file, char __user *user_buf,
+ size_t len, loff_t *offset)
+{
+ struct debug_buffer *buf = file->private_data;
+ int ret = 0;
+
+ mutex_lock(&buf->mutex);
+ if (buf->count == 0) {
+ ret = fill_buffer(buf);
+ if (ret != 0) {
+ mutex_unlock(&buf->mutex);
+ goto out;
+ }
+ }
+ mutex_unlock(&buf->mutex);
+
+ ret = simple_read_from_buffer(user_buf, len, offset,
+ buf->page, buf->count);
+
+out:
+ return ret;
+}
+
+static int debug_close(struct inode *inode, struct file *file)
+{
+ struct debug_buffer *buf = file->private_data;
+
+ if (buf) {
+ if (buf->page)
+ free_page((unsigned long)buf->page);
+ kfree(buf);
+ }
+
+ return 0;
+}
+
+static int debug_async_open(struct inode *inode, struct file *file)
+{
+ file->private_data = alloc_buffer(inode->i_private, fill_async_buffer);
+
+ return file->private_data ? 0 : -ENOMEM;
+}
+
+static int debug_periodic_open(struct inode *inode, struct file *file)
+{
+ file->private_data = alloc_buffer(inode->i_private,
+ fill_periodic_buffer);
+
+ return file->private_data ? 0 : -ENOMEM;
+}
+
+static int debug_registers_open(struct inode *inode, struct file *file)
+{
+ file->private_data = alloc_buffer(inode->i_private,
+ fill_registers_buffer);
+
+ return file->private_data ? 0 : -ENOMEM;
+}
+
+static inline void create_debug_files(struct admhcd *ahcd)
+{
+ struct usb_bus *bus = &admhcd_to_hcd(ahcd)->self;
+ struct device *dev = bus->dev;
+
+ ahcd->debug_dir = debugfs_create_dir(bus->bus_name, admhc_debug_root);
+ if (!ahcd->debug_dir)
+ goto dir_error;
+
+ ahcd->debug_async = debugfs_create_file("async", S_IRUGO,
+ ahcd->debug_dir, dev,
+ &debug_async_fops);
+ if (!ahcd->debug_async)
+ goto async_error;
+
+ ahcd->debug_periodic = debugfs_create_file("periodic", S_IRUGO,
+ ahcd->debug_dir, dev,
+ &debug_periodic_fops);
+ if (!ahcd->debug_periodic)
+ goto periodic_error;
+
+ ahcd->debug_registers = debugfs_create_file("registers", S_IRUGO,
+ ahcd->debug_dir, dev,
+ &debug_registers_fops);
+ if (!ahcd->debug_registers)
+ goto registers_error;
+
+ admhc_dbg(ahcd, "created debug files\n");
+ return;
+
+registers_error:
+ debugfs_remove(ahcd->debug_periodic);
+periodic_error:
+ debugfs_remove(ahcd->debug_async);
+async_error:
+ debugfs_remove(ahcd->debug_dir);
+dir_error:
+ ahcd->debug_periodic = NULL;
+ ahcd->debug_async = NULL;
+ ahcd->debug_dir = NULL;
+}
+
+static inline void remove_debug_files(struct admhcd *ahcd)
+{
+ debugfs_remove(ahcd->debug_registers);
+ debugfs_remove(ahcd->debug_periodic);
+ debugfs_remove(ahcd->debug_async);
+ debugfs_remove(ahcd->debug_dir);
+}
+
+#endif
+
+/*-------------------------------------------------------------------------*/
--- /dev/null
+/*
+ * ADM5120 HCD (Host Controller Driver) for USB
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This file was derived from: drivers/usb/host/ohci-au1xxx.c
+ * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
+ * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
+ * (C) Copyright 2002 Hewlett-Packard Company
+ *
+ * Written by Christopher Hoover <ch@hpl.hp.com>
+ * Based on fragments of previous driver by Rusell King et al.
+ *
+ * Modified for LH7A404 from ahcd-sa1111.c
+ * by Durgesh Pattamatta <pattamattad@sharpsec.com>
+ * Modified for AMD Alchemy Au1xxx
+ * by Matt Porter <mporter@kernel.crashing.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <linux/signal.h>
+
+#include <asm/bootinfo.h>
+#include <asm/mach-adm5120/adm5120_defs.h>
+
+#ifdef DEBUG
+#define HCD_DBG(f, a...) printk(KERN_DEBUG "%s: " f, hcd_name, ## a)
+#else
+#define HCD_DBG(f, a...) do {} while (0)
+#endif
+#define HCD_ERR(f, a...) printk(KERN_ERR "%s: " f, hcd_name, ## a)
+#define HCD_INFO(f, a...) printk(KERN_INFO "%s: " f, hcd_name, ## a)
+
+/*-------------------------------------------------------------------------*/
+
+static int admhc_adm5120_probe(const struct hc_driver *driver,
+ struct platform_device *dev)
+{
+ int retval;
+ struct usb_hcd *hcd;
+ int irq;
+ struct resource *regs;
+
+ /* sanity checks */
+ regs = platform_get_resource(dev, IORESOURCE_MEM, 0);
+ if (!regs) {
+ HCD_DBG("no IOMEM resource found\n");
+ return -ENODEV;
+ }
+
+ irq = platform_get_irq(dev, 0);
+ if (irq < 0) {
+ HCD_DBG("no IRQ resource found\n");
+ return -ENODEV;
+ }
+
+ hcd = usb_create_hcd(driver, &dev->dev, "ADM5120");
+ if (!hcd)
+ return -ENOMEM;
+
+ hcd->rsrc_start = regs->start;
+ hcd->rsrc_len = regs->end - regs->start + 1;
+
+ if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
+ HCD_DBG("request_mem_region failed\n");
+ retval = -EBUSY;
+ goto err_dev;
+ }
+
+ hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
+ if (!hcd->regs) {
+ HCD_DBG("ioremap failed\n");
+ retval = -ENOMEM;
+ goto err_mem;
+ }
+
+ admhc_hcd_init(hcd_to_admhcd(hcd));
+
+ retval = usb_add_hcd(hcd, irq, IRQF_DISABLED);
+ if (retval)
+ goto err_io;
+
+ return 0;
+
+err_io:
+ iounmap(hcd->regs);
+err_mem:
+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+err_dev:
+ usb_put_hcd(hcd);
+ return retval;
+}
+
+
+/* may be called without controller electrically present */
+/* may be called with controller, bus, and devices active */
+
+static void admhc_adm5120_remove(struct usb_hcd *hcd,
+ struct platform_device *dev)
+{
+ usb_remove_hcd(hcd);
+ iounmap(hcd->regs);
+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+ usb_put_hcd(hcd);
+}
+
+/*-------------------------------------------------------------------------*/
+
+static int __devinit
+admhc_adm5120_start(struct usb_hcd *hcd)
+{
+ struct admhcd *ahcd = hcd_to_admhcd (hcd);
+ int ret;
+
+ ret = admhc_init(ahcd);
+ if (ret < 0) {
+ HCD_ERR("unable to init %s\n", hcd->self.bus_name);
+ goto err;
+ }
+
+ ret = admhc_run(ahcd);
+ if (ret < 0) {
+ HCD_ERR("unable to run %s\n", hcd->self.bus_name);
+ goto err_stop;
+ }
+
+ return 0;
+
+err_stop:
+ admhc_stop(hcd);
+err:
+ return ret;
+}
+
+/*-------------------------------------------------------------------------*/
+
+static const struct hc_driver adm5120_hc_driver = {
+ .description = hcd_name,
+ .product_desc = "ADM5120 built-in USB 1.1 Host Controller",
+ .hcd_priv_size = sizeof(struct admhcd),
+
+ /*
+ * generic hardware linkage
+ */
+ .irq = admhc_irq,
+ .flags = HCD_USB11 | HCD_MEMORY,
+
+ /*
+ * basic lifecycle operations
+ */
+ .start = admhc_adm5120_start,
+ .stop = admhc_stop,
+ .shutdown = admhc_shutdown,
+
+ /*
+ * managing i/o requests and associated device resources
+ */
+ .urb_enqueue = admhc_urb_enqueue,
+ .urb_dequeue = admhc_urb_dequeue,
+ .endpoint_disable = admhc_endpoint_disable,
+
+ /*
+ * scheduling support
+ */
+ .get_frame_number = admhc_get_frame_number,
+
+ /*
+ * root hub support
+ */
+ .hub_status_data = admhc_hub_status_data,
+ .hub_control = admhc_hub_control,
+ .hub_irq_enable = admhc_hub_irq_enable,
+#ifdef CONFIG_PM
+ .bus_suspend = admhc_bus_suspend,
+ .bus_resume = admhc_bus_resume,
+#endif
+ .start_port_reset = admhc_start_port_reset,
+};
+
+/*-------------------------------------------------------------------------*/
+
+static int usb_hcd_adm5120_probe(struct platform_device *pdev)
+{
+ int ret;
+
+ ret = admhc_adm5120_probe(&adm5120_hc_driver, pdev);
+
+ return ret;
+}
+
+static int usb_hcd_adm5120_remove(struct platform_device *pdev)
+{
+ struct usb_hcd *hcd = platform_get_drvdata(pdev);
+
+ admhc_adm5120_remove(hcd, pdev);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+/* TODO */
+static int usb_hcd_adm5120_suspend(struct platform_device *dev)
+{
+ struct usb_hcd *hcd = platform_get_drvdata(dev);
+
+ return 0;
+}
+
+static int usb_hcd_adm5120_resume(struct platform_device *dev)
+{
+ struct usb_hcd *hcd = platform_get_drvdata(dev);
+
+ return 0;
+}
+#else
+#define usb_hcd_adm5120_suspend NULL
+#define usb_hcd_adm5120_resume NULL
+#endif /* CONFIG_PM */
+
+static struct platform_driver usb_hcd_adm5120_driver = {
+ .probe = usb_hcd_adm5120_probe,
+ .remove = usb_hcd_adm5120_remove,
+ .shutdown = usb_hcd_platform_shutdown,
+ .suspend = usb_hcd_adm5120_suspend,
+ .resume = usb_hcd_adm5120_resume,
+ .driver = {
+ .name = "adm5120-hcd",
+ .owner = THIS_MODULE,
+ },
+};
+
--- /dev/null
+/*
+ * ADM5120 HCD (Host Controller Driver) for USB
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This file was derived from: drivers/usb/host/ohci-hcd.c
+ * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
+ * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
+ *
+ * [ Initialisation is based on Linus' ]
+ * [ uhci code and gregs ahcd fragments ]
+ * [ (C) Copyright 1999 Linus Torvalds ]
+ * [ (C) Copyright 1999 Gregory P. Smith]
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/ioport.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/timer.h>
+#include <linux/list.h>
+#include <linux/usb.h>
+#include <linux/usb/otg.h>
+#include <linux/dma-mapping.h>
+#include <linux/dmapool.h>
+#include <linux/reboot.h>
+#include <linux/debugfs.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+#include <asm/unaligned.h>
+#include <asm/byteorder.h>
+
+#include "../core/hcd.h"
+#include "../core/hub.h"
+
+#define DRIVER_VERSION "0.25.0"
+#define DRIVER_AUTHOR "Gabor Juhos <juhosg@openwrt.org>"
+#define DRIVER_DESC "ADMtek USB 1.1 Host Controller Driver"
+
+/*-------------------------------------------------------------------------*/
+
+#undef ADMHC_VERBOSE_DEBUG /* not always helpful */
+
+/* For initializing controller (mask in an HCFS mode too) */
+#define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
+
+#define ADMHC_INTR_INIT \
+ ( ADMHC_INTR_MIE | ADMHC_INTR_INSM | ADMHC_INTR_FATI \
+ | ADMHC_INTR_RESI | ADMHC_INTR_TDC | ADMHC_INTR_BABI )
+
+/*-------------------------------------------------------------------------*/
+
+static const char hcd_name [] = "admhc-hcd";
+
+#define STATECHANGE_DELAY msecs_to_jiffies(300)
+
+#include "adm5120.h"
+
+static void admhc_dump(struct admhcd *ahcd, int verbose);
+static int admhc_init(struct admhcd *ahcd);
+static void admhc_stop(struct usb_hcd *hcd);
+
+#include "adm5120-dbg.c"
+#include "adm5120-mem.c"
+#include "adm5120-pm.c"
+#include "adm5120-hub.c"
+#include "adm5120-q.c"
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * queue up an urb for anything except the root hub
+ */
+static int admhc_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
+ gfp_t mem_flags)
+{
+ struct admhcd *ahcd = hcd_to_admhcd(hcd);
+ struct ed *ed;
+ struct urb_priv *urb_priv;
+ unsigned int pipe = urb->pipe;
+ int td_cnt = 0;
+ unsigned long flags;
+ int ret = 0;
+
+#ifdef ADMHC_VERBOSE_DEBUG
+ spin_lock_irqsave(&ahcd->lock, flags);
+ urb_print(ahcd, urb, "ENQEUE", usb_pipein(pipe), -EINPROGRESS);
+ spin_unlock_irqrestore(&ahcd->lock, flags);
+#endif
+
+ /* every endpoint has an ed, locate and maybe (re)initialize it */
+ ed = ed_get(ahcd, urb->ep, urb->dev, pipe, urb->interval);
+ if (!ed)
+ return -ENOMEM;
+
+ /* for the private part of the URB we need the number of TDs */
+ switch (ed->type) {
+ case PIPE_CONTROL:
+ if (urb->transfer_buffer_length > TD_DATALEN_MAX)
+ /* td_submit_urb() doesn't yet handle these */
+ return -EMSGSIZE;
+
+ /* 1 TD for setup, 1 for ACK, plus ... */
+ td_cnt = 2;
+ /* FALLTHROUGH */
+ case PIPE_BULK:
+ /* one TD for every 4096 Bytes (can be upto 8K) */
+ td_cnt += urb->transfer_buffer_length / TD_DATALEN_MAX;
+ /* ... and for any remaining bytes ... */
+ if ((urb->transfer_buffer_length % TD_DATALEN_MAX) != 0)
+ td_cnt++;
+ /* ... and maybe a zero length packet to wrap it up */
+ if (td_cnt == 0)
+ td_cnt++;
+ else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
+ && (urb->transfer_buffer_length
+ % usb_maxpacket(urb->dev, pipe,
+ usb_pipeout (pipe))) == 0)
+ td_cnt++;
+ break;
+ case PIPE_INTERRUPT:
+ /*
+ * for Interrupt IN/OUT transactions, each ED contains
+ * only 1 TD.
+ * TODO: check transfer_buffer_length?
+ */
+ td_cnt = 1;
+ break;
+ case PIPE_ISOCHRONOUS:
+ /* number of packets from URB */
+ td_cnt = urb->number_of_packets;
+ break;
+ }
+
+ urb_priv = urb_priv_alloc(ahcd, td_cnt, mem_flags);
+ if (!urb_priv)
+ return -ENOMEM;
+
+ urb_priv->ed = ed;
+
+ spin_lock_irqsave(&ahcd->lock, flags);
+ /* don't submit to a dead HC */
+ if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
+ ret = -ENODEV;
+ goto fail;
+ }
+ if (!HC_IS_RUNNING(hcd->state)) {
+ ret = -ENODEV;
+ goto fail;
+ }
+
+ ret = usb_hcd_link_urb_to_ep(hcd, urb);
+ if (ret)
+ goto fail;
+
+ /* schedule the ed if needed */
+ if (ed->state == ED_IDLE) {
+ ret = ed_schedule(ahcd, ed);
+ if (ret < 0) {
+ usb_hcd_unlink_urb_from_ep(hcd, urb);
+ goto fail;
+ }
+ if (ed->type == PIPE_ISOCHRONOUS) {
+ u16 frame = admhc_frame_no(ahcd);
+
+ /* delay a few frames before the first TD */
+ frame += max_t (u16, 8, ed->interval);
+ frame &= ~(ed->interval - 1);
+ frame |= ed->branch;
+ urb->start_frame = frame;
+
+ /* yes, only URB_ISO_ASAP is supported, and
+ * urb->start_frame is never used as input.
+ */
+ }
+ } else if (ed->type == PIPE_ISOCHRONOUS)
+ urb->start_frame = ed->last_iso + ed->interval;
+
+ /* fill the TDs and link them to the ed; and
+ * enable that part of the schedule, if needed
+ * and update count of queued periodic urbs
+ */
+ urb->hcpriv = urb_priv;
+ td_submit_urb(ahcd, urb);
+
+#ifdef ADMHC_VERBOSE_DEBUG
+ admhc_dump_ed(ahcd, "admhc_urb_enqueue", urb_priv->ed, 1);
+#endif
+
+fail:
+ if (ret)
+ urb_priv_free(ahcd, urb_priv);
+
+ spin_unlock_irqrestore(&ahcd->lock, flags);
+ return ret;
+}
+
+/*
+ * decouple the URB from the HC queues (TDs, urb_priv);
+ * reporting is always done
+ * asynchronously, and we might be dealing with an urb that's
+ * partially transferred, or an ED with other urbs being unlinked.
+ */
+static int admhc_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
+ int status)
+{
+ struct admhcd *ahcd = hcd_to_admhcd(hcd);
+ unsigned long flags;
+ int ret;
+
+ spin_lock_irqsave(&ahcd->lock, flags);
+
+#ifdef ADMHC_VERBOSE_DEBUG
+ urb_print(ahcd, urb, "DEQUEUE", 1, status);
+#endif
+ ret = usb_hcd_check_unlink_urb(hcd, urb, status);
+ if (ret) {
+ /* Do nothing */
+ ;
+ } else if (HC_IS_RUNNING(hcd->state)) {
+ struct urb_priv *urb_priv;
+
+ /* Unless an IRQ completed the unlink while it was being
+ * handed to us, flag it for unlink and giveback, and force
+ * some upcoming INTR_SF to call finish_unlinks()
+ */
+ urb_priv = urb->hcpriv;
+ if (urb_priv) {
+ if (urb_priv->ed->state == ED_OPER)
+ start_ed_unlink(ahcd, urb_priv->ed);
+ }
+ } else {
+ /*
+ * with HC dead, we won't respect hc queue pointers
+ * any more ... just clean up every urb's memory.
+ */
+ if (urb->hcpriv)
+ finish_urb(ahcd, urb, status);
+ }
+ spin_unlock_irqrestore(&ahcd->lock, flags);
+
+ return ret;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* frees config/altsetting state for endpoints,
+ * including ED memory, dummy TD, and bulk/intr data toggle
+ */
+
+static void admhc_endpoint_disable(struct usb_hcd *hcd,
+ struct usb_host_endpoint *ep)
+{
+ struct admhcd *ahcd = hcd_to_admhcd(hcd);
+ unsigned long flags;
+ struct ed *ed = ep->hcpriv;
+ unsigned limit = 1000;
+
+ /* ASSERT: any requests/urbs are being unlinked */
+ /* ASSERT: nobody can be submitting urbs for this any more */
+
+ if (!ed)
+ return;
+
+#ifdef ADMHC_VERBOSE_DEBUG
+ spin_lock_irqsave(&ahcd->lock, flags);
+ admhc_dump_ed(ahcd, "EP-DISABLE", ed, 1);
+ spin_unlock_irqrestore(&ahcd->lock, flags);
+#endif
+
+rescan:
+ spin_lock_irqsave(&ahcd->lock, flags);
+
+ if (!HC_IS_RUNNING(hcd->state)) {
+sanitize:
+ ed->state = ED_IDLE;
+ finish_unlinks(ahcd, 0);
+ }
+
+ switch (ed->state) {
+ case ED_UNLINK: /* wait for hw to finish? */
+ /* major IRQ delivery trouble loses INTR_SOFI too... */
+ if (limit-- == 0) {
+ admhc_warn(ahcd, "IRQ INTR_SOFI lossage\n");
+ goto sanitize;
+ }
+ spin_unlock_irqrestore(&ahcd->lock, flags);
+ schedule_timeout_uninterruptible(1);
+ goto rescan;
+ case ED_IDLE: /* fully unlinked */
+ if (list_empty(&ed->td_list)) {
+ td_free (ahcd, ed->dummy);
+ ed_free (ahcd, ed);
+ break;
+ }
+ /* else FALL THROUGH */
+ default:
+ /* caller was supposed to have unlinked any requests;
+ * that's not our job. can't recover; must leak ed.
+ */
+ admhc_err(ahcd, "leak ed %p (#%02x) state %d%s\n",
+ ed, ep->desc.bEndpointAddress, ed->state,
+ list_empty(&ed->td_list) ? "" : " (has tds)");
+ td_free(ahcd, ed->dummy);
+ break;
+ }
+
+ ep->hcpriv = NULL;
+
+ spin_unlock_irqrestore(&ahcd->lock, flags);
+ return;
+}
+
+static int admhc_get_frame_number(struct usb_hcd *hcd)
+{
+ struct admhcd *ahcd = hcd_to_admhcd(hcd);
+
+ return admhc_frame_no(ahcd);
+}
+
+static void admhc_usb_reset(struct admhcd *ahcd)
+{
+#if 0
+ ahcd->hc_control = admhc_readl(ahcd, &ahcd->regs->control);
+ ahcd->hc_control &= OHCI_CTRL_RWC;
+ admhc_writel(ahcd, ahcd->hc_control, &ahcd->regs->control);
+#else
+ /* FIXME */
+ ahcd->host_control = ADMHC_BUSS_RESET;
+ admhc_writel(ahcd, ahcd->host_control ,&ahcd->regs->host_control);
+#endif
+}
+
+/* admhc_shutdown forcibly disables IRQs and DMA, helping kexec and
+ * other cases where the next software may expect clean state from the
+ * "firmware". this is bus-neutral, unlike shutdown() methods.
+ */
+static void
+admhc_shutdown(struct usb_hcd *hcd)
+{
+ struct admhcd *ahcd;
+
+ ahcd = hcd_to_admhcd(hcd);
+ admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
+ admhc_dma_disable(ahcd);
+ admhc_usb_reset(ahcd);
+ /* flush the writes */
+ admhc_writel_flush(ahcd);
+}
+
+/*-------------------------------------------------------------------------*
+ * HC functions
+ *-------------------------------------------------------------------------*/
+
+static void admhc_eds_cleanup(struct admhcd *ahcd)
+{
+ if (ahcd->ed_tails[PIPE_INTERRUPT]) {
+ ed_free(ahcd, ahcd->ed_tails[PIPE_INTERRUPT]);
+ ahcd->ed_tails[PIPE_INTERRUPT] = NULL;
+ }
+
+ if (ahcd->ed_tails[PIPE_ISOCHRONOUS]) {
+ ed_free(ahcd, ahcd->ed_tails[PIPE_ISOCHRONOUS]);
+ ahcd->ed_tails[PIPE_ISOCHRONOUS] = NULL;
+ }
+
+ if (ahcd->ed_tails[PIPE_CONTROL]) {
+ ed_free(ahcd, ahcd->ed_tails[PIPE_CONTROL]);
+ ahcd->ed_tails[PIPE_CONTROL] = NULL;
+ }
+
+ if (ahcd->ed_tails[PIPE_BULK]) {
+ ed_free(ahcd, ahcd->ed_tails[PIPE_BULK]);
+ ahcd->ed_tails[PIPE_BULK] = NULL;
+ }
+
+ ahcd->ed_head = NULL;
+}
+
+#define ED_DUMMY_INFO (ED_SPEED_FULL | ED_SKIP)
+
+static int admhc_eds_init(struct admhcd *ahcd)
+{
+ struct ed *ed;
+
+ ed = ed_create(ahcd, PIPE_INTERRUPT, ED_DUMMY_INFO);
+ if (!ed)
+ goto err;
+
+ ahcd->ed_tails[PIPE_INTERRUPT] = ed;
+
+ ed = ed_create(ahcd, PIPE_ISOCHRONOUS, ED_DUMMY_INFO);
+ if (!ed)
+ goto err;
+
+ ahcd->ed_tails[PIPE_ISOCHRONOUS] = ed;
+ ed->ed_prev = ahcd->ed_tails[PIPE_INTERRUPT];
+ ahcd->ed_tails[PIPE_INTERRUPT]->ed_next = ed;
+ ahcd->ed_tails[PIPE_INTERRUPT]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
+
+ ed = ed_create(ahcd, PIPE_CONTROL, ED_DUMMY_INFO);
+ if (!ed)
+ goto err;
+
+ ahcd->ed_tails[PIPE_CONTROL] = ed;
+ ed->ed_prev = ahcd->ed_tails[PIPE_ISOCHRONOUS];
+ ahcd->ed_tails[PIPE_ISOCHRONOUS]->ed_next = ed;
+ ahcd->ed_tails[PIPE_ISOCHRONOUS]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
+
+ ed = ed_create(ahcd, PIPE_BULK, ED_DUMMY_INFO);
+ if (!ed)
+ goto err;
+
+ ahcd->ed_tails[PIPE_BULK] = ed;
+ ed->ed_prev = ahcd->ed_tails[PIPE_CONTROL];
+ ahcd->ed_tails[PIPE_CONTROL]->ed_next = ed;
+ ahcd->ed_tails[PIPE_CONTROL]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
+
+ ahcd->ed_head = ahcd->ed_tails[PIPE_INTERRUPT];
+
+#ifdef ADMHC_VERBOSE_DEBUG
+ admhc_dump_ed(ahcd, "ed intr", ahcd->ed_tails[PIPE_INTERRUPT], 1);
+ admhc_dump_ed(ahcd, "ed isoc", ahcd->ed_tails[PIPE_ISOCHRONOUS], 1);
+ admhc_dump_ed(ahcd, "ed ctrl", ahcd->ed_tails[PIPE_CONTROL], 1);
+ admhc_dump_ed(ahcd, "ed bulk", ahcd->ed_tails[PIPE_BULK], 1);
+#endif
+
+ return 0;
+
+err:
+ admhc_eds_cleanup(ahcd);
+ return -ENOMEM;
+}
+
+/* init memory, and kick BIOS/SMM off */
+
+static int admhc_init(struct admhcd *ahcd)
+{
+ struct usb_hcd *hcd = admhcd_to_hcd(ahcd);
+ int ret;
+
+ admhc_disable(ahcd);
+ ahcd->regs = hcd->regs;
+
+ /* Disable HC interrupts */
+ admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
+
+ /* Read the number of ports unless overridden */
+ if (ahcd->num_ports == 0)
+ ahcd->num_ports = admhc_read_rhdesc(ahcd) & ADMHC_RH_NUMP;
+
+ ret = admhc_mem_init(ahcd);
+ if (ret)
+ goto err;
+
+ /* init dummy endpoints */
+ ret = admhc_eds_init(ahcd);
+ if (ret)
+ goto err;
+
+ create_debug_files(ahcd);
+
+ return 0;
+
+err:
+ admhc_stop(hcd);
+ return ret;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* Start an OHCI controller, set the BUS operational
+ * resets USB and controller
+ * enable interrupts
+ */
+static int admhc_run(struct admhcd *ahcd)
+{
+ u32 temp;
+ int first = ahcd->fminterval == 0;
+ struct usb_hcd *hcd = admhcd_to_hcd(ahcd);
+
+ admhc_disable(ahcd);
+
+ /* boot firmware should have set this up (5.1.1.3.1) */
+ if (first) {
+ temp = admhc_readl(ahcd, &ahcd->regs->fminterval);
+ ahcd->fminterval = temp & ADMHC_SFI_FI_MASK;
+ if (ahcd->fminterval != FI)
+ admhc_dbg(ahcd, "fminterval delta %d\n",
+ ahcd->fminterval - FI);
+ ahcd->fminterval |=
+ (FSLDP(ahcd->fminterval) << ADMHC_SFI_FSLDP_SHIFT);
+ /* also: power/overcurrent flags in rhdesc */
+ }
+
+#if 0 /* TODO: not applicable */
+ /* Reset USB nearly "by the book". RemoteWakeupConnected was
+ * saved if boot firmware (BIOS/SMM/...) told us it's connected,
+ * or if bus glue did the same (e.g. for PCI add-in cards with
+ * PCI PM support).
+ */
+ if ((ahcd->hc_control & OHCI_CTRL_RWC) != 0
+ && !device_may_wakeup(hcd->self.controller))
+ device_init_wakeup(hcd->self.controller, 1);
+#endif
+
+ switch (ahcd->host_control & ADMHC_HC_BUSS) {
+ case ADMHC_BUSS_OPER:
+ temp = 0;
+ break;
+ case ADMHC_BUSS_SUSPEND:
+ /* FALLTHROUGH ? */
+ case ADMHC_BUSS_RESUME:
+ ahcd->host_control = ADMHC_BUSS_RESUME;
+ temp = 10 /* msec wait */;
+ break;
+ /* case ADMHC_BUSS_RESET: */
+ default:
+ ahcd->host_control = ADMHC_BUSS_RESET;
+ temp = 50 /* msec wait */;
+ break;
+ }
+ admhc_writel(ahcd, ahcd->host_control, &ahcd->regs->host_control);
+
+ /* flush the writes */
+ admhc_writel_flush(ahcd);
+
+ msleep(temp);
+ temp = admhc_read_rhdesc(ahcd);
+ if (!(temp & ADMHC_RH_NPS)) {
+ /* power down each port */
+ for (temp = 0; temp < ahcd->num_ports; temp++)
+ admhc_write_portstatus(ahcd, temp, ADMHC_PS_CPP);
+ }
+ /* flush those writes */
+ admhc_writel_flush(ahcd);
+
+ /* 2msec timelimit here means no irqs/preempt */
+ spin_lock_irq(&ahcd->lock);
+
+ admhc_writel(ahcd, ADMHC_CTRL_SR, &ahcd->regs->gencontrol);
+ temp = 30; /* ... allow extra time */
+ while ((admhc_readl(ahcd, &ahcd->regs->gencontrol) & ADMHC_CTRL_SR) != 0) {
+ if (--temp == 0) {
+ spin_unlock_irq(&ahcd->lock);
+ admhc_err(ahcd, "USB HC reset timed out!\n");
+ return -1;
+ }
+ udelay(1);
+ }
+
+ /* enable HOST mode, before access any host specific register */
+ admhc_writel(ahcd, ADMHC_CTRL_UHFE, &ahcd->regs->gencontrol);
+
+ /* Tell the controller where the descriptor list is */
+ admhc_writel(ahcd, (u32)ahcd->ed_head->dma, &ahcd->regs->hosthead);
+
+ periodic_reinit(ahcd);
+
+ /* use rhsc irqs after khubd is fully initialized */
+ hcd->poll_rh = 1;
+ hcd->uses_new_polling = 1;
+
+#if 0
+ /* wake on ConnectStatusChange, matching external hubs */
+ admhc_writel(ahcd, RH_HS_DRWE, &ahcd->regs->roothub.status);
+#else
+ /* FIXME roothub_write_status (ahcd, ADMHC_RH_DRWE); */
+#endif
+
+ /* Choose the interrupts we care about now, others later on demand */
+ admhc_intr_ack(ahcd, ~0);
+ admhc_intr_enable(ahcd, ADMHC_INTR_INIT);
+
+ admhc_writel(ahcd, ADMHC_RH_NPS | ADMHC_RH_LPSC, &ahcd->regs->rhdesc);
+
+ /* flush those writes */
+ admhc_writel_flush(ahcd);
+
+ /* start controller operations */
+ ahcd->host_control = ADMHC_BUSS_OPER;
+ admhc_writel(ahcd, ahcd->host_control, &ahcd->regs->host_control);
+
+ temp = 20;
+ while ((admhc_readl(ahcd, &ahcd->regs->host_control)
+ & ADMHC_HC_BUSS) != ADMHC_BUSS_OPER) {
+ if (--temp == 0) {
+ spin_unlock_irq(&ahcd->lock);
+ admhc_err(ahcd, "unable to setup operational mode!\n");
+ return -1;
+ }
+ mdelay(1);
+ }
+
+ hcd->state = HC_STATE_RUNNING;
+
+ ahcd->next_statechange = jiffies + STATECHANGE_DELAY;
+
+#if 0
+ /* FIXME: enabling DMA is always failed here for an unknown reason */
+ admhc_dma_enable(ahcd);
+
+ temp = 200;
+ while ((admhc_readl(ahcd, &ahcd->regs->host_control)
+ & ADMHC_HC_DMAE) != ADMHC_HC_DMAE) {
+ if (--temp == 0) {
+ spin_unlock_irq(&ahcd->lock);
+ admhc_err(ahcd, "unable to enable DMA!\n");
+ admhc_dump(ahcd, 1);
+ return -1;
+ }
+ mdelay(1);
+ }
+
+#endif
+
+ spin_unlock_irq(&ahcd->lock);
+
+ mdelay(ADMHC_POTPGT);
+
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* an interrupt happens */
+
+static irqreturn_t admhc_irq(struct usb_hcd *hcd)
+{
+ struct admhcd *ahcd = hcd_to_admhcd(hcd);
+ struct admhcd_regs __iomem *regs = ahcd->regs;
+ u32 ints;
+
+ ints = admhc_readl(ahcd, ®s->int_status);
+ if ((ints & ADMHC_INTR_INTA) == 0) {
+ /* no unmasked interrupt status is set */
+ return IRQ_NONE;
+ }
+
+ ints &= admhc_readl(ahcd, ®s->int_enable);
+
+ if (ints & ADMHC_INTR_FATI) {
+ /* e.g. due to PCI Master/Target Abort */
+ admhc_disable(ahcd);
+ admhc_err(ahcd, "Fatal Error, controller disabled\n");
+ admhc_dump(ahcd, 1);
+ admhc_usb_reset(ahcd);
+ }
+
+ if (ints & ADMHC_INTR_BABI) {
+ admhc_intr_disable(ahcd, ADMHC_INTR_BABI);
+ admhc_intr_ack(ahcd, ADMHC_INTR_BABI);
+ admhc_err(ahcd, "Babble Detected\n");
+ }
+
+ if (ints & ADMHC_INTR_INSM) {
+ admhc_vdbg(ahcd, "Root Hub Status Change\n");
+ ahcd->next_statechange = jiffies + STATECHANGE_DELAY;
+ admhc_intr_ack(ahcd, ADMHC_INTR_RESI | ADMHC_INTR_INSM);
+
+ /* NOTE: Vendors didn't always make the same implementation
+ * choices for RHSC. Many followed the spec; RHSC triggers
+ * on an edge, like setting and maybe clearing a port status
+ * change bit. With others it's level-triggered, active
+ * until khubd clears all the port status change bits. We'll
+ * always disable it here and rely on polling until khubd
+ * re-enables it.
+ */
+ admhc_intr_disable(ahcd, ADMHC_INTR_INSM);
+ usb_hcd_poll_rh_status(hcd);
+ } else if (ints & ADMHC_INTR_RESI) {
+ /* For connect and disconnect events, we expect the controller
+ * to turn on RHSC along with RD. But for remote wakeup events
+ * this might not happen.
+ */
+ admhc_vdbg(ahcd, "Resume Detect\n");
+ admhc_intr_ack(ahcd, ADMHC_INTR_RESI);
+ hcd->poll_rh = 1;
+ if (ahcd->autostop) {
+ spin_lock(&ahcd->lock);
+ admhc_rh_resume(ahcd);
+ spin_unlock(&ahcd->lock);
+ } else
+ usb_hcd_resume_root_hub(hcd);
+ }
+
+ if (ints & ADMHC_INTR_TDC) {
+ admhc_vdbg(ahcd, "Transfer Descriptor Complete\n");
+ admhc_intr_ack(ahcd, ADMHC_INTR_TDC);
+ if (HC_IS_RUNNING(hcd->state))
+ admhc_intr_disable(ahcd, ADMHC_INTR_TDC);
+ spin_lock(&ahcd->lock);
+ admhc_td_complete(ahcd);
+ spin_unlock(&ahcd->lock);
+ if (HC_IS_RUNNING(hcd->state))
+ admhc_intr_enable(ahcd, ADMHC_INTR_TDC);
+ }
+
+ if (ints & ADMHC_INTR_SO) {
+ /* could track INTR_SO to reduce available PCI/... bandwidth */
+ admhc_vdbg(ahcd, "Schedule Overrun\n");
+ }
+
+#if 1
+ spin_lock(&ahcd->lock);
+ if (ahcd->ed_rm_list)
+ finish_unlinks(ahcd, admhc_frame_no(ahcd));
+
+ if ((ints & ADMHC_INTR_SOFI) != 0 && !ahcd->ed_rm_list
+ && HC_IS_RUNNING(hcd->state))
+ admhc_intr_disable(ahcd, ADMHC_INTR_SOFI);
+ spin_unlock(&ahcd->lock);
+#else
+ if (ints & ADMHC_INTR_SOFI) {
+ admhc_vdbg(ahcd, "Start Of Frame\n");
+ spin_lock(&ahcd->lock);
+
+ /* handle any pending ED removes */
+ finish_unlinks(ahcd, admhc_frameno(ahcd));
+
+ /* leaving INTR_SOFI enabled when there's still unlinking
+ * to be done in the (next frame).
+ */
+ if ((ahcd->ed_rm_list == NULL) ||
+ HC_IS_RUNNING(hcd->state) == 0)
+ /*
+ * disable INTR_SOFI if there are no unlinking to be
+ * done (in the next frame)
+ */
+ admhc_intr_disable(ahcd, ADMHC_INTR_SOFI);
+
+ spin_unlock(&ahcd->lock);
+ }
+#endif
+
+ if (HC_IS_RUNNING(hcd->state)) {
+ admhc_intr_ack(ahcd, ints);
+ admhc_intr_enable(ahcd, ADMHC_INTR_MIE);
+ admhc_writel_flush(ahcd);
+ }
+
+ return IRQ_HANDLED;
+}
+
+/*-------------------------------------------------------------------------*/
+
+static void admhc_stop(struct usb_hcd *hcd)
+{
+ struct admhcd *ahcd = hcd_to_admhcd(hcd);
+
+ admhc_dump(ahcd, 1);
+
+ flush_scheduled_work();
+
+ admhc_usb_reset(ahcd);
+ admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
+
+ free_irq(hcd->irq, hcd);
+ hcd->irq = -1;
+
+ remove_debug_files(ahcd);
+ admhc_eds_cleanup(ahcd);
+ admhc_mem_cleanup(ahcd);
+}
+
+/*-------------------------------------------------------------------------*/
+
+#ifdef CONFIG_ADM5120
+#include "adm5120-drv.c"
+#define PLATFORM_DRIVER usb_hcd_adm5120_driver
+#endif
+
+#if !defined(PLATFORM_DRIVER)
+#error "missing bus glue for admhc-hcd"
+#endif
+
+#define DRIVER_INFO DRIVER_DESC " version " DRIVER_VERSION
+
+static int __init admhc_hcd_mod_init(void)
+{
+ int ret = 0;
+
+ if (usb_disabled())
+ return -ENODEV;
+
+ pr_info("%s: " DRIVER_INFO "\n", hcd_name);
+ pr_info("%s: block sizes: ed %Zd td %Zd\n", hcd_name,
+ sizeof (struct ed), sizeof (struct td));
+
+#ifdef DEBUG
+ admhc_debug_root = debugfs_create_dir("admhc", NULL);
+ if (!admhc_debug_root) {
+ ret = -ENOENT;
+ goto error_debug;
+ }
+#endif
+
+#ifdef PLATFORM_DRIVER
+ ret = platform_driver_register(&PLATFORM_DRIVER);
+ if (ret < 0)
+ goto error_platform;
+#endif
+
+ return ret;
+
+#ifdef PLATFORM_DRIVER
+ platform_driver_unregister(&PLATFORM_DRIVER);
+error_platform:
+#endif
+
+#ifdef DEBUG
+ debugfs_remove(admhc_debug_root);
+ admhc_debug_root = NULL;
+error_debug:
+#endif
+ return ret;
+}
+module_init(admhc_hcd_mod_init);
+
+static void __exit admhc_hcd_mod_exit(void)
+{
+ platform_driver_unregister(&PLATFORM_DRIVER);
+#ifdef DEBUG
+ debugfs_remove(admhc_debug_root);
+#endif
+}
+module_exit(admhc_hcd_mod_exit);
+
+MODULE_AUTHOR(DRIVER_AUTHOR);
+MODULE_DESCRIPTION(DRIVER_INFO);
+MODULE_VERSION(DRIVER_VERSION);
+MODULE_LICENSE("GPL v2");
--- /dev/null
+/*
+ * ADM5120 HCD (Host Controller Driver) for USB
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This file was derived from: drivers/usb/host/ohci-hub.c
+ * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
+ * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * ADM5120 Root Hub ... the nonsharable stuff
+ */
+
+#define dbg_port(hc,label,num,value) \
+ admhc_dbg(hc, \
+ "%s port%d " \
+ "= 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s\n", \
+ label, num, value, \
+ (value & ADMHC_PS_PRSC) ? " PRSC" : "", \
+ (value & ADMHC_PS_OCIC) ? " OCIC" : "", \
+ (value & ADMHC_PS_PSSC) ? " PSSC" : "", \
+ (value & ADMHC_PS_PESC) ? " PESC" : "", \
+ (value & ADMHC_PS_CSC) ? " CSC" : "", \
+ \
+ (value & ADMHC_PS_LSDA) ? " LSDA" : "", \
+ (value & ADMHC_PS_PPS) ? " PPS" : "", \
+ (value & ADMHC_PS_PRS) ? " PRS" : "", \
+ (value & ADMHC_PS_POCI) ? " POCI" : "", \
+ (value & ADMHC_PS_PSS) ? " PSS" : "", \
+ \
+ (value & ADMHC_PS_PES) ? " PES" : "", \
+ (value & ADMHC_PS_CCS) ? " CCS" : "" \
+ );
+
+#define dbg_port_write(hc,label,num,value) \
+ admhc_dbg(hc, \
+ "%s port%d " \
+ "= 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s\n", \
+ label, num, value, \
+ (value & ADMHC_PS_PRSC) ? " PRSC" : "", \
+ (value & ADMHC_PS_OCIC) ? " OCIC" : "", \
+ (value & ADMHC_PS_PSSC) ? " PSSC" : "", \
+ (value & ADMHC_PS_PESC) ? " PESC" : "", \
+ (value & ADMHC_PS_CSC) ? " CSC" : "", \
+ \
+ (value & ADMHC_PS_CPP) ? " CPP" : "", \
+ (value & ADMHC_PS_SPP) ? " SPP" : "", \
+ (value & ADMHC_PS_SPR) ? " SPR" : "", \
+ (value & ADMHC_PS_CPS) ? " CPS" : "", \
+ (value & ADMHC_PS_SPS) ? " SPS" : "", \
+ \
+ (value & ADMHC_PS_SPE) ? " SPE" : "", \
+ (value & ADMHC_PS_CPE) ? " CPE" : "" \
+ );
+
+/*-------------------------------------------------------------------------*/
+
+/* hcd->hub_irq_enable() */
+static void admhc_hub_irq_enable(struct usb_hcd *hcd)
+{
+ struct admhcd *ahcd = hcd_to_admhcd(hcd);
+
+ spin_lock_irq(&ahcd->lock);
+ if (!ahcd->autostop)
+ del_timer(&hcd->rh_timer); /* Prevent next poll */
+ admhc_intr_enable(ahcd, ADMHC_INTR_INSM);
+ spin_unlock_irq(&ahcd->lock);
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* build "status change" packet (one or two bytes) from HC registers */
+
+static int
+admhc_hub_status_data(struct usb_hcd *hcd, char *buf)
+{
+ struct admhcd *ahcd = hcd_to_admhcd(hcd);
+ int i, changed = 0, length = 1;
+ int any_connected = 0;
+ unsigned long flags;
+ u32 status;
+
+ spin_lock_irqsave(&ahcd->lock, flags);
+ if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags))
+ goto done;
+
+ /* init status */
+ status = admhc_read_rhdesc(ahcd);
+ if (status & (ADMHC_RH_LPSC | ADMHC_RH_OCIC))
+ buf [0] = changed = 1;
+ else
+ buf [0] = 0;
+ if (ahcd->num_ports > 7) {
+ buf [1] = 0;
+ length++;
+ }
+
+ /* look at each port */
+ for (i = 0; i < ahcd->num_ports; i++) {
+ status = admhc_read_portstatus(ahcd, i);
+
+ /* can't autostop if ports are connected */
+ any_connected |= (status & ADMHC_PS_CCS);
+
+ if (status & (ADMHC_PS_CSC | ADMHC_PS_PESC | ADMHC_PS_PSSC
+ | ADMHC_PS_OCIC | ADMHC_PS_PRSC)) {
+ changed = 1;
+ if (i < 7)
+ buf [0] |= 1 << (i + 1);
+ else
+ buf [1] |= 1 << (i - 7);
+ }
+ }
+
+ hcd->poll_rh = admhc_root_hub_state_changes(ahcd, changed,
+ any_connected);
+
+done:
+ spin_unlock_irqrestore(&ahcd->lock, flags);
+
+ return changed ? length : 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+static int admhc_get_hub_descriptor(struct admhcd *ahcd, char *buf)
+{
+ struct usb_hub_descriptor *desc = (struct usb_hub_descriptor *)buf;
+ u32 rh = admhc_read_rhdesc(ahcd);
+ u16 temp;
+
+ desc->bDescriptorType = USB_DT_HUB; /* Hub-descriptor */
+ desc->bPwrOn2PwrGood = ADMHC_POTPGT/2; /* use default value */
+ desc->bHubContrCurrent = 0x00; /* 0mA */
+
+ desc->bNbrPorts = ahcd->num_ports;
+ temp = 1 + (ahcd->num_ports / 8);
+ desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
+
+ /* FIXME */
+ temp = 0;
+ if (rh & ADMHC_RH_NPS) /* no power switching? */
+ temp |= 0x0002;
+ if (rh & ADMHC_RH_PSM) /* per-port power switching? */
+ temp |= 0x0001;
+ if (rh & ADMHC_RH_NOCP) /* no overcurrent reporting? */
+ temp |= 0x0010;
+ else if (rh & ADMHC_RH_OCPM) /* per-port overcurrent reporting? */
+ temp |= 0x0008;
+ desc->wHubCharacteristics = (__force __u16)cpu_to_hc16(ahcd, temp);
+
+ /* two bitmaps: ports removable, and usb 1.0 legacy PortPwrCtrlMask */
+ desc->bitmap[0] = 0;
+ desc->bitmap[0] = ~0;
+
+ return 0;
+}
+
+static int admhc_get_hub_status(struct admhcd *ahcd, char *buf)
+{
+ struct usb_hub_status *hs = (struct usb_hub_status *)buf;
+ u32 t = admhc_read_rhdesc(ahcd);
+ u16 status, change;
+
+ status = 0;
+ status |= (t & ADMHC_RH_LPS) ? HUB_STATUS_LOCAL_POWER : 0;
+ status |= (t & ADMHC_RH_OCI) ? HUB_STATUS_OVERCURRENT : 0;
+
+ change = 0;
+ change |= (t & ADMHC_RH_LPSC) ? HUB_CHANGE_LOCAL_POWER : 0;
+ change |= (t & ADMHC_RH_OCIC) ? HUB_CHANGE_OVERCURRENT : 0;
+
+ hs->wHubStatus = (__force __u16)cpu_to_hc16(ahcd, status);
+ hs->wHubChange = (__force __u16)cpu_to_hc16(ahcd, change);
+
+ return 0;
+}
+
+static int admhc_get_port_status(struct admhcd *ahcd, unsigned port, char *buf)
+{
+ struct usb_port_status *ps = (struct usb_port_status *)buf;
+ u32 t = admhc_read_portstatus(ahcd, port);
+ u16 status, change;
+
+ status = 0;
+ status |= (t & ADMHC_PS_CCS) ? USB_PORT_STAT_CONNECTION : 0;
+ status |= (t & ADMHC_PS_PES) ? USB_PORT_STAT_ENABLE : 0;
+ status |= (t & ADMHC_PS_PSS) ? USB_PORT_STAT_SUSPEND : 0;
+ status |= (t & ADMHC_PS_POCI) ? USB_PORT_STAT_OVERCURRENT : 0;
+ status |= (t & ADMHC_PS_PRS) ? USB_PORT_STAT_RESET : 0;
+ status |= (t & ADMHC_PS_PPS) ? USB_PORT_STAT_POWER : 0;
+ status |= (t & ADMHC_PS_LSDA) ? USB_PORT_STAT_LOW_SPEED : 0;
+
+ change = 0;
+ change |= (t & ADMHC_PS_CSC) ? USB_PORT_STAT_C_CONNECTION : 0;
+ change |= (t & ADMHC_PS_PESC) ? USB_PORT_STAT_C_ENABLE : 0;
+ change |= (t & ADMHC_PS_PSSC) ? USB_PORT_STAT_C_SUSPEND : 0;
+ change |= (t & ADMHC_PS_OCIC) ? USB_PORT_STAT_C_OVERCURRENT : 0;
+ change |= (t & ADMHC_PS_PRSC) ? USB_PORT_STAT_C_RESET : 0;
+
+ ps->wPortStatus = (__force __u16)cpu_to_hc16(ahcd, status);
+ ps->wPortChange = (__force __u16)cpu_to_hc16(ahcd, change);
+
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+#ifdef CONFIG_USB_OTG
+
+static int admhc_start_port_reset(struct usb_hcd *hcd, unsigned port)
+{
+ struct admhcd *ahcd = hcd_to_admhcd(hcd);
+ u32 status;
+
+ if (!port)
+ return -EINVAL;
+ port--;
+
+ /* start port reset before HNP protocol times out */
+ status = admhc_read_portstatus(ahcd, port);
+ if (!(status & ADMHC_PS_CCS))
+ return -ENODEV;
+
+ /* khubd will finish the reset later */
+ admhc_write_portstatus(ahcd, port, ADMHC_PS_PRS);
+ return 0;
+}
+
+static void start_hnp(struct admhcd *ahcd);
+
+#else
+
+#define admhc_start_port_reset NULL
+
+#endif
+
+/*-------------------------------------------------------------------------*/
+
+
+/* See usb 7.1.7.5: root hubs must issue at least 50 msec reset signaling,
+ * not necessarily continuous ... to guard against resume signaling.
+ * The short timeout is safe for non-root hubs, and is backward-compatible
+ * with earlier Linux hosts.
+ */
+#ifdef CONFIG_USB_SUSPEND
+#define PORT_RESET_MSEC 50
+#else
+#define PORT_RESET_MSEC 10
+#endif
+
+/* this timer value might be vendor-specific ... */
+#define PORT_RESET_HW_MSEC 10
+
+/* wrap-aware logic morphed from <linux/jiffies.h> */
+#define tick_before(t1,t2) ((s16)(((s16)(t1))-((s16)(t2))) < 0)
+
+/* called from some task, normally khubd */
+static inline int admhc_port_reset(struct admhcd *ahcd, unsigned port)
+{
+ u32 t;
+
+ admhc_vdbg(ahcd, "reset port%d\n", port);
+ t = admhc_read_portstatus(ahcd, port);
+ if (!(t & ADMHC_PS_CCS))
+ return -ENODEV;
+
+ admhc_write_portstatus(ahcd, port, ADMHC_PS_SPR);
+ mdelay(10);
+ admhc_write_portstatus(ahcd, port, (ADMHC_PS_SPE | ADMHC_PS_CSC));
+ mdelay(100);
+
+ return 0;
+}
+
+static inline int admhc_port_enable(struct admhcd *ahcd, unsigned port)
+{
+ u32 t;
+
+ admhc_vdbg(ahcd, "enable port%d\n", port);
+ t = admhc_read_portstatus(ahcd, port);
+ if (!(t & ADMHC_PS_CCS))
+ return -ENODEV;
+
+ admhc_write_portstatus(ahcd, port, ADMHC_PS_SPE);
+
+ return 0;
+}
+
+static inline int admhc_port_disable(struct admhcd *ahcd, unsigned port)
+{
+ u32 t;
+
+ admhc_vdbg(ahcd, "disable port%d\n", port);
+ t = admhc_read_portstatus(ahcd, port);
+ if (!(t & ADMHC_PS_CCS))
+ return -ENODEV;
+
+ admhc_write_portstatus(ahcd, port, ADMHC_PS_CPE);
+
+ return 0;
+}
+
+static inline int admhc_port_write(struct admhcd *ahcd, unsigned port,
+ u32 val)
+{
+#ifdef ADMHC_VERBOSE_DEBUG
+ dbg_port_write(ahcd, "write", port, val);
+#endif
+ admhc_write_portstatus(ahcd, port, val);
+
+ return 0;
+}
+
+static int admhc_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
+ u16 wIndex, char *buf, u16 wLength)
+{
+ struct admhcd *ahcd = hcd_to_admhcd(hcd);
+ int ports = hcd_to_bus(hcd)->root_hub->maxchild;
+ int ret = 0;
+
+ if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)))
+ return -ESHUTDOWN;
+
+ switch (typeReq) {
+ case ClearHubFeature:
+ switch (wValue) {
+ case C_HUB_OVER_CURRENT:
+#if 0 /* FIXME */
+ admhc_writel(ahcd, ADMHC_RH_OCIC,
+ &ahcd->regs->roothub.status);
+#endif
+ case C_HUB_LOCAL_POWER:
+ break;
+ default:
+ goto error;
+ }
+ break;
+ case ClearPortFeature:
+ if (!wIndex || wIndex > ports)
+ goto error;
+ wIndex--;
+
+ switch (wValue) {
+ case USB_PORT_FEAT_ENABLE:
+ ret = admhc_port_disable(ahcd, wIndex);
+ break;
+ case USB_PORT_FEAT_SUSPEND:
+ ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_CPS);
+ break;
+ case USB_PORT_FEAT_POWER:
+ ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_CPP);
+ break;
+ case USB_PORT_FEAT_C_CONNECTION:
+ ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_CSC);
+ break;
+ case USB_PORT_FEAT_C_ENABLE:
+ ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_PESC);
+ break;
+ case USB_PORT_FEAT_C_SUSPEND:
+ ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_PSSC);
+ break;
+ case USB_PORT_FEAT_C_OVER_CURRENT:
+ ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_OCIC);
+ break;
+ case USB_PORT_FEAT_C_RESET:
+ ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_PRSC);
+ break;
+ default:
+ goto error;
+ }
+ break;
+ case GetHubDescriptor:
+ ret = admhc_get_hub_descriptor(ahcd, buf);
+ break;
+ case GetHubStatus:
+ ret = admhc_get_hub_status(ahcd, buf);
+ break;
+ case GetPortStatus:
+ if (!wIndex || wIndex > ports)
+ goto error;
+ wIndex--;
+
+ ret = admhc_get_port_status(ahcd, wIndex, buf);
+ break;
+ case SetHubFeature:
+ switch (wValue) {
+ case C_HUB_OVER_CURRENT:
+ /* FIXME: this can be cleared, yes? */
+ case C_HUB_LOCAL_POWER:
+ break;
+ default:
+ goto error;
+ }
+ break;
+ case SetPortFeature:
+ if (!wIndex || wIndex > ports)
+ goto error;
+ wIndex--;
+
+ switch (wValue) {
+ case USB_PORT_FEAT_ENABLE:
+ ret = admhc_port_enable(ahcd, wIndex);
+ break;
+ case USB_PORT_FEAT_RESET:
+ ret = admhc_port_reset(ahcd, wIndex);
+ break;
+ case USB_PORT_FEAT_SUSPEND:
+#ifdef CONFIG_USB_OTG
+ if (hcd->self.otg_port == (wIndex + 1)
+ && hcd->self.b_hnp_enable)
+ start_hnp(ahcd);
+ else
+#endif
+ ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_SPS);
+ break;
+ case USB_PORT_FEAT_POWER:
+ ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_SPP);
+ break;
+ default:
+ goto error;
+ }
+ break;
+
+ default:
+error:
+ /* "protocol stall" on error */
+ ret = -EPIPE;
+ }
+
+ return ret;
+}
+
--- /dev/null
+/*
+ * ADM5120 HCD (Host Controller Driver) for USB
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This file was derived from: drivers/usb/host/ohci-mem.c
+ * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
+ * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * OHCI deals with three types of memory:
+ * - data used only by the HCD ... kmalloc is fine
+ * - async and periodic schedules, shared by HC and HCD ... these
+ * need to use dma_pool or dma_alloc_coherent
+ * - driver buffers, read/written by HC ... the hcd glue or the
+ * device driver provides us with dma addresses
+ *
+ * There's also "register" data, which is memory mapped.
+ * No memory seen by this driver (or any HCD) may be paged out.
+ */
+
+/*-------------------------------------------------------------------------*/
+
+static void admhc_hcd_init(struct admhcd *ahcd)
+{
+ ahcd->next_statechange = jiffies;
+ spin_lock_init(&ahcd->lock);
+ INIT_LIST_HEAD(&ahcd->pending);
+}
+
+/*-------------------------------------------------------------------------*/
+
+static int admhc_mem_init(struct admhcd *ahcd)
+{
+ ahcd->td_cache = dma_pool_create("admhc_td",
+ admhcd_to_hcd(ahcd)->self.controller,
+ sizeof(struct td),
+ TD_ALIGN, /* byte alignment */
+ 0 /* no page-crossing issues */
+ );
+ if (!ahcd->td_cache)
+ goto err;
+
+ ahcd->ed_cache = dma_pool_create("admhc_ed",
+ admhcd_to_hcd(ahcd)->self.controller,
+ sizeof(struct ed),
+ ED_ALIGN, /* byte alignment */
+ 0 /* no page-crossing issues */
+ );
+ if (!ahcd->ed_cache)
+ goto err_td_cache;
+
+ return 0;
+
+err_td_cache:
+ dma_pool_destroy(ahcd->td_cache);
+ ahcd->td_cache = NULL;
+err:
+ return -ENOMEM;
+}
+
+static void admhc_mem_cleanup(struct admhcd *ahcd)
+{
+ if (ahcd->td_cache) {
+ dma_pool_destroy(ahcd->td_cache);
+ ahcd->td_cache = NULL;
+ }
+
+ if (ahcd->ed_cache) {
+ dma_pool_destroy(ahcd->ed_cache);
+ ahcd->ed_cache = NULL;
+ }
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* ahcd "done list" processing needs this mapping */
+static inline struct td *dma_to_td(struct admhcd *ahcd, dma_addr_t td_dma)
+{
+ struct td *td;
+
+ td_dma &= TD_MASK;
+ td = ahcd->td_hash[TD_HASH_FUNC(td_dma)];
+ while (td && td->td_dma != td_dma)
+ td = td->td_hash;
+
+ return td;
+}
+
+/* TDs ... */
+static struct td *td_alloc(struct admhcd *ahcd, gfp_t mem_flags)
+{
+ dma_addr_t dma;
+ struct td *td;
+
+ td = dma_pool_alloc(ahcd->td_cache, mem_flags, &dma);
+ if (!td)
+ return NULL;
+
+ /* in case ahcd fetches it, make it look dead */
+ memset(td, 0, sizeof *td);
+ td->hwNextTD = cpu_to_hc32(ahcd, dma);
+ td->td_dma = dma;
+ /* hashed in td_fill */
+
+ return td;
+}
+
+static void td_free(struct admhcd *ahcd, struct td *td)
+{
+ struct td **prev = &ahcd->td_hash[TD_HASH_FUNC(td->td_dma)];
+
+ while (*prev && *prev != td)
+ prev = &(*prev)->td_hash;
+ if (*prev)
+ *prev = td->td_hash;
+#if 0
+ /* TODO: remove */
+ else if ((td->hwINFO & cpu_to_hc32(ahcd, TD_DONE)) != 0)
+ admhc_dbg (ahcd, "no hash for td %p\n", td);
+#else
+ else if ((td->flags & TD_FLAG_DONE) != 0)
+ admhc_dbg (ahcd, "no hash for td %p\n", td);
+#endif
+ dma_pool_free(ahcd->td_cache, td, td->td_dma);
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* EDs ... */
+static struct ed *ed_alloc(struct admhcd *ahcd, gfp_t mem_flags)
+{
+ dma_addr_t dma;
+ struct ed *ed;
+
+ ed = dma_pool_alloc(ahcd->ed_cache, mem_flags, &dma);
+ if (!ed)
+ return NULL;
+
+ memset(ed, 0, sizeof(*ed));
+ ed->dma = dma;
+
+ INIT_LIST_HEAD(&ed->td_list);
+ INIT_LIST_HEAD(&ed->urb_list);
+
+ return ed;
+}
+
+static void ed_free(struct admhcd *ahcd, struct ed *ed)
+{
+ dma_pool_free(ahcd->ed_cache, ed, ed->dma);
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* URB priv ... */
+static void urb_priv_free(struct admhcd *ahcd, struct urb_priv *urb_priv)
+{
+ int i;
+
+ for (i = 0; i < urb_priv->td_cnt; i++)
+ if (urb_priv->td[i])
+ td_free(ahcd, urb_priv->td[i]);
+
+ list_del(&urb_priv->pending);
+ kfree(urb_priv);
+}
+
+static struct urb_priv *urb_priv_alloc(struct admhcd *ahcd, int num_tds,
+ gfp_t mem_flags)
+{
+ struct urb_priv *priv;
+
+ /* allocate the private part of the URB */
+ priv = kzalloc(sizeof(*priv) + sizeof(struct td) * num_tds, mem_flags);
+ if (!priv)
+ goto err;
+
+ /* allocate the TDs (deferring hash chain updates) */
+ for (priv->td_cnt = 0; priv->td_cnt < num_tds; priv->td_cnt++) {
+ priv->td[priv->td_cnt] = td_alloc(ahcd, mem_flags);
+ if (priv->td[priv->td_cnt] == NULL)
+ goto err_free;
+ }
+
+ INIT_LIST_HEAD(&priv->pending);
+
+ return priv;
+
+err_free:
+ urb_priv_free(ahcd, priv);
+err:
+ return NULL;
+}
--- /dev/null
+/*
+ * ADM5120 HCD (Host Controller Driver) for USB
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This file was derived from fragments of the OHCI driver.
+ * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
+ * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#define OHCI_SCHED_ENABLES \
+ (OHCI_CTRL_CLE|OHCI_CTRL_BLE|OHCI_CTRL_PLE|OHCI_CTRL_IE)
+
+#ifdef CONFIG_PM
+static int admhc_restart(struct admhcd *ahcd);
+
+static int admhc_rh_suspend(struct admhcd *ahcd, int autostop)
+__releases(ahcd->lock)
+__acquires(ahcd->lock)
+{
+ int status = 0;
+
+ ahcd->hc_control = admhc_readl(ahcd, &ahcd->regs->control);
+ switch (ahcd->hc_control & OHCI_CTRL_HCFS) {
+ case OHCI_USB_RESUME:
+ admhc_dbg(ahcd, "resume/suspend?\n");
+ ahcd->hc_control &= ~OHCI_CTRL_HCFS;
+ ahcd->hc_control |= OHCI_USB_RESET;
+ admhc_writel(ahcd, ahcd->hc_control, &ahcd->ahcd->regs->control);
+ (void) admhc_readl(ahcd, &ahcd->regs->control);
+ /* FALL THROUGH */
+ case OHCI_USB_RESET:
+ status = -EBUSY;
+ admhc_dbg(ahcd, "needs reinit!\n");
+ goto done;
+ case OHCI_USB_SUSPEND:
+ if (!ahcd->autostop) {
+ admhc_dbg(ahcd, "already suspended\n");
+ goto done;
+ }
+ }
+ admhc_dbg(ahcd, "%s root hub\n",
+ autostop ? "auto-stop" : "suspend");
+
+ /* First stop any processing */
+ if (!autostop && (ahcd->hc_control & OHCI_SCHED_ENABLES)) {
+ ahcd->hc_control &= ~OHCI_SCHED_ENABLES;
+ admhc_writel(ahcd, ahcd->hc_control, &ahcd->ahcd->regs->control);
+ ahcd->hc_control = admhc_readl(ahcd, &ahcd->regs->control);
+ admhc_writel(ahcd, OHCI_INTR_SF, &ahcd->regs->intrstatus);
+
+ /* sched disables take effect on the next frame,
+ * then the last WDH could take 6+ msec
+ */
+ admhc_dbg(ahcd, "stopping schedules ...\n");
+ ahcd->autostop = 0;
+ spin_unlock_irq (&ahcd->lock);
+ msleep (8);
+ spin_lock_irq(&ahcd->lock);
+ }
+ dl_done_list (ahcd);
+ finish_unlinks (ahcd, admhc_frame_no(ahcd));
+
+ /* maybe resume can wake root hub */
+ if (device_may_wakeup(&admhcd_to_hcd(ahcd)->self.root_hub->dev) ||
+ autostop)
+ ahcd->hc_control |= OHCI_CTRL_RWE;
+ else {
+ admhc_writel(ahcd, OHCI_INTR_RHSC, &ahcd->regs->intrdisable);
+ ahcd->hc_control &= ~OHCI_CTRL_RWE;
+ }
+
+ /* Suspend hub ... this is the "global (to this bus) suspend" mode,
+ * which doesn't imply ports will first be individually suspended.
+ */
+ ahcd->hc_control &= ~OHCI_CTRL_HCFS;
+ ahcd->hc_control |= OHCI_USB_SUSPEND;
+ admhc_writel(ahcd, ahcd->hc_control, &ahcd->ahcd->regs->control);
+ (void) admhc_readl(ahcd, &ahcd->regs->control);
+
+ /* no resumes until devices finish suspending */
+ if (!autostop) {
+ ahcd->next_statechange = jiffies + msecs_to_jiffies (5);
+ ahcd->autostop = 0;
+ }
+
+done:
+ return status;
+}
+
+static inline struct ed *find_head(struct ed *ed)
+{
+ /* for bulk and control lists */
+ while (ed->ed_prev)
+ ed = ed->ed_prev;
+ return ed;
+}
+
+/* caller has locked the root hub */
+static int admhc_rh_resume(struct admhcd *ahcd)
+__releases(ahcd->lock)
+__acquires(ahcd->lock)
+{
+ struct usb_hcd *hcd = admhcd_to_hcd (ahcd);
+ u32 temp, enables;
+ int status = -EINPROGRESS;
+ int autostopped = ahcd->autostop;
+
+ ahcd->autostop = 0;
+ ahcd->hc_control = admhc_readl(ahcd, &ahcd->regs->control);
+
+ if (ahcd->hc_control & (OHCI_CTRL_IR | OHCI_SCHED_ENABLES)) {
+ /* this can happen after resuming a swsusp snapshot */
+ if (hcd->state == HC_STATE_RESUMING) {
+ admhc_dbg(ahcd, "BIOS/SMM active, control %03x\n",
+ ahcd->hc_control);
+ status = -EBUSY;
+ /* this happens when pmcore resumes HC then root */
+ } else {
+ admhc_dbg(ahcd, "duplicate resume\n");
+ status = 0;
+ }
+ } else switch (ahcd->hc_control & OHCI_CTRL_HCFS) {
+ case OHCI_USB_SUSPEND:
+ ahcd->hc_control &= ~(OHCI_CTRL_HCFS|OHCI_SCHED_ENABLES);
+ ahcd->hc_control |= OHCI_USB_RESUME;
+ admhc_writel(ahcd, ahcd->hc_control, &ahcd->ahcd->regs->control);
+ (void) admhc_readl(ahcd, &ahcd->regs->control);
+ admhc_dbg(ahcd, "%s root hub\n",
+ autostopped ? "auto-start" : "resume");
+ break;
+ case OHCI_USB_RESUME:
+ /* HCFS changes sometime after INTR_RD */
+ admhc_dbg(ahcd, "%swakeup root hub\n",
+ autostopped ? "auto-" : "");
+ break;
+ case OHCI_USB_OPER:
+ /* this can happen after resuming a swsusp snapshot */
+ admhc_dbg(ahcd, "snapshot resume? reinit\n");
+ status = -EBUSY;
+ break;
+ default: /* RESET, we lost power */
+ admhc_dbg(ahcd, "lost power\n");
+ status = -EBUSY;
+ }
+ if (status == -EBUSY) {
+ if (!autostopped) {
+ spin_unlock_irq (&ahcd->lock);
+ (void) ahcd_init (ahcd);
+ status = admhc_restart (ahcd);
+ spin_lock_irq(&ahcd->lock);
+ }
+ return status;
+ }
+ if (status != -EINPROGRESS)
+ return status;
+ if (autostopped)
+ goto skip_resume;
+ spin_unlock_irq (&ahcd->lock);
+
+ /* Some controllers (lucent erratum) need extra-long delays */
+ msleep (20 /* usb 11.5.1.10 */ + 12 /* 32 msec counter */ + 1);
+
+ temp = admhc_readl(ahcd, &ahcd->regs->control);
+ temp &= OHCI_CTRL_HCFS;
+ if (temp != OHCI_USB_RESUME) {
+ admhc_err (ahcd, "controller won't resume\n");
+ spin_lock_irq(&ahcd->lock);
+ return -EBUSY;
+ }
+
+ /* disable old schedule state, reinit from scratch */
+ admhc_writel(ahcd, 0, &ahcd->regs->ed_controlhead);
+ admhc_writel(ahcd, 0, &ahcd->regs->ed_controlcurrent);
+ admhc_writel(ahcd, 0, &ahcd->regs->ed_bulkhead);
+ admhc_writel(ahcd, 0, &ahcd->regs->ed_bulkcurrent);
+ admhc_writel(ahcd, 0, &ahcd->regs->ed_periodcurrent);
+ admhc_writel(ahcd, (u32) ahcd->hcca_dma, &ahcd->ahcd->regs->hcca);
+
+ /* Sometimes PCI D3 suspend trashes frame timings ... */
+ periodic_reinit(ahcd);
+
+ /* the following code is executed with ahcd->lock held and
+ * irqs disabled if and only if autostopped is true
+ */
+
+skip_resume:
+ /* interrupts might have been disabled */
+ admhc_writel(ahcd, OHCI_INTR_INIT, &ahcd->regs->int_enable);
+ if (ahcd->ed_rm_list)
+ admhc_writel(ahcd, OHCI_INTR_SF, &ahcd->regs->int_enable);
+
+ /* Then re-enable operations */
+ admhc_writel(ahcd, OHCI_USB_OPER, &ahcd->regs->control);
+ (void) admhc_readl(ahcd, &ahcd->regs->control);
+ if (!autostopped)
+ msleep (3);
+
+ temp = ahcd->hc_control;
+ temp &= OHCI_CTRL_RWC;
+ temp |= OHCI_CONTROL_INIT | OHCI_USB_OPER;
+ ahcd->hc_control = temp;
+ admhc_writel(ahcd, temp, &ahcd->regs->control);
+ (void) admhc_readl(ahcd, &ahcd->regs->control);
+
+ /* TRSMRCY */
+ if (!autostopped) {
+ msleep (10);
+ spin_lock_irq(&ahcd->lock);
+ }
+ /* now ahcd->lock is always held and irqs are always disabled */
+
+ /* keep it alive for more than ~5x suspend + resume costs */
+ ahcd->next_statechange = jiffies + STATECHANGE_DELAY;
+
+ /* maybe turn schedules back on */
+ enables = 0;
+ temp = 0;
+ if (!ahcd->ed_rm_list) {
+ if (ahcd->ed_controltail) {
+ admhc_writel(ahcd,
+ find_head (ahcd->ed_controltail)->dma,
+ &ahcd->regs->ed_controlhead);
+ enables |= OHCI_CTRL_CLE;
+ temp |= OHCI_CLF;
+ }
+ if (ahcd->ed_bulktail) {
+ admhc_writel(ahcd, find_head (ahcd->ed_bulktail)->dma,
+ &ahcd->regs->ed_bulkhead);
+ enables |= OHCI_CTRL_BLE;
+ temp |= OHCI_BLF;
+ }
+ }
+ if (hcd->self.bandwidth_isoc_reqs || hcd->self.bandwidth_int_reqs)
+ enables |= OHCI_CTRL_PLE|OHCI_CTRL_IE;
+ if (enables) {
+ admhc_dbg(ahcd, "restarting schedules ... %08x\n", enables);
+ ahcd->hc_control |= enables;
+ admhc_writel(ahcd, ahcd->hc_control, &ahcd->ahcd->regs->control);
+ if (temp)
+ admhc_writel(ahcd, temp, &ahcd->regs->cmdstatus);
+ (void) admhc_readl(ahcd, &ahcd->regs->control);
+ }
+
+ return 0;
+}
+
+static int admhc_bus_suspend(struct usb_hcd *hcd)
+{
+ struct admhcd *ahcd = hcd_to_admhcd(hcd);
+ int rc;
+
+ spin_lock_irq(&ahcd->lock);
+
+ if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)))
+ rc = -ESHUTDOWN;
+ else
+ rc = admhc_rh_suspend(ahcd, 0);
+ spin_unlock_irq(&ahcd->lock);
+ return rc;
+}
+
+static int admhc_bus_resume(struct usb_hcd *hcd)
+{
+ struct admhcd *ahcd = hcd_to_admhcd(hcd);
+ int rc;
+
+ if (time_before(jiffies, ahcd->next_statechange))
+ msleep(5);
+
+ spin_lock_irq(&ahcd->lock);
+
+ if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)))
+ rc = -ESHUTDOWN;
+ else
+ rc = admhc_rh_resume(ahcd);
+ spin_unlock_irq(&ahcd->lock);
+
+ /* poll until we know a device is connected or we autostop */
+ if (rc == 0)
+ usb_hcd_poll_rh_status(hcd);
+ return rc;
+}
+
+/* Carry out polling-, autostop-, and autoresume-related state changes */
+static int admhc_root_hub_state_changes(struct admhcd *ahcd, int changed,
+ int any_connected)
+{
+ int poll_rh = 1;
+
+ switch (ahcd->hc_control & OHCI_CTRL_HCFS) {
+
+ case OHCI_USB_OPER:
+ /* keep on polling until we know a device is connected
+ * and RHSC is enabled */
+ if (!ahcd->autostop) {
+ if (any_connected ||
+ !device_may_wakeup(&admhcd_to_hcd(ahcd)
+ ->self.root_hub->dev)) {
+ if (admhc_readl(ahcd, &ahcd->regs->int_enable) &
+ OHCI_INTR_RHSC)
+ poll_rh = 0;
+ } else {
+ ahcd->autostop = 1;
+ ahcd->next_statechange = jiffies + HZ;
+ }
+
+ /* if no devices have been attached for one second, autostop */
+ } else {
+ if (changed || any_connected) {
+ ahcd->autostop = 0;
+ ahcd->next_statechange = jiffies +
+ STATECHANGE_DELAY;
+ } else if (time_after_eq(jiffies,
+ ahcd->next_statechange)
+ && !ahcd->ed_rm_list
+ && !(ahcd->hc_control &
+ OHCI_SCHED_ENABLES)) {
+ ahcd_rh_suspend(ahcd, 1);
+ }
+ }
+ break;
+
+ /* if there is a port change, autostart or ask to be resumed */
+ case OHCI_USB_SUSPEND:
+ case OHCI_USB_RESUME:
+ if (changed) {
+ if (ahcd->autostop)
+ admhc_rh_resume(ahcd);
+ else
+ usb_hcd_resume_root_hub(admhcd_to_hcd(ahcd));
+ } else {
+ /* everything is idle, no need for polling */
+ poll_rh = 0;
+ }
+ break;
+ }
+ return poll_rh;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* must not be called from interrupt context */
+static int admhc_restart(struct admhcd *ahcd)
+{
+ int temp;
+ int i;
+ struct urb_priv *priv;
+
+ /* mark any devices gone, so they do nothing till khubd disconnects.
+ * recycle any "live" eds/tds (and urbs) right away.
+ * later, khubd disconnect processing will recycle the other state,
+ * (either as disconnect/reconnect, or maybe someday as a reset).
+ */
+ spin_lock_irq(&ahcd->lock);
+ admhc_disable(ahcd);
+ usb_root_hub_lost_power(admhcd_to_hcd(ahcd)->self.root_hub);
+ if (!list_empty(&ahcd->pending))
+ admhc_dbg(ahcd, "abort schedule...\n");
+ list_for_each_entry(priv, &ahcd->pending, pending) {
+ struct urb *urb = priv->td[0]->urb;
+ struct ed *ed = priv->ed;
+
+ switch (ed->state) {
+ case ED_OPER:
+ ed->state = ED_UNLINK;
+ ed->hwINFO |= cpu_to_hc32(ahcd, ED_DEQUEUE);
+ ed_deschedule (ahcd, ed);
+
+ ed->ed_next = ahcd->ed_rm_list;
+ ed->ed_prev = NULL;
+ ahcd->ed_rm_list = ed;
+ /* FALLTHROUGH */
+ case ED_UNLINK:
+ break;
+ default:
+ admhc_dbg(ahcd, "bogus ed %p state %d\n",
+ ed, ed->state);
+ }
+
+ if (!urb->unlinked)
+ urb->unlinked = -ESHUTDOWN;
+ }
+ finish_unlinks(ahcd, 0);
+ spin_unlock_irq(&ahcd->lock);
+
+ /* paranoia, in case that didn't work: */
+
+ /* empty the interrupt branches */
+ for (i = 0; i < NUM_INTS; i++) ahcd->load[i] = 0;
+ for (i = 0; i < NUM_INTS; i++) ahcd->hcca->int_table[i] = 0;
+
+ /* no EDs to remove */
+ ahcd->ed_rm_list = NULL;
+
+ /* empty control and bulk lists */
+ ahcd->ed_controltail = NULL;
+ ahcd->ed_bulktail = NULL;
+
+ if ((temp = admhc_run(ahcd)) < 0) {
+ admhc_err(ahcd, "can't restart, %d\n", temp);
+ return temp;
+ } else {
+ /* here we "know" root ports should always stay powered,
+ * and that if we try to turn them back on the root hub
+ * will respond to CSC processing.
+ */
+ i = ahcd->num_ports;
+ while (i--)
+ admhc_writel(ahcd, RH_PS_PSS,
+ &ahcd->regs->portstatus[i]);
+ admhc_dbg(ahcd, "restart complete\n");
+ }
+ return 0;
+}
+
+#else /* CONFIG_PM */
+
+static inline int admhc_rh_resume(struct admhcd *ahcd)
+{
+ return 0;
+}
+
+/* Carry out polling-related state changes.
+ * autostop isn't used when CONFIG_PM is turned off.
+ */
+static int admhc_root_hub_state_changes(struct admhcd *ahcd, int changed,
+ int any_connected)
+{
+ int poll_rh = 1;
+
+ /* keep on polling until RHSC is enabled */
+ if (admhc_readl(ahcd, &ahcd->regs->int_enable) & ADMHC_INTR_INSM)
+ poll_rh = 0;
+
+ return poll_rh;
+}
+
+#endif /* CONFIG_PM */
+
--- /dev/null
+/*
+ * ADM5120 HCD (Host Controller Driver) for USB
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This file was derived from: drivers/usb/host/ohci-q.c
+ * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
+ * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/irq.h>
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * URB goes back to driver, and isn't reissued.
+ * It's completely gone from HC data structures.
+ * PRECONDITION: ahcd lock held, irqs blocked.
+ */
+static void
+finish_urb(struct admhcd *ahcd, struct urb *urb, int status)
+__releases(ahcd->lock)
+__acquires(ahcd->lock)
+{
+ urb_priv_free(ahcd, urb->hcpriv);
+
+ if (likely(status == -EINPROGRESS))
+ status = 0;
+
+ switch (usb_pipetype(urb->pipe)) {
+ case PIPE_ISOCHRONOUS:
+ admhcd_to_hcd(ahcd)->self.bandwidth_isoc_reqs--;
+ break;
+ case PIPE_INTERRUPT:
+ admhcd_to_hcd(ahcd)->self.bandwidth_int_reqs--;
+ break;
+ }
+
+#ifdef ADMHC_VERBOSE_DEBUG
+ urb_print(ahcd, urb, "RET", usb_pipeout (urb->pipe), status);
+#endif
+
+ /* urb->complete() can reenter this HCD */
+ usb_hcd_unlink_urb_from_ep(admhcd_to_hcd(ahcd), urb);
+ spin_unlock(&ahcd->lock);
+ usb_hcd_giveback_urb(admhcd_to_hcd(ahcd), urb, status);
+ spin_lock(&ahcd->lock);
+}
+
+
+/*-------------------------------------------------------------------------*
+ * ED handling functions
+ *-------------------------------------------------------------------------*/
+
+#if 0 /* FIXME */
+/* search for the right schedule branch to use for a periodic ed.
+ * does some load balancing; returns the branch, or negative errno.
+ */
+static int balance(struct admhcd *ahcd, int interval, int load)
+{
+ int i, branch = -ENOSPC;
+
+ /* iso periods can be huge; iso tds specify frame numbers */
+ if (interval > NUM_INTS)
+ interval = NUM_INTS;
+
+ /* search for the least loaded schedule branch of that period
+ * that has enough bandwidth left unreserved.
+ */
+ for (i = 0; i < interval ; i++) {
+ if (branch < 0 || ahcd->load [branch] > ahcd->load [i]) {
+ int j;
+
+ /* usb 1.1 says 90% of one frame */
+ for (j = i; j < NUM_INTS; j += interval) {
+ if ((ahcd->load [j] + load) > 900)
+ break;
+ }
+ if (j < NUM_INTS)
+ continue;
+ branch = i;
+ }
+ }
+ return branch;
+}
+#endif
+
+/*-------------------------------------------------------------------------*/
+
+#if 0 /* FIXME */
+/* both iso and interrupt requests have periods; this routine puts them
+ * into the schedule tree in the apppropriate place. most iso devices use
+ * 1msec periods, but that's not required.
+ */
+static void periodic_link (struct admhcd *ahcd, struct ed *ed)
+{
+ unsigned i;
+
+ admhc_vdbg (ahcd, "link %sed %p branch %d [%dus.], interval %d\n",
+ (ed->hwINFO & cpu_to_hc32(ahcd, ED_ISO)) ? "iso " : "",
+ ed, ed->branch, ed->load, ed->interval);
+
+ for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
+ struct ed **prev = &ahcd->periodic [i];
+ __hc32 *prev_p = &ahcd->hcca->int_table [i];
+ struct ed *here = *prev;
+
+ /* sorting each branch by period (slow before fast)
+ * lets us share the faster parts of the tree.
+ * (plus maybe: put interrupt eds before iso)
+ */
+ while (here && ed != here) {
+ if (ed->interval > here->interval)
+ break;
+ prev = &here->ed_next;
+ prev_p = &here->hwNextED;
+ here = *prev;
+ }
+ if (ed != here) {
+ ed->ed_next = here;
+ if (here)
+ ed->hwNextED = *prev_p;
+ wmb ();
+ *prev = ed;
+ *prev_p = cpu_to_hc32(ahcd, ed->dma);
+ wmb();
+ }
+ ahcd->load [i] += ed->load;
+ }
+ admhcd_to_hcd(ahcd)->self.bandwidth_allocated += ed->load / ed->interval;
+}
+#endif
+
+/* link an ed into the HC chain */
+
+static int ed_schedule(struct admhcd *ahcd, struct ed *ed)
+{
+ struct ed *old_tail;
+
+ if (admhcd_to_hcd(ahcd)->state == HC_STATE_QUIESCING)
+ return -EAGAIN;
+
+ ed->state = ED_OPER;
+
+ old_tail = ahcd->ed_tails[ed->type];
+
+ ed->ed_next = old_tail->ed_next;
+ if (ed->ed_next) {
+ ed->ed_next->ed_prev = ed;
+ ed->hwNextED = cpu_to_hc32(ahcd, ed->ed_next->dma);
+ }
+ ed->ed_prev = old_tail;
+
+ old_tail->ed_next = ed;
+ old_tail->hwNextED = cpu_to_hc32(ahcd, ed->dma);
+
+ ahcd->ed_tails[ed->type] = ed;
+
+ admhc_dma_enable(ahcd);
+
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+#if 0 /* FIXME */
+/* scan the periodic table to find and unlink this ED */
+static void periodic_unlink (struct admhcd *ahcd, struct ed *ed)
+{
+ int i;
+
+ for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
+ struct ed *temp;
+ struct ed **prev = &ahcd->periodic [i];
+ __hc32 *prev_p = &ahcd->hcca->int_table [i];
+
+ while (*prev && (temp = *prev) != ed) {
+ prev_p = &temp->hwNextED;
+ prev = &temp->ed_next;
+ }
+ if (*prev) {
+ *prev_p = ed->hwNextED;
+ *prev = ed->ed_next;
+ }
+ ahcd->load [i] -= ed->load;
+ }
+
+ admhcd_to_hcd(ahcd)->self.bandwidth_allocated -= ed->load / ed->interval;
+ admhc_vdbg (ahcd, "unlink %sed %p branch %d [%dus.], interval %d\n",
+ (ed->hwINFO & cpu_to_hc32(ahcd, ED_ISO)) ? "iso " : "",
+ ed, ed->branch, ed->load, ed->interval);
+}
+#endif
+
+/* unlink an ed from the HC chain.
+ * just the link to the ed is unlinked.
+ * the link from the ed still points to another operational ed or 0
+ * so the HC can eventually finish the processing of the unlinked ed
+ * (assuming it already started that, which needn't be true).
+ *
+ * ED_UNLINK is a transient state: the HC may still see this ED, but soon
+ * it won't. ED_SKIP means the HC will finish its current transaction,
+ * but won't start anything new. The TD queue may still grow; device
+ * drivers don't know about this HCD-internal state.
+ *
+ * When the HC can't see the ED, something changes ED_UNLINK to one of:
+ *
+ * - ED_OPER: when there's any request queued, the ED gets rescheduled
+ * immediately. HC should be working on them.
+ *
+ * - ED_IDLE: when there's no TD queue. there's no reason for the HC
+ * to care about this ED; safe to disable the endpoint.
+ *
+ * When finish_unlinks() runs later, after SOF interrupt, it will often
+ * complete one or more URB unlinks before making that state change.
+ */
+static void ed_deschedule(struct admhcd *ahcd, struct ed *ed)
+{
+
+#ifdef ADMHC_VERBOSE_DEBUG
+ admhc_dump_ed(ahcd, "ED-DESCHED", ed, 1);
+#endif
+
+ ed->hwINFO |= cpu_to_hc32(ahcd, ED_SKIP);
+ wmb();
+ ed->state = ED_UNLINK;
+
+ /* remove this ED from the HC list */
+ ed->ed_prev->hwNextED = ed->hwNextED;
+
+ /* and remove it from our list also */
+ ed->ed_prev->ed_next = ed->ed_next;
+
+ if (ed->ed_next)
+ ed->ed_next->ed_prev = ed->ed_prev;
+
+ if (ahcd->ed_tails[ed->type] == ed)
+ ahcd->ed_tails[ed->type] = ed->ed_prev;
+}
+
+/*-------------------------------------------------------------------------*/
+
+static struct ed *ed_create(struct admhcd *ahcd, unsigned int type, u32 info)
+{
+ struct ed *ed;
+ struct td *td;
+
+ ed = ed_alloc(ahcd, GFP_ATOMIC);
+ if (!ed)
+ goto err;
+
+ /* dummy td; end of td list for this ed */
+ td = td_alloc(ahcd, GFP_ATOMIC);
+ if (!td)
+ goto err_free_ed;
+
+ switch (type) {
+ case PIPE_INTERRUPT:
+ info |= ED_INT;
+ break;
+ case PIPE_ISOCHRONOUS:
+ info |= ED_ISO;
+ break;
+ }
+
+ ed->dummy = td;
+ ed->state = ED_IDLE;
+ ed->type = type;
+
+ ed->hwINFO = cpu_to_hc32(ahcd, info);
+ ed->hwTailP = cpu_to_hc32(ahcd, td->td_dma);
+ ed->hwHeadP = ed->hwTailP; /* ED_C, ED_H zeroed */
+
+ return ed;
+
+err_free_ed:
+ ed_free(ahcd, ed);
+err:
+ return NULL;
+}
+
+/* get and maybe (re)init an endpoint. init _should_ be done only as part
+ * of enumeration, usb_set_configuration() or usb_set_interface().
+ */
+static struct ed *ed_get(struct admhcd *ahcd, struct usb_host_endpoint *ep,
+ struct usb_device *udev, unsigned int pipe, int interval)
+{
+ struct ed *ed;
+ unsigned long flags;
+
+ spin_lock_irqsave(&ahcd->lock, flags);
+
+ ed = ep->hcpriv;
+ if (!ed) {
+ u32 info;
+
+ /* FIXME: usbcore changes dev->devnum before SET_ADDRESS
+ * suceeds ... otherwise we wouldn't need "pipe".
+ */
+ info = usb_pipedevice(pipe);
+ info |= (ep->desc.bEndpointAddress & ~USB_DIR_IN) << ED_EN_SHIFT;
+ info |= le16_to_cpu(ep->desc.wMaxPacketSize) << ED_MPS_SHIFT;
+ if (udev->speed == USB_SPEED_FULL)
+ info |= ED_SPEED_FULL;
+
+ ed = ed_create(ahcd, usb_pipetype(pipe), info);
+ if (ed)
+ ep->hcpriv = ed;
+ }
+
+ spin_unlock_irqrestore(&ahcd->lock, flags);
+
+ return ed;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* request unlinking of an endpoint from an operational HC.
+ * put the ep on the rm_list
+ * real work is done at the next start frame (SOFI) hardware interrupt
+ * caller guarantees HCD is running, so hardware access is safe,
+ * and that ed->state is ED_OPER
+ */
+static void start_ed_unlink(struct admhcd *ahcd, struct ed *ed)
+{
+
+#ifdef ADMHC_VERBOSE_DEBUG
+ admhc_dump_ed(ahcd, "ED-UNLINK", ed, 1);
+#endif
+
+ ed->hwINFO |= cpu_to_hc32(ahcd, ED_DEQUEUE);
+ ed_deschedule(ahcd, ed);
+
+ /* add this ED into the remove list */
+ ed->ed_rm_next = ahcd->ed_rm_list;
+ ahcd->ed_rm_list = ed;
+
+ /* enable SOF interrupt */
+ admhc_intr_ack(ahcd, ADMHC_INTR_SOFI);
+ admhc_intr_enable(ahcd, ADMHC_INTR_SOFI);
+ /* flush those writes */
+ admhc_writel_flush(ahcd);
+
+ /* SOF interrupt might get delayed; record the frame counter value that
+ * indicates when the HC isn't looking at it, so concurrent unlinks
+ * behave. frame_no wraps every 2^16 msec, and changes right before
+ * SOF is triggered.
+ */
+ ed->tick = admhc_frame_no(ahcd) + 1;
+}
+
+/*-------------------------------------------------------------------------*
+ * TD handling functions
+ *-------------------------------------------------------------------------*/
+
+/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
+
+static void
+td_fill(struct admhcd *ahcd, u32 info, dma_addr_t data, int len,
+ struct urb *urb, int index)
+{
+ struct td *td, *td_pt;
+ struct urb_priv *urb_priv = urb->hcpriv;
+ int hash;
+ u32 cbl = 0;
+
+#if 1
+ if (index == (urb_priv->td_cnt - 1) &&
+ ((urb->transfer_flags & URB_NO_INTERRUPT) == 0))
+ cbl |= TD_IE;
+#else
+ if (index == (urb_priv->td_cnt - 1))
+ cbl |= TD_IE;
+#endif
+
+ /* use this td as the next dummy */
+ td_pt = urb_priv->td[index];
+
+ /* fill the old dummy TD */
+ td = urb_priv->td[index] = urb_priv->ed->dummy;
+ urb_priv->ed->dummy = td_pt;
+
+ td->ed = urb_priv->ed;
+ td->next_dl_td = NULL;
+ td->index = index;
+ td->urb = urb;
+ td->data_dma = data;
+ if (!len)
+ data = 0;
+
+ if (data)
+ cbl |= (len & TD_BL_MASK);
+
+ info |= TD_OWN;
+
+ /* setup hardware specific fields */
+ td->hwINFO = cpu_to_hc32(ahcd, info);
+ td->hwDBP = cpu_to_hc32(ahcd, data);
+ td->hwCBL = cpu_to_hc32(ahcd, cbl);
+ td->hwNextTD = cpu_to_hc32(ahcd, td_pt->td_dma);
+
+ /* append to queue */
+ list_add_tail(&td->td_list, &td->ed->td_list);
+
+ /* hash it for later reverse mapping */
+ hash = TD_HASH_FUNC(td->td_dma);
+ td->td_hash = ahcd->td_hash[hash];
+ ahcd->td_hash[hash] = td;
+
+ /* HC might read the TD (or cachelines) right away ... */
+ wmb();
+ td->ed->hwTailP = td->hwNextTD;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* Prepare all TDs of a transfer, and queue them onto the ED.
+ * Caller guarantees HC is active.
+ * Usually the ED is already on the schedule, so TDs might be
+ * processed as soon as they're queued.
+ */
+static void td_submit_urb(struct admhcd *ahcd, struct urb *urb)
+{
+ struct urb_priv *urb_priv = urb->hcpriv;
+ dma_addr_t data;
+ int data_len = urb->transfer_buffer_length;
+ int cnt = 0;
+ u32 info = 0;
+ int is_out = usb_pipeout(urb->pipe);
+ u32 toggle = 0;
+
+ /* OHCI handles the bulk/interrupt data toggles itself. We just
+ * use the device toggle bits for resetting, and rely on the fact
+ * that resetting toggle is meaningless if the endpoint is active.
+ */
+
+ if (usb_gettoggle(urb->dev, usb_pipeendpoint(urb->pipe), is_out)) {
+ toggle = TD_T_CARRY;
+ } else {
+ toggle = TD_T_DATA0;
+ usb_settoggle(urb->dev, usb_pipeendpoint (urb->pipe),
+ is_out, 1);
+ }
+
+ urb_priv->td_idx = 0;
+ list_add(&urb_priv->pending, &ahcd->pending);
+
+ if (data_len)
+ data = urb->transfer_dma;
+ else
+ data = 0;
+
+ /* NOTE: TD_CC is set so we can tell which TDs the HC processed by
+ * using TD_CC_GET, as well as by seeing them on the done list.
+ * (CC = NotAccessed ... 0x0F, or 0x0E in PSWs for ISO.)
+ */
+ switch (urb_priv->ed->type) {
+ case PIPE_INTERRUPT:
+ info = is_out
+ ? TD_T_CARRY | TD_SCC_NOTACCESSED | TD_DP_OUT
+ : TD_T_CARRY | TD_SCC_NOTACCESSED | TD_DP_IN;
+
+ /* setup service interval and starting frame number */
+ info |= (urb->start_frame & TD_FN_MASK);
+ info |= (urb->interval & TD_ISI_MASK) << TD_ISI_SHIFT;
+
+ td_fill(ahcd, info, data, data_len, urb, cnt);
+ cnt++;
+
+ admhcd_to_hcd(ahcd)->self.bandwidth_int_reqs++;
+ break;
+
+ case PIPE_BULK:
+ info = is_out
+ ? TD_SCC_NOTACCESSED | TD_DP_OUT
+ : TD_SCC_NOTACCESSED | TD_DP_IN;
+
+ /* TDs _could_ transfer up to 8K each */
+ while (data_len > TD_DATALEN_MAX) {
+ td_fill(ahcd, info | ((cnt) ? TD_T_CARRY : toggle),
+ data, TD_DATALEN_MAX, urb, cnt);
+ data += TD_DATALEN_MAX;
+ data_len -= TD_DATALEN_MAX;
+ cnt++;
+ }
+
+ td_fill(ahcd, info | ((cnt) ? TD_T_CARRY : toggle), data,
+ data_len, urb, cnt);
+ cnt++;
+
+ if ((urb->transfer_flags & URB_ZERO_PACKET)
+ && (cnt < urb_priv->td_cnt)) {
+ td_fill(ahcd, info | ((cnt) ? TD_T_CARRY : toggle),
+ 0, 0, urb, cnt);
+ cnt++;
+ }
+ break;
+
+ /* control manages DATA0/DATA1 toggle per-request; SETUP resets it,
+ * any DATA phase works normally, and the STATUS ack is special.
+ */
+ case PIPE_CONTROL:
+ /* fill a TD for the setup */
+ info = TD_SCC_NOTACCESSED | TD_DP_SETUP | TD_T_DATA0;
+ td_fill(ahcd, info, urb->setup_dma, 8, urb, cnt++);
+
+ if (data_len > 0) {
+ /* fill a TD for the data */
+ info = TD_SCC_NOTACCESSED | TD_T_DATA1;
+ info |= is_out ? TD_DP_OUT : TD_DP_IN;
+ /* NOTE: mishandles transfers >8K, some >4K */
+ td_fill(ahcd, info, data, data_len, urb, cnt++);
+ }
+
+ /* fill a TD for the ACK */
+ info = (is_out || data_len == 0)
+ ? TD_SCC_NOTACCESSED | TD_DP_IN | TD_T_DATA1
+ : TD_SCC_NOTACCESSED | TD_DP_OUT | TD_T_DATA1;
+ td_fill(ahcd, info, data, 0, urb, cnt++);
+
+ break;
+
+ /* ISO has no retransmit, so no toggle;
+ * Each TD could handle multiple consecutive frames (interval 1);
+ * we could often reduce the number of TDs here.
+ */
+ case PIPE_ISOCHRONOUS:
+ info = is_out
+ ? TD_T_CARRY | TD_SCC_NOTACCESSED | TD_DP_OUT
+ : TD_T_CARRY | TD_SCC_NOTACCESSED | TD_DP_IN;
+
+ for (cnt = 0; cnt < urb->number_of_packets; cnt++) {
+ int frame = urb->start_frame;
+
+ frame += cnt * urb->interval;
+ frame &= TD_FN_MASK;
+ td_fill(ahcd, info | frame,
+ data + urb->iso_frame_desc[cnt].offset,
+ urb->iso_frame_desc[cnt].length, urb, cnt);
+ }
+ admhcd_to_hcd(ahcd)->self.bandwidth_isoc_reqs++;
+ break;
+ }
+
+ if (urb_priv->td_cnt != cnt)
+ admhc_err(ahcd, "bad number of tds created for urb %p\n", urb);
+}
+
+/*-------------------------------------------------------------------------*
+ * Done List handling functions
+ *-------------------------------------------------------------------------*/
+
+/* calculate transfer length/status and update the urb */
+static int td_done(struct admhcd *ahcd, struct urb *urb, struct td *td)
+{
+ struct urb_priv *urb_priv = urb->hcpriv;
+ u32 info;
+ u32 bl;
+ u32 tdDBP;
+ int type = usb_pipetype(urb->pipe);
+ int cc;
+ int status = -EINPROGRESS;
+
+ info = hc32_to_cpup(ahcd, &td->hwINFO);
+ tdDBP = hc32_to_cpup(ahcd, &td->hwDBP);
+ bl = TD_BL_GET(hc32_to_cpup(ahcd, &td->hwCBL));
+ cc = TD_CC_GET(info);
+
+ /* ISO ... drivers see per-TD length/status */
+ if (type == PIPE_ISOCHRONOUS) {
+ /* TODO */
+ int dlen = 0;
+
+ /* NOTE: assumes FC in tdINFO == 0, and that
+ * only the first of 0..MAXPSW psws is used.
+ */
+ if (info & TD_CC) /* hc didn't touch? */
+ return status;
+
+ if (usb_pipeout(urb->pipe))
+ dlen = urb->iso_frame_desc[td->index].length;
+ else {
+ /* short reads are always OK for ISO */
+ if (cc == TD_CC_DATAUNDERRUN)
+ cc = TD_CC_NOERROR;
+ dlen = tdDBP - td->data_dma + bl;
+ }
+
+ urb->actual_length += dlen;
+ urb->iso_frame_desc[td->index].actual_length = dlen;
+ urb->iso_frame_desc[td->index].status = cc_to_error[cc];
+
+ if (cc != TD_CC_NOERROR)
+ admhc_vdbg (ahcd,
+ "urb %p iso td %p (%d) len %d cc %d\n",
+ urb, td, 1 + td->index, dlen, cc);
+
+ /* BULK, INT, CONTROL ... drivers see aggregate length/status,
+ * except that "setup" bytes aren't counted and "short" transfers
+ * might not be reported as errors.
+ */
+ } else {
+ /* update packet status if needed (short is normally ok) */
+ if (cc == TD_CC_DATAUNDERRUN
+ && !(urb->transfer_flags & URB_SHORT_NOT_OK))
+ cc = TD_CC_NOERROR;
+
+ if (cc != TD_CC_NOERROR && cc < TD_CC_HCD0)
+ status = cc_to_error[cc];
+
+
+ /* count all non-empty packets except control SETUP packet */
+ if ((type != PIPE_CONTROL || td->index != 0) && tdDBP != 0) {
+ urb->actual_length += tdDBP - td->data_dma + bl;
+ }
+
+ if (cc != TD_CC_NOERROR && cc < TD_CC_HCD0)
+ admhc_vdbg(ahcd,
+ "urb %p td %p (%d) cc %d, len=%d/%d\n",
+ urb, td, td->index, cc,
+ urb->actual_length,
+ urb->transfer_buffer_length);
+ }
+
+ list_del(&td->td_list);
+ urb_priv->td_idx++;
+
+ return status;
+}
+
+/*-------------------------------------------------------------------------*/
+
+static inline void
+ed_halted(struct admhcd *ahcd, struct td *td, int cc, struct td *rev)
+{
+ struct urb *urb = td->urb;
+ struct urb_priv *urb_priv = urb->hcpriv;
+ struct ed *ed = td->ed;
+ struct list_head *tmp = td->td_list.next;
+ __hc32 toggle = ed->hwHeadP & cpu_to_hc32(ahcd, ED_C);
+
+ admhc_dump_ed(ahcd, "ed halted", td->ed, 1);
+ /* clear ed halt; this is the td that caused it, but keep it inactive
+ * until its urb->complete() has a chance to clean up.
+ */
+ ed->hwINFO |= cpu_to_hc32(ahcd, ED_SKIP);
+ wmb();
+ ed->hwHeadP &= ~cpu_to_hc32(ahcd, ED_H);
+
+ /* Get rid of all later tds from this urb. We don't have
+ * to be careful: no errors and nothing was transferred.
+ * Also patch the ed so it looks as if those tds completed normally.
+ */
+ while (tmp != &ed->td_list) {
+ struct td *next;
+
+ next = list_entry(tmp, struct td, td_list);
+ tmp = next->td_list.next;
+
+ if (next->urb != urb)
+ break;
+
+ /* NOTE: if multi-td control DATA segments get supported,
+ * this urb had one of them, this td wasn't the last td
+ * in that segment (TD_R clear), this ed halted because
+ * of a short read, _and_ URB_SHORT_NOT_OK is clear ...
+ * then we need to leave the control STATUS packet queued
+ * and clear ED_SKIP.
+ */
+ list_del(&next->td_list);
+ urb_priv->td_cnt++;
+ ed->hwHeadP = next->hwNextTD | toggle;
+ }
+
+ /* help for troubleshooting: report anything that
+ * looks odd ... that doesn't include protocol stalls
+ * (or maybe some other things)
+ */
+ switch (cc) {
+ case TD_CC_DATAUNDERRUN:
+ if ((urb->transfer_flags & URB_SHORT_NOT_OK) == 0)
+ break;
+ /* fallthrough */
+ case TD_CC_STALL:
+ if (usb_pipecontrol(urb->pipe))
+ break;
+ /* fallthrough */
+ default:
+ admhc_dbg (ahcd,
+ "urb %p path %s ep%d%s %08x cc %d --> status %d\n",
+ urb, urb->dev->devpath,
+ usb_pipeendpoint (urb->pipe),
+ usb_pipein (urb->pipe) ? "in" : "out",
+ hc32_to_cpu(ahcd, td->hwINFO),
+ cc, cc_to_error [cc]);
+ }
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* there are some urbs/eds to unlink; called in_irq(), with HCD locked */
+static void
+finish_unlinks(struct admhcd *ahcd, u16 tick)
+{
+ struct ed *ed, **last;
+
+rescan_all:
+ for (last = &ahcd->ed_rm_list, ed = *last; ed != NULL; ed = *last) {
+ struct list_head *entry, *tmp;
+ int completed, modified;
+ __hc32 *prev;
+
+ /* only take off EDs that the HC isn't using, accounting for
+ * frame counter wraps and EDs with partially retired TDs
+ */
+ if (likely(HC_IS_RUNNING(admhcd_to_hcd(ahcd)->state))) {
+ if (tick_before (tick, ed->tick)) {
+skip_ed:
+ last = &ed->ed_rm_next;
+ continue;
+ }
+#if 0
+ if (!list_empty(&ed->td_list)) {
+ struct td *td;
+ u32 head;
+
+ td = list_entry(ed->td_list.next, struct td,
+ td_list);
+ head = hc32_to_cpu(ahcd, ed->hwHeadP) &
+ TD_MASK;
+
+ /* INTR_WDH may need to clean up first */
+ if (td->td_dma != head)
+ goto skip_ed;
+ }
+#endif
+ }
+
+ /* reentrancy: if we drop the schedule lock, someone might
+ * have modified this list. normally it's just prepending
+ * entries (which we'd ignore), but paranoia won't hurt.
+ */
+ *last = ed->ed_rm_next;
+ ed->ed_rm_next = NULL;
+ modified = 0;
+
+ /* unlink urbs as requested, but rescan the list after
+ * we call a completion since it might have unlinked
+ * another (earlier) urb
+ *
+ * When we get here, the HC doesn't see this ed. But it
+ * must not be rescheduled until all completed URBs have
+ * been given back to the driver.
+ */
+rescan_this:
+ completed = 0;
+ prev = &ed->hwHeadP;
+ list_for_each_safe(entry, tmp, &ed->td_list) {
+ struct td *td;
+ struct urb *urb;
+ struct urb_priv *urb_priv;
+ __hc32 savebits;
+ int status;
+
+ td = list_entry(entry, struct td, td_list);
+ urb = td->urb;
+ urb_priv = td->urb->hcpriv;
+
+ if (!urb->unlinked) {
+ prev = &td->hwNextTD;
+ continue;
+ }
+
+ if ((urb_priv) == NULL)
+ continue;
+
+ /* patch pointer hc uses */
+ savebits = *prev & ~cpu_to_hc32(ahcd, TD_MASK);
+ *prev = td->hwNextTD | savebits;
+
+ /* HC may have partly processed this TD */
+#ifdef ADMHC_VERBOSE_DEBUG
+ urb_print(ahcd, urb, "PARTIAL", 0);
+#endif
+ status = td_done(ahcd, urb, td);
+
+ /* if URB is done, clean up */
+ if (urb_priv->td_idx == urb_priv->td_cnt) {
+ modified = completed = 1;
+ finish_urb(ahcd, urb, status);
+ }
+ }
+ if (completed && !list_empty(&ed->td_list))
+ goto rescan_this;
+
+ /* ED's now officially unlinked, hc doesn't see */
+ ed->state = ED_IDLE;
+ ed->hwHeadP &= ~cpu_to_hc32(ahcd, ED_H);
+ ed->hwNextED = 0;
+ wmb();
+ ed->hwINFO &= ~cpu_to_hc32(ahcd, ED_SKIP | ED_DEQUEUE);
+
+ /* but if there's work queued, reschedule */
+ if (!list_empty(&ed->td_list)) {
+ if (HC_IS_RUNNING(admhcd_to_hcd(ahcd)->state))
+ ed_schedule(ahcd, ed);
+ }
+
+ if (modified)
+ goto rescan_all;
+ }
+}
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * Process normal completions (error or success) and clean the schedules.
+ *
+ * This is the main path for handing urbs back to drivers. The only other
+ * path is finish_unlinks(), which unlinks URBs using ed_rm_list, instead of
+ * scanning the (re-reversed) donelist as this does.
+ */
+
+static void ed_unhalt(struct admhcd *ahcd, struct ed *ed, struct urb *urb)
+{
+ struct list_head *entry,*tmp;
+ __hc32 toggle = ed->hwHeadP & cpu_to_hc32(ahcd, ED_C);
+
+#ifdef ADMHC_VERBOSE_DEBUG
+ admhc_dump_ed(ahcd, "UNHALT", ed, 0);
+#endif
+ /* clear ed halt; this is the td that caused it, but keep it inactive
+ * until its urb->complete() has a chance to clean up.
+ */
+ ed->hwINFO |= cpu_to_hc32(ahcd, ED_SKIP);
+ wmb();
+ ed->hwHeadP &= ~cpu_to_hc32(ahcd, ED_H);
+
+ list_for_each_safe(entry, tmp, &ed->td_list) {
+ struct td *td = list_entry(entry, struct td, td_list);
+ __hc32 info;
+
+ if (td->urb != urb)
+ break;
+
+ info = td->hwINFO;
+ info &= ~cpu_to_hc32(ahcd, TD_CC | TD_OWN);
+ td->hwINFO = info;
+
+ ed->hwHeadP = td->hwNextTD | toggle;
+ wmb();
+ }
+
+}
+
+static void ed_intr_refill(struct admhcd *ahcd, struct ed *ed)
+{
+ __hc32 toggle = ed->hwHeadP & cpu_to_hc32(ahcd, ED_C);
+
+ ed->hwHeadP = ed->hwTailP | toggle;
+}
+
+
+static inline int is_ed_halted(struct admhcd *ahcd, struct ed *ed)
+{
+ return ((hc32_to_cpup(ahcd, &ed->hwHeadP) & ED_H) == ED_H);
+}
+
+static inline int is_td_halted(struct admhcd *ahcd, struct ed *ed,
+ struct td *td)
+{
+ return ((hc32_to_cpup(ahcd, &ed->hwHeadP) & TD_MASK) ==
+ (hc32_to_cpup(ahcd, &td->hwNextTD) & TD_MASK));
+}
+
+static void ed_update(struct admhcd *ahcd, struct ed *ed)
+{
+ struct list_head *entry,*tmp;
+
+#ifdef ADMHC_VERBOSE_DEBUG
+ admhc_dump_ed(ahcd, "UPDATE", ed, 1);
+#endif
+
+ list_for_each_safe(entry, tmp, &ed->td_list) {
+ struct td *td = list_entry(entry, struct td, td_list);
+ struct urb *urb = td->urb;
+ struct urb_priv *urb_priv = urb->hcpriv;
+ int status;
+
+ if (hc32_to_cpup(ahcd, &td->hwINFO) & TD_OWN)
+ break;
+
+ /* update URB's length and status from TD */
+ status = td_done(ahcd, urb, td);
+ if (is_ed_halted(ahcd, ed) && is_td_halted(ahcd, ed, td))
+ ed_unhalt(ahcd, ed, urb);
+
+ if (ed->type == PIPE_INTERRUPT)
+ ed_intr_refill(ahcd,ed);
+
+ /* If all this urb's TDs are done, call complete() */
+ if (urb_priv->td_idx == urb_priv->td_cnt)
+ finish_urb(ahcd, urb, status);
+
+ /* clean schedule: unlink EDs that are no longer busy */
+ if (list_empty(&ed->td_list)) {
+ if (ed->state == ED_OPER)
+ start_ed_unlink(ahcd, ed);
+
+ /* ... reenabling halted EDs only after fault cleanup */
+ } else if ((ed->hwINFO & cpu_to_hc32(ahcd,
+ ED_SKIP | ED_DEQUEUE))
+ == cpu_to_hc32(ahcd, ED_SKIP)) {
+ td = list_entry(ed->td_list.next, struct td, td_list);
+#if 0
+ if (!(td->hwINFO & cpu_to_hc32(ahcd, TD_DONE))) {
+ ed->hwINFO &= ~cpu_to_hc32(ahcd, ED_SKIP);
+ /* ... hc may need waking-up */
+ switch (ed->type) {
+ case PIPE_CONTROL:
+ admhc_writel (ahcd, OHCI_CLF,
+ &ahcd->regs->cmdstatus);
+ break;
+ case PIPE_BULK:
+ admhc_writel (ahcd, OHCI_BLF,
+ &ahcd->regs->cmdstatus);
+ break;
+ }
+ }
+#else
+ if ((td->hwINFO & cpu_to_hc32(ahcd, TD_OWN)))
+ ed->hwINFO &= ~cpu_to_hc32(ahcd, ED_SKIP);
+#endif
+ }
+
+ }
+}
+
+/* there are some tds completed; called in_irq(), with HCD locked */
+static void admhc_td_complete(struct admhcd *ahcd)
+{
+ struct ed *ed;
+
+ for (ed = ahcd->ed_head; ed; ed = ed->ed_next) {
+ if (ed->state != ED_OPER)
+ continue;
+
+ ed_update(ahcd, ed);
+ }
+}
--- /dev/null
+/*
+ * ADM5120 HCD (Host Controller Driver) for USB
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This file was derived from: drivers/usb/host/ohci.h
+ * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
+ * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+/*
+ * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
+ * __leXX (normally) or __beXX (given OHCI_BIG_ENDIAN), depending on the
+ * host controller implementation.
+ */
+typedef __u32 __bitwise __hc32;
+typedef __u16 __bitwise __hc16;
+
+/*
+ * OHCI Endpoint Descriptor (ED) ... holds TD queue
+ * See OHCI spec, section 4.2
+ *
+ * This is a "Queue Head" for those transfers, which is why
+ * both EHCI and UHCI call similar structures a "QH".
+ */
+
+#define TD_DATALEN_MAX 4096
+
+#define ED_ALIGN 16
+#define ED_MASK ((u32)~(ED_ALIGN-1)) /* strip hw status in low addr bits */
+
+struct ed {
+ /* first fields are hardware-specified */
+ __hc32 hwINFO; /* endpoint config bitmap */
+ /* info bits defined by hcd */
+#define ED_DEQUEUE (1 << 27)
+ /* info bits defined by the hardware */
+#define ED_MPS_SHIFT 16
+#define ED_MPS_MASK ((1 << 11)-1)
+#define ED_MPS_GET(x) (((x) >> ED_MPS_SHIFT) & ED_MPS_MASK)
+#define ED_ISO (1 << 15) /* isochronous endpoint */
+#define ED_SKIP (1 << 14)
+#define ED_SPEED_FULL (1 << 13) /* fullspeed device */
+#define ED_INT (1 << 11) /* interrupt endpoint */
+#define ED_EN_SHIFT 7 /* endpoint shift */
+#define ED_EN_MASK ((1 << 4)-1) /* endpoint mask */
+#define ED_EN_GET(x) (((x) >> ED_EN_SHIFT) & ED_EN_MASK)
+#define ED_FA_MASK ((1 << 7)-1) /* function address mask */
+#define ED_FA_GET(x) ((x) & ED_FA_MASK)
+ __hc32 hwTailP; /* tail of TD list */
+ __hc32 hwHeadP; /* head of TD list (hc r/w) */
+#define ED_C (0x02) /* toggle carry */
+#define ED_H (0x01) /* halted */
+ __hc32 hwNextED; /* next ED in list */
+
+ /* rest are purely for the driver's use */
+ dma_addr_t dma; /* addr of ED */
+ struct td *dummy; /* next TD to activate */
+
+ struct list_head urb_list; /* list of our URBs */
+
+ /* host's view of schedule */
+ struct ed *ed_next; /* on schedule list */
+ struct ed *ed_prev; /* for non-interrupt EDs */
+ struct ed *ed_rm_next; /* on rm list */
+ struct list_head td_list; /* "shadow list" of our TDs */
+
+ /* create --> IDLE --> OPER --> ... --> IDLE --> destroy
+ * usually: OPER --> UNLINK --> (IDLE | OPER) --> ...
+ */
+ u8 state; /* ED_{IDLE,UNLINK,OPER} */
+#define ED_IDLE 0x00 /* NOT linked to HC */
+#define ED_UNLINK 0x01 /* being unlinked from hc */
+#define ED_OPER 0x02 /* IS linked to hc */
+
+ u8 type; /* PIPE_{BULK,...} */
+
+ /* periodic scheduling params (for intr and iso) */
+ u8 branch;
+ u16 interval;
+ u16 load;
+ u16 last_iso; /* iso only */
+
+ /* HC may see EDs on rm_list until next frame (frame_no == tick) */
+ u16 tick;
+} __attribute__ ((aligned(ED_ALIGN)));
+
+/*
+ * OHCI Transfer Descriptor (TD) ... one per transfer segment
+ * See OHCI spec, sections 4.3.1 (general = control/bulk/interrupt)
+ * and 4.3.2 (iso)
+ */
+
+#define TD_ALIGN 32
+#define TD_MASK ((u32)~(TD_ALIGN-1)) /* strip hw status in low addr bits */
+
+struct td {
+ /* first fields are hardware-specified */
+ __hc32 hwINFO; /* transfer info bitmask */
+
+ /* hwINFO bits */
+#define TD_OWN (1 << 31) /* owner of the descriptor */
+#define TD_CC_SHIFT 27 /* condition code */
+#define TD_CC_MASK 0xf
+#define TD_CC (TD_CC_MASK << TD_CC_SHIFT)
+#define TD_CC_GET(x) (((x) >> TD_CC_SHIFT) & TD_CC_MASK)
+
+#define TD_EC_SHIFT 25 /* error count */
+#define TD_EC_MASK 0x3
+#define TD_EC (TD_EC_MASK << TD_EC_SHIFT)
+#define TD_EC_GET(x) ((x >> TD_EC_SHIFT) & TD_EC_MASK)
+#define TD_T_SHIFT 23 /* data toggle state */
+#define TD_T_MASK 0x3
+#define TD_T (TD_T_MASK << TD_T_SHIFT)
+#define TD_T_DATA0 (0x2 << TD_T_SHIFT) /* DATA0 */
+#define TD_T_DATA1 (0x3 << TD_T_SHIFT) /* DATA1 */
+#define TD_T_CARRY (0x0 << TD_T_SHIFT) /* uses ED_C */
+#define TD_T_GET(x) (((x) >> TD_T_SHIFT) & TD_T_MASK)
+#define TD_DP_SHIFT 21 /* direction/pid */
+#define TD_DP_MASK 0x3
+#define TD_DP (TD_DP_MASK << TD_DP_SHIFT)
+#define TD_DP_GET (((x) >> TD_DP_SHIFT) & TD_DP_MASK)
+#define TD_DP_SETUP (0x0 << TD_DP_SHIFT) /* SETUP pid */
+#define TD_DP_OUT (0x1 << TD_DP_SHIFT) /* OUT pid */
+#define TD_DP_IN (0x2 << TD_DP_SHIFT) /* IN pid */
+#define TD_ISI_SHIFT 8 /* Interrupt Service Interval */
+#define TD_ISI_MASK 0x3f
+#define TD_ISI_GET(x) (((x) >> TD_ISI_SHIFT) & TD_ISI_MASK)
+#define TD_FN_MASK 0x3f /* frame number */
+#define TD_FN_GET(x) ((x) & TD_FN_MASK)
+
+ __hc32 hwDBP; /* Data Buffer Pointer (or 0) */
+ __hc32 hwCBL; /* Controller/Buffer Length */
+
+ /* hwCBL bits */
+#define TD_BL_MASK 0xffff /* buffer length */
+#define TD_BL_GET(x) ((x) & TD_BL_MASK)
+#define TD_IE (1 << 16) /* interrupt enable */
+ __hc32 hwNextTD; /* Next TD Pointer */
+
+ /* rest are purely for the driver's use */
+ __u8 index;
+ struct ed *ed;
+ struct td *td_hash; /* dma-->td hashtable */
+ struct td *next_dl_td;
+ struct urb *urb;
+
+ dma_addr_t td_dma; /* addr of this TD */
+ dma_addr_t data_dma; /* addr of data it points to */
+
+ struct list_head td_list; /* "shadow list", TDs on same ED */
+
+ u32 flags;
+#define TD_FLAG_DONE (1 << 17) /* retired to done list */
+#define TD_FLAG_ISO (1 << 16) /* copy of ED_ISO */
+} __attribute__ ((aligned(TD_ALIGN))); /* c/b/i need 16; only iso needs 32 */
+
+/*
+ * Hardware transfer status codes -- CC from td->hwINFO
+ */
+#define TD_CC_NOERROR 0x00
+#define TD_CC_CRC 0x01
+#define TD_CC_BITSTUFFING 0x02
+#define TD_CC_DATATOGGLEM 0x03
+#define TD_CC_STALL 0x04
+#define TD_CC_DEVNOTRESP 0x05
+#define TD_CC_PIDCHECKFAIL 0x06
+#define TD_CC_UNEXPECTEDPID 0x07
+#define TD_CC_DATAOVERRUN 0x08
+#define TD_CC_DATAUNDERRUN 0x09
+ /* 0x0A, 0x0B reserved for hardware */
+#define TD_CC_BUFFEROVERRUN 0x0C
+#define TD_CC_BUFFERUNDERRUN 0x0D
+ /* 0x0E, 0x0F reserved for HCD */
+#define TD_CC_HCD0 0x0E
+#define TD_CC_NOTACCESSED 0x0F
+
+/*
+ * preshifted status codes
+ */
+#define TD_SCC_NOTACCESSED (TD_CC_NOTACCESSED << TD_CC_SHIFT)
+
+
+/* map OHCI TD status codes (CC) to errno values */
+static const int cc_to_error [16] = {
+ /* No Error */ 0,
+ /* CRC Error */ -EILSEQ,
+ /* Bit Stuff */ -EPROTO,
+ /* Data Togg */ -EILSEQ,
+ /* Stall */ -EPIPE,
+ /* DevNotResp */ -ETIME,
+ /* PIDCheck */ -EPROTO,
+ /* UnExpPID */ -EPROTO,
+ /* DataOver */ -EOVERFLOW,
+ /* DataUnder */ -EREMOTEIO,
+ /* (for hw) */ -EIO,
+ /* (for hw) */ -EIO,
+ /* BufferOver */ -ECOMM,
+ /* BuffUnder */ -ENOSR,
+ /* (for HCD) */ -EALREADY,
+ /* (for HCD) */ -EALREADY
+};
+
+#define NUM_INTS 32
+
+/*
+ * This is the structure of the OHCI controller's memory mapped I/O region.
+ * You must use readl() and writel() (in <asm/io.h>) to access these fields!!
+ * Layout is in section 7 (and appendix B) of the spec.
+ */
+struct admhcd_regs {
+ __hc32 gencontrol; /* General Control */
+ __hc32 int_status; /* Interrupt Status */
+ __hc32 int_enable; /* Interrupt Enable */
+ __hc32 reserved00;
+ __hc32 host_control; /* Host General Control */
+ __hc32 reserved01;
+ __hc32 fminterval; /* Frame Interval */
+ __hc32 fmnumber; /* Frame Number */
+ __hc32 reserved02;
+ __hc32 reserved03;
+ __hc32 reserved04;
+ __hc32 reserved05;
+ __hc32 reserved06;
+ __hc32 reserved07;
+ __hc32 reserved08;
+ __hc32 reserved09;
+ __hc32 reserved10;
+ __hc32 reserved11;
+ __hc32 reserved12;
+ __hc32 reserved13;
+ __hc32 reserved14;
+ __hc32 reserved15;
+ __hc32 reserved16;
+ __hc32 reserved17;
+ __hc32 reserved18;
+ __hc32 reserved19;
+ __hc32 reserved20;
+ __hc32 reserved21;
+ __hc32 lsthresh; /* Low Speed Threshold */
+ __hc32 rhdesc; /* Root Hub Descriptor */
+#define MAX_ROOT_PORTS 2
+ __hc32 portstatus[MAX_ROOT_PORTS]; /* Port Status */
+ __hc32 hosthead; /* Host Descriptor Head */
+} __attribute__ ((aligned(32)));
+
+/*
+ * General Control register bits
+ */
+#define ADMHC_CTRL_UHFE (1 << 0) /* USB Host Function Enable */
+#define ADMHC_CTRL_SIR (1 << 1) /* Software Interrupt request */
+#define ADMHC_CTRL_DMAA (1 << 2) /* DMA Arbitration Control */
+#define ADMHC_CTRL_SR (1 << 3) /* Software Reset */
+
+/*
+ * Host General Control register bits
+ */
+#define ADMHC_HC_BUSS 0x3 /* USB bus state */
+#define ADMHC_BUSS_RESET 0x0
+#define ADMHC_BUSS_RESUME 0x1
+#define ADMHC_BUSS_OPER 0x2
+#define ADMHC_BUSS_SUSPEND 0x3
+#define ADMHC_HC_DMAE (1 << 2) /* DMA enable */
+
+/*
+ * Interrupt Status/Enable register bits
+ */
+#define ADMHC_INTR_SOFI (1 << 4) /* start of frame */
+#define ADMHC_INTR_RESI (1 << 5) /* resume detected */
+#define ADMHC_INTR_6 (1 << 6) /* unknown */
+#define ADMHC_INTR_7 (1 << 7) /* unknown */
+#define ADMHC_INTR_BABI (1 << 8) /* babble detected */
+#define ADMHC_INTR_INSM (1 << 9) /* root hub status change */
+#define ADMHC_INTR_SO (1 << 10) /* scheduling overrun */
+#define ADMHC_INTR_FNO (1 << 11) /* frame number overflow */
+#define ADMHC_INTR_TDC (1 << 20) /* transfer descriptor completed */
+#define ADMHC_INTR_SWI (1 << 29) /* software interrupt */
+#define ADMHC_INTR_FATI (1 << 30) /* fatal error */
+#define ADMHC_INTR_INTA (1 << 31) /* interrupt active */
+
+#define ADMHC_INTR_MIE (1 << 31) /* master interrupt enable */
+
+/*
+ * SOF Frame Interval register bits
+ */
+#define ADMHC_SFI_FI_MASK ((1 << 14)-1) /* Frame Interval value */
+#define ADMHC_SFI_FSLDP_SHIFT 16
+#define ADMHC_SFI_FSLDP_MASK ((1 << 15)-1)
+#define ADMHC_SFI_FIT (1 << 31) /* Frame Interval Toggle */
+
+/*
+ * SOF Frame Number register bits
+ */
+#define ADMHC_SFN_FN_MASK ((1 << 16)-1) /* Frame Number Mask */
+#define ADMHC_SFN_FR_SHIFT 16 /* Frame Remaining Shift */
+#define ADMHC_SFN_FR_MASK ((1 << 14)-1) /* Frame Remaining Mask */
+#define ADMHC_SFN_FRT (1 << 31) /* Frame Remaining Toggle */
+
+/*
+ * Root Hub Descriptor register bits
+ */
+#define ADMHC_RH_NUMP 0xff /* number of ports */
+#define ADMHC_RH_PSM (1 << 8) /* power switching mode */
+#define ADMHC_RH_NPS (1 << 9) /* no power switching */
+#define ADMHC_RH_OCPM (1 << 10) /* over current protection mode */
+#define ADMHC_RH_NOCP (1 << 11) /* no over current protection */
+#define ADMHC_RH_PPCM (0xff << 16) /* port power control */
+
+#define ADMHC_RH_LPS (1 << 24) /* local power switch */
+#define ADMHC_RH_OCI (1 << 25) /* over current indicator */
+
+/* status change bits */
+#define ADMHC_RH_LPSC (1 << 26) /* local power switch change */
+#define ADMHC_RH_OCIC (1 << 27) /* over current indicator change */
+
+#define ADMHC_RH_DRWE (1 << 28) /* device remote wakeup enable */
+#define ADMHC_RH_CRWE (1 << 29) /* clear remote wakeup enable */
+
+#define ADMHC_RH_CGP (1 << 24) /* clear global power */
+#define ADMHC_RH_SGP (1 << 26) /* set global power */
+
+/*
+ * Port Status register bits
+ */
+#define ADMHC_PS_CCS (1 << 0) /* current connect status */
+#define ADMHC_PS_PES (1 << 1) /* port enable status */
+#define ADMHC_PS_PSS (1 << 2) /* port suspend status */
+#define ADMHC_PS_POCI (1 << 3) /* port over current indicator */
+#define ADMHC_PS_PRS (1 << 4) /* port reset status */
+#define ADMHC_PS_PPS (1 << 8) /* port power status */
+#define ADMHC_PS_LSDA (1 << 9) /* low speed device attached */
+
+/* status change bits */
+#define ADMHC_PS_CSC (1 << 16) /* connect status change */
+#define ADMHC_PS_PESC (1 << 17) /* port enable status change */
+#define ADMHC_PS_PSSC (1 << 18) /* port suspend status change */
+#define ADMHC_PS_OCIC (1 << 19) /* over current indicator change */
+#define ADMHC_PS_PRSC (1 << 20) /* port reset status change */
+
+/* port feature bits */
+#define ADMHC_PS_CPE (1 << 0) /* clear port enable */
+#define ADMHC_PS_SPE (1 << 1) /* set port enable */
+#define ADMHC_PS_SPS (1 << 2) /* set port suspend */
+#define ADMHC_PS_CPS (1 << 3) /* clear suspend status */
+#define ADMHC_PS_SPR (1 << 4) /* set port reset */
+#define ADMHC_PS_SPP (1 << 8) /* set port power */
+#define ADMHC_PS_CPP (1 << 9) /* clear port power */
+
+/*
+ * the POTPGT value is not defined in the ADMHC, so define a dummy value
+ */
+#define ADMHC_POTPGT 2 /* in ms */
+
+/* hcd-private per-urb state */
+struct urb_priv {
+ struct ed *ed;
+ struct list_head pending; /* URBs on the same ED */
+
+ u32 td_cnt; /* # tds in this request */
+ u32 td_idx; /* index of the current td */
+ struct td *td[0]; /* all TDs in this request */
+};
+
+#define TD_HASH_SIZE 64 /* power'o'two */
+/* sizeof (struct td) ~= 64 == 2^6 ... */
+#define TD_HASH_FUNC(td_dma) ((td_dma ^ (td_dma >> 6)) % TD_HASH_SIZE)
+
+/*
+ * This is the full ADMHCD controller description
+ *
+ * Note how the "proper" USB information is just
+ * a subset of what the full implementation needs. (Linus)
+ */
+
+struct admhcd {
+ spinlock_t lock;
+
+ /*
+ * I/O memory used to communicate with the HC (dma-consistent)
+ */
+ struct admhcd_regs __iomem *regs;
+
+ /*
+ * hcd adds to schedule for a live hc any time, but removals finish
+ * only at the start of the next frame.
+ */
+
+ struct ed *ed_head;
+ struct ed *ed_tails[4];
+
+ struct ed *ed_rm_list; /* to be removed */
+
+ struct ed *periodic[NUM_INTS]; /* shadow int_table */
+
+#if 0 /* TODO: remove? */
+ /*
+ * OTG controllers and transceivers need software interaction;
+ * other external transceivers should be software-transparent
+ */
+ struct otg_transceiver *transceiver;
+#endif
+
+ /*
+ * memory management for queue data structures
+ */
+ struct dma_pool *td_cache;
+ struct dma_pool *ed_cache;
+ struct td *td_hash[TD_HASH_SIZE];
+ struct list_head pending;
+
+ /*
+ * driver state
+ */
+ int num_ports;
+ int load[NUM_INTS];
+ u32 host_control; /* copy of the host_control reg */
+ unsigned long next_statechange; /* suspend/resume */
+ u32 fminterval; /* saved register */
+ unsigned autostop:1; /* rh auto stopping/stopped */
+
+ unsigned long flags; /* for HC bugs */
+#define OHCI_QUIRK_AMD756 0x01 /* erratum #4 */
+#define OHCI_QUIRK_SUPERIO 0x02 /* natsemi */
+#define OHCI_QUIRK_INITRESET 0x04 /* SiS, OPTi, ... */
+#define OHCI_QUIRK_BE_DESC 0x08 /* BE descriptors */
+#define OHCI_QUIRK_BE_MMIO 0x10 /* BE registers */
+#define OHCI_QUIRK_ZFMICRO 0x20 /* Compaq ZFMicro chipset*/
+ // there are also chip quirks/bugs in init logic
+
+#ifdef DEBUG
+ struct dentry *debug_dir;
+ struct dentry *debug_async;
+ struct dentry *debug_periodic;
+ struct dentry *debug_registers;
+#endif
+};
+
+/* convert between an hcd pointer and the corresponding ahcd_hcd */
+static inline struct admhcd *hcd_to_admhcd(struct usb_hcd *hcd)
+{
+ return (struct admhcd *)(hcd->hcd_priv);
+}
+static inline struct usb_hcd *admhcd_to_hcd(const struct admhcd *ahcd)
+{
+ return container_of((void *)ahcd, struct usb_hcd, hcd_priv);
+}
+
+/*-------------------------------------------------------------------------*/
+
+#ifndef DEBUG
+#define STUB_DEBUG_FILES
+#endif /* DEBUG */
+
+#ifdef DEBUG
+# define admhc_dbg(ahcd, fmt, args...) \
+ printk(KERN_DEBUG "adm5120-hcd: " fmt , ## args )
+#else
+# define admhc_dbg(ahcd, fmt, args...) do { } while (0)
+#endif
+
+#define admhc_err(ahcd, fmt, args...) \
+ printk(KERN_ERR "adm5120-hcd: " fmt , ## args )
+#define admhc_info(ahcd, fmt, args...) \
+ printk(KERN_INFO "adm5120-hcd: " fmt , ## args )
+#define admhc_warn(ahcd, fmt, args...) \
+ printk(KERN_WARNING "adm5120-hcd: " fmt , ## args )
+
+#ifdef ADMHC_VERBOSE_DEBUG
+# define admhc_vdbg admhc_dbg
+#else
+# define admhc_vdbg(ahcd, fmt, args...) do { } while (0)
+#endif
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * While most USB host controllers implement their registers and
+ * in-memory communication descriptors in little-endian format,
+ * a minority (notably the IBM STB04XXX and the Motorola MPC5200
+ * processors) implement them in big endian format.
+ *
+ * In addition some more exotic implementations like the Toshiba
+ * Spider (aka SCC) cell southbridge are "mixed" endian, that is,
+ * they have a different endianness for registers vs. in-memory
+ * descriptors.
+ *
+ * This attempts to support either format at compile time without a
+ * runtime penalty, or both formats with the additional overhead
+ * of checking a flag bit.
+ *
+ * That leads to some tricky Kconfig rules howevber. There are
+ * different defaults based on some arch/ppc platforms, though
+ * the basic rules are:
+ *
+ * Controller type Kconfig options needed
+ * --------------- ----------------------
+ * little endian CONFIG_USB_ADMHC_LITTLE_ENDIAN
+ *
+ * fully big endian CONFIG_USB_ADMHC_BIG_ENDIAN_DESC _and_
+ * CONFIG_USB_ADMHC_BIG_ENDIAN_MMIO
+ *
+ * mixed endian CONFIG_USB_ADMHC_LITTLE_ENDIAN _and_
+ * CONFIG_USB_OHCI_BIG_ENDIAN_{MMIO,DESC}
+ *
+ * (If you have a mixed endian controller, you -must- also define
+ * CONFIG_USB_ADMHC_LITTLE_ENDIAN or things will not work when building
+ * both your mixed endian and a fully big endian controller support in
+ * the same kernel image).
+ */
+
+#ifdef CONFIG_USB_ADMHC_BIG_ENDIAN_DESC
+#ifdef CONFIG_USB_ADMHC_LITTLE_ENDIAN
+#define big_endian_desc(ahcd) (ahcd->flags & OHCI_QUIRK_BE_DESC)
+#else
+#define big_endian_desc(ahcd) 1 /* only big endian */
+#endif
+#else
+#define big_endian_desc(ahcd) 0 /* only little endian */
+#endif
+
+#ifdef CONFIG_USB_ADMHC_BIG_ENDIAN_MMIO
+#ifdef CONFIG_USB_ADMHC_LITTLE_ENDIAN
+#define big_endian_mmio(ahcd) (ahcd->flags & OHCI_QUIRK_BE_MMIO)
+#else
+#define big_endian_mmio(ahcd) 1 /* only big endian */
+#endif
+#else
+#define big_endian_mmio(ahcd) 0 /* only little endian */
+#endif
+
+/*
+ * Big-endian read/write functions are arch-specific.
+ * Other arches can be added if/when they're needed.
+ *
+ * REVISIT: arch/powerpc now has readl/writel_be, so the
+ * definition below can die once the STB04xxx support is
+ * finally ported over.
+ */
+#if defined(CONFIG_PPC) && !defined(CONFIG_PPC_MERGE)
+#define readl_be(addr) in_be32((__force unsigned *)addr)
+#define writel_be(val, addr) out_be32((__force unsigned *)addr, val)
+#endif
+
+static inline unsigned int admhc_readl(const struct admhcd *ahcd,
+ __hc32 __iomem *regs)
+{
+#ifdef CONFIG_USB_ADMHC_BIG_ENDIAN_MMIO
+ return big_endian_mmio(ahcd) ?
+ readl_be(regs) :
+ readl(regs);
+#else
+ return readl(regs);
+#endif
+}
+
+static inline void admhc_writel(const struct admhcd *ahcd,
+ const unsigned int val, __hc32 __iomem *regs)
+{
+#ifdef CONFIG_USB_ADMHC_BIG_ENDIAN_MMIO
+ big_endian_mmio(ahcd) ?
+ writel_be(val, regs) :
+ writel(val, regs);
+#else
+ writel(val, regs);
+#endif
+}
+
+static inline void admhc_writel_flush(const struct admhcd *ahcd)
+{
+#if 0
+ /* TODO: remove? */
+ (void) admhc_readl(ahcd, &ahcd->regs->gencontrol);
+#endif
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+/* cpu to ahcd */
+static inline __hc16 cpu_to_hc16(const struct admhcd *ahcd, const u16 x)
+{
+ return big_endian_desc(ahcd) ?
+ (__force __hc16)cpu_to_be16(x) :
+ (__force __hc16)cpu_to_le16(x);
+}
+
+static inline __hc16 cpu_to_hc16p(const struct admhcd *ahcd, const u16 *x)
+{
+ return big_endian_desc(ahcd) ?
+ cpu_to_be16p(x) :
+ cpu_to_le16p(x);
+}
+
+static inline __hc32 cpu_to_hc32(const struct admhcd *ahcd, const u32 x)
+{
+ return big_endian_desc(ahcd) ?
+ (__force __hc32)cpu_to_be32(x) :
+ (__force __hc32)cpu_to_le32(x);
+}
+
+static inline __hc32 cpu_to_hc32p(const struct admhcd *ahcd, const u32 *x)
+{
+ return big_endian_desc(ahcd) ?
+ cpu_to_be32p(x) :
+ cpu_to_le32p(x);
+}
+
+/* ahcd to cpu */
+static inline u16 hc16_to_cpu(const struct admhcd *ahcd, const __hc16 x)
+{
+ return big_endian_desc(ahcd) ?
+ be16_to_cpu((__force __be16)x) :
+ le16_to_cpu((__force __le16)x);
+}
+
+static inline u16 hc16_to_cpup(const struct admhcd *ahcd, const __hc16 *x)
+{
+ return big_endian_desc(ahcd) ?
+ be16_to_cpup((__force __be16 *)x) :
+ le16_to_cpup((__force __le16 *)x);
+}
+
+static inline u32 hc32_to_cpu(const struct admhcd *ahcd, const __hc32 x)
+{
+ return big_endian_desc(ahcd) ?
+ be32_to_cpu((__force __be32)x) :
+ le32_to_cpu((__force __le32)x);
+}
+
+static inline u32 hc32_to_cpup(const struct admhcd *ahcd, const __hc32 *x)
+{
+ return big_endian_desc(ahcd) ?
+ be32_to_cpup((__force __be32 *)x) :
+ le32_to_cpup((__force __le32 *)x);
+}
+
+/*-------------------------------------------------------------------------*/
+
+static inline u16 admhc_frame_no(const struct admhcd *ahcd)
+{
+ u32 t;
+
+ t = admhc_readl(ahcd, &ahcd->regs->fmnumber) & ADMHC_SFN_FN_MASK;
+ return (u16)t;
+}
+
+static inline u16 admhc_frame_remain(const struct admhcd *ahcd)
+{
+ u32 t;
+
+ t = admhc_readl(ahcd, &ahcd->regs->fmnumber) >> ADMHC_SFN_FR_SHIFT;
+ t &= ADMHC_SFN_FR_MASK;
+ return (u16)t;
+}
+
+/*-------------------------------------------------------------------------*/
+
+static inline void admhc_disable(struct admhcd *ahcd)
+{
+ admhcd_to_hcd(ahcd)->state = HC_STATE_HALT;
+}
+
+#define FI 0x2edf /* 12000 bits per frame (-1) */
+#define FSLDP(fi) (0x7fff & ((6 * ((fi) - 1200)) / 7))
+#define FIT ADMHC_SFI_FIT
+#define LSTHRESH 0x628 /* lowspeed bit threshold */
+
+static inline void periodic_reinit(struct admhcd *ahcd)
+{
+#if 0
+ u32 fi = ahcd->fminterval & ADMHC_SFI_FI_MASK;
+ u32 fit = admhc_readl(ahcd, &ahcd->regs->fminterval) & FIT;
+
+ /* TODO: adjust FSLargestDataPacket value too? */
+ admhc_writel(ahcd, (fit ^ FIT) | ahcd->fminterval,
+ &ahcd->regs->fminterval);
+#else
+ u32 fit = admhc_readl(ahcd, &ahcd->regs->fminterval) & FIT;
+
+ /* TODO: adjust FSLargestDataPacket value too? */
+ admhc_writel(ahcd, (fit ^ FIT) | ahcd->fminterval,
+ &ahcd->regs->fminterval);
+#endif
+}
+
+static inline u32 admhc_read_rhdesc(struct admhcd *ahcd)
+{
+ return admhc_readl(ahcd, &ahcd->regs->rhdesc);
+}
+
+static inline u32 admhc_read_portstatus(struct admhcd *ahcd, int port)
+{
+ return admhc_readl(ahcd, &ahcd->regs->portstatus[port]);
+}
+
+static inline void admhc_write_portstatus(struct admhcd *ahcd, int port,
+ u32 value)
+{
+ admhc_writel(ahcd, value, &ahcd->regs->portstatus[port]);
+}
+
+static inline void roothub_write_status(struct admhcd *ahcd, u32 value)
+{
+ /* FIXME: read-only bits must be masked out */
+ admhc_writel(ahcd, value, &ahcd->regs->rhdesc);
+}
+
+static inline void admhc_intr_disable(struct admhcd *ahcd, u32 ints)
+{
+ u32 t;
+
+ t = admhc_readl(ahcd, &ahcd->regs->int_enable);
+ t &= ~(ints);
+ admhc_writel(ahcd, t, &ahcd->regs->int_enable);
+ /* TODO: flush writes ?*/
+}
+
+static inline void admhc_intr_enable(struct admhcd *ahcd, u32 ints)
+{
+ u32 t;
+
+ t = admhc_readl(ahcd, &ahcd->regs->int_enable);
+ t |= ints;
+ admhc_writel(ahcd, t, &ahcd->regs->int_enable);
+ /* TODO: flush writes ?*/
+}
+
+static inline void admhc_intr_ack(struct admhcd *ahcd, u32 ints)
+{
+ admhc_writel(ahcd, ints, &ahcd->regs->int_status);
+}
+
+static inline void admhc_dma_enable(struct admhcd *ahcd)
+{
+ u32 t;
+
+ t = admhc_readl(ahcd, &ahcd->regs->host_control);
+ if (t & ADMHC_HC_DMAE)
+ return;
+
+ t |= ADMHC_HC_DMAE;
+ admhc_writel(ahcd, t, &ahcd->regs->host_control);
+ admhc_vdbg(ahcd,"DMA enabled\n");
+}
+
+static inline void admhc_dma_disable(struct admhcd *ahcd)
+{
+ u32 t;
+
+ t = admhc_readl(ahcd, &ahcd->regs->host_control);
+ if (!(t & ADMHC_HC_DMAE))
+ return;
+
+ t &= ~ADMHC_HC_DMAE;
+ admhc_writel(ahcd, t, &ahcd->regs->host_control);
+ admhc_vdbg(ahcd,"DMA disabled\n");
+}
--- /dev/null
+/*
+ * ADM5120_WDT 0.01: Infineon ADM5120 SoC watchdog driver
+ * Copyright (c) Ondrej Zajicek <santiago@crfreenet.org>, 2007
+ *
+ * based on
+ *
+ * RC32434_WDT 0.01: IDT Interprise 79RC32434 watchdog driver
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ */
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/fs.h>
+#include <linux/miscdevice.h>
+#include <linux/watchdog.h>
+#include <linux/irq.h>
+
+#include <asm/bootinfo.h>
+
+#include <asm/mach-adm5120/adm5120_info.h>
+#include <asm/mach-adm5120/adm5120_defs.h>
+#include <asm/mach-adm5120/adm5120_switch.h>
+
+#define DEFAULT_TIMEOUT 15 /* (secs) Default is 15 seconds */
+#define MAX_TIMEOUT 327
+/* Max is 327 seconds, counter is 15-bit integer, step is 10 ms */
+
+#define NAME "adm5120_wdt"
+#define VERSION "0.1"
+
+static int expect_close = 0;
+static int access = 0;
+static unsigned int timeout = DEFAULT_TIMEOUT;
+
+static int nowayout = WATCHDOG_NOWAYOUT;
+module_param(nowayout, int, 0);
+MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
+MODULE_LICENSE("GPL");
+
+
+static inline void wdt_set_timeout(void)
+{
+ u32 val = (1 << 31) | (((timeout * 100) & 0x7FFF) << 16);
+ SW_WRITE_REG(SWITCH_REG_WDOG0, val);
+}
+
+/*
+ It looks like WDOG0-register-write don't modify counter,
+ but WDOG0-register-read resets counter.
+*/
+
+static inline void wdt_reset_counter(void)
+{
+ SW_READ_REG(SWITCH_REG_WDOG0);
+}
+
+static inline void wdt_disable(void)
+{
+ SW_WRITE_REG(SWITCH_REG_WDOG0, 0x7FFF0000);
+}
+
+
+
+static int wdt_open(struct inode *inode, struct file *file)
+{
+ /* Allow only one person to hold it open */
+ if (access)
+ return -EBUSY;
+
+ if (nowayout) {
+ __module_get(THIS_MODULE);
+ }
+
+ /* Activate timer */
+ wdt_reset_counter();
+ wdt_set_timeout();
+ printk(KERN_INFO NAME ": enabling watchdog timer\n");
+ access = 1;
+ return 0;
+}
+
+static int wdt_release(struct inode *inode, struct file *file)
+{
+ /*
+ * Shut off the timer.
+ * Lock it in if it's a module and we set nowayout
+ */
+ if (expect_close && (nowayout == 0)) {
+ wdt_disable();
+ printk(KERN_INFO NAME ": disabling watchdog timer\n");
+ module_put(THIS_MODULE);
+ } else {
+ printk(KERN_CRIT NAME ": device closed unexpectedly. WDT will not stop!\n");
+ }
+ access = 0;
+ return 0;
+}
+
+static ssize_t wdt_write(struct file *file, const char *data, size_t len, loff_t *ppos)
+{
+ /* Refresh the timer. */
+ if (len) {
+ if (!nowayout) {
+ size_t i;
+
+ /* In case it was set long ago */
+ expect_close = 0;
+
+ for (i = 0; i != len; i++) {
+ char c;
+ if (get_user(c, data + i))
+ return -EFAULT;
+ if (c == 'V')
+ expect_close = 1;
+ }
+ }
+ wdt_reset_counter();
+ return len;
+ }
+ return 0;
+}
+
+static int wdt_ioctl(struct inode *inode, struct file *file,
+ unsigned int cmd, unsigned long arg)
+{
+ int new_timeout;
+ static struct watchdog_info ident = {
+ .options = WDIOF_SETTIMEOUT |
+ WDIOF_KEEPALIVEPING |
+ WDIOF_MAGICCLOSE,
+ .firmware_version = 0,
+ .identity = "ADM5120_WDT Watchdog",
+ };
+ switch (cmd) {
+ default:
+ return -ENOTTY;
+ case WDIOC_GETSUPPORT:
+ if(copy_to_user((struct watchdog_info *)arg, &ident, sizeof(ident)))
+ return -EFAULT;
+ return 0;
+ case WDIOC_GETSTATUS:
+ case WDIOC_GETBOOTSTATUS:
+ return put_user(0,(int *)arg);
+ case WDIOC_KEEPALIVE:
+ wdt_reset_counter();
+ return 0;
+ case WDIOC_SETTIMEOUT:
+ if (get_user(new_timeout, (int *)arg))
+ return -EFAULT;
+ if (new_timeout < 1)
+ return -EINVAL;
+ if (new_timeout > MAX_TIMEOUT)
+ return -EINVAL;
+ timeout = new_timeout;
+ wdt_set_timeout();
+ /* Fall */
+ case WDIOC_GETTIMEOUT:
+ return put_user(timeout, (int *)arg);
+ }
+}
+
+static struct file_operations wdt_fops = {
+ owner: THIS_MODULE,
+ llseek: no_llseek,
+ write: wdt_write,
+ ioctl: wdt_ioctl,
+ open: wdt_open,
+ release: wdt_release,
+};
+
+static struct miscdevice wdt_miscdev = {
+ minor: WATCHDOG_MINOR,
+ name: "watchdog",
+ fops: &wdt_fops,
+};
+
+static char banner[] __initdata = KERN_INFO NAME ": Watchdog Timer version " VERSION "\n";
+
+static int __init watchdog_init(void)
+{
+ int ret;
+
+ ret = misc_register(&wdt_miscdev);
+
+ if (ret)
+ return ret;
+
+ wdt_disable();
+ printk(banner);
+
+ return 0;
+}
+
+static void __exit watchdog_exit(void)
+{
+ misc_deregister(&wdt_miscdev);
+}
+
+module_init(watchdog_init);
+module_exit(watchdog_exit);
--- /dev/null
+/*
+ * ADM5120 board definitions
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#ifndef _ASM_MIPS_MACH_ADM5120_BOARD_H
+#define _ASM_MIPS_MACH_ADM5120_BOARD_H
+
+#include <linux/init.h>
+#include <linux/list.h>
+
+#define ADM5120_BOARD_NAMELEN 64
+
+struct adm5120_board {
+ unsigned long mach_type;
+ char name[ADM5120_BOARD_NAMELEN];
+
+ void (*board_setup)(void);
+ struct list_head list;
+};
+
+extern void adm5120_board_register(struct adm5120_board *) __init;
+
+#define ADM5120_BOARD(_type, _name, _setup) \
+static struct adm5120_board adm5120_board_##_type __initdata = { \
+ .mach_type = _type, \
+ .name = _name, \
+ .board_setup = _setup, \
+}; \
+ \
+static __init int adm5120_board_##_type##_register(void) \
+{ \
+ adm5120_board_register(&adm5120_board_##_type); \
+ return 0; \
+} \
+pure_initcall(adm5120_board_##_type##_register)
+
+#endif /* _ASM_MIPS_MACH_ADM5120_BOARD_H */
--- /dev/null
+/*
+ * ADM5120 SoC definitions
+ *
+ * This file defines some constants specific to the ADM5120 SoC
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+#ifndef _ASM_MIPS_MACH_ADM5120_DEFS_H
+#define _ASM_MIPS_MACH_ADM5120_DEFS_H
+
+#define ADM5120_SDRAM0_BASE 0x00000000
+#define ADM5120_SDRAM1_BASE 0x01000000
+#define ADM5120_SRAM1_BASE 0x10000000
+#define ADM5120_EXTIO0_BASE 0x10C00000
+#define ADM5120_EXTIO0_SIZE 0x00200000
+#define ADM5120_EXTIO1_BASE 0x10E00000
+#define ADM5120_EXTIO1_SIZE 0x00200000
+#define ADM5120_MPMC_BASE 0x11000000
+#define ADM5120_MPMC_SIZE 0x00200000
+#define ADM5120_USBC_BASE 0x11200000
+#define ADM5120_USBC_SIZE 0x00200000
+#define ADM5120_PCIMEM_BASE 0x11400000
+#define ADM5120_PCIMEM_SIZE 0x00100000
+#define ADM5120_PCIIO_BASE 0x11500000
+#define ADM5120_PCIIO_SIZE 0x000FFFF0
+#define ADM5120_PCICFG_ADDR 0x115FFFF0
+#define ADM5120_PCICFG_DATA 0x115FFFF8
+#define ADM5120_PCICFG_SIZE 0x00000010
+#define ADM5120_SWITCH_BASE 0x12000000
+#define ADM5120_SWITCH_SIZE 0x00200000
+#define ADM5120_INTC_BASE 0x12200000
+#define ADM5120_INTC_SIZE 0x00200000
+#define ADM5120_UART0_BASE 0x12600000
+#define ADM5120_UART1_BASE 0x12800000
+#define ADM5120_UART_SIZE 0x00200000
+#define ADM5120_SRAM0_BASE 0x1FC00000
+
+#define ADM5120_NAND_BASE ADM5120_SRAM1_BASE
+#define ADM5120_NAND_SIZE 0xB
+
+#define ADM5120_CLK_175 175000000
+#define ADM5120_CLK_200 200000000
+#define ADM5120_CLK_225 225000000
+#define ADM5120_CLK_250 250000000
+
+#define ADM5120_UART_CLOCK 62500000
+
+#endif /* _ASM_MIPS_MACH_ADM5120_DEFS_H */
--- /dev/null
+/*
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#ifndef _MACH_ADM5120_INFO_H
+#define _MACH_ADM5120_INFO_H
+
+#include <linux/types.h>
+
+extern unsigned int adm5120_prom_type;
+#define ADM5120_PROM_GENERIC 0
+#define ADM5120_PROM_CFE 1
+#define ADM5120_PROM_MYLOADER 2
+#define ADM5120_PROM_ROUTERBOOT 3
+#define ADM5120_PROM_BOOTBASE 4
+#define ADM5120_PROM_UBOOT 5
+#define ADM5120_PROM_LAST 5
+
+extern unsigned int adm5120_product_code;
+extern unsigned int adm5120_revision;
+extern unsigned int adm5120_nand_boot;
+
+extern unsigned long adm5120_speed;
+#define ADM5120_SPEED_175 175000000
+#define ADM5120_SPEED_200 200000000
+#define ADM5120_SPEED_225 225000000
+#define ADM5120_SPEED_250 250000000
+
+extern unsigned int adm5120_package;
+#define ADM5120_PACKAGE_PQFP 0
+#define ADM5120_PACKAGE_BGA 1
+
+extern unsigned long adm5120_memsize;
+
+/*
+ * TODO:remove adm5120_eth* variables when the switch driver will be
+ * converted into a real platform driver
+ */
+extern unsigned int adm5120_eth_num_ports;
+extern unsigned char adm5120_eth_macs[6][6];
+extern unsigned char adm5120_eth_vlans[6];
+
+extern void adm5120_soc_init(void) __init;
+extern void adm5120_mem_init(void) __init;
+extern void adm5120_ndelay(u32 ns);
+
+extern void (*adm5120_board_reset)(void);
+
+extern void adm5120_gpio_init(void) __init;
+extern void adm5120_gpio_csx0_enable(void) __init;
+extern void adm5120_gpio_csx1_enable(void) __init;
+extern void adm5120_gpio_ew_enable(void) __init;
+
+static inline int adm5120_package_pqfp(void)
+{
+ return (adm5120_package == ADM5120_PACKAGE_PQFP);
+}
+
+static inline int adm5120_package_bga(void)
+{
+ return (adm5120_package == ADM5120_PACKAGE_BGA);
+}
+
+static inline int adm5120_has_pci(void)
+{
+ return (adm5120_package == ADM5120_PACKAGE_BGA);
+}
+
+static inline int adm5120_has_gmii(void)
+{
+ return (adm5120_package == ADM5120_PACKAGE_BGA);
+}
+
+#endif /* _MACH_ADM5120_INFO_H */
--- /dev/null
+/*
+ * ADM5120 interrupt controller definitions
+ *
+ * This header file defines the hardware registers of the ADM5120 SoC
+ * built-in interrupt controller.
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#ifndef _MACH_ADM5120_INTC_H
+#define _MACH_ADM5120_INTC_H
+
+/*
+ * INTC register offsets
+ */
+#define INTC_REG_IRQ_STATUS 0x00 /* Interrupt status after masking */
+#define INTC_REG_IRQ_RAW_STATUS 0x04 /* Interrupt status before masking */
+#define INTC_REG_IRQ_ENABLE 0x08 /* Used to enable the interrupt sources */
+#define INTC_REG_IRQ_ENABLE_CLEAR 0x0C /* Used to disable the interrupt sources */
+#define INTC_REG_IRQ_DISABLE INTC_REG_IRQ_ENABLE_CLEAR
+#define INTC_REG_INT_MODE 0x14 /* The interrupt mode of the sources */
+#define INTC_REG_FIQ_STATUS 0x18 /* FIQ status */
+#define INTC_REG_IRQ_TEST_SOURCE 0x1C
+#define INTC_REG_IRQ_SOURCE_SELECT 0x20
+#define INTC_REG_INT_LEVEL 0x24
+
+/*
+ * INTC IRQ numbers
+ */
+#define INTC_IRQ_TIMER 0 /* built in timer */
+#define INTC_IRQ_UART0 1 /* built-in UART0 */
+#define INTC_IRQ_UART1 2 /* built-in UART1 */
+#define INTC_IRQ_USBC 3 /* USB Host Controller */
+#define INTC_IRQ_GPIO2 4 /* GPIO line 2 */
+#define INTC_IRQ_GPIO4 5 /* GPIO line 4 */
+#define INTC_IRQ_PCI0 6 /* PCI slot 2 */
+#define INTC_IRQ_PCI1 7 /* PCI slot 3 */
+#define INTC_IRQ_PCI2 8 /* PCI slot 4 */
+#define INTC_IRQ_SWITCH 9 /* built-in ethernet switch */
+#define INTC_IRQ_LAST INTC_IRQ_SWITCH
+#define INTC_IRQ_COUNT 10
+
+/*
+ * INTC register bits
+ */
+#define INTC_INT_TIMER ( 1 << INTC_IRQ_TIMER )
+#define INTC_INT_UART0 ( 1 << INTC_IRQ_UART0 )
+#define INTC_INT_UART1 ( 1 << INTC_IRQ_UART1 )
+#define INTC_INT_USBC ( 1 << INTC_IRQ_USBC )
+#define INTC_INT_INTX0 ( 1 << INTC_IRQ_INTX0 )
+#define INTC_INT_INTX1 ( 1 << INTC_IRQ_INTX1 )
+#define INTC_INT_PCI0 ( 1 << INTC_IRQ_PCI0 )
+#define INTC_INT_PCI1 ( 1 << INTC_IRQ_PCI1 )
+#define INTC_INT_PCI2 ( 1 << INTC_IRQ_PCI2 )
+#define INTC_INT_SWITCH ( 1 << INTC_IRQ_SWITCH )
+#define INTC_INT_ALL (( 1 << INTC_IRQ_COUNT)-1)
+
+#endif /* _MACH_ADM5120_INTC_H */
--- /dev/null
+/*
+ * ADM5120 MPMC (Multiport Memory Controller) register definitions
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#ifndef _MACH_ADM5120_MPMC_H
+#define _MACH_ADM5120_MPMC_H
+
+#define MPMC_READ_REG(r) __raw_readl( \
+ (void __iomem *)KSEG1ADDR(ADM5120_MPMC_BASE) + MPMC_REG_ ## r)
+#define MPMC_WRITE_REG(r, v) __raw_writel((v), \
+ (void __iomem *)KSEG1ADDR(ADM5120_MPMC_BASE) + MPMC_REG_ ## r)
+
+#define MPMC_REG_CTRL 0x0000
+#define MPMC_REG_STATUS 0x0004
+#define MPMC_REG_CONF 0x0008
+#define MPMC_REG_DC 0x0020
+#define MPMC_REG_DR 0x0024
+#define MPMC_REG_DRP 0x0030
+
+#define MPMC_REG_DC0 0x0100
+#define MPMC_REG_DRC0 0x0104
+#define MPMC_REG_DC1 0x0120
+#define MPMC_REG_DRC1 0x0124
+#define MPMC_REG_DC2 0x0140
+#define MPMC_REG_DRC2 0x0144
+#define MPMC_REG_DC3 0x0160
+#define MPMC_REG_DRC3 0x0164
+#define MPMC_REG_SC0 0x0200 /* for F_CS1_N */
+#define MPMC_REG_SC1 0x0220 /* for F_CS0_N */
+#define MPMC_REG_SC2 0x0240
+#define MPMC_REG_WEN2 0x0244
+#define MPMC_REG_OEN2 0x0248
+#define MPMC_REG_RD2 0x024C
+#define MPMC_REG_PG2 0x0250
+#define MPMC_REG_WR2 0x0254
+#define MPMC_REG_TN2 0x0258
+#define MPMC_REG_SC3 0x0260
+
+/* Control register bits */
+#define MPMC_CTRL_AM ( 1 << 1 ) /* Address Mirror */
+#define MPMC_CTRL_LPM ( 1 << 2 ) /* Low Power Mode */
+#define MPMC_CTRL_DWB ( 1 << 3 ) /* Drain Write Buffers */
+
+/* Status register bits */
+#define MPMC_STATUS_BUSY ( 1 << 0 ) /* Busy */
+#define MPMC_STATUS_WBS ( 1 << 1 ) /* Write Buffer Status */
+#define MPMC_STATUS_SRA ( 1 << 2 ) /* Self-Refresh Acknowledge*/
+
+/* Dynamic Control register bits */
+#define MPMC_DC_CE ( 1 << 0 )
+#define MPMC_DC_DMC ( 1 << 1 )
+#define MPMC_DC_SRR ( 1 << 2 )
+#define MPMC_DC_SI_SHIFT 7
+#define MPMC_DC_SI_MASK ( 3 << 7 )
+#define MPMC_DC_SI_NORMAL ( 0 << 7 )
+#define MPMC_DC_SI_MODE ( 1 << 7 )
+#define MPMC_DC_SI_PALL ( 2 << 7 )
+#define MPMC_DC_SI_NOP ( 3 << 7 )
+
+#define SRAM_REG_CONF 0x00
+#define SRAM_REG_WWE 0x04
+#define SRAM_REG_WOE 0x08
+#define SRAM_REG_WRD 0x0C
+#define SRAM_REG_WPG 0x10
+#define SRAM_REG_WWR 0x14
+#define SRAM_REG_WTR 0x18
+
+/* Dynamic Configuration register bits */
+#define DC_BE (1 << 19) /* buffer enable */
+#define DC_RW_SHIFT 28 /* shift for number of rows */
+#define DC_RW_MASK 0x03
+#define DC_NB_SHIFT 26 /* shift for number of banks */
+#define DC_NB_MASK 0x01
+#define DC_CW_SHIFT 22 /* shift for number of columns */
+#define DC_CW_MASK 0x07
+#define DC_DW_SHIFT 7 /* shift for device width */
+#define DC_DW_MASK 0x03
+
+/* Static Configuration register bits */
+#define SC_MW_MASK 0x03 /* memory width mask */
+#define SC_MW_8 0x00 /* 8 bit memory width */
+#define SC_MW_16 0x01 /* 16 bit memory width */
+#define SC_MW_32 0x02 /* 32 bit memory width */
+
+#endif /* _MACH_ADM5120_MPMC_H */
--- /dev/null
+/*
+ * ADM5120 NAND interface definitions
+ *
+ * This header file defines the hardware registers of the ADM5120 SoC
+ * built-in NAND interface.
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * NAND interface routines was based on a driver for Linux 2.6.19+ which
+ * was derived from the driver for Linux 2.4.xx published by Mikrotik for
+ * their RouterBoard 1xx and 5xx series boards.
+ * Copyright (C) 2007 David Goodenough <david.goodenough@linkchoose.co.uk>
+ * Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#ifndef _MACH_ADM5120_NAND_H
+#define _MACH_ADM5120_NAND_H
+
+#include <linux/types.h>
+#include <linux/io.h>
+
+#include <asm/mach-adm5120/adm5120_defs.h>
+#include <asm/mach-adm5120/adm5120_switch.h>
+
+/* NAND control registers */
+#define NAND_REG_DATA 0x0 /* data register */
+#define NAND_REG_SET_CEn 0x1 /* CE# low */
+#define NAND_REG_CLR_CEn 0x2 /* CE# high */
+#define NAND_REG_CLR_CLE 0x3 /* CLE low */
+#define NAND_REG_SET_CLE 0x4 /* CLE high */
+#define NAND_REG_CLR_ALE 0x5 /* ALE low */
+#define NAND_REG_SET_ALE 0x6 /* ALE high */
+#define NAND_REG_SET_SPn 0x7 /* SP# low (use spare area) */
+#define NAND_REG_CLR_SPn 0x8 /* SP# high (do not use spare area) */
+#define NAND_REG_SET_WPn 0x9 /* WP# low */
+#define NAND_REG_CLR_WPn 0xA /* WP# high */
+#define NAND_REG_STATUS 0xB /* Status register */
+
+#define ADM5120_NAND_STATUS_READY 0x80
+
+#define NAND_READ_REG(r) \
+ readb((void __iomem *)KSEG1ADDR(ADM5120_NAND_BASE) + (r))
+#define NAND_WRITE_REG(r, v) \
+ writeb((v),(void __iomem *)KSEG1ADDR(ADM5120_NAND_BASE) + (r))
+
+/*-------------------------------------------------------------------------*/
+
+static inline void adm5120_nand_enable(void)
+{
+ SW_WRITE_REG(SWITCH_REG_BW_CNTL1, BW_CNTL1_NAND_ENABLE);
+ SW_WRITE_REG(SWITCH_REG_BOOT_DONE, 1);
+}
+
+static inline void adm5120_nand_set_wpn(unsigned int set)
+{
+ NAND_WRITE_REG((set) ? NAND_REG_SET_WPn : NAND_REG_CLR_WPn, 1);
+}
+
+static inline void adm5120_nand_set_spn(unsigned int set)
+{
+ NAND_WRITE_REG((set) ? NAND_REG_SET_SPn : NAND_REG_CLR_SPn, 1);
+}
+
+static inline void adm5120_nand_set_cle(unsigned int set)
+{
+ NAND_WRITE_REG((set) ? NAND_REG_SET_CLE : NAND_REG_CLR_CLE, 1);
+}
+
+static inline void adm5120_nand_set_ale(unsigned int set)
+{
+ NAND_WRITE_REG((set) ? NAND_REG_SET_ALE : NAND_REG_CLR_ALE, 1);
+}
+
+static inline void adm5120_nand_set_cen(unsigned int set)
+{
+ NAND_WRITE_REG((set) ? NAND_REG_SET_CEn : NAND_REG_CLR_CEn, 1);
+}
+
+static inline u8 adm5120_nand_get_status(void)
+{
+ return NAND_READ_REG(NAND_REG_STATUS);
+}
+
+#endif /* _MACH_ADM5120_NAND_H */
--- /dev/null
+/*
+ * ADM5120 specific platform definitions
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#ifndef _ASM_MIPS_MACH_ADM5120_PLATFORM_H
+#define _ASM_MIPS_MACH_ADM5120_PLATFORM_H
+
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/input.h>
+#include <linux/leds.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/nand.h>
+#include <linux/gpio_buttons.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/serial.h>
+
+struct adm5120_flash_platform_data {
+ void (*set_vpp)(struct map_info *, int);
+ void (*switch_bank)(unsigned);
+ u32 window_size;
+#ifdef CONFIG_MTD_PARTITIONS
+ unsigned int nr_parts;
+ struct mtd_partition *parts;
+#endif
+};
+
+struct adm5120_switch_platform_data {
+ /* TODO: not yet implemented */
+};
+
+struct adm5120_pci_irq {
+ u8 slot;
+ u8 func;
+ u8 pin;
+ unsigned irq;
+};
+
+#define PCIIRQ(s,f,p,i) {.slot = (s), .func = (f), .pin = (p), .irq = (i)}
+
+#ifdef CONFIG_PCI
+extern void adm5120_pci_set_irq_map(unsigned int nr_irqs,
+ struct adm5120_pci_irq *map) __init;
+#else
+static inline void adm5120_pci_set_irq_map(unsigned int nr_irqs,
+ struct adm5120_pci_irq *map)
+{
+}
+#endif
+
+extern void adm5120_setup_eth_macs(u8 *mac_base) __init;
+
+extern struct adm5120_flash_platform_data adm5120_flash0_data;
+extern struct adm5120_flash_platform_data adm5120_flash1_data;
+
+extern void adm5120_add_device_flash(unsigned id) __init;
+extern void adm5120_add_device_usb(void) __init;
+extern void adm5120_add_device_uart(unsigned id) __init;
+extern void adm5120_add_device_nand(struct platform_nand_data *pdata) __init;
+extern void adm5120_add_device_switch(unsigned num_ports, u8 *vlan_map) __init;
+extern void adm5120_add_device_gpio(u32 disable_mask) __init;
+extern void adm5120_add_device_gpio_buttons(unsigned nbuttons,
+ struct gpio_button *buttons) __init;
+
+#define GPIO_LED_DEF(g, n, t, a) { \
+ .name = (n), \
+ .default_trigger = (t), \
+ .gpio = (g), \
+ .active_low = (a) \
+}
+
+#define GPIO_LED_STD(g, n, t) GPIO_LED_DEF((g), (n), (t), 0)
+#define GPIO_LED_INV(g, n, t) GPIO_LED_DEF((g), (n), (t), 1)
+
+extern void adm5120_add_device_gpio_leds(unsigned num_leds,
+ struct gpio_led *leds) __init;
+
+#endif /* _ASM_MIPS_MACH_ADM5120_PLATFORM_H */
--- /dev/null
+/*
+ * ADM5120 ethernet switch definitions
+ *
+ * This header file defines the hardware registers of the ADM5120 SoC
+ * built-in Ethernet switch.
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#ifndef _MACH_ADM5120_SWITCH_H
+#define _MACH_ADM5120_SWITCH_H
+
+#ifndef BIT
+# define BIT(at) (1 << (at))
+#endif
+#define BITMASK(len) (BIT(len)-1)
+
+#define SW_READ_REG(r) __raw_readl( \
+ (void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE) + r)
+#define SW_WRITE_REG(r, v) __raw_writel((v), \
+ (void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE) + r)
+
+/* Switch register offsets */
+#define SWITCH_REG_CODE 0x0000
+#define SWITCH_REG_SOFT_RESET 0x0004 /* Soft Reset */
+#define SWITCH_REG_BOOT_DONE 0x0008 /* Boot Done */
+#define SWITCH_REG_SW_RESET 0x000C /* Switch Reset */
+#define SWITCH_REG_PHY_STATUS 0x0014 /* PHY Status */
+#define SWITCH_REG_MEMCTRL 0x001C /* Memory Control */
+#define SWITCH_REG_CPUP_CONF 0x0024 /* CPU Port Configuration */
+#define SWITCH_REG_PORT_CONF0 0x0028 /* Port Configuration 0 */
+#define SWITCH_REG_PORT_CONF1 0x002C /* Port Configuration 1 */
+#define SWITCH_REG_PORT_CONF2 0x0030 /* Port Configuration 2 */
+#define SWITCH_REG_VLAN_G1 0x0040 /* VLAN group 1 */
+#define SWITCH_REG_VLAN_G2 0x0044 /* VLAN group 2 */
+#define SWITCH_REG_SEND_TRIG 0x0048 /* Send Trigger */
+#define SWITCH_REG_MAC_WT0 0x0058 /* MAC Write Address 0 */
+#define SWITCH_REG_MAC_WT1 0x005C /* MAC Write Address 1 */
+#define SWITCH_REG_BW_CNTL0 0x0060 /* Bandwidth Control 0 */
+#define SWITCH_REG_BW_CNTL1 0x0064 /* Bandwidth Control 1 */
+#define SWITCH_REG_PHY_CNTL0 0x0068 /* PHY Control 0 */
+#define SWITCH_REG_PHY_CNTL1 0x006C /* PHY Control 1 */
+#define SWITCH_REG_PORT_TH 0x0078 /* Port Threshold */
+#define SWITCH_REG_PHY_CNTL2 0x007C /* PHY Control 2 */
+#define SWITCH_REG_PHY_CNTL3 0x0080 /* PHY Control 3 */
+#define SWITCH_REG_PRI_CNTL 0x0084 /* Priority Control */
+#define SWITCH_REG_PHY_CNTL4 0x00A0 /* PHY Control 4 */
+#define SWITCH_REG_EMPTY_CNT 0x00A4 /* Empty Count */
+#define SWITCH_REG_PORT_CNTLS 0x00A8 /* Port Control Select */
+#define SWITCH_REG_PORT_CNTL 0x00AC /* Port Control */
+#define SWITCH_REG_INT_STATUS 0x00B0 /* Interrupt Status */
+#define SWITCH_REG_INT_MASK 0x00B4 /* Interrupt Mask */
+#define SWITCH_REG_GPIO_CONF0 0x00B8 /* GPIO Configuration 0 */
+#define SWITCH_REG_GPIO_CONF2 0x00BC /* GPIO Configuration 1 */
+#define SWITCH_REG_WDOG0 0x00C0 /* Watchdog 0 */
+#define SWITCH_REG_WDOG1 0x00C4 /* Watchdog 1 */
+
+#define SWITCH_REG_SHDA 0x00D0 /* Send High Descriptors Address */
+#define SWITCH_REG_SLDA 0x00D4 /* Send Low Descriptors Address */
+#define SWITCH_REG_RHDA 0x00D8 /* Receive High Descriptor Address */
+#define SWITCH_REG_RLDA 0x00DC /* Receive Low Descriptor Address */
+#define SWITCH_REG_SHWA 0x00E0 /* Send High Working Address */
+#define SWITCH_REG_SLWA 0x00E4 /* Send Low Working Address */
+#define SWITCH_REG_RHWA 0x00E8 /* Receive High Working Address */
+#define SWITCH_REG_RLWA 0x00EC /* Receive Low Working Address */
+
+#define SWITCH_REG_TIMER_INT 0x00F0 /* Timer */
+#define SWITCH_REG_TIMER 0x00F4 /* Timer Interrupt */
+
+#define SWITCH_REG_PORT0_LED 0x0100
+#define SWITCH_REG_PORT1_LED 0x0104
+#define SWITCH_REG_PORT2_LED 0x0108
+#define SWITCH_REG_PORT3_LED 0x010C
+#define SWITCH_REG_PORT4_LED 0x0110
+
+/* CODE register bits */
+#define CODE_PC_MASK BITMASK(16) /* Product Code */
+#define CODE_REV_SHIFT 16
+#define CODE_REV_MASK BITMASK(4) /* Product Revision */
+#define CODE_CLKS_SHIFT 20
+#define CODE_CLKS_MASK BITMASK(2) /* Clock Speed */
+#define CODE_CLKS_175 0 /* 175 MHz */
+#define CODE_CLKS_200 1 /* 200 MHz */
+#define CODE_CLKS_225 2 /* 225 MHz */
+#define CODE_CLKS_250 3 /* 250 MHz */
+#define CODE_NAB BIT(24) /* NAND boot */
+#define CODE_PK_MASK BITMASK(1) /* Package type */
+#define CODE_PK_SHIFT 29
+#define CODE_PK_BGA 0 /* BGA package */
+#define CODE_PK_PQFP 1 /* PQFP package */
+
+/* MEMCTRL register bits */
+#define MEMCTRL_SDRS_MASK BITMASK(3) /* SDRAM bank size */
+#define MEMCTRL_SDRS_4M 0x01
+#define MEMCTRL_SDRS_8M 0x02
+#define MEMCTRL_SDRS_16M 0x03
+#define MEMCTRL_SDRS_64M 0x04
+#define MEMCTRL_SDRS_128M 0x05
+#define MEMCTRL_SDR1_ENABLE BIT(5) /* enable SDRAM bank 1 */
+
+#define MEMCTRL_SRS0_SHIFT 8 /* shift for SRAM0 size */
+#define MEMCTRL_SRS1_SHIFT 16 /* shift for SRAM1 size */
+#define MEMCTRL_SRS_MASK BITMASK(3) /* SRAM size mask */
+#define MEMCTRL_SRS_DISABLED 0x00 /* Disabled */
+#define MEMCTRL_SRS_512K 0x01 /* 512KB*/
+#define MEMCTRL_SRS_1M 0x02 /* 1MB */
+#define MEMCTRL_SRS_2M 0x03 /* 2MB */
+#define MEMCTRL_SRS_4M 0x04 /* 4MB */
+
+/* Port bits used in various registers */
+#define SWITCH_PORT_PHY0 BIT(0)
+#define SWITCH_PORT_PHY1 BIT(1)
+#define SWITCH_PORT_PHY2 BIT(2)
+#define SWITCH_PORT_PHY3 BIT(3)
+#define SWITCH_PORT_PHY4 BIT(4)
+#define SWITCH_PORT_MII BIT(5)
+#define SWITCH_PORT_CPU BIT(6)
+
+/* Port bit shorthands */
+#define SWITCH_PORTS_PHY 0x1F /* phy ports */
+#define SWITCH_PORTS_NOCPU 0x3F /* physical ports */
+#define SWITCH_PORTS_ALL 0x7F /* all ports */
+
+/* CPUP_CONF register bits */
+#define CPUP_CONF_DCPUP BIT(0) /* Disable CPU port */
+#define CPUP_CONF_CRCP BIT(1) /* CRC padding from CPU */
+#define CPUP_CONF_BTM BIT(2) /* Bridge Testing Mode */
+#define CPUP_CONF_DUNP_SHIFT 9 /* Disable Unknown Packets for portX */
+#define CPUP_CONF_DMCP_SHIFT 16 /* Disable Mcast Packets form portX */
+#define CPUP_CONF_DBCP_SHIFT 24 /* Disable Bcast Packets form portX */
+
+/* PORT_CONF0 register bits */
+#define PORT_CONF0_DP_SHIFT 0 /* Disable Port */
+#define PORT_CONF0_EMCP_SHIFT 8 /* Enable All MC Packets */
+#define PORT_CONF0_BP_SHIFT 16 /* Enable Back Pressure */
+
+/* PORT_CONF1 register bits */
+#define PORT_CONF1_DISL_SHIFT 0 /* Disable Learning */
+#define PORT_CONF1_BS_SHIFT 6 /* Blocking State */
+#define PORT_CONF1_BM_SHIFT 12 /* Blocking Mode */
+
+/* SEND_TRIG register bits */
+#define SEND_TRIG_STL BIT(0) /* Send Trigger Low */
+#define SEND_TRIG_STH BIT(1) /* Send Trigger High */
+
+/* MAC_WT0 register bits */
+#define MAC_WT0_MAWC BIT(0) /* MAC address write command */
+#define MAC_WT0_MWD_SHIFT 1
+#define MAC_WT0_MWD BIT(1) /* MAC write done */
+#define MAC_WT0_WFB BIT(2) /* Write Filter Bit */
+#define MAC_WT0_WVN_SHIFT 3 /* Write Vlan Number shift */
+#define MAC_WT0_WVE BIT(6) /* Write VLAN enable */
+#define MAC_WT0_WPMN_SHIFT 7
+#define MAC_WT0_WAF_SHIFT 13 /* Write Age Field shift */
+#define MAC_WT0_WAF_EMPTY 0
+#define MAC_WT0_WAF_STATIC 7 /* age: static */
+#define MAC_WT0_MAC0_SHIFT 16
+#define MAC_WT0_MAC1_SHIFT 24
+
+/* MAC_WT1 register bits */
+#define MAC_WT1_MAC2_SHIFT 0
+#define MAC_WT1_MAC3_SHIFT 8
+#define MAC_WT1_MAC4_SHIFT 16
+#define MAC_WT1_MAC5_SHIFT 24
+
+/* BW_CNTL0/BW_CNTL1 register bits */
+#define BW_CNTL_DISABLE 0x00
+#define BW_CNTL_64K 0x01
+#define BW_CNTL_128K 0x02
+#define BW_CNTL_256K 0x03
+#define BW_CNTL_512K 0x04
+#define BW_CNTL_1M 0x05
+#define BW_CNTL_4M 0x06
+#define BW_CNTL_10M 0x07
+
+#define P4TBC_SHIFT 0
+#define P4RBC_SHIFT 4
+#define P5TBC_SHIFT 8
+#define P5RBC_SHIFT 12
+
+#define BW_CNTL1_NAND_ENABLE 0x100
+
+/* PHY_CNTL0 register bits */
+#define PHY_CNTL0_PHYA_MASK BITMASK(5)
+#define PHY_CNTL0_PHYR_MASK BITMASK(5)
+#define PHY_CNTL0_PHYR_SHIFT 8
+#define PHY_CNTL0_WC BIT(13) /* Write Command */
+#define PHY_CNTL0_RC BIT(14) /* Read Command */
+#define PHY_CNTL0_WTD_MASK BIT(16) /* Read Command */
+#define PHY_CNTL0_WTD_SHIFT 16
+
+/* PHY_CNTL1 register bits */
+#define PHY_CNTL1_WOD BIT(0) /* Write Operation Done */
+#define PHY_CNTL1_ROD BIT(1) /* Read Operation Done */
+#define PHY_CNTL1_RD_MASK BITMASK(16)
+#define PHY_CNTL1_RD_SHIFT 16
+
+/* PHY_CNTL2 register bits */
+#define PHY_CNTL2_ANE_SHIFT 0 /* Auto Negotiation Enable */
+#define PHY_CNTL2_SC_SHIFT 5 /* Speed Control */
+#define PHY_CNTL2_DC_SHIFT 10 /* Duplex Control */
+#define PHY_CNTL2_FNCV_SHIFT 15 /* Recommended FC Value */
+#define PHY_CNTL2_PHYR_SHIFT 20 /* PHY reset */
+#define PHY_CNTL2_AMDIX_SHIFT 25 /* Auto MDIX enable */
+/* PHY_CNTL2_RMAE is bad in datasheet */
+#define PHY_CNTL2_RMAE BIT(31) /* Recommended MCC Average enable */
+
+/* PHY_CNTL3 register bits */
+#define PHY_CNTL3_RNT BIT(10) /* Recommend Normal Threshold */
+
+/* PORT_TH register bits */
+#define PORT_TH_PPT_MASK BITMASK(8) /* Per Port Threshold */
+#define PORT_TH_CPUT_SHIFT 8 /* CPU Port Buffer Threshold */
+#define PORT_TH_CPUT_MASK BITMASK(8)
+#define PORT_TH_CPUHT_SHIFT 16 /* CPU Hold Threshold */
+#define PORT_TH_CPUHT_MASK BITMASK(8)
+#define PORT_TH_CPURT_SHIFT 24 /* CPU Release Threshold */
+#define PORT_TH_CPURT_MASK BITMASK(8)
+
+/* EMPTY_CNT register bits */
+#define EMPTY_CNT_EBGB_MASK BITMASK(9) /* Empty Blocks in the Global Buffer */
+
+/* GPIO_CONF0 register bits */
+#define GPIO_CONF0_MASK BITMASK(8)
+#define GPIO_CONF0_IM_SHIFT 0
+#define GPIO_CONF0_IV_SHIFT 8
+#define GPIO_CONF0_OE_SHIFT 16
+#define GPIO_CONF0_OV_SHIFT 24
+#define GPIO_CONF0_IM_MASK (0xFF << GPIO_CONF0_IM_SHIFT)
+#define GPIO_CONF0_IV_MASK (0xFF << GPIO_CONF0_IV_SHIFT)
+#define GPIO_CONF0_OE_MASK (0xFF << GPIO_CONF0_OE_SHIFT)
+#define GPIO_CONF0_OV_MASK (0xFF << GPIO_CONF0_OV_SHIFT)
+
+/* GPIO_CONF2 register bits */
+#define GPIO_CONF2_CSX0 BIT(4) /* enable CSX0:INTX0 on GPIO 1:2 */
+#define GPIO_CONF2_CSX1 BIT(5) /* enable CSX1:INTX1 on GPIO 3:4 */
+#define GPIO_CONF2_EW BIT(6) /* enable wait state pin for CSX0/1 */
+
+/* INT_STATUS/INT_MASK register bits */
+#define SWITCH_INT_SHD BIT(0) /* Send High Done */
+#define SWITCH_INT_SLD BIT(1) /* Send Low Done */
+#define SWITCH_INT_RHD BIT(2) /* Receive High Done */
+#define SWITCH_INT_RLD BIT(3) /* Receive Low Done */
+#define SWITCH_INT_HDF BIT(4) /* High Descriptor Full */
+#define SWITCH_INT_LDF BIT(5) /* Low Descriptor Full */
+#define SWITCH_INT_P0QF BIT(6) /* Port0 Queue Full */
+#define SWITCH_INT_P1QF BIT(7) /* Port1 Queue Full */
+#define SWITCH_INT_P2QF BIT(8) /* Port2 Queue Full */
+#define SWITCH_INT_P3QF BIT(9) /* Port3 Queue Full */
+#define SWITCH_INT_P4QF BIT(10) /* Port4 Queue Full */
+#define SWITCH_INT_P5QF BIT(11) /* Port5 Queue Full */
+#define SWITCH_INT_CPQF BIT(13) /* CPU Queue Full */
+#define SWITCH_INT_GQF BIT(14) /* Global Queue Full */
+#define SWITCH_INT_MD BIT(15) /* Must Drop */
+#define SWITCH_INT_BCS BIT(16) /* BC Storm */
+#define SWITCH_INT_PSC BIT(18) /* Port Status Change */
+#define SWITCH_INT_ID BIT(19) /* Intruder Detected */
+#define SWITCH_INT_W0TE BIT(20) /* Watchdog 0 Timer Expired */
+#define SWITCH_INT_W1TE BIT(21) /* Watchdog 1 Timer Expired */
+#define SWITCH_INT_RDE BIT(22) /* Receive Descriptor Error */
+#define SWITCH_INT_SDE BIT(23) /* Send Descriptor Error */
+#define SWITCH_INT_CPUH BIT(24) /* CPU Hold */
+
+/* TIMER_INT register bits */
+#define TIMER_INT_TOS BIT(0) /* time-out status */
+#define TIMER_INT_TOM BIT(16) /* mask time-out interrupt */
+
+/* TIMER register bits */
+#define TIMER_PERIOD_MASK BITMASK(16) /* mask for timer period */
+#define TIMER_PERIOD_DEFAULT 0xFFFF /* default timer period */
+#define TIMER_TE BIT(16) /* timer enable bit */
+
+/* PORTx_LED register bits */
+#define LED_MODE_MASK BITMASK(4)
+#define LED_MODE_INPUT 0
+#define LED_MODE_FLASH 1
+#define LED_MODE_OUT_HIGH 2
+#define LED_MODE_OUT_LOW 3
+#define LED_MODE_LINK 4
+#define LED_MODE_SPEED 5
+#define LED_MODE_DUPLEX 6
+#define LED_MODE_ACT 7
+#define LED_MODE_COLL 8
+#define LED_MODE_LINK_ACT 9
+#define LED_MODE_DUPLEX_COLL 10
+#define LED_MODE_10M_ACT 11
+#define LED_MODE_100M_ACT 12
+#define LED0_MODE_SHIFT 0 /* LED0 mode shift */
+#define LED1_MODE_SHIFT 4 /* LED1 mode shift */
+#define LED2_MODE_SHIFT 8 /* LED2 mode shift */
+#define LED0_IV_SHIFT 12 /* LED0 input value shift */
+#define LED1_IV_SHIFT 13 /* LED1 input value shift */
+#define LED2_IV_SHIFT 14 /* LED2 input value shift */
+
+#endif /* _MACH_ADM5120_SWITCH_H */
--- /dev/null
+/*
+ * ADM5120 UART definitions
+ *
+ * This header file defines the hardware registers of the ADM5120 SoC
+ * built-in UARTs.
+ *
+ * Copyright (C) 2007 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#ifndef _MACH_ADM5120_UART_H
+#define _MACH_ADM5120_UART_H
+
+#define UART_BAUDDIV(clk, baud) ((clk/(16 * (baud)))-1)
+
+#define UART_REG_DATA 0x00
+#define UART_REG_RSR 0x04
+#define UART_REG_ECR UART_REG_RSR
+#define UART_REG_LCRH 0x08
+#define UART_REG_LCRM 0x0C
+#define UART_REG_LCRL 0x10
+#define UART_REG_CTRL 0x14
+#define UART_REG_FLAG 0x18
+
+/* Receive Status Register bits */
+#define UART_RSR_FE ( 1 << 0 )
+#define UART_RSR_PE ( 1 << 1 )
+#define UART_RSR_BE ( 1 << 2 )
+#define UART_RSR_OE ( 1 << 3 )
+#define UART_RSR_ERR ( UART_RSR_FE | UART_RSR_PE | UART_RSR_BE )
+
+#define UART_ECR_ALL 0xFF
+
+/* Line Control High register bits */
+#define UART_LCRH_BRK ( 1 << 0 ) /* send break */
+#define UART_LCRH_PEN ( 1 << 1 ) /* parity enable */
+#define UART_LCRH_EPS ( 1 << 2 ) /* even parity select */
+#define UART_LCRH_STP1 ( 0 << 3 ) /* one stop bits select */
+#define UART_LCRH_STP2 ( 1 << 3 ) /* two stop bits select */
+#define UART_LCRH_FEN ( 1 << 4 ) /* FIFO enable */
+
+#define UART_LCRH_WLEN5 ( 0 << 5 )
+#define UART_LCRH_WLEN6 ( 1 << 5 )
+#define UART_LCRH_WLEN7 ( 2 << 5 )
+#define UART_LCRH_WLEN8 ( 3 << 5 )
+
+/* Control register bits */
+#define UART_CTRL_EN ( 1 << 0 )
+
+/* Flag register bits */
+#define UART_FLAG_CTS ( 1 << 0 )
+#define UART_FLAG_DSR ( 1 << 1 )
+#define UART_FLAG_DCD ( 1 << 2 )
+#define UART_FLAG_BUSY ( 1 << 3 )
+#define UART_FLAG_RXFE ( 1 << 4 )
+#define UART_FLAG_TXFF ( 1 << 5 )
+#define UART_FLAG_RXFF ( 1 << 6 )
+#define UART_FLAG_TXFE ( 1 << 7 )
+
+#endif /* _MACH_ADM5120_UART_H */
--- /dev/null
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+/* DO NOT EDIT!! - this file automatically generated
+ * from .s file by awk -f s2h.awk
+ */
+/* Size definitions
+ * Copyright (C) ARM Limited 1998. All rights reserved.
+ */
+
+#ifndef __sizes_h
+#define __sizes_h 1
+
+/* handy sizes */
+#define SZ_16 0x00000010
+#define SZ_256 0x00000100
+#define SZ_512 0x00000200
+
+#define SZ_1K 0x00000400
+#define SZ_4K 0x00001000
+#define SZ_8K 0x00002000
+#define SZ_16K 0x00004000
+#define SZ_64K 0x00010000
+#define SZ_128K 0x00020000
+#define SZ_256K 0x00040000
+#define SZ_512K 0x00080000
+
+#define SZ_1M 0x00100000
+#define SZ_2M 0x00200000
+#define SZ_4M 0x00400000
+#define SZ_8M 0x00800000
+#define SZ_16M 0x01000000
+#define SZ_32M 0x02000000
+#define SZ_64M 0x04000000
+#define SZ_128M 0x08000000
+#define SZ_256M 0x10000000
+#define SZ_512M 0x20000000
+
+#define SZ_1G 0x40000000
+#define SZ_2G 0x80000000
+
+#endif
+
+/* END */
--- /dev/null
+/*
+ * ADM5120 specific CPU feature overrides
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This file was derived from: include/asm-mips/cpu-features.h
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ * Copyright (C) 2004 Maciej W. Rozycki
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+#ifndef __ASM_MACH_ADM5120_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_ADM5120_CPU_FEATURE_OVERRIDES_H
+
+/*
+ * The ADM5120 SOC has a built-in MIPS 4Kc core.
+ */
+#define cpu_has_tlb 1
+#define cpu_has_4kex 1
+#define cpu_has_3k_cache 0
+#define cpu_has_4k_cache 1
+#define cpu_has_tx39_cache 0
+#define cpu_has_sb1_cache 0
+#define cpu_has_fpu 0
+#define cpu_has_32fpr 0
+#define cpu_has_counter 1
+#define cpu_has_watch 1
+#define cpu_has_divec 1
+/* #define cpu_has_vce ? */
+/* #define cpu_has_cache_cdex_p ? */
+/* #define cpu_has_cache_cdex_s ? */
+#define cpu_has_prefetch 1
+/* #define cpu_has_mcheck ? */
+#define cpu_has_ejtag 1
+#define cpu_has_llsc 1
+
+#define cpu_has_mips16 0
+#define cpu_has_mdmx 0
+#define cpu_has_mips3d 0
+#define cpu_has_smartmips 0
+
+/* #define cpu_has_vtag_icache ? */
+/* #define cpu_has_dc_aliases ? */
+/* #define cpu_has_ic_fills_f_dc ? */
+/* #define cpu_has_pindexed_dcache ? */
+
+/* #define cpu_icache_snoops_remote_store ? */
+
+#define cpu_has_mips32r1 1
+#define cpu_has_mips32r2 0
+#define cpu_has_mips64r1 0
+#define cpu_has_mips64r2 0
+
+#define cpu_has_dsp 0
+#define cpu_has_mipsmt 0
+
+/* #define cpu_has_nofpuex ? */
+#define cpu_has_64bits 0
+#define cpu_has_64bit_zero_reg 0
+#define cpu_has_64bit_gp_regs 0
+#define cpu_has_64bit_addresses 0
+
+/* #define cpu_has_inclusive_pcaches ? */
+
+#define cpu_dcache_line_size() 16
+#define cpu_icache_line_size() 16
+
+#endif /* __ASM_MACH_ADM5120_CPU_FEATURE_OVERRIDES_H */
--- /dev/null
+/*
+ * ADM5120 GPIO wrappers for arch-neutral GPIO calls
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#ifndef _ASM_MIPS_MACH_ADM5120_GPIO_H
+#define _ASM_MIPS_MACH_ADM5120_GPIO_H
+
+#define ARCH_NR_GPIOS 64
+
+#include <asm-generic/gpio.h>
+
+#include <asm/mach-adm5120/adm5120_switch.h>
+
+#define ADM5120_GPIO_PIN0 0
+#define ADM5120_GPIO_PIN1 1
+#define ADM5120_GPIO_PIN2 2
+#define ADM5120_GPIO_PIN3 3
+#define ADM5120_GPIO_PIN4 4
+#define ADM5120_GPIO_PIN5 5
+#define ADM5120_GPIO_PIN6 6
+#define ADM5120_GPIO_PIN7 7
+#define ADM5120_GPIO_P0L0 8
+#define ADM5120_GPIO_P0L1 9
+#define ADM5120_GPIO_P0L2 10
+#define ADM5120_GPIO_P1L0 11
+#define ADM5120_GPIO_P1L1 12
+#define ADM5120_GPIO_P1L2 13
+#define ADM5120_GPIO_P2L0 14
+#define ADM5120_GPIO_P2L1 15
+#define ADM5120_GPIO_P2L2 16
+#define ADM5120_GPIO_P3L0 17
+#define ADM5120_GPIO_P3L1 18
+#define ADM5120_GPIO_P3L2 19
+#define ADM5120_GPIO_P4L0 20
+#define ADM5120_GPIO_P4L1 21
+#define ADM5120_GPIO_P4L2 22
+#define ADM5120_GPIO_MAX 22
+#define ADM5120_GPIO_COUNT ADM5120_GPIO_MAX+1
+
+#define ADM5120_GPIO_LOW 0
+#define ADM5120_GPIO_HIGH 1
+
+#define ADM5120_GPIO_SWITCH 0x10
+#define ADM5120_GPIO_FLASH (ADM5120_GPIO_SWITCH | LED_MODE_FLASH)
+#define ADM5120_GPIO_LINK (ADM5120_GPIO_SWITCH | LED_MODE_LINK)
+#define ADM5120_GPIO_SPEED (ADM5120_GPIO_SWITCH | LED_MODE_SPEED)
+#define ADM5120_GPIO_DUPLEX (ADM5120_GPIO_SWITCH | LED_MODE_DUPLEX)
+#define ADM5120_GPIO_ACT (ADM5120_GPIO_SWITCH | LED_MODE_ACT)
+#define ADM5120_GPIO_COLL (ADM5120_GPIO_SWITCH | LED_MODE_COLL)
+#define ADM5120_GPIO_LINK_ACT (ADM5120_GPIO_SWITCH | LED_MODE_LINK_ACT)
+#define ADM5120_GPIO_DUPLEX_COLL (ADM5120_GPIO_SWITCH | LED_MODE_DUPLEX_COLL)
+#define ADM5120_GPIO_10M_ACT (ADM5120_GPIO_SWITCH | LED_MODE_10M_ACT)
+#define ADM5120_GPIO_100M_ACT (ADM5120_GPIO_SWITCH | LED_MODE_100M_ACT)
+
+extern int __adm5120_gpio0_get_value(unsigned gpio);
+extern void __adm5120_gpio0_set_value(unsigned gpio, int value);
+extern int __adm5120_gpio1_get_value(unsigned gpio);
+extern void __adm5120_gpio1_set_value(unsigned gpio, int value);
+extern int adm5120_gpio_to_irq(unsigned gpio);
+extern int adm5120_irq_to_gpio(unsigned irq);
+
+static inline int gpio_get_value(unsigned gpio)
+{
+ int ret;
+
+ switch (gpio) {
+ case ADM5120_GPIO_PIN0 ... ADM5120_GPIO_PIN7:
+ ret = __adm5120_gpio0_get_value(gpio);
+ break;
+ case ADM5120_GPIO_P0L0 ... ADM5120_GPIO_P4L2:
+ ret = __adm5120_gpio1_get_value(gpio - ADM5120_GPIO_P0L0);
+ break;
+ default:
+ ret = __gpio_get_value(gpio);
+ break;
+ }
+
+ return ret;
+}
+
+static inline void gpio_set_value(unsigned gpio, int value)
+{
+ switch (gpio) {
+ case ADM5120_GPIO_PIN0 ... ADM5120_GPIO_PIN7:
+ __adm5120_gpio0_set_value(gpio, value);
+ break;
+ case ADM5120_GPIO_P0L0 ... ADM5120_GPIO_P4L2:
+ __adm5120_gpio1_set_value(gpio - ADM5120_GPIO_P0L0, value);
+ break;
+ default:
+ __gpio_set_value(gpio, value);
+ break;
+ }
+}
+
+static inline int gpio_to_irq(unsigned gpio)
+{
+ return adm5120_gpio_to_irq(gpio);
+}
+
+static inline int irq_to_gpio(unsigned irq)
+{
+ return adm5120_irq_to_gpio(irq);
+}
+
+#define gpio_cansleep __gpio_cansleep
+
+#endif /* _ASM_MIPS_MACH_ADM5120_GPIO_H */
--- /dev/null
+/*
+ * ADM5120 specific IRQ numbers
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+#ifndef _ASM_MIPS_MACH_ADM5120_IRQ_H
+#define _ASM_MIPS_MACH_ADM5120_IRQ_H
+
+#define MIPS_CPU_IRQ_BASE 0
+#define NR_IRQS 24
+
+#include_next <irq.h>
+
+#include <asm/mach-adm5120/adm5120_intc.h>
+
+#define NO_IRQ (-1)
+
+#define MIPS_CPU_IRQ_COUNT 8
+#define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x))
+
+#define ADM5120_INTC_IRQ_BASE (MIPS_CPU_IRQ_BASE + MIPS_CPU_IRQ_COUNT)
+#define ADM5120_INTC_IRQ(x) (ADM5120_INTC_IRQ_BASE + (x))
+
+#define ADM5120_IRQ_INTC MIPS_CPU_IRQ(2)
+#define ADM5120_IRQ_COUNTER MIPS_CPU_IRQ(7)
+
+#define ADM5120_IRQ_TIMER ADM5120_INTC_IRQ(INTC_IRQ_TIMER)
+#define ADM5120_IRQ_UART0 ADM5120_INTC_IRQ(INTC_IRQ_UART0)
+#define ADM5120_IRQ_UART1 ADM5120_INTC_IRQ(INTC_IRQ_UART1)
+#define ADM5120_IRQ_USBC ADM5120_INTC_IRQ(INTC_IRQ_USBC)
+#define ADM5120_IRQ_GPIO2 ADM5120_INTC_IRQ(INTC_IRQ_GPIO2)
+#define ADM5120_IRQ_GPIO4 ADM5120_INTC_IRQ(INTC_IRQ_GPIO4)
+#define ADM5120_IRQ_PCI0 ADM5120_INTC_IRQ(INTC_IRQ_PCI0)
+#define ADM5120_IRQ_PCI1 ADM5120_INTC_IRQ(INTC_IRQ_PCI1)
+#define ADM5120_IRQ_PCI2 ADM5120_INTC_IRQ(INTC_IRQ_PCI2)
+#define ADM5120_IRQ_SWITCH ADM5120_INTC_IRQ(INTC_IRQ_SWITCH)
+
+#endif /* _ASM_MIPS_MACH_ADM5120_IRQ_H */
--- /dev/null
+/*
+ * ADMBoot specific definitions
+ *
+ * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#ifndef _ADMBOOT_H
+#define _ADMBOOT_H
+
+extern int admboot_get_mac_base(u32 offset, u32 len, u8 *mac) __init;
+
+#endif /* _ADMBOOT_H */
--- /dev/null
+/*
+ * Broadcom's CFE definitions
+ *
+ * Copyright (C) 2006-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#ifndef _PROM_CFE_H_
+#define _PROM_CFE_H_
+
+extern int cfe_present(void) __init;
+extern char *cfe_getenv(char *);
+
+#endif /*_PROM_CFE_H_*/
--- /dev/null
+/*
+ * Generic prom definitions
+ *
+ * Copyright (C) 2006-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#ifndef _PROM_GENERIC_H_
+#define _PROM_GENERIC_H_
+
+extern int generic_prom_present(void) __init;
+extern char *generic_prom_getenv(char *);
+
+#endif /*_PROM_GENERIC_H_*/
--- /dev/null
+/*
+ * Compex's MyLoader specific definitions
+ *
+ * Copyright (C) 2006-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#ifndef _MYLOADER_H_
+#define _MYLOADER_H_
+
+/*
+ * Firmware file format:
+ *
+ * <header>
+ * [<block descriptor 0>]
+ * ...
+ * [<block descriptor n>]
+ * <null block descriptor>
+ * [<block data 0>]
+ * ...
+ * [<block data n>]
+ *
+ *
+ */
+
+/* Myloader specific magic numbers */
+#define MYLO_MAGIC_FIRMWARE 0x4C594D00
+#define MYLO_MAGIC_20021103 0x20021103
+#define MYLO_MAGIC_20021107 0x20021107
+
+#define MYLO_MAGIC_SYS_PARAMS MYLO_MAGIC_20021107
+#define MYLO_MAGIC_PARTITIONS MYLO_MAGIC_20021103
+#define MYLO_MAGIC_BOARD_PARAMS MYLO_MAGIC_20021103
+
+/*
+ * Addresses of the data structures provided by MyLoader
+ */
+#define MYLO_MIPS_SYS_PARAMS 0x80000800 /* System Parameters */
+#define MYLO_MIPS_BOARD_PARAMS 0x80000A00 /* Board Parameters */
+#define MYLO_MIPS_PARTITIONS 0x80000C00 /* Partition Table */
+#define MYLO_MIPS_BOOT_PARAMS 0x80000E00 /* Boot Parameters */
+
+/* Vendor ID's (seems to be same as the PCI vendor ID's) */
+#define VENID_COMPEX 0x11F6
+
+/* Devices based on the ADM5120 */
+#define DEVID_COMPEX_NP27G 0x0078
+#define DEVID_COMPEX_NP28G 0x044C
+#define DEVID_COMPEX_NP28GHS 0x044E
+#define DEVID_COMPEX_WP54Gv1C 0x0514
+#define DEVID_COMPEX_WP54G 0x0515
+#define DEVID_COMPEX_WP54AG 0x0546
+#define DEVID_COMPEX_WPP54AG 0x0550
+#define DEVID_COMPEX_WPP54G 0x0555
+
+/* Devices based on the IXP422 */
+#define DEVID_COMPEX_WP18 0x047E
+#define DEVID_COMPEX_NP18A 0x0489
+
+/* Other devices */
+#define DEVID_COMPEX_NP26G8M 0x03E8
+#define DEVID_COMPEX_NP26G16M 0x03E9
+
+struct mylo_fw_header {
+ uint32_t magic; /* must be MYLO_MAGIC_FIRMWARE */
+ uint32_t crc; /* CRC of the whole firmware */
+ uint32_t res0; /* unknown/unused */
+ uint32_t res1; /* unknown/unused */
+ uint16_t vid; /* vendor ID */
+ uint16_t did; /* device ID */
+ uint16_t svid; /* sub vendor ID */
+ uint16_t sdid; /* sub device ID */
+ uint32_t rev; /* device revision */
+ uint32_t fwhi; /* FIXME: firmware version high? */
+ uint32_t fwlo; /* FIXME: firmware version low? */
+ uint32_t flags; /* firmware flags */
+};
+
+#define FW_FLAG_BOARD_PARAMS_WP 0x01 /* board parameters are write protected */
+#define FW_FLAG_BOOT_SECTOR_WE 0x02 /* enable of write boot sectors (below 64K) */
+
+struct mylo_fw_blockdesc {
+ uint32_t type; /* block type */
+ uint32_t addr; /* relative address to flash start */
+ uint32_t dlen; /* size of block data in bytes */
+ uint32_t blen; /* total size of block in bytes */
+};
+
+#define FW_DESC_TYPE_UNUSED 0
+#define FW_DESC_TYPE_USED 1
+
+struct mylo_partition {
+ uint16_t flags; /* partition flags */
+ uint16_t type; /* type of the partition */
+ uint32_t addr; /* relative address of the partition from the
+ flash start */
+ uint32_t size; /* size of the partition in bytes */
+ uint32_t param; /* if this is the active partition, the
+ MyLoader load code to this address */
+};
+
+#define PARTITION_FLAG_ACTIVE 0x8000 /* this is the active partition,
+ * MyLoader loads firmware from here */
+#define PARTITION_FLAG_ISRAM 0x2000 /* FIXME: this is a RAM partition? */
+#define PARTIIION_FLAG_RAMLOAD 0x1000 /* FIXME: load this partition into the RAM? */
+#define PARTITION_FLAG_PRELOAD 0x0800 /* the partition data preloaded to RAM
+ * before decompression */
+#define PARTITION_FLAG_HAVEHDR 0x0002 /* the partition data have a header */
+
+#define PARTITION_TYPE_FREE 0
+#define PARTITION_TYPE_USED 1
+
+#define MYLO_MAX_PARTITIONS 8 /* maximum number of partitions in the
+ partition table */
+
+struct mylo_partition_table {
+ uint32_t magic; /* must be MYLO_MAGIC_PARTITIONS */
+ uint32_t res0; /* unknown/unused */
+ uint32_t res1; /* unknown/unused */
+ uint32_t res2; /* unknown/unused */
+ struct mylo_partition partitions[MYLO_MAX_PARTITIONS];
+};
+
+struct mylo_partition_header {
+ uint32_t len; /* length of the partition data */
+ uint32_t crc; /* CRC value of the partition data */
+};
+
+struct mylo_system_params {
+ uint32_t magic; /* must be MYLO_MAGIC_SYS_PARAMS */
+ uint32_t res0;
+ uint32_t res1;
+ uint32_t mylo_ver;
+ uint16_t vid; /* Vendor ID */
+ uint16_t did; /* Device ID */
+ uint16_t svid; /* Sub Vendor ID */
+ uint16_t sdid; /* Sub Device ID */
+ uint32_t rev; /* device revision */
+ uint32_t fwhi;
+ uint32_t fwlo;
+ uint32_t tftp_addr;
+ uint32_t prog_start;
+ uint32_t flash_size; /* Size of boot FLASH in bytes */
+ uint32_t dram_size; /* Size of onboard RAM in bytes */
+};
+
+
+struct mylo_eth_addr {
+ uint8_t mac[6];
+ uint8_t csum[2];
+};
+
+#define MYLO_ETHADDR_COUNT 8 /* maximum number of ethernet address
+ in the board parameters */
+
+struct mylo_board_params {
+ uint32_t magic; /* must be MYLO_MAGIC_BOARD_PARAMS */
+ uint32_t res0;
+ uint32_t res1;
+ uint32_t res2;
+ struct mylo_eth_addr addr[MYLO_ETHADDR_COUNT];
+};
+
+struct myloader_info {
+ u32 vid;
+ u32 did;
+ u32 svid;
+ u32 sdid;
+ uint8_t macs[MYLO_ETHADDR_COUNT][6];
+};
+
+extern struct myloader_info myloader_info;
+extern int myloader_present(void) __init;
+
+#endif /* _MYLOADER_H_*/
--- /dev/null
+/*
+ * Mikrotik's RouterBOOT definitions
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#ifndef _ROUTERBOOT_H
+#define _ROUTERBOOT_H
+
+#define RB_MAC_SIZE 6
+
+struct rb_bios_settings {
+ u32 hs_offs; /* hard settings offset */
+ u32 hs_size; /* hard settings size */
+ u32 fw_offs; /* firmware offset */
+ u32 ss_offs; /* soft settings offset */
+ u32 ss_size; /* soft settings size */
+};
+
+struct rb_hard_settings {
+ char *name; /* board name */
+ char *bios_ver; /* BIOS version */
+ u32 mem_size; /* memory size in bytes */
+ u32 mac_count; /* number of mac addresses */
+ u8 *mac_base; /* mac address base */
+};
+
+/*
+ * Magic numbers
+ */
+#define RB_MAGIC_HARD 0x64726148 /* "Hard" */
+#define RB_MAGIC_SOFT 0x74666F53 /* "Soft" */
+#define RB_MAGIC_DAWN 0x6E776144 /* "Dawn" */
+
+#define RB_ID_TERMINATOR 0
+
+/*
+ * ID values for Hardware settings
+ */
+#define RB_ID_HARD_01 1
+#define RB_ID_HARD_02 2
+#define RB_ID_FLASH_INFO 3
+#define RB_ID_MAC_ADDRESS_PACK 4
+#define RB_ID_BOARD_NAME 5
+#define RB_ID_BIOS_VERSION 6
+#define RB_ID_HARD_07 7
+#define RB_ID_SDRAM_TIMINGS 8
+#define RB_ID_DEVICE_TIMINGS 9
+#define RB_ID_SOFTWARE_ID 10
+#define RB_ID_SERIAL_NUMBER 11
+#define RB_ID_HARD_12 12
+#define RB_ID_MEMORY_SIZE 13
+#define RB_ID_MAC_ADDRESS_COUNT 14
+
+/*
+ * ID values for Software settings
+ */
+#define RB_ID_UART_SPEED 1
+#define RB_ID_BOOT_DELAY 2
+#define RB_ID_BOOT_DEVICE 3
+#define RB_ID_BOOT_KEY 4
+#define RB_ID_CPU_MODE 5
+#define RB_ID_FW_VERSION 6
+#define RB_ID_SOFT_07 7
+#define RB_ID_SOFT_08 8
+#define RB_ID_BOOT_PROTOCOL 9
+#define RB_ID_SOFT_10 10
+#define RB_ID_SOFT_11 11
+
+/*
+ * UART_SPEED values
+ */
+#define RB_UART_SPEED_115200 0
+#define RB_UART_SPEED_57600 1
+#define RB_UART_SPEED_38400 2
+#define RB_UART_SPEED_19200 3
+#define RB_UART_SPEED_9600 4
+#define RB_UART_SPEED_4800 5
+#define RB_UART_SPEED_2400 6
+#define RB_UART_SPEED_1200 7
+
+/*
+ * BOOT_DELAY values
+ */
+#define RB_BOOT_DELAY_0SEC 0
+#define RB_BOOT_DELAY_1SEC 1
+#define RB_BOOT_DELAY_2SEC 2
+
+/*
+ * BOOT_DEVICE values
+ */
+#define RB_BOOT_DEVICE_ETHER 0
+#define RB_BOOT_DEVICE_NANDETH 1
+#define RB_BOOT_DEVICE_ETHONCE 2
+#define RB_BOOT_DEVICE_NANDONLY 3
+
+/*
+ * BOOT_KEY values
+ */
+#define RB_BOOT_KEY_ANY 0
+#define RB_BOOT_KEY_DEL 1
+
+/*
+ * CPU_MODE values
+ */
+#define RB_CPU_MODE_POWERSAVE 0
+#define RB_CPU_MODE_REGULAR 1
+
+/*
+ * BOOT_PROTOCOL values
+ */
+#define RB_BOOT_PROTOCOL_BOOTP 0
+#define RB_BOOT_PROTOCOL_DHCP 1
+
+extern int routerboot_present(void) __init;
+extern char *routerboot_get_boardname(void);
+
+extern struct rb_hard_settings rb_hs;
+
+#endif /* _ROUTERBOOT_H */
--- /dev/null
+/*
+ * ZyNOS (ZyXEL's Networking OS) definitions
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#ifndef _ZYNOS_H
+#define _ZYNOS_H
+
+#define ZYNOS_NAME_LEN 32
+#define ZYNOS_FEAT_BYTES 22
+#define ZYNOS_MAC_LEN 6
+
+struct zynos_board_info {
+ unsigned char vendor[ZYNOS_NAME_LEN];
+ unsigned char product[ZYNOS_NAME_LEN];
+ u32 bootext_addr;
+ u32 res0;
+ u16 board_id;
+ u8 res1[6];
+ u8 feat_other[ZYNOS_FEAT_BYTES];
+ u8 feat_main;
+ u8 res2;
+ u8 mac[ZYNOS_MAC_LEN];
+ u8 country;
+ u8 dbgflag;
+} __attribute__ ((packed));
+
+/*
+ * Vendor IDs
+ */
+#define ZYNOS_VENDOR_ID_ZYXEL 0
+#define ZYNOS_VENDOR_ID_NETGEAR 1
+#define ZYNOS_VENDOR_ID_DLINK 2
+#define ZYNOS_VENDOR_ID_OTHER 3
+#define ZYNOS_VENDOR_ID_LUCENT 4
+
+/*
+ * Vendor names
+ */
+#define ZYNOS_VENDOR_DLINK "D-Link"
+#define ZYNOS_VENDOR_LUCENT "LUCENT"
+#define ZYNOS_VENDOR_NETGEAR "NetGear"
+#define ZYNOS_VENDOR_ZYXEL "ZyXEL"
+
+/*
+ * Board IDs (big-endian)
+ */
+#define ZYNOS_BOARD_ES2108 0x00F2 /* Ethernet Switch 2108 */
+#define ZYNOS_BOARD_ES2108F 0x01AF /* Ethernet Switch 2108-F */
+#define ZYNOS_BOARD_ES2108G 0x00F3 /* Ethernet Switch 2108-G */
+#define ZYNOS_BOARD_ES2108LC 0x00FC /* Ethernet Switch 2108-LC */
+#define ZYNOS_BOARD_ES2108PWR 0x00F4 /* Ethernet Switch 2108PWR */
+#define ZYNOS_BOARD_HS100 0x9FF1 /* HomeSafe 100/100W */
+#define ZYNOS_BOARD_P334 0x9FF5 /* Prestige 334 */
+#define ZYNOS_BOARD_P334U 0x9FDD /* Prestige 334U */
+#define ZYNOS_BOARD_P334W 0x9FF3 /* Prestige 334W */
+#define ZYNOS_BOARD_P334WH 0x00E0 /* Prestige 334WH */
+#define ZYNOS_BOARD_P334WHD 0x00E1 /* Prestige 334WHD */
+#define ZYNOS_BOARD_P334WT 0x9FEF /* Prestige 334WT */
+#define ZYNOS_BOARD_P334WT_ALT 0x9F02 /* Prestige 334WT alternative*/
+#define ZYNOS_BOARD_P335 0x9FED /* Prestige 335/335WT */
+#define ZYNOS_BOARD_P335PLUS 0x0025 /* Prestige 335Plus */
+#define ZYNOS_BOARD_P335U 0x9FDC /* Prestige 335U */
+
+/*
+ * Some magic numbers (big-endian)
+ */
+#define ZYNOS_MAGIC_DBGAREA1 0x48646267 /* "Hdbg" */
+#define ZYNOS_MAGIC_DBGAREA2 0x61726561 /* "area" */
+
+struct bootbase_info {
+ u16 vendor_id;
+ u16 board_id;
+ u8 mac[6];
+};
+
+extern struct bootbase_info bootbase_info;
+extern int bootbase_present(void) __init;
+
+#endif /* _ZYNOS_H */
--- /dev/null
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_ADM5120_WAR_H
+#define __ASM_MIPS_MACH_ADM5120_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR 0
+#define R4600_V1_HIT_CACHEOP_WAR 0
+#define R4600_V2_HIT_CACHEOP_WAR 0
+#define R5432_CP0_INTERRUPT_WAR 0
+#define BCM1250_M3_WAR 0
+#define SIBYTE_1956_WAR 0
+#define MIPS4K_ICACHE_REFILL_WAR 0
+#define MIPS_CACHE_SYNC_WAR 0
+#define TX49XX_ICACHE_INDEX_INV_WAR 0
+#define RM9000_CDEX_SMP_WAR 0
+#define ICACHE_REFILLS_WORKAROUND_WAR 0
+#define R10000_LLSC_WAR 0
+#define MIPS34K_MISSED_ITLB_WAR 0
+
+#endif /* __ASM_MIPS_MACH_ADM5120_WAR_H */
+++ /dev/null
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -18,6 +18,21 @@
- prompt "System type"
- default SGI_IP22
-
-+config ADM5120
-+ bool "Infineon/ADMtek ADM5120 SoC based machines"
-+ select CEVT_R4K
-+ select CSRC_R4K
-+ select SYS_HAS_CPU_MIPS32_R1
-+ select SYS_HAS_EARLY_PRINTK
-+ select DMA_NONCOHERENT
-+ select IRQ_CPU
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
-+ select SYS_SUPPORTS_BIG_ENDIAN
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select GENERIC_GPIO
-+ select HAVE_GPIO_LIB
-+ select SWAP_IO_SPACE if CPU_BIG_ENDIAN
-+
- config MACH_ALCHEMY
- bool "Alchemy processor based machines"
-
-@@ -687,6 +702,7 @@
-
- endchoice
-
-+source "arch/mips/adm5120/Kconfig"
- source "arch/mips/au1000/Kconfig"
- source "arch/mips/basler/excite/Kconfig"
- source "arch/mips/jazz/Kconfig"
---- a/arch/mips/Makefile
-+++ b/arch/mips/Makefile
-@@ -174,6 +174,21 @@
- load-$(CONFIG_MACH_JAZZ) += 0xffffffff80080000
-
- #
-+# Infineon/ADMtek ADM5120
-+#
-+libs-$(CONFIG_ADM5120) += arch/mips/adm5120/prom/
-+core-$(CONFIG_ADM5120) += arch/mips/adm5120/common/
-+core-$(CONFIG_ADM5120_OEM_CELLVISION) += arch/mips/adm5120/cellvision/
-+core-$(CONFIG_ADM5120_OEM_COMPEX) += arch/mips/adm5120/compex/
-+core-$(CONFIG_ADM5120_OEM_EDIMAX) += arch/mips/adm5120/edimax/
-+core-$(CONFIG_ADM5120_OEM_INFINEON) += arch/mips/adm5120/infineon/
-+core-$(CONFIG_ADM5120_OEM_MIKROTIK) += arch/mips/adm5120/mikrotik/
-+core-$(CONFIG_ADM5120_OEM_MOTOROLA) += arch/mips/adm5120/motorola/
-+core-$(CONFIG_ADM5120_OEM_ZYXEL) += arch/mips/adm5120/zyxel/
-+cflags-$(CONFIG_ADM5120) += -Iinclude/asm-mips/mach-adm5120
-+load-$(CONFIG_ADM5120) += 0xffffffff80001000
-+
-+#
- # Common Alchemy Au1x00 stuff
- #
- core-$(CONFIG_SOC_AU1X00) += arch/mips/au1000/common/
---- a/include/asm-mips/bootinfo.h
-+++ b/include/asm-mips/bootinfo.h
-@@ -94,6 +94,55 @@
- #define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */
- #define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */
-
-+/*
-+ * Valid machtype for group ADM5120
-+ */
-+#define MACH_ADM5120_GENERIC 0 /* Generic board */
-+#define MACH_ADM5120_WP54G_WRT 1 /* Compex WP54G-WRT */
-+#define MACH_ADM5120_WP54 2 /* Compex WP54G/WP54AG/WPP54G/WPP54AG */
-+#define MACH_ADM5120_NP28G 3 /* Compex NP28G */
-+#define MACH_ADM5120_NP28GHS 4 /* Compex NP28G HotSpot */
-+#define MACH_ADM5120_NP27G 5 /* Compex NP27G */
-+#define MACH_ADM5120_WP54Gv1C 6 /* Compex WP54G version 1C */
-+#define MACH_ADM5120_RB_11X 7 /* Mikrotik RouterBOARD 111/112 */
-+#define MACH_ADM5120_RB_133 8 /* Mikrotik RouterBOARD 133 */
-+#define MACH_ADM5120_RB_133C 9 /* Mikrotik RouterBOARD 133c */
-+#define MACH_ADM5120_RB_150 10 /* Mikrotik RouterBOARD 150 */
-+#define MACH_ADM5120_RB_153 11 /* Mikrotik RouterBOARD 153 */
-+#define MACH_ADM5120_RB_192 12 /* Mikrotik RouterBOARD 192 */
-+#define MACH_ADM5120_HS100 13 /* ZyXEL HomeSafe 100/100W */
-+#define MACH_ADM5120_P334U 14 /* ZyXEL Prestige 334U */
-+#define MACH_ADM5120_P334W 15 /* ZyXEL Prestige 334W */
-+#define MACH_ADM5120_P334WH 16 /* ZyXEL Prestige 334WH */
-+#define MACH_ADM5120_P334WHD 17 /* ZyXEL Prestige 334WHD */
-+#define MACH_ADM5120_P334WT 18 /* ZyXEL Prestige 334WT */
-+#define MACH_ADM5120_P335 19 /* ZyXEL Prestige 335/335WT */
-+#define MACH_ADM5120_P335PLUS 20 /* ZyXEL Prestige 335Plus */
-+#define MACH_ADM5120_P335U 21 /* ZyXEL Prestige 335U */
-+#define MACH_ADM5120_ES2108 22 /* ZyXEL Ethernet Switch 2108 */
-+#define MACH_ADM5120_ES2108F 23 /* ZyXEL Ethernet Switch 2108-F */
-+#define MACH_ADM5120_ES2108G 24 /* ZyXEL Ethernet Switch 2108-G */
-+#define MACH_ADM5120_ES2108LC 25 /* ZyXEL Ethernet Switch 2108-LC */
-+#define MACH_ADM5120_ES2108PWR 26 /* ZyXEL Ethernet Switch 2108-PWR */
-+#define MACH_ADM5120_ES2024A 27 /* ZyXEL Ethernet Switch 2024A */
-+#define MACH_ADM5120_ES2024PWR 28 /* ZyXEL Ethernet Switch 2024PWR */
-+#define MACH_ADM5120_CAS630 29 /* Cellvision CAS-630/630W */
-+#define MACH_ADM5120_CAS670 30 /* Cellvision CAS-670/670W */
-+#define MACH_ADM5120_CAS700 31 /* Cellvision CAS-700/700W */
-+#define MACH_ADM5120_CAS771 32 /* Cellvision CAS-771/771W */
-+#define MACH_ADM5120_CAS790 33 /* Cellvision CAS-790 */
-+#define MACH_ADM5120_CAS861 34 /* Cellvision CAS-861/861W */
-+#define MACH_ADM5120_NFS101U 35 /* Cellvision NFS-101U/101WU */
-+#define MACH_ADM5120_NFS202U 36 /* Cellvision NFS-202U/202WU */
-+#define MACH_ADM5120_EASY5120PATA 37 /* Infineon EASY 5120P-ATA */
-+#define MACH_ADM5120_EASY5120RT 38 /* Infineon EASY 5120-RT */
-+#define MACH_ADM5120_EASY5120WVOIP 39 /* Infineon EASY 5120-WVoIP */
-+#define MACH_ADM5120_EASY83000 40 /* Infineon EASY-83000 */
-+#define MACH_ADM5120_BR6104K 41 /* Edimax BR-6104K */
-+#define MACH_ADM5120_BR6104KP 42 /* Edimax BR-6104KP */
-+#define MACH_ADM5120_BR61X4WG 43 /* Edimax BR-6104Wg/BR-6114WG */
-+#define MACH_ADM5120_PMUGW 44 /* Motorola Powerline MU Gateway */
-+
- #define CL_SIZE COMMAND_LINE_SIZE
-
- extern char *system_type;
+++ /dev/null
---- a/drivers/mtd/maps/Kconfig
-+++ b/drivers/mtd/maps/Kconfig
-@@ -586,5 +586,9 @@
-
- This selection automatically selects the map_ram driver.
-
-+config MTD_ADM5120
-+ tristate "Map driver for ADM5120 based boards"
-+ depends on ADM5120
-+
- endmenu
-
---- a/drivers/mtd/maps/Makefile
-+++ b/drivers/mtd/maps/Makefile
-@@ -44,6 +44,7 @@
- obj-$(CONFIG_MTD_SOLUTIONENGINE)+= solutionengine.o
- obj-$(CONFIG_MTD_PCI) += pci.o
- obj-$(CONFIG_MTD_ALCHEMY) += alchemy-flash.o
-+obj-$(CONFIG_MTD_ADM5120) += adm5120-flash.o
- obj-$(CONFIG_MTD_AUTCPU12) += autcpu12-nvram.o
- obj-$(CONFIG_MTD_EDB7312) += edb7312.o
- obj-$(CONFIG_MTD_IMPA7) += impa7.o
+++ /dev/null
---- a/drivers/net/Kconfig
-+++ b/drivers/net/Kconfig
-@@ -613,6 +613,10 @@
- If you have an Alchemy Semi AU1X00 based system
- say Y. Otherwise, say N.
-
-+config ADM5120_ENET
-+ tristate "ADM5120 Ethernet switch support"
-+ depends on ADM5120
-+
- config SGI_IOC3_ETH
- bool "SGI IOC3 Ethernet"
- depends on PCI && SGI_IP27
---- a/drivers/net/Makefile
-+++ b/drivers/net/Makefile
-@@ -186,6 +186,7 @@
- # This is also a 82596 and should probably be merged
- obj-$(CONFIG_LP486E) += lp486e.o
-
-+obj-$(CONFIG_ADM5120_ENET) += adm5120sw.o
- obj-$(CONFIG_ETH16I) += eth16i.o
- obj-$(CONFIG_ZORRO8390) += zorro8390.o
- obj-$(CONFIG_HPLANCE) += hplance.o 7990.o
+++ /dev/null
---- a/drivers/usb/host/Kconfig
-+++ b/drivers/usb/host/Kconfig
-@@ -4,6 +4,10 @@
- comment "USB Host Controller Drivers"
- depends on USB
-
-+config USB_ADM5120_HCD
-+ tristate "ADM5120 HCD support (EXPERIMENTAL)"
-+ depends on USB && ADM5120 && EXPERIMENTAL
-+
- config USB_C67X00_HCD
- tristate "Cypress C67x00 HCD support"
- depends on USB
---- a/drivers/usb/host/Makefile
-+++ b/drivers/usb/host/Makefile
-@@ -10,6 +10,7 @@
-
- obj-$(CONFIG_PCI) += pci-quirks.o
-
-+obj-$(CONFIG_USB_ADM5120_HCD) += adm5120-hcd.o
- obj-$(CONFIG_USB_EHCI_HCD) += ehci-hcd.o
- obj-$(CONFIG_USB_ISP116X_HCD) += isp116x-hcd.o
- obj-$(CONFIG_USB_OHCI_HCD) += ohci-hcd.o
---- a/drivers/usb/Makefile
-+++ b/drivers/usb/Makefile
-@@ -16,6 +16,7 @@
- obj-$(CONFIG_USB_SL811_HCD) += host/
- obj-$(CONFIG_USB_U132_HCD) += host/
- obj-$(CONFIG_USB_R8A66597_HCD) += host/
-+obj-$(CONFIG_USB_ADM5120_HCD) += host/
-
- obj-$(CONFIG_USB_C67X00_HCD) += c67x00/
-
+++ /dev/null
---- a/arch/mips/pci/Makefile
-+++ b/arch/mips/pci/Makefile
-@@ -48,3 +48,4 @@
- obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
- obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
- obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
-+obj-$(CONFIG_ADM5120) += pci-adm5120.o
---- a/include/linux/pci_ids.h
-+++ b/include/linux/pci_ids.h
-@@ -1707,6 +1707,9 @@
- #define PCI_VENDOR_ID_ESDGMBH 0x12fe
- #define PCI_DEVICE_ID_ESDGMBH_CPCIASIO4 0x0111
-
-+#define PCI_VENDOR_ID_ADMTEK 0x1317
-+#define PCI_DEVICE_ID_ADMTEK_ADM5120 0x5120
-+
- #define PCI_VENDOR_ID_SIIG 0x131f
- #define PCI_SUBVENDOR_ID_SIIG 0x131f
- #define PCI_DEVICE_ID_SIIG_1S_10x_550 0x1000
+++ /dev/null
---- a/drivers/leds/Kconfig
-+++ b/drivers/leds/Kconfig
-@@ -207,4 +207,12 @@
- This allows LEDs to be controlled by network device activity.
- If unsure, say Y.
-
-+config LEDS_TRIGGER_ADM5120_SWITCH
-+ tristate "LED ADM5120 Switch Port Status Trigger"
-+ depends on LEDS_TRIGGERS && ADM5120
-+ help
-+ This allows LEDs to be controlled by the port states of
-+ the ADM5120 built-in Ethernet Switch
-+ If unsure, say N.
-+
- endif # NEW_LEDS
---- a/drivers/leds/Makefile
-+++ b/drivers/leds/Makefile
-@@ -30,3 +30,4 @@
- obj-$(CONFIG_LEDS_TRIGGER_DEFAULT_ON) += ledtrig-default-on.o
- obj-$(CONFIG_LEDS_TRIGGER_MORSE) += ledtrig-morse.o
- obj-$(CONFIG_LEDS_TRIGGER_NETDEV) += ledtrig-netdev.o
-+obj-$(CONFIG_LEDS_TRIGGER_ADM5120_SWITCH) += ledtrig-adm5120-switch.o
+++ /dev/null
---- a/drivers/mtd/Kconfig
-+++ b/drivers/mtd/Kconfig
-@@ -174,6 +174,22 @@
- ---help---
- TI AR7 partitioning support
-
-+config MTD_MYLOADER_PARTS
-+ tristate "MyLoader partition parsing"
-+ depends on ADM5120 && MTD_PARTITIONS
-+ ---help---
-+ MyLoader is a bootloader which allows the user to define partitions
-+ in flash devices, by putting a table in the second erase block
-+ on the device, similar to a partition table. This table gives the
-+ offsets and lengths of the user defined partitions.
-+
-+ If you need code which can detect and parse these tables, and
-+ register MTD 'partitions' corresponding to each image detected,
-+ enable this option.
-+
-+ You will still need the parsing functions to be called by the driver
-+ for your particular device. It won't happen automatically.
-+
- comment "User Modules And Translation Layers"
-
- config MTD_CHAR
---- a/drivers/mtd/Makefile
-+++ b/drivers/mtd/Makefile
-@@ -13,6 +13,7 @@
- obj-$(CONFIG_MTD_AFS_PARTS) += afs.o
- obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o
- obj-$(CONFIG_MTD_OF_PARTS) += ofpart.o
-+obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o
-
- # 'Users' - code which presents functionality to userspace.
- obj-$(CONFIG_MTD_CHAR) += mtdchar.o
+++ /dev/null
---- a/drivers/mtd/chips/cfi_cmdset_0002.c
-+++ b/drivers/mtd/chips/cfi_cmdset_0002.c
-@@ -47,12 +47,19 @@
- #define MANUFACTURER_AMD 0x0001
- #define MANUFACTURER_ATMEL 0x001F
- #define MANUFACTURER_SST 0x00BF
-+#define MANUFACTURER_MACRONIX 0x00C2
- #define SST49LF004B 0x0060
- #define SST49LF040B 0x0050
- #define SST49LF008A 0x005a
- #define AT49BV6416 0x00d6
- #define MANUFACTURER_SAMSUNG 0x00ec
-
-+/* Macronix */
-+#define MX29LV160B 0x2249 /* MX29LV160 Bottom-boot chip */
-+#define MX29LV160T 0x22C4 /* MX29LV160 Top-boot chip */
-+#define MX29LV320B 0x22A8 /* MX29LV320 Bottom-boot chip */
-+#define MX29LV320T 0x22A7 /* MX29LV320 Top-boot chip */
-+
- static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
- static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
- static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
-@@ -243,6 +250,41 @@
- }
- }
-
-+#ifdef CONFIG_MTD_CFI_FIXUP_MACRONIX_BOOTLOC
-+/*
-+ * Some Macronix chips has no/bad bootblock information in the CFI table
-+ */
-+static void fixup_macronix_bootloc(struct mtd_info *mtd, void* param)
-+{
-+ struct map_info *map = mtd->priv;
-+ struct cfi_private *cfi = map->fldrv_priv;
-+ struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
-+ __u8 t;
-+
-+ switch (cfi->id) {
-+ /* TODO: put affected chip ids here */
-+ case MX29LV160B:
-+ case MX29LV320B:
-+ t = 2; /* Bottom boot */
-+ break;
-+ case MX29LV160T:
-+ case MX29LV320T:
-+ t = 3; /* Top boot */
-+ break;
-+ default:
-+ return;
-+ }
-+
-+ if (extp->TopBottom == t)
-+ /* boot location detected by the CFI layer is correct */
-+ return;
-+
-+ extp->TopBottom = t;
-+ printk("%s: Macronix chip detected, id:0x%04X, boot location forced "
-+ "to %s\n", map->name, cfi->id, (t == 2) ? "bottom" : "top");
-+}
-+#endif /* CONFIG_MTD_CFI_FIXUP_MACRONIX_BOOTLOC */
-+
- static struct cfi_fixup cfi_fixup_table[] = {
- { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri, NULL },
- #ifdef AMD_BOOTLOC_BUG
-@@ -278,6 +320,9 @@
- */
- { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_erase_chip, NULL },
- { CFI_MFR_ATMEL, AT49BV6416, fixup_use_atmel_lock, NULL },
-+#ifdef CONFIG_MTD_CFI_FIXUP_MACRONIX_BOOTLOC
-+ { MANUFACTURER_MACRONIX, CFI_ID_ANY, fixup_macronix_bootloc, NULL, },
-+#endif
- { 0, 0, NULL, NULL }
- };
-
---- a/drivers/mtd/chips/Kconfig
-+++ b/drivers/mtd/chips/Kconfig
-@@ -196,6 +196,14 @@
- provides support for one of those command sets, used on chips
- including the AMD Am29LV320.
-
-+config MTD_CFI_FIXUP_MACRONIX_BOOTLOC
-+ bool "Fix boot-block location for Macronix flash chips"
-+ depends on MTD_CFI_AMDSTD
-+ help
-+ Some Macronix flash chips have no/wrong boot-block location in the
-+ CFI table, and the driver may detect the type incorrectly. Select
-+ this if your board has such chip.
-+
- config MTD_CFI_STAA
- tristate "Support for ST (Advanced Architecture) flash chips"
- depends on MTD_GEN_PROBE
+++ /dev/null
---- a/drivers/mtd/chips/jedec_probe.c
-+++ b/drivers/mtd/chips/jedec_probe.c
-@@ -121,6 +121,10 @@
- #define UPD29F064115 0x221C
-
- /* PMC */
-+#define PM39LV512 0x001B
-+#define PM39LV010 0x001C
-+#define PM39LV020 0x003D
-+#define PM39LV040 0x003E
- #define PM49FL002 0x006D
- #define PM49FL004 0x006E
- #define PM49FL008 0x006A
-@@ -1173,6 +1177,54 @@
- ERASEINFO(0x02000,2),
- ERASEINFO(0x04000,1),
- }
-+ }, {
-+ .mfr_id = MANUFACTURER_PMC,
-+ .dev_id = PM39LV512,
-+ .name = "PMC Pm39LV512",
-+ .devtypes = CFI_DEVICETYPE_X8,
-+ .uaddr = MTD_UADDR_0x0555_0x02AA,
-+ .dev_size = SIZE_64KiB,
-+ .cmd_set = P_ID_AMD_STD,
-+ .nr_regions = 1,
-+ .regions = {
-+ ERASEINFO(0x01000,16),
-+ }
-+ }, {
-+ .mfr_id = MANUFACTURER_PMC,
-+ .dev_id = PM39LV010,
-+ .name = "PMC Pm39LV010",
-+ .devtypes = CFI_DEVICETYPE_X8,
-+ .uaddr = MTD_UADDR_0x0555_0x02AA,
-+ .dev_size = SIZE_128KiB,
-+ .cmd_set = P_ID_AMD_STD,
-+ .nr_regions = 1,
-+ .regions = {
-+ ERASEINFO(0x01000,32),
-+ }
-+ }, {
-+ .mfr_id = MANUFACTURER_PMC,
-+ .dev_id = PM39LV020,
-+ .name = "PMC Pm39LV020",
-+ .devtypes = CFI_DEVICETYPE_X8,
-+ .uaddr = MTD_UADDR_0x0555_0x02AA,
-+ .dev_size = SIZE_256KiB,
-+ .cmd_set = P_ID_AMD_STD,
-+ .nr_regions = 1,
-+ .regions = {
-+ ERASEINFO(0x01000,64),
-+ }
-+ }, {
-+ .mfr_id = MANUFACTURER_PMC,
-+ .dev_id = PM39LV040,
-+ .name = "PMC Pm39LV040",
-+ .devtypes = CFI_DEVICETYPE_X8,
-+ .uaddr = MTD_UADDR_0x0555_0x02AA,
-+ .dev_size = SIZE_512KiB,
-+ .cmd_set = P_ID_AMD_STD,
-+ .nr_regions = 1,
-+ .regions = {
-+ ERASEINFO(0x01000,128),
-+ }
- }, {
- .mfr_id = MANUFACTURER_PMC,
- .dev_id = PM49FL002,
+++ /dev/null
---- a/drivers/mtd/Kconfig
-+++ b/drivers/mtd/Kconfig
-@@ -57,6 +57,11 @@
- depends on MTD_PARTITIONS
- default y
-
-+config MTD_TRXSPLIT
-+ bool "Automatically find and split TRX partitions"
-+ depends on MTD_PARTITIONS
-+ default n
-+
- config MTD_REDBOOT_PARTS
- tristate "RedBoot partition table parsing"
- depends on MTD_PARTITIONS
---- a/drivers/mtd/Makefile
-+++ b/drivers/mtd/Makefile
-@@ -8,6 +8,7 @@
- mtd-$(CONFIG_MTD_PARTITIONS) += mtdpart.o
-
- obj-$(CONFIG_MTD_CONCAT) += mtdconcat.o
-+obj-$(CONFIG_MTD_TRXSPLIT) += trxsplit.o
- obj-$(CONFIG_MTD_REDBOOT_PARTS) += redboot.o
- obj-$(CONFIG_MTD_CMDLINE_PARTS) += cmdlinepart.o
- obj-$(CONFIG_MTD_AFS_PARTS) += afs.o
+++ /dev/null
---- a/drivers/ata/Makefile
-+++ b/drivers/ata/Makefile
-@@ -72,6 +72,7 @@
- obj-$(CONFIG_PATA_PLATFORM) += pata_platform.o
- obj-$(CONFIG_PATA_OF_PLATFORM) += pata_of_platform.o
- obj-$(CONFIG_PATA_ICSIDE) += pata_icside.o
-+obj-$(CONFIG_PATA_RB153_CF) += pata_rb153_cf.o
- # Should be last but two libata driver
- obj-$(CONFIG_PATA_ACPI) += pata_acpi.o
- # Should be last but one libata driver
---- a/drivers/ata/Kconfig
-+++ b/drivers/ata/Kconfig
-@@ -566,6 +566,15 @@
-
- If unsure, say N.
-
-+config PATA_RB153_CF
-+ tristate "RouterBOARD 153 Compact Flash support"
-+ depends on ADM5120_MACH_RB_153
-+ help
-+ This option enables support for a Compact Flash connected on
-+ the RouterBOARD 153.
-+
-+ If unsure, say N.
-+
- config PATA_RB532
- tristate "RouterBoard 532 PATA CompactFlash support"
- depends on MIKROTIK_RB532
+++ /dev/null
---- a/arch/mips/kernel/head.S
-+++ b/arch/mips/kernel/head.S
-@@ -126,7 +126,12 @@
- /*
- * Reserved space for exception handlers.
- * Necessary for machines which link their kernels at KSEG0.
-+ * Use as temporary storage for the kernel command line, so that it
-+ * can be updated easily without having to relink the kernel.
- */
-+
-+EXPORT(_image_cmdline)
-+ .ascii "CMDLINE:"
- .fill 0x400
- #endif
-
+++ /dev/null
---- a/drivers/serial/amba-pl010.c
-+++ b/drivers/serial/amba-pl010.c
-@@ -52,11 +52,10 @@
-
- #include <asm/io.h>
-
--#define UART_NR 8
--
- #define SERIAL_AMBA_MAJOR 204
- #define SERIAL_AMBA_MINOR 16
--#define SERIAL_AMBA_NR UART_NR
-+#define SERIAL_AMBA_NR CONFIG_SERIAL_AMBA_PL010_NUMPORTS
-+#define SERIAL_AMBA_NAME CONFIG_SERIAL_AMBA_PL010_PORTNAME
-
- #define AMBA_ISR_PASS_LIMIT 256
-
-@@ -82,9 +81,9 @@
- struct uart_amba_port *uap = (struct uart_amba_port *)port;
- unsigned int cr;
-
-- cr = readb(uap->port.membase + UART010_CR);
-+ cr = __raw_readl(uap->port.membase + UART010_CR);
- cr &= ~UART010_CR_TIE;
-- writel(cr, uap->port.membase + UART010_CR);
-+ __raw_writel(cr, uap->port.membase + UART010_CR);
- }
-
- static void pl010_start_tx(struct uart_port *port)
-@@ -92,9 +91,9 @@
- struct uart_amba_port *uap = (struct uart_amba_port *)port;
- unsigned int cr;
-
-- cr = readb(uap->port.membase + UART010_CR);
-+ cr = __raw_readl(uap->port.membase + UART010_CR);
- cr |= UART010_CR_TIE;
-- writel(cr, uap->port.membase + UART010_CR);
-+ __raw_writel(cr, uap->port.membase + UART010_CR);
- }
-
- static void pl010_stop_rx(struct uart_port *port)
-@@ -102,9 +101,9 @@
- struct uart_amba_port *uap = (struct uart_amba_port *)port;
- unsigned int cr;
-
-- cr = readb(uap->port.membase + UART010_CR);
-+ cr = __raw_readl(uap->port.membase + UART010_CR);
- cr &= ~(UART010_CR_RIE | UART010_CR_RTIE);
-- writel(cr, uap->port.membase + UART010_CR);
-+ __raw_writel(cr, uap->port.membase + UART010_CR);
- }
-
- static void pl010_enable_ms(struct uart_port *port)
-@@ -112,9 +111,9 @@
- struct uart_amba_port *uap = (struct uart_amba_port *)port;
- unsigned int cr;
-
-- cr = readb(uap->port.membase + UART010_CR);
-+ cr = __raw_readl(uap->port.membase + UART010_CR);
- cr |= UART010_CR_MSIE;
-- writel(cr, uap->port.membase + UART010_CR);
-+ __raw_writel(cr, uap->port.membase + UART010_CR);
- }
-
- static void pl010_rx_chars(struct uart_amba_port *uap)
-@@ -122,9 +121,9 @@
- struct tty_struct *tty = uap->port.info->tty;
- unsigned int status, ch, flag, rsr, max_count = 256;
-
-- status = readb(uap->port.membase + UART01x_FR);
-+ status = __raw_readl(uap->port.membase + UART01x_FR);
- while (UART_RX_DATA(status) && max_count--) {
-- ch = readb(uap->port.membase + UART01x_DR);
-+ ch = __raw_readl(uap->port.membase + UART01x_DR);
- flag = TTY_NORMAL;
-
- uap->port.icount.rx++;
-@@ -133,9 +132,9 @@
- * Note that the error handling code is
- * out of the main execution path
- */
-- rsr = readb(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX;
-+ rsr = __raw_readl(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX;
- if (unlikely(rsr & UART01x_RSR_ANY)) {
-- writel(0, uap->port.membase + UART01x_ECR);
-+ __raw_writel(0, uap->port.membase + UART01x_ECR);
-
- if (rsr & UART01x_RSR_BE) {
- rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE);
-@@ -165,7 +164,7 @@
- uart_insert_char(&uap->port, rsr, UART01x_RSR_OE, ch, flag);
-
- ignore_char:
-- status = readb(uap->port.membase + UART01x_FR);
-+ status = __raw_readl(uap->port.membase + UART01x_FR);
- }
- spin_unlock(&uap->port.lock);
- tty_flip_buffer_push(tty);
-@@ -178,7 +177,7 @@
- int count;
-
- if (uap->port.x_char) {
-- writel(uap->port.x_char, uap->port.membase + UART01x_DR);
-+ __raw_writel(uap->port.x_char, uap->port.membase + UART01x_DR);
- uap->port.icount.tx++;
- uap->port.x_char = 0;
- return;
-@@ -190,7 +189,7 @@
-
- count = uap->port.fifosize >> 1;
- do {
-- writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
-+ __raw_writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
- xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
- uap->port.icount.tx++;
- if (uart_circ_empty(xmit))
-@@ -208,9 +207,9 @@
- {
- unsigned int status, delta;
-
-- writel(0, uap->port.membase + UART010_ICR);
-+ __raw_writel(0, uap->port.membase + UART010_ICR);
-
-- status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
-+ status = __raw_readl(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
-
- delta = status ^ uap->old_status;
- uap->old_status = status;
-@@ -238,7 +237,7 @@
-
- spin_lock(&uap->port.lock);
-
-- status = readb(uap->port.membase + UART010_IIR);
-+ status = __raw_readl(uap->port.membase + UART010_IIR);
- if (status) {
- do {
- if (status & (UART010_IIR_RTIS | UART010_IIR_RIS))
-@@ -251,7 +250,7 @@
- if (pass_counter-- == 0)
- break;
-
-- status = readb(uap->port.membase + UART010_IIR);
-+ status = __raw_readl(uap->port.membase + UART010_IIR);
- } while (status & (UART010_IIR_RTIS | UART010_IIR_RIS |
- UART010_IIR_TIS));
- handled = 1;
-@@ -265,7 +264,7 @@
- static unsigned int pl010_tx_empty(struct uart_port *port)
- {
- struct uart_amba_port *uap = (struct uart_amba_port *)port;
-- unsigned int status = readb(uap->port.membase + UART01x_FR);
-+ unsigned int status = __raw_readl(uap->port.membase + UART01x_FR);
- return status & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT;
- }
-
-@@ -275,7 +274,7 @@
- unsigned int result = 0;
- unsigned int status;
-
-- status = readb(uap->port.membase + UART01x_FR);
-+ status = __raw_readl(uap->port.membase + UART01x_FR);
- if (status & UART01x_FR_DCD)
- result |= TIOCM_CAR;
- if (status & UART01x_FR_DSR)
-@@ -301,12 +300,12 @@
- unsigned int lcr_h;
-
- spin_lock_irqsave(&uap->port.lock, flags);
-- lcr_h = readb(uap->port.membase + UART010_LCRH);
-+ lcr_h = __raw_readl(uap->port.membase + UART010_LCRH);
- if (break_state == -1)
- lcr_h |= UART01x_LCRH_BRK;
- else
- lcr_h &= ~UART01x_LCRH_BRK;
-- writel(lcr_h, uap->port.membase + UART010_LCRH);
-+ __raw_writel(lcr_h, uap->port.membase + UART010_LCRH);
- spin_unlock_irqrestore(&uap->port.lock, flags);
- }
-
-@@ -334,12 +333,12 @@
- /*
- * initialise the old status of the modem signals
- */
-- uap->old_status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
-+ uap->old_status = __raw_readl(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
-
- /*
- * Finally, enable interrupts
- */
-- writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE,
-+ __raw_writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE,
- uap->port.membase + UART010_CR);
-
- return 0;
-@@ -362,10 +361,10 @@
- /*
- * disable all interrupts, disable the port
- */
-- writel(0, uap->port.membase + UART010_CR);
-+ __raw_writel(0, uap->port.membase + UART010_CR);
-
- /* disable break condition and fifos */
-- writel(readb(uap->port.membase + UART010_LCRH) &
-+ __raw_writel(__raw_readl(uap->port.membase + UART010_LCRH) &
- ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN),
- uap->port.membase + UART010_LCRH);
-
-@@ -387,7 +386,7 @@
- /*
- * Ask the core to calculate the divisor for us.
- */
-- baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16);
-+ baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16);
- quot = uart_get_divisor(port, baud);
-
- switch (termios->c_cflag & CSIZE) {
-@@ -450,25 +449,25 @@
- uap->port.ignore_status_mask |= UART_DUMMY_RSR_RX;
-
- /* first, disable everything */
-- old_cr = readb(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE;
-+ old_cr = __raw_readl(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE;
-
- if (UART_ENABLE_MS(port, termios->c_cflag))
- old_cr |= UART010_CR_MSIE;
-
-- writel(0, uap->port.membase + UART010_CR);
-+ __raw_writel(0, uap->port.membase + UART010_CR);
-
- /* Set baud rate */
- quot -= 1;
-- writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM);
-- writel(quot & 0xff, uap->port.membase + UART010_LCRL);
-+ __raw_writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM);
-+ __raw_writel(quot & 0xff, uap->port.membase + UART010_LCRL);
-
- /*
- * ----------v----------v----------v----------v-----
- * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
- * ----------^----------^----------^----------^-----
- */
-- writel(lcr_h, uap->port.membase + UART010_LCRH);
-- writel(old_cr, uap->port.membase + UART010_CR);
-+ __raw_writel(lcr_h, uap->port.membase + UART010_LCRH);
-+ __raw_writel(old_cr, uap->port.membase + UART010_CR);
-
- spin_unlock_irqrestore(&uap->port.lock, flags);
- }
-@@ -540,7 +539,7 @@
- .verify_port = pl010_verify_port,
- };
-
--static struct uart_amba_port *amba_ports[UART_NR];
-+static struct uart_amba_port *amba_ports[SERIAL_AMBA_NR];
-
- #ifdef CONFIG_SERIAL_AMBA_PL010_CONSOLE
-
-@@ -550,10 +549,10 @@
- unsigned int status;
-
- do {
-- status = readb(uap->port.membase + UART01x_FR);
-+ status = __raw_readl(uap->port.membase + UART01x_FR);
- barrier();
- } while (!UART_TX_READY(status));
-- writel(ch, uap->port.membase + UART01x_DR);
-+ __raw_writel(ch, uap->port.membase + UART01x_DR);
- }
-
- static void
-@@ -567,8 +566,8 @@
- /*
- * First save the CR then disable the interrupts
- */
-- old_cr = readb(uap->port.membase + UART010_CR);
-- writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR);
-+ old_cr = __raw_readl(uap->port.membase + UART010_CR);
-+ __raw_writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR);
-
- uart_console_write(&uap->port, s, count, pl010_console_putchar);
-
-@@ -577,10 +576,10 @@
- * and restore the TCR
- */
- do {
-- status = readb(uap->port.membase + UART01x_FR);
-+ status = __raw_readl(uap->port.membase + UART01x_FR);
- barrier();
- } while (status & UART01x_FR_BUSY);
-- writel(old_cr, uap->port.membase + UART010_CR);
-+ __raw_writel(old_cr, uap->port.membase + UART010_CR);
-
- clk_disable(uap->clk);
- }
-@@ -589,9 +588,9 @@
- pl010_console_get_options(struct uart_amba_port *uap, int *baud,
- int *parity, int *bits)
- {
-- if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) {
-+ if (__raw_readl(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) {
- unsigned int lcr_h, quot;
-- lcr_h = readb(uap->port.membase + UART010_LCRH);
-+ lcr_h = __raw_readl(uap->port.membase + UART010_LCRH);
-
- *parity = 'n';
- if (lcr_h & UART01x_LCRH_PEN) {
-@@ -606,8 +605,8 @@
- else
- *bits = 8;
-
-- quot = readb(uap->port.membase + UART010_LCRL) |
-- readb(uap->port.membase + UART010_LCRM) << 8;
-+ quot = __raw_readl(uap->port.membase + UART010_LCRL) |
-+ __raw_readl(uap->port.membase + UART010_LCRM) << 8;
- *baud = uap->port.uartclk / (16 * (quot + 1));
- }
- }
-@@ -625,7 +624,7 @@
- * if so, search for the first available port that does have
- * console support.
- */
-- if (co->index >= UART_NR)
-+ if (co->index >= SERIAL_AMBA_NR)
- co->index = 0;
- uap = amba_ports[co->index];
- if (!uap)
-@@ -643,7 +642,7 @@
-
- static struct uart_driver amba_reg;
- static struct console amba_console = {
-- .name = "ttyAM",
-+ .name = SERIAL_AMBA_NAME,
- .write = pl010_console_write,
- .device = uart_console_device,
- .setup = pl010_console_setup,
-@@ -659,11 +658,11 @@
-
- static struct uart_driver amba_reg = {
- .owner = THIS_MODULE,
-- .driver_name = "ttyAM",
-- .dev_name = "ttyAM",
-+ .driver_name = SERIAL_AMBA_NAME,
-+ .dev_name = SERIAL_AMBA_NAME,
- .major = SERIAL_AMBA_MAJOR,
- .minor = SERIAL_AMBA_MINOR,
-- .nr = UART_NR,
-+ .nr = SERIAL_AMBA_NR,
- .cons = AMBA_CONSOLE,
- };
-
---- a/drivers/serial/Kconfig
-+++ b/drivers/serial/Kconfig
-@@ -287,10 +287,25 @@
- help
- This selects the ARM(R) AMBA(R) PrimeCell PL010 UART. If you have
- an Integrator/AP or Integrator/PP2 platform, or if you have a
-- Cirrus Logic EP93xx CPU, say Y or M here.
-+ Cirrus Logic EP93xx CPU or an Infineon ADM5120 SOC, say Y or M here.
-
- If unsure, say N.
-
-+config SERIAL_AMBA_PL010_NUMPORTS
-+ int "Maximum number of AMBA PL010 serial ports"
-+ depends on SERIAL_AMBA_PL010
-+ default "8"
-+ ---help---
-+ Set this to the number of serial ports you want the AMBA PL010 driver
-+ to support.
-+
-+config SERIAL_AMBA_PL010_PORTNAME
-+ string "Name of the AMBA PL010 serial ports"
-+ depends on SERIAL_AMBA_PL010
-+ default "ttyAM"
-+ ---help---
-+ ::: To be written :::
-+
- config SERIAL_AMBA_PL010_CONSOLE
- bool "Support for console on AMBA serial port"
- depends on SERIAL_AMBA_PL010=y
+++ /dev/null
---- a/drivers/amba/bus.c
-+++ b/drivers/amba/bus.c
-@@ -17,6 +17,10 @@
- #include <asm/io.h>
- #include <asm/sizes.h>
-
-+#ifndef NO_IRQ
-+#define NO_IRQ (-1)
-+#endif
-+
- #define to_amba_device(d) container_of(d, struct amba_device, dev)
- #define to_amba_driver(d) container_of(d, struct amba_driver, drv)
-
+++ /dev/null
---- a/drivers/pci/Kconfig
-+++ b/drivers/pci/Kconfig
-@@ -42,6 +42,12 @@
-
- When in doubt, say N.
-
-+config PCI_DISABLE_COMMON_QUIRKS
-+ bool "PCI disable common quirks"
-+ depends on PCI
-+ help
-+ If you don't know what to do here, say N.
-+
- config HT_IRQ
- bool "Interrupts on hypertransport devices"
- default y
---- a/drivers/pci/quirks.c
-+++ b/drivers/pci/quirks.c
-@@ -24,6 +24,7 @@
- #include <linux/kallsyms.h>
- #include "pci.h"
-
-+#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS
- /* The Mellanox Tavor device gives false positive parity errors
- * Mark this device with a broken_parity_status, to allow
- * PCI scanning code to "skip" this now blacklisted device.
-@@ -1495,6 +1496,7 @@
- }
- }
- DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
-+#endif /* !CONFIG_PCI_DISABLE_COMMON_QUIRKS */
-
- static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end)
- {
-@@ -1561,6 +1563,7 @@
- }
- EXPORT_SYMBOL(pci_fixup_device);
-
-+#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS
- /* Enable 1k I/O space granularity on the Intel P64H2 */
- static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
- {
-@@ -1934,3 +1937,4 @@
- quirk_msi_intx_disable_bug);
-
- #endif /* CONFIG_PCI_MSI */
-+#endif /* !CONFIG_PCI_DISABLE_COMMON_QUIRKS */
+++ /dev/null
---- a/drivers/leds/leds-gpio.c
-+++ b/drivers/leds/leds-gpio.c
-@@ -43,13 +43,17 @@
- container_of(led_cdev, struct gpio_led_data, cdev);
- int level;
-
-- if (value == LED_OFF)
-- level = 0;
-- else
-- level = 1;
--
-- if (led_dat->active_low)
-- level = !level;
-+ switch (value) {
-+ case LED_OFF:
-+ level = led_dat->active_low ? 1 : 0;
-+ break;
-+ case LED_FULL:
-+ level = led_dat->active_low ? 0 : 1;
-+ break;
-+ default:
-+ level = value;
-+ break;
-+ }
-
- /* Setting GPIOs with I2C/etc requires a task context, and we don't
- * seem to have a reliable way to know if we're already in one; so
+++ /dev/null
---- a/drivers/watchdog/Kconfig
-+++ b/drivers/watchdog/Kconfig
-@@ -632,6 +632,18 @@
-
- # MIPS Architecture
-
-+config ADM5120_WDT
-+ tristate "Infineon ADM5120 SoC hardware watchdog"
-+ depends on WATCHDOG && ADM5120
-+ help
-+ This is a driver for hardware watchdog integrated in Infineon
-+ ADM5120 SoC. This watchdog simply watches your kernel to make sure
-+ it doesn't freeze, and if it does, it reboots your computer after a
-+ certain amount of time.
-+
-+ To compile this driver as a module, choose M here: the module will be
-+ called adm5120_wdt.
-+
- config INDYDOG
- tristate "Indy/I2 Hardware Watchdog"
- depends on SGI_HAS_INDYDOG
---- a/drivers/watchdog/Makefile
-+++ b/drivers/watchdog/Makefile
-@@ -91,6 +91,7 @@
- # M68KNOMMU Architecture
-
- # MIPS Architecture
-+obj-$(CONFIG_ADM5120_WDT) += adm5120_wdt.o
- obj-$(CONFIG_INDYDOG) += indydog.o
- obj-$(CONFIG_WDT_MTX1) += mtx-1_wdt.o
- obj-$(CONFIG_WDT_RM9K_GPI) += rm9k_wdt.o
--- /dev/null
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -18,6 +18,21 @@
+ prompt "System type"
+ default SGI_IP22
+
++config ADM5120
++ bool "Infineon/ADMtek ADM5120 SoC based machines"
++ select CEVT_R4K
++ select CSRC_R4K
++ select SYS_HAS_CPU_MIPS32_R1
++ select SYS_HAS_EARLY_PRINTK
++ select DMA_NONCOHERENT
++ select IRQ_CPU
++ select SYS_SUPPORTS_LITTLE_ENDIAN
++ select SYS_SUPPORTS_BIG_ENDIAN
++ select SYS_SUPPORTS_32BIT_KERNEL
++ select GENERIC_GPIO
++ select HAVE_GPIO_LIB
++ select SWAP_IO_SPACE if CPU_BIG_ENDIAN
++
+ config MACH_ALCHEMY
+ bool "Alchemy processor based machines"
+
+@@ -687,6 +702,7 @@
+
+ endchoice
+
++source "arch/mips/adm5120/Kconfig"
+ source "arch/mips/au1000/Kconfig"
+ source "arch/mips/basler/excite/Kconfig"
+ source "arch/mips/jazz/Kconfig"
+--- a/arch/mips/Makefile
++++ b/arch/mips/Makefile
+@@ -174,6 +174,21 @@
+ load-$(CONFIG_MACH_JAZZ) += 0xffffffff80080000
+
+ #
++# Infineon/ADMtek ADM5120
++#
++libs-$(CONFIG_ADM5120) += arch/mips/adm5120/prom/
++core-$(CONFIG_ADM5120) += arch/mips/adm5120/common/
++core-$(CONFIG_ADM5120_OEM_CELLVISION) += arch/mips/adm5120/cellvision/
++core-$(CONFIG_ADM5120_OEM_COMPEX) += arch/mips/adm5120/compex/
++core-$(CONFIG_ADM5120_OEM_EDIMAX) += arch/mips/adm5120/edimax/
++core-$(CONFIG_ADM5120_OEM_INFINEON) += arch/mips/adm5120/infineon/
++core-$(CONFIG_ADM5120_OEM_MIKROTIK) += arch/mips/adm5120/mikrotik/
++core-$(CONFIG_ADM5120_OEM_MOTOROLA) += arch/mips/adm5120/motorola/
++core-$(CONFIG_ADM5120_OEM_ZYXEL) += arch/mips/adm5120/zyxel/
++cflags-$(CONFIG_ADM5120) += -Iinclude/asm-mips/mach-adm5120
++load-$(CONFIG_ADM5120) += 0xffffffff80001000
++
++#
+ # Common Alchemy Au1x00 stuff
+ #
+ core-$(CONFIG_SOC_AU1X00) += arch/mips/au1000/common/
+--- a/include/asm-mips/bootinfo.h
++++ b/include/asm-mips/bootinfo.h
+@@ -94,6 +94,55 @@
+ #define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */
+ #define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */
+
++/*
++ * Valid machtype for group ADM5120
++ */
++#define MACH_ADM5120_GENERIC 0 /* Generic board */
++#define MACH_ADM5120_WP54G_WRT 1 /* Compex WP54G-WRT */
++#define MACH_ADM5120_WP54 2 /* Compex WP54G/WP54AG/WPP54G/WPP54AG */
++#define MACH_ADM5120_NP28G 3 /* Compex NP28G */
++#define MACH_ADM5120_NP28GHS 4 /* Compex NP28G HotSpot */
++#define MACH_ADM5120_NP27G 5 /* Compex NP27G */
++#define MACH_ADM5120_WP54Gv1C 6 /* Compex WP54G version 1C */
++#define MACH_ADM5120_RB_11X 7 /* Mikrotik RouterBOARD 111/112 */
++#define MACH_ADM5120_RB_133 8 /* Mikrotik RouterBOARD 133 */
++#define MACH_ADM5120_RB_133C 9 /* Mikrotik RouterBOARD 133c */
++#define MACH_ADM5120_RB_150 10 /* Mikrotik RouterBOARD 150 */
++#define MACH_ADM5120_RB_153 11 /* Mikrotik RouterBOARD 153 */
++#define MACH_ADM5120_RB_192 12 /* Mikrotik RouterBOARD 192 */
++#define MACH_ADM5120_HS100 13 /* ZyXEL HomeSafe 100/100W */
++#define MACH_ADM5120_P334U 14 /* ZyXEL Prestige 334U */
++#define MACH_ADM5120_P334W 15 /* ZyXEL Prestige 334W */
++#define MACH_ADM5120_P334WH 16 /* ZyXEL Prestige 334WH */
++#define MACH_ADM5120_P334WHD 17 /* ZyXEL Prestige 334WHD */
++#define MACH_ADM5120_P334WT 18 /* ZyXEL Prestige 334WT */
++#define MACH_ADM5120_P335 19 /* ZyXEL Prestige 335/335WT */
++#define MACH_ADM5120_P335PLUS 20 /* ZyXEL Prestige 335Plus */
++#define MACH_ADM5120_P335U 21 /* ZyXEL Prestige 335U */
++#define MACH_ADM5120_ES2108 22 /* ZyXEL Ethernet Switch 2108 */
++#define MACH_ADM5120_ES2108F 23 /* ZyXEL Ethernet Switch 2108-F */
++#define MACH_ADM5120_ES2108G 24 /* ZyXEL Ethernet Switch 2108-G */
++#define MACH_ADM5120_ES2108LC 25 /* ZyXEL Ethernet Switch 2108-LC */
++#define MACH_ADM5120_ES2108PWR 26 /* ZyXEL Ethernet Switch 2108-PWR */
++#define MACH_ADM5120_ES2024A 27 /* ZyXEL Ethernet Switch 2024A */
++#define MACH_ADM5120_ES2024PWR 28 /* ZyXEL Ethernet Switch 2024PWR */
++#define MACH_ADM5120_CAS630 29 /* Cellvision CAS-630/630W */
++#define MACH_ADM5120_CAS670 30 /* Cellvision CAS-670/670W */
++#define MACH_ADM5120_CAS700 31 /* Cellvision CAS-700/700W */
++#define MACH_ADM5120_CAS771 32 /* Cellvision CAS-771/771W */
++#define MACH_ADM5120_CAS790 33 /* Cellvision CAS-790 */
++#define MACH_ADM5120_CAS861 34 /* Cellvision CAS-861/861W */
++#define MACH_ADM5120_NFS101U 35 /* Cellvision NFS-101U/101WU */
++#define MACH_ADM5120_NFS202U 36 /* Cellvision NFS-202U/202WU */
++#define MACH_ADM5120_EASY5120PATA 37 /* Infineon EASY 5120P-ATA */
++#define MACH_ADM5120_EASY5120RT 38 /* Infineon EASY 5120-RT */
++#define MACH_ADM5120_EASY5120WVOIP 39 /* Infineon EASY 5120-WVoIP */
++#define MACH_ADM5120_EASY83000 40 /* Infineon EASY-83000 */
++#define MACH_ADM5120_BR6104K 41 /* Edimax BR-6104K */
++#define MACH_ADM5120_BR6104KP 42 /* Edimax BR-6104KP */
++#define MACH_ADM5120_BR61X4WG 43 /* Edimax BR-6104Wg/BR-6114WG */
++#define MACH_ADM5120_PMUGW 44 /* Motorola Powerline MU Gateway */
++
+ #define CL_SIZE COMMAND_LINE_SIZE
+
+ extern char *system_type;
--- /dev/null
+--- a/drivers/mtd/maps/Kconfig
++++ b/drivers/mtd/maps/Kconfig
+@@ -586,5 +586,9 @@
+
+ This selection automatically selects the map_ram driver.
+
++config MTD_ADM5120
++ tristate "Map driver for ADM5120 based boards"
++ depends on ADM5120
++
+ endmenu
+
+--- a/drivers/mtd/maps/Makefile
++++ b/drivers/mtd/maps/Makefile
+@@ -44,6 +44,7 @@
+ obj-$(CONFIG_MTD_SOLUTIONENGINE)+= solutionengine.o
+ obj-$(CONFIG_MTD_PCI) += pci.o
+ obj-$(CONFIG_MTD_ALCHEMY) += alchemy-flash.o
++obj-$(CONFIG_MTD_ADM5120) += adm5120-flash.o
+ obj-$(CONFIG_MTD_AUTCPU12) += autcpu12-nvram.o
+ obj-$(CONFIG_MTD_EDB7312) += edb7312.o
+ obj-$(CONFIG_MTD_IMPA7) += impa7.o
--- /dev/null
+--- a/drivers/net/Kconfig
++++ b/drivers/net/Kconfig
+@@ -613,6 +613,10 @@
+ If you have an Alchemy Semi AU1X00 based system
+ say Y. Otherwise, say N.
+
++config ADM5120_ENET
++ tristate "ADM5120 Ethernet switch support"
++ depends on ADM5120
++
+ config SGI_IOC3_ETH
+ bool "SGI IOC3 Ethernet"
+ depends on PCI && SGI_IP27
+--- a/drivers/net/Makefile
++++ b/drivers/net/Makefile
+@@ -186,6 +186,7 @@
+ # This is also a 82596 and should probably be merged
+ obj-$(CONFIG_LP486E) += lp486e.o
+
++obj-$(CONFIG_ADM5120_ENET) += adm5120sw.o
+ obj-$(CONFIG_ETH16I) += eth16i.o
+ obj-$(CONFIG_ZORRO8390) += zorro8390.o
+ obj-$(CONFIG_HPLANCE) += hplance.o 7990.o
--- /dev/null
+--- a/drivers/usb/host/Kconfig
++++ b/drivers/usb/host/Kconfig
+@@ -4,6 +4,10 @@
+ comment "USB Host Controller Drivers"
+ depends on USB
+
++config USB_ADM5120_HCD
++ tristate "ADM5120 HCD support (EXPERIMENTAL)"
++ depends on USB && ADM5120 && EXPERIMENTAL
++
+ config USB_C67X00_HCD
+ tristate "Cypress C67x00 HCD support"
+ depends on USB
+--- a/drivers/usb/host/Makefile
++++ b/drivers/usb/host/Makefile
+@@ -10,6 +10,7 @@
+
+ obj-$(CONFIG_PCI) += pci-quirks.o
+
++obj-$(CONFIG_USB_ADM5120_HCD) += adm5120-hcd.o
+ obj-$(CONFIG_USB_EHCI_HCD) += ehci-hcd.o
+ obj-$(CONFIG_USB_ISP116X_HCD) += isp116x-hcd.o
+ obj-$(CONFIG_USB_OHCI_HCD) += ohci-hcd.o
+--- a/drivers/usb/Makefile
++++ b/drivers/usb/Makefile
+@@ -16,6 +16,7 @@
+ obj-$(CONFIG_USB_SL811_HCD) += host/
+ obj-$(CONFIG_USB_U132_HCD) += host/
+ obj-$(CONFIG_USB_R8A66597_HCD) += host/
++obj-$(CONFIG_USB_ADM5120_HCD) += host/
+
+ obj-$(CONFIG_USB_C67X00_HCD) += c67x00/
+
--- /dev/null
+--- a/arch/mips/pci/Makefile
++++ b/arch/mips/pci/Makefile
+@@ -48,3 +48,4 @@
+ obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
+ obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
+ obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
++obj-$(CONFIG_ADM5120) += pci-adm5120.o
+--- a/include/linux/pci_ids.h
++++ b/include/linux/pci_ids.h
+@@ -1707,6 +1707,9 @@
+ #define PCI_VENDOR_ID_ESDGMBH 0x12fe
+ #define PCI_DEVICE_ID_ESDGMBH_CPCIASIO4 0x0111
+
++#define PCI_VENDOR_ID_ADMTEK 0x1317
++#define PCI_DEVICE_ID_ADMTEK_ADM5120 0x5120
++
+ #define PCI_VENDOR_ID_SIIG 0x131f
+ #define PCI_SUBVENDOR_ID_SIIG 0x131f
+ #define PCI_DEVICE_ID_SIIG_1S_10x_550 0x1000
--- /dev/null
+--- a/drivers/leds/Kconfig
++++ b/drivers/leds/Kconfig
+@@ -207,4 +207,12 @@
+ This allows LEDs to be controlled by network device activity.
+ If unsure, say Y.
+
++config LEDS_TRIGGER_ADM5120_SWITCH
++ tristate "LED ADM5120 Switch Port Status Trigger"
++ depends on LEDS_TRIGGERS && ADM5120
++ help
++ This allows LEDs to be controlled by the port states of
++ the ADM5120 built-in Ethernet Switch
++ If unsure, say N.
++
+ endif # NEW_LEDS
+--- a/drivers/leds/Makefile
++++ b/drivers/leds/Makefile
+@@ -30,3 +30,4 @@
+ obj-$(CONFIG_LEDS_TRIGGER_DEFAULT_ON) += ledtrig-default-on.o
+ obj-$(CONFIG_LEDS_TRIGGER_MORSE) += ledtrig-morse.o
+ obj-$(CONFIG_LEDS_TRIGGER_NETDEV) += ledtrig-netdev.o
++obj-$(CONFIG_LEDS_TRIGGER_ADM5120_SWITCH) += ledtrig-adm5120-switch.o
--- /dev/null
+--- a/drivers/mtd/Kconfig
++++ b/drivers/mtd/Kconfig
+@@ -174,6 +174,22 @@
+ ---help---
+ TI AR7 partitioning support
+
++config MTD_MYLOADER_PARTS
++ tristate "MyLoader partition parsing"
++ depends on ADM5120 && MTD_PARTITIONS
++ ---help---
++ MyLoader is a bootloader which allows the user to define partitions
++ in flash devices, by putting a table in the second erase block
++ on the device, similar to a partition table. This table gives the
++ offsets and lengths of the user defined partitions.
++
++ If you need code which can detect and parse these tables, and
++ register MTD 'partitions' corresponding to each image detected,
++ enable this option.
++
++ You will still need the parsing functions to be called by the driver
++ for your particular device. It won't happen automatically.
++
+ comment "User Modules And Translation Layers"
+
+ config MTD_CHAR
+--- a/drivers/mtd/Makefile
++++ b/drivers/mtd/Makefile
+@@ -13,6 +13,7 @@
+ obj-$(CONFIG_MTD_AFS_PARTS) += afs.o
+ obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o
+ obj-$(CONFIG_MTD_OF_PARTS) += ofpart.o
++obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o
+
+ # 'Users' - code which presents functionality to userspace.
+ obj-$(CONFIG_MTD_CHAR) += mtdchar.o
--- /dev/null
+--- a/drivers/mtd/chips/cfi_cmdset_0002.c
++++ b/drivers/mtd/chips/cfi_cmdset_0002.c
+@@ -47,12 +47,19 @@
+ #define MANUFACTURER_AMD 0x0001
+ #define MANUFACTURER_ATMEL 0x001F
+ #define MANUFACTURER_SST 0x00BF
++#define MANUFACTURER_MACRONIX 0x00C2
+ #define SST49LF004B 0x0060
+ #define SST49LF040B 0x0050
+ #define SST49LF008A 0x005a
+ #define AT49BV6416 0x00d6
+ #define MANUFACTURER_SAMSUNG 0x00ec
+
++/* Macronix */
++#define MX29LV160B 0x2249 /* MX29LV160 Bottom-boot chip */
++#define MX29LV160T 0x22C4 /* MX29LV160 Top-boot chip */
++#define MX29LV320B 0x22A8 /* MX29LV320 Bottom-boot chip */
++#define MX29LV320T 0x22A7 /* MX29LV320 Top-boot chip */
++
+ static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
+ static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
+ static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
+@@ -243,6 +250,41 @@
+ }
+ }
+
++#ifdef CONFIG_MTD_CFI_FIXUP_MACRONIX_BOOTLOC
++/*
++ * Some Macronix chips has no/bad bootblock information in the CFI table
++ */
++static void fixup_macronix_bootloc(struct mtd_info *mtd, void* param)
++{
++ struct map_info *map = mtd->priv;
++ struct cfi_private *cfi = map->fldrv_priv;
++ struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
++ __u8 t;
++
++ switch (cfi->id) {
++ /* TODO: put affected chip ids here */
++ case MX29LV160B:
++ case MX29LV320B:
++ t = 2; /* Bottom boot */
++ break;
++ case MX29LV160T:
++ case MX29LV320T:
++ t = 3; /* Top boot */
++ break;
++ default:
++ return;
++ }
++
++ if (extp->TopBottom == t)
++ /* boot location detected by the CFI layer is correct */
++ return;
++
++ extp->TopBottom = t;
++ printk("%s: Macronix chip detected, id:0x%04X, boot location forced "
++ "to %s\n", map->name, cfi->id, (t == 2) ? "bottom" : "top");
++}
++#endif /* CONFIG_MTD_CFI_FIXUP_MACRONIX_BOOTLOC */
++
+ static struct cfi_fixup cfi_fixup_table[] = {
+ { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri, NULL },
+ #ifdef AMD_BOOTLOC_BUG
+@@ -278,6 +320,9 @@
+ */
+ { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_erase_chip, NULL },
+ { CFI_MFR_ATMEL, AT49BV6416, fixup_use_atmel_lock, NULL },
++#ifdef CONFIG_MTD_CFI_FIXUP_MACRONIX_BOOTLOC
++ { MANUFACTURER_MACRONIX, CFI_ID_ANY, fixup_macronix_bootloc, NULL, },
++#endif
+ { 0, 0, NULL, NULL }
+ };
+
+--- a/drivers/mtd/chips/Kconfig
++++ b/drivers/mtd/chips/Kconfig
+@@ -196,6 +196,14 @@
+ provides support for one of those command sets, used on chips
+ including the AMD Am29LV320.
+
++config MTD_CFI_FIXUP_MACRONIX_BOOTLOC
++ bool "Fix boot-block location for Macronix flash chips"
++ depends on MTD_CFI_AMDSTD
++ help
++ Some Macronix flash chips have no/wrong boot-block location in the
++ CFI table, and the driver may detect the type incorrectly. Select
++ this if your board has such chip.
++
+ config MTD_CFI_STAA
+ tristate "Support for ST (Advanced Architecture) flash chips"
+ depends on MTD_GEN_PROBE
--- /dev/null
+--- a/drivers/mtd/chips/jedec_probe.c
++++ b/drivers/mtd/chips/jedec_probe.c
+@@ -121,6 +121,10 @@
+ #define UPD29F064115 0x221C
+
+ /* PMC */
++#define PM39LV512 0x001B
++#define PM39LV010 0x001C
++#define PM39LV020 0x003D
++#define PM39LV040 0x003E
+ #define PM49FL002 0x006D
+ #define PM49FL004 0x006E
+ #define PM49FL008 0x006A
+@@ -1173,6 +1177,54 @@
+ ERASEINFO(0x02000,2),
+ ERASEINFO(0x04000,1),
+ }
++ }, {
++ .mfr_id = MANUFACTURER_PMC,
++ .dev_id = PM39LV512,
++ .name = "PMC Pm39LV512",
++ .devtypes = CFI_DEVICETYPE_X8,
++ .uaddr = MTD_UADDR_0x0555_0x02AA,
++ .dev_size = SIZE_64KiB,
++ .cmd_set = P_ID_AMD_STD,
++ .nr_regions = 1,
++ .regions = {
++ ERASEINFO(0x01000,16),
++ }
++ }, {
++ .mfr_id = MANUFACTURER_PMC,
++ .dev_id = PM39LV010,
++ .name = "PMC Pm39LV010",
++ .devtypes = CFI_DEVICETYPE_X8,
++ .uaddr = MTD_UADDR_0x0555_0x02AA,
++ .dev_size = SIZE_128KiB,
++ .cmd_set = P_ID_AMD_STD,
++ .nr_regions = 1,
++ .regions = {
++ ERASEINFO(0x01000,32),
++ }
++ }, {
++ .mfr_id = MANUFACTURER_PMC,
++ .dev_id = PM39LV020,
++ .name = "PMC Pm39LV020",
++ .devtypes = CFI_DEVICETYPE_X8,
++ .uaddr = MTD_UADDR_0x0555_0x02AA,
++ .dev_size = SIZE_256KiB,
++ .cmd_set = P_ID_AMD_STD,
++ .nr_regions = 1,
++ .regions = {
++ ERASEINFO(0x01000,64),
++ }
++ }, {
++ .mfr_id = MANUFACTURER_PMC,
++ .dev_id = PM39LV040,
++ .name = "PMC Pm39LV040",
++ .devtypes = CFI_DEVICETYPE_X8,
++ .uaddr = MTD_UADDR_0x0555_0x02AA,
++ .dev_size = SIZE_512KiB,
++ .cmd_set = P_ID_AMD_STD,
++ .nr_regions = 1,
++ .regions = {
++ ERASEINFO(0x01000,128),
++ }
+ }, {
+ .mfr_id = MANUFACTURER_PMC,
+ .dev_id = PM49FL002,
--- /dev/null
+--- a/drivers/mtd/Kconfig
++++ b/drivers/mtd/Kconfig
+@@ -57,6 +57,11 @@
+ depends on MTD_PARTITIONS
+ default y
+
++config MTD_TRXSPLIT
++ bool "Automatically find and split TRX partitions"
++ depends on MTD_PARTITIONS
++ default n
++
+ config MTD_REDBOOT_PARTS
+ tristate "RedBoot partition table parsing"
+ depends on MTD_PARTITIONS
+--- a/drivers/mtd/Makefile
++++ b/drivers/mtd/Makefile
+@@ -8,6 +8,7 @@
+ mtd-$(CONFIG_MTD_PARTITIONS) += mtdpart.o
+
+ obj-$(CONFIG_MTD_CONCAT) += mtdconcat.o
++obj-$(CONFIG_MTD_TRXSPLIT) += trxsplit.o
+ obj-$(CONFIG_MTD_REDBOOT_PARTS) += redboot.o
+ obj-$(CONFIG_MTD_CMDLINE_PARTS) += cmdlinepart.o
+ obj-$(CONFIG_MTD_AFS_PARTS) += afs.o
--- /dev/null
+--- a/drivers/ata/Makefile
++++ b/drivers/ata/Makefile
+@@ -72,6 +72,7 @@
+ obj-$(CONFIG_PATA_PLATFORM) += pata_platform.o
+ obj-$(CONFIG_PATA_OF_PLATFORM) += pata_of_platform.o
+ obj-$(CONFIG_PATA_ICSIDE) += pata_icside.o
++obj-$(CONFIG_PATA_RB153_CF) += pata_rb153_cf.o
+ # Should be last but two libata driver
+ obj-$(CONFIG_PATA_ACPI) += pata_acpi.o
+ # Should be last but one libata driver
+--- a/drivers/ata/Kconfig
++++ b/drivers/ata/Kconfig
+@@ -566,6 +566,15 @@
+
+ If unsure, say N.
+
++config PATA_RB153_CF
++ tristate "RouterBOARD 153 Compact Flash support"
++ depends on ADM5120_MACH_RB_153
++ help
++ This option enables support for a Compact Flash connected on
++ the RouterBOARD 153.
++
++ If unsure, say N.
++
+ config PATA_RB532
+ tristate "RouterBoard 532 PATA CompactFlash support"
+ depends on MIKROTIK_RB532
--- /dev/null
+--- a/arch/mips/kernel/head.S
++++ b/arch/mips/kernel/head.S
+@@ -126,7 +126,12 @@
+ /*
+ * Reserved space for exception handlers.
+ * Necessary for machines which link their kernels at KSEG0.
++ * Use as temporary storage for the kernel command line, so that it
++ * can be updated easily without having to relink the kernel.
+ */
++
++EXPORT(_image_cmdline)
++ .ascii "CMDLINE:"
+ .fill 0x400
+ #endif
+
--- /dev/null
+--- a/drivers/serial/amba-pl010.c
++++ b/drivers/serial/amba-pl010.c
+@@ -52,11 +52,10 @@
+
+ #include <asm/io.h>
+
+-#define UART_NR 8
+-
+ #define SERIAL_AMBA_MAJOR 204
+ #define SERIAL_AMBA_MINOR 16
+-#define SERIAL_AMBA_NR UART_NR
++#define SERIAL_AMBA_NR CONFIG_SERIAL_AMBA_PL010_NUMPORTS
++#define SERIAL_AMBA_NAME CONFIG_SERIAL_AMBA_PL010_PORTNAME
+
+ #define AMBA_ISR_PASS_LIMIT 256
+
+@@ -82,9 +81,9 @@
+ struct uart_amba_port *uap = (struct uart_amba_port *)port;
+ unsigned int cr;
+
+- cr = readb(uap->port.membase + UART010_CR);
++ cr = __raw_readl(uap->port.membase + UART010_CR);
+ cr &= ~UART010_CR_TIE;
+- writel(cr, uap->port.membase + UART010_CR);
++ __raw_writel(cr, uap->port.membase + UART010_CR);
+ }
+
+ static void pl010_start_tx(struct uart_port *port)
+@@ -92,9 +91,9 @@
+ struct uart_amba_port *uap = (struct uart_amba_port *)port;
+ unsigned int cr;
+
+- cr = readb(uap->port.membase + UART010_CR);
++ cr = __raw_readl(uap->port.membase + UART010_CR);
+ cr |= UART010_CR_TIE;
+- writel(cr, uap->port.membase + UART010_CR);
++ __raw_writel(cr, uap->port.membase + UART010_CR);
+ }
+
+ static void pl010_stop_rx(struct uart_port *port)
+@@ -102,9 +101,9 @@
+ struct uart_amba_port *uap = (struct uart_amba_port *)port;
+ unsigned int cr;
+
+- cr = readb(uap->port.membase + UART010_CR);
++ cr = __raw_readl(uap->port.membase + UART010_CR);
+ cr &= ~(UART010_CR_RIE | UART010_CR_RTIE);
+- writel(cr, uap->port.membase + UART010_CR);
++ __raw_writel(cr, uap->port.membase + UART010_CR);
+ }
+
+ static void pl010_enable_ms(struct uart_port *port)
+@@ -112,9 +111,9 @@
+ struct uart_amba_port *uap = (struct uart_amba_port *)port;
+ unsigned int cr;
+
+- cr = readb(uap->port.membase + UART010_CR);
++ cr = __raw_readl(uap->port.membase + UART010_CR);
+ cr |= UART010_CR_MSIE;
+- writel(cr, uap->port.membase + UART010_CR);
++ __raw_writel(cr, uap->port.membase + UART010_CR);
+ }
+
+ static void pl010_rx_chars(struct uart_amba_port *uap)
+@@ -122,9 +121,9 @@
+ struct tty_struct *tty = uap->port.info->tty;
+ unsigned int status, ch, flag, rsr, max_count = 256;
+
+- status = readb(uap->port.membase + UART01x_FR);
++ status = __raw_readl(uap->port.membase + UART01x_FR);
+ while (UART_RX_DATA(status) && max_count--) {
+- ch = readb(uap->port.membase + UART01x_DR);
++ ch = __raw_readl(uap->port.membase + UART01x_DR);
+ flag = TTY_NORMAL;
+
+ uap->port.icount.rx++;
+@@ -133,9 +132,9 @@
+ * Note that the error handling code is
+ * out of the main execution path
+ */
+- rsr = readb(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX;
++ rsr = __raw_readl(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX;
+ if (unlikely(rsr & UART01x_RSR_ANY)) {
+- writel(0, uap->port.membase + UART01x_ECR);
++ __raw_writel(0, uap->port.membase + UART01x_ECR);
+
+ if (rsr & UART01x_RSR_BE) {
+ rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE);
+@@ -165,7 +164,7 @@
+ uart_insert_char(&uap->port, rsr, UART01x_RSR_OE, ch, flag);
+
+ ignore_char:
+- status = readb(uap->port.membase + UART01x_FR);
++ status = __raw_readl(uap->port.membase + UART01x_FR);
+ }
+ spin_unlock(&uap->port.lock);
+ tty_flip_buffer_push(tty);
+@@ -178,7 +177,7 @@
+ int count;
+
+ if (uap->port.x_char) {
+- writel(uap->port.x_char, uap->port.membase + UART01x_DR);
++ __raw_writel(uap->port.x_char, uap->port.membase + UART01x_DR);
+ uap->port.icount.tx++;
+ uap->port.x_char = 0;
+ return;
+@@ -190,7 +189,7 @@
+
+ count = uap->port.fifosize >> 1;
+ do {
+- writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
++ __raw_writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
+ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+ uap->port.icount.tx++;
+ if (uart_circ_empty(xmit))
+@@ -208,9 +207,9 @@
+ {
+ unsigned int status, delta;
+
+- writel(0, uap->port.membase + UART010_ICR);
++ __raw_writel(0, uap->port.membase + UART010_ICR);
+
+- status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
++ status = __raw_readl(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
+
+ delta = status ^ uap->old_status;
+ uap->old_status = status;
+@@ -238,7 +237,7 @@
+
+ spin_lock(&uap->port.lock);
+
+- status = readb(uap->port.membase + UART010_IIR);
++ status = __raw_readl(uap->port.membase + UART010_IIR);
+ if (status) {
+ do {
+ if (status & (UART010_IIR_RTIS | UART010_IIR_RIS))
+@@ -251,7 +250,7 @@
+ if (pass_counter-- == 0)
+ break;
+
+- status = readb(uap->port.membase + UART010_IIR);
++ status = __raw_readl(uap->port.membase + UART010_IIR);
+ } while (status & (UART010_IIR_RTIS | UART010_IIR_RIS |
+ UART010_IIR_TIS));
+ handled = 1;
+@@ -265,7 +264,7 @@
+ static unsigned int pl010_tx_empty(struct uart_port *port)
+ {
+ struct uart_amba_port *uap = (struct uart_amba_port *)port;
+- unsigned int status = readb(uap->port.membase + UART01x_FR);
++ unsigned int status = __raw_readl(uap->port.membase + UART01x_FR);
+ return status & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT;
+ }
+
+@@ -275,7 +274,7 @@
+ unsigned int result = 0;
+ unsigned int status;
+
+- status = readb(uap->port.membase + UART01x_FR);
++ status = __raw_readl(uap->port.membase + UART01x_FR);
+ if (status & UART01x_FR_DCD)
+ result |= TIOCM_CAR;
+ if (status & UART01x_FR_DSR)
+@@ -301,12 +300,12 @@
+ unsigned int lcr_h;
+
+ spin_lock_irqsave(&uap->port.lock, flags);
+- lcr_h = readb(uap->port.membase + UART010_LCRH);
++ lcr_h = __raw_readl(uap->port.membase + UART010_LCRH);
+ if (break_state == -1)
+ lcr_h |= UART01x_LCRH_BRK;
+ else
+ lcr_h &= ~UART01x_LCRH_BRK;
+- writel(lcr_h, uap->port.membase + UART010_LCRH);
++ __raw_writel(lcr_h, uap->port.membase + UART010_LCRH);
+ spin_unlock_irqrestore(&uap->port.lock, flags);
+ }
+
+@@ -334,12 +333,12 @@
+ /*
+ * initialise the old status of the modem signals
+ */
+- uap->old_status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
++ uap->old_status = __raw_readl(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
+
+ /*
+ * Finally, enable interrupts
+ */
+- writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE,
++ __raw_writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE,
+ uap->port.membase + UART010_CR);
+
+ return 0;
+@@ -362,10 +361,10 @@
+ /*
+ * disable all interrupts, disable the port
+ */
+- writel(0, uap->port.membase + UART010_CR);
++ __raw_writel(0, uap->port.membase + UART010_CR);
+
+ /* disable break condition and fifos */
+- writel(readb(uap->port.membase + UART010_LCRH) &
++ __raw_writel(__raw_readl(uap->port.membase + UART010_LCRH) &
+ ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN),
+ uap->port.membase + UART010_LCRH);
+
+@@ -387,7 +386,7 @@
+ /*
+ * Ask the core to calculate the divisor for us.
+ */
+- baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16);
++ baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16);
+ quot = uart_get_divisor(port, baud);
+
+ switch (termios->c_cflag & CSIZE) {
+@@ -450,25 +449,25 @@
+ uap->port.ignore_status_mask |= UART_DUMMY_RSR_RX;
+
+ /* first, disable everything */
+- old_cr = readb(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE;
++ old_cr = __raw_readl(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE;
+
+ if (UART_ENABLE_MS(port, termios->c_cflag))
+ old_cr |= UART010_CR_MSIE;
+
+- writel(0, uap->port.membase + UART010_CR);
++ __raw_writel(0, uap->port.membase + UART010_CR);
+
+ /* Set baud rate */
+ quot -= 1;
+- writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM);
+- writel(quot & 0xff, uap->port.membase + UART010_LCRL);
++ __raw_writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM);
++ __raw_writel(quot & 0xff, uap->port.membase + UART010_LCRL);
+
+ /*
+ * ----------v----------v----------v----------v-----
+ * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
+ * ----------^----------^----------^----------^-----
+ */
+- writel(lcr_h, uap->port.membase + UART010_LCRH);
+- writel(old_cr, uap->port.membase + UART010_CR);
++ __raw_writel(lcr_h, uap->port.membase + UART010_LCRH);
++ __raw_writel(old_cr, uap->port.membase + UART010_CR);
+
+ spin_unlock_irqrestore(&uap->port.lock, flags);
+ }
+@@ -540,7 +539,7 @@
+ .verify_port = pl010_verify_port,
+ };
+
+-static struct uart_amba_port *amba_ports[UART_NR];
++static struct uart_amba_port *amba_ports[SERIAL_AMBA_NR];
+
+ #ifdef CONFIG_SERIAL_AMBA_PL010_CONSOLE
+
+@@ -550,10 +549,10 @@
+ unsigned int status;
+
+ do {
+- status = readb(uap->port.membase + UART01x_FR);
++ status = __raw_readl(uap->port.membase + UART01x_FR);
+ barrier();
+ } while (!UART_TX_READY(status));
+- writel(ch, uap->port.membase + UART01x_DR);
++ __raw_writel(ch, uap->port.membase + UART01x_DR);
+ }
+
+ static void
+@@ -567,8 +566,8 @@
+ /*
+ * First save the CR then disable the interrupts
+ */
+- old_cr = readb(uap->port.membase + UART010_CR);
+- writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR);
++ old_cr = __raw_readl(uap->port.membase + UART010_CR);
++ __raw_writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR);
+
+ uart_console_write(&uap->port, s, count, pl010_console_putchar);
+
+@@ -577,10 +576,10 @@
+ * and restore the TCR
+ */
+ do {
+- status = readb(uap->port.membase + UART01x_FR);
++ status = __raw_readl(uap->port.membase + UART01x_FR);
+ barrier();
+ } while (status & UART01x_FR_BUSY);
+- writel(old_cr, uap->port.membase + UART010_CR);
++ __raw_writel(old_cr, uap->port.membase + UART010_CR);
+
+ clk_disable(uap->clk);
+ }
+@@ -589,9 +588,9 @@
+ pl010_console_get_options(struct uart_amba_port *uap, int *baud,
+ int *parity, int *bits)
+ {
+- if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) {
++ if (__raw_readl(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) {
+ unsigned int lcr_h, quot;
+- lcr_h = readb(uap->port.membase + UART010_LCRH);
++ lcr_h = __raw_readl(uap->port.membase + UART010_LCRH);
+
+ *parity = 'n';
+ if (lcr_h & UART01x_LCRH_PEN) {
+@@ -606,8 +605,8 @@
+ else
+ *bits = 8;
+
+- quot = readb(uap->port.membase + UART010_LCRL) |
+- readb(uap->port.membase + UART010_LCRM) << 8;
++ quot = __raw_readl(uap->port.membase + UART010_LCRL) |
++ __raw_readl(uap->port.membase + UART010_LCRM) << 8;
+ *baud = uap->port.uartclk / (16 * (quot + 1));
+ }
+ }
+@@ -625,7 +624,7 @@
+ * if so, search for the first available port that does have
+ * console support.
+ */
+- if (co->index >= UART_NR)
++ if (co->index >= SERIAL_AMBA_NR)
+ co->index = 0;
+ uap = amba_ports[co->index];
+ if (!uap)
+@@ -643,7 +642,7 @@
+
+ static struct uart_driver amba_reg;
+ static struct console amba_console = {
+- .name = "ttyAM",
++ .name = SERIAL_AMBA_NAME,
+ .write = pl010_console_write,
+ .device = uart_console_device,
+ .setup = pl010_console_setup,
+@@ -659,11 +658,11 @@
+
+ static struct uart_driver amba_reg = {
+ .owner = THIS_MODULE,
+- .driver_name = "ttyAM",
+- .dev_name = "ttyAM",
++ .driver_name = SERIAL_AMBA_NAME,
++ .dev_name = SERIAL_AMBA_NAME,
+ .major = SERIAL_AMBA_MAJOR,
+ .minor = SERIAL_AMBA_MINOR,
+- .nr = UART_NR,
++ .nr = SERIAL_AMBA_NR,
+ .cons = AMBA_CONSOLE,
+ };
+
+--- a/drivers/serial/Kconfig
++++ b/drivers/serial/Kconfig
+@@ -287,10 +287,25 @@
+ help
+ This selects the ARM(R) AMBA(R) PrimeCell PL010 UART. If you have
+ an Integrator/AP or Integrator/PP2 platform, or if you have a
+- Cirrus Logic EP93xx CPU, say Y or M here.
++ Cirrus Logic EP93xx CPU or an Infineon ADM5120 SOC, say Y or M here.
+
+ If unsure, say N.
+
++config SERIAL_AMBA_PL010_NUMPORTS
++ int "Maximum number of AMBA PL010 serial ports"
++ depends on SERIAL_AMBA_PL010
++ default "8"
++ ---help---
++ Set this to the number of serial ports you want the AMBA PL010 driver
++ to support.
++
++config SERIAL_AMBA_PL010_PORTNAME
++ string "Name of the AMBA PL010 serial ports"
++ depends on SERIAL_AMBA_PL010
++ default "ttyAM"
++ ---help---
++ ::: To be written :::
++
+ config SERIAL_AMBA_PL010_CONSOLE
+ bool "Support for console on AMBA serial port"
+ depends on SERIAL_AMBA_PL010=y
--- /dev/null
+--- a/drivers/amba/bus.c
++++ b/drivers/amba/bus.c
+@@ -17,6 +17,10 @@
+ #include <asm/io.h>
+ #include <asm/sizes.h>
+
++#ifndef NO_IRQ
++#define NO_IRQ (-1)
++#endif
++
+ #define to_amba_device(d) container_of(d, struct amba_device, dev)
+ #define to_amba_driver(d) container_of(d, struct amba_driver, drv)
+
--- /dev/null
+--- a/drivers/pci/Kconfig
++++ b/drivers/pci/Kconfig
+@@ -42,6 +42,12 @@
+
+ When in doubt, say N.
+
++config PCI_DISABLE_COMMON_QUIRKS
++ bool "PCI disable common quirks"
++ depends on PCI
++ help
++ If you don't know what to do here, say N.
++
+ config HT_IRQ
+ bool "Interrupts on hypertransport devices"
+ default y
+--- a/drivers/pci/quirks.c
++++ b/drivers/pci/quirks.c
+@@ -24,6 +24,7 @@
+ #include <linux/kallsyms.h>
+ #include "pci.h"
+
++#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS
+ /* The Mellanox Tavor device gives false positive parity errors
+ * Mark this device with a broken_parity_status, to allow
+ * PCI scanning code to "skip" this now blacklisted device.
+@@ -1495,6 +1496,7 @@
+ }
+ }
+ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
++#endif /* !CONFIG_PCI_DISABLE_COMMON_QUIRKS */
+
+ static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end)
+ {
+@@ -1561,6 +1563,7 @@
+ }
+ EXPORT_SYMBOL(pci_fixup_device);
+
++#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS
+ /* Enable 1k I/O space granularity on the Intel P64H2 */
+ static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
+ {
+@@ -1934,3 +1937,4 @@
+ quirk_msi_intx_disable_bug);
+
+ #endif /* CONFIG_PCI_MSI */
++#endif /* !CONFIG_PCI_DISABLE_COMMON_QUIRKS */
--- /dev/null
+--- a/drivers/leds/leds-gpio.c
++++ b/drivers/leds/leds-gpio.c
+@@ -43,13 +43,17 @@
+ container_of(led_cdev, struct gpio_led_data, cdev);
+ int level;
+
+- if (value == LED_OFF)
+- level = 0;
+- else
+- level = 1;
+-
+- if (led_dat->active_low)
+- level = !level;
++ switch (value) {
++ case LED_OFF:
++ level = led_dat->active_low ? 1 : 0;
++ break;
++ case LED_FULL:
++ level = led_dat->active_low ? 0 : 1;
++ break;
++ default:
++ level = value;
++ break;
++ }
+
+ /* Setting GPIOs with I2C/etc requires a task context, and we don't
+ * seem to have a reliable way to know if we're already in one; so
--- /dev/null
+--- a/drivers/watchdog/Kconfig
++++ b/drivers/watchdog/Kconfig
+@@ -632,6 +632,18 @@
+
+ # MIPS Architecture
+
++config ADM5120_WDT
++ tristate "Infineon ADM5120 SoC hardware watchdog"
++ depends on WATCHDOG && ADM5120
++ help
++ This is a driver for hardware watchdog integrated in Infineon
++ ADM5120 SoC. This watchdog simply watches your kernel to make sure
++ it doesn't freeze, and if it does, it reboots your computer after a
++ certain amount of time.
++
++ To compile this driver as a module, choose M here: the module will be
++ called adm5120_wdt.
++
+ config INDYDOG
+ tristate "Indy/I2 Hardware Watchdog"
+ depends on SGI_HAS_INDYDOG
+--- a/drivers/watchdog/Makefile
++++ b/drivers/watchdog/Makefile
+@@ -91,6 +91,7 @@
+ # M68KNOMMU Architecture
+
+ # MIPS Architecture
++obj-$(CONFIG_ADM5120_WDT) += adm5120_wdt.o
+ obj-$(CONFIG_INDYDOG) += indydog.o
+ obj-$(CONFIG_WDT_MTX1) += mtx-1_wdt.o
+ obj-$(CONFIG_WDT_RM9K_GPI) += rm9k_wdt.o
+++ /dev/null
-CONFIG_32BIT=y
-# CONFIG_64BIT is not set
-CONFIG_ADM5120=y
-CONFIG_ADM5120_ENET=y
-CONFIG_ADM5120_MACH_P_334WT=y
-CONFIG_ADM5120_MACH_P_335=y
-# CONFIG_ADM5120_OEM_CELLVISION is not set
-# CONFIG_ADM5120_OEM_COMPEX is not set
-# CONFIG_ADM5120_OEM_EDIMAX is not set
-# CONFIG_ADM5120_OEM_INFINEON is not set
-# CONFIG_ADM5120_OEM_MIKROTIK is not set
-# CONFIG_ADM5120_OEM_MOTOROLA is not set
-CONFIG_ADM5120_OEM_ZYXEL=y
-CONFIG_ADM5120_SOC_BGA=y
-CONFIG_ADM5120_WDT=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_ARCH_POPULATES_NODE_MAP=y
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-CONFIG_ARCH_SUPPORTS_OPROFILE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM_AMBA=y
-CONFIG_BASE_SMALL=0
-CONFIG_BAYCOM_SER_FDX=m
-CONFIG_BAYCOM_SER_HDX=m
-# CONFIG_BCM47XX is not set
-CONFIG_BINFMT_MISC=m
-CONFIG_BITREVERSE=y
-CONFIG_CEVT_R4K=y
-CONFIG_CIFS_DEBUG2=y
-CONFIG_CIFS_EXPERIMENTAL=y
-CONFIG_CIFS_STATS2=y
-CONFIG_CIFS_WEAK_PW_HASH=y
-CONFIG_CIFS_XATTR=y
-CONFIG_CLASSIC_RCU=y
-CONFIG_CMDLINE="console=ttyS0,115200 rootfstype=squashfs,jffs2 init=/etc/preinit"
-CONFIG_CPU_BIG_ENDIAN=y
-CONFIG_CPU_HAS_LLSC=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_SYNC=y
-# CONFIG_CPU_LITTLE_ENDIAN is not set
-# CONFIG_CPU_LOONGSON2 is not set
-CONFIG_CPU_MIPS32=y
-CONFIG_CPU_MIPS32_R1=y
-# CONFIG_CPU_MIPS32_R2 is not set
-# CONFIG_CPU_MIPS64_R1 is not set
-# CONFIG_CPU_MIPS64_R2 is not set
-CONFIG_CPU_MIPSR1=y
-# CONFIG_CPU_NEVADA is not set
-# CONFIG_CPU_R10000 is not set
-# CONFIG_CPU_R3000 is not set
-# CONFIG_CPU_R4300 is not set
-# CONFIG_CPU_R4X00 is not set
-# CONFIG_CPU_R5000 is not set
-# CONFIG_CPU_R5432 is not set
-# CONFIG_CPU_R6000 is not set
-# CONFIG_CPU_R8000 is not set
-# CONFIG_CPU_RM7000 is not set
-# CONFIG_CPU_RM9000 is not set
-# CONFIG_CPU_SB1 is not set
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-# CONFIG_CPU_TX39XX is not set
-# CONFIG_CPU_TX49XX is not set
-# CONFIG_CPU_VR41XX is not set
-CONFIG_CSRC_R4K=y
-CONFIG_DEVPORT=y
-# CONFIG_DM9000 is not set
-CONFIG_DMA_NEED_PCI_MAP_STATE=y
-CONFIG_DMA_NONCOHERENT=y
-# CONFIG_E1000E_ENABLED is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_ELF_CORE=y
-# CONFIG_EXT3_FS_POSIX_ACL is not set
-# CONFIG_EXT3_FS_SECURITY is not set
-CONFIG_EXT3_FS_XATTR=y
-CONFIG_FS_MBCACHE=m
-CONFIG_FS_POSIX_ACL=y
-CONFIG_GENERIC_ACL=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-# CONFIG_GENERIC_FIND_FIRST_BIT is not set
-CONFIG_GENERIC_FIND_NEXT_BIT=y
-CONFIG_GENERIC_GPIO=y
-# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
-CONFIG_GPIO_SYSFS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAVE_DMA_ATTRS is not set
-CONFIG_HAVE_GPIO_LIB=y
-CONFIG_HAVE_IDE=y
-# CONFIG_HAVE_KPROBES is not set
-# CONFIG_HAVE_KRETPROBES is not set
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HID=m
-CONFIG_HID_SUPPORT=y
-CONFIG_HW_HAS_PCI=y
-CONFIG_HW_RANDOM=y
-CONFIG_HZ=250
-# CONFIG_HZ_100 is not set
-CONFIG_HZ_250=y
-# CONFIG_I2C is not set
-# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_IBM_NEW_EMAC_RGMII is not set
-# CONFIG_IBM_NEW_EMAC_TAH is not set
-# CONFIG_IBM_NEW_EMAC_ZMII is not set
-# CONFIG_IDE is not set
-CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-CONFIG_INPUT=m
-# CONFIG_INPUT_EVDEV is not set
-CONFIG_IPV6_MIP6=m
-CONFIG_IPV6_NDISC_NODETYPE=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTE_INFO=y
-CONFIG_IPV6_TUNNEL=m
-CONFIG_IP_NF_TARGET_CLUSTERIP=m
-CONFIG_IRQ_CPU=y
-# CONFIG_IWLWIFI_LEDS is not set
-# CONFIG_JOLIET is not set
-# CONFIG_LEDS_ALIX is not set
-CONFIG_LEDS_GPIO=m
-CONFIG_LEDS_TRIGGER_ADM5120_SWITCH=m
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-# CONFIG_LEMOTE_FULONG is not set
-# CONFIG_MACH_ALCHEMY is not set
-# CONFIG_MACH_DECSTATION is not set
-# CONFIG_MACH_JAZZ is not set
-# CONFIG_MACH_VR41XX is not set
-CONFIG_MII=m
-# CONFIG_MINIX_FS is not set
-CONFIG_MIPS=y
-# CONFIG_MIPS_ATLAS is not set
-# CONFIG_MIPS_COBALT is not set
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-# CONFIG_MIPS_MALTA is not set
-CONFIG_MIPS_MT_DISABLED=y
-# CONFIG_MIPS_MT_SMP is not set
-# CONFIG_MIPS_MT_SMTC is not set
-# CONFIG_MIPS_SEAD is not set
-# CONFIG_MIPS_SIM is not set
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MTD=y
-# CONFIG_MTD_ABSENT is not set
-CONFIG_MTD_ADM5120=y
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_BLOCK2MTD=y
-CONFIG_MTD_CFI=y
-# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_CFI_FIXUP_MACRONIX_BOOTLOC=y
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-# CONFIG_MTD_CFI_INTELEXT is not set
-# CONFIG_MTD_CFI_STAA is not set
-CONFIG_MTD_CFI_UTIL=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-# CONFIG_MTD_CONCAT is not set
-# CONFIG_MTD_DEBUG is not set
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-CONFIG_MTD_GEN_PROBE=y
-# CONFIG_MTD_JEDECPROBE is not set
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_MYLOADER_PARTS is not set
-# CONFIG_MTD_ONENAND is not set
-CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_PCI is not set
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_PHYSMAP is not set
-# CONFIG_MTD_PLATRAM is not set
-# CONFIG_MTD_PMC551 is not set
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_SLRAM is not set
-CONFIG_MTD_TRXSPLIT=y
-# CONFIG_NET_PCI is not set
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_NET_VENDOR_3COM is not set
-# CONFIG_NO_IOPORT is not set
-# CONFIG_OCF_OCF is not set
-CONFIG_PAGEFLAGS_EXTENDED=y
-# CONFIG_PAGE_SIZE_16KB is not set
-CONFIG_PAGE_SIZE_4KB=y
-# CONFIG_PAGE_SIZE_64KB is not set
-# CONFIG_PAGE_SIZE_8KB is not set
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_PCI=y
-# CONFIG_PCIPCWATCHDOG is not set
-CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
-CONFIG_PCI_DOMAINS=y
-# CONFIG_PCSPKR_PLATFORM is not set
-# CONFIG_PMC_MSP is not set
-# CONFIG_PMC_YOSEMITE is not set
-# CONFIG_PNX8550_JBS is not set
-# CONFIG_PNX8550_STB810 is not set
-CONFIG_RFKILL_LEDS=y
-CONFIG_RTC_LIB=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
-CONFIG_SCSI_WAIT_SCAN=m
-# CONFIG_SERIAL_8250 is not set
-CONFIG_SERIAL_AMBA_PL010=y
-CONFIG_SERIAL_AMBA_PL010_CONSOLE=y
-CONFIG_SERIAL_AMBA_PL010_NUMPORTS=2
-CONFIG_SERIAL_AMBA_PL010_PORTNAME="ttyS"
-# CONFIG_SERIAL_AMBA_PL011 is not set
-CONFIG_SERIO=y
-# CONFIG_SERIO_AMBAKMI is not set
-# CONFIG_SERIO_I8042 is not set
-# CONFIG_SERIO_LIBPS2 is not set
-# CONFIG_SERIO_PCIPS2 is not set
-# CONFIG_SERIO_RAW is not set
-CONFIG_SERIO_SERPORT=y
-# CONFIG_SGI_IP22 is not set
-# CONFIG_SGI_IP27 is not set
-# CONFIG_SGI_IP28 is not set
-# CONFIG_SGI_IP32 is not set
-# CONFIG_SIBYTE_BIGSUR is not set
-# CONFIG_SIBYTE_CARMEL is not set
-# CONFIG_SIBYTE_CRHINE is not set
-# CONFIG_SIBYTE_CRHONE is not set
-# CONFIG_SIBYTE_LITTLESUR is not set
-# CONFIG_SIBYTE_RHONE is not set
-# CONFIG_SIBYTE_SENTOSA is not set
-# CONFIG_SIBYTE_SWARM is not set
-CONFIG_SOFT_WATCHDOG=m
-# CONFIG_SPARSEMEM_STATIC is not set
-# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
-CONFIG_SSB_POSSIBLE=y
-CONFIG_SWAP_IO_SPACE=y
-CONFIG_SYSVIPC_SYSCTL=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-# CONFIG_THERMAL is not set
-# CONFIG_THERMAL_HWMON is not set
-CONFIG_TICK_ONESHOT=y
-CONFIG_TMPFS_POSIX_ACL=y
-# CONFIG_TOSHIBA_JMR3927 is not set
-# CONFIG_TOSHIBA_RBTX4927 is not set
-# CONFIG_TOSHIBA_RBTX4938 is not set
-CONFIG_TRAD_SIGNALS=y
-CONFIG_USB=m
-CONFIG_USB_ADM5120_HCD=m
-CONFIG_USB_DEBUG=y
-CONFIG_USB_EHCI_HCD=m
-# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
-# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
-CONFIG_USB_OHCI_HCD=m
-CONFIG_USB_SUPPORT=y
-# CONFIG_USB_UHCI_HCD is not set
-# CONFIG_VGASTATE is not set
-CONFIG_VIDEO_MEDIA=m
-CONFIG_VIDEO_V4L2=m
-CONFIG_VIDEO_V4L2_COMMON=m
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_ZONE_DMA_FLAG=0
--- /dev/null
+CONFIG_32BIT=y
+# CONFIG_64BIT is not set
+CONFIG_ADM5120=y
+CONFIG_ADM5120_ENET=y
+CONFIG_ADM5120_MACH_P_334WT=y
+CONFIG_ADM5120_MACH_P_335=y
+# CONFIG_ADM5120_OEM_CELLVISION is not set
+# CONFIG_ADM5120_OEM_COMPEX is not set
+# CONFIG_ADM5120_OEM_EDIMAX is not set
+# CONFIG_ADM5120_OEM_INFINEON is not set
+# CONFIG_ADM5120_OEM_MIKROTIK is not set
+# CONFIG_ADM5120_OEM_MOTOROLA is not set
+CONFIG_ADM5120_OEM_ZYXEL=y
+CONFIG_ADM5120_SOC_BGA=y
+CONFIG_ADM5120_WDT=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM_AMBA=y
+CONFIG_BASE_SMALL=0
+CONFIG_BAYCOM_SER_FDX=m
+CONFIG_BAYCOM_SER_HDX=m
+# CONFIG_BCM47XX is not set
+CONFIG_BINFMT_MISC=m
+CONFIG_BITREVERSE=y
+CONFIG_CEVT_R4K=y
+CONFIG_CIFS_DEBUG2=y
+CONFIG_CIFS_EXPERIMENTAL=y
+CONFIG_CIFS_STATS2=y
+CONFIG_CIFS_WEAK_PW_HASH=y
+CONFIG_CIFS_XATTR=y
+CONFIG_CLASSIC_RCU=y
+CONFIG_CMDLINE="console=ttyS0,115200 rootfstype=squashfs,jffs2 init=/etc/preinit"
+CONFIG_CPU_BIG_ENDIAN=y
+CONFIG_CPU_HAS_LLSC=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_SYNC=y
+# CONFIG_CPU_LITTLE_ENDIAN is not set
+# CONFIG_CPU_LOONGSON2 is not set
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPS32_R1=y
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+CONFIG_CPU_MIPSR1=y
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_VR41XX is not set
+CONFIG_CSRC_R4K=y
+CONFIG_DEVPORT=y
+# CONFIG_DM9000 is not set
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_DMA_NONCOHERENT=y
+# CONFIG_E1000E_ENABLED is not set
+CONFIG_EARLY_PRINTK=y
+CONFIG_ELF_CORE=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_FS_MBCACHE=m
+CONFIG_FS_POSIX_ACL=y
+CONFIG_GENERIC_ACL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
+CONFIG_GPIO_SYSFS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+# CONFIG_HAVE_DMA_ATTRS is not set
+CONFIG_HAVE_GPIO_LIB=y
+CONFIG_HAVE_IDE=y
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HID=m
+CONFIG_HID_SUPPORT=y
+CONFIG_HW_HAS_PCI=y
+CONFIG_HW_RANDOM=y
+CONFIG_HZ=250
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_I2C is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IDE is not set
+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_INPUT=m
+# CONFIG_INPUT_EVDEV is not set
+CONFIG_IPV6_MIP6=m
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_IPV6_PRIVACY=y
+CONFIG_IPV6_ROUTE_INFO=y
+CONFIG_IPV6_TUNNEL=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
+CONFIG_IRQ_CPU=y
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_LEDS_ALIX is not set
+CONFIG_LEDS_GPIO=m
+CONFIG_LEDS_TRIGGER_ADM5120_SWITCH=m
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_LEMOTE_FULONG is not set
+# CONFIG_MACH_ALCHEMY is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_MACH_VR41XX is not set
+CONFIG_MII=m
+# CONFIG_MINIX_FS is not set
+CONFIG_MIPS=y
+# CONFIG_MIPS_ATLAS is not set
+# CONFIG_MIPS_COBALT is not set
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+# CONFIG_MIPS_MALTA is not set
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+# CONFIG_MIPS_SEAD is not set
+# CONFIG_MIPS_SIM is not set
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MTD=y
+# CONFIG_MTD_ABSENT is not set
+CONFIG_MTD_ADM5120=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_BLOCK2MTD=y
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_FIXUP_MACRONIX_BOOTLOC=y
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_CONCAT is not set
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_MYLOADER_PARTS is not set
+# CONFIG_MTD_ONENAND is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_PCI is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_PLATRAM is not set
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_SLRAM is not set
+CONFIG_MTD_TRXSPLIT=y
+# CONFIG_NET_PCI is not set
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NO_IOPORT is not set
+# CONFIG_OCF_OCF is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+# CONFIG_PAGE_SIZE_16KB is not set
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_64KB is not set
+# CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_PCI=y
+# CONFIG_PCIPCWATCHDOG is not set
+CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_PCSPKR_PLATFORM is not set
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+CONFIG_RFKILL_LEDS=y
+CONFIG_RTC_LIB=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_SCSI_WAIT_SCAN=m
+# CONFIG_SERIAL_8250 is not set
+CONFIG_SERIAL_AMBA_PL010=y
+CONFIG_SERIAL_AMBA_PL010_CONSOLE=y
+CONFIG_SERIAL_AMBA_PL010_NUMPORTS=2
+CONFIG_SERIAL_AMBA_PL010_PORTNAME="ttyS"
+# CONFIG_SERIAL_AMBA_PL011 is not set
+CONFIG_SERIO=y
+# CONFIG_SERIO_AMBAKMI is not set
+# CONFIG_SERIO_I8042 is not set
+# CONFIG_SERIO_LIBPS2 is not set
+# CONFIG_SERIO_PCIPS2 is not set
+# CONFIG_SERIO_RAW is not set
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_SWARM is not set
+CONFIG_SOFT_WATCHDOG=m
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SSB_POSSIBLE=y
+CONFIG_SWAP_IO_SPACE=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_TICK_ONESHOT=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_TOSHIBA_RBTX4927 is not set
+# CONFIG_TOSHIBA_RBTX4938 is not set
+CONFIG_TRAD_SIGNALS=y
+CONFIG_USB=m
+CONFIG_USB_ADM5120_HCD=m
+CONFIG_USB_DEBUG=y
+CONFIG_USB_EHCI_HCD=m
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_HCD=m
+CONFIG_USB_SUPPORT=y
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_MEDIA=m
+CONFIG_VIDEO_V4L2=m
+CONFIG_VIDEO_V4L2_COMMON=m
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-CONFIG_32BIT=y
-# CONFIG_64BIT is not set
-# CONFIG_8139TOO is not set
-CONFIG_ADM5120=y
-CONFIG_ADM5120_ENET=y
-CONFIG_ADM5120_MACH_BR_6104K=y
-CONFIG_ADM5120_MACH_BR_6104KP=y
-CONFIG_ADM5120_MACH_BR_61X4WG=y
-CONFIG_ADM5120_MACH_CAS_771=y
-CONFIG_ADM5120_MACH_EASY5120P_ATA=y
-CONFIG_ADM5120_MACH_EASY5120_RT=y
-CONFIG_ADM5120_MACH_EASY5120_WVOIP=y
-CONFIG_ADM5120_MACH_EASY83000=y
-CONFIG_ADM5120_MACH_NFS_101=y
-CONFIG_ADM5120_MACH_NP27G=y
-CONFIG_ADM5120_MACH_NP28G=y
-CONFIG_ADM5120_MACH_PMUGW=y
-CONFIG_ADM5120_MACH_RB_11X=y
-CONFIG_ADM5120_MACH_RB_133=y
-CONFIG_ADM5120_MACH_RB_133C=y
-CONFIG_ADM5120_MACH_RB_150=y
-CONFIG_ADM5120_MACH_RB_153=y
-CONFIG_ADM5120_MACH_RB_192=y
-CONFIG_ADM5120_MACH_WP54=y
-CONFIG_ADM5120_OEM_CELLVISION=y
-CONFIG_ADM5120_OEM_COMPEX=y
-CONFIG_ADM5120_OEM_EDIMAX=y
-CONFIG_ADM5120_OEM_INFINEON=y
-CONFIG_ADM5120_OEM_MIKROTIK=y
-CONFIG_ADM5120_OEM_MOTOROLA=y
-# CONFIG_ADM5120_OEM_ZYXEL is not set
-CONFIG_ADM5120_SOC_BGA=y
-CONFIG_ADM5120_WDT=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_ARCH_POPULATES_NODE_MAP=y
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-CONFIG_ARCH_SUPPORTS_OPROFILE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM_AMBA=y
-CONFIG_ATA=m
-# CONFIG_ATA_NONSTANDARD is not set
-# CONFIG_ATA_PIIX is not set
-CONFIG_ATA_SFF=y
-CONFIG_BASE_SMALL=0
-CONFIG_BAYCOM_SER_FDX=m
-CONFIG_BAYCOM_SER_HDX=m
-# CONFIG_BCM47XX is not set
-CONFIG_BINFMT_MISC=m
-CONFIG_BITREVERSE=y
-CONFIG_CEVT_R4K=y
-CONFIG_CIFS_DEBUG2=y
-CONFIG_CIFS_EXPERIMENTAL=y
-CONFIG_CIFS_STATS2=y
-CONFIG_CIFS_WEAK_PW_HASH=y
-CONFIG_CIFS_XATTR=y
-CONFIG_CLASSIC_RCU=y
-CONFIG_CMDLINE="console=ttyS0,115200 rootfstype=squashfs,yaffs2,jffs2 init=/etc/preinit"
-# CONFIG_CPU_BIG_ENDIAN is not set
-CONFIG_CPU_HAS_LLSC=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-# CONFIG_CPU_LOONGSON2 is not set
-CONFIG_CPU_MIPS32=y
-CONFIG_CPU_MIPS32_R1=y
-# CONFIG_CPU_MIPS32_R2 is not set
-# CONFIG_CPU_MIPS64_R1 is not set
-# CONFIG_CPU_MIPS64_R2 is not set
-CONFIG_CPU_MIPSR1=y
-# CONFIG_CPU_NEVADA is not set
-# CONFIG_CPU_R10000 is not set
-# CONFIG_CPU_R3000 is not set
-# CONFIG_CPU_R4300 is not set
-# CONFIG_CPU_R4X00 is not set
-# CONFIG_CPU_R5000 is not set
-# CONFIG_CPU_R5432 is not set
-# CONFIG_CPU_R6000 is not set
-# CONFIG_CPU_R8000 is not set
-# CONFIG_CPU_RM7000 is not set
-# CONFIG_CPU_RM9000 is not set
-# CONFIG_CPU_SB1 is not set
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-# CONFIG_CPU_TX39XX is not set
-# CONFIG_CPU_TX49XX is not set
-# CONFIG_CPU_VR41XX is not set
-CONFIG_CSRC_R4K=y
-CONFIG_DEVPORT=y
-# CONFIG_DM9000 is not set
-CONFIG_DMA_NEED_PCI_MAP_STATE=y
-CONFIG_DMA_NONCOHERENT=y
-# CONFIG_E1000E_ENABLED is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_ELF_CORE=y
-# CONFIG_EXT3_FS_POSIX_ACL is not set
-# CONFIG_EXT3_FS_SECURITY is not set
-CONFIG_EXT3_FS_XATTR=y
-CONFIG_FS_MBCACHE=m
-CONFIG_FS_POSIX_ACL=y
-CONFIG_GENERIC_ACL=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-# CONFIG_GENERIC_FIND_FIRST_BIT is not set
-CONFIG_GENERIC_FIND_NEXT_BIT=y
-CONFIG_GENERIC_GPIO=y
-# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
-CONFIG_GPIO_SYSFS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAVE_DMA_ATTRS is not set
-CONFIG_HAVE_GPIO_LIB=y
-CONFIG_HAVE_IDE=y
-# CONFIG_HAVE_KPROBES is not set
-# CONFIG_HAVE_KRETPROBES is not set
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HID=m
-CONFIG_HID_SUPPORT=y
-CONFIG_HW_HAS_PCI=y
-CONFIG_HW_RANDOM=y
-CONFIG_HZ=250
-# CONFIG_HZ_100 is not set
-CONFIG_HZ_250=y
-# CONFIG_I2C is not set
-# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_IBM_NEW_EMAC_RGMII is not set
-# CONFIG_IBM_NEW_EMAC_TAH is not set
-# CONFIG_IBM_NEW_EMAC_ZMII is not set
-# CONFIG_IDE is not set
-CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-CONFIG_INPUT=m
-# CONFIG_INPUT_EVDEV is not set
-CONFIG_IPV6_MIP6=m
-CONFIG_IPV6_NDISC_NODETYPE=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTE_INFO=y
-CONFIG_IPV6_TUNNEL=m
-CONFIG_IP_NF_TARGET_CLUSTERIP=m
-CONFIG_IRQ_CPU=y
-# CONFIG_IWLWIFI_LEDS is not set
-# CONFIG_JOLIET is not set
-CONFIG_KEXEC=y
-# CONFIG_LEDS_ALIX is not set
-CONFIG_LEDS_GPIO=m
-CONFIG_LEDS_TRIGGER_ADM5120_SWITCH=m
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-# CONFIG_LEMOTE_FULONG is not set
-# CONFIG_MACH_ALCHEMY is not set
-# CONFIG_MACH_DECSTATION is not set
-# CONFIG_MACH_JAZZ is not set
-# CONFIG_MACH_VR41XX is not set
-CONFIG_MII=m
-# CONFIG_MINIX_FS is not set
-CONFIG_MIPS=y
-# CONFIG_MIPS_ATLAS is not set
-# CONFIG_MIPS_COBALT is not set
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-# CONFIG_MIPS_MALTA is not set
-CONFIG_MIPS_MT_DISABLED=y
-# CONFIG_MIPS_MT_SMP is not set
-# CONFIG_MIPS_MT_SMTC is not set
-# CONFIG_MIPS_SEAD is not set
-# CONFIG_MIPS_SIM is not set
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MTD=y
-# CONFIG_MTD_ABSENT is not set
-CONFIG_MTD_ADM5120=y
-# CONFIG_MTD_ALAUDA is not set
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_MTD_BLOCK2MTD is not set
-CONFIG_MTD_CFI=y
-# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_CFI_FIXUP_MACRONIX_BOOTLOC=y
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-# CONFIG_MTD_CFI_INTELEXT is not set
-# CONFIG_MTD_CFI_STAA is not set
-CONFIG_MTD_CFI_UTIL=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-# CONFIG_MTD_CONCAT is not set
-# CONFIG_MTD_DEBUG is not set
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-CONFIG_MTD_GEN_PROBE=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MTDRAM is not set
-CONFIG_MTD_MYLOADER_PARTS=y
-CONFIG_MTD_NAND=y
-# CONFIG_MTD_NAND_CAFE is not set
-# CONFIG_MTD_NAND_DISKONCHIP is not set
-# CONFIG_MTD_NAND_ECC_SMC is not set
-CONFIG_MTD_NAND_IDS=y
-# CONFIG_MTD_NAND_MUSEUM_IDS is not set
-# CONFIG_MTD_NAND_NANDSIM is not set
-CONFIG_MTD_NAND_PLATFORM=y
-# CONFIG_MTD_NAND_VERIFY_WRITE is not set
-# CONFIG_MTD_ONENAND is not set
-CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_PCI is not set
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_PHYSMAP is not set
-# CONFIG_MTD_PLATRAM is not set
-# CONFIG_MTD_PMC551 is not set
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_SLRAM is not set
-CONFIG_MTD_TRXSPLIT=y
-# CONFIG_NATSEMI is not set
-# CONFIG_NE2K_PCI is not set
-# CONFIG_NETFILTER_XT_TARGET_TARPIT is not set
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_NET_VENDOR_3COM is not set
-# CONFIG_NO_IOPORT is not set
-# CONFIG_OCF_OCF is not set
-CONFIG_PAGEFLAGS_EXTENDED=y
-# CONFIG_PAGE_SIZE_16KB is not set
-CONFIG_PAGE_SIZE_4KB=y
-# CONFIG_PAGE_SIZE_64KB is not set
-# CONFIG_PAGE_SIZE_8KB is not set
-# CONFIG_PARTITION_ADVANCED is not set
-# CONFIG_PATA_PLATFORM is not set
-CONFIG_PATA_RB153_CF=m
-# CONFIG_PATA_SCH is not set
-CONFIG_PCI=y
-# CONFIG_PCIPCWATCHDOG is not set
-CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
-CONFIG_PCI_DOMAINS=y
-# CONFIG_PCSPKR_PLATFORM is not set
-# CONFIG_PMC_MSP is not set
-# CONFIG_PMC_YOSEMITE is not set
-# CONFIG_PNX8550_JBS is not set
-# CONFIG_PNX8550_STB810 is not set
-# CONFIG_R6040 is not set
-CONFIG_RFKILL_LEDS=y
-CONFIG_RTC_LIB=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
-CONFIG_SCSI_WAIT_SCAN=m
-# CONFIG_SERIAL_8250 is not set
-CONFIG_SERIAL_AMBA_PL010=y
-CONFIG_SERIAL_AMBA_PL010_CONSOLE=y
-CONFIG_SERIAL_AMBA_PL010_NUMPORTS=2
-CONFIG_SERIAL_AMBA_PL010_PORTNAME="ttyS"
-# CONFIG_SERIAL_AMBA_PL011 is not set
-CONFIG_SERIO=y
-# CONFIG_SERIO_AMBAKMI is not set
-# CONFIG_SERIO_I8042 is not set
-# CONFIG_SERIO_LIBPS2 is not set
-# CONFIG_SERIO_PCIPS2 is not set
-# CONFIG_SERIO_RAW is not set
-CONFIG_SERIO_SERPORT=y
-# CONFIG_SGI_IP22 is not set
-# CONFIG_SGI_IP27 is not set
-# CONFIG_SGI_IP28 is not set
-# CONFIG_SGI_IP32 is not set
-# CONFIG_SIBYTE_BIGSUR is not set
-# CONFIG_SIBYTE_CARMEL is not set
-# CONFIG_SIBYTE_CRHINE is not set
-# CONFIG_SIBYTE_CRHONE is not set
-# CONFIG_SIBYTE_LITTLESUR is not set
-# CONFIG_SIBYTE_RHONE is not set
-# CONFIG_SIBYTE_SENTOSA is not set
-# CONFIG_SIBYTE_SWARM is not set
-CONFIG_SOFT_WATCHDOG=m
-# CONFIG_SPARSEMEM_STATIC is not set
-# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
-CONFIG_SSB_POSSIBLE=y
-CONFIG_SYSVIPC_SYSCTL=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-# CONFIG_TC35815 is not set
-# CONFIG_THERMAL is not set
-# CONFIG_THERMAL_HWMON is not set
-CONFIG_TICK_ONESHOT=y
-CONFIG_TMPFS_POSIX_ACL=y
-# CONFIG_TOSHIBA_JMR3927 is not set
-# CONFIG_TOSHIBA_RBTX4927 is not set
-# CONFIG_TOSHIBA_RBTX4938 is not set
-CONFIG_TRAD_SIGNALS=y
-CONFIG_USB=m
-CONFIG_USB_ADM5120_HCD=m
-CONFIG_USB_EHCI_HCD=m
-# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
-# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
-CONFIG_USB_OHCI_HCD=m
-CONFIG_USB_SUPPORT=y
-# CONFIG_USB_UHCI_HCD is not set
-# CONFIG_VGASTATE is not set
-# CONFIG_VIA_RHINE is not set
-CONFIG_VIDEO_MEDIA=m
-CONFIG_VIDEO_V4L2=m
-CONFIG_VIDEO_V4L2_COMMON=m
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_YAFFS_9BYTE_TAGS=y
-# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
-CONFIG_YAFFS_AUTO_YAFFS2=y
-CONFIG_YAFFS_CHECKPOINT_RESERVED_BLOCKS=0
-# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
-# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
-CONFIG_YAFFS_FS=y
-CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
-CONFIG_YAFFS_YAFFS1=y
-CONFIG_YAFFS_YAFFS2=y
-CONFIG_ZONE_DMA_FLAG=0
--- /dev/null
+CONFIG_32BIT=y
+# CONFIG_64BIT is not set
+# CONFIG_8139TOO is not set
+CONFIG_ADM5120=y
+CONFIG_ADM5120_ENET=y
+CONFIG_ADM5120_MACH_BR_6104K=y
+CONFIG_ADM5120_MACH_BR_6104KP=y
+CONFIG_ADM5120_MACH_BR_61X4WG=y
+CONFIG_ADM5120_MACH_CAS_771=y
+CONFIG_ADM5120_MACH_EASY5120P_ATA=y
+CONFIG_ADM5120_MACH_EASY5120_RT=y
+CONFIG_ADM5120_MACH_EASY5120_WVOIP=y
+CONFIG_ADM5120_MACH_EASY83000=y
+CONFIG_ADM5120_MACH_NFS_101=y
+CONFIG_ADM5120_MACH_NP27G=y
+CONFIG_ADM5120_MACH_NP28G=y
+CONFIG_ADM5120_MACH_PMUGW=y
+CONFIG_ADM5120_MACH_RB_11X=y
+CONFIG_ADM5120_MACH_RB_133=y
+CONFIG_ADM5120_MACH_RB_133C=y
+CONFIG_ADM5120_MACH_RB_150=y
+CONFIG_ADM5120_MACH_RB_153=y
+CONFIG_ADM5120_MACH_RB_192=y
+CONFIG_ADM5120_MACH_WP54=y
+CONFIG_ADM5120_OEM_CELLVISION=y
+CONFIG_ADM5120_OEM_COMPEX=y
+CONFIG_ADM5120_OEM_EDIMAX=y
+CONFIG_ADM5120_OEM_INFINEON=y
+CONFIG_ADM5120_OEM_MIKROTIK=y
+CONFIG_ADM5120_OEM_MOTOROLA=y
+# CONFIG_ADM5120_OEM_ZYXEL is not set
+CONFIG_ADM5120_SOC_BGA=y
+CONFIG_ADM5120_WDT=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM_AMBA=y
+CONFIG_ATA=m
+# CONFIG_ATA_NONSTANDARD is not set
+# CONFIG_ATA_PIIX is not set
+CONFIG_ATA_SFF=y
+CONFIG_BASE_SMALL=0
+CONFIG_BAYCOM_SER_FDX=m
+CONFIG_BAYCOM_SER_HDX=m
+# CONFIG_BCM47XX is not set
+CONFIG_BINFMT_MISC=m
+CONFIG_BITREVERSE=y
+CONFIG_CEVT_R4K=y
+CONFIG_CIFS_DEBUG2=y
+CONFIG_CIFS_EXPERIMENTAL=y
+CONFIG_CIFS_STATS2=y
+CONFIG_CIFS_WEAK_PW_HASH=y
+CONFIG_CIFS_XATTR=y
+CONFIG_CLASSIC_RCU=y
+CONFIG_CMDLINE="console=ttyS0,115200 rootfstype=squashfs,yaffs2,jffs2 init=/etc/preinit"
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_HAS_LLSC=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+# CONFIG_CPU_LOONGSON2 is not set
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPS32_R1=y
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+CONFIG_CPU_MIPSR1=y
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_VR41XX is not set
+CONFIG_CSRC_R4K=y
+CONFIG_DEVPORT=y
+# CONFIG_DM9000 is not set
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_DMA_NONCOHERENT=y
+# CONFIG_E1000E_ENABLED is not set
+CONFIG_EARLY_PRINTK=y
+CONFIG_ELF_CORE=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_FS_MBCACHE=m
+CONFIG_FS_POSIX_ACL=y
+CONFIG_GENERIC_ACL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
+CONFIG_GPIO_SYSFS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+# CONFIG_HAVE_DMA_ATTRS is not set
+CONFIG_HAVE_GPIO_LIB=y
+CONFIG_HAVE_IDE=y
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HID=m
+CONFIG_HID_SUPPORT=y
+CONFIG_HW_HAS_PCI=y
+CONFIG_HW_RANDOM=y
+CONFIG_HZ=250
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_I2C is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IDE is not set
+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_INPUT=m
+# CONFIG_INPUT_EVDEV is not set
+CONFIG_IPV6_MIP6=m
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_IPV6_PRIVACY=y
+CONFIG_IPV6_ROUTE_INFO=y
+CONFIG_IPV6_TUNNEL=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
+CONFIG_IRQ_CPU=y
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_JOLIET is not set
+CONFIG_KEXEC=y
+# CONFIG_LEDS_ALIX is not set
+CONFIG_LEDS_GPIO=m
+CONFIG_LEDS_TRIGGER_ADM5120_SWITCH=m
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_LEMOTE_FULONG is not set
+# CONFIG_MACH_ALCHEMY is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_MACH_VR41XX is not set
+CONFIG_MII=m
+# CONFIG_MINIX_FS is not set
+CONFIG_MIPS=y
+# CONFIG_MIPS_ATLAS is not set
+# CONFIG_MIPS_COBALT is not set
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+# CONFIG_MIPS_MALTA is not set
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+# CONFIG_MIPS_SEAD is not set
+# CONFIG_MIPS_SIM is not set
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MTD=y
+# CONFIG_MTD_ABSENT is not set
+CONFIG_MTD_ADM5120=y
+# CONFIG_MTD_ALAUDA is not set
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_MTD_BLOCK2MTD is not set
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_FIXUP_MACRONIX_BOOTLOC=y
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_CONCAT is not set
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MTDRAM is not set
+CONFIG_MTD_MYLOADER_PARTS=y
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_CAFE is not set
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+CONFIG_MTD_NAND_PLATFORM=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_ONENAND is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_PCI is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_PLATRAM is not set
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_SLRAM is not set
+CONFIG_MTD_TRXSPLIT=y
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_NETFILTER_XT_TARGET_TARPIT is not set
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NO_IOPORT is not set
+# CONFIG_OCF_OCF is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+# CONFIG_PAGE_SIZE_16KB is not set
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_64KB is not set
+# CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PARTITION_ADVANCED is not set
+# CONFIG_PATA_PLATFORM is not set
+CONFIG_PATA_RB153_CF=m
+# CONFIG_PATA_SCH is not set
+CONFIG_PCI=y
+# CONFIG_PCIPCWATCHDOG is not set
+CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_PCSPKR_PLATFORM is not set
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_R6040 is not set
+CONFIG_RFKILL_LEDS=y
+CONFIG_RTC_LIB=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_SCSI_WAIT_SCAN=m
+# CONFIG_SERIAL_8250 is not set
+CONFIG_SERIAL_AMBA_PL010=y
+CONFIG_SERIAL_AMBA_PL010_CONSOLE=y
+CONFIG_SERIAL_AMBA_PL010_NUMPORTS=2
+CONFIG_SERIAL_AMBA_PL010_PORTNAME="ttyS"
+# CONFIG_SERIAL_AMBA_PL011 is not set
+CONFIG_SERIO=y
+# CONFIG_SERIO_AMBAKMI is not set
+# CONFIG_SERIO_I8042 is not set
+# CONFIG_SERIO_LIBPS2 is not set
+# CONFIG_SERIO_PCIPS2 is not set
+# CONFIG_SERIO_RAW is not set
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_SWARM is not set
+CONFIG_SOFT_WATCHDOG=m
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SSB_POSSIBLE=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+# CONFIG_TC35815 is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_TICK_ONESHOT=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_TOSHIBA_RBTX4927 is not set
+# CONFIG_TOSHIBA_RBTX4938 is not set
+CONFIG_TRAD_SIGNALS=y
+CONFIG_USB=m
+CONFIG_USB_ADM5120_HCD=m
+CONFIG_USB_EHCI_HCD=m
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_HCD=m
+CONFIG_USB_SUPPORT=y
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIA_RHINE is not set
+CONFIG_VIDEO_MEDIA=m
+CONFIG_VIDEO_V4L2=m
+CONFIG_VIDEO_V4L2_COMMON=m
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_YAFFS_9BYTE_TAGS=y
+# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
+CONFIG_YAFFS_AUTO_YAFFS2=y
+CONFIG_YAFFS_CHECKPOINT_RESERVED_BLOCKS=0
+# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
+# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
+CONFIG_YAFFS_FS=y
+CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
+CONFIG_YAFFS_YAFFS1=y
+CONFIG_YAFFS_YAFFS2=y
+CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-CONFIG_32BIT=y
-# CONFIG_64BIT is not set
-CONFIG_AR7=y
-CONFIG_AR7_GPIO=y
-CONFIG_AR7_WDT=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_ARCH_POPULATES_NODE_MAP=y
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-CONFIG_ARCH_SUPPORTS_OPROFILE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ATM_DRIVERS=y
-CONFIG_BASE_SMALL=0
-# CONFIG_BCM47XX is not set
-CONFIG_BITREVERSE=y
-CONFIG_BOOT_ELF32=y
-# CONFIG_BROADCOM_PHY is not set
-# CONFIG_BT is not set
-CONFIG_CEVT_R4K=y
-CONFIG_CLASSIC_RCU=y
-CONFIG_CMDLINE="init=/etc/preinit rootfstype=squashfs,jffs2,"
-CONFIG_CPMAC=y
-# CONFIG_CPU_BIG_ENDIAN is not set
-CONFIG_CPU_HAS_LLSC=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-# CONFIG_CPU_LOONGSON2 is not set
-CONFIG_CPU_MIPS32=y
-CONFIG_CPU_MIPS32_R1=y
-# CONFIG_CPU_MIPS32_R2 is not set
-# CONFIG_CPU_MIPS64_R1 is not set
-# CONFIG_CPU_MIPS64_R2 is not set
-CONFIG_CPU_MIPSR1=y
-# CONFIG_CPU_NEVADA is not set
-# CONFIG_CPU_R10000 is not set
-# CONFIG_CPU_R3000 is not set
-# CONFIG_CPU_R4300 is not set
-# CONFIG_CPU_R4X00 is not set
-# CONFIG_CPU_R5000 is not set
-# CONFIG_CPU_R5432 is not set
-# CONFIG_CPU_R6000 is not set
-# CONFIG_CPU_R8000 is not set
-# CONFIG_CPU_RM7000 is not set
-# CONFIG_CPU_RM9000 is not set
-# CONFIG_CPU_SB1 is not set
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-# CONFIG_CPU_TX39XX is not set
-# CONFIG_CPU_TX49XX is not set
-# CONFIG_CPU_VR41XX is not set
-CONFIG_CRYPTO_GF128MUL=m
-CONFIG_CSRC_R4K=y
-# CONFIG_DM9000 is not set
-CONFIG_DMA_NEED_PCI_MAP_STATE=y
-CONFIG_DMA_NONCOHERENT=y
-# CONFIG_E1000E_ENABLED is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_FIXED_PHY=y
-CONFIG_FS_POSIX_ACL=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-# CONFIG_GENERIC_FIND_FIRST_BIT is not set
-CONFIG_GENERIC_FIND_NEXT_BIT=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAVE_DMA_ATTRS is not set
-CONFIG_HAVE_IDE=y
-# CONFIG_HAVE_KPROBES is not set
-# CONFIG_HAVE_KRETPROBES is not set
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HW_RANDOM=y
-# CONFIG_I2C is not set
-# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_IBM_NEW_EMAC_RGMII is not set
-# CONFIG_IBM_NEW_EMAC_TAH is not set
-# CONFIG_IBM_NEW_EMAC_ZMII is not set
-# CONFIG_IDE is not set
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IPV6_NDISC_NODETYPE=y
-CONFIG_IRQ_CPU=y
-# CONFIG_ISDN is not set
-# CONFIG_IWLWIFI_LEDS is not set
-CONFIG_KALLSYMS=y
-# CONFIG_LEDS_ALIX is not set
-CONFIG_LEDS_GPIO=y
-# CONFIG_LEMOTE_FULONG is not set
-# CONFIG_MACH_ALCHEMY is not set
-# CONFIG_MACH_DECSTATION is not set
-# CONFIG_MACH_JAZZ is not set
-# CONFIG_MACH_VR41XX is not set
-# CONFIG_MDIO_BITBANG is not set
-CONFIG_MIPS=y
-# CONFIG_MIPS_ATLAS is not set
-# CONFIG_MIPS_COBALT is not set
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-# CONFIG_MIPS_MALTA is not set
-CONFIG_MIPS_MT_DISABLED=y
-# CONFIG_MIPS_MT_SMP is not set
-# CONFIG_MIPS_MT_SMTC is not set
-# CONFIG_MIPS_SEAD is not set
-# CONFIG_MIPS_SIM is not set
-CONFIG_MTD=y
-# CONFIG_MTD_ABSENT is not set
-CONFIG_MTD_AR7_PARTS=y
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_MTD_BLOCK2MTD is not set
-CONFIG_MTD_CFI=y
-# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_CFI_UTIL=y
-CONFIG_MTD_CHAR=y
-# CONFIG_MTD_CMDLINE_PARTS is not set
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-# CONFIG_MTD_CONCAT is not set
-# CONFIG_MTD_DEBUG is not set
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-CONFIG_MTD_GEN_PROBE=y
-# CONFIG_MTD_JEDECPROBE is not set
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_ONENAND is not set
-CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_PHRAM is not set
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_BANKWIDTH=2
-CONFIG_MTD_PHYSMAP_LEN=0
-CONFIG_MTD_PHYSMAP_START=0x10000000
-# CONFIG_MTD_PLATRAM is not set
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_SLRAM is not set
-CONFIG_NO_EXCEPT_FILL=y
-# CONFIG_NO_IOPORT is not set
-# CONFIG_OCF_OCF is not set
-CONFIG_PAGEFLAGS_EXTENDED=y
-# CONFIG_PAGE_SIZE_16KB is not set
-CONFIG_PAGE_SIZE_4KB=y
-# CONFIG_PAGE_SIZE_64KB is not set
-# CONFIG_PAGE_SIZE_8KB is not set
-# CONFIG_PCSPKR_PLATFORM is not set
-CONFIG_PHYLIB=y
-# CONFIG_PMC_MSP is not set
-# CONFIG_PMC_YOSEMITE is not set
-# CONFIG_PNX8550_JBS is not set
-# CONFIG_PNX8550_STB810 is not set
-# CONFIG_QSEMI_PHY is not set
-# CONFIG_REALTEK_PHY is not set
-CONFIG_RFKILL_LEDS=y
-CONFIG_RTC_LIB=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
-# CONFIG_SCSI is not set
-# CONFIG_SCSI_DMA is not set
-# CONFIG_SERIAL_8250_EXTENDED is not set
-# CONFIG_SGI_IP22 is not set
-# CONFIG_SGI_IP27 is not set
-# CONFIG_SGI_IP28 is not set
-# CONFIG_SGI_IP32 is not set
-# CONFIG_SIBYTE_BIGSUR is not set
-# CONFIG_SIBYTE_CARMEL is not set
-# CONFIG_SIBYTE_CRHINE is not set
-# CONFIG_SIBYTE_CRHONE is not set
-# CONFIG_SIBYTE_LITTLESUR is not set
-# CONFIG_SIBYTE_RHONE is not set
-# CONFIG_SIBYTE_SENTOSA is not set
-# CONFIG_SIBYTE_SWARM is not set
-# CONFIG_SMSC_PHY is not set
-# CONFIG_SOFT_WATCHDOG is not set
-# CONFIG_SOUND is not set
-# CONFIG_SPARSEMEM_STATIC is not set
-# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
-CONFIG_SSB_POSSIBLE=y
-CONFIG_SWAP_IO_SPACE=y
-CONFIG_SYSVIPC_SYSCTL=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
-CONFIG_SYS_SUPPORTS_KGDB=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-# CONFIG_THERMAL is not set
-# CONFIG_THERMAL_HWMON is not set
-CONFIG_TICK_ONESHOT=y
-# CONFIG_TOSHIBA_JMR3927 is not set
-# CONFIG_TOSHIBA_RBTX4927 is not set
-# CONFIG_TOSHIBA_RBTX4938 is not set
-CONFIG_TRAD_SIGNALS=y
-# CONFIG_VGASTATE is not set
-# CONFIG_VIDEO_DEV is not set
-# CONFIG_VIDEO_MEDIA is not set
-CONFIG_VLYNQ=y
-# CONFIG_W1 is not set
-CONFIG_ZONE_DMA_FLAG=0
--- /dev/null
+CONFIG_32BIT=y
+# CONFIG_64BIT is not set
+CONFIG_AR7=y
+CONFIG_AR7_GPIO=y
+CONFIG_AR7_WDT=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ATM_DRIVERS=y
+CONFIG_BASE_SMALL=0
+# CONFIG_BCM47XX is not set
+CONFIG_BITREVERSE=y
+CONFIG_BOOT_ELF32=y
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_BT is not set
+CONFIG_CEVT_R4K=y
+CONFIG_CLASSIC_RCU=y
+CONFIG_CMDLINE="init=/etc/preinit rootfstype=squashfs,jffs2,"
+CONFIG_CPMAC=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_HAS_LLSC=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+# CONFIG_CPU_LOONGSON2 is not set
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPS32_R1=y
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+CONFIG_CPU_MIPSR1=y
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_VR41XX is not set
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CSRC_R4K=y
+# CONFIG_DM9000 is not set
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_DMA_NONCOHERENT=y
+# CONFIG_E1000E_ENABLED is not set
+CONFIG_EARLY_PRINTK=y
+CONFIG_FIXED_PHY=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+# CONFIG_HAVE_DMA_ATTRS is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HW_RANDOM=y
+# CONFIG_I2C is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IDE is not set
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_IRQ_CPU=y
+# CONFIG_ISDN is not set
+# CONFIG_IWLWIFI_LEDS is not set
+CONFIG_KALLSYMS=y
+# CONFIG_LEDS_ALIX is not set
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEMOTE_FULONG is not set
+# CONFIG_MACH_ALCHEMY is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_MIPS=y
+# CONFIG_MIPS_ATLAS is not set
+# CONFIG_MIPS_COBALT is not set
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+# CONFIG_MIPS_MALTA is not set
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+# CONFIG_MIPS_SEAD is not set
+# CONFIG_MIPS_SIM is not set
+CONFIG_MTD=y
+# CONFIG_MTD_ABSENT is not set
+CONFIG_MTD_AR7_PARTS=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_MTD_BLOCK2MTD is not set
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_CHAR=y
+# CONFIG_MTD_CMDLINE_PARTS is not set
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_CONCAT is not set
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_ONENAND is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_PHRAM is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+CONFIG_MTD_PHYSMAP_LEN=0
+CONFIG_MTD_PHYSMAP_START=0x10000000
+# CONFIG_MTD_PLATRAM is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_SLRAM is not set
+CONFIG_NO_EXCEPT_FILL=y
+# CONFIG_NO_IOPORT is not set
+# CONFIG_OCF_OCF is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+# CONFIG_PAGE_SIZE_16KB is not set
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_64KB is not set
+# CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PCSPKR_PLATFORM is not set
+CONFIG_PHYLIB=y
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+CONFIG_RFKILL_LEDS=y
+CONFIG_RTC_LIB=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SERIAL_8250_EXTENDED is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_SOUND is not set
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SSB_POSSIBLE=y
+CONFIG_SWAP_IO_SPACE=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_SYS_SUPPORTS_KGDB=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_TICK_ONESHOT=y
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_TOSHIBA_RBTX4927 is not set
+# CONFIG_TOSHIBA_RBTX4938 is not set
+CONFIG_TRAD_SIGNALS=y
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_VIDEO_MEDIA is not set
+CONFIG_VLYNQ=y
+# CONFIG_W1 is not set
+CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -18,6 +18,23 @@
- prompt "System type"
- default SGI_IP22
-
-+config AR7
-+ bool "Texas Instruments AR7"
-+ select BOOT_ELF32
-+ select DMA_NONCOHERENT
-+ select CEVT_R4K
-+ select CSRC_R4K
-+ select IRQ_CPU
-+ select SWAP_IO_SPACE
-+ select SYS_HAS_CPU_MIPS32_R1
-+ select SYS_HAS_EARLY_PRINTK
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select SYS_SUPPORTS_KGDB
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
-+ select SYS_SUPPORTS_BIG_ENDIAN
-+ select GENERIC_GPIO
-+ select GENERIC_HARDIRQS_NO__DO_IRQ
-+
- config MACH_ALCHEMY
- bool "Alchemy processor based machines"
-
---- a/arch/mips/kernel/traps.c
-+++ b/arch/mips/kernel/traps.c
-@@ -1188,9 +1188,22 @@
-
- exception_handlers[n] = handler;
- if (n == 0 && cpu_has_divec) {
-- *(u32 *)(ebase + 0x200) = 0x08000000 |
-- (0x03ffffff & (handler >> 2));
-- flush_icache_range(ebase + 0x200, ebase + 0x204);
-+ if ((handler ^ (ebase + 4)) & 0xfc000000) {
-+ /* lui k0, 0x0000 */
-+ *(u32 *)(ebase + 0x200) = 0x3c1a0000 | (handler >> 16);
-+ /* ori k0, 0x0000 */
-+ *(u32 *)(ebase + 0x204) =
-+ 0x375a0000 | (handler & 0xffff);
-+ /* jr k0 */
-+ *(u32 *)(ebase + 0x208) = 0x03400008;
-+ /* nop */
-+ *(u32 *)(ebase + 0x20C) = 0x00000000;
-+ flush_icache_range(ebase + 0x200, ebase + 0x210);
-+ } else {
-+ *(u32 *)(ebase + 0x200) =
-+ 0x08000000 | (0x03ffffff & (handler >> 2));
-+ flush_icache_range(ebase + 0x200, ebase + 0x204);
-+ }
- }
- return (void *)old_handler;
- }
---- a/arch/mips/Makefile
-+++ b/arch/mips/Makefile
-@@ -167,6 +167,13 @@
- #
-
- #
-+# Texas Instruments AR7
-+#
-+core-$(CONFIG_AR7) += arch/mips/ar7/
-+cflags-$(CONFIG_AR7) += -Iinclude/asm-mips/ar7
-+load-$(CONFIG_AR7) += 0xffffffff94100000
-+
-+#
- # Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
- #
- core-$(CONFIG_MACH_JAZZ) += arch/mips/jazz/
---- a/include/asm-mips/page.h
-+++ b/include/asm-mips/page.h
-@@ -182,8 +182,10 @@
- #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
- VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
-
--#define UNCAC_ADDR(addr) ((addr) - PAGE_OFFSET + UNCAC_BASE)
--#define CAC_ADDR(addr) ((addr) - UNCAC_BASE + PAGE_OFFSET)
-+#define UNCAC_ADDR(addr) ((addr) - PAGE_OFFSET + UNCAC_BASE + \
-+ PHYS_OFFSET)
-+#define CAC_ADDR(addr) ((addr) - UNCAC_BASE + PAGE_OFFSET - \
-+ PHYS_OFFSET)
-
- #include <asm-generic/memory_model.h>
- #include <asm-generic/page.h>
+++ /dev/null
---- a/drivers/mtd/Kconfig
-+++ b/drivers/mtd/Kconfig
-@@ -174,6 +174,12 @@
- ---help---
- TI AR7 partitioning support
-
-+config MTD_AR7_PARTS
-+ tristate "TI AR7 partitioning support"
-+ depends on MTD_PARTITIONS
-+ ---help---
-+ TI AR7 partitioning support
-+
- comment "User Modules And Translation Layers"
-
- config MTD_CHAR
---- a/drivers/mtd/Makefile
-+++ b/drivers/mtd/Makefile
-@@ -13,6 +13,7 @@
- obj-$(CONFIG_MTD_AFS_PARTS) += afs.o
- obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o
- obj-$(CONFIG_MTD_OF_PARTS) += ofpart.o
-+obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o
-
- # 'Users' - code which presents functionality to userspace.
- obj-$(CONFIG_MTD_CHAR) += mtdchar.o
---- a/drivers/mtd/maps/physmap.c
-+++ b/drivers/mtd/maps/physmap.c
-@@ -87,7 +87,8 @@
-
- static const char *rom_probe_types[] = { "cfi_probe", "jedec_probe", "map_rom", NULL };
- #ifdef CONFIG_MTD_PARTITIONS
--static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", NULL };
-+static const char *part_probe_types[] = {"cmdlinepart", "RedBoot",
-+ "ar7part", NULL };
- #endif
-
- static int physmap_flash_probe(struct platform_device *dev)
+++ /dev/null
---- a/drivers/char/Kconfig
-+++ b/drivers/char/Kconfig
-@@ -960,6 +960,15 @@
- To compile this driver as a module, choose M here: the
- module will be called mwave.
-
-+config AR7_GPIO
-+ tristate "TI AR7 GPIO Support"
-+ depends on AR7
-+ help
-+ Give userspace access to the GPIO pins on the Texas Instruments AR7
-+ processors.
-+
-+ If compiled as a module, it will be called ar7_gpio.
-+
- config SCx200_GPIO
- tristate "NatSemi SCx200 GPIO Support"
- depends on SCx200
---- a/drivers/char/Makefile
-+++ b/drivers/char/Makefile
-@@ -91,6 +91,7 @@
- obj-$(CONFIG_PPDEV) += ppdev.o
- obj-$(CONFIG_NWBUTTON) += nwbutton.o
- obj-$(CONFIG_NWFLASH) += nwflash.o
-+obj-$(CONFIG_AR7_GPIO) += ar7_gpio.o
- obj-$(CONFIG_SCx200_GPIO) += scx200_gpio.o
- obj-$(CONFIG_PC8736x_GPIO) += pc8736x_gpio.o
- obj-$(CONFIG_NSC_GPIO) += nsc_gpio.o
+++ /dev/null
---- a/drivers/Kconfig
-+++ b/drivers/Kconfig
-@@ -100,5 +100,7 @@
-
- source "drivers/uio/Kconfig"
-
-+source "drivers/vlynq/Kconfig"
-+
- source "drivers/xen/Kconfig"
- endmenu
---- a/drivers/Makefile
-+++ b/drivers/Makefile
-@@ -92,5 +92,6 @@
- obj-$(CONFIG_HID) += hid/
- obj-$(CONFIG_PPC_PS3) += ps3/
- obj-$(CONFIG_OF) += of/
-+obj-$(CONFIG_VLYNQ) += vlynq/
- obj-$(CONFIG_SSB) += ssb/
- obj-$(CONFIG_VIRTIO) += virtio/
+++ /dev/null
---- a/drivers/net/Kconfig
-+++ b/drivers/net/Kconfig
-@@ -1867,7 +1867,7 @@
-
- config CPMAC
- tristate "TI AR7 CPMAC Ethernet support (EXPERIMENTAL)"
-- depends on NET_ETHERNET && EXPERIMENTAL && AR7 && BROKEN
-+ depends on NET_ETHERNET && EXPERIMENTAL && AR7
- select PHYLIB
- help
- TI AR7 CPMAC Ethernet support
+++ /dev/null
---- a/drivers/mtd/ar7part.c
-+++ b/drivers/mtd/ar7part.c
-@@ -34,6 +34,10 @@
- #define LOADER_MAGIC1 le32_to_cpu(0xfeedfa42)
- #define LOADER_MAGIC2 le32_to_cpu(0xfeed1281)
-
-+#ifndef SQUASHFS_MAGIC
-+#define SQUASHFS_MAGIC 0x73717368
-+#endif
-+
- struct ar7_bin_rec {
- unsigned int checksum;
- unsigned int length;
-@@ -47,7 +51,8 @@
- unsigned long origin)
- {
- struct ar7_bin_rec header;
-- unsigned int offset, len;
-+ unsigned int offset;
-+ size_t len;
- unsigned int pre_size = master->erasesize, post_size = 0;
- unsigned int root_offset = ROOT_OFFSET;
-
-@@ -66,7 +71,7 @@
- do { /* Try 10 blocks starting from master->erasesize */
- offset = pre_size;
- master->read(master, offset,
-- sizeof(header), &len, (u8 *)&header);
-+ sizeof(header), &len, (uint8_t *)&header);
- if (!strncmp((char *)&header, "TIENV0.8", 8))
- ar7_parts[1].offset = pre_size;
- if (header.checksum == LOADER_MAGIC1)
-@@ -88,7 +93,7 @@
- while (header.length) {
- offset += sizeof(header) + header.length;
- master->read(master, offset, sizeof(header),
-- &len, (u8 *)&header);
-+ &len, (uint8_t *)&header);
- }
- root_offset = offset + sizeof(header) + 4;
- break;
-@@ -96,10 +101,10 @@
- while (header.length) {
- offset += sizeof(header) + header.length;
- master->read(master, offset, sizeof(header),
-- &len, (u8 *)&header);
-+ &len, (uint8_t *)&header);
- }
- root_offset = offset + sizeof(header) + 4 + 0xff;
-- root_offset &= ~(u32)0xff;
-+ root_offset &= ~(uint32_t)0xff;
- break;
- default:
- printk(KERN_WARNING "Unknown magic: %08x\n", header.checksum);
+++ /dev/null
---- a/drivers/serial/8250.c
-+++ b/drivers/serial/8250.c
-@@ -266,6 +266,13 @@
- .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
- .flags = UART_CAP_FIFO,
- },
-+ [PORT_AR7] = {
-+ .name = "TI-AR7",
-+ .fifo_size = 16,
-+ .tx_loadsz = 16,
-+ .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
-+ .flags = UART_CAP_FIFO | UART_CAP_AFE,
-+ },
- };
-
- #if defined (CONFIG_SERIAL_8250_AU1X00)
-@@ -2524,7 +2531,11 @@
- {
- struct uart_8250_port *up = (struct uart_8250_port *)port;
-
-+#ifdef CONFIG_AR7
-+ wait_for_xmitr(up, BOTH_EMPTY);
-+#else
- wait_for_xmitr(up, UART_LSR_THRE);
-+#endif
- serial_out(up, UART_TX, ch);
- }
-
---- a/include/linux/serial_core.h
-+++ b/include/linux/serial_core.h
-@@ -40,7 +40,8 @@
- #define PORT_NS16550A 14
- #define PORT_XSCALE 15
- #define PORT_RM9000 16 /* PMC-Sierra RM9xxx internal UART */
--#define PORT_MAX_8250 16 /* max port ID */
-+#define PORT_AR7 17
-+#define PORT_MAX_8250 17 /* max port ID */
-
- /*
- * ARM specific type numbers. These are not currently guaranteed
+++ /dev/null
-This patch fixes the network driver cpmac.c for compilation with
-configuration option CONFIG_NETDEVICES_MULTIQUEUE.
-
-These compiler warnings are fixed by the patch:
-drivers/net/cpmac.c: In function 'cpmac_end_xmit':
-drivers/net/cpmac.c:630: warning: passing argument 2 of 'netif_subqueue_stopped' makes pointer from integer without a cast
-drivers/net/cpmac.c:641: warning: passing argument 2 of 'netif_subqueue_stopped' makes pointer from integer without a cast
-drivers/net/cpmac.c: In function 'cpmac_probe':
-drivers/net/cpmac.c:1128: warning: unused variable 'i'
-
-During runtime, the unpatched driver raises a fatal runtime exception.
-This is fixed by calling __netif_subqueue_stopped instead
-of netif_subqueue_stopped, too.
-
-Two additional code parts were modified for CONFIG_NETDEVICES_MULTIQUEUE
-because other drivers do it in the same way.
-
- Signed-off-by: Stefan Weil <weil@mail.berlios.de>
-
---- a/drivers/net/cpmac.c
-+++ b/drivers/net/cpmac.c
-@@ -627,7 +627,7 @@
- dev_kfree_skb_irq(desc->skb);
- desc->skb = NULL;
- #ifdef CONFIG_NETDEVICES_MULTIQUEUE
-- if (netif_subqueue_stopped(dev, queue))
-+ if (__netif_subqueue_stopped(dev, queue))
- netif_wake_subqueue(dev, queue);
- #else
- if (netif_queue_stopped(dev))
-@@ -638,7 +638,7 @@
- printk(KERN_WARNING
- "%s: end_xmit: spurious interrupt\n", dev->name);
- #ifdef CONFIG_NETDEVICES_MULTIQUEUE
-- if (netif_subqueue_stopped(dev, queue))
-+ if (__netif_subqueue_stopped(dev, queue))
- netif_wake_subqueue(dev, queue);
- #else
- if (netif_queue_stopped(dev))
-@@ -1124,7 +1124,7 @@
-
- static int __devinit cpmac_probe(struct platform_device *pdev)
- {
-- int rc, phy_id, i;
-+ int rc, phy_id;
- char *mdio_bus_id = "0";
- struct resource *mem;
- struct cpmac_priv *priv;
-@@ -1152,7 +1152,11 @@
- }
- }
-
-+#ifdef CONFIG_NETDEVICES_MULTIQUEUE
- dev = alloc_etherdev_mq(sizeof(*priv), CPMAC_QUEUES);
-+#else
-+ dev = alloc_etherdev(sizeof(*priv));
-+#endif
-
- if (!dev) {
- printk(KERN_ERR "cpmac: Unable to allocate net_device\n");
-@@ -1179,7 +1183,9 @@
- dev->set_multicast_list = cpmac_set_multicast_list;
- dev->tx_timeout = cpmac_tx_timeout;
- dev->ethtool_ops = &cpmac_ethtool_ops;
-+#ifdef CONFIG_NETDEVICES_MULTIQUEUE
- dev->features |= NETIF_F_MULTI_QUEUE;
-+#endif
-
- netif_napi_add(dev, &priv->napi, cpmac_poll, 64);
-
+++ /dev/null
---- a/drivers/net/cpmac.c
-+++ b/drivers/net/cpmac.c
-@@ -948,7 +948,8 @@
- int new_state = 0;
-
- spin_lock(&priv->lock);
-- if (priv->phy->link) {
-+ if (1 /* priv->phy->link */) {
-+ netif_carrier_on(dev);
- netif_start_queue(dev);
- if (priv->phy->duplex != priv->oldduplex) {
- new_state = 1;
-@@ -960,11 +961,11 @@
- priv->oldspeed = priv->phy->speed;
- }
-
-- if (!priv->oldlink) {
-+ /*if (!priv->oldlink) {
- new_state = 1;
-- priv->oldlink = 1;
-+ priv->oldlink = 1;*/
- netif_schedule(dev);
-- }
-+ /*}*/
- } else if (priv->oldlink) {
- netif_stop_queue(dev);
- new_state = 1;
--- /dev/null
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -18,6 +18,23 @@
+ prompt "System type"
+ default SGI_IP22
+
++config AR7
++ bool "Texas Instruments AR7"
++ select BOOT_ELF32
++ select DMA_NONCOHERENT
++ select CEVT_R4K
++ select CSRC_R4K
++ select IRQ_CPU
++ select SWAP_IO_SPACE
++ select SYS_HAS_CPU_MIPS32_R1
++ select SYS_HAS_EARLY_PRINTK
++ select SYS_SUPPORTS_32BIT_KERNEL
++ select SYS_SUPPORTS_KGDB
++ select SYS_SUPPORTS_LITTLE_ENDIAN
++ select SYS_SUPPORTS_BIG_ENDIAN
++ select GENERIC_GPIO
++ select GENERIC_HARDIRQS_NO__DO_IRQ
++
+ config MACH_ALCHEMY
+ bool "Alchemy processor based machines"
+
+--- a/arch/mips/kernel/traps.c
++++ b/arch/mips/kernel/traps.c
+@@ -1188,9 +1188,22 @@
+
+ exception_handlers[n] = handler;
+ if (n == 0 && cpu_has_divec) {
+- *(u32 *)(ebase + 0x200) = 0x08000000 |
+- (0x03ffffff & (handler >> 2));
+- flush_icache_range(ebase + 0x200, ebase + 0x204);
++ if ((handler ^ (ebase + 4)) & 0xfc000000) {
++ /* lui k0, 0x0000 */
++ *(u32 *)(ebase + 0x200) = 0x3c1a0000 | (handler >> 16);
++ /* ori k0, 0x0000 */
++ *(u32 *)(ebase + 0x204) =
++ 0x375a0000 | (handler & 0xffff);
++ /* jr k0 */
++ *(u32 *)(ebase + 0x208) = 0x03400008;
++ /* nop */
++ *(u32 *)(ebase + 0x20C) = 0x00000000;
++ flush_icache_range(ebase + 0x200, ebase + 0x210);
++ } else {
++ *(u32 *)(ebase + 0x200) =
++ 0x08000000 | (0x03ffffff & (handler >> 2));
++ flush_icache_range(ebase + 0x200, ebase + 0x204);
++ }
+ }
+ return (void *)old_handler;
+ }
+--- a/arch/mips/Makefile
++++ b/arch/mips/Makefile
+@@ -167,6 +167,13 @@
+ #
+
+ #
++# Texas Instruments AR7
++#
++core-$(CONFIG_AR7) += arch/mips/ar7/
++cflags-$(CONFIG_AR7) += -Iinclude/asm-mips/ar7
++load-$(CONFIG_AR7) += 0xffffffff94100000
++
++#
+ # Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
+ #
+ core-$(CONFIG_MACH_JAZZ) += arch/mips/jazz/
+--- a/include/asm-mips/page.h
++++ b/include/asm-mips/page.h
+@@ -182,8 +182,10 @@
+ #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
+ VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
+
+-#define UNCAC_ADDR(addr) ((addr) - PAGE_OFFSET + UNCAC_BASE)
+-#define CAC_ADDR(addr) ((addr) - UNCAC_BASE + PAGE_OFFSET)
++#define UNCAC_ADDR(addr) ((addr) - PAGE_OFFSET + UNCAC_BASE + \
++ PHYS_OFFSET)
++#define CAC_ADDR(addr) ((addr) - UNCAC_BASE + PAGE_OFFSET - \
++ PHYS_OFFSET)
+
+ #include <asm-generic/memory_model.h>
+ #include <asm-generic/page.h>
--- /dev/null
+--- a/drivers/mtd/Kconfig
++++ b/drivers/mtd/Kconfig
+@@ -174,6 +174,12 @@
+ ---help---
+ TI AR7 partitioning support
+
++config MTD_AR7_PARTS
++ tristate "TI AR7 partitioning support"
++ depends on MTD_PARTITIONS
++ ---help---
++ TI AR7 partitioning support
++
+ comment "User Modules And Translation Layers"
+
+ config MTD_CHAR
+--- a/drivers/mtd/Makefile
++++ b/drivers/mtd/Makefile
+@@ -13,6 +13,7 @@
+ obj-$(CONFIG_MTD_AFS_PARTS) += afs.o
+ obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o
+ obj-$(CONFIG_MTD_OF_PARTS) += ofpart.o
++obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o
+
+ # 'Users' - code which presents functionality to userspace.
+ obj-$(CONFIG_MTD_CHAR) += mtdchar.o
+--- a/drivers/mtd/maps/physmap.c
++++ b/drivers/mtd/maps/physmap.c
+@@ -87,7 +87,8 @@
+
+ static const char *rom_probe_types[] = { "cfi_probe", "jedec_probe", "map_rom", NULL };
+ #ifdef CONFIG_MTD_PARTITIONS
+-static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", NULL };
++static const char *part_probe_types[] = {"cmdlinepart", "RedBoot",
++ "ar7part", NULL };
+ #endif
+
+ static int physmap_flash_probe(struct platform_device *dev)
--- /dev/null
+--- a/drivers/char/Kconfig
++++ b/drivers/char/Kconfig
+@@ -960,6 +960,15 @@
+ To compile this driver as a module, choose M here: the
+ module will be called mwave.
+
++config AR7_GPIO
++ tristate "TI AR7 GPIO Support"
++ depends on AR7
++ help
++ Give userspace access to the GPIO pins on the Texas Instruments AR7
++ processors.
++
++ If compiled as a module, it will be called ar7_gpio.
++
+ config SCx200_GPIO
+ tristate "NatSemi SCx200 GPIO Support"
+ depends on SCx200
+--- a/drivers/char/Makefile
++++ b/drivers/char/Makefile
+@@ -91,6 +91,7 @@
+ obj-$(CONFIG_PPDEV) += ppdev.o
+ obj-$(CONFIG_NWBUTTON) += nwbutton.o
+ obj-$(CONFIG_NWFLASH) += nwflash.o
++obj-$(CONFIG_AR7_GPIO) += ar7_gpio.o
+ obj-$(CONFIG_SCx200_GPIO) += scx200_gpio.o
+ obj-$(CONFIG_PC8736x_GPIO) += pc8736x_gpio.o
+ obj-$(CONFIG_NSC_GPIO) += nsc_gpio.o
--- /dev/null
+--- a/drivers/Kconfig
++++ b/drivers/Kconfig
+@@ -100,5 +100,7 @@
+
+ source "drivers/uio/Kconfig"
+
++source "drivers/vlynq/Kconfig"
++
+ source "drivers/xen/Kconfig"
+ endmenu
+--- a/drivers/Makefile
++++ b/drivers/Makefile
+@@ -92,5 +92,6 @@
+ obj-$(CONFIG_HID) += hid/
+ obj-$(CONFIG_PPC_PS3) += ps3/
+ obj-$(CONFIG_OF) += of/
++obj-$(CONFIG_VLYNQ) += vlynq/
+ obj-$(CONFIG_SSB) += ssb/
+ obj-$(CONFIG_VIRTIO) += virtio/
--- /dev/null
+--- a/drivers/net/Kconfig
++++ b/drivers/net/Kconfig
+@@ -1867,7 +1867,7 @@
+
+ config CPMAC
+ tristate "TI AR7 CPMAC Ethernet support (EXPERIMENTAL)"
+- depends on NET_ETHERNET && EXPERIMENTAL && AR7 && BROKEN
++ depends on NET_ETHERNET && EXPERIMENTAL && AR7
+ select PHYLIB
+ help
+ TI AR7 CPMAC Ethernet support
--- /dev/null
+--- a/drivers/mtd/ar7part.c
++++ b/drivers/mtd/ar7part.c
+@@ -34,6 +34,10 @@
+ #define LOADER_MAGIC1 le32_to_cpu(0xfeedfa42)
+ #define LOADER_MAGIC2 le32_to_cpu(0xfeed1281)
+
++#ifndef SQUASHFS_MAGIC
++#define SQUASHFS_MAGIC 0x73717368
++#endif
++
+ struct ar7_bin_rec {
+ unsigned int checksum;
+ unsigned int length;
+@@ -47,7 +51,8 @@
+ unsigned long origin)
+ {
+ struct ar7_bin_rec header;
+- unsigned int offset, len;
++ unsigned int offset;
++ size_t len;
+ unsigned int pre_size = master->erasesize, post_size = 0;
+ unsigned int root_offset = ROOT_OFFSET;
+
+@@ -66,7 +71,7 @@
+ do { /* Try 10 blocks starting from master->erasesize */
+ offset = pre_size;
+ master->read(master, offset,
+- sizeof(header), &len, (u8 *)&header);
++ sizeof(header), &len, (uint8_t *)&header);
+ if (!strncmp((char *)&header, "TIENV0.8", 8))
+ ar7_parts[1].offset = pre_size;
+ if (header.checksum == LOADER_MAGIC1)
+@@ -88,7 +93,7 @@
+ while (header.length) {
+ offset += sizeof(header) + header.length;
+ master->read(master, offset, sizeof(header),
+- &len, (u8 *)&header);
++ &len, (uint8_t *)&header);
+ }
+ root_offset = offset + sizeof(header) + 4;
+ break;
+@@ -96,10 +101,10 @@
+ while (header.length) {
+ offset += sizeof(header) + header.length;
+ master->read(master, offset, sizeof(header),
+- &len, (u8 *)&header);
++ &len, (uint8_t *)&header);
+ }
+ root_offset = offset + sizeof(header) + 4 + 0xff;
+- root_offset &= ~(u32)0xff;
++ root_offset &= ~(uint32_t)0xff;
+ break;
+ default:
+ printk(KERN_WARNING "Unknown magic: %08x\n", header.checksum);
--- /dev/null
+--- a/drivers/serial/8250.c
++++ b/drivers/serial/8250.c
+@@ -266,6 +266,13 @@
+ .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
+ .flags = UART_CAP_FIFO,
+ },
++ [PORT_AR7] = {
++ .name = "TI-AR7",
++ .fifo_size = 16,
++ .tx_loadsz = 16,
++ .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
++ .flags = UART_CAP_FIFO | UART_CAP_AFE,
++ },
+ };
+
+ #if defined (CONFIG_SERIAL_8250_AU1X00)
+@@ -2524,7 +2531,11 @@
+ {
+ struct uart_8250_port *up = (struct uart_8250_port *)port;
+
++#ifdef CONFIG_AR7
++ wait_for_xmitr(up, BOTH_EMPTY);
++#else
+ wait_for_xmitr(up, UART_LSR_THRE);
++#endif
+ serial_out(up, UART_TX, ch);
+ }
+
+--- a/include/linux/serial_core.h
++++ b/include/linux/serial_core.h
+@@ -40,7 +40,8 @@
+ #define PORT_NS16550A 14
+ #define PORT_XSCALE 15
+ #define PORT_RM9000 16 /* PMC-Sierra RM9xxx internal UART */
+-#define PORT_MAX_8250 16 /* max port ID */
++#define PORT_AR7 17
++#define PORT_MAX_8250 17 /* max port ID */
+
+ /*
+ * ARM specific type numbers. These are not currently guaranteed
--- /dev/null
+This patch fixes the network driver cpmac.c for compilation with
+configuration option CONFIG_NETDEVICES_MULTIQUEUE.
+
+These compiler warnings are fixed by the patch:
+drivers/net/cpmac.c: In function 'cpmac_end_xmit':
+drivers/net/cpmac.c:630: warning: passing argument 2 of 'netif_subqueue_stopped' makes pointer from integer without a cast
+drivers/net/cpmac.c:641: warning: passing argument 2 of 'netif_subqueue_stopped' makes pointer from integer without a cast
+drivers/net/cpmac.c: In function 'cpmac_probe':
+drivers/net/cpmac.c:1128: warning: unused variable 'i'
+
+During runtime, the unpatched driver raises a fatal runtime exception.
+This is fixed by calling __netif_subqueue_stopped instead
+of netif_subqueue_stopped, too.
+
+Two additional code parts were modified for CONFIG_NETDEVICES_MULTIQUEUE
+because other drivers do it in the same way.
+
+ Signed-off-by: Stefan Weil <weil@mail.berlios.de>
+
+--- a/drivers/net/cpmac.c
++++ b/drivers/net/cpmac.c
+@@ -627,7 +627,7 @@
+ dev_kfree_skb_irq(desc->skb);
+ desc->skb = NULL;
+ #ifdef CONFIG_NETDEVICES_MULTIQUEUE
+- if (netif_subqueue_stopped(dev, queue))
++ if (__netif_subqueue_stopped(dev, queue))
+ netif_wake_subqueue(dev, queue);
+ #else
+ if (netif_queue_stopped(dev))
+@@ -638,7 +638,7 @@
+ printk(KERN_WARNING
+ "%s: end_xmit: spurious interrupt\n", dev->name);
+ #ifdef CONFIG_NETDEVICES_MULTIQUEUE
+- if (netif_subqueue_stopped(dev, queue))
++ if (__netif_subqueue_stopped(dev, queue))
+ netif_wake_subqueue(dev, queue);
+ #else
+ if (netif_queue_stopped(dev))
+@@ -1124,7 +1124,7 @@
+
+ static int __devinit cpmac_probe(struct platform_device *pdev)
+ {
+- int rc, phy_id, i;
++ int rc, phy_id;
+ char *mdio_bus_id = "0";
+ struct resource *mem;
+ struct cpmac_priv *priv;
+@@ -1152,7 +1152,11 @@
+ }
+ }
+
++#ifdef CONFIG_NETDEVICES_MULTIQUEUE
+ dev = alloc_etherdev_mq(sizeof(*priv), CPMAC_QUEUES);
++#else
++ dev = alloc_etherdev(sizeof(*priv));
++#endif
+
+ if (!dev) {
+ printk(KERN_ERR "cpmac: Unable to allocate net_device\n");
+@@ -1179,7 +1183,9 @@
+ dev->set_multicast_list = cpmac_set_multicast_list;
+ dev->tx_timeout = cpmac_tx_timeout;
+ dev->ethtool_ops = &cpmac_ethtool_ops;
++#ifdef CONFIG_NETDEVICES_MULTIQUEUE
+ dev->features |= NETIF_F_MULTI_QUEUE;
++#endif
+
+ netif_napi_add(dev, &priv->napi, cpmac_poll, 64);
+
--- /dev/null
+--- a/drivers/net/cpmac.c
++++ b/drivers/net/cpmac.c
+@@ -948,7 +948,8 @@
+ int new_state = 0;
+
+ spin_lock(&priv->lock);
+- if (priv->phy->link) {
++ if (1 /* priv->phy->link */) {
++ netif_carrier_on(dev);
+ netif_start_queue(dev);
+ if (priv->phy->duplex != priv->oldduplex) {
+ new_state = 1;
+@@ -960,11 +961,11 @@
+ priv->oldspeed = priv->phy->speed;
+ }
+
+- if (!priv->oldlink) {
++ /*if (!priv->oldlink) {
+ new_state = 1;
+- priv->oldlink = 1;
++ priv->oldlink = 1;*/
+ netif_schedule(dev);
+- }
++ /*}*/
+ } else if (priv->oldlink) {
+ netif_stop_queue(dev);
+ new_state = 1;
+++ /dev/null
-CONFIG_32BIT=y
-# CONFIG_64BIT is not set
-# CONFIG_8139TOO is not set
-CONFIG_ADM6996_PHY=y
-CONFIG_AG71XX=y
-# CONFIG_AR71XX_EARLY_SERIAL is not set
-CONFIG_AR71XX_MACH_GENERIC=y
-CONFIG_AR71XX_MACH_RB_4XX=y
-CONFIG_AR71XX_MACH_WP543=y
-CONFIG_AR71XX_WDT=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_ARCH_POPULATES_NODE_MAP=y
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-CONFIG_ARCH_SUPPORTS_OPROFILE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ATHEROS_AR71XX=y
-CONFIG_BASE_SMALL=0
-# CONFIG_BCM47XX is not set
-CONFIG_BITREVERSE=y
-# CONFIG_BROADCOM_PHY is not set
-CONFIG_CEVT_R4K=y
-CONFIG_CLASSIC_RCU=y
-CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=squashfs,yaffs,jffs2 noinitrd console=ttyS0,115200 init=/etc/preinit"
-CONFIG_CPU_BIG_ENDIAN=y
-CONFIG_CPU_HAS_LLSC=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_SYNC=y
-# CONFIG_CPU_LITTLE_ENDIAN is not set
-# CONFIG_CPU_LOONGSON2 is not set
-CONFIG_CPU_MIPS32=y
-# CONFIG_CPU_MIPS32_R1 is not set
-CONFIG_CPU_MIPS32_R2=y
-# CONFIG_CPU_MIPS64_R1 is not set
-# CONFIG_CPU_MIPS64_R2 is not set
-CONFIG_CPU_MIPSR2=y
-# CONFIG_CPU_NEVADA is not set
-# CONFIG_CPU_R10000 is not set
-# CONFIG_CPU_R3000 is not set
-# CONFIG_CPU_R4300 is not set
-# CONFIG_CPU_R4X00 is not set
-# CONFIG_CPU_R5000 is not set
-# CONFIG_CPU_R5432 is not set
-# CONFIG_CPU_R6000 is not set
-# CONFIG_CPU_R8000 is not set
-# CONFIG_CPU_RM7000 is not set
-# CONFIG_CPU_RM9000 is not set
-# CONFIG_CPU_SB1 is not set
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-# CONFIG_CPU_TX39XX is not set
-# CONFIG_CPU_TX49XX is not set
-# CONFIG_CPU_VR41XX is not set
-CONFIG_CSRC_R4K=y
-CONFIG_DEVPORT=y
-# CONFIG_DM9000 is not set
-CONFIG_DMA_NEED_PCI_MAP_STATE=y
-CONFIG_DMA_NONCOHERENT=y
-# CONFIG_E1000E_ENABLED is not set
-CONFIG_EARLY_PRINTK=y
-# CONFIG_FIXED_PHY is not set
-CONFIG_FS_POSIX_ACL=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-# CONFIG_GENERIC_FIND_FIRST_BIT is not set
-CONFIG_GENERIC_FIND_NEXT_BIT=y
-CONFIG_GENERIC_GPIO=y
-# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
-CONFIG_GPIO_SYSFS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAVE_DMA_ATTRS is not set
-CONFIG_HAVE_GPIO_LIB=y
-CONFIG_HAVE_IDE=y
-# CONFIG_HAVE_KPROBES is not set
-# CONFIG_HAVE_KRETPROBES is not set
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HW_HAS_PCI=y
-CONFIG_HW_RANDOM=m
-# CONFIG_I2C is not set
-# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_IBM_NEW_EMAC_RGMII is not set
-# CONFIG_IBM_NEW_EMAC_TAH is not set
-# CONFIG_IBM_NEW_EMAC_ZMII is not set
-CONFIG_ICPLUS_PHY=y
-# CONFIG_IDE is not set
-CONFIG_INITRAMFS_ROOT_GID=0
-CONFIG_INITRAMFS_ROOT_UID=0
-CONFIG_INITRAMFS_SOURCE="../../root"
-CONFIG_IPV6_NDISC_NODETYPE=y
-CONFIG_IRQ_CPU=y
-# CONFIG_IWLWIFI_LEDS is not set
-# CONFIG_LEDS_ALIX is not set
-CONFIG_LEDS_GPIO=y
-# CONFIG_LEMOTE_FULONG is not set
-# CONFIG_M25PXX_USE_FAST_READ is not set
-# CONFIG_MACH_ALCHEMY is not set
-# CONFIG_MACH_DECSTATION is not set
-# CONFIG_MACH_JAZZ is not set
-# CONFIG_MACH_VR41XX is not set
-# CONFIG_MDIO_BITBANG is not set
-CONFIG_MICREL_PHY=y
-CONFIG_MIPS=y
-# CONFIG_MIPS_ATLAS is not set
-# CONFIG_MIPS_COBALT is not set
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-CONFIG_MIPS_MACHINE=y
-# CONFIG_MIPS_MALTA is not set
-CONFIG_MIPS_MT_DISABLED=y
-# CONFIG_MIPS_MT_SMP is not set
-# CONFIG_MIPS_MT_SMTC is not set
-# CONFIG_MIPS_SEAD is not set
-# CONFIG_MIPS_SIM is not set
-CONFIG_MTD=y
-# CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_ALAUDA is not set
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_MTD_BLOCK2MTD is not set
-# CONFIG_MTD_CFI is not set
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-CONFIG_MTD_CHAR=y
-# CONFIG_MTD_CMDLINE_PARTS is not set
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-CONFIG_MTD_CONCAT=y
-# CONFIG_MTD_DEBUG is not set
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-# CONFIG_MTD_JEDECPROBE is not set
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MTDRAM is not set
-CONFIG_MTD_NAND=y
-# CONFIG_MTD_NAND_CAFE is not set
-# CONFIG_MTD_NAND_DISKONCHIP is not set
-# CONFIG_MTD_NAND_ECC_SMC is not set
-CONFIG_MTD_NAND_IDS=y
-# CONFIG_MTD_NAND_MUSEUM_IDS is not set
-# CONFIG_MTD_NAND_NANDSIM is not set
-# CONFIG_MTD_NAND_PLATFORM is not set
-CONFIG_MTD_NAND_RB4XX=y
-# CONFIG_MTD_NAND_VERIFY_WRITE is not set
-# CONFIG_MTD_ONENAND is not set
-CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_PLATRAM is not set
-# CONFIG_MTD_PMC551 is not set
-# CONFIG_MTD_RAM is not set
-CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-2
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_REDBOOT_PARTS_READONLY=y
-CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_SLRAM is not set
-CONFIG_MYLOADER=y
-# CONFIG_NATSEMI is not set
-# CONFIG_NE2K_PCI is not set
-# CONFIG_NET_VENDOR_3COM is not set
-# CONFIG_NO_IOPORT is not set
-# CONFIG_OCF_OCF is not set
-CONFIG_PAGEFLAGS_EXTENDED=y
-# CONFIG_PAGE_SIZE_16KB is not set
-CONFIG_PAGE_SIZE_4KB=y
-# CONFIG_PAGE_SIZE_64KB is not set
-# CONFIG_PAGE_SIZE_8KB is not set
-CONFIG_PCI=y
-# CONFIG_PCIPCWATCHDOG is not set
-CONFIG_PCI_DOMAINS=y
-# CONFIG_PCSPKR_PLATFORM is not set
-CONFIG_PHYLIB=y
-# CONFIG_PMC_MSP is not set
-# CONFIG_PMC_YOSEMITE is not set
-# CONFIG_PNX8550_JBS is not set
-# CONFIG_PNX8550_STB810 is not set
-# CONFIG_QSEMI_PHY is not set
-# CONFIG_R6040 is not set
-# CONFIG_REALTEK_PHY is not set
-CONFIG_RFKILL_LEDS=y
-CONFIG_RTC_LIB=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
-CONFIG_SCSI_WAIT_SCAN=m
-# CONFIG_SERIAL_8250_EXTENDED is not set
-CONFIG_SERIAL_8250_NR_UARTS=1
-CONFIG_SERIAL_8250_RUNTIME_UARTS=1
-# CONFIG_SGI_IP22 is not set
-# CONFIG_SGI_IP27 is not set
-# CONFIG_SGI_IP28 is not set
-# CONFIG_SGI_IP32 is not set
-# CONFIG_SIBYTE_BIGSUR is not set
-# CONFIG_SIBYTE_CARMEL is not set
-# CONFIG_SIBYTE_CRHINE is not set
-# CONFIG_SIBYTE_CRHONE is not set
-# CONFIG_SIBYTE_LITTLESUR is not set
-# CONFIG_SIBYTE_RHONE is not set
-# CONFIG_SIBYTE_SENTOSA is not set
-# CONFIG_SIBYTE_SWARM is not set
-# CONFIG_SMSC_PHY is not set
-# CONFIG_SOFT_WATCHDOG is not set
-# CONFIG_SPARSEMEM_STATIC is not set
-# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
-CONFIG_SPI=y
-CONFIG_SPI_AR71XX=y
-CONFIG_SPI_BITBANG=y
-# CONFIG_SPI_GPIO is not set
-CONFIG_SPI_MASTER=y
-# CONFIG_SPI_SPIDEV is not set
-CONFIG_SSB_POSSIBLE=y
-CONFIG_SYSVIPC_SYSCTL=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
-# CONFIG_TC35815 is not set
-# CONFIG_THERMAL is not set
-# CONFIG_THERMAL_HWMON is not set
-CONFIG_TICK_ONESHOT=y
-# CONFIG_TOSHIBA_JMR3927 is not set
-# CONFIG_TOSHIBA_RBTX4927 is not set
-# CONFIG_TOSHIBA_RBTX4938 is not set
-CONFIG_TRAD_SIGNALS=y
-CONFIG_USB=m
-CONFIG_USB_EHCI_AR71XX=y
-CONFIG_USB_EHCI_HCD=m
-CONFIG_USB_OHCI_AR71XX=y
-# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
-# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
-CONFIG_USB_OHCI_HCD=m
-CONFIG_USB_SUPPORT=y
-# CONFIG_USB_UHCI_HCD is not set
-# CONFIG_VGASTATE is not set
-# CONFIG_VIA_RHINE is not set
-CONFIG_VIDEO_MEDIA=m
-CONFIG_VIDEO_V4L2=m
-CONFIG_VIDEO_V4L2_COMMON=m
-CONFIG_YAFFS_9BYTE_TAGS=y
-CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED=y
-CONFIG_YAFFS_AUTO_YAFFS2=y
-CONFIG_YAFFS_CHECKPOINT_RESERVED_BLOCKS=0
-# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
-# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
-CONFIG_YAFFS_FS=y
-CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
-CONFIG_YAFFS_YAFFS1=y
-CONFIG_YAFFS_YAFFS2=y
-CONFIG_ZONE_DMA_FLAG=0
--- /dev/null
+CONFIG_32BIT=y
+# CONFIG_64BIT is not set
+# CONFIG_8139TOO is not set
+CONFIG_ADM6996_PHY=y
+CONFIG_AG71XX=y
+# CONFIG_AR71XX_EARLY_SERIAL is not set
+CONFIG_AR71XX_MACH_GENERIC=y
+CONFIG_AR71XX_MACH_RB_4XX=y
+CONFIG_AR71XX_MACH_WP543=y
+CONFIG_AR71XX_WDT=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ATHEROS_AR71XX=y
+CONFIG_BASE_SMALL=0
+# CONFIG_BCM47XX is not set
+CONFIG_BITREVERSE=y
+# CONFIG_BROADCOM_PHY is not set
+CONFIG_CEVT_R4K=y
+CONFIG_CLASSIC_RCU=y
+CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=squashfs,yaffs,jffs2 noinitrd console=ttyS0,115200 init=/etc/preinit"
+CONFIG_CPU_BIG_ENDIAN=y
+CONFIG_CPU_HAS_LLSC=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_SYNC=y
+# CONFIG_CPU_LITTLE_ENDIAN is not set
+# CONFIG_CPU_LOONGSON2 is not set
+CONFIG_CPU_MIPS32=y
+# CONFIG_CPU_MIPS32_R1 is not set
+CONFIG_CPU_MIPS32_R2=y
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+CONFIG_CPU_MIPSR2=y
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_VR41XX is not set
+CONFIG_CSRC_R4K=y
+CONFIG_DEVPORT=y
+# CONFIG_DM9000 is not set
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_DMA_NONCOHERENT=y
+# CONFIG_E1000E_ENABLED is not set
+CONFIG_EARLY_PRINTK=y
+# CONFIG_FIXED_PHY is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
+CONFIG_GPIO_SYSFS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+# CONFIG_HAVE_DMA_ATTRS is not set
+CONFIG_HAVE_GPIO_LIB=y
+CONFIG_HAVE_IDE=y
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HW_HAS_PCI=y
+CONFIG_HW_RANDOM=m
+# CONFIG_I2C is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+CONFIG_ICPLUS_PHY=y
+# CONFIG_IDE is not set
+CONFIG_INITRAMFS_ROOT_GID=0
+CONFIG_INITRAMFS_ROOT_UID=0
+CONFIG_INITRAMFS_SOURCE="../../root"
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_IRQ_CPU=y
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_LEDS_ALIX is not set
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEMOTE_FULONG is not set
+# CONFIG_M25PXX_USE_FAST_READ is not set
+# CONFIG_MACH_ALCHEMY is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_MICREL_PHY=y
+CONFIG_MIPS=y
+# CONFIG_MIPS_ATLAS is not set
+# CONFIG_MIPS_COBALT is not set
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+CONFIG_MIPS_MACHINE=y
+# CONFIG_MIPS_MALTA is not set
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+# CONFIG_MIPS_SEAD is not set
+# CONFIG_MIPS_SIM is not set
+CONFIG_MTD=y
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_ALAUDA is not set
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_MTD_BLOCK2MTD is not set
+# CONFIG_MTD_CFI is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CHAR=y
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_CONCAT=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MTDRAM is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_CAFE is not set
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+CONFIG_MTD_NAND_RB4XX=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_ONENAND is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_PLATRAM is not set
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_RAM is not set
+CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-2
+CONFIG_MTD_REDBOOT_PARTS=y
+CONFIG_MTD_REDBOOT_PARTS_READONLY=y
+CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_SLRAM is not set
+CONFIG_MYLOADER=y
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NO_IOPORT is not set
+# CONFIG_OCF_OCF is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+# CONFIG_PAGE_SIZE_16KB is not set
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_64KB is not set
+# CONFIG_PAGE_SIZE_8KB is not set
+CONFIG_PCI=y
+# CONFIG_PCIPCWATCHDOG is not set
+CONFIG_PCI_DOMAINS=y
+# CONFIG_PCSPKR_PLATFORM is not set
+CONFIG_PHYLIB=y
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_R6040 is not set
+# CONFIG_REALTEK_PHY is not set
+CONFIG_RFKILL_LEDS=y
+CONFIG_RTC_LIB=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_SCSI_WAIT_SCAN=m
+# CONFIG_SERIAL_8250_EXTENDED is not set
+CONFIG_SERIAL_8250_NR_UARTS=1
+CONFIG_SERIAL_8250_RUNTIME_UARTS=1
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPI=y
+CONFIG_SPI_AR71XX=y
+CONFIG_SPI_BITBANG=y
+# CONFIG_SPI_GPIO is not set
+CONFIG_SPI_MASTER=y
+# CONFIG_SPI_SPIDEV is not set
+CONFIG_SSB_POSSIBLE=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+# CONFIG_TC35815 is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_TICK_ONESHOT=y
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_TOSHIBA_RBTX4927 is not set
+# CONFIG_TOSHIBA_RBTX4938 is not set
+CONFIG_TRAD_SIGNALS=y
+CONFIG_USB=m
+CONFIG_USB_EHCI_AR71XX=y
+CONFIG_USB_EHCI_HCD=m
+CONFIG_USB_OHCI_AR71XX=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_HCD=m
+CONFIG_USB_SUPPORT=y
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIA_RHINE is not set
+CONFIG_VIDEO_MEDIA=m
+CONFIG_VIDEO_V4L2=m
+CONFIG_VIDEO_V4L2_COMMON=m
+CONFIG_YAFFS_9BYTE_TAGS=y
+CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED=y
+CONFIG_YAFFS_AUTO_YAFFS2=y
+CONFIG_YAFFS_CHECKPOINT_RESERVED_BLOCKS=0
+# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
+# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
+CONFIG_YAFFS_FS=y
+CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
+CONFIG_YAFFS_YAFFS1=y
+CONFIG_YAFFS_YAFFS2=y
+CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
---- a/arch/mips/Makefile
-+++ b/arch/mips/Makefile
-@@ -597,6 +597,13 @@
- cflags-$(CONFIG_TOSHIBA_RBTX4938) += -Iinclude/asm-mips/mach-tx49xx
- load-$(CONFIG_TOSHIBA_RBTX4938) += 0xffffffff80100000
-
-+#
-+# Atheros AR71xx
-+#
-+core-$(CONFIG_ATHEROS_AR71XX) += arch/mips/ar71xx/
-+cflags-$(CONFIG_ATHEROS_AR71XX) += -Iinclude/asm-mips/mach-ar71xx
-+load-$(CONFIG_ATHEROS_AR71XX) += 0xffffffff80060000
-+
- # temporary until string.h is fixed
- cflags-y += -ffreestanding
-
---- a/include/asm-mips/bootinfo.h
-+++ b/include/asm-mips/bootinfo.h
-@@ -79,6 +79,16 @@
- #define MACH_LASAT_200 1 /* Masquerade PRO/SP200 */
-
- /*
-+ * Valid machtype for Atheros AR71xx based boards
-+ */
-+#define MACH_AR71XX_GENERIC 0
-+#define MACH_AR71XX_WP543 1 /* Compex WP543 */
-+#define MACH_AR71XX_RB_411 2 /* MikroTik RouterBOARD 411/411A/411AH */
-+#define MACH_AR71XX_RB_433 3 /* MikroTik RouterBOARD 433/433AH */
-+#define MACH_AR71XX_RB_450 4 /* MikroTik RouterBOARD 450 */
-+#define MACH_AR71XX_RB_493 5 /* Mikrotik RouterBOARD 493/493AH */
-+
-+/*
- * Valid machtype for group NEC EMMA2RH
- */
- #define MACH_NEC_MARKEINS 0 /* NEC EMMA2RH Mark-eins */
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -21,6 +21,24 @@
- config MACH_ALCHEMY
- bool "Alchemy processor based machines"
-
-+config ATHEROS_AR71XX
-+ bool "Atheros AR71xx based boards"
-+ select CEVT_R4K
-+ select CSRC_R4K
-+ select DMA_NONCOHERENT
-+ select HW_HAS_PCI
-+ select IRQ_CPU
-+ select GENERIC_GPIO
-+ select HAVE_GPIO_LIB
-+ select SYS_HAS_CPU_MIPS32_R1
-+ select SYS_HAS_CPU_MIPS32_R2
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select SYS_SUPPORTS_BIG_ENDIAN
-+ select SYS_HAS_EARLY_PRINTK
-+ select MIPS_MACHINE
-+ help
-+ Support for Atheros AR71xx based boards.
-+
- config BASLER_EXCITE
- bool "Basler eXcite smart camera"
- select CEVT_R4K
-@@ -687,6 +705,7 @@
-
- endchoice
-
-+source "arch/mips/ar71xx/Kconfig"
- source "arch/mips/au1000/Kconfig"
- source "arch/mips/basler/excite/Kconfig"
- source "arch/mips/jazz/Kconfig"
+++ /dev/null
---- a/arch/mips/pci/Makefile
-+++ b/arch/mips/pci/Makefile
-@@ -15,6 +15,7 @@
- obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o
- obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o
- obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o
-+obj-$(CONFIG_ATHEROS_AR71XX) += pci-ar71xx.o
-
- #
- # These are still pretty much in the old state, watch, go blind.
+++ /dev/null
---- a/drivers/usb/host/Kconfig
-+++ b/drivers/usb/host/Kconfig
-@@ -81,6 +81,12 @@
- depends on USB_EHCI_HCD && (440EPX || ARCH_IXP4XX)
- default y
-
-+config USB_EHCI_AR71XX
-+ bool "USB EHCI support for AR71xx"
-+ depends on USB_EHCI_HCD && ATHEROS_AR71XX
-+ help
-+ Support for Atheros AR71xx built-in EHCI controller
-+
- config USB_EHCI_FSL
- bool "Support for Freescale on-chip EHCI USB controller"
- depends on USB_EHCI_HCD && FSL_SOC
-@@ -152,6 +158,12 @@
- To compile this driver as a module, choose M here: the
- module will be called ohci-hcd.
-
-+config USB_OHCI_AR71XX
-+ bool "USB OHCI support for Atheros AR71xx"
-+ depends on USB_OHCI_HCD && ATHEROS_AR71XX
-+ help
-+ Support for Atheros AR71xx built-in OHCI controller
-+
- config USB_OHCI_HCD_PPC_SOC
- bool "OHCI support for on-chip PPC USB controller"
- depends on USB_OHCI_HCD && (STB03xxx || PPC_MPC52xx)
---- a/drivers/usb/host/ehci-hcd.c
-+++ b/drivers/usb/host/ehci-hcd.c
-@@ -1034,6 +1034,11 @@
- #define PLATFORM_DRIVER ixp4xx_ehci_driver
- #endif
-
-+#ifdef CONFIG_USB_EHCI_AR71XX
-+#include "ehci-ar71xx.c"
-+#define PLATFORM_DRIVER ehci_hcd_ar71xx_driver
-+#endif
-+
- #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
- !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER)
- #error "missing bus glue for ehci-hcd"
---- a/drivers/usb/host/ohci.h
-+++ b/drivers/usb/host/ohci.h
-@@ -538,6 +538,11 @@
- #define writel_be(val, addr) out_be32((__force unsigned *)addr, val)
- #endif
-
-+#if defined(CONFIG_ATHEROS_AR71XX)
-+#define readl_be(addr) __raw_readl(addr)
-+#define writel_be(val, addr) __raw_writel(addr, val)
-+#endif
-+
- static inline unsigned int _ohci_readl (const struct ohci_hcd *ohci,
- __hc32 __iomem * regs)
- {
---- a/drivers/usb/host/ohci-hcd.c
-+++ b/drivers/usb/host/ohci-hcd.c
-@@ -1057,6 +1057,11 @@
- #define SM501_OHCI_DRIVER ohci_hcd_sm501_driver
- #endif
-
-+#ifdef CONFIG_USB_OHCI_AR71XX
-+#include "ohci-ar71xx.c"
-+#define PLATFORM_DRIVER ohci_hcd_ar71xx_driver
-+#endif
-+
- #if !defined(PCI_DRIVER) && \
- !defined(PLATFORM_DRIVER) && \
- !defined(OF_PLATFORM_DRIVER) && \
+++ /dev/null
---- a/drivers/spi/Kconfig
-+++ b/drivers/spi/Kconfig
-@@ -52,6 +52,13 @@
- comment "SPI Master Controller Drivers"
- depends on SPI_MASTER
-
-+config SPI_AR71XX
-+ tristate "Atheros AR71xx SPI Controller"
-+ depends on SPI_MASTER && ATHEROS_AR71XX
-+ select SPI_BITBANG
-+ help
-+ This is the SPI contoller driver for Atheros AR71xx.
-+
- config SPI_ATMEL
- tristate "Atmel SPI Controller"
- depends on (ARCH_AT91 || AVR32) && SPI_MASTER
---- a/drivers/spi/Makefile
-+++ b/drivers/spi/Makefile
-@@ -11,6 +11,7 @@
- obj-$(CONFIG_SPI_MASTER) += spi.o
-
- # SPI master controller drivers (bus)
-+obj-$(CONFIG_SPI_AR71XX) += ar71xx_spi.o
- obj-$(CONFIG_SPI_ATMEL) += atmel_spi.o
- obj-$(CONFIG_SPI_BFIN) += spi_bfin5xx.o
- obj-$(CONFIG_SPI_BITBANG) += spi_bitbang.o
+++ /dev/null
---- a/drivers/net/Kconfig
-+++ b/drivers/net/Kconfig
-@@ -2060,6 +2060,8 @@
-
- The safe and default value for this is N.
-
-+source drivers/net/ag71xx/Kconfig
-+
- config DL2K
- tristate "DL2000/TC902x-based Gigabit Ethernet support"
- depends on PCI
---- a/drivers/net/Makefile
-+++ b/drivers/net/Makefile
-@@ -2,6 +2,7 @@
- # Makefile for the Linux network (ethercard) device drivers.
- #
-
-+obj-$(CONFIG_AG71XX) += ag71xx/
- obj-$(CONFIG_E1000) += e1000/
- obj-$(CONFIG_E1000E) += e1000e/
- obj-$(CONFIG_IBM_EMAC) += ibm_emac/
+++ /dev/null
---- a/drivers/watchdog/Kconfig
-+++ b/drivers/watchdog/Kconfig
-@@ -683,6 +683,13 @@
- help
- Hardware driver for the built-in watchdog timer on TXx9 MIPS SoCs.
-
-+config AR71XX_WDT
-+ tristate "Atheros AR71xx Watchdog Timer"
-+ depends on ATHEROS_AR71XX
-+ help
-+ Hardware driver for the built-in watchdog timer on the Atheros
-+ AR71xx SoCs.
-+
- # PARISC Architecture
-
- # POWERPC Architecture
---- a/drivers/watchdog/Makefile
-+++ b/drivers/watchdog/Makefile
-@@ -97,6 +97,7 @@
- obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o
- obj-$(CONFIG_AR7_WDT) += ar7_wdt.o
- obj-$(CONFIG_TXX9_WDT) += txx9wdt.o
-+obj-$(CONFIG_AR71XX_WDT) += ar71xx_wdt.o
-
- # PARISC Architecture
-
+++ /dev/null
---- a/drivers/mtd/devices/m25p80.c
-+++ b/drivers/mtd/devices/m25p80.c
-@@ -455,6 +455,10 @@
- { "at26df161a", 0x1f4601, 64 * 1024, 32, SECT_4K, },
- { "at26df321", 0x1f4701, 64 * 1024, 64, SECT_4K, },
-
-+ /* PMC -- pm25x "blocks" are 32K, sectors are 4K */
-+ { "pm25lv512", 0, 32 * 1024, 2, SECT_4K },
-+ { "pm25lv010", 0, 32 * 1024, 4, SECT_4K },
-+
- /* Spansion -- single (large) sector size only, at least
- * for the chips listed here (without boot sectors).
- */
+++ /dev/null
---- a/drivers/net/phy/Kconfig
-+++ b/drivers/net/phy/Kconfig
-@@ -76,6 +76,11 @@
- ---help---
- Currently supports the Marvell 88E6060 switch.
-
-+config MICREL_PHY
-+ tristate "Drivers for Micrel/Kendin PHYs"
-+ ---help---
-+ Currently has a driver for the KSZ8041
-+
- config FIXED_PHY
- bool "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs"
- depends on PHYLIB=y
---- a/drivers/net/phy/Makefile
-+++ b/drivers/net/phy/Makefile
-@@ -15,5 +15,6 @@
- obj-$(CONFIG_ADM6996_PHY) += adm6996.o
- obj-$(CONFIG_MVSWITCH_PHY) += mvswitch.o
- obj-$(CONFIG_REALTEK_PHY) += realtek.o
-+obj-$(CONFIG_MICREL_PHY) += micrel.o
- obj-$(CONFIG_FIXED_PHY) += fixed.o
- obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o
+++ /dev/null
---- a/drivers/mtd/redboot.c
-+++ b/drivers/mtd/redboot.c
-@@ -62,31 +62,32 @@
- static char nullstring[] = "unallocated";
- #endif
-
-+ buf = vmalloc(master->erasesize);
-+ if (!buf)
-+ return -ENOMEM;
-+
-+ restart:
- if ( directory < 0 ) {
- offset = master->size + directory * master->erasesize;
-- while (master->block_isbad &&
-+ while (master->block_isbad &&
- master->block_isbad(master, offset)) {
- if (!offset) {
- nogood:
- printk(KERN_NOTICE "Failed to find a non-bad block to check for RedBoot partition table\n");
-+ vfree(buf);
- return -EIO;
- }
- offset -= master->erasesize;
- }
- } else {
- offset = directory * master->erasesize;
-- while (master->block_isbad &&
-+ while (master->block_isbad &&
- master->block_isbad(master, offset)) {
- offset += master->erasesize;
- if (offset == master->size)
- goto nogood;
- }
- }
-- buf = vmalloc(master->erasesize);
--
-- if (!buf)
-- return -ENOMEM;
--
- printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n",
- master->name, offset);
-
-@@ -158,6 +159,11 @@
- }
- if (i == numslots) {
- /* Didn't find it */
-+ if (offset + master->erasesize < master->size) {
-+ /* not at the end of the flash yet, maybe next block :) */
-+ directory++;
-+ goto restart;
-+ }
- printk(KERN_NOTICE "No RedBoot partition table detected in %s\n",
- master->name);
- ret = 0;
+++ /dev/null
---- a/drivers/mtd/nand/Kconfig
-+++ b/drivers/mtd/nand/Kconfig
-@@ -386,4 +386,8 @@
- Enables support for NAND Flash chips wired onto Freescale PowerPC
- processor localbus with User-Programmable Machine support.
-
-+config MTD_NAND_RB4XX
-+ tristate "NAND flash driver for RouterBoard 4xx series"
-+ depends on MTD_NAND && ATHEROS_AR71XX
-+
- endif # MTD_NAND
---- a/drivers/mtd/nand/Makefile
-+++ b/drivers/mtd/nand/Makefile
-@@ -29,6 +29,7 @@
- obj-$(CONFIG_MTD_NAND_BASLER_EXCITE) += excite_nandflash.o
- obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o
- obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o
-+obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o
- obj-$(CONFIG_MTD_ALAUDA) += alauda.o
- obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o
- obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o
+++ /dev/null
---- a/arch/mips/Makefile
-+++ b/arch/mips/Makefile
-@@ -158,6 +158,7 @@
- #
- libs-$(CONFIG_ARC) += arch/mips/fw/arc/
- libs-$(CONFIG_CFE) += arch/mips/fw/cfe/
-+libs-$(CONFIG_MYLOADER) += arch/mips/fw/myloader/
- libs-$(CONFIG_SNIPROM) += arch/mips/fw/sni/
- libs-y += arch/mips/fw/lib/
- libs-$(CONFIG_SIBYTE_CFE) += arch/mips/sibyte/cfe/
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -874,6 +874,9 @@
- config MIPS_DISABLE_OBSOLETE_IDE
- bool
-
-+config MYLOADER
-+ bool
-+
- config SYNC_R4K
- bool
-
+++ /dev/null
---- /dev/null
-+++ b/include/asm-mips/mips_machine.h
-@@ -0,0 +1,49 @@
-+/*
-+ * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ *
-+ */
-+
-+#ifndef __ASM_MIPS_MACHINE_H
-+#define __ASM_MIPS_MACHINE_H
-+
-+#include <linux/init.h>
-+#include <linux/list.h>
-+
-+#include <asm/bootinfo.h>
-+
-+#define MIPS_MACHINE_NAME_LEN 64
-+
-+struct mips_machine {
-+ unsigned long mach_type;
-+ void (*mach_setup)(void);
-+ unsigned char mach_name[MIPS_MACHINE_NAME_LEN];
-+ struct list_head list;
-+};
-+
-+void mips_machine_register(struct mips_machine *) __init;
-+void mips_machine_setup(void) __init;
-+
-+extern unsigned char mips_machine_name[MIPS_MACHINE_NAME_LEN];
-+
-+#define MIPS_MACHINE(_type, _name, _setup) \
-+static struct mips_machine machine_##_type __initdata = \
-+{ \
-+ .mach_type = _type, \
-+ .mach_name = _name, \
-+ .mach_setup = _setup, \
-+}; \
-+ \
-+static int __init register_machine_##_type(void) \
-+{ \
-+ mips_machine_register(&machine_##_type); \
-+ return 0; \
-+} \
-+ \
-+pure_initcall(register_machine_##_type)
-+
-+#endif /* __ASM_MIPS_MACHINE_H */
-+
---- /dev/null
-+++ b/arch/mips/kernel/mips_machine.c
-@@ -0,0 +1,58 @@
-+/*
-+ * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ *
-+ */
-+
-+#include <asm/mips_machine.h>
-+#include <asm/bootinfo.h>
-+
-+static struct list_head mips_machines __initdata =
-+ LIST_HEAD_INIT(mips_machines);
-+
-+unsigned char mips_machine_name[MIPS_MACHINE_NAME_LEN] = "Unknown";
-+
-+static struct mips_machine * __init mips_machine_find(unsigned long machtype)
-+{
-+ struct list_head *this;
-+
-+ list_for_each(this, &mips_machines) {
-+ struct mips_machine *mach;
-+
-+ mach = list_entry(this, struct mips_machine, list);
-+ if (mach->mach_type == machtype)
-+ return mach;
-+ }
-+
-+ return NULL;
-+}
-+
-+void __init mips_machine_register(struct mips_machine *mach)
-+{
-+ list_add_tail(&mach->list, &mips_machines);
-+}
-+
-+void __init mips_machine_setup(void)
-+{
-+ struct mips_machine *mach;
-+
-+ mach = mips_machine_find(mips_machtype);
-+ if (!mach) {
-+ printk(KERN_ALERT "MIPS: no machine registered for "
-+ "machtype %lu\n", mips_machtype);
-+ return;
-+ }
-+
-+ if (mach->mach_name[0])
-+ strncpy(mips_machine_name, mach->mach_name,
-+ MIPS_MACHINE_NAME_LEN);
-+
-+ printk(KERN_INFO "MIPS: machine is %s\n", mips_machine_name);
-+
-+ if (mach->mach_setup)
-+ mach->mach_setup();
-+}
-+
---- a/arch/mips/kernel/Makefile
-+++ b/arch/mips/kernel/Makefile
-@@ -86,6 +86,7 @@
-
- obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o
- obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
-+obj-$(CONFIG_MIPS_MACHINE) += mips_machine.o
-
- CFLAGS_cpu-bugs64.o = $(shell if $(CC) $(KBUILD_CFLAGS) -Wa,-mdaddi -c -o /dev/null -xc /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi)
-
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -880,6 +880,9 @@
- config SYNC_R4K
- bool
-
-+config MIPS_MACHINE
-+ def_bool n
-+
- config NO_IOPORT
- def_bool n
-
+++ /dev/null
---- a/arch/mips/kernel/traps.c
-+++ b/arch/mips/kernel/traps.c
-@@ -43,6 +43,7 @@
- #include <asm/mmu_context.h>
- #include <asm/types.h>
- #include <asm/stacktrace.h>
-+#include <asm/time.h>
-
- extern asmlinkage void handle_int(void);
- extern asmlinkage void handle_tlbm(void);
-@@ -1464,6 +1465,8 @@
- */
- if (cpu_has_mips_r2) {
- cp0_compare_irq = (read_c0_intctl() >> 29) & 7;
-+ if (get_c0_compare_irq)
-+ cp0_compare_irq = get_c0_compare_irq();
- cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7;
- if (cp0_perfcount_irq == cp0_compare_irq)
- cp0_perfcount_irq = -1;
---- a/include/asm-mips/time.h
-+++ b/include/asm-mips/time.h
-@@ -53,6 +53,7 @@
- #ifdef CONFIG_CEVT_R4K
- extern int mips_clockevent_init(void);
- extern unsigned int __weak get_c0_compare_int(void);
-+extern unsigned int __weak get_c0_compare_irq(void);
- #else
- static inline int mips_clockevent_init(void)
- {
+++ /dev/null
---- a/arch/mips/kernel/cevt-r4k.c
-+++ b/arch/mips/kernel/cevt-r4k.c
-@@ -13,6 +13,22 @@
- #include <asm/smtc_ipi.h>
- #include <asm/time.h>
-
-+/*
-+ * Compare interrupt can be routed and latched outside the core,
-+ * so a single execution hazard barrier may not be enough to give
-+ * it time to clear as seen in the Cause register. 4 time the
-+ * pipeline depth seems reasonably conservative, and empirically
-+ * works better in configurations with high CPU/bus clock ratios.
-+ */
-+
-+#define compare_change_hazard() \
-+ do { \
-+ irq_disable_hazard(); \
-+ irq_disable_hazard(); \
-+ irq_disable_hazard(); \
-+ irq_disable_hazard(); \
-+ } while (0)
-+
- static int mips_next_event(unsigned long delta,
- struct clock_event_device *evt)
- {
-@@ -28,6 +44,7 @@
- cnt = read_c0_count();
- cnt += delta;
- write_c0_compare(cnt);
-+ compare_change_hazard();
- res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0;
- #ifdef CONFIG_MIPS_MT_SMTC
- evpe(vpflags);
-@@ -187,7 +204,7 @@
- */
- if (c0_compare_int_pending()) {
- write_c0_compare(read_c0_count());
-- irq_disable_hazard();
-+ compare_change_hazard();
- if (c0_compare_int_pending())
- return 0;
- }
-@@ -196,7 +213,7 @@
- cnt = read_c0_count();
- cnt += delta;
- write_c0_compare(cnt);
-- irq_disable_hazard();
-+ compare_change_hazard();
- if ((int)(read_c0_count() - cnt) < 0)
- break;
- /* increase delta if the timer was already expired */
-@@ -205,11 +222,12 @@
- while ((int)(read_c0_count() - cnt) <= 0)
- ; /* Wait for expiry */
-
-+ compare_change_hazard();
- if (!c0_compare_int_pending())
- return 0;
-
- write_c0_compare(read_c0_count());
-- irq_disable_hazard();
-+ compare_change_hazard();
- if (c0_compare_int_pending())
- return 0;
-
--- /dev/null
+--- a/arch/mips/Makefile
++++ b/arch/mips/Makefile
+@@ -597,6 +597,13 @@
+ cflags-$(CONFIG_TOSHIBA_RBTX4938) += -Iinclude/asm-mips/mach-tx49xx
+ load-$(CONFIG_TOSHIBA_RBTX4938) += 0xffffffff80100000
+
++#
++# Atheros AR71xx
++#
++core-$(CONFIG_ATHEROS_AR71XX) += arch/mips/ar71xx/
++cflags-$(CONFIG_ATHEROS_AR71XX) += -Iinclude/asm-mips/mach-ar71xx
++load-$(CONFIG_ATHEROS_AR71XX) += 0xffffffff80060000
++
+ # temporary until string.h is fixed
+ cflags-y += -ffreestanding
+
+--- a/include/asm-mips/bootinfo.h
++++ b/include/asm-mips/bootinfo.h
+@@ -79,6 +79,16 @@
+ #define MACH_LASAT_200 1 /* Masquerade PRO/SP200 */
+
+ /*
++ * Valid machtype for Atheros AR71xx based boards
++ */
++#define MACH_AR71XX_GENERIC 0
++#define MACH_AR71XX_WP543 1 /* Compex WP543 */
++#define MACH_AR71XX_RB_411 2 /* MikroTik RouterBOARD 411/411A/411AH */
++#define MACH_AR71XX_RB_433 3 /* MikroTik RouterBOARD 433/433AH */
++#define MACH_AR71XX_RB_450 4 /* MikroTik RouterBOARD 450 */
++#define MACH_AR71XX_RB_493 5 /* Mikrotik RouterBOARD 493/493AH */
++
++/*
+ * Valid machtype for group NEC EMMA2RH
+ */
+ #define MACH_NEC_MARKEINS 0 /* NEC EMMA2RH Mark-eins */
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -21,6 +21,24 @@
+ config MACH_ALCHEMY
+ bool "Alchemy processor based machines"
+
++config ATHEROS_AR71XX
++ bool "Atheros AR71xx based boards"
++ select CEVT_R4K
++ select CSRC_R4K
++ select DMA_NONCOHERENT
++ select HW_HAS_PCI
++ select IRQ_CPU
++ select GENERIC_GPIO
++ select HAVE_GPIO_LIB
++ select SYS_HAS_CPU_MIPS32_R1
++ select SYS_HAS_CPU_MIPS32_R2
++ select SYS_SUPPORTS_32BIT_KERNEL
++ select SYS_SUPPORTS_BIG_ENDIAN
++ select SYS_HAS_EARLY_PRINTK
++ select MIPS_MACHINE
++ help
++ Support for Atheros AR71xx based boards.
++
+ config BASLER_EXCITE
+ bool "Basler eXcite smart camera"
+ select CEVT_R4K
+@@ -687,6 +705,7 @@
+
+ endchoice
+
++source "arch/mips/ar71xx/Kconfig"
+ source "arch/mips/au1000/Kconfig"
+ source "arch/mips/basler/excite/Kconfig"
+ source "arch/mips/jazz/Kconfig"
--- /dev/null
+--- a/arch/mips/pci/Makefile
++++ b/arch/mips/pci/Makefile
+@@ -15,6 +15,7 @@
+ obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o
+ obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o
+ obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o
++obj-$(CONFIG_ATHEROS_AR71XX) += pci-ar71xx.o
+
+ #
+ # These are still pretty much in the old state, watch, go blind.
--- /dev/null
+--- a/drivers/usb/host/Kconfig
++++ b/drivers/usb/host/Kconfig
+@@ -81,6 +81,12 @@
+ depends on USB_EHCI_HCD && (440EPX || ARCH_IXP4XX)
+ default y
+
++config USB_EHCI_AR71XX
++ bool "USB EHCI support for AR71xx"
++ depends on USB_EHCI_HCD && ATHEROS_AR71XX
++ help
++ Support for Atheros AR71xx built-in EHCI controller
++
+ config USB_EHCI_FSL
+ bool "Support for Freescale on-chip EHCI USB controller"
+ depends on USB_EHCI_HCD && FSL_SOC
+@@ -152,6 +158,12 @@
+ To compile this driver as a module, choose M here: the
+ module will be called ohci-hcd.
+
++config USB_OHCI_AR71XX
++ bool "USB OHCI support for Atheros AR71xx"
++ depends on USB_OHCI_HCD && ATHEROS_AR71XX
++ help
++ Support for Atheros AR71xx built-in OHCI controller
++
+ config USB_OHCI_HCD_PPC_SOC
+ bool "OHCI support for on-chip PPC USB controller"
+ depends on USB_OHCI_HCD && (STB03xxx || PPC_MPC52xx)
+--- a/drivers/usb/host/ehci-hcd.c
++++ b/drivers/usb/host/ehci-hcd.c
+@@ -1034,6 +1034,11 @@
+ #define PLATFORM_DRIVER ixp4xx_ehci_driver
+ #endif
+
++#ifdef CONFIG_USB_EHCI_AR71XX
++#include "ehci-ar71xx.c"
++#define PLATFORM_DRIVER ehci_hcd_ar71xx_driver
++#endif
++
+ #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
+ !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER)
+ #error "missing bus glue for ehci-hcd"
+--- a/drivers/usb/host/ohci.h
++++ b/drivers/usb/host/ohci.h
+@@ -538,6 +538,11 @@
+ #define writel_be(val, addr) out_be32((__force unsigned *)addr, val)
+ #endif
+
++#if defined(CONFIG_ATHEROS_AR71XX)
++#define readl_be(addr) __raw_readl(addr)
++#define writel_be(val, addr) __raw_writel(addr, val)
++#endif
++
+ static inline unsigned int _ohci_readl (const struct ohci_hcd *ohci,
+ __hc32 __iomem * regs)
+ {
+--- a/drivers/usb/host/ohci-hcd.c
++++ b/drivers/usb/host/ohci-hcd.c
+@@ -1057,6 +1057,11 @@
+ #define SM501_OHCI_DRIVER ohci_hcd_sm501_driver
+ #endif
+
++#ifdef CONFIG_USB_OHCI_AR71XX
++#include "ohci-ar71xx.c"
++#define PLATFORM_DRIVER ohci_hcd_ar71xx_driver
++#endif
++
+ #if !defined(PCI_DRIVER) && \
+ !defined(PLATFORM_DRIVER) && \
+ !defined(OF_PLATFORM_DRIVER) && \
--- /dev/null
+--- a/drivers/spi/Kconfig
++++ b/drivers/spi/Kconfig
+@@ -52,6 +52,13 @@
+ comment "SPI Master Controller Drivers"
+ depends on SPI_MASTER
+
++config SPI_AR71XX
++ tristate "Atheros AR71xx SPI Controller"
++ depends on SPI_MASTER && ATHEROS_AR71XX
++ select SPI_BITBANG
++ help
++ This is the SPI contoller driver for Atheros AR71xx.
++
+ config SPI_ATMEL
+ tristate "Atmel SPI Controller"
+ depends on (ARCH_AT91 || AVR32) && SPI_MASTER
+--- a/drivers/spi/Makefile
++++ b/drivers/spi/Makefile
+@@ -11,6 +11,7 @@
+ obj-$(CONFIG_SPI_MASTER) += spi.o
+
+ # SPI master controller drivers (bus)
++obj-$(CONFIG_SPI_AR71XX) += ar71xx_spi.o
+ obj-$(CONFIG_SPI_ATMEL) += atmel_spi.o
+ obj-$(CONFIG_SPI_BFIN) += spi_bfin5xx.o
+ obj-$(CONFIG_SPI_BITBANG) += spi_bitbang.o
--- /dev/null
+--- a/drivers/net/Kconfig
++++ b/drivers/net/Kconfig
+@@ -2060,6 +2060,8 @@
+
+ The safe and default value for this is N.
+
++source drivers/net/ag71xx/Kconfig
++
+ config DL2K
+ tristate "DL2000/TC902x-based Gigabit Ethernet support"
+ depends on PCI
+--- a/drivers/net/Makefile
++++ b/drivers/net/Makefile
+@@ -2,6 +2,7 @@
+ # Makefile for the Linux network (ethercard) device drivers.
+ #
+
++obj-$(CONFIG_AG71XX) += ag71xx/
+ obj-$(CONFIG_E1000) += e1000/
+ obj-$(CONFIG_E1000E) += e1000e/
+ obj-$(CONFIG_IBM_EMAC) += ibm_emac/
--- /dev/null
+--- a/drivers/watchdog/Kconfig
++++ b/drivers/watchdog/Kconfig
+@@ -683,6 +683,13 @@
+ help
+ Hardware driver for the built-in watchdog timer on TXx9 MIPS SoCs.
+
++config AR71XX_WDT
++ tristate "Atheros AR71xx Watchdog Timer"
++ depends on ATHEROS_AR71XX
++ help
++ Hardware driver for the built-in watchdog timer on the Atheros
++ AR71xx SoCs.
++
+ # PARISC Architecture
+
+ # POWERPC Architecture
+--- a/drivers/watchdog/Makefile
++++ b/drivers/watchdog/Makefile
+@@ -97,6 +97,7 @@
+ obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o
+ obj-$(CONFIG_AR7_WDT) += ar7_wdt.o
+ obj-$(CONFIG_TXX9_WDT) += txx9wdt.o
++obj-$(CONFIG_AR71XX_WDT) += ar71xx_wdt.o
+
+ # PARISC Architecture
+
--- /dev/null
+--- a/drivers/mtd/devices/m25p80.c
++++ b/drivers/mtd/devices/m25p80.c
+@@ -455,6 +455,10 @@
+ { "at26df161a", 0x1f4601, 64 * 1024, 32, SECT_4K, },
+ { "at26df321", 0x1f4701, 64 * 1024, 64, SECT_4K, },
+
++ /* PMC -- pm25x "blocks" are 32K, sectors are 4K */
++ { "pm25lv512", 0, 32 * 1024, 2, SECT_4K },
++ { "pm25lv010", 0, 32 * 1024, 4, SECT_4K },
++
+ /* Spansion -- single (large) sector size only, at least
+ * for the chips listed here (without boot sectors).
+ */
--- /dev/null
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -76,6 +76,11 @@
+ ---help---
+ Currently supports the Marvell 88E6060 switch.
+
++config MICREL_PHY
++ tristate "Drivers for Micrel/Kendin PHYs"
++ ---help---
++ Currently has a driver for the KSZ8041
++
+ config FIXED_PHY
+ bool "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs"
+ depends on PHYLIB=y
+--- a/drivers/net/phy/Makefile
++++ b/drivers/net/phy/Makefile
+@@ -15,5 +15,6 @@
+ obj-$(CONFIG_ADM6996_PHY) += adm6996.o
+ obj-$(CONFIG_MVSWITCH_PHY) += mvswitch.o
+ obj-$(CONFIG_REALTEK_PHY) += realtek.o
++obj-$(CONFIG_MICREL_PHY) += micrel.o
+ obj-$(CONFIG_FIXED_PHY) += fixed.o
+ obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o
--- /dev/null
+--- a/drivers/mtd/redboot.c
++++ b/drivers/mtd/redboot.c
+@@ -62,31 +62,32 @@
+ static char nullstring[] = "unallocated";
+ #endif
+
++ buf = vmalloc(master->erasesize);
++ if (!buf)
++ return -ENOMEM;
++
++ restart:
+ if ( directory < 0 ) {
+ offset = master->size + directory * master->erasesize;
+- while (master->block_isbad &&
++ while (master->block_isbad &&
+ master->block_isbad(master, offset)) {
+ if (!offset) {
+ nogood:
+ printk(KERN_NOTICE "Failed to find a non-bad block to check for RedBoot partition table\n");
++ vfree(buf);
+ return -EIO;
+ }
+ offset -= master->erasesize;
+ }
+ } else {
+ offset = directory * master->erasesize;
+- while (master->block_isbad &&
++ while (master->block_isbad &&
+ master->block_isbad(master, offset)) {
+ offset += master->erasesize;
+ if (offset == master->size)
+ goto nogood;
+ }
+ }
+- buf = vmalloc(master->erasesize);
+-
+- if (!buf)
+- return -ENOMEM;
+-
+ printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n",
+ master->name, offset);
+
+@@ -158,6 +159,11 @@
+ }
+ if (i == numslots) {
+ /* Didn't find it */
++ if (offset + master->erasesize < master->size) {
++ /* not at the end of the flash yet, maybe next block :) */
++ directory++;
++ goto restart;
++ }
+ printk(KERN_NOTICE "No RedBoot partition table detected in %s\n",
+ master->name);
+ ret = 0;
--- /dev/null
+--- a/drivers/mtd/nand/Kconfig
++++ b/drivers/mtd/nand/Kconfig
+@@ -386,4 +386,8 @@
+ Enables support for NAND Flash chips wired onto Freescale PowerPC
+ processor localbus with User-Programmable Machine support.
+
++config MTD_NAND_RB4XX
++ tristate "NAND flash driver for RouterBoard 4xx series"
++ depends on MTD_NAND && ATHEROS_AR71XX
++
+ endif # MTD_NAND
+--- a/drivers/mtd/nand/Makefile
++++ b/drivers/mtd/nand/Makefile
+@@ -29,6 +29,7 @@
+ obj-$(CONFIG_MTD_NAND_BASLER_EXCITE) += excite_nandflash.o
+ obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o
+ obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o
++obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o
+ obj-$(CONFIG_MTD_ALAUDA) += alauda.o
+ obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o
+ obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o
--- /dev/null
+--- a/arch/mips/Makefile
++++ b/arch/mips/Makefile
+@@ -158,6 +158,7 @@
+ #
+ libs-$(CONFIG_ARC) += arch/mips/fw/arc/
+ libs-$(CONFIG_CFE) += arch/mips/fw/cfe/
++libs-$(CONFIG_MYLOADER) += arch/mips/fw/myloader/
+ libs-$(CONFIG_SNIPROM) += arch/mips/fw/sni/
+ libs-y += arch/mips/fw/lib/
+ libs-$(CONFIG_SIBYTE_CFE) += arch/mips/sibyte/cfe/
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -874,6 +874,9 @@
+ config MIPS_DISABLE_OBSOLETE_IDE
+ bool
+
++config MYLOADER
++ bool
++
+ config SYNC_R4K
+ bool
+
--- /dev/null
+--- /dev/null
++++ b/include/asm-mips/mips_machine.h
+@@ -0,0 +1,49 @@
++/*
++ * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ */
++
++#ifndef __ASM_MIPS_MACHINE_H
++#define __ASM_MIPS_MACHINE_H
++
++#include <linux/init.h>
++#include <linux/list.h>
++
++#include <asm/bootinfo.h>
++
++#define MIPS_MACHINE_NAME_LEN 64
++
++struct mips_machine {
++ unsigned long mach_type;
++ void (*mach_setup)(void);
++ unsigned char mach_name[MIPS_MACHINE_NAME_LEN];
++ struct list_head list;
++};
++
++void mips_machine_register(struct mips_machine *) __init;
++void mips_machine_setup(void) __init;
++
++extern unsigned char mips_machine_name[MIPS_MACHINE_NAME_LEN];
++
++#define MIPS_MACHINE(_type, _name, _setup) \
++static struct mips_machine machine_##_type __initdata = \
++{ \
++ .mach_type = _type, \
++ .mach_name = _name, \
++ .mach_setup = _setup, \
++}; \
++ \
++static int __init register_machine_##_type(void) \
++{ \
++ mips_machine_register(&machine_##_type); \
++ return 0; \
++} \
++ \
++pure_initcall(register_machine_##_type)
++
++#endif /* __ASM_MIPS_MACHINE_H */
++
+--- /dev/null
++++ b/arch/mips/kernel/mips_machine.c
+@@ -0,0 +1,58 @@
++/*
++ * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ */
++
++#include <asm/mips_machine.h>
++#include <asm/bootinfo.h>
++
++static struct list_head mips_machines __initdata =
++ LIST_HEAD_INIT(mips_machines);
++
++unsigned char mips_machine_name[MIPS_MACHINE_NAME_LEN] = "Unknown";
++
++static struct mips_machine * __init mips_machine_find(unsigned long machtype)
++{
++ struct list_head *this;
++
++ list_for_each(this, &mips_machines) {
++ struct mips_machine *mach;
++
++ mach = list_entry(this, struct mips_machine, list);
++ if (mach->mach_type == machtype)
++ return mach;
++ }
++
++ return NULL;
++}
++
++void __init mips_machine_register(struct mips_machine *mach)
++{
++ list_add_tail(&mach->list, &mips_machines);
++}
++
++void __init mips_machine_setup(void)
++{
++ struct mips_machine *mach;
++
++ mach = mips_machine_find(mips_machtype);
++ if (!mach) {
++ printk(KERN_ALERT "MIPS: no machine registered for "
++ "machtype %lu\n", mips_machtype);
++ return;
++ }
++
++ if (mach->mach_name[0])
++ strncpy(mips_machine_name, mach->mach_name,
++ MIPS_MACHINE_NAME_LEN);
++
++ printk(KERN_INFO "MIPS: machine is %s\n", mips_machine_name);
++
++ if (mach->mach_setup)
++ mach->mach_setup();
++}
++
+--- a/arch/mips/kernel/Makefile
++++ b/arch/mips/kernel/Makefile
+@@ -86,6 +86,7 @@
+
+ obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o
+ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
++obj-$(CONFIG_MIPS_MACHINE) += mips_machine.o
+
+ CFLAGS_cpu-bugs64.o = $(shell if $(CC) $(KBUILD_CFLAGS) -Wa,-mdaddi -c -o /dev/null -xc /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi)
+
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -880,6 +880,9 @@
+ config SYNC_R4K
+ bool
+
++config MIPS_MACHINE
++ def_bool n
++
+ config NO_IOPORT
+ def_bool n
+
--- /dev/null
+--- a/arch/mips/kernel/traps.c
++++ b/arch/mips/kernel/traps.c
+@@ -43,6 +43,7 @@
+ #include <asm/mmu_context.h>
+ #include <asm/types.h>
+ #include <asm/stacktrace.h>
++#include <asm/time.h>
+
+ extern asmlinkage void handle_int(void);
+ extern asmlinkage void handle_tlbm(void);
+@@ -1464,6 +1465,8 @@
+ */
+ if (cpu_has_mips_r2) {
+ cp0_compare_irq = (read_c0_intctl() >> 29) & 7;
++ if (get_c0_compare_irq)
++ cp0_compare_irq = get_c0_compare_irq();
+ cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7;
+ if (cp0_perfcount_irq == cp0_compare_irq)
+ cp0_perfcount_irq = -1;
+--- a/include/asm-mips/time.h
++++ b/include/asm-mips/time.h
+@@ -53,6 +53,7 @@
+ #ifdef CONFIG_CEVT_R4K
+ extern int mips_clockevent_init(void);
+ extern unsigned int __weak get_c0_compare_int(void);
++extern unsigned int __weak get_c0_compare_irq(void);
+ #else
+ static inline int mips_clockevent_init(void)
+ {
--- /dev/null
+--- a/arch/mips/kernel/cevt-r4k.c
++++ b/arch/mips/kernel/cevt-r4k.c
+@@ -13,6 +13,22 @@
+ #include <asm/smtc_ipi.h>
+ #include <asm/time.h>
+
++/*
++ * Compare interrupt can be routed and latched outside the core,
++ * so a single execution hazard barrier may not be enough to give
++ * it time to clear as seen in the Cause register. 4 time the
++ * pipeline depth seems reasonably conservative, and empirically
++ * works better in configurations with high CPU/bus clock ratios.
++ */
++
++#define compare_change_hazard() \
++ do { \
++ irq_disable_hazard(); \
++ irq_disable_hazard(); \
++ irq_disable_hazard(); \
++ irq_disable_hazard(); \
++ } while (0)
++
+ static int mips_next_event(unsigned long delta,
+ struct clock_event_device *evt)
+ {
+@@ -28,6 +44,7 @@
+ cnt = read_c0_count();
+ cnt += delta;
+ write_c0_compare(cnt);
++ compare_change_hazard();
+ res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0;
+ #ifdef CONFIG_MIPS_MT_SMTC
+ evpe(vpflags);
+@@ -187,7 +204,7 @@
+ */
+ if (c0_compare_int_pending()) {
+ write_c0_compare(read_c0_count());
+- irq_disable_hazard();
++ compare_change_hazard();
+ if (c0_compare_int_pending())
+ return 0;
+ }
+@@ -196,7 +213,7 @@
+ cnt = read_c0_count();
+ cnt += delta;
+ write_c0_compare(cnt);
+- irq_disable_hazard();
++ compare_change_hazard();
+ if ((int)(read_c0_count() - cnt) < 0)
+ break;
+ /* increase delta if the timer was already expired */
+@@ -205,11 +222,12 @@
+ while ((int)(read_c0_count() - cnt) <= 0)
+ ; /* Wait for expiry */
+
++ compare_change_hazard();
+ if (!c0_compare_int_pending())
+ return 0;
+
+ write_c0_compare(read_c0_count());
+- irq_disable_hazard();
++ compare_change_hazard();
+ if (c0_compare_int_pending())
+ return 0;
+
+++ /dev/null
-CONFIG_32BIT=y
-# CONFIG_64BIT is not set
-CONFIG_AR2313=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_ARCH_POPULATES_NODE_MAP=y
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-CONFIG_ARCH_SUPPORTS_OPROFILE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ATHEROS=y
-CONFIG_ATHEROS_AR5312=y
-CONFIG_ATHEROS_AR5315=y
-CONFIG_ATHEROS_AR5315_PCI=y
-# CONFIG_ATM is not set
-# CONFIG_ATMEL is not set
-CONFIG_BASE_SMALL=0
-# CONFIG_BCM47XX is not set
-CONFIG_BITREVERSE=y
-# CONFIG_BROADCOM_PHY is not set
-# CONFIG_BT is not set
-CONFIG_CEVT_R4K=y
-CONFIG_CLASSIC_RCU=y
-CONFIG_CMDLINE="console=ttyS0,9600 rootfstype=squashfs,jffs2 init=/etc/preinit"
-CONFIG_CPU_BIG_ENDIAN=y
-CONFIG_CPU_HAS_LLSC=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_SYNC=y
-# CONFIG_CPU_LITTLE_ENDIAN is not set
-# CONFIG_CPU_LOONGSON2 is not set
-CONFIG_CPU_MIPS32=y
-CONFIG_CPU_MIPS32_R1=y
-# CONFIG_CPU_MIPS32_R2 is not set
-# CONFIG_CPU_MIPS64_R1 is not set
-# CONFIG_CPU_MIPS64_R2 is not set
-CONFIG_CPU_MIPSR1=y
-# CONFIG_CPU_NEVADA is not set
-# CONFIG_CPU_R10000 is not set
-# CONFIG_CPU_R3000 is not set
-# CONFIG_CPU_R4300 is not set
-# CONFIG_CPU_R4X00 is not set
-# CONFIG_CPU_R5000 is not set
-# CONFIG_CPU_R5432 is not set
-# CONFIG_CPU_R6000 is not set
-# CONFIG_CPU_R8000 is not set
-# CONFIG_CPU_RM7000 is not set
-# CONFIG_CPU_RM9000 is not set
-# CONFIG_CPU_SB1 is not set
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-# CONFIG_CPU_TX39XX is not set
-# CONFIG_CPU_TX49XX is not set
-# CONFIG_CPU_VR41XX is not set
-CONFIG_CSRC_R4K=y
-CONFIG_DEVPORT=y
-# CONFIG_DM9000 is not set
-CONFIG_DMA_NEED_PCI_MAP_STATE=y
-CONFIG_DMA_NONCOHERENT=y
-# CONFIG_E1000E_ENABLED is not set
-# CONFIG_FIXED_PHY is not set
-CONFIG_FS_POSIX_ACL=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-# CONFIG_GENERIC_FIND_FIRST_BIT is not set
-CONFIG_GENERIC_FIND_NEXT_BIT=y
-CONFIG_GENERIC_GPIO=y
-# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
-CONFIG_GPIO_DEVICE=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAVE_DMA_ATTRS is not set
-CONFIG_HAVE_IDE=y
-# CONFIG_HAVE_KPROBES is not set
-# CONFIG_HAVE_KRETPROBES is not set
-CONFIG_HAVE_OPROFILE=y
-# CONFIG_HERMES is not set
-# CONFIG_HOSTAP is not set
-CONFIG_HW_HAS_PCI=y
-CONFIG_HW_RANDOM=y
-# CONFIG_I2C is not set
-# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_IBM_NEW_EMAC_RGMII is not set
-# CONFIG_IBM_NEW_EMAC_TAH is not set
-# CONFIG_IBM_NEW_EMAC_ZMII is not set
-CONFIG_ICPLUS_PHY=y
-# CONFIG_IDE is not set
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IPV6_NDISC_NODETYPE=y
-# CONFIG_IPW2100 is not set
-# CONFIG_IPW2200 is not set
-CONFIG_IRQ_CPU=y
-# CONFIG_IWLWIFI_LEDS is not set
-# CONFIG_LEDS_ALIX is not set
-CONFIG_LEDS_GPIO=y
-# CONFIG_LEMOTE_FULONG is not set
-CONFIG_LZO_COMPRESS=m
-CONFIG_LZO_DECOMPRESS=m
-# CONFIG_MACH_ALCHEMY is not set
-# CONFIG_MACH_DECSTATION is not set
-# CONFIG_MACH_JAZZ is not set
-# CONFIG_MACH_VR41XX is not set
-# CONFIG_MDIO_BITBANG is not set
-CONFIG_MIPS=y
-# CONFIG_MIPS_ATLAS is not set
-# CONFIG_MIPS_COBALT is not set
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-# CONFIG_MIPS_MALTA is not set
-CONFIG_MIPS_MT_DISABLED=y
-# CONFIG_MIPS_MT_SMP is not set
-# CONFIG_MIPS_MT_SMTC is not set
-# CONFIG_MIPS_SEAD is not set
-# CONFIG_MIPS_SIM is not set
-CONFIG_MTD=y
-# CONFIG_MTD_ABSENT is not set
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_MTD_BLOCK2MTD is not set
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_AMDSTD=y
-# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
-# CONFIG_MTD_CFI_GEOMETRY is not set
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-# CONFIG_MTD_CFI_INTELEXT is not set
-# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
-CONFIG_MTD_CFI_NOSWAP=y
-# CONFIG_MTD_CFI_STAA is not set
-CONFIG_MTD_CFI_UTIL=y
-CONFIG_MTD_CHAR=y
-# CONFIG_MTD_CMDLINE_PARTS is not set
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-# CONFIG_MTD_CONCAT is not set
-# CONFIG_MTD_DEBUG is not set
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-CONFIG_MTD_GEN_PROBE=y
-# CONFIG_MTD_JEDECPROBE is not set
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_ONENAND is not set
-# CONFIG_MTD_OTP is not set
-CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_PCI is not set
-# CONFIG_MTD_PHRAM is not set
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_BANKWIDTH=0
-CONFIG_MTD_PHYSMAP_LEN=0x0
-CONFIG_MTD_PHYSMAP_START=0x0
-# CONFIG_MTD_PLATRAM is not set
-# CONFIG_MTD_PMC551 is not set
-# CONFIG_MTD_RAM is not set
-CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-3
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_REDBOOT_PARTS_READONLY=y
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_SLRAM is not set
-CONFIG_MTD_SPIFLASH=y
-CONFIG_MVSWITCH_PHY=y
-# CONFIG_NET_PCI is not set
-# CONFIG_NET_VENDOR_3COM is not set
-# CONFIG_NO_IOPORT is not set
-# CONFIG_OCF_OCF is not set
-CONFIG_PAGEFLAGS_EXTENDED=y
-# CONFIG_PAGE_SIZE_16KB is not set
-CONFIG_PAGE_SIZE_4KB=y
-# CONFIG_PAGE_SIZE_64KB is not set
-# CONFIG_PAGE_SIZE_8KB is not set
-CONFIG_PCI=y
-# CONFIG_PCIPCWATCHDOG is not set
-CONFIG_PCI_DOMAINS=y
-# CONFIG_PCSPKR_PLATFORM is not set
-CONFIG_PHYLIB=y
-# CONFIG_PMC_MSP is not set
-# CONFIG_PMC_YOSEMITE is not set
-# CONFIG_PNX8550_JBS is not set
-# CONFIG_PNX8550_STB810 is not set
-# CONFIG_PRISM54 is not set
-# CONFIG_QSEMI_PHY is not set
-# CONFIG_REALTEK_PHY is not set
-CONFIG_RFKILL_LEDS=y
-CONFIG_RTC_LIB=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
-CONFIG_SCSI_WAIT_SCAN=m
-# CONFIG_SERIAL_8250_EXTENDED is not set
-CONFIG_SERIAL_8250_NR_UARTS=1
-CONFIG_SERIAL_8250_RUNTIME_UARTS=1
-# CONFIG_SGI_IP22 is not set
-# CONFIG_SGI_IP27 is not set
-# CONFIG_SGI_IP28 is not set
-# CONFIG_SGI_IP32 is not set
-# CONFIG_SIBYTE_BIGSUR is not set
-# CONFIG_SIBYTE_CARMEL is not set
-# CONFIG_SIBYTE_CRHINE is not set
-# CONFIG_SIBYTE_CRHONE is not set
-# CONFIG_SIBYTE_LITTLESUR is not set
-# CONFIG_SIBYTE_RHONE is not set
-# CONFIG_SIBYTE_SENTOSA is not set
-# CONFIG_SIBYTE_SWARM is not set
-CONFIG_SLABINFO=y
-# CONFIG_SMSC_PHY is not set
-# CONFIG_SOFT_WATCHDOG is not set
-# CONFIG_SPARSEMEM_STATIC is not set
-# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
-CONFIG_SSB_POSSIBLE=y
-CONFIG_SYSVIPC_SYSCTL=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
-# CONFIG_THERMAL is not set
-# CONFIG_THERMAL_HWMON is not set
-CONFIG_TICK_ONESHOT=y
-# CONFIG_TOSHIBA_JMR3927 is not set
-# CONFIG_TOSHIBA_RBTX4927 is not set
-# CONFIG_TOSHIBA_RBTX4938 is not set
-CONFIG_TRAD_SIGNALS=y
-CONFIG_USB=m
-# CONFIG_USB_EHCI_HCD is not set
-# CONFIG_USB_ISIGHTFW is not set
-CONFIG_USB_STORAGE_CYPRESS_ATACB=y
-CONFIG_USB_SUPPORT=y
-# CONFIG_USB_UHCI_HCD is not set
-CONFIG_USB_WDM=m
-# CONFIG_VGASTATE is not set
-CONFIG_VIDEO_MEDIA=m
-CONFIG_VIDEO_V4L1=m
-CONFIG_VIDEO_V4L2=m
-CONFIG_VIDEO_V4L2_COMMON=m
-CONFIG_ZONE_DMA_FLAG=0
-CONFIG_ATHEROS_WDT=y
--- /dev/null
+CONFIG_32BIT=y
+# CONFIG_64BIT is not set
+CONFIG_AR2313=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ATHEROS=y
+CONFIG_ATHEROS_AR5312=y
+CONFIG_ATHEROS_AR5315=y
+CONFIG_ATHEROS_AR5315_PCI=y
+# CONFIG_ATM is not set
+# CONFIG_ATMEL is not set
+CONFIG_BASE_SMALL=0
+# CONFIG_BCM47XX is not set
+CONFIG_BITREVERSE=y
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_BT is not set
+CONFIG_CEVT_R4K=y
+CONFIG_CLASSIC_RCU=y
+CONFIG_CMDLINE="console=ttyS0,9600 rootfstype=squashfs,jffs2 init=/etc/preinit"
+CONFIG_CPU_BIG_ENDIAN=y
+CONFIG_CPU_HAS_LLSC=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_SYNC=y
+# CONFIG_CPU_LITTLE_ENDIAN is not set
+# CONFIG_CPU_LOONGSON2 is not set
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPS32_R1=y
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+CONFIG_CPU_MIPSR1=y
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_VR41XX is not set
+CONFIG_CSRC_R4K=y
+CONFIG_DEVPORT=y
+# CONFIG_DM9000 is not set
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_DMA_NONCOHERENT=y
+# CONFIG_E1000E_ENABLED is not set
+# CONFIG_FIXED_PHY is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
+CONFIG_GPIO_DEVICE=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+# CONFIG_HAVE_DMA_ATTRS is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HERMES is not set
+# CONFIG_HOSTAP is not set
+CONFIG_HW_HAS_PCI=y
+CONFIG_HW_RANDOM=y
+# CONFIG_I2C is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+CONFIG_ICPLUS_PHY=y
+# CONFIG_IDE is not set
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPW2100 is not set
+# CONFIG_IPW2200 is not set
+CONFIG_IRQ_CPU=y
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_LEDS_ALIX is not set
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEMOTE_FULONG is not set
+CONFIG_LZO_COMPRESS=m
+CONFIG_LZO_DECOMPRESS=m
+# CONFIG_MACH_ALCHEMY is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_MIPS=y
+# CONFIG_MIPS_ATLAS is not set
+# CONFIG_MIPS_COBALT is not set
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+# CONFIG_MIPS_MALTA is not set
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+# CONFIG_MIPS_SEAD is not set
+# CONFIG_MIPS_SIM is not set
+CONFIG_MTD=y
+# CONFIG_MTD_ABSENT is not set
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_MTD_BLOCK2MTD is not set
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_GEOMETRY is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_CHAR=y
+# CONFIG_MTD_CMDLINE_PARTS is not set
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_CONCAT is not set
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_ONENAND is not set
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_PCI is not set
+# CONFIG_MTD_PHRAM is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_BANKWIDTH=0
+CONFIG_MTD_PHYSMAP_LEN=0x0
+CONFIG_MTD_PHYSMAP_START=0x0
+# CONFIG_MTD_PLATRAM is not set
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_RAM is not set
+CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-3
+CONFIG_MTD_REDBOOT_PARTS=y
+CONFIG_MTD_REDBOOT_PARTS_READONLY=y
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_SLRAM is not set
+CONFIG_MTD_SPIFLASH=y
+CONFIG_MVSWITCH_PHY=y
+# CONFIG_NET_PCI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NO_IOPORT is not set
+# CONFIG_OCF_OCF is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+# CONFIG_PAGE_SIZE_16KB is not set
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_64KB is not set
+# CONFIG_PAGE_SIZE_8KB is not set
+CONFIG_PCI=y
+# CONFIG_PCIPCWATCHDOG is not set
+CONFIG_PCI_DOMAINS=y
+# CONFIG_PCSPKR_PLATFORM is not set
+CONFIG_PHYLIB=y
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_PRISM54 is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+CONFIG_RFKILL_LEDS=y
+CONFIG_RTC_LIB=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_SCSI_WAIT_SCAN=m
+# CONFIG_SERIAL_8250_EXTENDED is not set
+CONFIG_SERIAL_8250_NR_UARTS=1
+CONFIG_SERIAL_8250_RUNTIME_UARTS=1
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_SWARM is not set
+CONFIG_SLABINFO=y
+# CONFIG_SMSC_PHY is not set
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SSB_POSSIBLE=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_TICK_ONESHOT=y
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_TOSHIBA_RBTX4927 is not set
+# CONFIG_TOSHIBA_RBTX4938 is not set
+CONFIG_TRAD_SIGNALS=y
+CONFIG_USB=m
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_ISIGHTFW is not set
+CONFIG_USB_STORAGE_CYPRESS_ATACB=y
+CONFIG_USB_SUPPORT=y
+# CONFIG_USB_UHCI_HCD is not set
+CONFIG_USB_WDM=m
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_MEDIA=m
+CONFIG_VIDEO_V4L1=m
+CONFIG_VIDEO_V4L2=m
+CONFIG_VIDEO_V4L2_COMMON=m
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_ATHEROS_WDT=y
+++ /dev/null
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -59,6 +59,18 @@
- help
- Support for BCM47XX based boards
-
-+config ATHEROS
-+ bool "Atheros SoC support (EXPERIMENTAL)"
-+ depends on EXPERIMENTAL
-+ select DMA_NONCOHERENT
-+ select CEVT_R4K
-+ select CSRC_R4K
-+ select IRQ_CPU
-+ select SYS_HAS_CPU_MIPS32_R1
-+ select SYS_SUPPORTS_BIG_ENDIAN
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select GENERIC_GPIO
-+
- config MIPS_COBALT
- bool "Cobalt Server"
- select CEVT_R4K
-@@ -687,6 +699,7 @@
-
- endchoice
-
-+source "arch/mips/atheros/Kconfig"
- source "arch/mips/au1000/Kconfig"
- source "arch/mips/basler/excite/Kconfig"
- source "arch/mips/jazz/Kconfig"
---- a/arch/mips/Makefile
-+++ b/arch/mips/Makefile
-@@ -276,6 +276,13 @@
- load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000
-
- #
-+# Atheros AR5312/AR2312 WiSoC
-+#
-+core-$(CONFIG_ATHEROS) += arch/mips/atheros/
-+cflags-$(CONFIG_ATHEROS) += -Iinclude/asm-mips/mach-atheros
-+load-$(CONFIG_ATHEROS) += 0xffffffff80041000
-+
-+#
- # Cobalt Server
- #
- core-$(CONFIG_MIPS_COBALT) += arch/mips/cobalt/
---- a/include/asm-mips/bootinfo.h
-+++ b/include/asm-mips/bootinfo.h
-@@ -94,6 +94,18 @@
- #define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */
- #define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */
-
-+/*
-+ * Valid machtype for group ATHEROS
-+ */
-+#define MACH_GROUP_ATHEROS 26
-+#define MACH_ATHEROS_AR5312 0
-+#define MACH_ATHEROS_AR2312 1
-+#define MACH_ATHEROS_AR2313 2
-+#define MACH_ATHEROS_AR2315 3
-+#define MACH_ATHEROS_AR2316 4
-+#define MACH_ATHEROS_AR2317 5
-+#define MACH_ATHEROS_AR2318 6
-+
- #define CL_SIZE COMMAND_LINE_SIZE
-
- extern char *system_type;
+++ /dev/null
---- a/drivers/mtd/devices/Kconfig
-+++ b/drivers/mtd/devices/Kconfig
-@@ -84,6 +84,10 @@
- help
- This option enables FAST_READ access supported by ST M25Pxx.
-
-+config MTD_SPIFLASH
-+ tristate "Atheros AR2315/6/7 SPI Flash support"
-+ depends on ATHEROS_AR5315
-+
- config MTD_SLRAM
- tristate "Uncached system RAM"
- help
---- a/drivers/mtd/devices/Makefile
-+++ b/drivers/mtd/devices/Makefile
-@@ -17,3 +17,4 @@
- obj-$(CONFIG_MTD_BLOCK2MTD) += block2mtd.o
- obj-$(CONFIG_MTD_DATAFLASH) += mtd_dataflash.o
- obj-$(CONFIG_MTD_M25P80) += m25p80.o
-+obj-$(CONFIG_MTD_SPIFLASH) += spiflash.o
+++ /dev/null
---- a/drivers/watchdog/Kconfig
-+++ b/drivers/watchdog/Kconfig
-@@ -683,6 +683,12 @@
- help
- Hardware driver for the built-in watchdog timer on TXx9 MIPS SoCs.
-
-+config ATHEROS_WDT
-+ tristate "Atheros wisoc Watchdog Timer"
-+ depends on ATHEROS
-+ help
-+ Hardware driver for the Atheros wisoc Watchdog Timer.
-+
- # PARISC Architecture
-
- # POWERPC Architecture
---- a/drivers/watchdog/Makefile
-+++ b/drivers/watchdog/Makefile
-@@ -97,6 +97,7 @@
- obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o
- obj-$(CONFIG_AR7_WDT) += ar7_wdt.o
- obj-$(CONFIG_TXX9_WDT) += txx9wdt.o
-+obj-$(CONFIG_ATHEROS_WDT) += ar2315-wtd.o
-
- # PARISC Architecture
-
+++ /dev/null
---- a/drivers/net/Kconfig
-+++ b/drivers/net/Kconfig
-@@ -367,6 +367,12 @@
- help
- Select this if your platform comes with an external 93CX6 eeprom.
-
-+config AR2313
-+ tristate "AR2313 Ethernet support"
-+ depends on NET_ETHERNET && ATHEROS
-+ help
-+ Support for the AR231x/531x ethernet controller
-+
- config MACE
- tristate "MACE (Power Mac ethernet) support"
- depends on PPC_PMAC && PPC32
---- a/drivers/net/Makefile
-+++ b/drivers/net/Makefile
-@@ -194,6 +194,7 @@
- obj-$(CONFIG_KORINA) += korina.o
- obj-$(CONFIG_MIPS_JAZZ_SONIC) += jazzsonic.o
- obj-$(CONFIG_MIPS_AU1X00_ENET) += au1000_eth.o
-+obj-$(CONFIG_AR2313) += ar2313/
- obj-$(CONFIG_MIPS_SIM_NET) += mipsnet.o
- obj-$(CONFIG_SGI_IOC3_ETH) += ioc3-eth.o
- obj-$(CONFIG_DECLANCE) += declance.o
+++ /dev/null
---- a/drivers/net/ar2313/ar2313.c
-+++ b/drivers/net/ar2313/ar2313.c
-@@ -291,7 +291,7 @@
- sp->mii_bus.write = mdiobus_write;
- sp->mii_bus.reset = mdiobus_reset;
- sp->mii_bus.name = "ar2313_eth_mii";
-- sp->mii_bus.id = 0;
-+ snprintf(sp->mii_bus.id, MII_BUS_ID_SIZE, "0");
- sp->mii_bus.irq = kmalloc(sizeof(int), GFP_KERNEL);
- *sp->mii_bus.irq = PHY_POLL;
-
+++ /dev/null
---- a/drivers/mtd/redboot.c
-+++ b/drivers/mtd/redboot.c
-@@ -62,31 +62,32 @@
- static char nullstring[] = "unallocated";
- #endif
-
-+ buf = vmalloc(master->erasesize);
-+ if (!buf)
-+ return -ENOMEM;
-+
-+ restart:
- if ( directory < 0 ) {
- offset = master->size + directory * master->erasesize;
-- while (master->block_isbad &&
-+ while (master->block_isbad &&
- master->block_isbad(master, offset)) {
- if (!offset) {
- nogood:
- printk(KERN_NOTICE "Failed to find a non-bad block to check for RedBoot partition table\n");
-+ vfree(buf);
- return -EIO;
- }
- offset -= master->erasesize;
- }
- } else {
- offset = directory * master->erasesize;
-- while (master->block_isbad &&
-+ while (master->block_isbad &&
- master->block_isbad(master, offset)) {
- offset += master->erasesize;
- if (offset == master->size)
- goto nogood;
- }
- }
-- buf = vmalloc(master->erasesize);
--
-- if (!buf)
-- return -ENOMEM;
--
- printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n",
- master->name, offset);
-
-@@ -158,6 +159,11 @@
- }
- if (i == numslots) {
- /* Didn't find it */
-+ if (offset + master->erasesize < master->size) {
-+ /* not at the end of the flash yet, maybe next block :) */
-+ directory++;
-+ goto restart;
-+ }
- printk(KERN_NOTICE "No RedBoot partition table detected in %s\n",
- master->name);
- ret = 0;
+++ /dev/null
---- a/net/core/dev.c
-+++ b/net/core/dev.c
-@@ -3786,8 +3786,8 @@
- /* Fix illegal SG+CSUM combinations. */
- if ((dev->features & NETIF_F_SG) &&
- !(dev->features & NETIF_F_ALL_CSUM)) {
-- printk(KERN_NOTICE "%s: Dropping NETIF_F_SG since no checksum feature.\n",
-- dev->name);
-+ //printk(KERN_NOTICE "%s: Dropping NETIF_F_SG since no checksum feature.\n",
-+ // dev->name);
- dev->features &= ~NETIF_F_SG;
- }
-
-@@ -3800,9 +3800,9 @@
- }
- if (dev->features & NETIF_F_UFO) {
- if (!(dev->features & NETIF_F_HW_CSUM)) {
-- printk(KERN_ERR "%s: Dropping NETIF_F_UFO since no "
-- "NETIF_F_HW_CSUM feature.\n",
-- dev->name);
-+ //printk(KERN_ERR "%s: Dropping NETIF_F_UFO since no "
-+ // "NETIF_F_HW_CSUM feature.\n",
-+ // dev->name);
- dev->features &= ~NETIF_F_UFO;
- }
- if (!(dev->features & NETIF_F_SG)) {
+++ /dev/null
---- a/drivers/net/ar2313/ar2313.c
-+++ b/drivers/net/ar2313/ar2313.c
-@@ -953,9 +953,9 @@
- ((status >> DMA_RX_LEN_SHIFT) & 0x3fff) - CRC_LEN);
-
- dev->stats.rx_bytes += skb->len;
-- skb->protocol = eth_type_trans(skb, dev);
-+
- /* pass the packet to upper layers */
-- netif_rx(skb);
-+ sp->rx(skb);
-
- skb_new->dev = dev;
- /* 16 bit align */
-@@ -1370,6 +1370,8 @@
- return PTR_ERR(phydev);
- }
-
-+ sp->rx = phydev->netif_rx;
-+
- /* mask with MAC supported features */
- phydev->supported &= (SUPPORTED_10baseT_Half
- | SUPPORTED_10baseT_Full
---- a/drivers/net/ar2313/ar2313.h
-+++ b/drivers/net/ar2313/ar2313.h
-@@ -107,6 +107,8 @@
- */
- struct ar2313_private {
- struct net_device *dev;
-+ int (*rx)(struct sk_buff *skb);
-+
- int version;
- u32 mb[2];
-
+++ /dev/null
---- a/arch/mips/kernel/cevt-r4k.c
-+++ b/arch/mips/kernel/cevt-r4k.c
-@@ -205,6 +205,7 @@
- while ((int)(read_c0_count() - cnt) <= 0)
- ; /* Wait for expiry */
-
-+ irq_disable_hazard();
- if (!c0_compare_int_pending())
- return 0;
-
+++ /dev/null
---- a/arch/mips/kernel/traps.c
-+++ b/arch/mips/kernel/traps.c
-@@ -43,6 +43,7 @@
- #include <asm/mmu_context.h>
- #include <asm/types.h>
- #include <asm/stacktrace.h>
-+#include <asm/time.h>
-
- extern asmlinkage void handle_int(void);
- extern asmlinkage void handle_tlbm(void);
-@@ -1464,6 +1465,8 @@
- */
- if (cpu_has_mips_r2) {
- cp0_compare_irq = (read_c0_intctl() >> 29) & 7;
-+ if (get_c0_compare_irq)
-+ cp0_compare_irq = get_c0_compare_irq();
- cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7;
- if (cp0_perfcount_irq == cp0_compare_irq)
- cp0_perfcount_irq = -1;
---- a/include/asm-mips/time.h
-+++ b/include/asm-mips/time.h
-@@ -53,6 +53,7 @@
- #ifdef CONFIG_CEVT_R4K
- extern int mips_clockevent_init(void);
- extern unsigned int __weak get_c0_compare_int(void);
-+extern unsigned int __weak get_c0_compare_irq(void);
- #else
- static inline int mips_clockevent_init(void)
- {
---- a/arch/mips/atheros/board.c
-+++ b/arch/mips/atheros/board.c
-@@ -205,6 +205,11 @@
- void __init plat_time_init(void) {
- board_time_init();
- }
-+
-+unsigned int __cpuinit get_c0_compare_irq(void)
-+{
-+ return CP0_LEGACY_COMPARE_IRQ;
-+}
- #endif
-
- void __init arch_init_irq(void)
--- /dev/null
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -59,6 +59,18 @@
+ help
+ Support for BCM47XX based boards
+
++config ATHEROS
++ bool "Atheros SoC support (EXPERIMENTAL)"
++ depends on EXPERIMENTAL
++ select DMA_NONCOHERENT
++ select CEVT_R4K
++ select CSRC_R4K
++ select IRQ_CPU
++ select SYS_HAS_CPU_MIPS32_R1
++ select SYS_SUPPORTS_BIG_ENDIAN
++ select SYS_SUPPORTS_32BIT_KERNEL
++ select GENERIC_GPIO
++
+ config MIPS_COBALT
+ bool "Cobalt Server"
+ select CEVT_R4K
+@@ -687,6 +699,7 @@
+
+ endchoice
+
++source "arch/mips/atheros/Kconfig"
+ source "arch/mips/au1000/Kconfig"
+ source "arch/mips/basler/excite/Kconfig"
+ source "arch/mips/jazz/Kconfig"
+--- a/arch/mips/Makefile
++++ b/arch/mips/Makefile
+@@ -276,6 +276,13 @@
+ load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000
+
+ #
++# Atheros AR5312/AR2312 WiSoC
++#
++core-$(CONFIG_ATHEROS) += arch/mips/atheros/
++cflags-$(CONFIG_ATHEROS) += -Iinclude/asm-mips/mach-atheros
++load-$(CONFIG_ATHEROS) += 0xffffffff80041000
++
++#
+ # Cobalt Server
+ #
+ core-$(CONFIG_MIPS_COBALT) += arch/mips/cobalt/
+--- a/include/asm-mips/bootinfo.h
++++ b/include/asm-mips/bootinfo.h
+@@ -94,6 +94,18 @@
+ #define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */
+ #define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */
+
++/*
++ * Valid machtype for group ATHEROS
++ */
++#define MACH_GROUP_ATHEROS 26
++#define MACH_ATHEROS_AR5312 0
++#define MACH_ATHEROS_AR2312 1
++#define MACH_ATHEROS_AR2313 2
++#define MACH_ATHEROS_AR2315 3
++#define MACH_ATHEROS_AR2316 4
++#define MACH_ATHEROS_AR2317 5
++#define MACH_ATHEROS_AR2318 6
++
+ #define CL_SIZE COMMAND_LINE_SIZE
+
+ extern char *system_type;
--- /dev/null
+--- a/drivers/mtd/devices/Kconfig
++++ b/drivers/mtd/devices/Kconfig
+@@ -84,6 +84,10 @@
+ help
+ This option enables FAST_READ access supported by ST M25Pxx.
+
++config MTD_SPIFLASH
++ tristate "Atheros AR2315/6/7 SPI Flash support"
++ depends on ATHEROS_AR5315
++
+ config MTD_SLRAM
+ tristate "Uncached system RAM"
+ help
+--- a/drivers/mtd/devices/Makefile
++++ b/drivers/mtd/devices/Makefile
+@@ -17,3 +17,4 @@
+ obj-$(CONFIG_MTD_BLOCK2MTD) += block2mtd.o
+ obj-$(CONFIG_MTD_DATAFLASH) += mtd_dataflash.o
+ obj-$(CONFIG_MTD_M25P80) += m25p80.o
++obj-$(CONFIG_MTD_SPIFLASH) += spiflash.o
--- /dev/null
+--- a/drivers/watchdog/Kconfig
++++ b/drivers/watchdog/Kconfig
+@@ -683,6 +683,12 @@
+ help
+ Hardware driver for the built-in watchdog timer on TXx9 MIPS SoCs.
+
++config ATHEROS_WDT
++ tristate "Atheros wisoc Watchdog Timer"
++ depends on ATHEROS
++ help
++ Hardware driver for the Atheros wisoc Watchdog Timer.
++
+ # PARISC Architecture
+
+ # POWERPC Architecture
+--- a/drivers/watchdog/Makefile
++++ b/drivers/watchdog/Makefile
+@@ -97,6 +97,7 @@
+ obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o
+ obj-$(CONFIG_AR7_WDT) += ar7_wdt.o
+ obj-$(CONFIG_TXX9_WDT) += txx9wdt.o
++obj-$(CONFIG_ATHEROS_WDT) += ar2315-wtd.o
+
+ # PARISC Architecture
+
--- /dev/null
+--- a/drivers/net/Kconfig
++++ b/drivers/net/Kconfig
+@@ -367,6 +367,12 @@
+ help
+ Select this if your platform comes with an external 93CX6 eeprom.
+
++config AR2313
++ tristate "AR2313 Ethernet support"
++ depends on NET_ETHERNET && ATHEROS
++ help
++ Support for the AR231x/531x ethernet controller
++
+ config MACE
+ tristate "MACE (Power Mac ethernet) support"
+ depends on PPC_PMAC && PPC32
+--- a/drivers/net/Makefile
++++ b/drivers/net/Makefile
+@@ -194,6 +194,7 @@
+ obj-$(CONFIG_KORINA) += korina.o
+ obj-$(CONFIG_MIPS_JAZZ_SONIC) += jazzsonic.o
+ obj-$(CONFIG_MIPS_AU1X00_ENET) += au1000_eth.o
++obj-$(CONFIG_AR2313) += ar2313/
+ obj-$(CONFIG_MIPS_SIM_NET) += mipsnet.o
+ obj-$(CONFIG_SGI_IOC3_ETH) += ioc3-eth.o
+ obj-$(CONFIG_DECLANCE) += declance.o
--- /dev/null
+--- a/drivers/net/ar2313/ar2313.c
++++ b/drivers/net/ar2313/ar2313.c
+@@ -291,7 +291,7 @@
+ sp->mii_bus.write = mdiobus_write;
+ sp->mii_bus.reset = mdiobus_reset;
+ sp->mii_bus.name = "ar2313_eth_mii";
+- sp->mii_bus.id = 0;
++ snprintf(sp->mii_bus.id, MII_BUS_ID_SIZE, "0");
+ sp->mii_bus.irq = kmalloc(sizeof(int), GFP_KERNEL);
+ *sp->mii_bus.irq = PHY_POLL;
+
--- /dev/null
+--- a/drivers/mtd/redboot.c
++++ b/drivers/mtd/redboot.c
+@@ -62,31 +62,32 @@
+ static char nullstring[] = "unallocated";
+ #endif
+
++ buf = vmalloc(master->erasesize);
++ if (!buf)
++ return -ENOMEM;
++
++ restart:
+ if ( directory < 0 ) {
+ offset = master->size + directory * master->erasesize;
+- while (master->block_isbad &&
++ while (master->block_isbad &&
+ master->block_isbad(master, offset)) {
+ if (!offset) {
+ nogood:
+ printk(KERN_NOTICE "Failed to find a non-bad block to check for RedBoot partition table\n");
++ vfree(buf);
+ return -EIO;
+ }
+ offset -= master->erasesize;
+ }
+ } else {
+ offset = directory * master->erasesize;
+- while (master->block_isbad &&
++ while (master->block_isbad &&
+ master->block_isbad(master, offset)) {
+ offset += master->erasesize;
+ if (offset == master->size)
+ goto nogood;
+ }
+ }
+- buf = vmalloc(master->erasesize);
+-
+- if (!buf)
+- return -ENOMEM;
+-
+ printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n",
+ master->name, offset);
+
+@@ -158,6 +159,11 @@
+ }
+ if (i == numslots) {
+ /* Didn't find it */
++ if (offset + master->erasesize < master->size) {
++ /* not at the end of the flash yet, maybe next block :) */
++ directory++;
++ goto restart;
++ }
+ printk(KERN_NOTICE "No RedBoot partition table detected in %s\n",
+ master->name);
+ ret = 0;
--- /dev/null
+--- a/net/core/dev.c
++++ b/net/core/dev.c
+@@ -3786,8 +3786,8 @@
+ /* Fix illegal SG+CSUM combinations. */
+ if ((dev->features & NETIF_F_SG) &&
+ !(dev->features & NETIF_F_ALL_CSUM)) {
+- printk(KERN_NOTICE "%s: Dropping NETIF_F_SG since no checksum feature.\n",
+- dev->name);
++ //printk(KERN_NOTICE "%s: Dropping NETIF_F_SG since no checksum feature.\n",
++ // dev->name);
+ dev->features &= ~NETIF_F_SG;
+ }
+
+@@ -3800,9 +3800,9 @@
+ }
+ if (dev->features & NETIF_F_UFO) {
+ if (!(dev->features & NETIF_F_HW_CSUM)) {
+- printk(KERN_ERR "%s: Dropping NETIF_F_UFO since no "
+- "NETIF_F_HW_CSUM feature.\n",
+- dev->name);
++ //printk(KERN_ERR "%s: Dropping NETIF_F_UFO since no "
++ // "NETIF_F_HW_CSUM feature.\n",
++ // dev->name);
+ dev->features &= ~NETIF_F_UFO;
+ }
+ if (!(dev->features & NETIF_F_SG)) {
--- /dev/null
+--- a/drivers/net/ar2313/ar2313.c
++++ b/drivers/net/ar2313/ar2313.c
+@@ -953,9 +953,9 @@
+ ((status >> DMA_RX_LEN_SHIFT) & 0x3fff) - CRC_LEN);
+
+ dev->stats.rx_bytes += skb->len;
+- skb->protocol = eth_type_trans(skb, dev);
++
+ /* pass the packet to upper layers */
+- netif_rx(skb);
++ sp->rx(skb);
+
+ skb_new->dev = dev;
+ /* 16 bit align */
+@@ -1370,6 +1370,8 @@
+ return PTR_ERR(phydev);
+ }
+
++ sp->rx = phydev->netif_rx;
++
+ /* mask with MAC supported features */
+ phydev->supported &= (SUPPORTED_10baseT_Half
+ | SUPPORTED_10baseT_Full
+--- a/drivers/net/ar2313/ar2313.h
++++ b/drivers/net/ar2313/ar2313.h
+@@ -107,6 +107,8 @@
+ */
+ struct ar2313_private {
+ struct net_device *dev;
++ int (*rx)(struct sk_buff *skb);
++
+ int version;
+ u32 mb[2];
+
--- /dev/null
+--- a/arch/mips/kernel/cevt-r4k.c
++++ b/arch/mips/kernel/cevt-r4k.c
+@@ -205,6 +205,7 @@
+ while ((int)(read_c0_count() - cnt) <= 0)
+ ; /* Wait for expiry */
+
++ irq_disable_hazard();
+ if (!c0_compare_int_pending())
+ return 0;
+
--- /dev/null
+--- a/arch/mips/kernel/traps.c
++++ b/arch/mips/kernel/traps.c
+@@ -43,6 +43,7 @@
+ #include <asm/mmu_context.h>
+ #include <asm/types.h>
+ #include <asm/stacktrace.h>
++#include <asm/time.h>
+
+ extern asmlinkage void handle_int(void);
+ extern asmlinkage void handle_tlbm(void);
+@@ -1464,6 +1465,8 @@
+ */
+ if (cpu_has_mips_r2) {
+ cp0_compare_irq = (read_c0_intctl() >> 29) & 7;
++ if (get_c0_compare_irq)
++ cp0_compare_irq = get_c0_compare_irq();
+ cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7;
+ if (cp0_perfcount_irq == cp0_compare_irq)
+ cp0_perfcount_irq = -1;
+--- a/include/asm-mips/time.h
++++ b/include/asm-mips/time.h
+@@ -53,6 +53,7 @@
+ #ifdef CONFIG_CEVT_R4K
+ extern int mips_clockevent_init(void);
+ extern unsigned int __weak get_c0_compare_int(void);
++extern unsigned int __weak get_c0_compare_irq(void);
+ #else
+ static inline int mips_clockevent_init(void)
+ {
+--- a/arch/mips/atheros/board.c
++++ b/arch/mips/atheros/board.c
+@@ -205,6 +205,11 @@
+ void __init plat_time_init(void) {
+ board_time_init();
+ }
++
++unsigned int __cpuinit get_c0_compare_irq(void)
++{
++ return CP0_LEGACY_COMPARE_IRQ;
++}
+ #endif
+
+ void __init arch_init_irq(void)
+++ /dev/null
-CONFIG_32BIT=y
-# CONFIG_64BIT is not set
-CONFIG_64BIT_PHYS_ADDR=y
-# CONFIG_8139TOO is not set
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_ARCH_POPULATES_NODE_MAP=y
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-CONFIG_ARCH_SUPPORTS_OPROFILE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-# CONFIG_ATM is not set
-CONFIG_BASE_SMALL=0
-# CONFIG_BCM47XX is not set
-CONFIG_BITREVERSE=y
-# CONFIG_BROADCOM_PHY is not set
-CONFIG_CEVT_R4K=y
-CONFIG_CHR_DEV_SG=m
-CONFIG_CLASSIC_RCU=y
-CONFIG_CMDLINE="root=/dev/mtdblock0 rootfstype=squashfs,jffs2 init=/etc/preinit"
-# CONFIG_CPU_BIG_ENDIAN is not set
-CONFIG_CPU_HAS_LLSC=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-# CONFIG_CPU_LOONGSON2 is not set
-CONFIG_CPU_MIPS32=y
-CONFIG_CPU_MIPS32_R1=y
-# CONFIG_CPU_MIPS32_R2 is not set
-# CONFIG_CPU_MIPS64_R1 is not set
-# CONFIG_CPU_MIPS64_R2 is not set
-CONFIG_CPU_MIPSR1=y
-# CONFIG_CPU_NEVADA is not set
-# CONFIG_CPU_R10000 is not set
-# CONFIG_CPU_R3000 is not set
-# CONFIG_CPU_R4300 is not set
-# CONFIG_CPU_R4X00 is not set
-# CONFIG_CPU_R5000 is not set
-# CONFIG_CPU_R5432 is not set
-# CONFIG_CPU_R6000 is not set
-# CONFIG_CPU_R8000 is not set
-# CONFIG_CPU_RM7000 is not set
-# CONFIG_CPU_RM9000 is not set
-# CONFIG_CPU_SB1 is not set
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-# CONFIG_CPU_TX39XX is not set
-# CONFIG_CPU_TX49XX is not set
-# CONFIG_CPU_VR41XX is not set
-CONFIG_CRAMFS=m
-CONFIG_CRC16=y
-CONFIG_CRYPTO_AEAD=m
-CONFIG_CRYPTO_AUTHENC=m
-CONFIG_CRYPTO_GF128MUL=m
-CONFIG_CSRC_R4K=y
-CONFIG_DEVPORT=y
-# CONFIG_DM9000 is not set
-CONFIG_DMA_NEED_PCI_MAP_STATE=y
-CONFIG_DMA_NONCOHERENT=y
-CONFIG_DUMMY=m
-# CONFIG_E1000E_ENABLED is not set
-CONFIG_ELF_CORE=y
-# CONFIG_FIXED_PHY is not set
-CONFIG_FS_POSIX_ACL=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_FIND_NEXT_BIT=y
-CONFIG_GENERIC_GPIO=y
-# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
-# CONFIG_HAMRADIO is not set
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAVE_IDE=y
-# CONFIG_HAVE_KPROBES is not set
-# CONFIG_HAVE_KRETPROBES is not set
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HID=m
-CONFIG_HID_SUPPORT=y
-CONFIG_HW_HAS_PCI=y
-CONFIG_HW_RANDOM=y
-CONFIG_HZ=250
-# CONFIG_HZ_100 is not set
-CONFIG_HZ_250=y
-CONFIG_I2C=m
-CONFIG_I2C_ALGOBIT=m
-CONFIG_I2C_ALGOPCA=m
-CONFIG_I2C_ALGOPCF=m
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=m
-# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_IBM_NEW_EMAC_RGMII is not set
-# CONFIG_IBM_NEW_EMAC_TAH is not set
-# CONFIG_IBM_NEW_EMAC_ZMII is not set
-# CONFIG_IDE is not set
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQ_CPU=y
-CONFIG_KEXEC=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_GPIO=y
-# CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_KEYBOARD_STOWAWAY is not set
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_LEDS_ALIX is not set
-CONFIG_LEDS_GPIO=y
-# CONFIG_LEDS_TRIGGERS is not set
-# CONFIG_LEMOTE_FULONG is not set
-CONFIG_LZO_COMPRESS=m
-CONFIG_LZO_DECOMPRESS=m
-CONFIG_MACH_ALCHEMY=y
-# CONFIG_MACH_DECSTATION is not set
-# CONFIG_MACH_JAZZ is not set
-# CONFIG_MACH_VR41XX is not set
-CONFIG_MAGIC_SYSRQ=y
-# CONFIG_MDIO_BITBANG is not set
-# CONFIG_MEMSTICK is not set
-CONFIG_MIPS=y
-# CONFIG_MIPS_ATLAS is not set
-CONFIG_MIPS_AU1X00_ENET=y
-# CONFIG_MIPS_BOSPORUS is not set
-# CONFIG_MIPS_COBALT is not set
-# CONFIG_MIPS_DB1000 is not set
-# CONFIG_MIPS_DB1100 is not set
-# CONFIG_MIPS_DB1200 is not set
-# CONFIG_MIPS_DB1500 is not set
-# CONFIG_MIPS_DB1550 is not set
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-# CONFIG_MIPS_MALTA is not set
-# CONFIG_MIPS_MIRAGE is not set
-CONFIG_MIPS_MTX1=y
-CONFIG_MIPS_MT_DISABLED=y
-# CONFIG_MIPS_MT_SMP is not set
-# CONFIG_MIPS_MT_SMTC is not set
-# CONFIG_MIPS_PB1000 is not set
-# CONFIG_MIPS_PB1100 is not set
-# CONFIG_MIPS_PB1200 is not set
-# CONFIG_MIPS_PB1500 is not set
-# CONFIG_MIPS_PB1550 is not set
-# CONFIG_MIPS_SEAD is not set
-# CONFIG_MIPS_SIM is not set
-# CONFIG_MIPS_XXS1500 is not set
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MTD=y
-# CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_ALCHEMY is not set
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_MTD_BLOCK2MTD is not set
-CONFIG_MTD_CFI=y
-# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-# CONFIG_MTD_CFI_INTELEXT is not set
-# CONFIG_MTD_CFI_STAA is not set
-CONFIG_MTD_CFI_UTIL=y
-CONFIG_MTD_CHAR=y
-# CONFIG_MTD_CMDLINE_PARTS is not set
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-CONFIG_MTD_CONCAT=y
-# CONFIG_MTD_DEBUG is not set
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-CONFIG_MTD_GEN_PROBE=y
-# CONFIG_MTD_JEDECPROBE is not set
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MTDRAM is not set
-CONFIG_MTD_MTX1=y
-# CONFIG_MTD_ONENAND is not set
-CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_PHYSMAP is not set
-# CONFIG_MTD_PLATRAM is not set
-# CONFIG_MTD_PMC551 is not set
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_NATSEMI is not set
-# CONFIG_NE2K_PCI is not set
-# CONFIG_NET_SCH_ESFQ_NFCT is not set
-# CONFIG_NET_VENDOR_3COM is not set
-CONFIG_NO_HZ=y
-# CONFIG_NO_IOPORT is not set
-# CONFIG_PAGE_SIZE_16KB is not set
-CONFIG_PAGE_SIZE_4KB=y
-# CONFIG_PAGE_SIZE_64KB is not set
-# CONFIG_PAGE_SIZE_8KB is not set
-CONFIG_PCI=y
-# CONFIG_PCIPCWATCHDOG is not set
-CONFIG_PCI_DOMAINS=y
-CONFIG_PHYLIB=y
-# CONFIG_PMC_MSP is not set
-# CONFIG_PMC_YOSEMITE is not set
-# CONFIG_PNX8550_JBS is not set
-# CONFIG_PNX8550_STB810 is not set
-# CONFIG_PPP_MPPE is not set
-# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-# CONFIG_QSEMI_PHY is not set
-# CONFIG_R6040 is not set
-# CONFIG_REALTEK_PHY is not set
-CONFIG_RESOURCES_64BIT=y
-# CONFIG_RTC is not set
-CONFIG_RTC_LIB=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
-CONFIG_SCSI_CONSTANTS=y
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_SCSI_WAIT_SCAN=m
-CONFIG_SERIAL_8250_AU1X00=y
-# CONFIG_SERIAL_8250_EXTENDED is not set
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_PCI=m
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-# CONFIG_SGI_IP22 is not set
-# CONFIG_SGI_IP27 is not set
-# CONFIG_SGI_IP28 is not set
-# CONFIG_SGI_IP32 is not set
-# CONFIG_SIBYTE_BIGSUR is not set
-# CONFIG_SIBYTE_CARMEL is not set
-# CONFIG_SIBYTE_CRHINE is not set
-# CONFIG_SIBYTE_CRHONE is not set
-# CONFIG_SIBYTE_LITTLESUR is not set
-# CONFIG_SIBYTE_RHONE is not set
-# CONFIG_SIBYTE_SENTOSA is not set
-# CONFIG_SIBYTE_SWARM is not set
-CONFIG_SLABINFO=y
-# CONFIG_SMC91X is not set
-# CONFIG_SMSC_PHY is not set
-# CONFIG_SND_AU1X00 is not set
-CONFIG_SOC_AU1500=y
-CONFIG_SOC_AU1X00=y
-CONFIG_SOFT_WATCHDOG=m
-# CONFIG_SPARSEMEM_STATIC is not set
-# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
-CONFIG_SSB_POSSIBLE=y
-# CONFIG_STANDALONE is not set
-CONFIG_SYSVIPC_SYSCTL=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_KGDB=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-# CONFIG_TC35815 is not set
-# CONFIG_THERMAL is not set
-CONFIG_TICK_ONESHOT=y
-# CONFIG_TMD_HERMES is not set
-# CONFIG_TOSHIBA_JMR3927 is not set
-# CONFIG_TOSHIBA_RBTX4927 is not set
-# CONFIG_TOSHIBA_RBTX4938 is not set
-CONFIG_TRAD_SIGNALS=y
-# CONFIG_USB_R8A66597_HCD is not set
-CONFIG_USB_SUPPORT=y
-# CONFIG_USBPCWATCHDOG is not set
-# CONFIG_VGASTATE is not set
-# CONFIG_VIA_RHINE is not set
-CONFIG_VIDEO_CAPTURE_DRIVERS=y
-CONFIG_VIDEO_V4L1=y
-CONFIG_VIDEO_V4L2_COMMON=m
-CONFIG_WDT_MTX1=y
-CONFIG_ZONE_DMA_FLAG=0
--- /dev/null
+CONFIG_32BIT=y
+# CONFIG_64BIT is not set
+CONFIG_64BIT_PHYS_ADDR=y
+# CONFIG_8139TOO is not set
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_ATM is not set
+CONFIG_BASE_SMALL=0
+# CONFIG_BCM47XX is not set
+CONFIG_BITREVERSE=y
+# CONFIG_BROADCOM_PHY is not set
+CONFIG_CEVT_R4K=y
+CONFIG_CHR_DEV_SG=m
+CONFIG_CLASSIC_RCU=y
+CONFIG_CMDLINE="root=/dev/mtdblock0 rootfstype=squashfs,jffs2 init=/etc/preinit"
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_HAS_LLSC=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+# CONFIG_CPU_LOONGSON2 is not set
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPS32_R1=y
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+CONFIG_CPU_MIPSR1=y
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_VR41XX is not set
+CONFIG_CRAMFS=m
+CONFIG_CRC16=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_AUTHENC=m
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CSRC_R4K=y
+CONFIG_DEVPORT=y
+# CONFIG_DM9000 is not set
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DUMMY=m
+# CONFIG_E1000E_ENABLED is not set
+CONFIG_ELF_CORE=y
+# CONFIG_FIXED_PHY is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
+# CONFIG_HAMRADIO is not set
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAVE_IDE=y
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HID=m
+CONFIG_HID_SUPPORT=y
+CONFIG_HW_HAS_PCI=y
+CONFIG_HW_RANDOM=y
+CONFIG_HZ=250
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+CONFIG_I2C=m
+CONFIG_I2C_ALGOBIT=m
+CONFIG_I2C_ALGOPCA=m
+CONFIG_I2C_ALGOPCF=m
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=m
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IDE is not set
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQ_CPU=y
+CONFIG_KEXEC=y
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_LEDS_ALIX is not set
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEDS_TRIGGERS is not set
+# CONFIG_LEMOTE_FULONG is not set
+CONFIG_LZO_COMPRESS=m
+CONFIG_LZO_DECOMPRESS=m
+CONFIG_MACH_ALCHEMY=y
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_MACH_VR41XX is not set
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_MDIO_BITBANG is not set
+# CONFIG_MEMSTICK is not set
+CONFIG_MIPS=y
+# CONFIG_MIPS_ATLAS is not set
+CONFIG_MIPS_AU1X00_ENET=y
+# CONFIG_MIPS_BOSPORUS is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MIPS_DB1000 is not set
+# CONFIG_MIPS_DB1100 is not set
+# CONFIG_MIPS_DB1200 is not set
+# CONFIG_MIPS_DB1500 is not set
+# CONFIG_MIPS_DB1550 is not set
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_MIRAGE is not set
+CONFIG_MIPS_MTX1=y
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+# CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1100 is not set
+# CONFIG_MIPS_PB1200 is not set
+# CONFIG_MIPS_PB1500 is not set
+# CONFIG_MIPS_PB1550 is not set
+# CONFIG_MIPS_SEAD is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_MIPS_XXS1500 is not set
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MTD=y
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_ALCHEMY is not set
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_MTD_BLOCK2MTD is not set
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_CHAR=y
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_CONCAT=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MTDRAM is not set
+CONFIG_MTD_MTX1=y
+# CONFIG_MTD_ONENAND is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_PLATRAM is not set
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_NET_SCH_ESFQ_NFCT is not set
+# CONFIG_NET_VENDOR_3COM is not set
+CONFIG_NO_HZ=y
+# CONFIG_NO_IOPORT is not set
+# CONFIG_PAGE_SIZE_16KB is not set
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_64KB is not set
+# CONFIG_PAGE_SIZE_8KB is not set
+CONFIG_PCI=y
+# CONFIG_PCIPCWATCHDOG is not set
+CONFIG_PCI_DOMAINS=y
+CONFIG_PHYLIB=y
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_PPP_MPPE is not set
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_R6040 is not set
+# CONFIG_REALTEK_PHY is not set
+CONFIG_RESOURCES_64BIT=y
+# CONFIG_RTC is not set
+CONFIG_RTC_LIB=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_SCSI_CONSTANTS=y
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_SCSI_WAIT_SCAN=m
+CONFIG_SERIAL_8250_AU1X00=y
+# CONFIG_SERIAL_8250_EXTENDED is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_PCI=m
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_SWARM is not set
+CONFIG_SLABINFO=y
+# CONFIG_SMC91X is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_SND_AU1X00 is not set
+CONFIG_SOC_AU1500=y
+CONFIG_SOC_AU1X00=y
+CONFIG_SOFT_WATCHDOG=m
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_STANDALONE is not set
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_KGDB=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+# CONFIG_TC35815 is not set
+# CONFIG_THERMAL is not set
+CONFIG_TICK_ONESHOT=y
+# CONFIG_TMD_HERMES is not set
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_TOSHIBA_RBTX4927 is not set
+# CONFIG_TOSHIBA_RBTX4938 is not set
+CONFIG_TRAD_SIGNALS=y
+# CONFIG_USB_R8A66597_HCD is not set
+CONFIG_USB_SUPPORT=y
+# CONFIG_USBPCWATCHDOG is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIA_RHINE is not set
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+CONFIG_VIDEO_V4L1=y
+CONFIG_VIDEO_V4L2_COMMON=m
+CONFIG_WDT_MTX1=y
+CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-CONFIG_32BIT=y
-# CONFIG_64BIT is not set
-# CONFIG_8139TOO is not set
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_ARCH_POPULATES_NODE_MAP=y
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-CONFIG_ARCH_SUPPORTS_OPROFILE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-# CONFIG_ARPD is not set
-# CONFIG_ATMEL is not set
-CONFIG_B44=y
-CONFIG_B44_PCI=y
-CONFIG_B44_PCICORE_AUTOSELECT=y
-CONFIG_B44_PCI_AUTOSELECT=y
-CONFIG_BASE_SMALL=0
-CONFIG_BCM47XX=y
-CONFIG_BITREVERSE=y
-# CONFIG_BONDING is not set
-# CONFIG_BSD_DISKLABEL is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_BT_HCIVHCI is not set
-CONFIG_CEVT_R4K=y
-CONFIG_CFE=y
-# CONFIG_CIFS_STATS is not set
-CONFIG_CLASSIC_RCU=y
-# CONFIG_CLS_U32_MARK is not set
-# CONFIG_CLS_U32_PERF is not set
-CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=squashfs,jffs2 init=/etc/preinit noinitrd console=ttyS0,115200"
-# CONFIG_CONFIGFS_FS is not set
-CONFIG_CONNECTOR=m
-# CONFIG_CPU_BIG_ENDIAN is not set
-CONFIG_CPU_HAS_LLSC=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-# CONFIG_CPU_LOONGSON2 is not set
-CONFIG_CPU_MIPS32=y
-CONFIG_CPU_MIPS32_R1=y
-# CONFIG_CPU_MIPS32_R2 is not set
-# CONFIG_CPU_MIPS64_R1 is not set
-# CONFIG_CPU_MIPS64_R2 is not set
-CONFIG_CPU_MIPSR1=y
-# CONFIG_CPU_NEVADA is not set
-# CONFIG_CPU_R10000 is not set
-# CONFIG_CPU_R3000 is not set
-# CONFIG_CPU_R4300 is not set
-# CONFIG_CPU_R4X00 is not set
-# CONFIG_CPU_R5000 is not set
-# CONFIG_CPU_R5432 is not set
-# CONFIG_CPU_R6000 is not set
-# CONFIG_CPU_R8000 is not set
-# CONFIG_CPU_RM7000 is not set
-# CONFIG_CPU_RM9000 is not set
-# CONFIG_CPU_SB1 is not set
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-# CONFIG_CPU_TX39XX is not set
-# CONFIG_CPU_TX49XX is not set
-# CONFIG_CPU_VR41XX is not set
-CONFIG_CRYPTO_AEAD=m
-CONFIG_CRYPTO_AUTHENC=m
-CONFIG_CRYPTO_GF128MUL=m
-CONFIG_CSRC_R4K=y
-CONFIG_DEVPORT=y
-# CONFIG_DM9000 is not set
-CONFIG_DMA_NEED_PCI_MAP_STATE=y
-CONFIG_DMA_NONCOHERENT=y
-# CONFIG_E100 is not set
-# CONFIG_E1000E_ENABLED is not set
-CONFIG_FS_POSIX_ACL=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_FIND_NEXT_BIT=y
-CONFIG_GENERIC_GPIO=y
-# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
-# CONFIG_HAMRADIO is not set
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAVE_IDE=y
-# CONFIG_HAVE_KPROBES is not set
-# CONFIG_HAVE_KRETPROBES is not set
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HID=m
-CONFIG_HW_HAS_PCI=y
-CONFIG_HW_RANDOM=y
-CONFIG_HZ=250
-# CONFIG_HZ_100 is not set
-CONFIG_HZ_250=y
-# CONFIG_I2C is not set
-# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_IBM_NEW_EMAC_RGMII is not set
-# CONFIG_IBM_NEW_EMAC_TAH is not set
-# CONFIG_IBM_NEW_EMAC_ZMII is not set
-# CONFIG_IDE is not set
-# CONFIG_IEEE80211_SOFTMAC is not set
-CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_POLLDEV=y
-# CONFIG_IP6_NF_MATCH_FRAG is not set
-# CONFIG_IP6_NF_MATCH_HL is not set
-# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set
-# CONFIG_IP6_NF_MATCH_OPTS is not set
-# CONFIG_IP6_NF_MATCH_RT is not set
-# CONFIG_IP6_NF_TARGET_HL is not set
-CONFIG_IPW2200_QOS=y
-# CONFIG_IP_ROUTE_VERBOSE is not set
-CONFIG_IRQ_CPU=y
-# CONFIG_LEDS_ALIX is not set
-CONFIG_LEDS_GPIO=y
-# CONFIG_LEMOTE_FULONG is not set
-# CONFIG_LLC2 is not set
-CONFIG_LZO_COMPRESS=m
-CONFIG_LZO_DECOMPRESS=m
-# CONFIG_MACH_ALCHEMY is not set
-# CONFIG_MACH_DECSTATION is not set
-# CONFIG_MACH_JAZZ is not set
-# CONFIG_MACH_VR41XX is not set
-# CONFIG_MEMSTICK is not set
-CONFIG_MIPS=y
-# CONFIG_MIPS_ATLAS is not set
-# CONFIG_MIPS_COBALT is not set
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-# CONFIG_MIPS_MALTA is not set
-CONFIG_MIPS_MT_DISABLED=y
-# CONFIG_MIPS_MT_SMP is not set
-# CONFIG_MIPS_MT_SMTC is not set
-# CONFIG_MIPS_SEAD is not set
-# CONFIG_MIPS_SIM is not set
-CONFIG_MTD=y
-# CONFIG_MTD_ABSENT is not set
-CONFIG_MTD_BCM47XX=y
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_MTD_BLOCK2MTD is not set
-CONFIG_MTD_CFI=y
-# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-CONFIG_MTD_CFI_INTELEXT=y
-# CONFIG_MTD_CFI_STAA is not set
-CONFIG_MTD_CFI_UTIL=y
-CONFIG_MTD_CHAR=y
-# CONFIG_MTD_CMDLINE_PARTS is not set
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-# CONFIG_MTD_CONCAT is not set
-# CONFIG_MTD_DEBUG is not set
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-CONFIG_MTD_GEN_PROBE=y
-# CONFIG_MTD_JEDECPROBE is not set
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_ONENAND is not set
-CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_PCI is not set
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_PHYSMAP is not set
-# CONFIG_MTD_PLATRAM is not set
-# CONFIG_MTD_PMC551 is not set
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_NATSEMI is not set
-# CONFIG_NE2K_PCI is not set
-# CONFIG_NET_EMATCH is not set
-# CONFIG_NET_IPGRE_BROADCAST is not set
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_NET_SCH_NETEM is not set
-# CONFIG_NET_VENDOR_3COM is not set
-# CONFIG_NO_IOPORT is not set
-# CONFIG_PAGE_SIZE_16KB is not set
-CONFIG_PAGE_SIZE_4KB=y
-# CONFIG_PAGE_SIZE_64KB is not set
-# CONFIG_PAGE_SIZE_8KB is not set
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-# CONFIG_PMC_MSP is not set
-# CONFIG_PMC_YOSEMITE is not set
-# CONFIG_PNX8550_JBS is not set
-# CONFIG_PNX8550_STB810 is not set
-# CONFIG_PPP_MULTILINK is not set
-# CONFIG_PPP_SYNC_TTY is not set
-# CONFIG_PROC_KCORE is not set
-# CONFIG_R6040 is not set
-CONFIG_RFKILL=y
-CONFIG_RFKILL_INPUT=y
-CONFIG_RFKILL_LEDS=y
-# CONFIG_RTC is not set
-CONFIG_RTC_LIB=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
-# CONFIG_SCSI_MULTI_LUN is not set
-CONFIG_SCSI_WAIT_SCAN=m
-# CONFIG_SERIAL_8250_DETECT_IRQ is not set
-CONFIG_SERIAL_8250_EXTENDED=y
-# CONFIG_SERIAL_8250_MANY_PORTS is not set
-# CONFIG_SERIAL_8250_RSA is not set
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-# CONFIG_SGI_IP22 is not set
-# CONFIG_SGI_IP27 is not set
-# CONFIG_SGI_IP28 is not set
-# CONFIG_SGI_IP32 is not set
-# CONFIG_SIBYTE_BIGSUR is not set
-# CONFIG_SIBYTE_CARMEL is not set
-# CONFIG_SIBYTE_CRHINE is not set
-# CONFIG_SIBYTE_CRHONE is not set
-# CONFIG_SIBYTE_LITTLESUR is not set
-# CONFIG_SIBYTE_RHONE is not set
-# CONFIG_SIBYTE_SENTOSA is not set
-# CONFIG_SIBYTE_SWARM is not set
-CONFIG_SLABINFO=y
-# CONFIG_SPARSEMEM_STATIC is not set
-# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
-CONFIG_SSB=y
-CONFIG_SSB_B43_PCI_BRIDGE=y
-CONFIG_SSB_DEBUG=y
-CONFIG_SSB_DRIVER_EXTIF=y
-# CONFIG_SSB_DRIVER_GIGE is not set
-CONFIG_SSB_DRIVER_MIPS=y
-CONFIG_SSB_DRIVER_PCICORE=y
-CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
-CONFIG_SSB_EMBEDDED=y
-CONFIG_SSB_PCICORE_HOSTMODE=y
-CONFIG_SSB_PCIHOST=y
-CONFIG_SSB_PCIHOST_POSSIBLE=y
-CONFIG_SSB_POSSIBLE=y
-CONFIG_SSB_SERIAL=y
-# CONFIG_SSB_SILENT is not set
-CONFIG_SYSVIPC_SYSCTL=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-# CONFIG_TC35815 is not set
-# CONFIG_THERMAL is not set
-CONFIG_TICK_ONESHOT=y
-# CONFIG_TOSHIBA_JMR3927 is not set
-# CONFIG_TOSHIBA_RBTX4927 is not set
-# CONFIG_TOSHIBA_RBTX4938 is not set
-CONFIG_TRAD_SIGNALS=y
-CONFIG_USB=m
-# CONFIG_USB_ACM is not set
-CONFIG_USB_EHCI_HCD=m
-# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
-# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
-CONFIG_USB_OHCI_HCD=m
-# CONFIG_USB_R8A66597_HCD is not set
-CONFIG_USB_SUPPORT=y
-# CONFIG_USB_UHCI_HCD is not set
-# CONFIG_VGASTATE is not set
-# CONFIG_VIA_RHINE is not set
-# CONFIG_VIDEO_DEV is not set
-# CONFIG_W1_CON is not set
-# CONFIG_WATCHDOG is not set
-CONFIG_ZONE_DMA_FLAG=0
--- /dev/null
+CONFIG_32BIT=y
+# CONFIG_64BIT is not set
+# CONFIG_8139TOO is not set
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_ARPD is not set
+# CONFIG_ATMEL is not set
+CONFIG_B44=y
+CONFIG_B44_PCI=y
+CONFIG_B44_PCICORE_AUTOSELECT=y
+CONFIG_B44_PCI_AUTOSELECT=y
+CONFIG_BASE_SMALL=0
+CONFIG_BCM47XX=y
+CONFIG_BITREVERSE=y
+# CONFIG_BONDING is not set
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_BT_HCIVHCI is not set
+CONFIG_CEVT_R4K=y
+CONFIG_CFE=y
+# CONFIG_CIFS_STATS is not set
+CONFIG_CLASSIC_RCU=y
+# CONFIG_CLS_U32_MARK is not set
+# CONFIG_CLS_U32_PERF is not set
+CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=squashfs,jffs2 init=/etc/preinit noinitrd console=ttyS0,115200"
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_CONNECTOR=m
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_HAS_LLSC=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+# CONFIG_CPU_LOONGSON2 is not set
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPS32_R1=y
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+CONFIG_CPU_MIPSR1=y
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_VR41XX is not set
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_AUTHENC=m
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CSRC_R4K=y
+CONFIG_DEVPORT=y
+# CONFIG_DM9000 is not set
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_DMA_NONCOHERENT=y
+# CONFIG_E100 is not set
+# CONFIG_E1000E_ENABLED is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
+# CONFIG_HAMRADIO is not set
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAVE_IDE=y
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HID=m
+CONFIG_HW_HAS_PCI=y
+CONFIG_HW_RANDOM=y
+CONFIG_HZ=250
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_I2C is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IDE is not set
+# CONFIG_IEEE80211_SOFTMAC is not set
+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_POLLDEV=y
+# CONFIG_IP6_NF_MATCH_FRAG is not set
+# CONFIG_IP6_NF_MATCH_HL is not set
+# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set
+# CONFIG_IP6_NF_MATCH_OPTS is not set
+# CONFIG_IP6_NF_MATCH_RT is not set
+# CONFIG_IP6_NF_TARGET_HL is not set
+CONFIG_IPW2200_QOS=y
+# CONFIG_IP_ROUTE_VERBOSE is not set
+CONFIG_IRQ_CPU=y
+# CONFIG_LEDS_ALIX is not set
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEMOTE_FULONG is not set
+# CONFIG_LLC2 is not set
+CONFIG_LZO_COMPRESS=m
+CONFIG_LZO_DECOMPRESS=m
+# CONFIG_MACH_ALCHEMY is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_MEMSTICK is not set
+CONFIG_MIPS=y
+# CONFIG_MIPS_ATLAS is not set
+# CONFIG_MIPS_COBALT is not set
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+# CONFIG_MIPS_MALTA is not set
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+# CONFIG_MIPS_SEAD is not set
+# CONFIG_MIPS_SIM is not set
+CONFIG_MTD=y
+# CONFIG_MTD_ABSENT is not set
+CONFIG_MTD_BCM47XX=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_MTD_BLOCK2MTD is not set
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_CHAR=y
+# CONFIG_MTD_CMDLINE_PARTS is not set
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_CONCAT is not set
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_ONENAND is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_PCI is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_PLATRAM is not set
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_IPGRE_BROADCAST is not set
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NET_SCH_NETEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NO_IOPORT is not set
+# CONFIG_PAGE_SIZE_16KB is not set
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_64KB is not set
+# CONFIG_PAGE_SIZE_8KB is not set
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_SYNC_TTY is not set
+# CONFIG_PROC_KCORE is not set
+# CONFIG_R6040 is not set
+CONFIG_RFKILL=y
+CONFIG_RFKILL_INPUT=y
+CONFIG_RFKILL_LEDS=y
+# CONFIG_RTC is not set
+CONFIG_RTC_LIB=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+# CONFIG_SCSI_MULTI_LUN is not set
+CONFIG_SCSI_WAIT_SCAN=m
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+CONFIG_SERIAL_8250_EXTENDED=y
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+# CONFIG_SERIAL_8250_RSA is not set
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_SWARM is not set
+CONFIG_SLABINFO=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SSB=y
+CONFIG_SSB_B43_PCI_BRIDGE=y
+CONFIG_SSB_DEBUG=y
+CONFIG_SSB_DRIVER_EXTIF=y
+# CONFIG_SSB_DRIVER_GIGE is not set
+CONFIG_SSB_DRIVER_MIPS=y
+CONFIG_SSB_DRIVER_PCICORE=y
+CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
+CONFIG_SSB_EMBEDDED=y
+CONFIG_SSB_PCICORE_HOSTMODE=y
+CONFIG_SSB_PCIHOST=y
+CONFIG_SSB_PCIHOST_POSSIBLE=y
+CONFIG_SSB_POSSIBLE=y
+CONFIG_SSB_SERIAL=y
+# CONFIG_SSB_SILENT is not set
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+# CONFIG_TC35815 is not set
+# CONFIG_THERMAL is not set
+CONFIG_TICK_ONESHOT=y
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_TOSHIBA_RBTX4927 is not set
+# CONFIG_TOSHIBA_RBTX4938 is not set
+CONFIG_TRAD_SIGNALS=y
+CONFIG_USB=m
+# CONFIG_USB_ACM is not set
+CONFIG_USB_EHCI_HCD=m
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_HCD=m
+# CONFIG_USB_R8A66597_HCD is not set
+CONFIG_USB_SUPPORT=y
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_W1_CON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-/*
- * CFE environment variable access
- *
- * Copyright 2001-2003, Broadcom Corporation
- * Copyright 2006, Felix Fietkau <nbd@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <asm/io.h>
-#include <asm/uaccess.h>
-
-#define NVRAM_SIZE (0x1ff0)
-static char _nvdata[NVRAM_SIZE];
-static char _valuestr[256];
-
-/*
- * TLV types. These codes are used in the "type-length-value"
- * encoding of the items stored in the NVRAM device (flash or EEPROM)
- *
- * The layout of the flash/nvram is as follows:
- *
- * <type> <length> <data ...> <type> <length> <data ...> <type_end>
- *
- * The type code of "ENV_TLV_TYPE_END" marks the end of the list.
- * The "length" field marks the length of the data section, not
- * including the type and length fields.
- *
- * Environment variables are stored as follows:
- *
- * <type_env> <length> <flags> <name> = <value>
- *
- * If bit 0 (low bit) is set, the length is an 8-bit value.
- * If bit 0 (low bit) is clear, the length is a 16-bit value
- *
- * Bit 7 set indicates "user" TLVs. In this case, bit 0 still
- * indicates the size of the length field.
- *
- * Flags are from the constants below:
- *
- */
-#define ENV_LENGTH_16BITS 0x00 /* for low bit */
-#define ENV_LENGTH_8BITS 0x01
-
-#define ENV_TYPE_USER 0x80
-
-#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))
-#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)
-
-/*
- * The actual TLV types we support
- */
-
-#define ENV_TLV_TYPE_END 0x00
-#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS)
-
-/*
- * Environment variable flags
- */
-
-#define ENV_FLG_NORMAL 0x00 /* normal read/write */
-#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */
-#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */
-
-#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */
-#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */
-
-
-/* *********************************************************************
- * _nvram_read(buffer,offset,length)
- *
- * Read data from the NVRAM device
- *
- * Input parameters:
- * buffer - destination buffer
- * offset - offset of data to read
- * length - number of bytes to read
- *
- * Return value:
- * number of bytes read, or <0 if error occured
- ********************************************************************* */
-static int
-_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)
-{
- int i;
- if (offset > NVRAM_SIZE)
- return -1;
-
- for ( i = 0; i < length; i++) {
- buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];
- }
- return length;
-}
-
-
-static char*
-_strnchr(const char *dest,int c,size_t cnt)
-{
- while (*dest && (cnt > 0)) {
- if (*dest == c) return (char *) dest;
- dest++;
- cnt--;
- }
- return NULL;
-}
-
-
-
-/*
- * Core support API: Externally visible.
- */
-
-/*
- * Get the value of an NVRAM variable
- * @param name name of variable to get
- * @return value of variable or NULL if undefined
- */
-
-char*
-cfe_env_get(unsigned char *nv_buf, char* name)
-{
- int size;
- unsigned char *buffer;
- unsigned char *ptr;
- unsigned char *envval;
- unsigned int reclen;
- unsigned int rectype;
- int offset;
- int flg;
-
- if (!strcmp(name, "nvram_type"))
- return "cfe";
-
- size = NVRAM_SIZE;
- buffer = &_nvdata[0];
-
- ptr = buffer;
- offset = 0;
-
- /* Read the record type and length */
- if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
- goto error;
- }
-
- while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) {
-
- /* Adjust pointer for TLV type */
- rectype = *(ptr);
- offset++;
- size--;
-
- /*
- * Read the length. It can be either 1 or 2 bytes
- * depending on the code
- */
- if (rectype & ENV_LENGTH_8BITS) {
- /* Read the record type and length - 8 bits */
- if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
- goto error;
- }
- reclen = *(ptr);
- size--;
- offset++;
- }
- else {
- /* Read the record type and length - 16 bits, MSB first */
- if (_nvram_read(nv_buf, ptr,offset,2) != 2) {
- goto error;
- }
- reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);
- size -= 2;
- offset += 2;
- }
-
- if (reclen > size)
- break; /* should not happen, bad NVRAM */
-
- switch (rectype) {
- case ENV_TLV_TYPE_ENV:
- /* Read the TLV data */
- if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)
- goto error;
- flg = *ptr++;
- envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));
- if (envval) {
- *envval++ = '\0';
- memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));
- _valuestr[(reclen-1)-(envval-ptr)] = '\0';
-#if 0
- printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr);
-#endif
- if(!strcmp(ptr, name)){
- return _valuestr;
- }
- if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))
- return _valuestr;
- }
- break;
-
- default:
- /* Unknown TLV type, skip it. */
- break;
- }
-
- /*
- * Advance to next TLV
- */
-
- size -= (int)reclen;
- offset += reclen;
-
- /* Read the next record type */
- ptr = buffer;
- if (_nvram_read(nv_buf, ptr,offset,1) != 1)
- goto error;
- }
-
-error:
- return NULL;
-
-}
-
+++ /dev/null
-/*
- * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#ifndef __NVRAM_H
-#define __NVRAM_H
-
-struct nvram_header {
- u32 magic;
- u32 len;
- u32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
- u32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
- u32 config_ncdl; /* ncdl values for memc */
-};
-
-struct nvram_tuple {
- char *name;
- char *value;
- struct nvram_tuple *next;
-};
-
-#define NVRAM_HEADER 0x48534C46 /* 'FLSH' */
-#define NVRAM_VERSION 1
-#define NVRAM_HEADER_SIZE 20
-#define NVRAM_SPACE 0x8000
-
-#define NVRAM_MAX_VALUE_LEN 255
-#define NVRAM_MAX_PARAM_LEN 64
-
-char *nvram_get(const char *name);
-
-#endif
+++ /dev/null
-/*
- * BCM947xx nvram variable access
- *
- * Copyright 2005, Broadcom Corporation
- * Copyright 2006, Felix Fietkau <nbd@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/ssb/ssb.h>
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <linux/interrupt.h>
-#include <linux/spinlock.h>
-#include <linux/slab.h>
-#include <asm/byteorder.h>
-#include <asm/bootinfo.h>
-#include <asm/addrspace.h>
-#include <asm/io.h>
-#include <asm/uaccess.h>
-
-#include <nvram.h>
-
-#define MB * 1048576
-extern struct ssb_bus ssb;
-
-static char nvram_buf[NVRAM_SPACE];
-static int cfe_env;
-extern char *cfe_env_get(char *nv_buf, const char *name);
-
-/* Probe for NVRAM header */
-static void __init early_nvram_init(void)
-{
- struct ssb_mipscore *mcore = &ssb.mipscore;
- struct nvram_header *header;
- int i;
- u32 base, lim, off;
- u32 *src, *dst;
-
- base = mcore->flash_window;
- lim = mcore->flash_window_size;
- cfe_env = 0;
-
-
- /* XXX: hack for supporting the CFE environment stuff on WGT634U */
- if (lim >= 8 MB) {
- src = (u32 *) KSEG1ADDR(base + 8 MB - 0x2000);
- dst = (u32 *) nvram_buf;
-
- if ((*src & 0xff00ff) == 0x000001) {
- printk("early_nvram_init: WGT634U NVRAM found.\n");
-
- for (i = 0; i < 0x1ff0; i++) {
- if (*src == 0xFFFFFFFF)
- break;
- *dst++ = *src++;
- }
- cfe_env = 1;
- return;
- }
- }
-
- off = 0x20000;
- while (off <= lim) {
- /* Windowed flash access */
- header = (struct nvram_header *) KSEG1ADDR(base + off - NVRAM_SPACE);
- if (header->magic == NVRAM_HEADER)
- goto found;
- off <<= 1;
- }
-
- /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
- header = (struct nvram_header *) KSEG1ADDR(base + 4096);
- if (header->magic == NVRAM_HEADER)
- goto found;
-
- header = (struct nvram_header *) KSEG1ADDR(base + 1024);
- if (header->magic == NVRAM_HEADER)
- goto found;
-
- return;
-
-found:
- src = (u32 *) header;
- dst = (u32 *) nvram_buf;
- for (i = 0; i < sizeof(struct nvram_header); i += 4)
- *dst++ = *src++;
- for (; i < header->len && i < NVRAM_SPACE; i += 4)
- *dst++ = le32_to_cpu(*src++);
-}
-
-char *nvram_get(const char *name)
-{
- char *var, *value, *end, *eq;
-
- if (!name)
- return NULL;
-
- if (!nvram_buf[0])
- early_nvram_init();
-
- if (cfe_env)
- return cfe_env_get(nvram_buf, name);
-
- /* Look for name=value and return value */
- var = &nvram_buf[sizeof(struct nvram_header)];
- end = nvram_buf + sizeof(nvram_buf) - 2;
- end[0] = end[1] = '\0';
- for (; *var; var = value + strlen(value) + 1) {
- if (!(eq = strchr(var, '=')))
- break;
- value = eq + 1;
- if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
- return value;
- }
-
- return NULL;
-}
-
-EXPORT_SYMBOL(nvram_get);
+++ /dev/null
-/*
- * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
- * Copyright (C) 2005 Waldemar Brodkorb <wbx@openwrt.org>
- * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
- *
- * original functions for finding root filesystem from Mike Baker
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * Copyright 2001-2003, Broadcom Corporation
- * All Rights Reserved.
- *
- * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
- * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
- * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
- *
- * Flash mapping for BCM947XX boards
- */
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/wait.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/map.h>
-#ifdef CONFIG_MTD_PARTITIONS
-#include <linux/mtd/partitions.h>
-#endif
-#include <linux/crc32.h>
-#ifdef CONFIG_SSB
-#include <linux/ssb/ssb.h>
-#endif
-#include <asm/io.h>
-
-
-#define TRX_MAGIC 0x30524448 /* "HDR0" */
-#define TRX_VERSION 1
-#define TRX_MAX_LEN 0x3A0000
-#define TRX_NO_HEADER 1 /* Do not write TRX header */
-#define TRX_GZ_FILES 0x2 /* Contains up to TRX_MAX_OFFSET individual gzip files */
-#define TRX_MAX_OFFSET 3
-
-struct trx_header {
- u32 magic; /* "HDR0" */
- u32 len; /* Length of file including header */
- u32 crc32; /* 32-bit CRC from flag_version to end of file */
- u32 flag_version; /* 0:15 flags, 16:31 version */
- u32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */
-};
-
-#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
-#define NVRAM_SPACE 0x8000
-#define WINDOW_ADDR 0x1fc00000
-#define WINDOW_SIZE 0x400000
-#define BUSWIDTH 2
-
-#ifdef CONFIG_SSB
-extern struct ssb_bus ssb_bcm47xx;
-#endif
-static struct mtd_info *bcm47xx_mtd;
-
-static void bcm47xx_map_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len)
-{
- if (len==1) {
- memcpy_fromio(to, map->virt + from, len);
- } else {
- int i;
- u16 *dest = (u16 *) to;
- u16 *src = (u16 *) (map->virt + from);
- for (i = 0; i < (len / 2); i++) {
- dest[i] = src[i];
- }
- if (len & 1)
- *((u8 *)dest+len-1) = src[i] & 0xff;
- }
-}
-
-static struct map_info bcm47xx_map = {
- name: "Physically mapped flash",
- size: WINDOW_SIZE,
- bankwidth: BUSWIDTH,
- phys: WINDOW_ADDR,
-};
-
-#ifdef CONFIG_MTD_PARTITIONS
-
-static struct mtd_partition bcm47xx_parts[] = {
- { name: "cfe", offset: 0, size: 0, mask_flags: MTD_WRITEABLE, },
- { name: "linux", offset: 0, size: 0, },
- { name: "rootfs", offset: 0, size: 0, },
- { name: "nvram", offset: 0, size: 0, },
- { name: NULL, },
-};
-
-static int __init
-find_cfe_size(struct mtd_info *mtd, size_t size)
-{
- struct trx_header *trx;
- unsigned char buf[512];
- int off;
- size_t len;
- int blocksize;
-
- trx = (struct trx_header *) buf;
-
- blocksize = mtd->erasesize;
- if (blocksize < 0x10000)
- blocksize = 0x10000;
-
- for (off = (128*1024); off < size; off += blocksize) {
- memset(buf, 0xe5, sizeof(buf));
-
- /*
- * Read into buffer
- */
- if (mtd->read(mtd, off, sizeof(buf), &len, buf) ||
- len != sizeof(buf))
- continue;
-
- /* found a TRX header */
- if (le32_to_cpu(trx->magic) == TRX_MAGIC) {
- goto found;
- }
- }
-
- printk(KERN_NOTICE
- "%s: Couldn't find bootloader size\n",
- mtd->name);
- return -1;
-
- found:
- printk(KERN_NOTICE "bootloader size: %d\n", off);
- return off;
-
-}
-
-/*
- * Copied from mtdblock.c
- *
- * Cache stuff...
- *
- * Since typical flash erasable sectors are much larger than what Linux's
- * buffer cache can handle, we must implement read-modify-write on flash
- * sectors for each block write requests. To avoid over-erasing flash sectors
- * and to speed things up, we locally cache a whole flash sector while it is
- * being written to until a different sector is required.
- */
-
-static void erase_callback(struct erase_info *done)
-{
- wait_queue_head_t *wait_q = (wait_queue_head_t *)done->priv;
- wake_up(wait_q);
-}
-
-static int erase_write (struct mtd_info *mtd, unsigned long pos,
- int len, const char *buf)
-{
- struct erase_info erase;
- DECLARE_WAITQUEUE(wait, current);
- wait_queue_head_t wait_q;
- size_t retlen;
- int ret;
-
- /*
- * First, let's erase the flash block.
- */
-
- init_waitqueue_head(&wait_q);
- erase.mtd = mtd;
- erase.callback = erase_callback;
- erase.addr = pos;
- erase.len = len;
- erase.priv = (u_long)&wait_q;
-
- set_current_state(TASK_INTERRUPTIBLE);
- add_wait_queue(&wait_q, &wait);
-
- ret = mtd->erase(mtd, &erase);
- if (ret) {
- set_current_state(TASK_RUNNING);
- remove_wait_queue(&wait_q, &wait);
- printk (KERN_WARNING "erase of region [0x%lx, 0x%x] "
- "on \"%s\" failed\n",
- pos, len, mtd->name);
- return ret;
- }
-
- schedule(); /* Wait for erase to finish. */
- remove_wait_queue(&wait_q, &wait);
-
- /*
- * Next, writhe data to flash.
- */
-
- ret = mtd->write (mtd, pos, len, &retlen, buf);
- if (ret)
- return ret;
- if (retlen != len)
- return -EIO;
- return 0;
-}
-
-
-
-
-static int __init
-find_root(struct mtd_info *mtd, size_t size, struct mtd_partition *part)
-{
- struct trx_header trx, *trx2;
- unsigned char buf[512], *block;
- int off, blocksize;
- u32 i, crc = ~0;
- size_t len;
- struct squashfs_super_block *sb = (struct squashfs_super_block *) buf;
-
- blocksize = mtd->erasesize;
- if (blocksize < 0x10000)
- blocksize = 0x10000;
-
- for (off = (128*1024); off < size; off += blocksize) {
- memset(&trx, 0xe5, sizeof(trx));
-
- /*
- * Read into buffer
- */
- if (mtd->read(mtd, off, sizeof(trx), &len, (char *) &trx) ||
- len != sizeof(trx))
- continue;
-
- /* found a TRX header */
- if (le32_to_cpu(trx.magic) == TRX_MAGIC) {
- part->offset = le32_to_cpu(trx.offsets[2]) ? :
- le32_to_cpu(trx.offsets[1]);
- part->size = le32_to_cpu(trx.len);
-
- part->size -= part->offset;
- part->offset += off;
-
- goto found;
- }
- }
-
- printk(KERN_NOTICE
- "%s: Couldn't find root filesystem\n",
- mtd->name);
- return -1;
-
- found:
- if (part->size == 0)
- return 0;
-
- if (mtd->read(mtd, part->offset, sizeof(buf), &len, buf) || len != sizeof(buf))
- return 0;
-
- /* Move the fs outside of the trx */
- part->size = 0;
-
- if (trx.len != part->offset + part->size - off) {
- /* Update the trx offsets and length */
- trx.len = part->offset + part->size - off;
-
- /* Update the trx crc32 */
- for (i = (u32) &(((struct trx_header *)NULL)->flag_version); i <= trx.len; i += sizeof(buf)) {
- if (mtd->read(mtd, off + i, sizeof(buf), &len, buf) || len != sizeof(buf))
- return 0;
- crc = crc32_le(crc, buf, min(sizeof(buf), trx.len - i));
- }
- trx.crc32 = crc;
-
- /* read first eraseblock from the trx */
- block = kmalloc(mtd->erasesize, GFP_KERNEL);
- trx2 = (struct trx_header *) block;
- if (mtd->read(mtd, off, mtd->erasesize, &len, block) || len != mtd->erasesize) {
- printk("Error accessing the first trx eraseblock\n");
- return 0;
- }
-
- printk("Updating TRX offsets and length:\n");
- printk("old trx = [0x%08x, 0x%08x, 0x%08x], len=0x%08x crc32=0x%08x\n", trx2->offsets[0], trx2->offsets[1], trx2->offsets[2], trx2->len, trx2->crc32);
- printk("new trx = [0x%08x, 0x%08x, 0x%08x], len=0x%08x crc32=0x%08x\n", trx.offsets[0], trx.offsets[1], trx.offsets[2], trx.len, trx.crc32);
-
- /* Write updated trx header to the flash */
- memcpy(block, &trx, sizeof(trx));
- if (mtd->unlock)
- mtd->unlock(mtd, off, mtd->erasesize);
- erase_write(mtd, off, mtd->erasesize, block);
- if (mtd->sync)
- mtd->sync(mtd);
- kfree(block);
- printk("Done\n");
- }
-
- return part->size;
-}
-
-struct mtd_partition * __init
-init_mtd_partitions(struct mtd_info *mtd, size_t size)
-{
- int cfe_size;
-
- if ((cfe_size = find_cfe_size(mtd,size)) < 0)
- return NULL;
-
- /* boot loader */
- bcm47xx_parts[0].offset = 0;
- bcm47xx_parts[0].size = cfe_size;
-
- /* nvram */
- if (cfe_size != 384 * 1024) {
- bcm47xx_parts[3].offset = size - ROUNDUP(NVRAM_SPACE, mtd->erasesize);
- bcm47xx_parts[3].size = ROUNDUP(NVRAM_SPACE, mtd->erasesize);
- } else {
- /* nvram (old 128kb config partition on netgear wgt634u) */
- bcm47xx_parts[3].offset = bcm47xx_parts[0].size;
- bcm47xx_parts[3].size = ROUNDUP(NVRAM_SPACE, mtd->erasesize);
- }
-
- /* linux (kernel and rootfs) */
- if (cfe_size != 384 * 1024) {
- bcm47xx_parts[1].offset = bcm47xx_parts[0].size;
- bcm47xx_parts[1].size = bcm47xx_parts[3].offset -
- bcm47xx_parts[1].offset;
- } else {
- /* do not count the elf loader, which is on one block */
- bcm47xx_parts[1].offset = bcm47xx_parts[0].size +
- bcm47xx_parts[3].size + mtd->erasesize;
- bcm47xx_parts[1].size = size -
- bcm47xx_parts[0].size -
- (2*bcm47xx_parts[3].size) -
- mtd->erasesize;
- }
-
- /* find and size rootfs */
- find_root(mtd,size,&bcm47xx_parts[2]);
- bcm47xx_parts[2].size = size - bcm47xx_parts[2].offset - bcm47xx_parts[3].size;
-
- return bcm47xx_parts;
-}
-#endif
-
-int __init init_bcm47xx_map(void)
-{
-#ifdef CONFIG_SSB
- struct ssb_mipscore *mcore = &ssb_bcm47xx.mipscore;
-#endif
- size_t size;
- int ret = 0;
-#ifdef CONFIG_MTD_PARTITIONS
- struct mtd_partition *parts;
- int i;
-#endif
-
-#ifdef CONFIG_SSB
- u32 window = mcore->flash_window;
- u32 window_size = mcore->flash_window_size;
-
- printk("flash init: 0x%08x 0x%08x\n", window, window_size);
- bcm47xx_map.phys = window;
- bcm47xx_map.size = window_size;
- bcm47xx_map.virt = ioremap_nocache(window, window_size);
-#else
- printk("flash init: 0x%08x 0x%08x\n", WINDOW_ADDR, WINDOW_SIZE);
- bcm47xx_map.virt = ioremap_nocache(WINDOW_ADDR, WINDOW_SIZE);
-#endif
-
- if (!bcm47xx_map.virt) {
- printk("Failed to ioremap\n");
- return -EIO;
- }
-
- simple_map_init(&bcm47xx_map);
-
- if (!(bcm47xx_mtd = do_map_probe("cfi_probe", &bcm47xx_map))) {
- printk("Failed to do_map_probe\n");
- iounmap((void *)bcm47xx_map.virt);
- return -ENXIO;
- }
-
- /* override copy_from routine */
- bcm47xx_map.copy_from = bcm47xx_map_copy_from;
-
- bcm47xx_mtd->owner = THIS_MODULE;
-
- size = bcm47xx_mtd->size;
-
- printk(KERN_NOTICE "Flash device: 0x%x at 0x%x\n", size, WINDOW_ADDR);
-
-#ifdef CONFIG_MTD_PARTITIONS
- parts = init_mtd_partitions(bcm47xx_mtd, size);
- for (i = 0; parts[i].name; i++);
- ret = add_mtd_partitions(bcm47xx_mtd, parts, i);
- if (ret) {
- printk(KERN_ERR "Flash: add_mtd_partitions failed\n");
- goto fail;
- }
-#endif
- return 0;
-
- fail:
- if (bcm47xx_mtd)
- map_destroy(bcm47xx_mtd);
- if (bcm47xx_map.virt)
- iounmap((void *)bcm47xx_map.virt);
- bcm47xx_map.virt = 0;
- return ret;
-}
-
-void __exit cleanup_bcm47xx_map(void)
-{
-#ifdef CONFIG_MTD_PARTITIONS
- del_mtd_partitions(bcm47xx_mtd);
-#endif
- map_destroy(bcm47xx_mtd);
- iounmap((void *)bcm47xx_map.virt);
-}
-
-module_init(init_bcm47xx_map);
-module_exit(cleanup_bcm47xx_map);
+++ /dev/null
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2005 Embedded Alley Solutions, Inc
- * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
- * Copyright (C) 2006 Michael Buesch
- */
-#ifndef __ASM_MACH_GENERIC_KERNEL_ENTRY_H
-#define __ASM_MACH_GENERIC_KERNEL_ENTRY_H
-
-/* Intentionally empty macro, used in head.S. Override in
- * arch/mips/mach-xxx/kernel-entry-init.h when necessary.
- */
- .macro kernel_entry_setup
- .endm
-
-/*
- * Do SMP slave processor setup necessary before we can savely execute C code.
- */
- .macro smp_slave_setup
- .endm
-
-
-#endif /* __ASM_MACH_GENERIC_KERNEL_ENTRY_H */
--- /dev/null
+/*
+ * CFE environment variable access
+ *
+ * Copyright 2001-2003, Broadcom Corporation
+ * Copyright 2006, Felix Fietkau <nbd@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <asm/io.h>
+#include <asm/uaccess.h>
+
+#define NVRAM_SIZE (0x1ff0)
+static char _nvdata[NVRAM_SIZE];
+static char _valuestr[256];
+
+/*
+ * TLV types. These codes are used in the "type-length-value"
+ * encoding of the items stored in the NVRAM device (flash or EEPROM)
+ *
+ * The layout of the flash/nvram is as follows:
+ *
+ * <type> <length> <data ...> <type> <length> <data ...> <type_end>
+ *
+ * The type code of "ENV_TLV_TYPE_END" marks the end of the list.
+ * The "length" field marks the length of the data section, not
+ * including the type and length fields.
+ *
+ * Environment variables are stored as follows:
+ *
+ * <type_env> <length> <flags> <name> = <value>
+ *
+ * If bit 0 (low bit) is set, the length is an 8-bit value.
+ * If bit 0 (low bit) is clear, the length is a 16-bit value
+ *
+ * Bit 7 set indicates "user" TLVs. In this case, bit 0 still
+ * indicates the size of the length field.
+ *
+ * Flags are from the constants below:
+ *
+ */
+#define ENV_LENGTH_16BITS 0x00 /* for low bit */
+#define ENV_LENGTH_8BITS 0x01
+
+#define ENV_TYPE_USER 0x80
+
+#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))
+#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)
+
+/*
+ * The actual TLV types we support
+ */
+
+#define ENV_TLV_TYPE_END 0x00
+#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS)
+
+/*
+ * Environment variable flags
+ */
+
+#define ENV_FLG_NORMAL 0x00 /* normal read/write */
+#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */
+#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */
+
+#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */
+#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */
+
+
+/* *********************************************************************
+ * _nvram_read(buffer,offset,length)
+ *
+ * Read data from the NVRAM device
+ *
+ * Input parameters:
+ * buffer - destination buffer
+ * offset - offset of data to read
+ * length - number of bytes to read
+ *
+ * Return value:
+ * number of bytes read, or <0 if error occured
+ ********************************************************************* */
+static int
+_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)
+{
+ int i;
+ if (offset > NVRAM_SIZE)
+ return -1;
+
+ for ( i = 0; i < length; i++) {
+ buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];
+ }
+ return length;
+}
+
+
+static char*
+_strnchr(const char *dest,int c,size_t cnt)
+{
+ while (*dest && (cnt > 0)) {
+ if (*dest == c) return (char *) dest;
+ dest++;
+ cnt--;
+ }
+ return NULL;
+}
+
+
+
+/*
+ * Core support API: Externally visible.
+ */
+
+/*
+ * Get the value of an NVRAM variable
+ * @param name name of variable to get
+ * @return value of variable or NULL if undefined
+ */
+
+char*
+cfe_env_get(unsigned char *nv_buf, char* name)
+{
+ int size;
+ unsigned char *buffer;
+ unsigned char *ptr;
+ unsigned char *envval;
+ unsigned int reclen;
+ unsigned int rectype;
+ int offset;
+ int flg;
+
+ if (!strcmp(name, "nvram_type"))
+ return "cfe";
+
+ size = NVRAM_SIZE;
+ buffer = &_nvdata[0];
+
+ ptr = buffer;
+ offset = 0;
+
+ /* Read the record type and length */
+ if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
+ goto error;
+ }
+
+ while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) {
+
+ /* Adjust pointer for TLV type */
+ rectype = *(ptr);
+ offset++;
+ size--;
+
+ /*
+ * Read the length. It can be either 1 or 2 bytes
+ * depending on the code
+ */
+ if (rectype & ENV_LENGTH_8BITS) {
+ /* Read the record type and length - 8 bits */
+ if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
+ goto error;
+ }
+ reclen = *(ptr);
+ size--;
+ offset++;
+ }
+ else {
+ /* Read the record type and length - 16 bits, MSB first */
+ if (_nvram_read(nv_buf, ptr,offset,2) != 2) {
+ goto error;
+ }
+ reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);
+ size -= 2;
+ offset += 2;
+ }
+
+ if (reclen > size)
+ break; /* should not happen, bad NVRAM */
+
+ switch (rectype) {
+ case ENV_TLV_TYPE_ENV:
+ /* Read the TLV data */
+ if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)
+ goto error;
+ flg = *ptr++;
+ envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));
+ if (envval) {
+ *envval++ = '\0';
+ memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));
+ _valuestr[(reclen-1)-(envval-ptr)] = '\0';
+#if 0
+ printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr);
+#endif
+ if(!strcmp(ptr, name)){
+ return _valuestr;
+ }
+ if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))
+ return _valuestr;
+ }
+ break;
+
+ default:
+ /* Unknown TLV type, skip it. */
+ break;
+ }
+
+ /*
+ * Advance to next TLV
+ */
+
+ size -= (int)reclen;
+ offset += reclen;
+
+ /* Read the next record type */
+ ptr = buffer;
+ if (_nvram_read(nv_buf, ptr,offset,1) != 1)
+ goto error;
+ }
+
+error:
+ return NULL;
+
+}
+
--- /dev/null
+/*
+ * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __NVRAM_H
+#define __NVRAM_H
+
+struct nvram_header {
+ u32 magic;
+ u32 len;
+ u32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
+ u32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
+ u32 config_ncdl; /* ncdl values for memc */
+};
+
+struct nvram_tuple {
+ char *name;
+ char *value;
+ struct nvram_tuple *next;
+};
+
+#define NVRAM_HEADER 0x48534C46 /* 'FLSH' */
+#define NVRAM_VERSION 1
+#define NVRAM_HEADER_SIZE 20
+#define NVRAM_SPACE 0x8000
+
+#define NVRAM_MAX_VALUE_LEN 255
+#define NVRAM_MAX_PARAM_LEN 64
+
+char *nvram_get(const char *name);
+
+#endif
--- /dev/null
+/*
+ * BCM947xx nvram variable access
+ *
+ * Copyright 2005, Broadcom Corporation
+ * Copyright 2006, Felix Fietkau <nbd@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/ssb/ssb.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+#include <linux/slab.h>
+#include <asm/byteorder.h>
+#include <asm/bootinfo.h>
+#include <asm/addrspace.h>
+#include <asm/io.h>
+#include <asm/uaccess.h>
+
+#include <nvram.h>
+
+#define MB * 1048576
+extern struct ssb_bus ssb;
+
+static char nvram_buf[NVRAM_SPACE];
+static int cfe_env;
+extern char *cfe_env_get(char *nv_buf, const char *name);
+
+/* Probe for NVRAM header */
+static void __init early_nvram_init(void)
+{
+ struct ssb_mipscore *mcore = &ssb.mipscore;
+ struct nvram_header *header;
+ int i;
+ u32 base, lim, off;
+ u32 *src, *dst;
+
+ base = mcore->flash_window;
+ lim = mcore->flash_window_size;
+ cfe_env = 0;
+
+
+ /* XXX: hack for supporting the CFE environment stuff on WGT634U */
+ if (lim >= 8 MB) {
+ src = (u32 *) KSEG1ADDR(base + 8 MB - 0x2000);
+ dst = (u32 *) nvram_buf;
+
+ if ((*src & 0xff00ff) == 0x000001) {
+ printk("early_nvram_init: WGT634U NVRAM found.\n");
+
+ for (i = 0; i < 0x1ff0; i++) {
+ if (*src == 0xFFFFFFFF)
+ break;
+ *dst++ = *src++;
+ }
+ cfe_env = 1;
+ return;
+ }
+ }
+
+ off = 0x20000;
+ while (off <= lim) {
+ /* Windowed flash access */
+ header = (struct nvram_header *) KSEG1ADDR(base + off - NVRAM_SPACE);
+ if (header->magic == NVRAM_HEADER)
+ goto found;
+ off <<= 1;
+ }
+
+ /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
+ header = (struct nvram_header *) KSEG1ADDR(base + 4096);
+ if (header->magic == NVRAM_HEADER)
+ goto found;
+
+ header = (struct nvram_header *) KSEG1ADDR(base + 1024);
+ if (header->magic == NVRAM_HEADER)
+ goto found;
+
+ return;
+
+found:
+ src = (u32 *) header;
+ dst = (u32 *) nvram_buf;
+ for (i = 0; i < sizeof(struct nvram_header); i += 4)
+ *dst++ = *src++;
+ for (; i < header->len && i < NVRAM_SPACE; i += 4)
+ *dst++ = le32_to_cpu(*src++);
+}
+
+char *nvram_get(const char *name)
+{
+ char *var, *value, *end, *eq;
+
+ if (!name)
+ return NULL;
+
+ if (!nvram_buf[0])
+ early_nvram_init();
+
+ if (cfe_env)
+ return cfe_env_get(nvram_buf, name);
+
+ /* Look for name=value and return value */
+ var = &nvram_buf[sizeof(struct nvram_header)];
+ end = nvram_buf + sizeof(nvram_buf) - 2;
+ end[0] = end[1] = '\0';
+ for (; *var; var = value + strlen(value) + 1) {
+ if (!(eq = strchr(var, '=')))
+ break;
+ value = eq + 1;
+ if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
+ return value;
+ }
+
+ return NULL;
+}
+
+EXPORT_SYMBOL(nvram_get);
--- /dev/null
+/*
+ * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
+ * Copyright (C) 2005 Waldemar Brodkorb <wbx@openwrt.org>
+ * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
+ *
+ * original functions for finding root filesystem from Mike Baker
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Copyright 2001-2003, Broadcom Corporation
+ * All Rights Reserved.
+ *
+ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
+ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
+ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
+ *
+ * Flash mapping for BCM947XX boards
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/wait.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+#ifdef CONFIG_MTD_PARTITIONS
+#include <linux/mtd/partitions.h>
+#endif
+#include <linux/crc32.h>
+#ifdef CONFIG_SSB
+#include <linux/ssb/ssb.h>
+#endif
+#include <asm/io.h>
+
+
+#define TRX_MAGIC 0x30524448 /* "HDR0" */
+#define TRX_VERSION 1
+#define TRX_MAX_LEN 0x3A0000
+#define TRX_NO_HEADER 1 /* Do not write TRX header */
+#define TRX_GZ_FILES 0x2 /* Contains up to TRX_MAX_OFFSET individual gzip files */
+#define TRX_MAX_OFFSET 3
+
+struct trx_header {
+ u32 magic; /* "HDR0" */
+ u32 len; /* Length of file including header */
+ u32 crc32; /* 32-bit CRC from flag_version to end of file */
+ u32 flag_version; /* 0:15 flags, 16:31 version */
+ u32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */
+};
+
+#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
+#define NVRAM_SPACE 0x8000
+#define WINDOW_ADDR 0x1fc00000
+#define WINDOW_SIZE 0x400000
+#define BUSWIDTH 2
+
+#ifdef CONFIG_SSB
+extern struct ssb_bus ssb_bcm47xx;
+#endif
+static struct mtd_info *bcm47xx_mtd;
+
+static void bcm47xx_map_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len)
+{
+ if (len==1) {
+ memcpy_fromio(to, map->virt + from, len);
+ } else {
+ int i;
+ u16 *dest = (u16 *) to;
+ u16 *src = (u16 *) (map->virt + from);
+ for (i = 0; i < (len / 2); i++) {
+ dest[i] = src[i];
+ }
+ if (len & 1)
+ *((u8 *)dest+len-1) = src[i] & 0xff;
+ }
+}
+
+static struct map_info bcm47xx_map = {
+ name: "Physically mapped flash",
+ size: WINDOW_SIZE,
+ bankwidth: BUSWIDTH,
+ phys: WINDOW_ADDR,
+};
+
+#ifdef CONFIG_MTD_PARTITIONS
+
+static struct mtd_partition bcm47xx_parts[] = {
+ { name: "cfe", offset: 0, size: 0, mask_flags: MTD_WRITEABLE, },
+ { name: "linux", offset: 0, size: 0, },
+ { name: "rootfs", offset: 0, size: 0, },
+ { name: "nvram", offset: 0, size: 0, },
+ { name: NULL, },
+};
+
+static int __init
+find_cfe_size(struct mtd_info *mtd, size_t size)
+{
+ struct trx_header *trx;
+ unsigned char buf[512];
+ int off;
+ size_t len;
+ int blocksize;
+
+ trx = (struct trx_header *) buf;
+
+ blocksize = mtd->erasesize;
+ if (blocksize < 0x10000)
+ blocksize = 0x10000;
+
+ for (off = (128*1024); off < size; off += blocksize) {
+ memset(buf, 0xe5, sizeof(buf));
+
+ /*
+ * Read into buffer
+ */
+ if (mtd->read(mtd, off, sizeof(buf), &len, buf) ||
+ len != sizeof(buf))
+ continue;
+
+ /* found a TRX header */
+ if (le32_to_cpu(trx->magic) == TRX_MAGIC) {
+ goto found;
+ }
+ }
+
+ printk(KERN_NOTICE
+ "%s: Couldn't find bootloader size\n",
+ mtd->name);
+ return -1;
+
+ found:
+ printk(KERN_NOTICE "bootloader size: %d\n", off);
+ return off;
+
+}
+
+/*
+ * Copied from mtdblock.c
+ *
+ * Cache stuff...
+ *
+ * Since typical flash erasable sectors are much larger than what Linux's
+ * buffer cache can handle, we must implement read-modify-write on flash
+ * sectors for each block write requests. To avoid over-erasing flash sectors
+ * and to speed things up, we locally cache a whole flash sector while it is
+ * being written to until a different sector is required.
+ */
+
+static void erase_callback(struct erase_info *done)
+{
+ wait_queue_head_t *wait_q = (wait_queue_head_t *)done->priv;
+ wake_up(wait_q);
+}
+
+static int erase_write (struct mtd_info *mtd, unsigned long pos,
+ int len, const char *buf)
+{
+ struct erase_info erase;
+ DECLARE_WAITQUEUE(wait, current);
+ wait_queue_head_t wait_q;
+ size_t retlen;
+ int ret;
+
+ /*
+ * First, let's erase the flash block.
+ */
+
+ init_waitqueue_head(&wait_q);
+ erase.mtd = mtd;
+ erase.callback = erase_callback;
+ erase.addr = pos;
+ erase.len = len;
+ erase.priv = (u_long)&wait_q;
+
+ set_current_state(TASK_INTERRUPTIBLE);
+ add_wait_queue(&wait_q, &wait);
+
+ ret = mtd->erase(mtd, &erase);
+ if (ret) {
+ set_current_state(TASK_RUNNING);
+ remove_wait_queue(&wait_q, &wait);
+ printk (KERN_WARNING "erase of region [0x%lx, 0x%x] "
+ "on \"%s\" failed\n",
+ pos, len, mtd->name);
+ return ret;
+ }
+
+ schedule(); /* Wait for erase to finish. */
+ remove_wait_queue(&wait_q, &wait);
+
+ /*
+ * Next, writhe data to flash.
+ */
+
+ ret = mtd->write (mtd, pos, len, &retlen, buf);
+ if (ret)
+ return ret;
+ if (retlen != len)
+ return -EIO;
+ return 0;
+}
+
+
+
+
+static int __init
+find_root(struct mtd_info *mtd, size_t size, struct mtd_partition *part)
+{
+ struct trx_header trx, *trx2;
+ unsigned char buf[512], *block;
+ int off, blocksize;
+ u32 i, crc = ~0;
+ size_t len;
+ struct squashfs_super_block *sb = (struct squashfs_super_block *) buf;
+
+ blocksize = mtd->erasesize;
+ if (blocksize < 0x10000)
+ blocksize = 0x10000;
+
+ for (off = (128*1024); off < size; off += blocksize) {
+ memset(&trx, 0xe5, sizeof(trx));
+
+ /*
+ * Read into buffer
+ */
+ if (mtd->read(mtd, off, sizeof(trx), &len, (char *) &trx) ||
+ len != sizeof(trx))
+ continue;
+
+ /* found a TRX header */
+ if (le32_to_cpu(trx.magic) == TRX_MAGIC) {
+ part->offset = le32_to_cpu(trx.offsets[2]) ? :
+ le32_to_cpu(trx.offsets[1]);
+ part->size = le32_to_cpu(trx.len);
+
+ part->size -= part->offset;
+ part->offset += off;
+
+ goto found;
+ }
+ }
+
+ printk(KERN_NOTICE
+ "%s: Couldn't find root filesystem\n",
+ mtd->name);
+ return -1;
+
+ found:
+ if (part->size == 0)
+ return 0;
+
+ if (mtd->read(mtd, part->offset, sizeof(buf), &len, buf) || len != sizeof(buf))
+ return 0;
+
+ /* Move the fs outside of the trx */
+ part->size = 0;
+
+ if (trx.len != part->offset + part->size - off) {
+ /* Update the trx offsets and length */
+ trx.len = part->offset + part->size - off;
+
+ /* Update the trx crc32 */
+ for (i = (u32) &(((struct trx_header *)NULL)->flag_version); i <= trx.len; i += sizeof(buf)) {
+ if (mtd->read(mtd, off + i, sizeof(buf), &len, buf) || len != sizeof(buf))
+ return 0;
+ crc = crc32_le(crc, buf, min(sizeof(buf), trx.len - i));
+ }
+ trx.crc32 = crc;
+
+ /* read first eraseblock from the trx */
+ block = kmalloc(mtd->erasesize, GFP_KERNEL);
+ trx2 = (struct trx_header *) block;
+ if (mtd->read(mtd, off, mtd->erasesize, &len, block) || len != mtd->erasesize) {
+ printk("Error accessing the first trx eraseblock\n");
+ return 0;
+ }
+
+ printk("Updating TRX offsets and length:\n");
+ printk("old trx = [0x%08x, 0x%08x, 0x%08x], len=0x%08x crc32=0x%08x\n", trx2->offsets[0], trx2->offsets[1], trx2->offsets[2], trx2->len, trx2->crc32);
+ printk("new trx = [0x%08x, 0x%08x, 0x%08x], len=0x%08x crc32=0x%08x\n", trx.offsets[0], trx.offsets[1], trx.offsets[2], trx.len, trx.crc32);
+
+ /* Write updated trx header to the flash */
+ memcpy(block, &trx, sizeof(trx));
+ if (mtd->unlock)
+ mtd->unlock(mtd, off, mtd->erasesize);
+ erase_write(mtd, off, mtd->erasesize, block);
+ if (mtd->sync)
+ mtd->sync(mtd);
+ kfree(block);
+ printk("Done\n");
+ }
+
+ return part->size;
+}
+
+struct mtd_partition * __init
+init_mtd_partitions(struct mtd_info *mtd, size_t size)
+{
+ int cfe_size;
+
+ if ((cfe_size = find_cfe_size(mtd,size)) < 0)
+ return NULL;
+
+ /* boot loader */
+ bcm47xx_parts[0].offset = 0;
+ bcm47xx_parts[0].size = cfe_size;
+
+ /* nvram */
+ if (cfe_size != 384 * 1024) {
+ bcm47xx_parts[3].offset = size - ROUNDUP(NVRAM_SPACE, mtd->erasesize);
+ bcm47xx_parts[3].size = ROUNDUP(NVRAM_SPACE, mtd->erasesize);
+ } else {
+ /* nvram (old 128kb config partition on netgear wgt634u) */
+ bcm47xx_parts[3].offset = bcm47xx_parts[0].size;
+ bcm47xx_parts[3].size = ROUNDUP(NVRAM_SPACE, mtd->erasesize);
+ }
+
+ /* linux (kernel and rootfs) */
+ if (cfe_size != 384 * 1024) {
+ bcm47xx_parts[1].offset = bcm47xx_parts[0].size;
+ bcm47xx_parts[1].size = bcm47xx_parts[3].offset -
+ bcm47xx_parts[1].offset;
+ } else {
+ /* do not count the elf loader, which is on one block */
+ bcm47xx_parts[1].offset = bcm47xx_parts[0].size +
+ bcm47xx_parts[3].size + mtd->erasesize;
+ bcm47xx_parts[1].size = size -
+ bcm47xx_parts[0].size -
+ (2*bcm47xx_parts[3].size) -
+ mtd->erasesize;
+ }
+
+ /* find and size rootfs */
+ find_root(mtd,size,&bcm47xx_parts[2]);
+ bcm47xx_parts[2].size = size - bcm47xx_parts[2].offset - bcm47xx_parts[3].size;
+
+ return bcm47xx_parts;
+}
+#endif
+
+int __init init_bcm47xx_map(void)
+{
+#ifdef CONFIG_SSB
+ struct ssb_mipscore *mcore = &ssb_bcm47xx.mipscore;
+#endif
+ size_t size;
+ int ret = 0;
+#ifdef CONFIG_MTD_PARTITIONS
+ struct mtd_partition *parts;
+ int i;
+#endif
+
+#ifdef CONFIG_SSB
+ u32 window = mcore->flash_window;
+ u32 window_size = mcore->flash_window_size;
+
+ printk("flash init: 0x%08x 0x%08x\n", window, window_size);
+ bcm47xx_map.phys = window;
+ bcm47xx_map.size = window_size;
+ bcm47xx_map.virt = ioremap_nocache(window, window_size);
+#else
+ printk("flash init: 0x%08x 0x%08x\n", WINDOW_ADDR, WINDOW_SIZE);
+ bcm47xx_map.virt = ioremap_nocache(WINDOW_ADDR, WINDOW_SIZE);
+#endif
+
+ if (!bcm47xx_map.virt) {
+ printk("Failed to ioremap\n");
+ return -EIO;
+ }
+
+ simple_map_init(&bcm47xx_map);
+
+ if (!(bcm47xx_mtd = do_map_probe("cfi_probe", &bcm47xx_map))) {
+ printk("Failed to do_map_probe\n");
+ iounmap((void *)bcm47xx_map.virt);
+ return -ENXIO;
+ }
+
+ /* override copy_from routine */
+ bcm47xx_map.copy_from = bcm47xx_map_copy_from;
+
+ bcm47xx_mtd->owner = THIS_MODULE;
+
+ size = bcm47xx_mtd->size;
+
+ printk(KERN_NOTICE "Flash device: 0x%x at 0x%x\n", size, WINDOW_ADDR);
+
+#ifdef CONFIG_MTD_PARTITIONS
+ parts = init_mtd_partitions(bcm47xx_mtd, size);
+ for (i = 0; parts[i].name; i++);
+ ret = add_mtd_partitions(bcm47xx_mtd, parts, i);
+ if (ret) {
+ printk(KERN_ERR "Flash: add_mtd_partitions failed\n");
+ goto fail;
+ }
+#endif
+ return 0;
+
+ fail:
+ if (bcm47xx_mtd)
+ map_destroy(bcm47xx_mtd);
+ if (bcm47xx_map.virt)
+ iounmap((void *)bcm47xx_map.virt);
+ bcm47xx_map.virt = 0;
+ return ret;
+}
+
+void __exit cleanup_bcm47xx_map(void)
+{
+#ifdef CONFIG_MTD_PARTITIONS
+ del_mtd_partitions(bcm47xx_mtd);
+#endif
+ map_destroy(bcm47xx_mtd);
+ iounmap((void *)bcm47xx_map.virt);
+}
+
+module_init(init_bcm47xx_map);
+module_exit(cleanup_bcm47xx_map);
--- /dev/null
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005 Embedded Alley Solutions, Inc
+ * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
+ * Copyright (C) 2006 Michael Buesch
+ */
+#ifndef __ASM_MACH_GENERIC_KERNEL_ENTRY_H
+#define __ASM_MACH_GENERIC_KERNEL_ENTRY_H
+
+/* Intentionally empty macro, used in head.S. Override in
+ * arch/mips/mach-xxx/kernel-entry-init.h when necessary.
+ */
+ .macro kernel_entry_setup
+ .endm
+
+/*
+ * Do SMP slave processor setup necessary before we can savely execute C code.
+ */
+ .macro smp_slave_setup
+ .endm
+
+
+#endif /* __ASM_MACH_GENERIC_KERNEL_ENTRY_H */
+++ /dev/null
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -50,8 +50,10 @@
- select SYS_SUPPORTS_32BIT_KERNEL
- select SYS_SUPPORTS_LITTLE_ENDIAN
- select SSB
-+ select SSB_SERIAL
- select SSB_DRIVER_MIPS
- select SSB_DRIVER_EXTIF
-+ select SSB_DRIVER_PCICORE
- select SSB_PCICORE_HOSTMODE if PCI
- select GENERIC_GPIO
- select SYS_HAS_EARLY_PRINTK
-@@ -790,6 +792,7 @@
-
- config CFE
- bool
-+ # Common Firmware Environment
-
- config DMA_COHERENT
- bool
---- a/include/asm-mips/bootinfo.h
-+++ b/include/asm-mips/bootinfo.h
-@@ -94,6 +94,12 @@
- #define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */
- #define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */
-
-+/*
-+ * Valid machtype for group Broadcom
-+ */
-+#define MACH_GROUP_BRCM 23 /* Broadcom */
-+#define MACH_BCM47XX 1 /* Broadcom BCM47xx */
-+
- #define CL_SIZE COMMAND_LINE_SIZE
-
- extern char *system_type;
---- a/include/linux/pci_ids.h
-+++ b/include/linux/pci_ids.h
-@@ -2001,6 +2001,7 @@
- #define PCI_DEVICE_ID_TIGON3_5906M 0x1713
- #define PCI_DEVICE_ID_BCM4401 0x4401
- #define PCI_DEVICE_ID_BCM4401B0 0x4402
-+#define PCI_DEVICE_ID_BCM4713 0x4713
-
- #define PCI_VENDOR_ID_TOPIC 0x151f
- #define PCI_DEVICE_ID_TOPIC_TP560 0x0000
+++ /dev/null
---- a/drivers/mtd/maps/Kconfig
-+++ b/drivers/mtd/maps/Kconfig
-@@ -337,6 +337,12 @@
- Mapping for the Flaga digital module. If you don't have one, ignore
- this setting.
-
-+config MTD_BCM47XX
-+ tristate "BCM47xx flash device"
-+ depends on MIPS && MTD_CFI && BCM47XX
-+ help
-+ Support for the flash chips on the BCM947xx board.
-+
- config MTD_WALNUT
- tristate "Flash device mapped on IBM 405GP Walnut"
- depends on MTD_JEDECPROBE && WALNUT && !PPC_MERGE
---- a/drivers/mtd/maps/Makefile
-+++ b/drivers/mtd/maps/Makefile
-@@ -31,6 +31,7 @@
- obj-$(CONFIG_MTD_PCMCIA) += pcmciamtd.o
- obj-$(CONFIG_MTD_RPXLITE) += rpxlite.o
- obj-$(CONFIG_MTD_TQM8XXL) += tqm8xxl.o
-+obj-$(CONFIG_MTD_BCM47XX) += bcm47xx-flash.o
- obj-$(CONFIG_MTD_SA1100) += sa1100-flash.o
- obj-$(CONFIG_MTD_IPAQ) += ipaq-flash.o
- obj-$(CONFIG_MTD_SBC_GXX) += sbc_gxx.o
+++ /dev/null
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -228,7 +228,6 @@
- select I8259
- select MIPS_BOARDS_GEN
- select MIPS_BONITO64
-- select MIPS_CPU_SCACHE
- select PCI_GT64XXX_PCI0
- select MIPS_MSC
- select SWAP_IO_SPACE
-@@ -1421,13 +1420,6 @@
- bool
- select BOARD_SCACHE
-
--#
--# Support for a MIPS32 / MIPS64 style S-caches
--#
--config MIPS_CPU_SCACHE
-- bool
-- select BOARD_SCACHE
--
- config R5000_CPU_SCACHE
- bool
- select BOARD_SCACHE
---- a/arch/mips/kernel/cpu-probe.c
-+++ b/arch/mips/kernel/cpu-probe.c
-@@ -704,6 +704,8 @@
- break;
- case PRID_IMP_25KF:
- c->cputype = CPU_25KF;
-+ /* Probe for L2 cache */
-+ c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
- break;
- case PRID_IMP_34K:
- c->cputype = CPU_34K;
---- a/arch/mips/mm/c-r4k.c
-+++ b/arch/mips/mm/c-r4k.c
-@@ -1103,7 +1103,6 @@
-
- extern int r5k_sc_init(void);
- extern int rm7k_sc_init(void);
--extern int mips_sc_init(void);
-
- static void __cpuinit setup_scache(void)
- {
-@@ -1157,29 +1156,17 @@
- #endif
-
- default:
-- if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
-- c->isa_level == MIPS_CPU_ISA_M32R2 ||
-- c->isa_level == MIPS_CPU_ISA_M64R1 ||
-- c->isa_level == MIPS_CPU_ISA_M64R2) {
--#ifdef CONFIG_MIPS_CPU_SCACHE
-- if (mips_sc_init ()) {
-- scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
-- printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
-- scache_size >> 10,
-- way_string[c->scache.ways], c->scache.linesz);
-- }
--#else
-- if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
-- panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
--#endif
-- return;
-- }
- sc_present = 0;
- }
-
- if (!sc_present)
- return;
-
-+ if ((c->isa_level == MIPS_CPU_ISA_M32R1 ||
-+ c->isa_level == MIPS_CPU_ISA_M64R1) &&
-+ !(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
-+ panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
-+
- /* compute a couple of other cache variables */
- c->scache.waysize = scache_size / c->scache.ways;
-
---- a/arch/mips/mm/Makefile
-+++ b/arch/mips/mm/Makefile
-@@ -32,6 +32,5 @@
- obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o
- obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o
- obj-$(CONFIG_RM7000_CPU_SCACHE) += sc-rm7k.o
--obj-$(CONFIG_MIPS_CPU_SCACHE) += sc-mips.o
-
- EXTRA_CFLAGS += -Werror
+++ /dev/null
---- a/arch/mips/kernel/genex.S
-+++ b/arch/mips/kernel/genex.S
-@@ -51,6 +51,10 @@
- NESTED(except_vec3_generic, 0, sp)
- .set push
- .set noat
-+#ifdef CONFIG_BCM47XX
-+ nop
-+ nop
-+#endif
- #if R5432_CP0_INTERRUPT_WAR
- mfc0 k0, CP0_INDEX
- #endif
---- a/arch/mips/mm/c-r4k.c
-+++ b/arch/mips/mm/c-r4k.c
-@@ -33,6 +33,9 @@
- #include <asm/cacheflush.h> /* for run_uncached() */
-
-
-+/* For enabling BCM4710 cache workarounds */
-+int bcm4710 = 0;
-+
- /*
- * Special Variant of smp_call_function for use by cache functions:
- *
-@@ -97,6 +100,9 @@
- {
- unsigned long dc_lsize = cpu_dcache_line_size();
-
-+ if (bcm4710)
-+ r4k_blast_dcache_page = blast_dcache_page;
-+ else
- if (dc_lsize == 0)
- r4k_blast_dcache_page = (void *)cache_noop;
- else if (dc_lsize == 16)
-@@ -111,6 +117,9 @@
- {
- unsigned long dc_lsize = cpu_dcache_line_size();
-
-+ if (bcm4710)
-+ r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
-+ else
- if (dc_lsize == 0)
- r4k_blast_dcache_page_indexed = (void *)cache_noop;
- else if (dc_lsize == 16)
-@@ -125,6 +134,9 @@
- {
- unsigned long dc_lsize = cpu_dcache_line_size();
-
-+ if (bcm4710)
-+ r4k_blast_dcache = blast_dcache;
-+ else
- if (dc_lsize == 0)
- r4k_blast_dcache = (void *)cache_noop;
- else if (dc_lsize == 16)
-@@ -630,6 +642,8 @@
- unsigned long addr = (unsigned long) arg;
-
- R4600_HIT_CACHEOP_WAR_IMPL;
-+ BCM4710_PROTECTED_FILL_TLB(addr);
-+ BCM4710_PROTECTED_FILL_TLB(addr + 4);
- if (dc_lsize)
- protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
- if (!cpu_icache_snoops_remote_store && scache_size)
-@@ -1215,6 +1229,17 @@
- * silly idea of putting something else there ...
- */
- switch (current_cpu_type()) {
-+ case CPU_BCM3302:
-+ {
-+ u32 cm;
-+ cm = read_c0_diag();
-+ /* Enable icache */
-+ cm |= (1 << 31);
-+ /* Enable dcache */
-+ cm |= (1 << 30);
-+ write_c0_diag(cm);
-+ }
-+ break;
- case CPU_R4000PC:
- case CPU_R4000SC:
- case CPU_R4000MC:
-@@ -1254,6 +1279,15 @@
- break;
- }
-
-+ /* Check if special workarounds are required */
-+#ifdef CONFIG_BCM47XX
-+ if (current_cpu_data.cputype == CPU_BCM4710 && (current_cpu_data.processor_id & 0xff) == 0) {
-+ printk("Enabling BCM4710A0 cache workarounds.\n");
-+ bcm4710 = 1;
-+ } else
-+#endif
-+ bcm4710 = 0;
-+
- probe_pcache();
- setup_scache();
-
-@@ -1303,5 +1337,13 @@
- build_clear_page();
- build_copy_page();
- local_r4k___flush_cache_all(NULL);
-+#ifdef CONFIG_BCM47XX
-+ {
-+ static void (*_coherency_setup)(void);
-+ _coherency_setup = (void (*)(void)) KSEG1ADDR(coherency_setup);
-+ _coherency_setup();
-+ }
-+#else
- coherency_setup();
-+#endif
- }
---- a/arch/mips/mm/tlbex.c
-+++ b/arch/mips/mm/tlbex.c
-@@ -677,6 +677,9 @@
- /* No need for uasm_i_nop */
- }
-
-+#ifdef CONFIG_BCM47XX
-+ uasm_i_nop(&p);
-+#endif
- #ifdef CONFIG_64BIT
- build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
- #else
-@@ -1084,6 +1087,9 @@
- struct uasm_reloc **r, unsigned int pte,
- unsigned int ptr)
- {
-+#ifdef CONFIG_BCM47XX
-+ uasm_i_nop(p);
-+#endif
- #ifdef CONFIG_64BIT
- build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */
- #else
---- a/include/asm-mips/r4kcache.h
-+++ b/include/asm-mips/r4kcache.h
-@@ -17,6 +17,20 @@
- #include <asm/cpu-features.h>
- #include <asm/mipsmtregs.h>
-
-+#ifdef CONFIG_BCM47XX
-+#include <asm/paccess.h>
-+#include <linux/ssb/ssb.h>
-+#define BCM4710_DUMMY_RREG() ((void) *((u8 *) KSEG1ADDR(SSB_ENUM_BASE + SSB_IMSTATE)))
-+
-+#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
-+#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
-+#else
-+#define BCM4710_DUMMY_RREG()
-+
-+#define BCM4710_FILL_TLB(addr)
-+#define BCM4710_PROTECTED_FILL_TLB(addr)
-+#endif
-+
- /*
- * This macro return a properly sign-extended address suitable as base address
- * for indexed cache operations. Two issues here:
-@@ -150,6 +164,7 @@
- static inline void flush_dcache_line_indexed(unsigned long addr)
- {
- __dflush_prologue
-+ BCM4710_DUMMY_RREG();
- cache_op(Index_Writeback_Inv_D, addr);
- __dflush_epilogue
- }
-@@ -169,6 +184,7 @@
- static inline void flush_dcache_line(unsigned long addr)
- {
- __dflush_prologue
-+ BCM4710_DUMMY_RREG();
- cache_op(Hit_Writeback_Inv_D, addr);
- __dflush_epilogue
- }
-@@ -176,6 +192,7 @@
- static inline void invalidate_dcache_line(unsigned long addr)
- {
- __dflush_prologue
-+ BCM4710_DUMMY_RREG();
- cache_op(Hit_Invalidate_D, addr);
- __dflush_epilogue
- }
-@@ -208,6 +225,7 @@
- */
- static inline void protected_flush_icache_line(unsigned long addr)
- {
-+ BCM4710_DUMMY_RREG();
- protected_cache_op(Hit_Invalidate_I, addr);
- }
-
-@@ -219,6 +237,7 @@
- */
- static inline void protected_writeback_dcache_line(unsigned long addr)
- {
-+ BCM4710_DUMMY_RREG();
- protected_cache_op(Hit_Writeback_Inv_D, addr);
- }
-
-@@ -339,8 +358,52 @@
- : "r" (base), \
- "i" (op));
-
-+static inline void blast_dcache(void)
-+{
-+ unsigned long start = KSEG0;
-+ unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways;
-+ unsigned long end = (start + dcache_size);
-+
-+ do {
-+ BCM4710_DUMMY_RREG();
-+ cache_op(Index_Writeback_Inv_D, start);
-+ start += current_cpu_data.dcache.linesz;
-+ } while(start < end);
-+}
-+
-+static inline void blast_dcache_page(unsigned long page)
-+{
-+ unsigned long start = page;
-+ unsigned long end = start + PAGE_SIZE;
-+
-+ BCM4710_FILL_TLB(start);
-+ do {
-+ BCM4710_DUMMY_RREG();
-+ cache_op(Hit_Writeback_Inv_D, start);
-+ start += current_cpu_data.dcache.linesz;
-+ } while(start < end);
-+}
-+
-+static inline void blast_dcache_page_indexed(unsigned long page)
-+{
-+ unsigned long start = page;
-+ unsigned long end = start + PAGE_SIZE;
-+ unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
-+ unsigned long ws_end = current_cpu_data.dcache.ways <<
-+ current_cpu_data.dcache.waybit;
-+ unsigned long ws, addr;
-+ for (ws = 0; ws < ws_end; ws += ws_inc) {
-+ start = page + ws;
-+ for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) {
-+ BCM4710_DUMMY_RREG();
-+ cache_op(Index_Writeback_Inv_D, addr);
-+ }
-+ }
-+}
-+
-+
- /* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
--#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize) \
-+#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, war) \
- static inline void blast_##pfx##cache##lsize(void) \
- { \
- unsigned long start = INDEX_BASE; \
-@@ -352,6 +415,7 @@
- \
- __##pfx##flush_prologue \
- \
-+ war \
- for (ws = 0; ws < ws_end; ws += ws_inc) \
- for (addr = start; addr < end; addr += lsize * 32) \
- cache##lsize##_unroll32(addr|ws, indexop); \
-@@ -366,6 +430,7 @@
- \
- __##pfx##flush_prologue \
- \
-+ war \
- do { \
- cache##lsize##_unroll32(start, hitop); \
- start += lsize * 32; \
-@@ -384,6 +449,8 @@
- current_cpu_data.desc.waybit; \
- unsigned long ws, addr; \
- \
-+ war \
-+ \
- __##pfx##flush_prologue \
- \
- for (ws = 0; ws < ws_end; ws += ws_inc) \
-@@ -393,35 +460,37 @@
- __##pfx##flush_epilogue \
- }
-
--__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16)
--__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
--__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
--__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
--__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
--__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
--__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
--__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
--__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
--
--__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16)
--__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32)
--__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16)
--__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32)
--__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64)
--__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128)
-+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
-+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, BCM4710_FILL_TLB(start);)
-+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
-+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
-+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, BCM4710_FILL_TLB(start);)
-+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
-+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, BCM4710_FILL_TLB(start);)
-+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
-+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
-+
-+__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )
-+__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, )
-+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, )
-+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, )
-+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, )
-+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, )
-
- /* build blast_xxx_range, protected_blast_xxx_range */
--#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
-+#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, war, war2) \
- static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
- unsigned long end) \
- { \
- unsigned long lsize = cpu_##desc##_line_size(); \
- unsigned long addr = start & ~(lsize - 1); \
- unsigned long aend = (end - 1) & ~(lsize - 1); \
-+ war \
- \
- __##pfx##flush_prologue \
- \
- while (1) { \
-+ war2 \
- prot##cache_op(hitop, addr); \
- if (addr == aend) \
- break; \
-@@ -431,13 +500,13 @@
- __##pfx##flush_epilogue \
- }
-
--__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_)
--__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_)
--__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_)
--__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, )
--__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, )
-+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
-+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_,, )
-+__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_,, )
-+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D,, BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
-+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD,,, )
- /* blast_inv_dcache_range */
--__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, )
--__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, )
-+__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D,,,BCM4710_DUMMY_RREG();)
-+__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD,,, )
-
- #endif /* _ASM_R4KCACHE_H */
---- a/include/asm-mips/stackframe.h
-+++ b/include/asm-mips/stackframe.h
-@@ -359,6 +359,10 @@
- .macro RESTORE_SP_AND_RET
- LONG_L sp, PT_R29(sp)
- .set mips3
-+#ifdef CONFIG_BCM47XX
-+ nop
-+ nop
-+#endif
- eret
- .set mips0
- .endm
+++ /dev/null
---- a/arch/mips/mm/init.c
-+++ b/arch/mips/mm/init.c
-@@ -211,7 +211,7 @@
- void *vfrom, *vto;
-
- vto = kmap_atomic(to, KM_USER1);
-- if (cpu_has_dc_aliases &&
-+ if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
- page_mapped(from) && !Page_dcache_dirty(from)) {
- vfrom = kmap_coherent(from, vaddr);
- copy_page(vto, vfrom);
-@@ -235,7 +235,7 @@
- struct page *page, unsigned long vaddr, void *dst, const void *src,
- unsigned long len)
- {
-- if (cpu_has_dc_aliases &&
-+ if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
- page_mapped(page) && !Page_dcache_dirty(page)) {
- void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
- memcpy(vto, src, len);
-@@ -255,7 +255,7 @@
- struct page *page, unsigned long vaddr, void *dst, const void *src,
- unsigned long len)
- {
-- if (cpu_has_dc_aliases &&
-+ if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
- page_mapped(page) && !Page_dcache_dirty(page)) {
- void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
- memcpy(dst, vfrom, len);
---- /dev/null
-+++ b/include/asm-mips/mach-bcm47xx/cpu-feature-overrides.h
-@@ -0,0 +1,13 @@
-+/*
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file "COPYING" in the main directory of this archive
-+ * for more details.
-+ *
-+ * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
-+ */
-+#ifndef __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H
-+#define __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H
-+
-+#define cpu_use_kmap_coherent 0
-+
-+#endif /* __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H */
---- a/include/asm-mips/cpu-features.h
-+++ b/include/asm-mips/cpu-features.h
-@@ -101,6 +101,9 @@
- #ifndef cpu_has_pindexed_dcache
- #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
- #endif
-+#ifndef cpu_use_kmap_coherent
-+#define cpu_use_kmap_coherent 1
-+#endif
-
- /*
- * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
---- a/arch/mips/mm/c-r4k.c
-+++ b/arch/mips/mm/c-r4k.c
-@@ -484,7 +484,7 @@
- * Use kmap_coherent or kmap_atomic to do flushes for
- * another ASID than the current one.
- */
-- if (cpu_has_dc_aliases)
-+ if (cpu_has_dc_aliases && cpu_use_kmap_coherent)
- vaddr = kmap_coherent(page, addr);
- else
- vaddr = kmap_atomic(page, KM_USER0);
-@@ -505,7 +505,7 @@
- }
-
- if (vaddr) {
-- if (cpu_has_dc_aliases)
-+ if (cpu_has_dc_aliases && cpu_use_kmap_coherent)
- kunmap_coherent();
- else
- kunmap_atomic(vaddr, KM_USER0);
+++ /dev/null
-Index: linux-2.6.25.17/drivers/net/b44.c
-===================================================================
---- linux-2.6.25.17.orig/drivers/net/b44.c 2008-10-16 23:13:19.000000000 +0200
-+++ linux-2.6.25.17/drivers/net/b44.c 2008-11-02 12:13:38.000000000 +0100
-@@ -339,7 +339,7 @@ static int b44_phy_reset(struct b44 *bp)
- }
- }
-
-- return 0;
-+ return err;
- }
-
- static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags)
-@@ -384,7 +384,7 @@ static void b44_set_flow_ctrl(struct b44
- __b44_set_flow_ctrl(bp, pause_enab);
- }
-
--#ifdef SSB_DRIVER_MIPS
-+#ifdef CONFIG_SSB_DRIVER_MIPS
- extern char *nvram_get(char *name);
- static void b44_wap54g10_workaround(struct b44 *bp)
- {
-@@ -2211,6 +2211,10 @@ static int __devinit b44_init_one(struct
- */
- b44_chip_reset(bp, B44_CHIP_RESET_FULL);
-
-+ /* do a phy reset to test if there is an active phy */
-+ if (b44_phy_reset(bp) < 0)
-+ bp->phy_addr = B44_PHY_ADDR_NO_PHY;
-+
- printk(KERN_INFO "%s: Broadcom 44xx/47xx 10/100BaseT Ethernet %s\n",
- dev->name, print_mac(mac, dev->dev_addr));
-
+++ /dev/null
---- a/drivers/net/b44.c 2008-11-16 15:33:32.000000000 +0100
-+++ b/drivers/net/b44.c 2008-11-18 10:36:18.000000000 +0100
-@@ -2094,6 +2094,11 @@
- return -EINVAL;
- }
-
-+ if (bp->sdev->id.coreid == 0x806 && bp->sdev->id.revision == 0x0) {
-+ bp->phy_addr = B44_PHY_ADDR_NO_PHY;
-+ bp->dma_offset = 0;
-+ }
-+
- memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
-
- bp->imask = IMASK_DEF;
+++ /dev/null
---- a/drivers/net/b44.c
-+++ b/drivers/net/b44.c
-@@ -73,8 +73,8 @@
- (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP))
- #define NEXT_TX(N) (((N) + 1) & (B44_TX_RING_SIZE - 1))
-
--#define RX_PKT_OFFSET 30
--#define RX_PKT_BUF_SZ (1536 + RX_PKT_OFFSET + 64)
-+#define RX_PKT_OFFSET (RX_HEADER_LEN + 2)
-+#define RX_PKT_BUF_SZ (1536 + RX_PKT_OFFSET)
-
- /* minimum number of free TX descriptors required to wake up TX process */
- #define B44_TX_WAKEUP_THRESH (B44_TX_RING_SIZE / 4)
-@@ -682,7 +682,6 @@ static int b44_alloc_rx_skb(struct b44 *
- }
-
- rh = (struct rx_header *) skb->data;
-- skb_reserve(skb, RX_PKT_OFFSET);
-
- rh->len = 0;
- rh->flags = 0;
-@@ -693,13 +692,13 @@ static int b44_alloc_rx_skb(struct b44 *
- if (src_map != NULL)
- src_map->skb = NULL;
-
-- ctrl = (DESC_CTRL_LEN & (RX_PKT_BUF_SZ - RX_PKT_OFFSET));
-+ ctrl = (DESC_CTRL_LEN & RX_PKT_BUF_SZ);
- if (dest_idx == (B44_RX_RING_SIZE - 1))
- ctrl |= DESC_CTRL_EOT;
-
- dp = &bp->rx_ring[dest_idx];
- dp->ctrl = cpu_to_le32(ctrl);
-- dp->addr = cpu_to_le32((u32) mapping + RX_PKT_OFFSET + bp->dma_offset);
-+ dp->addr = cpu_to_le32((u32) mapping + bp->dma_offset);
-
- if (bp->flags & B44_FLAG_RX_RING_HACK)
- b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
-@@ -809,8 +808,8 @@ static int b44_rx(struct b44 *bp, int bu
- dma_unmap_single(bp->sdev->dma_dev, map,
- skb_size, DMA_FROM_DEVICE);
- /* Leave out rx_header */
-- skb_put(skb, len + RX_PKT_OFFSET);
-- skb_pull(skb, RX_PKT_OFFSET);
-+ skb_put(skb, len + RX_PKT_OFFSET);
-+ skb_pull(skb, RX_PKT_OFFSET);
- } else {
- struct sk_buff *copy_skb;
-
+++ /dev/null
---- a/drivers/ssb/driver_chipcommon.c
-+++ b/drivers/ssb/driver_chipcommon.c
-@@ -270,6 +270,8 @@
- void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
- u32 *plltype, u32 *n, u32 *m)
- {
-+ if ((chipco_read32(cc, SSB_CHIPCO_CHIPID) & SSB_CHIPCO_IDMASK) == 0x5354)
-+ return;
- *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
- *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
- switch (*plltype) {
-@@ -293,6 +295,8 @@
- void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
- u32 *plltype, u32 *n, u32 *m)
- {
-+ if ((chipco_read32(cc, SSB_CHIPCO_CHIPID) & SSB_CHIPCO_IDMASK) == 0x5354)
-+ return;
- *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
- *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
- switch (*plltype) {
---- a/drivers/ssb/driver_mipscore.c
-+++ b/drivers/ssb/driver_mipscore.c
-@@ -161,6 +161,8 @@
-
- if ((pll_type == SSB_PLLTYPE_5) || (bus->chip_id == 0x5365)) {
- rate = 200000000;
-+ } else if (bus->chip_id == 0x5354) {
-+ rate = 240000000;
- } else {
- rate = ssb_calc_clock_rate(pll_type, n, m);
- }
---- a/drivers/ssb/main.c
-+++ b/drivers/ssb/main.c
-@@ -867,6 +867,8 @@
-
- if (bus->chip_id == 0x5365) {
- rate = 100000000;
-+ } else if (bus->chip_id == 0x5354) {
-+ rate = 120000000;
- } else {
- rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
- if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */
+++ /dev/null
---- a/drivers/usb/host/ohci-ssb.c
-+++ b/drivers/usb/host/ohci-ssb.c
-@@ -142,10 +142,59 @@
- int err = -ENOMEM;
- u32 tmp, flags = 0;
-
-- if (dev->id.coreid == SSB_DEV_USB11_HOSTDEV)
-+ /*
-+ * THE FOLLOWING COMMENTS PRESERVED FROM GPL SOURCE RELEASE
-+ *
-+ * The USB core requires a special bit to be set during core
-+ * reset to enable host (OHCI) mode. Resetting the SB core in
-+ * pcibios_enable_device() is a hack for compatibility with
-+ * vanilla usb-ohci so that it does not have to know about
-+ * SB. A driver that wants to use the USB core in device mode
-+ * should know about SB and should reset the bit back to 0
-+ * after calling pcibios_enable_device().
-+ */
-+
-+ if (dev->id.coreid == SSB_DEV_USB11_HOSTDEV) {
- flags |= SSB_OHCI_TMSLOW_HOSTMODE;
-+ ssb_device_enable(dev, flags);
-+ }
-+
-+ /*
-+ * USB 2.0 special considerations:
-+ *
-+ * 1. Since the core supports both OHCI and EHCI functions, it must
-+ * only be reset once.
-+ *
-+ * 2. In addition to the standard SB reset sequence, the Host Control
-+ * Register must be programmed to bring the USB core and various
-+ * phy components out of reset.
-+ */
-+
-+ else if (dev->id.coreid == SSB_DEV_USB20_HOST) {
-+#warning FIX ME need test for core being up & exit
-+ ssb_device_enable(dev, 0);
-+ ssb_write32(dev, 0x200, 0x7ff);
-+ udelay(1);
-+ if (dev->id.revision == 1) { // bug in rev 1
-+
-+ /* Change Flush control reg */
-+ tmp = ssb_read32(dev, 0x400);
-+ tmp &= ~8;
-+ ssb_write32(dev, 0x400, tmp);
-+ tmp = ssb_read32(dev, 0x400);
-+ printk("USB20H fcr: 0x%0x\n", tmp);
-+
-+ /* Change Shim control reg */
-+ tmp = ssb_read32(dev, 0x304);
-+ tmp &= ~0x100;
-+ ssb_write32(dev, 0x304, tmp);
-+ tmp = ssb_read32(dev, 0x304);
-+ printk("USB20H shim: 0x%0x\n", tmp);
-+ }
-+ }
-+ else
-+ ssb_device_enable(dev, 0);
-
-- ssb_device_enable(dev, flags);
-
- hcd = usb_create_hcd(&ssb_ohci_hc_driver, dev->dev,
- dev->dev->bus_id);
-@@ -236,6 +285,7 @@
- static const struct ssb_device_id ssb_ohci_table[] = {
- SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOSTDEV, SSB_ANY_REV),
- SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOST, SSB_ANY_REV),
-+ SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB20_HOST, SSB_ANY_REV),
- SSB_DEVTABLE_END
- };
- MODULE_DEVICE_TABLE(ssb, ssb_ohci_table);
+++ /dev/null
---- a/drivers/usb/host/ohci-ssb.c
-+++ b/drivers/usb/host/ohci-ssb.c
-@@ -195,6 +195,11 @@
- else
- ssb_device_enable(dev, 0);
-
-+ /*
-+ * Set dma mask - 32 bit mask is just an assumption
-+ */
-+ if (ssb_dma_set_mask(dev, DMA_32BIT_MASK))
-+ return -EOPNOTSUPP;
-
- hcd = usb_create_hcd(&ssb_ohci_hc_driver, dev->dev,
- dev->dev->bus_id);
+++ /dev/null
---- a/include/asm-mips/cacheflush.h
-+++ b/include/asm-mips/cacheflush.h
-@@ -32,7 +32,7 @@
- extern void (*flush_cache_all)(void);
- extern void (*__flush_cache_all)(void);
- extern void (*flush_cache_mm)(struct mm_struct *mm);
--#define flush_cache_dup_mm(mm) do { (void) (mm); } while (0)
-+#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
- extern void (*flush_cache_range)(struct vm_area_struct *vma,
- unsigned long start, unsigned long end);
- extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn);
+++ /dev/null
---- a/arch/mips/mm/init.c
-+++ b/arch/mips/mm/init.c
-@@ -205,32 +205,6 @@
- preempt_check_resched();
- }
-
--void copy_user_highpage(struct page *to, struct page *from,
-- unsigned long vaddr, struct vm_area_struct *vma)
--{
-- void *vfrom, *vto;
--
-- vto = kmap_atomic(to, KM_USER1);
-- if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
-- page_mapped(from) && !Page_dcache_dirty(from)) {
-- vfrom = kmap_coherent(from, vaddr);
-- copy_page(vto, vfrom);
-- kunmap_coherent();
-- } else {
-- vfrom = kmap_atomic(from, KM_USER0);
-- copy_page(vto, vfrom);
-- kunmap_atomic(vfrom, KM_USER0);
-- }
-- if (((vma->vm_flags & VM_EXEC) && !cpu_has_ic_fills_f_dc) ||
-- pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
-- flush_data_cache_page((unsigned long)vto);
-- kunmap_atomic(vto, KM_USER1);
-- /* Make sure this page is cleared on other CPU's too before using it */
-- smp_wmb();
--}
--
--EXPORT_SYMBOL(copy_user_highpage);
--
- void copy_to_user_page(struct vm_area_struct *vma,
- struct page *page, unsigned long vaddr, void *dst, const void *src,
- unsigned long len)
---- a/include/asm-mips/page.h
-+++ b/include/asm-mips/page.h
-@@ -32,6 +32,7 @@
- #ifndef __ASSEMBLY__
-
- #include <linux/pfn.h>
-+#include <asm/cpu-features.h>
- #include <asm/io.h>
-
- /*
-@@ -64,13 +65,16 @@
- flush_data_cache_page((unsigned long)addr);
- }
-
--extern void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
-- struct page *to);
--struct vm_area_struct;
--extern void copy_user_highpage(struct page *to, struct page *from,
-- unsigned long vaddr, struct vm_area_struct *vma);
-+static inline void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
-+ struct page *to)
-+{
-+ extern void (*flush_data_cache_page)(unsigned long addr);
-
--#define __HAVE_ARCH_COPY_USER_HIGHPAGE
-+ copy_page(vto, vfrom);
-+ if (!cpu_has_ic_fills_f_dc ||
-+ pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
-+ flush_data_cache_page((unsigned long)vto);
-+}
-
- /*
- * These are used to make use of C type-checking..
+++ /dev/null
---- a/arch/mips/bcm47xx/irq.c
-+++ b/arch/mips/bcm47xx/irq.c
-@@ -1,5 +1,6 @@
- /*
- * Copyright (C) 2004 Florian Schirmer <jolt@tuxbox.org>
-+ * Copyright (C) 2008 Michael Buesch <mb@bu3sch.de>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
-@@ -23,10 +24,19 @@
- */
-
- #include <linux/types.h>
-+#include <linux/errno.h>
-+#include <linux/init.h>
- #include <linux/interrupt.h>
- #include <linux/irq.h>
-+#include <linux/pci.h>
-+#include <linux/ssb/ssb.h>
-+
- #include <asm/irq_cpu.h>
-
-+
-+extern struct ssb_bus ssb_bcm47xx;
-+
-+
- void plat_irq_dispatch(void)
- {
- u32 cause;
-@@ -53,3 +63,19 @@
- {
- mips_cpu_irq_init();
- }
-+
-+int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-+{
-+ int res;
-+
-+ res = ssb_pcibios_map_irq(dev, slot, pin);
-+ if (res < 0) {
-+ printk(KERN_ALERT "PCI: Failed to map IRQ of device %s\n",
-+ dev->dev.bus_id);
-+ return 0;
-+ }
-+ /* IRQ-0 and IRQ-1 are software interrupts. */
-+ WARN_ON((res == 0) || (res == 1));
-+
-+ return res;
-+}
---- a/arch/mips/bcm47xx/setup.c
-+++ b/arch/mips/bcm47xx/setup.c
-@@ -2,7 +2,7 @@
- * Copyright (C) 2004 Florian Schirmer <jolt@tuxbox.org>
- * Copyright (C) 2005 Waldemar Brodkorb <wbx@openwrt.org>
- * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
-- * Copyright (C) 2006 Michael Buesch <mb@bu3sch.de>
-+ * Copyright (C) 2006-2008 Michael Buesch <mb@bu3sch.de>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
-@@ -25,23 +25,52 @@
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-+#include <linux/init.h>
- #include <linux/types.h>
--#include <linux/ssb/ssb.h>
-+#include <linux/tty.h>
-+#include <linux/serial.h>
-+#include <linux/serial_core.h>
-+#include <linux/serial_reg.h>
-+#include <linux/serial_8250.h>
- #include <asm/bootinfo.h>
--#include <asm/reboot.h>
- #include <asm/time.h>
--#include <bcm47xx.h>
-+#include <asm/reboot.h>
- #include <asm/fw/cfe/cfe_api.h>
-+#include <linux/pm.h>
-+#include <linux/ssb/ssb.h>
-+#include <linux/ssb/ssb_embedded.h>
-+
-+#include "include/nvram.h"
-
- struct ssb_bus ssb_bcm47xx;
- EXPORT_SYMBOL(ssb_bcm47xx);
-
-+extern void bcm47xx_pci_init(void);
-+
-+int pcibios_plat_dev_init(struct pci_dev *dev)
-+{
-+ int err;
-+
-+ err = ssb_pcibios_plat_dev_init(dev);
-+ if (err) {
-+ printk(KERN_ALERT "PCI: Failed to init device %s\n",
-+ pci_name(dev));
-+ }
-+
-+ return err;
-+}
-+
- static void bcm47xx_machine_restart(char *command)
- {
- printk(KERN_ALERT "Please stand by while rebooting the system...\n");
- local_irq_disable();
-+ /* CFE has a reboot callback, but that does not work.
-+ * Oopses with: Reserved instruction in kernel code.
-+ */
-+
- /* Set the watchdog timer to reset immediately */
-- ssb_chipco_watchdog_timer_set(&ssb_bcm47xx.chipco, 1);
-+ if (ssb_watchdog_timer_set(&ssb_bcm47xx, 1))
-+ printk(KERN_EMERG "SSB watchdog-triggered reboot failed!\n");
- while (1)
- cpu_relax();
- }
-@@ -50,12 +79,13 @@
- {
- /* Disable interrupts and watchdog and spin forever */
- local_irq_disable();
-- ssb_chipco_watchdog_timer_set(&ssb_bcm47xx.chipco, 0);
-+ if (ssb_watchdog_timer_set(&ssb_bcm47xx, 0))
-+ printk(KERN_EMERG "Failed to disable SSB watchdog!\n");
- while (1)
- cpu_relax();
- }
-
--static void str2eaddr(char *str, char *dest)
-+static void e_aton(char *str, char *dest)
- {
- int i = 0;
-
-@@ -72,52 +102,142 @@
- }
- }
-
--static int bcm47xx_get_invariants(struct ssb_bus *bus,
-- struct ssb_init_invariants *iv)
-+static void bcm47xx_fill_sprom(struct ssb_sprom *sprom)
- {
-- char buf[100];
-+ char *s;
-
-- /* Fill boardinfo structure */
-- memset(&(iv->boardinfo), 0 , sizeof(struct ssb_boardinfo));
-+ memset(sprom, 0xFF, sizeof(struct ssb_sprom));
-
-- if (cfe_getenv("boardvendor", buf, sizeof(buf)) >= 0)
-- iv->boardinfo.type = (u16)simple_strtoul(buf, NULL, 0);
-- if (cfe_getenv("boardtype", buf, sizeof(buf)) >= 0)
-- iv->boardinfo.type = (u16)simple_strtoul(buf, NULL, 0);
-- if (cfe_getenv("boardrev", buf, sizeof(buf)) >= 0)
-- iv->boardinfo.rev = (u16)simple_strtoul(buf, NULL, 0);
--
-- /* Fill sprom structure */
-- memset(&(iv->sprom), 0, sizeof(struct ssb_sprom));
-- iv->sprom.revision = 3;
--
-- if (cfe_getenv("et0macaddr", buf, sizeof(buf)) >= 0)
-- str2eaddr(buf, iv->sprom.et0mac);
-- if (cfe_getenv("et1macaddr", buf, sizeof(buf)) >= 0)
-- str2eaddr(buf, iv->sprom.et1mac);
-- if (cfe_getenv("et0phyaddr", buf, sizeof(buf)) >= 0)
-- iv->sprom.et0phyaddr = simple_strtoul(buf, NULL, 10);
-- if (cfe_getenv("et1phyaddr", buf, sizeof(buf)) >= 0)
-- iv->sprom.et1phyaddr = simple_strtoul(buf, NULL, 10);
-- if (cfe_getenv("et0mdcport", buf, sizeof(buf)) >= 0)
-- iv->sprom.et0mdcport = simple_strtoul(buf, NULL, 10);
-- if (cfe_getenv("et1mdcport", buf, sizeof(buf)) >= 0)
-- iv->sprom.et1mdcport = simple_strtoul(buf, NULL, 10);
-+ sprom->revision = 1;
-+ if ((s = nvram_get("il0macaddr")))
-+ e_aton(s, sprom->il0mac);
-+ if ((s = nvram_get("et0macaddr")))
-+ e_aton(s, sprom->et0mac);
-+ if ((s = nvram_get("et1macaddr")))
-+ e_aton(s, sprom->et1mac);
-+ if ((s = nvram_get("et0phyaddr")))
-+ sprom->et0phyaddr = simple_strtoul(s, NULL, 0);
-+ if ((s = nvram_get("et1phyaddr")))
-+ sprom->et1phyaddr = simple_strtoul(s, NULL, 0);
-+ if ((s = nvram_get("et0mdcport")))
-+ sprom->et0mdcport = !!simple_strtoul(s, NULL, 10);
-+ if ((s = nvram_get("et1mdcport")))
-+ sprom->et1mdcport = !!simple_strtoul(s, NULL, 10);
-+ if ((s = nvram_get("pa0b0")))
-+ sprom->pa0b0 = simple_strtoul(s, NULL, 0);
-+ if ((s = nvram_get("pa0b1")))
-+ sprom->pa0b1 = simple_strtoul(s, NULL, 0);
-+ if ((s = nvram_get("pa0b2")))
-+ sprom->pa0b2 = simple_strtoul(s, NULL, 0);
-+ if ((s = nvram_get("pa1b0")))
-+ sprom->pa1b0 = simple_strtoul(s, NULL, 0);
-+ if ((s = nvram_get("pa1b1")))
-+ sprom->pa1b1 = simple_strtoul(s, NULL, 0);
-+ if ((s = nvram_get("pa1b2")))
-+ sprom->pa1b2 = simple_strtoul(s, NULL, 0);
-+ if ((s = nvram_get("wl0gpio0")))
-+ sprom->gpio0 = simple_strtoul(s, NULL, 0);
-+ if ((s = nvram_get("wl0gpio1")))
-+ sprom->gpio1 = simple_strtoul(s, NULL, 0);
-+ if ((s = nvram_get("wl0gpio2")))
-+ sprom->gpio2 = simple_strtoul(s, NULL, 0);
-+ if ((s = nvram_get("wl0gpio3")))
-+ sprom->gpio3 = simple_strtoul(s, NULL, 0);
-+ if ((s = nvram_get("pa0maxpwr")))
-+ sprom->maxpwr_bg = simple_strtoul(s, NULL, 0);
-+ if ((s = nvram_get("pa1maxpwr")))
-+ sprom->maxpwr_a = simple_strtoul(s, NULL, 0);
-+ if ((s = nvram_get("pa0itssit")))
-+ sprom->itssi_bg = simple_strtoul(s, NULL, 0);
-+ if ((s = nvram_get("pa1itssit")))
-+ sprom->itssi_a = simple_strtoul(s, NULL, 0);
-+ sprom->boardflags_lo = 0;
-+ if ((s = nvram_get("boardflags")))
-+ sprom->boardflags_lo = simple_strtoul(s, NULL, 0);
-+ sprom->boardflags_hi = 0;
-+ if ((s = nvram_get("boardflags2")))
-+ sprom->boardflags_hi = simple_strtoul(s, NULL, 0);
-+}
-+
-+static int bcm47xx_get_invariants(struct ssb_bus *bus, struct ssb_init_invariants *iv)
-+{
-+ char *s;
-+
-+ iv->boardinfo.vendor = SSB_BOARDVENDOR_BCM;
-+ if ((s = nvram_get("boardtype")))
-+ iv->boardinfo.type = (u16)simple_strtoul(s, NULL, 0);
-+ if ((s = nvram_get("boardrev")))
-+ iv->boardinfo.rev = (u16)simple_strtoul(s, NULL, 0);
-+
-+ bcm47xx_fill_sprom(&iv->sprom);
-+
-+ if ((s = nvram_get("cardbus")))
-+ iv->has_cardbus_slot = !!simple_strtoul(s, NULL, 10);
-
- return 0;
- }
-
- void __init plat_mem_setup(void)
- {
-- int err;
-+ int i, err;
-+ char *s;
-+ struct ssb_mipscore *mcore;
-+
-+ err = ssb_bus_ssbbus_register(&ssb_bcm47xx, SSB_ENUM_BASE, bcm47xx_get_invariants);
-+ if (err) {
-+ const char *msg = "Failed to initialize SSB bus (err %d)\n";
-+ printk(msg, err); /* Make sure the message gets out of the box. */
-+ panic(msg, err);
-+ }
-+ mcore = &ssb_bcm47xx.mipscore;
-+
-+ s = nvram_get("kernel_args");
-+ if (s && !strncmp(s, "console=ttyS1", 13)) {
-+ struct ssb_serial_port port;
-+
-+ printk("Swapping serial ports!\n");
-+ /* swap serial ports */
-+ memcpy(&port, &mcore->serial_ports[0], sizeof(port));
-+ memcpy(&mcore->serial_ports[0], &mcore->serial_ports[1], sizeof(port));
-+ memcpy(&mcore->serial_ports[1], &port, sizeof(port));
-+ }
-
-- err = ssb_bus_ssbbus_register(&ssb_bcm47xx, SSB_ENUM_BASE,
-- bcm47xx_get_invariants);
-- if (err)
-- panic("Failed to initialize SSB bus (err %d)\n", err);
-+ for (i = 0; i < mcore->nr_serial_ports; i++) {
-+ struct ssb_serial_port *port = &(mcore->serial_ports[i]);
-+ struct uart_port s;
-+
-+ memset(&s, 0, sizeof(s));
-+ s.line = i;
-+ s.mapbase = (unsigned int) port->regs;
-+ s.membase = port->regs;
-+ s.irq = port->irq + 2;
-+ s.uartclk = port->baud_base;
-+ s.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
-+ s.iotype = SERIAL_IO_MEM;
-+ s.regshift = port->reg_shift;
-+
-+ early_serial_setup(&s);
-+ }
-+ printk("Serial init done.\n");
-
- _machine_restart = bcm47xx_machine_restart;
- _machine_halt = bcm47xx_machine_halt;
- pm_power_off = bcm47xx_machine_halt;
- }
-
-+static int __init bcm47xx_register_gpiodev(void)
-+{
-+ static struct resource res = {
-+ .start = 0xFFFFFFFF,
-+ };
-+ struct platform_device *pdev;
-+
-+ pdev = platform_device_register_simple("GPIODEV", 0, &res, 1);
-+ if (!pdev) {
-+ printk(KERN_ERR "bcm47xx: GPIODEV init failed\n");
-+ return -ENODEV;
-+ }
-+
-+ return 0;
-+}
-+device_initcall(bcm47xx_register_gpiodev);
---- a/arch/mips/bcm47xx/time.c
-+++ b/arch/mips/bcm47xx/time.c
-@@ -22,11 +22,17 @@
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
--
- #include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/sched.h>
-+#include <linux/serial_reg.h>
-+#include <linux/interrupt.h>
- #include <linux/ssb/ssb.h>
-+#include <asm/addrspace.h>
-+#include <asm/io.h>
- #include <asm/time.h>
--#include <bcm47xx.h>
-+
-+extern struct ssb_bus ssb_bcm47xx;
-
- void __init plat_time_init(void)
- {
---- a/arch/mips/bcm47xx/nvram.c
-+++ b/arch/mips/bcm47xx/nvram.c
-@@ -24,10 +24,10 @@
- #include <asm/io.h>
- #include <asm/uaccess.h>
-
--#include <nvram.h>
-+#include "include/nvram.h"
-
- #define MB * 1048576
--extern struct ssb_bus ssb;
-+extern struct ssb_bus ssb_bcm47xx;
-
- static char nvram_buf[NVRAM_SPACE];
- static int cfe_env;
-@@ -36,7 +36,7 @@
- /* Probe for NVRAM header */
- static void __init early_nvram_init(void)
- {
-- struct ssb_mipscore *mcore = &ssb.mipscore;
-+ struct ssb_mipscore *mcore = &ssb_bcm47xx.mipscore;
- struct nvram_header *header;
- int i;
- u32 base, lim, off;
---- a/arch/mips/bcm47xx/Makefile
-+++ b/arch/mips/bcm47xx/Makefile
-@@ -3,4 +3,4 @@
- # under Linux.
- #
-
--obj-y := gpio.o irq.o prom.o serial.o setup.o time.o wgt634u.o
-+obj-y := cfe_env.o gpio.o irq.o nvram.o prom.o serial.o setup.o time.o wgt634u.o
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -54,6 +54,7 @@
- select SSB_DRIVER_MIPS
- select SSB_DRIVER_EXTIF
- select SSB_DRIVER_PCICORE
-+ select SSB_B43_PCI_BRIDGE
- select SSB_PCICORE_HOSTMODE if PCI
- select GENERIC_GPIO
- select SYS_HAS_EARLY_PRINTK
+++ /dev/null
---- a/scripts/gen_initramfs_list.sh
-+++ b/scripts/gen_initramfs_list.sh
-@@ -287,7 +287,7 @@
- if [ "${is_cpio_compressed}" = "compressed" ]; then
- cat ${cpio_tfile} > ${output_file}
- else
-- cat ${cpio_tfile} | gzip -f -9 - > ${output_file}
-+ lzma e -lc1 -lp2 -pb2 ${cpio_tfile} ${output_file}
- fi
- [ -z ${cpio_file} ] && rm ${cpio_tfile}
- fi
---- a/init/initramfs.c
-+++ b/init/initramfs.c
-@@ -441,6 +441,69 @@
- outcnt = 0;
- }
-
-+#include <linux/LzmaDecode.h>
-+static int __init lzma_unzip(void)
-+{
-+ unsigned int i; /* temp value */
-+ unsigned int lc; /* literal context bits */
-+ unsigned int lp; /* literal pos state bits */
-+ unsigned int pb; /* pos state bits */
-+ unsigned int osize; /* uncompressed size */
-+ unsigned char *workspace;
-+ unsigned char* outputbuffer;
-+ unsigned int outsizeProcessed = 0;
-+ int workspace_size;
-+ int res;
-+
-+ // lzma args
-+ i = get_byte();
-+ lc = i % 9, i = i / 9;
-+ lp = i % 5, pb = i / 5;
-+
-+ // skip dictionary size
-+ for (i = 0; i < 4; i++)
-+ get_byte();
-+
-+ /* read the lower half of uncompressed size in the header */
-+ osize = ((unsigned int)get_byte()) +
-+ ((unsigned int)get_byte() << 8) +
-+ ((unsigned int)get_byte() << 16) +
-+ ((unsigned int)get_byte() << 24);
-+
-+ /* skip rest of the header (upper half of uncompressed size) */
-+ for (i = 0; i < 4; i++)
-+ get_byte();
-+
-+ workspace_size = ((LZMA_BASE_SIZE + (LZMA_LIT_SIZE << (lc + lp))) * sizeof(CProb)) + 100;
-+ printk( KERN_NOTICE "initramfs: LZMA lc=%d,lp=%d,pb=%d,origSize=%d\n",
-+ lc,lp,pb,osize);
-+ outputbuffer = kmalloc(osize, GFP_KERNEL);
-+ if (outputbuffer == 0) {
-+ printk(KERN_ERR "initramfs: Couldn't allocate lzma output buffer\n");
-+ return -1;
-+ }
-+
-+ workspace = kmalloc(workspace_size, GFP_KERNEL);
-+ if (workspace == NULL) {
-+ printk(KERN_ERR "initramfs: Couldn't allocate lzma workspace\n");
-+ return -1;
-+ }
-+
-+ res = LzmaDecode(workspace, workspace_size, lc, lp, pb, inbuf + inptr, insize - inptr, outputbuffer, osize, &outsizeProcessed);
-+ if( res != 0 ) {
-+ panic( KERN_ERR "initramfs: Lzma decode failure\n");
-+ return -1;
-+ }
-+
-+ flush_buffer(outputbuffer, outsizeProcessed);
-+ inptr = insize;
-+
-+ kfree(outputbuffer);
-+ kfree(workspace);
-+ state = Reset;
-+ return 0;
-+}
-+
- static char * __init unpack_to_rootfs(char *buf, unsigned len, int check_only)
- {
- int written;
-@@ -475,12 +538,28 @@
- inptr = 0;
- outcnt = 0; /* bytes in output buffer */
- bytes_out = 0;
-- crc = (ulg)0xffffffffL; /* shift register contents */
-- makecrc();
-- gunzip();
-- if (state != Reset)
-+ if( inbuf[0] == 037 && ((inbuf[1] == 0213) || (inbuf[1] == 0236)))
-+ {
-+ printk( KERN_NOTICE "detected gzip initramfs\n");
-+ crc = (ulg)0xffffffffL; /* shift register contents */
-+ makecrc();
-+ gunzip();
-+ if (state != Reset)
- error("junk in gzipped archive");
-- this_header = saved_offset + inptr;
-+ }
-+ else if(!memcmp(inbuf+1, "\x00\x00\x80\x00", 4)) /* FIXME: hardcoded dictionary size */
-+ {
-+ printk( KERN_NOTICE "detected lzma initramfs\n");
-+ lzma_unzip();
-+ }
-+ else
-+ {
-+ // skip forward ?
-+ crc = (ulg)0xffffffffL; /* shift register contents */
-+ makecrc();
-+ gunzip();
-+ }
-+ this_header = saved_offset + inptr;
- buf += inptr;
- len -= inptr;
- }
+++ /dev/null
-The SSB pcicore driver does create some MMIO resource collisions.
-However, the pcicore PCI-fixup routine fixes these collisions afterwards.
-Remove this sanity check for now until we find a better solution.
---mb
---- a/arch/mips/pci/pci.c
-+++ b/arch/mips/pci/pci.c
-@@ -182,12 +182,10 @@
- if ((idx == PCI_ROM_RESOURCE) &&
- (!(r->flags & IORESOURCE_ROM_ENABLE)))
- continue;
-- if (!r->start && r->end) {
-- printk(KERN_ERR "PCI: Device %s not available "
-- "because of resource collisions\n",
-+ if (!r->start && r->end)
-+ printk(KERN_WARNING "PCI: Device %s resource"
-+ "collisions detected. Ignoring...\n",
- pci_name(dev));
-- return -EINVAL;
-- }
- if (r->flags & IORESOURCE_IO)
- cmd |= PCI_COMMAND_IO;
- if (r->flags & IORESOURCE_MEM)
+++ /dev/null
---- a/drivers/ssb/main.c
-+++ b/drivers/ssb/main.c
-@@ -1173,7 +1173,9 @@
- /* ssb must be initialized after PCI but before the ssb drivers.
- * That means we must use some initcall between subsys_initcall
- * and device_initcall. */
--fs_initcall(ssb_modinit);
-+//FIXME on embedded we need to be early to make sure we can register
-+// a new PCI bus, if needed.
-+subsys_initcall(ssb_modinit);
-
- static void __exit ssb_modexit(void)
- {
+++ /dev/null
-Subject: [OpenWrt-Devel] [PATCH] ssb-pcicore: Fix IRQ-vector init on embedded devices
-
-On embedded devices we must not route the interrupts through
-the PCI core, if our host-bus is not PCI.
-
-Reported-by: Steve Brown <sbrown@cortland.com>
-Signed-off-by: Michael Buesch <mb@bu3sch.de>
-
---- a/drivers/ssb/driver_pcicore.c
-+++ b/drivers/ssb/driver_pcicore.c
-@@ -519,6 +519,13 @@
- int err = 0;
- u32 tmp;
-
-+ if (dev->bus->bustype != SSB_BUSTYPE_PCI) {
-+ /* This SSB device is not on a PCI host-bus. So the IRQs are
-+ * not routed through the PCI core.
-+ * So we must not enable routing through the PCI core. */
-+ goto out;
-+ }
-+
- if (!pdev)
- goto out;
- bus = pdev->bus;
+++ /dev/null
-Add support for 8bit reads/writes to SSB.
---- a/drivers/ssb/main.c
-+++ b/drivers/ssb/main.c
-@@ -508,6 +508,14 @@
- return err;
- }
-
-+static u8 ssb_ssb_read8(struct ssb_device *dev, u16 offset)
-+{
-+ struct ssb_bus *bus = dev->bus;
-+
-+ offset += dev->core_index * SSB_CORE_SIZE;
-+ return readb(bus->mmio + offset);
-+}
-+
- static u16 ssb_ssb_read16(struct ssb_device *dev, u16 offset)
- {
- struct ssb_bus *bus = dev->bus;
-@@ -524,6 +532,14 @@
- return readl(bus->mmio + offset);
- }
-
-+static void ssb_ssb_write8(struct ssb_device *dev, u16 offset, u8 value)
-+{
-+ struct ssb_bus *bus = dev->bus;
-+
-+ offset += dev->core_index * SSB_CORE_SIZE;
-+ writeb(value, bus->mmio + offset);
-+}
-+
- static void ssb_ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
- {
- struct ssb_bus *bus = dev->bus;
-@@ -542,8 +558,10 @@
-
- /* Ops for the plain SSB bus without a host-device (no PCI or PCMCIA). */
- static const struct ssb_bus_ops ssb_ssb_ops = {
-+ .read8 = ssb_ssb_read8,
- .read16 = ssb_ssb_read16,
- .read32 = ssb_ssb_read32,
-+ .write8 = ssb_ssb_write8,
- .write16 = ssb_ssb_write16,
- .write32 = ssb_ssb_write32,
- };
---- a/drivers/ssb/pci.c
-+++ b/drivers/ssb/pci.c
-@@ -577,6 +577,19 @@
- }
- #endif /* DEBUG */
-
-+static u8 ssb_pci_read8(struct ssb_device *dev, u16 offset)
-+{
-+ struct ssb_bus *bus = dev->bus;
-+
-+ if (unlikely(ssb_pci_assert_buspower(bus)))
-+ return 0xFF;
-+ if (unlikely(bus->mapped_device != dev)) {
-+ if (unlikely(ssb_pci_switch_core(bus, dev)))
-+ return 0xFF;
-+ }
-+ return ioread8(bus->mmio + offset);
-+}
-+
- static u16 ssb_pci_read16(struct ssb_device *dev, u16 offset)
- {
- struct ssb_bus *bus = dev->bus;
-@@ -603,6 +616,19 @@
- return ioread32(bus->mmio + offset);
- }
-
-+static void ssb_pci_write8(struct ssb_device *dev, u16 offset, u8 value)
-+{
-+ struct ssb_bus *bus = dev->bus;
-+
-+ if (unlikely(ssb_pci_assert_buspower(bus)))
-+ return;
-+ if (unlikely(bus->mapped_device != dev)) {
-+ if (unlikely(ssb_pci_switch_core(bus, dev)))
-+ return;
-+ }
-+ iowrite8(value, bus->mmio + offset);
-+}
-+
- static void ssb_pci_write16(struct ssb_device *dev, u16 offset, u16 value)
- {
- struct ssb_bus *bus = dev->bus;
-@@ -631,8 +657,10 @@
-
- /* Not "static", as it's used in main.c */
- const struct ssb_bus_ops ssb_pci_ops = {
-+ .read8 = ssb_pci_read8,
- .read16 = ssb_pci_read16,
- .read32 = ssb_pci_read32,
-+ .write8 = ssb_pci_write8,
- .write16 = ssb_pci_write16,
- .write32 = ssb_pci_write32,
- };
---- a/drivers/ssb/pcmcia.c
-+++ b/drivers/ssb/pcmcia.c
-@@ -172,6 +172,22 @@
- return 0;
- }
-
-+static u8 ssb_pcmcia_read8(struct ssb_device *dev, u16 offset)
-+{
-+ struct ssb_bus *bus = dev->bus;
-+ unsigned long flags;
-+ int err;
-+ u8 value = 0xFF;
-+
-+ spin_lock_irqsave(&bus->bar_lock, flags);
-+ err = select_core_and_segment(dev, &offset);
-+ if (likely(!err))
-+ value = readb(bus->mmio + offset);
-+ spin_unlock_irqrestore(&bus->bar_lock, flags);
-+
-+ return value;
-+}
-+
- static u16 ssb_pcmcia_read16(struct ssb_device *dev, u16 offset)
- {
- struct ssb_bus *bus = dev->bus;
-@@ -206,6 +222,20 @@
- return (lo | (hi << 16));
- }
-
-+static void ssb_pcmcia_write8(struct ssb_device *dev, u16 offset, u8 value)
-+{
-+ struct ssb_bus *bus = dev->bus;
-+ unsigned long flags;
-+ int err;
-+
-+ spin_lock_irqsave(&bus->bar_lock, flags);
-+ err = select_core_and_segment(dev, &offset);
-+ if (likely(!err))
-+ writeb(value, bus->mmio + offset);
-+ mmiowb();
-+ spin_unlock_irqrestore(&bus->bar_lock, flags);
-+}
-+
- static void ssb_pcmcia_write16(struct ssb_device *dev, u16 offset, u16 value)
- {
- struct ssb_bus *bus = dev->bus;
-@@ -238,8 +268,10 @@
-
- /* Not "static", as it's used in main.c */
- const struct ssb_bus_ops ssb_pcmcia_ops = {
-+ .read8 = ssb_pcmcia_read8,
- .read16 = ssb_pcmcia_read16,
- .read32 = ssb_pcmcia_read32,
-+ .write8 = ssb_pcmcia_write8,
- .write16 = ssb_pcmcia_write16,
- .write32 = ssb_pcmcia_write32,
- };
---- a/include/linux/ssb/ssb.h
-+++ b/include/linux/ssb/ssb.h
-@@ -72,8 +72,10 @@
- /* Lowlevel read/write operations on the device MMIO.
- * Internal, don't use that outside of ssb. */
- struct ssb_bus_ops {
-+ u8 (*read8)(struct ssb_device *dev, u16 offset);
- u16 (*read16)(struct ssb_device *dev, u16 offset);
- u32 (*read32)(struct ssb_device *dev, u16 offset);
-+ void (*write8)(struct ssb_device *dev, u16 offset, u8 value);
- void (*write16)(struct ssb_device *dev, u16 offset, u16 value);
- void (*write32)(struct ssb_device *dev, u16 offset, u32 value);
- };
-@@ -348,6 +350,10 @@
-
-
- /* Device MMIO register read/write functions. */
-+static inline u8 ssb_read8(struct ssb_device *dev, u16 offset)
-+{
-+ return dev->ops->read8(dev, offset);
-+}
- static inline u16 ssb_read16(struct ssb_device *dev, u16 offset)
- {
- return dev->ops->read16(dev, offset);
-@@ -356,6 +362,10 @@
- {
- return dev->ops->read32(dev, offset);
- }
-+static inline void ssb_write8(struct ssb_device *dev, u16 offset, u8 value)
-+{
-+ dev->ops->write8(dev, offset, value);
-+}
- static inline void ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
- {
- dev->ops->write16(dev, offset, value);
+++ /dev/null
-Allow registering PCI devices after early boot.
-
-This is an ugly hack and needs to be rewritten before going upstream.
---- a/arch/mips/pci/pci.c
-+++ b/arch/mips/pci/pci.c
-@@ -21,6 +21,17 @@
- */
- int pci_probe_only;
-
-+/*
-+ * Indicate whether PCI-bios init was already done.
-+ */
-+static int pcibios_init_done;
-+
-+/*
-+ * The currently used busnumber.
-+ */
-+static int next_busno;
-+static int need_domain_info;
-+
- #define PCI_ASSIGN_ALL_BUSSES 1
-
- unsigned int pci_probe = PCI_ASSIGN_ALL_BUSSES;
-@@ -75,8 +86,32 @@
- res->start = start;
- }
-
--void __devinit register_pci_controller(struct pci_controller *hose)
-+/* Most MIPS systems have straight-forward swizzling needs. */
-+
-+static inline u8 bridge_swizzle(u8 pin, u8 slot)
-+{
-+ return (((pin - 1) + slot) % 4) + 1;
-+}
-+
-+static u8 common_swizzle(struct pci_dev *dev, u8 *pinp)
- {
-+ u8 pin = *pinp;
-+
-+ while (dev->bus->parent) {
-+ pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
-+ /* Move up the chain of bridges. */
-+ dev = dev->bus->self;
-+ }
-+ *pinp = pin;
-+
-+ /* The slot is the slot of the last bridge. */
-+ return PCI_SLOT(dev->devfn);
-+}
-+
-+void register_pci_controller(struct pci_controller *hose)
-+{
-+ struct pci_bus *bus;
-+
- if (request_resource(&iomem_resource, hose->mem_resource) < 0)
- goto out;
- if (request_resource(&ioport_resource, hose->io_resource) < 0) {
-@@ -84,9 +119,6 @@
- goto out;
- }
-
-- *hose_tail = hose;
-- hose_tail = &hose->next;
--
- /*
- * Do not panic here but later - this might hapen before console init.
- */
-@@ -94,41 +126,47 @@
- printk(KERN_WARNING
- "registering PCI controller with io_map_base unset\n");
- }
-- return;
-
--out:
-- printk(KERN_WARNING
-- "Skipping PCI bus scan due to resource conflict\n");
--}
-+ if (pcibios_init_done) {
-+ //TODO
-
--/* Most MIPS systems have straight-forward swizzling needs. */
-+ printk(KERN_INFO "Registering a PCI bus after boot\n");
-
--static inline u8 bridge_swizzle(u8 pin, u8 slot)
--{
-- return (((pin - 1) + slot) % 4) + 1;
--}
-+ if (!hose->iommu)
-+ PCI_DMA_BUS_IS_PHYS = 1;
-
--static u8 __init common_swizzle(struct pci_dev *dev, u8 *pinp)
--{
-- u8 pin = *pinp;
-+ bus = pci_scan_bus(next_busno, hose->pci_ops, hose);
-+ hose->bus = bus;
-+ need_domain_info = need_domain_info || hose->index;
-+ hose->need_domain_info = need_domain_info;
-+ if (bus) {
-+ next_busno = bus->subordinate + 1;
-+ /* Don't allow 8-bit bus number overflow inside the hose -
-+ reserve some space for bridges. */
-+ if (next_busno > 224) {
-+ next_busno = 0;
-+ need_domain_info = 1;
-+ }
-+ }
-+ if (!pci_probe_only)
-+ pci_assign_unassigned_resources();
-+ pci_fixup_irqs(common_swizzle, pcibios_map_irq);
-+ } else {
-+ *hose_tail = hose;
-+ hose_tail = &hose->next;
-+ }
-
-- while (dev->bus->parent) {
-- pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
-- /* Move up the chain of bridges. */
-- dev = dev->bus->self;
-- }
-- *pinp = pin;
-+ return;
-
-- /* The slot is the slot of the last bridge. */
-- return PCI_SLOT(dev->devfn);
-+out:
-+ printk(KERN_WARNING
-+ "Skipping PCI bus scan due to resource conflict\n");
- }
-
- static int __init pcibios_init(void)
- {
- struct pci_controller *hose;
- struct pci_bus *bus;
-- int next_busno;
-- int need_domain_info = 0;
-
- /* Scan all of the recorded PCI controllers. */
- for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
-@@ -157,6 +195,7 @@
- if (!pci_probe_only)
- pci_assign_unassigned_resources();
- pci_fixup_irqs(common_swizzle, pcibios_map_irq);
-+ pcibios_init_done = 1;
-
- return 0;
- }
---- a/drivers/ssb/main.c
-+++ b/drivers/ssb/main.c
-@@ -1191,9 +1191,7 @@
- /* ssb must be initialized after PCI but before the ssb drivers.
- * That means we must use some initcall between subsys_initcall
- * and device_initcall. */
--//FIXME on embedded we need to be early to make sure we can register
--// a new PCI bus, if needed.
--subsys_initcall(ssb_modinit);
-+fs_initcall(ssb_modinit);
-
- static void __exit ssb_modexit(void)
- {
+++ /dev/null
---- a/drivers/ssb/Kconfig
-+++ b/drivers/ssb/Kconfig
-@@ -125,4 +125,13 @@
-
- If unsure, say N
-
-+config SSB_DRIVER_GIGE
-+ bool "SSB Broadcom Gigabit Ethernet driver"
-+ depends on SSB_PCIHOST_POSSIBLE && SSB_EMBEDDED && MIPS
-+ help
-+ Driver for the Sonics Silicon Backplane attached
-+ Broadcom Gigabit Ethernet.
-+
-+ If unsure, say N
-+
- endmenu
---- a/drivers/ssb/Makefile
-+++ b/drivers/ssb/Makefile
-@@ -11,6 +11,7 @@
- ssb-$(CONFIG_SSB_DRIVER_MIPS) += driver_mipscore.o
- ssb-$(CONFIG_SSB_DRIVER_EXTIF) += driver_extif.o
- ssb-$(CONFIG_SSB_DRIVER_PCICORE) += driver_pcicore.o
-+ssb-$(CONFIG_SSB_DRIVER_GIGE) += driver_gige.o
-
- # b43 pci-ssb-bridge driver
- # Not strictly a part of SSB, but kept here for convenience
---- /dev/null
-+++ b/drivers/ssb/driver_gige.c
-@@ -0,0 +1,294 @@
-+/*
-+ * Sonics Silicon Backplane
-+ * Broadcom Gigabit Ethernet core driver
-+ *
-+ * Copyright 2008, Broadcom Corporation
-+ * Copyright 2008, Michael Buesch <mb@bu3sch.de>
-+ *
-+ * Licensed under the GNU/GPL. See COPYING for details.
-+ */
-+
-+#include <linux/ssb/ssb.h>
-+#include <linux/ssb/ssb_driver_gige.h>
-+#include <linux/pci.h>
-+#include <linux/pci_regs.h>
-+
-+
-+/*
-+MODULE_DESCRIPTION("SSB Broadcom Gigabit Ethernet driver");
-+MODULE_AUTHOR("Michael Buesch");
-+MODULE_LICENSE("GPL");
-+*/
-+
-+static const struct ssb_device_id ssb_gige_tbl[] = {
-+ SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET_GBIT, SSB_ANY_REV),
-+ SSB_DEVTABLE_END
-+};
-+/* MODULE_DEVICE_TABLE(ssb, ssb_gige_tbl); */
-+
-+
-+static inline u8 gige_read8(struct ssb_gige *dev, u16 offset)
-+{
-+ return ssb_read8(dev->dev, offset);
-+}
-+
-+static inline u16 gige_read16(struct ssb_gige *dev, u16 offset)
-+{
-+ return ssb_read16(dev->dev, offset);
-+}
-+
-+static inline u32 gige_read32(struct ssb_gige *dev, u16 offset)
-+{
-+ return ssb_read32(dev->dev, offset);
-+}
-+
-+static inline void gige_write8(struct ssb_gige *dev,
-+ u16 offset, u8 value)
-+{
-+ ssb_write8(dev->dev, offset, value);
-+}
-+
-+static inline void gige_write16(struct ssb_gige *dev,
-+ u16 offset, u16 value)
-+{
-+ ssb_write16(dev->dev, offset, value);
-+}
-+
-+static inline void gige_write32(struct ssb_gige *dev,
-+ u16 offset, u32 value)
-+{
-+ ssb_write32(dev->dev, offset, value);
-+}
-+
-+static inline
-+u8 gige_pcicfg_read8(struct ssb_gige *dev, unsigned int offset)
-+{
-+ BUG_ON(offset >= 256);
-+ return gige_read8(dev, SSB_GIGE_PCICFG + offset);
-+}
-+
-+static inline
-+u16 gige_pcicfg_read16(struct ssb_gige *dev, unsigned int offset)
-+{
-+ BUG_ON(offset >= 256);
-+ return gige_read16(dev, SSB_GIGE_PCICFG + offset);
-+}
-+
-+static inline
-+u32 gige_pcicfg_read32(struct ssb_gige *dev, unsigned int offset)
-+{
-+ BUG_ON(offset >= 256);
-+ return gige_read32(dev, SSB_GIGE_PCICFG + offset);
-+}
-+
-+static inline
-+void gige_pcicfg_write8(struct ssb_gige *dev,
-+ unsigned int offset, u8 value)
-+{
-+ BUG_ON(offset >= 256);
-+ gige_write8(dev, SSB_GIGE_PCICFG + offset, value);
-+}
-+
-+static inline
-+void gige_pcicfg_write16(struct ssb_gige *dev,
-+ unsigned int offset, u16 value)
-+{
-+ BUG_ON(offset >= 256);
-+ gige_write16(dev, SSB_GIGE_PCICFG + offset, value);
-+}
-+
-+static inline
-+void gige_pcicfg_write32(struct ssb_gige *dev,
-+ unsigned int offset, u32 value)
-+{
-+ BUG_ON(offset >= 256);
-+ gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
-+}
-+
-+static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
-+ int reg, int size, u32 *val)
-+{
-+ struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
-+ unsigned long flags;
-+
-+ if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0))
-+ return PCIBIOS_DEVICE_NOT_FOUND;
-+ if (reg >= 256)
-+ return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+ spin_lock_irqsave(&dev->lock, flags);
-+ switch (size) {
-+ case 1:
-+ *val = gige_pcicfg_read8(dev, reg);
-+ break;
-+ case 2:
-+ *val = gige_pcicfg_read16(dev, reg);
-+ break;
-+ case 4:
-+ *val = gige_pcicfg_read32(dev, reg);
-+ break;
-+ default:
-+ WARN_ON(1);
-+ }
-+ spin_unlock_irqrestore(&dev->lock, flags);
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
-+ int reg, int size, u32 val)
-+{
-+ struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
-+ unsigned long flags;
-+
-+ if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0))
-+ return PCIBIOS_DEVICE_NOT_FOUND;
-+ if (reg >= 256)
-+ return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+ spin_lock_irqsave(&dev->lock, flags);
-+ switch (size) {
-+ case 1:
-+ gige_pcicfg_write8(dev, reg, val);
-+ break;
-+ case 2:
-+ gige_pcicfg_write16(dev, reg, val);
-+ break;
-+ case 4:
-+ gige_pcicfg_write32(dev, reg, val);
-+ break;
-+ default:
-+ WARN_ON(1);
-+ }
-+ spin_unlock_irqrestore(&dev->lock, flags);
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
-+{
-+ struct ssb_gige *dev;
-+ u32 base, tmslow, tmshigh;
-+
-+ dev = kzalloc(sizeof(*dev), GFP_KERNEL);
-+ if (!dev)
-+ return -ENOMEM;
-+ dev->dev = sdev;
-+
-+ spin_lock_init(&dev->lock);
-+ dev->pci_controller.pci_ops = &dev->pci_ops;
-+ dev->pci_controller.io_resource = &dev->io_resource;
-+ dev->pci_controller.mem_resource = &dev->mem_resource;
-+ dev->pci_controller.io_map_base = 0x800;
-+ dev->pci_ops.read = ssb_gige_pci_read_config;
-+ dev->pci_ops.write = ssb_gige_pci_write_config;
-+
-+ dev->io_resource.name = SSB_GIGE_IO_RES_NAME;
-+ dev->io_resource.start = 0x800;
-+ dev->io_resource.end = 0x8FF;
-+ dev->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
-+
-+ if (!ssb_device_is_enabled(sdev))
-+ ssb_device_enable(sdev, 0);
-+
-+ /* Setup BAR0. This is a 64k MMIO region. */
-+ base = ssb_admatch_base(ssb_read32(sdev, SSB_ADMATCH1));
-+ gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_0, base);
-+ gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_1, 0);
-+
-+ dev->mem_resource.name = SSB_GIGE_MEM_RES_NAME;
-+ dev->mem_resource.start = base;
-+ dev->mem_resource.end = base + 0x10000 - 1;
-+ dev->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
-+
-+ /* Enable the memory region. */
-+ gige_pcicfg_write16(dev, PCI_COMMAND,
-+ gige_pcicfg_read16(dev, PCI_COMMAND)
-+ | PCI_COMMAND_MEMORY);
-+
-+ /* Write flushing is controlled by the Flush Status Control register.
-+ * We want to flush every register write with a timeout and we want
-+ * to disable the IRQ mask while flushing to avoid concurrency.
-+ * Note that automatic write flushing does _not_ work from
-+ * an IRQ handler. The driver must flush manually by reading a register.
-+ */
-+ gige_write32(dev, SSB_GIGE_SHIM_FLUSHSTAT, 0x00000068);
-+
-+ /* Check if we have an RGMII or GMII PHY-bus.
-+ * On RGMII do not bypass the DLLs */
-+ tmslow = ssb_read32(sdev, SSB_TMSLOW);
-+ tmshigh = ssb_read32(sdev, SSB_TMSHIGH);
-+ if (tmshigh & SSB_GIGE_TMSHIGH_RGMII) {
-+ tmslow &= ~SSB_GIGE_TMSLOW_TXBYPASS;
-+ tmslow &= ~SSB_GIGE_TMSLOW_RXBYPASS;
-+ dev->has_rgmii = 1;
-+ } else {
-+ tmslow |= SSB_GIGE_TMSLOW_TXBYPASS;
-+ tmslow |= SSB_GIGE_TMSLOW_RXBYPASS;
-+ dev->has_rgmii = 0;
-+ }
-+ tmslow |= SSB_GIGE_TMSLOW_DLLEN;
-+ ssb_write32(sdev, SSB_TMSLOW, tmslow);
-+
-+ ssb_set_drvdata(sdev, dev);
-+ register_pci_controller(&dev->pci_controller);
-+
-+ return 0;
-+}
-+
-+bool pdev_is_ssb_gige_core(struct pci_dev *pdev)
-+{
-+ if (!pdev->resource[0].name)
-+ return 0;
-+ return (strcmp(pdev->resource[0].name, SSB_GIGE_MEM_RES_NAME) == 0);
-+}
-+EXPORT_SYMBOL(pdev_is_ssb_gige_core);
-+
-+int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
-+ struct pci_dev *pdev)
-+{
-+ struct ssb_gige *dev = ssb_get_drvdata(sdev);
-+ struct resource *res;
-+
-+ if (pdev->bus->ops != &dev->pci_ops) {
-+ /* The PCI device is not on this SSB GigE bridge device. */
-+ return -ENODEV;
-+ }
-+
-+ /* Fixup the PCI resources. */
-+ res = &(pdev->resource[0]);
-+ res->flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
-+ res->name = dev->mem_resource.name;
-+ res->start = dev->mem_resource.start;
-+ res->end = dev->mem_resource.end;
-+
-+ /* Fixup interrupt lines. */
-+ pdev->irq = ssb_mips_irq(sdev) + 2;
-+ pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, pdev->irq);
-+
-+ return 0;
-+}
-+
-+int ssb_gige_map_irq(struct ssb_device *sdev,
-+ const struct pci_dev *pdev)
-+{
-+ struct ssb_gige *dev = ssb_get_drvdata(sdev);
-+
-+ if (pdev->bus->ops != &dev->pci_ops) {
-+ /* The PCI device is not on this SSB GigE bridge device. */
-+ return -ENODEV;
-+ }
-+
-+ return ssb_mips_irq(sdev) + 2;
-+}
-+
-+static struct ssb_driver ssb_gige_driver = {
-+ .name = "BCM-GigE",
-+ .id_table = ssb_gige_tbl,
-+ .probe = ssb_gige_probe,
-+};
-+
-+int ssb_gige_init(void)
-+{
-+ return ssb_driver_register(&ssb_gige_driver);
-+}
---- /dev/null
-+++ b/include/linux/ssb/ssb_driver_gige.h
-@@ -0,0 +1,174 @@
-+#ifndef LINUX_SSB_DRIVER_GIGE_H_
-+#define LINUX_SSB_DRIVER_GIGE_H_
-+
-+#include <linux/ssb/ssb.h>
-+#include <linux/pci.h>
-+#include <linux/spinlock.h>
-+
-+
-+#ifdef CONFIG_SSB_DRIVER_GIGE
-+
-+
-+#define SSB_GIGE_PCIIO 0x0000 /* PCI I/O Registers (1024 bytes) */
-+#define SSB_GIGE_RESERVED 0x0400 /* Reserved (1024 bytes) */
-+#define SSB_GIGE_PCICFG 0x0800 /* PCI config space (256 bytes) */
-+#define SSB_GIGE_SHIM_FLUSHSTAT 0x0C00 /* PCI to OCP: Flush status control (32bit) */
-+#define SSB_GIGE_SHIM_FLUSHRDA 0x0C04 /* PCI to OCP: Flush read address (32bit) */
-+#define SSB_GIGE_SHIM_FLUSHTO 0x0C08 /* PCI to OCP: Flush timeout counter (32bit) */
-+#define SSB_GIGE_SHIM_BARRIER 0x0C0C /* PCI to OCP: Barrier register (32bit) */
-+#define SSB_GIGE_SHIM_MAOCPSI 0x0C10 /* PCI to OCP: MaocpSI Control (32bit) */
-+#define SSB_GIGE_SHIM_SIOCPMA 0x0C14 /* PCI to OCP: SiocpMa Control (32bit) */
-+
-+/* TM Status High flags */
-+#define SSB_GIGE_TMSHIGH_RGMII 0x00010000 /* Have an RGMII PHY-bus */
-+/* TM Status Low flags */
-+#define SSB_GIGE_TMSLOW_TXBYPASS 0x00080000 /* TX bypass (no delay) */
-+#define SSB_GIGE_TMSLOW_RXBYPASS 0x00100000 /* RX bypass (no delay) */
-+#define SSB_GIGE_TMSLOW_DLLEN 0x01000000 /* Enable DLL controls */
-+
-+/* Boardflags (low) */
-+#define SSB_GIGE_BFL_ROBOSWITCH 0x0010
-+
-+
-+#define SSB_GIGE_MEM_RES_NAME "SSB Broadcom 47xx GigE memory"
-+#define SSB_GIGE_IO_RES_NAME "SSB Broadcom 47xx GigE I/O"
-+
-+struct ssb_gige {
-+ struct ssb_device *dev;
-+
-+ spinlock_t lock;
-+
-+ /* True, if the device has an RGMII bus.
-+ * False, if the device has a GMII bus. */
-+ bool has_rgmii;
-+
-+ /* The PCI controller device. */
-+ struct pci_controller pci_controller;
-+ struct pci_ops pci_ops;
-+ struct resource mem_resource;
-+ struct resource io_resource;
-+};
-+
-+/* Check whether a PCI device is a SSB Gigabit Ethernet core. */
-+extern bool pdev_is_ssb_gige_core(struct pci_dev *pdev);
-+
-+/* Convert a pci_dev pointer to a ssb_gige pointer. */
-+static inline struct ssb_gige * pdev_to_ssb_gige(struct pci_dev *pdev)
-+{
-+ if (!pdev_is_ssb_gige_core(pdev))
-+ return NULL;
-+ return container_of(pdev->bus->ops, struct ssb_gige, pci_ops);
-+}
-+
-+/* Returns whether the PHY is connected by an RGMII bus. */
-+static inline bool ssb_gige_is_rgmii(struct pci_dev *pdev)
-+{
-+ struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
-+ return (dev ? dev->has_rgmii : 0);
-+}
-+
-+/* Returns whether we have a Roboswitch. */
-+static inline bool ssb_gige_have_roboswitch(struct pci_dev *pdev)
-+{
-+ struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
-+ if (dev)
-+ return !!(dev->dev->bus->sprom.boardflags_lo &
-+ SSB_GIGE_BFL_ROBOSWITCH);
-+ return 0;
-+}
-+
-+/* Returns whether we can only do one DMA at once. */
-+static inline bool ssb_gige_one_dma_at_once(struct pci_dev *pdev)
-+{
-+ struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
-+ if (dev)
-+ return ((dev->dev->bus->chip_id == 0x4785) &&
-+ (dev->dev->bus->chip_rev < 2));
-+ return 0;
-+}
-+
-+/* Returns whether we must flush posted writes. */
-+static inline bool ssb_gige_must_flush_posted_writes(struct pci_dev *pdev)
-+{
-+ struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
-+ if (dev)
-+ return (dev->dev->bus->chip_id == 0x4785);
-+ return 0;
-+}
-+
-+extern char * nvram_get(const char *name);
-+/* Get the device MAC address */
-+static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
-+{
-+#ifdef CONFIG_BCM947XX
-+ char *res = nvram_get("et0macaddr");
-+ if (res)
-+ memcpy(macaddr, res, 6);
-+#endif
-+}
-+
-+extern int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
-+ struct pci_dev *pdev);
-+extern int ssb_gige_map_irq(struct ssb_device *sdev,
-+ const struct pci_dev *pdev);
-+
-+/* The GigE driver is not a standalone module, because we don't have support
-+ * for unregistering the driver. So we could not unload the module anyway. */
-+extern int ssb_gige_init(void);
-+static inline void ssb_gige_exit(void)
-+{
-+ /* Currently we can not unregister the GigE driver,
-+ * because we can not unregister the PCI bridge. */
-+ BUG();
-+}
-+
-+
-+#else /* CONFIG_SSB_DRIVER_GIGE */
-+/* Gigabit Ethernet driver disabled */
-+
-+
-+static inline int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
-+ struct pci_dev *pdev)
-+{
-+ return -ENOSYS;
-+}
-+static inline int ssb_gige_map_irq(struct ssb_device *sdev,
-+ const struct pci_dev *pdev)
-+{
-+ return -ENOSYS;
-+}
-+static inline int ssb_gige_init(void)
-+{
-+ return 0;
-+}
-+static inline void ssb_gige_exit(void)
-+{
-+}
-+
-+static inline bool pdev_is_ssb_gige_core(struct pci_dev *pdev)
-+{
-+ return 0;
-+}
-+static inline struct ssb_gige * pdev_to_ssb_gige(struct pci_dev *pdev)
-+{
-+ return NULL;
-+}
-+static inline bool ssb_gige_is_rgmii(struct pci_dev *pdev)
-+{
-+ return 0;
-+}
-+static inline bool ssb_gige_have_roboswitch(struct pci_dev *pdev)
-+{
-+ return 0;
-+}
-+static inline bool ssb_gige_one_dma_at_once(struct pci_dev *pdev)
-+{
-+ return 0;
-+}
-+static inline bool ssb_gige_must_flush_posted_writes(struct pci_dev *pdev)
-+{
-+ return 0;
-+}
-+
-+#endif /* CONFIG_SSB_DRIVER_GIGE */
-+#endif /* LINUX_SSB_DRIVER_GIGE_H_ */
---- a/drivers/ssb/driver_pcicore.c
-+++ b/drivers/ssb/driver_pcicore.c
-@@ -60,78 +60,6 @@
- /* Core to access the external PCI config space. Can only have one. */
- static struct ssb_pcicore *extpci_core;
-
--static u32 ssb_pcicore_pcibus_iobase = 0x100;
--static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
--
--int pcibios_plat_dev_init(struct pci_dev *d)
--{
-- struct resource *res;
-- int pos, size;
-- u32 *base;
--
-- ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
-- pci_name(d));
--
-- /* Fix up resource bases */
-- for (pos = 0; pos < 6; pos++) {
-- res = &d->resource[pos];
-- if (res->flags & IORESOURCE_IO)
-- base = &ssb_pcicore_pcibus_iobase;
-- else
-- base = &ssb_pcicore_pcibus_membase;
-- res->flags |= IORESOURCE_PCI_FIXED;
-- if (res->end) {
-- size = res->end - res->start + 1;
-- if (*base & (size - 1))
-- *base = (*base + size) & ~(size - 1);
-- res->start = *base;
-- res->end = res->start + size - 1;
-- *base += size;
-- pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
-- }
-- /* Fix up PCI bridge BAR0 only */
-- if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
-- break;
-- }
-- /* Fix up interrupt lines */
-- d->irq = ssb_mips_irq(extpci_core->dev) + 2;
-- pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
--
-- return 0;
--}
--
--static void __init ssb_fixup_pcibridge(struct pci_dev *dev)
--{
-- u8 lat;
--
-- if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
-- return;
--
-- ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
--
-- /* Enable PCI bridge bus mastering and memory space */
-- pci_set_master(dev);
-- if (pcibios_enable_device(dev, ~0) < 0) {
-- ssb_printk(KERN_ERR "PCI: SSB bridge enable failed\n");
-- return;
-- }
--
-- /* Enable PCI bridge BAR1 prefetch and burst */
-- pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
--
-- /* Make sure our latency is high enough to handle the devices behind us */
-- lat = 168;
-- ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
-- pci_name(dev), lat);
-- pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
--}
--DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_fixup_pcibridge);
--
--int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
--{
-- return ssb_mips_irq(extpci_core->dev) + 2;
--}
--
- static u32 get_cfgspace_addr(struct ssb_pcicore *pc,
- unsigned int bus, unsigned int dev,
- unsigned int func, unsigned int off)
-@@ -320,6 +248,95 @@
- .mem_offset = 0x24000000,
- };
-
-+static u32 ssb_pcicore_pcibus_iobase = 0x100;
-+static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
-+
-+/* This function is called when doing a pci_enable_device().
-+ * We must first check if the device is a device on the PCI-core bridge. */
-+int ssb_pcicore_plat_dev_init(struct pci_dev *d)
-+{
-+ struct resource *res;
-+ int pos, size;
-+ u32 *base;
-+
-+ if (d->bus->ops != &ssb_pcicore_pciops) {
-+ /* This is not a device on the PCI-core bridge. */
-+ return -ENODEV;
-+ }
-+
-+ ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
-+ pci_name(d));
-+
-+ /* Fix up resource bases */
-+ for (pos = 0; pos < 6; pos++) {
-+ res = &d->resource[pos];
-+ if (res->flags & IORESOURCE_IO)
-+ base = &ssb_pcicore_pcibus_iobase;
-+ else
-+ base = &ssb_pcicore_pcibus_membase;
-+ res->flags |= IORESOURCE_PCI_FIXED;
-+ if (res->end) {
-+ size = res->end - res->start + 1;
-+ if (*base & (size - 1))
-+ *base = (*base + size) & ~(size - 1);
-+ res->start = *base;
-+ res->end = res->start + size - 1;
-+ *base += size;
-+ pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
-+ }
-+ /* Fix up PCI bridge BAR0 only */
-+ if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
-+ break;
-+ }
-+ /* Fix up interrupt lines */
-+ d->irq = ssb_mips_irq(extpci_core->dev) + 2;
-+ pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
-+
-+ return 0;
-+}
-+
-+/* Early PCI fixup for a device on the PCI-core bridge. */
-+static void ssb_pcicore_fixup_pcibridge(struct pci_dev *dev)
-+{
-+ u8 lat;
-+
-+ if (dev->bus->ops != &ssb_pcicore_pciops) {
-+ /* This is not a device on the PCI-core bridge. */
-+ return;
-+ }
-+ if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
-+ return;
-+
-+ ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
-+
-+ /* Enable PCI bridge bus mastering and memory space */
-+ pci_set_master(dev);
-+ if (pcibios_enable_device(dev, ~0) < 0) {
-+ ssb_printk(KERN_ERR "PCI: SSB bridge enable failed\n");
-+ return;
-+ }
-+
-+ /* Enable PCI bridge BAR1 prefetch and burst */
-+ pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
-+
-+ /* Make sure our latency is high enough to handle the devices behind us */
-+ lat = 168;
-+ ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
-+ pci_name(dev), lat);
-+ pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
-+}
-+DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_pcicore_fixup_pcibridge);
-+
-+/* PCI device IRQ mapping. */
-+int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-+{
-+ if (dev->bus->ops != &ssb_pcicore_pciops) {
-+ /* This is not a device on the PCI-core bridge. */
-+ return -ENODEV;
-+ }
-+ return ssb_mips_irq(extpci_core->dev) + 2;
-+}
-+
- static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
- {
- u32 val;
---- a/drivers/ssb/embedded.c
-+++ b/drivers/ssb/embedded.c
-@@ -10,6 +10,9 @@
-
- #include <linux/ssb/ssb.h>
- #include <linux/ssb/ssb_embedded.h>
-+#include <linux/ssb/ssb_driver_pci.h>
-+#include <linux/ssb/ssb_driver_gige.h>
-+#include <linux/pci.h>
-
- #include "ssb_private.h"
-
-@@ -130,3 +133,90 @@
- return res;
- }
- EXPORT_SYMBOL(ssb_gpio_polarity);
-+
-+#ifdef CONFIG_SSB_DRIVER_GIGE
-+static int gige_pci_init_callback(struct ssb_bus *bus, unsigned long data)
-+{
-+ struct pci_dev *pdev = (struct pci_dev *)data;
-+ struct ssb_device *dev;
-+ unsigned int i;
-+ int res;
-+
-+ for (i = 0; i < bus->nr_devices; i++) {
-+ dev = &(bus->devices[i]);
-+ if (dev->id.coreid != SSB_DEV_ETHERNET_GBIT)
-+ continue;
-+ if (!dev->dev ||
-+ !dev->dev->driver ||
-+ !device_is_registered(dev->dev))
-+ continue;
-+ res = ssb_gige_pcibios_plat_dev_init(dev, pdev);
-+ if (res >= 0)
-+ return res;
-+ }
-+
-+ return -ENODEV;
-+}
-+#endif /* CONFIG_SSB_DRIVER_GIGE */
-+
-+int ssb_pcibios_plat_dev_init(struct pci_dev *dev)
-+{
-+ int err;
-+
-+ err = ssb_pcicore_plat_dev_init(dev);
-+ if (!err)
-+ return 0;
-+#ifdef CONFIG_SSB_DRIVER_GIGE
-+ err = ssb_for_each_bus_call((unsigned long)dev, gige_pci_init_callback);
-+ if (err >= 0)
-+ return err;
-+#endif
-+ /* This is not a PCI device on any SSB device. */
-+
-+ return -ENODEV;
-+}
-+
-+#ifdef CONFIG_SSB_DRIVER_GIGE
-+static int gige_map_irq_callback(struct ssb_bus *bus, unsigned long data)
-+{
-+ const struct pci_dev *pdev = (const struct pci_dev *)data;
-+ struct ssb_device *dev;
-+ unsigned int i;
-+ int res;
-+
-+ for (i = 0; i < bus->nr_devices; i++) {
-+ dev = &(bus->devices[i]);
-+ if (dev->id.coreid != SSB_DEV_ETHERNET_GBIT)
-+ continue;
-+ if (!dev->dev ||
-+ !dev->dev->driver ||
-+ !device_is_registered(dev->dev))
-+ continue;
-+ res = ssb_gige_map_irq(dev, pdev);
-+ if (res >= 0)
-+ return res;
-+ }
-+
-+ return -ENODEV;
-+}
-+#endif /* CONFIG_SSB_DRIVER_GIGE */
-+
-+int ssb_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-+{
-+ int res;
-+
-+ /* Check if this PCI device is a device on a SSB bus or device
-+ * and return the IRQ number for it. */
-+
-+ res = ssb_pcicore_pcibios_map_irq(dev, slot, pin);
-+ if (res >= 0)
-+ return res;
-+#ifdef CONFIG_SSB_DRIVER_GIGE
-+ res = ssb_for_each_bus_call((unsigned long)dev, gige_map_irq_callback);
-+ if (res >= 0)
-+ return res;
-+#endif
-+ /* This is not a PCI device on any SSB device. */
-+
-+ return -ENODEV;
-+}
---- a/include/linux/ssb/ssb.h
-+++ b/include/linux/ssb/ssb.h
-@@ -426,5 +426,12 @@
- extern u32 ssb_admatch_base(u32 adm);
- extern u32 ssb_admatch_size(u32 adm);
-
-+/* PCI device mapping and fixup routines.
-+ * Called from the architecture pcibios init code.
-+ * These are only available on SSB_EMBEDDED configurations. */
-+#ifdef CONFIG_SSB_EMBEDDED
-+int ssb_pcibios_plat_dev_init(struct pci_dev *dev);
-+int ssb_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
-+#endif /* CONFIG_SSB_EMBEDDED */
-
- #endif /* LINUX_SSB_H_ */
---- a/include/linux/ssb/ssb_driver_pci.h
-+++ b/include/linux/ssb/ssb_driver_pci.h
-@@ -1,6 +1,11 @@
- #ifndef LINUX_SSB_PCICORE_H_
- #define LINUX_SSB_PCICORE_H_
-
-+#include <linux/types.h>
-+
-+struct pci_dev;
-+
-+
- #ifdef CONFIG_SSB_DRIVER_PCICORE
-
- /* PCI core registers. */
-@@ -88,6 +93,9 @@
- extern int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
- struct ssb_device *dev);
-
-+int ssb_pcicore_plat_dev_init(struct pci_dev *d);
-+int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
-+
-
- #else /* CONFIG_SSB_DRIVER_PCICORE */
-
-@@ -107,5 +115,16 @@
- return 0;
- }
-
-+static inline
-+int ssb_pcicore_plat_dev_init(struct pci_dev *d)
-+{
-+ return -ENODEV;
-+}
-+static inline
-+int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-+{
-+ return -ENODEV;
-+}
-+
- #endif /* CONFIG_SSB_DRIVER_PCICORE */
- #endif /* LINUX_SSB_PCICORE_H_ */
---- a/drivers/ssb/main.c
-+++ b/drivers/ssb/main.c
-@@ -14,6 +14,7 @@
- #include <linux/io.h>
- #include <linux/ssb/ssb.h>
- #include <linux/ssb/ssb_regs.h>
-+#include <linux/ssb/ssb_driver_gige.h>
- #include <linux/dma-mapping.h>
- #include <linux/pci.h>
-
-@@ -68,6 +69,25 @@
- }
- #endif /* CONFIG_SSB_PCIHOST */
-
-+int ssb_for_each_bus_call(unsigned long data,
-+ int (*func)(struct ssb_bus *bus, unsigned long data))
-+{
-+ struct ssb_bus *bus;
-+ int res;
-+
-+ ssb_buses_lock();
-+ list_for_each_entry(bus, &buses, list) {
-+ res = func(bus, data);
-+ if (res >= 0) {
-+ ssb_buses_unlock();
-+ return res;
-+ }
-+ }
-+ ssb_buses_unlock();
-+
-+ return -ENODEV;
-+}
-+
- static struct ssb_device *ssb_device_get(struct ssb_device *dev)
- {
- if (dev)
-@@ -1181,7 +1201,14 @@
- err = b43_pci_ssb_bridge_init();
- if (err) {
- ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge "
-- "initialization failed");
-+ "initialization failed\n");
-+ /* don't fail SSB init because of this */
-+ err = 0;
-+ }
-+ err = ssb_gige_init();
-+ if (err) {
-+ ssb_printk(KERN_ERR "SSB Broadcom Gigabit Ethernet "
-+ "driver initialization failed\n");
- /* don't fail SSB init because of this */
- err = 0;
- }
-@@ -1195,6 +1222,7 @@
-
- static void __exit ssb_modexit(void)
- {
-+ ssb_gige_exit();
- b43_pci_ssb_bridge_exit();
- bus_unregister(&ssb_bustype);
- }
---- a/drivers/ssb/ssb_private.h
-+++ b/drivers/ssb/ssb_private.h
-@@ -118,6 +118,8 @@
- extern int ssb_devices_freeze(struct ssb_bus *bus);
- extern int ssb_devices_thaw(struct ssb_bus *bus);
- extern struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev);
-+int ssb_for_each_bus_call(unsigned long data,
-+ int (*func)(struct ssb_bus *bus, unsigned long data));
-
- /* b43_pci_bridge.c */
- #ifdef CONFIG_SSB_B43_PCI_BRIDGE
---- a/drivers/net/tg3.c
-+++ b/drivers/net/tg3.c
-@@ -38,6 +38,7 @@
- #include <linux/workqueue.h>
- #include <linux/prefetch.h>
- #include <linux/dma-mapping.h>
-+#include <linux/ssb/ssb_driver_gige.h>
-
- #include <net/checksum.h>
- #include <net/ip.h>
-@@ -425,8 +426,9 @@
- static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
- {
- tp->write32_mbox(tp, off, val);
-- if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
-- !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
-+ if ((tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) ||
-+ (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
-+ !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND)))
- tp->read32_mbox(tp, off);
- }
-
-@@ -706,7 +708,7 @@
-
- #define PHY_BUSY_LOOPS 5000
-
--static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
-+static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 *val)
- {
- u32 frame_val;
- unsigned int loops;
-@@ -720,7 +722,7 @@
-
- *val = 0x0;
-
-- frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
-+ frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
- MI_COM_PHY_ADDR_MASK);
- frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
- MI_COM_REG_ADDR_MASK);
-@@ -755,7 +757,12 @@
- return ret;
- }
-
--static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
-+static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
-+{
-+ return __tg3_readphy(tp, PHY_ADDR, reg, val);
-+}
-+
-+static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 val)
- {
- u32 frame_val;
- unsigned int loops;
-@@ -771,7 +778,7 @@
- udelay(80);
- }
-
-- frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
-+ frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
- MI_COM_PHY_ADDR_MASK);
- frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
- MI_COM_REG_ADDR_MASK);
-@@ -804,6 +811,11 @@
- return ret;
- }
-
-+static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
-+{
-+ return __tg3_writephy(tp, PHY_ADDR, reg, val);
-+}
-+
- static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
- {
- tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
-@@ -2250,6 +2262,14 @@
- }
- }
-
-+ if (tp->tg3_flags & TG3_FLG3_ROBOSWITCH) {
-+ current_link_up = 1;
-+ current_speed = SPEED_1000; //FIXME
-+ current_duplex = DUPLEX_FULL;
-+ tp->link_config.active_speed = current_speed;
-+ tp->link_config.active_duplex = current_duplex;
-+ }
-+
- if (current_link_up == 1 &&
- tp->link_config.active_duplex == DUPLEX_FULL)
- tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
-@@ -5197,6 +5217,11 @@
- int i;
- u32 val;
-
-+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
-+ /* We don't use firmware. */
-+ return 0;
-+ }
-+
- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
- /* Wait up to 20ms for init done. */
- for (i = 0; i < 200; i++) {
-@@ -5435,6 +5460,14 @@
- tw32(0x5000, 0x400);
- }
-
-+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
-+ /* BCM4785: In order to avoid repercussions from using potentially
-+ * defective internal ROM, stop the Rx RISC CPU, which is not
-+ * required. */
-+ tg3_stop_fw(tp);
-+ tg3_halt_cpu(tp, RX_CPU_BASE);
-+ }
-+
- tw32(GRC_MODE, tp->grc_mode);
-
- if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
-@@ -5704,9 +5737,12 @@
- return -ENODEV;
- }
-
-- /* Clear firmware's nvram arbitration. */
-- if (tp->tg3_flags & TG3_FLAG_NVRAM)
-- tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
-+ if (!(tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)) {
-+ /* Clear firmware's nvram arbitration. */
-+ if (tp->tg3_flags & TG3_FLAG_NVRAM)
-+ tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
-+ }
-+
- return 0;
- }
-
-@@ -5787,6 +5823,11 @@
- struct fw_info info;
- int err, i;
-
-+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
-+ /* We don't use firmware. */
-+ return 0;
-+ }
-+
- info.text_base = TG3_FW_TEXT_ADDR;
- info.text_len = TG3_FW_TEXT_LEN;
- info.text_data = &tg3FwText[0];
-@@ -6345,6 +6386,11 @@
- unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
- int err, i;
-
-+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
-+ /* We don't use firmware. */
-+ return 0;
-+ }
-+
- if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
- return 0;
-
-@@ -7306,6 +7352,11 @@
-
- spin_lock(&tp->lock);
-
-+ if (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) {
-+ /* BCM4785: Flush posted writes from GbE to host memory. */
-+ tr32(HOSTCC_MODE);
-+ }
-+
- if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
- /* All of this garbage is because when using non-tagged
- * IRQ status the mailbox/status_block protocol the chip
-@@ -8906,6 +8957,11 @@
- __le32 *buf;
- int i, j, k, err = 0, size;
-
-+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
-+ /* We don't have NVRAM. */
-+ return 0;
-+ }
-+
- if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
- return -EIO;
-
-@@ -9689,7 +9745,7 @@
- return -EAGAIN;
-
- spin_lock_bh(&tp->lock);
-- err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
-+ err = __tg3_readphy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, &mii_regval);
- spin_unlock_bh(&tp->lock);
-
- data->val_out = mii_regval;
-@@ -9708,7 +9764,7 @@
- return -EAGAIN;
-
- spin_lock_bh(&tp->lock);
-- err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
-+ err = __tg3_writephy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
- spin_unlock_bh(&tp->lock);
-
- return err;
-@@ -10177,6 +10233,12 @@
- /* Chips other than 5700/5701 use the NVRAM for fetching info. */
- static void __devinit tg3_nvram_init(struct tg3 *tp)
- {
-+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
-+ /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
-+ tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
-+ return;
-+ }
-+
- tw32_f(GRC_EEPROM_ADDR,
- (EEPROM_ADDR_FSM_RESET |
- (EEPROM_DEFAULT_CLOCK_PERIOD <<
-@@ -10317,6 +10379,9 @@
- {
- int ret;
-
-+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
-+ return -ENODEV;
-+
- if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
- return tg3_nvram_read_using_eeprom(tp, offset, val);
-
-@@ -10563,6 +10628,9 @@
- {
- int ret;
-
-+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
-+ return -ENODEV;
-+
- if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
- tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
- ~GRC_LCLCTRL_GPIO_OUTPUT1);
-@@ -11610,7 +11678,6 @@
- tp->write32 = tg3_write_flush_reg32;
- }
-
--
- if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
- (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
- tp->write32_tx_mbox = tg3_write32_tx_mbox;
-@@ -11646,6 +11713,11 @@
- GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
- tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
-
-+ if (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) {
-+ tp->write32_tx_mbox = tg3_write_flush_reg32;
-+ tp->write32_rx_mbox = tg3_write_flush_reg32;
-+ }
-+
- /* Get eeprom hw config before calling tg3_set_power_state().
- * In particular, the TG3_FLG2_IS_NIC flag must be
- * determined before calling tg3_set_power_state() so that
-@@ -12017,6 +12089,10 @@
- }
-
- if (!is_valid_ether_addr(&dev->dev_addr[0])) {
-+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
-+ ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
-+ }
-+ if (!is_valid_ether_addr(&dev->dev_addr[0])) {
- #ifdef CONFIG_SPARC
- if (!tg3_get_default_macaddr_sparc(tp))
- return 0;
-@@ -12508,6 +12584,7 @@
- case PHY_ID_BCM5704: return "5704";
- case PHY_ID_BCM5705: return "5705";
- case PHY_ID_BCM5750: return "5750";
-+ case PHY_ID_BCM5750_2: return "5750-2";
- case PHY_ID_BCM5752: return "5752";
- case PHY_ID_BCM5714: return "5714";
- case PHY_ID_BCM5780: return "5780";
-@@ -12695,6 +12772,13 @@
- tp->msg_enable = tg3_debug;
- else
- tp->msg_enable = TG3_DEF_MSG_ENABLE;
-+ if (pdev_is_ssb_gige_core(pdev)) {
-+ tp->tg3_flags3 |= TG3_FLG3_IS_SSB_CORE;
-+ if (ssb_gige_must_flush_posted_writes(pdev))
-+ tp->tg3_flags3 |= TG3_FLG3_FLUSH_POSTED_WRITES;
-+ if (ssb_gige_have_roboswitch(pdev))
-+ tp->tg3_flags3 |= TG3_FLG3_ROBOSWITCH;
-+ }
-
- /* The word/byte swap controls here control register access byte
- * swapping. DMA data byte swapping is controlled in the GRC_MODE
---- a/drivers/net/tg3.h
-+++ b/drivers/net/tg3.h
-@@ -2477,6 +2477,9 @@
- #define TG3_FLG3_ENABLE_APE 0x00000002
- #define TG3_FLG3_5761_5784_AX_FIXES 0x00000004
- #define TG3_FLG3_5701_DMA_BUG 0x00000008
-+#define TG3_FLG3_IS_SSB_CORE 0x00000010
-+#define TG3_FLG3_FLUSH_POSTED_WRITES 0x00000020
-+#define TG3_FLG3_ROBOSWITCH 0x00000040
-
- struct timer_list timer;
- u16 timer_counter;
-@@ -2532,6 +2535,7 @@
- #define PHY_ID_BCM5714 0x60008340
- #define PHY_ID_BCM5780 0x60008350
- #define PHY_ID_BCM5755 0xbc050cc0
-+#define PHY_ID_BCM5750_2 0xbc050cd0
- #define PHY_ID_BCM5787 0xbc050ce0
- #define PHY_ID_BCM5756 0xbc050ed0
- #define PHY_ID_BCM5784 0xbc050fa0
-@@ -2568,7 +2572,7 @@
- (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
- (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \
- (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM5761 || \
-- (X) == PHY_ID_BCM8002)
-+ (X) == PHY_ID_BCM8002 || (X) == PHY_ID_BCM5750_2)
-
- struct tg3_hw_stats *hw_stats;
- dma_addr_t stats_mapping;
---- a/drivers/ssb/driver_mipscore.c
-+++ b/drivers/ssb/driver_mipscore.c
-@@ -212,6 +212,7 @@
- /* fallthrough */
- case SSB_DEV_PCI:
- case SSB_DEV_ETHERNET:
-+ case SSB_DEV_ETHERNET_GBIT:
- case SSB_DEV_80211:
- case SSB_DEV_USB20_HOST:
- /* These devices get their own IRQ line if available, the rest goes on IRQ0 */
+++ /dev/null
-Add gpio_is_valid() for bcm47xx
---- a/arch/mips/bcm47xx/gpio.c
-+++ b/arch/mips/bcm47xx/gpio.c
-@@ -77,3 +77,15 @@
- }
- EXPORT_SYMBOL_GPL(bcm47xx_gpio_direction_output);
-
-+int bcm47xx_gpio_is_valid(int gpio)
-+{
-+ if (ssb_bcm47xx.chipco.dev) {
-+ if (gpio >= 0 && gpio < BCM47XX_CHIPCO_GPIO_LINES)
-+ return 1;
-+ } else if (ssb_bcm47xx.extif.dev) {
-+ if (gpio >= 0 && gpio < BCM47XX_EXTIF_GPIO_LINES)
-+ return 1;
-+ }
-+ return 0;
-+}
-+EXPORT_SYMBOL_GPL(bcm47xx_gpio_is_valid);
---- a/include/asm-mips/mach-bcm47xx/gpio.h
-+++ b/include/asm-mips/mach-bcm47xx/gpio.h
-@@ -17,6 +17,7 @@
- extern void bcm47xx_gpio_set_value(unsigned gpio, int value);
- extern int bcm47xx_gpio_direction_input(unsigned gpio);
- extern int bcm47xx_gpio_direction_output(unsigned gpio, int value);
-+extern int bcm47xx_gpio_is_valid(int gpio);
-
- static inline int gpio_request(unsigned gpio, const char *label)
- {
-@@ -52,6 +53,8 @@
- return bcm47xx_gpio_direction_output(gpio, value);
- }
-
-+#define gpio_is_valid bcm47xx_gpio_is_valid
-+
-
- /* cansleep wrappers */
- #include <asm-generic/gpio.h>
+++ /dev/null
---- a/arch/mips/bcm47xx/prom.c
-+++ b/arch/mips/bcm47xx/prom.c
-@@ -32,6 +32,7 @@
- #include <asm/fw/cfe/cfe_error.h>
-
- static int cfe_cons_handle;
-+static void (* __prom_putchar)(char c);
-
- const char *get_system_type(void)
- {
-@@ -40,65 +41,40 @@
-
- void prom_putchar(char c)
- {
-+ if (__prom_putchar)
-+ __prom_putchar(c);
-+}
-+
-+void prom_putchar_cfe(char c)
-+{
- while (cfe_write(cfe_cons_handle, &c, 1) == 0)
- ;
- }
-
--static __init void prom_init_cfe(void)
-+static __init int prom_init_cfe(void)
- {
- uint32_t cfe_ept;
- uint32_t cfe_handle;
- uint32_t cfe_eptseal;
-- int argc = fw_arg0;
-- char **envp = (char **) fw_arg2;
-- int *prom_vec = (int *) fw_arg3;
--
-- /*
-- * Check if a loader was used; if NOT, the 4 arguments are
-- * what CFE gives us (handle, 0, EPT and EPTSEAL)
-- */
-- if (argc < 0) {
-- cfe_handle = (uint32_t)argc;
-- cfe_ept = (uint32_t)envp;
-- cfe_eptseal = (uint32_t)prom_vec;
-- } else {
-- if ((int)prom_vec < 0) {
-- /*
-- * Old loader; all it gives us is the handle,
-- * so use the "known" entrypoint and assume
-- * the seal.
-- */
-- cfe_handle = (uint32_t)prom_vec;
-- cfe_ept = 0xBFC00500;
-- cfe_eptseal = CFE_EPTSEAL;
-- } else {
-- /*
-- * Newer loaders bundle the handle/ept/eptseal
-- * Note: prom_vec is in the loader's useg
-- * which is still alive in the TLB.
-- */
-- cfe_handle = prom_vec[0];
-- cfe_ept = prom_vec[2];
-- cfe_eptseal = prom_vec[3];
-- }
-- }
-
-- if (cfe_eptseal != CFE_EPTSEAL) {
-- /* too early for panic to do any good */
-- printk(KERN_ERR "CFE's entrypoint seal doesn't match.");
-- while (1) ;
-- }
-+ cfe_eptseal = (uint32_t) fw_arg3;
-+ cfe_handle = (uint32_t) fw_arg0;
-+ cfe_ept = (uint32_t) fw_arg2;
-+
-+ if (cfe_eptseal != CFE_EPTSEAL)
-+ return -1;
-
- cfe_init(cfe_handle, cfe_ept);
-+ return 0;
- }
-
--static __init void prom_init_console(void)
-+static __init void prom_init_console_cfe(void)
- {
- /* Initialize CFE console */
- cfe_cons_handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE);
- }
-
--static __init void prom_init_cmdline(void)
-+static __init void prom_init_cmdline_cfe(void)
- {
- char buf[CL_SIZE];
-
-@@ -146,9 +122,12 @@
-
- void __init prom_init(void)
- {
-- prom_init_cfe();
-- prom_init_console();
-- prom_init_cmdline();
-+ if (prom_init_cfe() == 0) {
-+ //prom_init_console_cfe();
-+ //prom_init_cmdline_cfe();
-+ __prom_putchar = prom_putchar_cfe;
-+ }
-+
- prom_init_mem();
- }
-
+++ /dev/null
---- linux-2.6.28.9/arch/mips/Kconfig 2009-04-17 10:43:28.000000000 +0200
-+++ linux-2.6.28.9.new/arch/mips/Kconfig 2009-04-17 10:43:51.000000000 +0200
-@@ -56,7 +56,6 @@
- select SSB_B43_PCI_BRIDGE if PCI
- select SSB_PCICORE_HOSTMODE if PCI
- select GENERIC_GPIO
-- select SYS_HAS_EARLY_PRINTK
- select CFE
- help
- Support for BCM47XX based boards
--- /dev/null
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -50,8 +50,10 @@
+ select SYS_SUPPORTS_32BIT_KERNEL
+ select SYS_SUPPORTS_LITTLE_ENDIAN
+ select SSB
++ select SSB_SERIAL
+ select SSB_DRIVER_MIPS
+ select SSB_DRIVER_EXTIF
++ select SSB_DRIVER_PCICORE
+ select SSB_PCICORE_HOSTMODE if PCI
+ select GENERIC_GPIO
+ select SYS_HAS_EARLY_PRINTK
+@@ -790,6 +792,7 @@
+
+ config CFE
+ bool
++ # Common Firmware Environment
+
+ config DMA_COHERENT
+ bool
+--- a/include/asm-mips/bootinfo.h
++++ b/include/asm-mips/bootinfo.h
+@@ -94,6 +94,12 @@
+ #define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */
+ #define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */
+
++/*
++ * Valid machtype for group Broadcom
++ */
++#define MACH_GROUP_BRCM 23 /* Broadcom */
++#define MACH_BCM47XX 1 /* Broadcom BCM47xx */
++
+ #define CL_SIZE COMMAND_LINE_SIZE
+
+ extern char *system_type;
+--- a/include/linux/pci_ids.h
++++ b/include/linux/pci_ids.h
+@@ -2001,6 +2001,7 @@
+ #define PCI_DEVICE_ID_TIGON3_5906M 0x1713
+ #define PCI_DEVICE_ID_BCM4401 0x4401
+ #define PCI_DEVICE_ID_BCM4401B0 0x4402
++#define PCI_DEVICE_ID_BCM4713 0x4713
+
+ #define PCI_VENDOR_ID_TOPIC 0x151f
+ #define PCI_DEVICE_ID_TOPIC_TP560 0x0000
--- /dev/null
+--- a/drivers/mtd/maps/Kconfig
++++ b/drivers/mtd/maps/Kconfig
+@@ -337,6 +337,12 @@
+ Mapping for the Flaga digital module. If you don't have one, ignore
+ this setting.
+
++config MTD_BCM47XX
++ tristate "BCM47xx flash device"
++ depends on MIPS && MTD_CFI && BCM47XX
++ help
++ Support for the flash chips on the BCM947xx board.
++
+ config MTD_WALNUT
+ tristate "Flash device mapped on IBM 405GP Walnut"
+ depends on MTD_JEDECPROBE && WALNUT && !PPC_MERGE
+--- a/drivers/mtd/maps/Makefile
++++ b/drivers/mtd/maps/Makefile
+@@ -31,6 +31,7 @@
+ obj-$(CONFIG_MTD_PCMCIA) += pcmciamtd.o
+ obj-$(CONFIG_MTD_RPXLITE) += rpxlite.o
+ obj-$(CONFIG_MTD_TQM8XXL) += tqm8xxl.o
++obj-$(CONFIG_MTD_BCM47XX) += bcm47xx-flash.o
+ obj-$(CONFIG_MTD_SA1100) += sa1100-flash.o
+ obj-$(CONFIG_MTD_IPAQ) += ipaq-flash.o
+ obj-$(CONFIG_MTD_SBC_GXX) += sbc_gxx.o
--- /dev/null
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -228,7 +228,6 @@
+ select I8259
+ select MIPS_BOARDS_GEN
+ select MIPS_BONITO64
+- select MIPS_CPU_SCACHE
+ select PCI_GT64XXX_PCI0
+ select MIPS_MSC
+ select SWAP_IO_SPACE
+@@ -1421,13 +1420,6 @@
+ bool
+ select BOARD_SCACHE
+
+-#
+-# Support for a MIPS32 / MIPS64 style S-caches
+-#
+-config MIPS_CPU_SCACHE
+- bool
+- select BOARD_SCACHE
+-
+ config R5000_CPU_SCACHE
+ bool
+ select BOARD_SCACHE
+--- a/arch/mips/kernel/cpu-probe.c
++++ b/arch/mips/kernel/cpu-probe.c
+@@ -704,6 +704,8 @@
+ break;
+ case PRID_IMP_25KF:
+ c->cputype = CPU_25KF;
++ /* Probe for L2 cache */
++ c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
+ break;
+ case PRID_IMP_34K:
+ c->cputype = CPU_34K;
+--- a/arch/mips/mm/c-r4k.c
++++ b/arch/mips/mm/c-r4k.c
+@@ -1103,7 +1103,6 @@
+
+ extern int r5k_sc_init(void);
+ extern int rm7k_sc_init(void);
+-extern int mips_sc_init(void);
+
+ static void __cpuinit setup_scache(void)
+ {
+@@ -1157,29 +1156,17 @@
+ #endif
+
+ default:
+- if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
+- c->isa_level == MIPS_CPU_ISA_M32R2 ||
+- c->isa_level == MIPS_CPU_ISA_M64R1 ||
+- c->isa_level == MIPS_CPU_ISA_M64R2) {
+-#ifdef CONFIG_MIPS_CPU_SCACHE
+- if (mips_sc_init ()) {
+- scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
+- printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
+- scache_size >> 10,
+- way_string[c->scache.ways], c->scache.linesz);
+- }
+-#else
+- if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
+- panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
+-#endif
+- return;
+- }
+ sc_present = 0;
+ }
+
+ if (!sc_present)
+ return;
+
++ if ((c->isa_level == MIPS_CPU_ISA_M32R1 ||
++ c->isa_level == MIPS_CPU_ISA_M64R1) &&
++ !(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
++ panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
++
+ /* compute a couple of other cache variables */
+ c->scache.waysize = scache_size / c->scache.ways;
+
+--- a/arch/mips/mm/Makefile
++++ b/arch/mips/mm/Makefile
+@@ -32,6 +32,5 @@
+ obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o
+ obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o
+ obj-$(CONFIG_RM7000_CPU_SCACHE) += sc-rm7k.o
+-obj-$(CONFIG_MIPS_CPU_SCACHE) += sc-mips.o
+
+ EXTRA_CFLAGS += -Werror
--- /dev/null
+--- a/arch/mips/kernel/genex.S
++++ b/arch/mips/kernel/genex.S
+@@ -51,6 +51,10 @@
+ NESTED(except_vec3_generic, 0, sp)
+ .set push
+ .set noat
++#ifdef CONFIG_BCM47XX
++ nop
++ nop
++#endif
+ #if R5432_CP0_INTERRUPT_WAR
+ mfc0 k0, CP0_INDEX
+ #endif
+--- a/arch/mips/mm/c-r4k.c
++++ b/arch/mips/mm/c-r4k.c
+@@ -33,6 +33,9 @@
+ #include <asm/cacheflush.h> /* for run_uncached() */
+
+
++/* For enabling BCM4710 cache workarounds */
++int bcm4710 = 0;
++
+ /*
+ * Special Variant of smp_call_function for use by cache functions:
+ *
+@@ -97,6 +100,9 @@
+ {
+ unsigned long dc_lsize = cpu_dcache_line_size();
+
++ if (bcm4710)
++ r4k_blast_dcache_page = blast_dcache_page;
++ else
+ if (dc_lsize == 0)
+ r4k_blast_dcache_page = (void *)cache_noop;
+ else if (dc_lsize == 16)
+@@ -111,6 +117,9 @@
+ {
+ unsigned long dc_lsize = cpu_dcache_line_size();
+
++ if (bcm4710)
++ r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
++ else
+ if (dc_lsize == 0)
+ r4k_blast_dcache_page_indexed = (void *)cache_noop;
+ else if (dc_lsize == 16)
+@@ -125,6 +134,9 @@
+ {
+ unsigned long dc_lsize = cpu_dcache_line_size();
+
++ if (bcm4710)
++ r4k_blast_dcache = blast_dcache;
++ else
+ if (dc_lsize == 0)
+ r4k_blast_dcache = (void *)cache_noop;
+ else if (dc_lsize == 16)
+@@ -630,6 +642,8 @@
+ unsigned long addr = (unsigned long) arg;
+
+ R4600_HIT_CACHEOP_WAR_IMPL;
++ BCM4710_PROTECTED_FILL_TLB(addr);
++ BCM4710_PROTECTED_FILL_TLB(addr + 4);
+ if (dc_lsize)
+ protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
+ if (!cpu_icache_snoops_remote_store && scache_size)
+@@ -1215,6 +1229,17 @@
+ * silly idea of putting something else there ...
+ */
+ switch (current_cpu_type()) {
++ case CPU_BCM3302:
++ {
++ u32 cm;
++ cm = read_c0_diag();
++ /* Enable icache */
++ cm |= (1 << 31);
++ /* Enable dcache */
++ cm |= (1 << 30);
++ write_c0_diag(cm);
++ }
++ break;
+ case CPU_R4000PC:
+ case CPU_R4000SC:
+ case CPU_R4000MC:
+@@ -1254,6 +1279,15 @@
+ break;
+ }
+
++ /* Check if special workarounds are required */
++#ifdef CONFIG_BCM47XX
++ if (current_cpu_data.cputype == CPU_BCM4710 && (current_cpu_data.processor_id & 0xff) == 0) {
++ printk("Enabling BCM4710A0 cache workarounds.\n");
++ bcm4710 = 1;
++ } else
++#endif
++ bcm4710 = 0;
++
+ probe_pcache();
+ setup_scache();
+
+@@ -1303,5 +1337,13 @@
+ build_clear_page();
+ build_copy_page();
+ local_r4k___flush_cache_all(NULL);
++#ifdef CONFIG_BCM47XX
++ {
++ static void (*_coherency_setup)(void);
++ _coherency_setup = (void (*)(void)) KSEG1ADDR(coherency_setup);
++ _coherency_setup();
++ }
++#else
+ coherency_setup();
++#endif
+ }
+--- a/arch/mips/mm/tlbex.c
++++ b/arch/mips/mm/tlbex.c
+@@ -677,6 +677,9 @@
+ /* No need for uasm_i_nop */
+ }
+
++#ifdef CONFIG_BCM47XX
++ uasm_i_nop(&p);
++#endif
+ #ifdef CONFIG_64BIT
+ build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
+ #else
+@@ -1084,6 +1087,9 @@
+ struct uasm_reloc **r, unsigned int pte,
+ unsigned int ptr)
+ {
++#ifdef CONFIG_BCM47XX
++ uasm_i_nop(p);
++#endif
+ #ifdef CONFIG_64BIT
+ build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */
+ #else
+--- a/include/asm-mips/r4kcache.h
++++ b/include/asm-mips/r4kcache.h
+@@ -17,6 +17,20 @@
+ #include <asm/cpu-features.h>
+ #include <asm/mipsmtregs.h>
+
++#ifdef CONFIG_BCM47XX
++#include <asm/paccess.h>
++#include <linux/ssb/ssb.h>
++#define BCM4710_DUMMY_RREG() ((void) *((u8 *) KSEG1ADDR(SSB_ENUM_BASE + SSB_IMSTATE)))
++
++#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
++#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
++#else
++#define BCM4710_DUMMY_RREG()
++
++#define BCM4710_FILL_TLB(addr)
++#define BCM4710_PROTECTED_FILL_TLB(addr)
++#endif
++
+ /*
+ * This macro return a properly sign-extended address suitable as base address
+ * for indexed cache operations. Two issues here:
+@@ -150,6 +164,7 @@
+ static inline void flush_dcache_line_indexed(unsigned long addr)
+ {
+ __dflush_prologue
++ BCM4710_DUMMY_RREG();
+ cache_op(Index_Writeback_Inv_D, addr);
+ __dflush_epilogue
+ }
+@@ -169,6 +184,7 @@
+ static inline void flush_dcache_line(unsigned long addr)
+ {
+ __dflush_prologue
++ BCM4710_DUMMY_RREG();
+ cache_op(Hit_Writeback_Inv_D, addr);
+ __dflush_epilogue
+ }
+@@ -176,6 +192,7 @@
+ static inline void invalidate_dcache_line(unsigned long addr)
+ {
+ __dflush_prologue
++ BCM4710_DUMMY_RREG();
+ cache_op(Hit_Invalidate_D, addr);
+ __dflush_epilogue
+ }
+@@ -208,6 +225,7 @@
+ */
+ static inline void protected_flush_icache_line(unsigned long addr)
+ {
++ BCM4710_DUMMY_RREG();
+ protected_cache_op(Hit_Invalidate_I, addr);
+ }
+
+@@ -219,6 +237,7 @@
+ */
+ static inline void protected_writeback_dcache_line(unsigned long addr)
+ {
++ BCM4710_DUMMY_RREG();
+ protected_cache_op(Hit_Writeback_Inv_D, addr);
+ }
+
+@@ -339,8 +358,52 @@
+ : "r" (base), \
+ "i" (op));
+
++static inline void blast_dcache(void)
++{
++ unsigned long start = KSEG0;
++ unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways;
++ unsigned long end = (start + dcache_size);
++
++ do {
++ BCM4710_DUMMY_RREG();
++ cache_op(Index_Writeback_Inv_D, start);
++ start += current_cpu_data.dcache.linesz;
++ } while(start < end);
++}
++
++static inline void blast_dcache_page(unsigned long page)
++{
++ unsigned long start = page;
++ unsigned long end = start + PAGE_SIZE;
++
++ BCM4710_FILL_TLB(start);
++ do {
++ BCM4710_DUMMY_RREG();
++ cache_op(Hit_Writeback_Inv_D, start);
++ start += current_cpu_data.dcache.linesz;
++ } while(start < end);
++}
++
++static inline void blast_dcache_page_indexed(unsigned long page)
++{
++ unsigned long start = page;
++ unsigned long end = start + PAGE_SIZE;
++ unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
++ unsigned long ws_end = current_cpu_data.dcache.ways <<
++ current_cpu_data.dcache.waybit;
++ unsigned long ws, addr;
++ for (ws = 0; ws < ws_end; ws += ws_inc) {
++ start = page + ws;
++ for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) {
++ BCM4710_DUMMY_RREG();
++ cache_op(Index_Writeback_Inv_D, addr);
++ }
++ }
++}
++
++
+ /* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
+-#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize) \
++#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, war) \
+ static inline void blast_##pfx##cache##lsize(void) \
+ { \
+ unsigned long start = INDEX_BASE; \
+@@ -352,6 +415,7 @@
+ \
+ __##pfx##flush_prologue \
+ \
++ war \
+ for (ws = 0; ws < ws_end; ws += ws_inc) \
+ for (addr = start; addr < end; addr += lsize * 32) \
+ cache##lsize##_unroll32(addr|ws, indexop); \
+@@ -366,6 +430,7 @@
+ \
+ __##pfx##flush_prologue \
+ \
++ war \
+ do { \
+ cache##lsize##_unroll32(start, hitop); \
+ start += lsize * 32; \
+@@ -384,6 +449,8 @@
+ current_cpu_data.desc.waybit; \
+ unsigned long ws, addr; \
+ \
++ war \
++ \
+ __##pfx##flush_prologue \
+ \
+ for (ws = 0; ws < ws_end; ws += ws_inc) \
+@@ -393,35 +460,37 @@
+ __##pfx##flush_epilogue \
+ }
+
+-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16)
+-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
+-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
+-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
+-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
+-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
+-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
+-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
+-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
+-
+-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16)
+-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32)
+-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16)
+-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32)
+-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64)
+-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128)
++__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
++__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, BCM4710_FILL_TLB(start);)
++__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
++__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
++__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, BCM4710_FILL_TLB(start);)
++__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
++__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, BCM4710_FILL_TLB(start);)
++__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
++__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
++
++__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )
++__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, )
++__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, )
++__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, )
++__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, )
++__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, )
+
+ /* build blast_xxx_range, protected_blast_xxx_range */
+-#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
++#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, war, war2) \
+ static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
+ unsigned long end) \
+ { \
+ unsigned long lsize = cpu_##desc##_line_size(); \
+ unsigned long addr = start & ~(lsize - 1); \
+ unsigned long aend = (end - 1) & ~(lsize - 1); \
++ war \
+ \
+ __##pfx##flush_prologue \
+ \
+ while (1) { \
++ war2 \
+ prot##cache_op(hitop, addr); \
+ if (addr == aend) \
+ break; \
+@@ -431,13 +500,13 @@
+ __##pfx##flush_epilogue \
+ }
+
+-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_)
+-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_)
+-__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_)
+-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, )
+-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, )
++__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
++__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_,, )
++__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_,, )
++__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D,, BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
++__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD,,, )
+ /* blast_inv_dcache_range */
+-__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, )
+-__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, )
++__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D,,,BCM4710_DUMMY_RREG();)
++__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD,,, )
+
+ #endif /* _ASM_R4KCACHE_H */
+--- a/include/asm-mips/stackframe.h
++++ b/include/asm-mips/stackframe.h
+@@ -359,6 +359,10 @@
+ .macro RESTORE_SP_AND_RET
+ LONG_L sp, PT_R29(sp)
+ .set mips3
++#ifdef CONFIG_BCM47XX
++ nop
++ nop
++#endif
+ eret
+ .set mips0
+ .endm
--- /dev/null
+--- a/arch/mips/mm/init.c
++++ b/arch/mips/mm/init.c
+@@ -211,7 +211,7 @@
+ void *vfrom, *vto;
+
+ vto = kmap_atomic(to, KM_USER1);
+- if (cpu_has_dc_aliases &&
++ if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
+ page_mapped(from) && !Page_dcache_dirty(from)) {
+ vfrom = kmap_coherent(from, vaddr);
+ copy_page(vto, vfrom);
+@@ -235,7 +235,7 @@
+ struct page *page, unsigned long vaddr, void *dst, const void *src,
+ unsigned long len)
+ {
+- if (cpu_has_dc_aliases &&
++ if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
+ page_mapped(page) && !Page_dcache_dirty(page)) {
+ void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
+ memcpy(vto, src, len);
+@@ -255,7 +255,7 @@
+ struct page *page, unsigned long vaddr, void *dst, const void *src,
+ unsigned long len)
+ {
+- if (cpu_has_dc_aliases &&
++ if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
+ page_mapped(page) && !Page_dcache_dirty(page)) {
+ void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
+ memcpy(dst, vfrom, len);
+--- /dev/null
++++ b/include/asm-mips/mach-bcm47xx/cpu-feature-overrides.h
+@@ -0,0 +1,13 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
++ */
++#ifndef __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H
++#define __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H
++
++#define cpu_use_kmap_coherent 0
++
++#endif /* __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H */
+--- a/include/asm-mips/cpu-features.h
++++ b/include/asm-mips/cpu-features.h
+@@ -101,6 +101,9 @@
+ #ifndef cpu_has_pindexed_dcache
+ #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
+ #endif
++#ifndef cpu_use_kmap_coherent
++#define cpu_use_kmap_coherent 1
++#endif
+
+ /*
+ * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
+--- a/arch/mips/mm/c-r4k.c
++++ b/arch/mips/mm/c-r4k.c
+@@ -484,7 +484,7 @@
+ * Use kmap_coherent or kmap_atomic to do flushes for
+ * another ASID than the current one.
+ */
+- if (cpu_has_dc_aliases)
++ if (cpu_has_dc_aliases && cpu_use_kmap_coherent)
+ vaddr = kmap_coherent(page, addr);
+ else
+ vaddr = kmap_atomic(page, KM_USER0);
+@@ -505,7 +505,7 @@
+ }
+
+ if (vaddr) {
+- if (cpu_has_dc_aliases)
++ if (cpu_has_dc_aliases && cpu_use_kmap_coherent)
+ kunmap_coherent();
+ else
+ kunmap_atomic(vaddr, KM_USER0);
--- /dev/null
+Index: linux-2.6.25.17/drivers/net/b44.c
+===================================================================
+--- linux-2.6.25.17.orig/drivers/net/b44.c 2008-10-16 23:13:19.000000000 +0200
++++ linux-2.6.25.17/drivers/net/b44.c 2008-11-02 12:13:38.000000000 +0100
+@@ -339,7 +339,7 @@ static int b44_phy_reset(struct b44 *bp)
+ }
+ }
+
+- return 0;
++ return err;
+ }
+
+ static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags)
+@@ -384,7 +384,7 @@ static void b44_set_flow_ctrl(struct b44
+ __b44_set_flow_ctrl(bp, pause_enab);
+ }
+
+-#ifdef SSB_DRIVER_MIPS
++#ifdef CONFIG_SSB_DRIVER_MIPS
+ extern char *nvram_get(char *name);
+ static void b44_wap54g10_workaround(struct b44 *bp)
+ {
+@@ -2211,6 +2211,10 @@ static int __devinit b44_init_one(struct
+ */
+ b44_chip_reset(bp, B44_CHIP_RESET_FULL);
+
++ /* do a phy reset to test if there is an active phy */
++ if (b44_phy_reset(bp) < 0)
++ bp->phy_addr = B44_PHY_ADDR_NO_PHY;
++
+ printk(KERN_INFO "%s: Broadcom 44xx/47xx 10/100BaseT Ethernet %s\n",
+ dev->name, print_mac(mac, dev->dev_addr));
+
--- /dev/null
+--- a/drivers/net/b44.c 2008-11-16 15:33:32.000000000 +0100
++++ b/drivers/net/b44.c 2008-11-18 10:36:18.000000000 +0100
+@@ -2094,6 +2094,11 @@
+ return -EINVAL;
+ }
+
++ if (bp->sdev->id.coreid == 0x806 && bp->sdev->id.revision == 0x0) {
++ bp->phy_addr = B44_PHY_ADDR_NO_PHY;
++ bp->dma_offset = 0;
++ }
++
+ memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
+
+ bp->imask = IMASK_DEF;
--- /dev/null
+--- a/drivers/net/b44.c
++++ b/drivers/net/b44.c
+@@ -73,8 +73,8 @@
+ (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP))
+ #define NEXT_TX(N) (((N) + 1) & (B44_TX_RING_SIZE - 1))
+
+-#define RX_PKT_OFFSET 30
+-#define RX_PKT_BUF_SZ (1536 + RX_PKT_OFFSET + 64)
++#define RX_PKT_OFFSET (RX_HEADER_LEN + 2)
++#define RX_PKT_BUF_SZ (1536 + RX_PKT_OFFSET)
+
+ /* minimum number of free TX descriptors required to wake up TX process */
+ #define B44_TX_WAKEUP_THRESH (B44_TX_RING_SIZE / 4)
+@@ -682,7 +682,6 @@ static int b44_alloc_rx_skb(struct b44 *
+ }
+
+ rh = (struct rx_header *) skb->data;
+- skb_reserve(skb, RX_PKT_OFFSET);
+
+ rh->len = 0;
+ rh->flags = 0;
+@@ -693,13 +692,13 @@ static int b44_alloc_rx_skb(struct b44 *
+ if (src_map != NULL)
+ src_map->skb = NULL;
+
+- ctrl = (DESC_CTRL_LEN & (RX_PKT_BUF_SZ - RX_PKT_OFFSET));
++ ctrl = (DESC_CTRL_LEN & RX_PKT_BUF_SZ);
+ if (dest_idx == (B44_RX_RING_SIZE - 1))
+ ctrl |= DESC_CTRL_EOT;
+
+ dp = &bp->rx_ring[dest_idx];
+ dp->ctrl = cpu_to_le32(ctrl);
+- dp->addr = cpu_to_le32((u32) mapping + RX_PKT_OFFSET + bp->dma_offset);
++ dp->addr = cpu_to_le32((u32) mapping + bp->dma_offset);
+
+ if (bp->flags & B44_FLAG_RX_RING_HACK)
+ b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
+@@ -809,8 +808,8 @@ static int b44_rx(struct b44 *bp, int bu
+ dma_unmap_single(bp->sdev->dma_dev, map,
+ skb_size, DMA_FROM_DEVICE);
+ /* Leave out rx_header */
+- skb_put(skb, len + RX_PKT_OFFSET);
+- skb_pull(skb, RX_PKT_OFFSET);
++ skb_put(skb, len + RX_PKT_OFFSET);
++ skb_pull(skb, RX_PKT_OFFSET);
+ } else {
+ struct sk_buff *copy_skb;
+
--- /dev/null
+--- a/drivers/ssb/driver_chipcommon.c
++++ b/drivers/ssb/driver_chipcommon.c
+@@ -270,6 +270,8 @@
+ void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
+ u32 *plltype, u32 *n, u32 *m)
+ {
++ if ((chipco_read32(cc, SSB_CHIPCO_CHIPID) & SSB_CHIPCO_IDMASK) == 0x5354)
++ return;
+ *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
+ *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
+ switch (*plltype) {
+@@ -293,6 +295,8 @@
+ void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
+ u32 *plltype, u32 *n, u32 *m)
+ {
++ if ((chipco_read32(cc, SSB_CHIPCO_CHIPID) & SSB_CHIPCO_IDMASK) == 0x5354)
++ return;
+ *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
+ *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
+ switch (*plltype) {
+--- a/drivers/ssb/driver_mipscore.c
++++ b/drivers/ssb/driver_mipscore.c
+@@ -161,6 +161,8 @@
+
+ if ((pll_type == SSB_PLLTYPE_5) || (bus->chip_id == 0x5365)) {
+ rate = 200000000;
++ } else if (bus->chip_id == 0x5354) {
++ rate = 240000000;
+ } else {
+ rate = ssb_calc_clock_rate(pll_type, n, m);
+ }
+--- a/drivers/ssb/main.c
++++ b/drivers/ssb/main.c
+@@ -867,6 +867,8 @@
+
+ if (bus->chip_id == 0x5365) {
+ rate = 100000000;
++ } else if (bus->chip_id == 0x5354) {
++ rate = 120000000;
+ } else {
+ rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
+ if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */
--- /dev/null
+--- a/drivers/usb/host/ohci-ssb.c
++++ b/drivers/usb/host/ohci-ssb.c
+@@ -142,10 +142,59 @@
+ int err = -ENOMEM;
+ u32 tmp, flags = 0;
+
+- if (dev->id.coreid == SSB_DEV_USB11_HOSTDEV)
++ /*
++ * THE FOLLOWING COMMENTS PRESERVED FROM GPL SOURCE RELEASE
++ *
++ * The USB core requires a special bit to be set during core
++ * reset to enable host (OHCI) mode. Resetting the SB core in
++ * pcibios_enable_device() is a hack for compatibility with
++ * vanilla usb-ohci so that it does not have to know about
++ * SB. A driver that wants to use the USB core in device mode
++ * should know about SB and should reset the bit back to 0
++ * after calling pcibios_enable_device().
++ */
++
++ if (dev->id.coreid == SSB_DEV_USB11_HOSTDEV) {
+ flags |= SSB_OHCI_TMSLOW_HOSTMODE;
++ ssb_device_enable(dev, flags);
++ }
++
++ /*
++ * USB 2.0 special considerations:
++ *
++ * 1. Since the core supports both OHCI and EHCI functions, it must
++ * only be reset once.
++ *
++ * 2. In addition to the standard SB reset sequence, the Host Control
++ * Register must be programmed to bring the USB core and various
++ * phy components out of reset.
++ */
++
++ else if (dev->id.coreid == SSB_DEV_USB20_HOST) {
++#warning FIX ME need test for core being up & exit
++ ssb_device_enable(dev, 0);
++ ssb_write32(dev, 0x200, 0x7ff);
++ udelay(1);
++ if (dev->id.revision == 1) { // bug in rev 1
++
++ /* Change Flush control reg */
++ tmp = ssb_read32(dev, 0x400);
++ tmp &= ~8;
++ ssb_write32(dev, 0x400, tmp);
++ tmp = ssb_read32(dev, 0x400);
++ printk("USB20H fcr: 0x%0x\n", tmp);
++
++ /* Change Shim control reg */
++ tmp = ssb_read32(dev, 0x304);
++ tmp &= ~0x100;
++ ssb_write32(dev, 0x304, tmp);
++ tmp = ssb_read32(dev, 0x304);
++ printk("USB20H shim: 0x%0x\n", tmp);
++ }
++ }
++ else
++ ssb_device_enable(dev, 0);
+
+- ssb_device_enable(dev, flags);
+
+ hcd = usb_create_hcd(&ssb_ohci_hc_driver, dev->dev,
+ dev->dev->bus_id);
+@@ -236,6 +285,7 @@
+ static const struct ssb_device_id ssb_ohci_table[] = {
+ SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOSTDEV, SSB_ANY_REV),
+ SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOST, SSB_ANY_REV),
++ SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB20_HOST, SSB_ANY_REV),
+ SSB_DEVTABLE_END
+ };
+ MODULE_DEVICE_TABLE(ssb, ssb_ohci_table);
--- /dev/null
+--- a/drivers/usb/host/ohci-ssb.c
++++ b/drivers/usb/host/ohci-ssb.c
+@@ -195,6 +195,11 @@
+ else
+ ssb_device_enable(dev, 0);
+
++ /*
++ * Set dma mask - 32 bit mask is just an assumption
++ */
++ if (ssb_dma_set_mask(dev, DMA_32BIT_MASK))
++ return -EOPNOTSUPP;
+
+ hcd = usb_create_hcd(&ssb_ohci_hc_driver, dev->dev,
+ dev->dev->bus_id);
--- /dev/null
+--- a/include/asm-mips/cacheflush.h
++++ b/include/asm-mips/cacheflush.h
+@@ -32,7 +32,7 @@
+ extern void (*flush_cache_all)(void);
+ extern void (*__flush_cache_all)(void);
+ extern void (*flush_cache_mm)(struct mm_struct *mm);
+-#define flush_cache_dup_mm(mm) do { (void) (mm); } while (0)
++#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
+ extern void (*flush_cache_range)(struct vm_area_struct *vma,
+ unsigned long start, unsigned long end);
+ extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn);
--- /dev/null
+--- a/arch/mips/mm/init.c
++++ b/arch/mips/mm/init.c
+@@ -205,32 +205,6 @@
+ preempt_check_resched();
+ }
+
+-void copy_user_highpage(struct page *to, struct page *from,
+- unsigned long vaddr, struct vm_area_struct *vma)
+-{
+- void *vfrom, *vto;
+-
+- vto = kmap_atomic(to, KM_USER1);
+- if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
+- page_mapped(from) && !Page_dcache_dirty(from)) {
+- vfrom = kmap_coherent(from, vaddr);
+- copy_page(vto, vfrom);
+- kunmap_coherent();
+- } else {
+- vfrom = kmap_atomic(from, KM_USER0);
+- copy_page(vto, vfrom);
+- kunmap_atomic(vfrom, KM_USER0);
+- }
+- if (((vma->vm_flags & VM_EXEC) && !cpu_has_ic_fills_f_dc) ||
+- pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
+- flush_data_cache_page((unsigned long)vto);
+- kunmap_atomic(vto, KM_USER1);
+- /* Make sure this page is cleared on other CPU's too before using it */
+- smp_wmb();
+-}
+-
+-EXPORT_SYMBOL(copy_user_highpage);
+-
+ void copy_to_user_page(struct vm_area_struct *vma,
+ struct page *page, unsigned long vaddr, void *dst, const void *src,
+ unsigned long len)
+--- a/include/asm-mips/page.h
++++ b/include/asm-mips/page.h
+@@ -32,6 +32,7 @@
+ #ifndef __ASSEMBLY__
+
+ #include <linux/pfn.h>
++#include <asm/cpu-features.h>
+ #include <asm/io.h>
+
+ /*
+@@ -64,13 +65,16 @@
+ flush_data_cache_page((unsigned long)addr);
+ }
+
+-extern void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
+- struct page *to);
+-struct vm_area_struct;
+-extern void copy_user_highpage(struct page *to, struct page *from,
+- unsigned long vaddr, struct vm_area_struct *vma);
++static inline void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
++ struct page *to)
++{
++ extern void (*flush_data_cache_page)(unsigned long addr);
+
+-#define __HAVE_ARCH_COPY_USER_HIGHPAGE
++ copy_page(vto, vfrom);
++ if (!cpu_has_ic_fills_f_dc ||
++ pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
++ flush_data_cache_page((unsigned long)vto);
++}
+
+ /*
+ * These are used to make use of C type-checking..
--- /dev/null
+--- a/arch/mips/bcm47xx/irq.c
++++ b/arch/mips/bcm47xx/irq.c
+@@ -1,5 +1,6 @@
+ /*
+ * Copyright (C) 2004 Florian Schirmer <jolt@tuxbox.org>
++ * Copyright (C) 2008 Michael Buesch <mb@bu3sch.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+@@ -23,10 +24,19 @@
+ */
+
+ #include <linux/types.h>
++#include <linux/errno.h>
++#include <linux/init.h>
+ #include <linux/interrupt.h>
+ #include <linux/irq.h>
++#include <linux/pci.h>
++#include <linux/ssb/ssb.h>
++
+ #include <asm/irq_cpu.h>
+
++
++extern struct ssb_bus ssb_bcm47xx;
++
++
+ void plat_irq_dispatch(void)
+ {
+ u32 cause;
+@@ -53,3 +63,19 @@
+ {
+ mips_cpu_irq_init();
+ }
++
++int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
++{
++ int res;
++
++ res = ssb_pcibios_map_irq(dev, slot, pin);
++ if (res < 0) {
++ printk(KERN_ALERT "PCI: Failed to map IRQ of device %s\n",
++ dev->dev.bus_id);
++ return 0;
++ }
++ /* IRQ-0 and IRQ-1 are software interrupts. */
++ WARN_ON((res == 0) || (res == 1));
++
++ return res;
++}
+--- a/arch/mips/bcm47xx/setup.c
++++ b/arch/mips/bcm47xx/setup.c
+@@ -2,7 +2,7 @@
+ * Copyright (C) 2004 Florian Schirmer <jolt@tuxbox.org>
+ * Copyright (C) 2005 Waldemar Brodkorb <wbx@openwrt.org>
+ * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
+- * Copyright (C) 2006 Michael Buesch <mb@bu3sch.de>
++ * Copyright (C) 2006-2008 Michael Buesch <mb@bu3sch.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+@@ -25,23 +25,52 @@
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
++#include <linux/init.h>
+ #include <linux/types.h>
+-#include <linux/ssb/ssb.h>
++#include <linux/tty.h>
++#include <linux/serial.h>
++#include <linux/serial_core.h>
++#include <linux/serial_reg.h>
++#include <linux/serial_8250.h>
+ #include <asm/bootinfo.h>
+-#include <asm/reboot.h>
+ #include <asm/time.h>
+-#include <bcm47xx.h>
++#include <asm/reboot.h>
+ #include <asm/fw/cfe/cfe_api.h>
++#include <linux/pm.h>
++#include <linux/ssb/ssb.h>
++#include <linux/ssb/ssb_embedded.h>
++
++#include "include/nvram.h"
+
+ struct ssb_bus ssb_bcm47xx;
+ EXPORT_SYMBOL(ssb_bcm47xx);
+
++extern void bcm47xx_pci_init(void);
++
++int pcibios_plat_dev_init(struct pci_dev *dev)
++{
++ int err;
++
++ err = ssb_pcibios_plat_dev_init(dev);
++ if (err) {
++ printk(KERN_ALERT "PCI: Failed to init device %s\n",
++ pci_name(dev));
++ }
++
++ return err;
++}
++
+ static void bcm47xx_machine_restart(char *command)
+ {
+ printk(KERN_ALERT "Please stand by while rebooting the system...\n");
+ local_irq_disable();
++ /* CFE has a reboot callback, but that does not work.
++ * Oopses with: Reserved instruction in kernel code.
++ */
++
+ /* Set the watchdog timer to reset immediately */
+- ssb_chipco_watchdog_timer_set(&ssb_bcm47xx.chipco, 1);
++ if (ssb_watchdog_timer_set(&ssb_bcm47xx, 1))
++ printk(KERN_EMERG "SSB watchdog-triggered reboot failed!\n");
+ while (1)
+ cpu_relax();
+ }
+@@ -50,12 +79,13 @@
+ {
+ /* Disable interrupts and watchdog and spin forever */
+ local_irq_disable();
+- ssb_chipco_watchdog_timer_set(&ssb_bcm47xx.chipco, 0);
++ if (ssb_watchdog_timer_set(&ssb_bcm47xx, 0))
++ printk(KERN_EMERG "Failed to disable SSB watchdog!\n");
+ while (1)
+ cpu_relax();
+ }
+
+-static void str2eaddr(char *str, char *dest)
++static void e_aton(char *str, char *dest)
+ {
+ int i = 0;
+
+@@ -72,52 +102,142 @@
+ }
+ }
+
+-static int bcm47xx_get_invariants(struct ssb_bus *bus,
+- struct ssb_init_invariants *iv)
++static void bcm47xx_fill_sprom(struct ssb_sprom *sprom)
+ {
+- char buf[100];
++ char *s;
+
+- /* Fill boardinfo structure */
+- memset(&(iv->boardinfo), 0 , sizeof(struct ssb_boardinfo));
++ memset(sprom, 0xFF, sizeof(struct ssb_sprom));
+
+- if (cfe_getenv("boardvendor", buf, sizeof(buf)) >= 0)
+- iv->boardinfo.type = (u16)simple_strtoul(buf, NULL, 0);
+- if (cfe_getenv("boardtype", buf, sizeof(buf)) >= 0)
+- iv->boardinfo.type = (u16)simple_strtoul(buf, NULL, 0);
+- if (cfe_getenv("boardrev", buf, sizeof(buf)) >= 0)
+- iv->boardinfo.rev = (u16)simple_strtoul(buf, NULL, 0);
+-
+- /* Fill sprom structure */
+- memset(&(iv->sprom), 0, sizeof(struct ssb_sprom));
+- iv->sprom.revision = 3;
+-
+- if (cfe_getenv("et0macaddr", buf, sizeof(buf)) >= 0)
+- str2eaddr(buf, iv->sprom.et0mac);
+- if (cfe_getenv("et1macaddr", buf, sizeof(buf)) >= 0)
+- str2eaddr(buf, iv->sprom.et1mac);
+- if (cfe_getenv("et0phyaddr", buf, sizeof(buf)) >= 0)
+- iv->sprom.et0phyaddr = simple_strtoul(buf, NULL, 10);
+- if (cfe_getenv("et1phyaddr", buf, sizeof(buf)) >= 0)
+- iv->sprom.et1phyaddr = simple_strtoul(buf, NULL, 10);
+- if (cfe_getenv("et0mdcport", buf, sizeof(buf)) >= 0)
+- iv->sprom.et0mdcport = simple_strtoul(buf, NULL, 10);
+- if (cfe_getenv("et1mdcport", buf, sizeof(buf)) >= 0)
+- iv->sprom.et1mdcport = simple_strtoul(buf, NULL, 10);
++ sprom->revision = 1;
++ if ((s = nvram_get("il0macaddr")))
++ e_aton(s, sprom->il0mac);
++ if ((s = nvram_get("et0macaddr")))
++ e_aton(s, sprom->et0mac);
++ if ((s = nvram_get("et1macaddr")))
++ e_aton(s, sprom->et1mac);
++ if ((s = nvram_get("et0phyaddr")))
++ sprom->et0phyaddr = simple_strtoul(s, NULL, 0);
++ if ((s = nvram_get("et1phyaddr")))
++ sprom->et1phyaddr = simple_strtoul(s, NULL, 0);
++ if ((s = nvram_get("et0mdcport")))
++ sprom->et0mdcport = !!simple_strtoul(s, NULL, 10);
++ if ((s = nvram_get("et1mdcport")))
++ sprom->et1mdcport = !!simple_strtoul(s, NULL, 10);
++ if ((s = nvram_get("pa0b0")))
++ sprom->pa0b0 = simple_strtoul(s, NULL, 0);
++ if ((s = nvram_get("pa0b1")))
++ sprom->pa0b1 = simple_strtoul(s, NULL, 0);
++ if ((s = nvram_get("pa0b2")))
++ sprom->pa0b2 = simple_strtoul(s, NULL, 0);
++ if ((s = nvram_get("pa1b0")))
++ sprom->pa1b0 = simple_strtoul(s, NULL, 0);
++ if ((s = nvram_get("pa1b1")))
++ sprom->pa1b1 = simple_strtoul(s, NULL, 0);
++ if ((s = nvram_get("pa1b2")))
++ sprom->pa1b2 = simple_strtoul(s, NULL, 0);
++ if ((s = nvram_get("wl0gpio0")))
++ sprom->gpio0 = simple_strtoul(s, NULL, 0);
++ if ((s = nvram_get("wl0gpio1")))
++ sprom->gpio1 = simple_strtoul(s, NULL, 0);
++ if ((s = nvram_get("wl0gpio2")))
++ sprom->gpio2 = simple_strtoul(s, NULL, 0);
++ if ((s = nvram_get("wl0gpio3")))
++ sprom->gpio3 = simple_strtoul(s, NULL, 0);
++ if ((s = nvram_get("pa0maxpwr")))
++ sprom->maxpwr_bg = simple_strtoul(s, NULL, 0);
++ if ((s = nvram_get("pa1maxpwr")))
++ sprom->maxpwr_a = simple_strtoul(s, NULL, 0);
++ if ((s = nvram_get("pa0itssit")))
++ sprom->itssi_bg = simple_strtoul(s, NULL, 0);
++ if ((s = nvram_get("pa1itssit")))
++ sprom->itssi_a = simple_strtoul(s, NULL, 0);
++ sprom->boardflags_lo = 0;
++ if ((s = nvram_get("boardflags")))
++ sprom->boardflags_lo = simple_strtoul(s, NULL, 0);
++ sprom->boardflags_hi = 0;
++ if ((s = nvram_get("boardflags2")))
++ sprom->boardflags_hi = simple_strtoul(s, NULL, 0);
++}
++
++static int bcm47xx_get_invariants(struct ssb_bus *bus, struct ssb_init_invariants *iv)
++{
++ char *s;
++
++ iv->boardinfo.vendor = SSB_BOARDVENDOR_BCM;
++ if ((s = nvram_get("boardtype")))
++ iv->boardinfo.type = (u16)simple_strtoul(s, NULL, 0);
++ if ((s = nvram_get("boardrev")))
++ iv->boardinfo.rev = (u16)simple_strtoul(s, NULL, 0);
++
++ bcm47xx_fill_sprom(&iv->sprom);
++
++ if ((s = nvram_get("cardbus")))
++ iv->has_cardbus_slot = !!simple_strtoul(s, NULL, 10);
+
+ return 0;
+ }
+
+ void __init plat_mem_setup(void)
+ {
+- int err;
++ int i, err;
++ char *s;
++ struct ssb_mipscore *mcore;
++
++ err = ssb_bus_ssbbus_register(&ssb_bcm47xx, SSB_ENUM_BASE, bcm47xx_get_invariants);
++ if (err) {
++ const char *msg = "Failed to initialize SSB bus (err %d)\n";
++ printk(msg, err); /* Make sure the message gets out of the box. */
++ panic(msg, err);
++ }
++ mcore = &ssb_bcm47xx.mipscore;
++
++ s = nvram_get("kernel_args");
++ if (s && !strncmp(s, "console=ttyS1", 13)) {
++ struct ssb_serial_port port;
++
++ printk("Swapping serial ports!\n");
++ /* swap serial ports */
++ memcpy(&port, &mcore->serial_ports[0], sizeof(port));
++ memcpy(&mcore->serial_ports[0], &mcore->serial_ports[1], sizeof(port));
++ memcpy(&mcore->serial_ports[1], &port, sizeof(port));
++ }
+
+- err = ssb_bus_ssbbus_register(&ssb_bcm47xx, SSB_ENUM_BASE,
+- bcm47xx_get_invariants);
+- if (err)
+- panic("Failed to initialize SSB bus (err %d)\n", err);
++ for (i = 0; i < mcore->nr_serial_ports; i++) {
++ struct ssb_serial_port *port = &(mcore->serial_ports[i]);
++ struct uart_port s;
++
++ memset(&s, 0, sizeof(s));
++ s.line = i;
++ s.mapbase = (unsigned int) port->regs;
++ s.membase = port->regs;
++ s.irq = port->irq + 2;
++ s.uartclk = port->baud_base;
++ s.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
++ s.iotype = SERIAL_IO_MEM;
++ s.regshift = port->reg_shift;
++
++ early_serial_setup(&s);
++ }
++ printk("Serial init done.\n");
+
+ _machine_restart = bcm47xx_machine_restart;
+ _machine_halt = bcm47xx_machine_halt;
+ pm_power_off = bcm47xx_machine_halt;
+ }
+
++static int __init bcm47xx_register_gpiodev(void)
++{
++ static struct resource res = {
++ .start = 0xFFFFFFFF,
++ };
++ struct platform_device *pdev;
++
++ pdev = platform_device_register_simple("GPIODEV", 0, &res, 1);
++ if (!pdev) {
++ printk(KERN_ERR "bcm47xx: GPIODEV init failed\n");
++ return -ENODEV;
++ }
++
++ return 0;
++}
++device_initcall(bcm47xx_register_gpiodev);
+--- a/arch/mips/bcm47xx/time.c
++++ b/arch/mips/bcm47xx/time.c
+@@ -22,11 +22,17 @@
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+-
+ #include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/sched.h>
++#include <linux/serial_reg.h>
++#include <linux/interrupt.h>
+ #include <linux/ssb/ssb.h>
++#include <asm/addrspace.h>
++#include <asm/io.h>
+ #include <asm/time.h>
+-#include <bcm47xx.h>
++
++extern struct ssb_bus ssb_bcm47xx;
+
+ void __init plat_time_init(void)
+ {
+--- a/arch/mips/bcm47xx/nvram.c
++++ b/arch/mips/bcm47xx/nvram.c
+@@ -24,10 +24,10 @@
+ #include <asm/io.h>
+ #include <asm/uaccess.h>
+
+-#include <nvram.h>
++#include "include/nvram.h"
+
+ #define MB * 1048576
+-extern struct ssb_bus ssb;
++extern struct ssb_bus ssb_bcm47xx;
+
+ static char nvram_buf[NVRAM_SPACE];
+ static int cfe_env;
+@@ -36,7 +36,7 @@
+ /* Probe for NVRAM header */
+ static void __init early_nvram_init(void)
+ {
+- struct ssb_mipscore *mcore = &ssb.mipscore;
++ struct ssb_mipscore *mcore = &ssb_bcm47xx.mipscore;
+ struct nvram_header *header;
+ int i;
+ u32 base, lim, off;
+--- a/arch/mips/bcm47xx/Makefile
++++ b/arch/mips/bcm47xx/Makefile
+@@ -3,4 +3,4 @@
+ # under Linux.
+ #
+
+-obj-y := gpio.o irq.o prom.o serial.o setup.o time.o wgt634u.o
++obj-y := cfe_env.o gpio.o irq.o nvram.o prom.o serial.o setup.o time.o wgt634u.o
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -54,6 +54,7 @@
+ select SSB_DRIVER_MIPS
+ select SSB_DRIVER_EXTIF
+ select SSB_DRIVER_PCICORE
++ select SSB_B43_PCI_BRIDGE
+ select SSB_PCICORE_HOSTMODE if PCI
+ select GENERIC_GPIO
+ select SYS_HAS_EARLY_PRINTK
--- /dev/null
+--- a/scripts/gen_initramfs_list.sh
++++ b/scripts/gen_initramfs_list.sh
+@@ -287,7 +287,7 @@
+ if [ "${is_cpio_compressed}" = "compressed" ]; then
+ cat ${cpio_tfile} > ${output_file}
+ else
+- cat ${cpio_tfile} | gzip -f -9 - > ${output_file}
++ lzma e -lc1 -lp2 -pb2 ${cpio_tfile} ${output_file}
+ fi
+ [ -z ${cpio_file} ] && rm ${cpio_tfile}
+ fi
+--- a/init/initramfs.c
++++ b/init/initramfs.c
+@@ -441,6 +441,69 @@
+ outcnt = 0;
+ }
+
++#include <linux/LzmaDecode.h>
++static int __init lzma_unzip(void)
++{
++ unsigned int i; /* temp value */
++ unsigned int lc; /* literal context bits */
++ unsigned int lp; /* literal pos state bits */
++ unsigned int pb; /* pos state bits */
++ unsigned int osize; /* uncompressed size */
++ unsigned char *workspace;
++ unsigned char* outputbuffer;
++ unsigned int outsizeProcessed = 0;
++ int workspace_size;
++ int res;
++
++ // lzma args
++ i = get_byte();
++ lc = i % 9, i = i / 9;
++ lp = i % 5, pb = i / 5;
++
++ // skip dictionary size
++ for (i = 0; i < 4; i++)
++ get_byte();
++
++ /* read the lower half of uncompressed size in the header */
++ osize = ((unsigned int)get_byte()) +
++ ((unsigned int)get_byte() << 8) +
++ ((unsigned int)get_byte() << 16) +
++ ((unsigned int)get_byte() << 24);
++
++ /* skip rest of the header (upper half of uncompressed size) */
++ for (i = 0; i < 4; i++)
++ get_byte();
++
++ workspace_size = ((LZMA_BASE_SIZE + (LZMA_LIT_SIZE << (lc + lp))) * sizeof(CProb)) + 100;
++ printk( KERN_NOTICE "initramfs: LZMA lc=%d,lp=%d,pb=%d,origSize=%d\n",
++ lc,lp,pb,osize);
++ outputbuffer = kmalloc(osize, GFP_KERNEL);
++ if (outputbuffer == 0) {
++ printk(KERN_ERR "initramfs: Couldn't allocate lzma output buffer\n");
++ return -1;
++ }
++
++ workspace = kmalloc(workspace_size, GFP_KERNEL);
++ if (workspace == NULL) {
++ printk(KERN_ERR "initramfs: Couldn't allocate lzma workspace\n");
++ return -1;
++ }
++
++ res = LzmaDecode(workspace, workspace_size, lc, lp, pb, inbuf + inptr, insize - inptr, outputbuffer, osize, &outsizeProcessed);
++ if( res != 0 ) {
++ panic( KERN_ERR "initramfs: Lzma decode failure\n");
++ return -1;
++ }
++
++ flush_buffer(outputbuffer, outsizeProcessed);
++ inptr = insize;
++
++ kfree(outputbuffer);
++ kfree(workspace);
++ state = Reset;
++ return 0;
++}
++
+ static char * __init unpack_to_rootfs(char *buf, unsigned len, int check_only)
+ {
+ int written;
+@@ -475,12 +538,28 @@
+ inptr = 0;
+ outcnt = 0; /* bytes in output buffer */
+ bytes_out = 0;
+- crc = (ulg)0xffffffffL; /* shift register contents */
+- makecrc();
+- gunzip();
+- if (state != Reset)
++ if( inbuf[0] == 037 && ((inbuf[1] == 0213) || (inbuf[1] == 0236)))
++ {
++ printk( KERN_NOTICE "detected gzip initramfs\n");
++ crc = (ulg)0xffffffffL; /* shift register contents */
++ makecrc();
++ gunzip();
++ if (state != Reset)
+ error("junk in gzipped archive");
+- this_header = saved_offset + inptr;
++ }
++ else if(!memcmp(inbuf+1, "\x00\x00\x80\x00", 4)) /* FIXME: hardcoded dictionary size */
++ {
++ printk( KERN_NOTICE "detected lzma initramfs\n");
++ lzma_unzip();
++ }
++ else
++ {
++ // skip forward ?
++ crc = (ulg)0xffffffffL; /* shift register contents */
++ makecrc();
++ gunzip();
++ }
++ this_header = saved_offset + inptr;
+ buf += inptr;
+ len -= inptr;
+ }
--- /dev/null
+The SSB pcicore driver does create some MMIO resource collisions.
+However, the pcicore PCI-fixup routine fixes these collisions afterwards.
+Remove this sanity check for now until we find a better solution.
+--mb
+--- a/arch/mips/pci/pci.c
++++ b/arch/mips/pci/pci.c
+@@ -182,12 +182,10 @@
+ if ((idx == PCI_ROM_RESOURCE) &&
+ (!(r->flags & IORESOURCE_ROM_ENABLE)))
+ continue;
+- if (!r->start && r->end) {
+- printk(KERN_ERR "PCI: Device %s not available "
+- "because of resource collisions\n",
++ if (!r->start && r->end)
++ printk(KERN_WARNING "PCI: Device %s resource"
++ "collisions detected. Ignoring...\n",
+ pci_name(dev));
+- return -EINVAL;
+- }
+ if (r->flags & IORESOURCE_IO)
+ cmd |= PCI_COMMAND_IO;
+ if (r->flags & IORESOURCE_MEM)
--- /dev/null
+--- a/drivers/ssb/main.c
++++ b/drivers/ssb/main.c
+@@ -1173,7 +1173,9 @@
+ /* ssb must be initialized after PCI but before the ssb drivers.
+ * That means we must use some initcall between subsys_initcall
+ * and device_initcall. */
+-fs_initcall(ssb_modinit);
++//FIXME on embedded we need to be early to make sure we can register
++// a new PCI bus, if needed.
++subsys_initcall(ssb_modinit);
+
+ static void __exit ssb_modexit(void)
+ {
--- /dev/null
+Subject: [OpenWrt-Devel] [PATCH] ssb-pcicore: Fix IRQ-vector init on embedded devices
+
+On embedded devices we must not route the interrupts through
+the PCI core, if our host-bus is not PCI.
+
+Reported-by: Steve Brown <sbrown@cortland.com>
+Signed-off-by: Michael Buesch <mb@bu3sch.de>
+
+--- a/drivers/ssb/driver_pcicore.c
++++ b/drivers/ssb/driver_pcicore.c
+@@ -519,6 +519,13 @@
+ int err = 0;
+ u32 tmp;
+
++ if (dev->bus->bustype != SSB_BUSTYPE_PCI) {
++ /* This SSB device is not on a PCI host-bus. So the IRQs are
++ * not routed through the PCI core.
++ * So we must not enable routing through the PCI core. */
++ goto out;
++ }
++
+ if (!pdev)
+ goto out;
+ bus = pdev->bus;
--- /dev/null
+Add support for 8bit reads/writes to SSB.
+--- a/drivers/ssb/main.c
++++ b/drivers/ssb/main.c
+@@ -508,6 +508,14 @@
+ return err;
+ }
+
++static u8 ssb_ssb_read8(struct ssb_device *dev, u16 offset)
++{
++ struct ssb_bus *bus = dev->bus;
++
++ offset += dev->core_index * SSB_CORE_SIZE;
++ return readb(bus->mmio + offset);
++}
++
+ static u16 ssb_ssb_read16(struct ssb_device *dev, u16 offset)
+ {
+ struct ssb_bus *bus = dev->bus;
+@@ -524,6 +532,14 @@
+ return readl(bus->mmio + offset);
+ }
+
++static void ssb_ssb_write8(struct ssb_device *dev, u16 offset, u8 value)
++{
++ struct ssb_bus *bus = dev->bus;
++
++ offset += dev->core_index * SSB_CORE_SIZE;
++ writeb(value, bus->mmio + offset);
++}
++
+ static void ssb_ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
+ {
+ struct ssb_bus *bus = dev->bus;
+@@ -542,8 +558,10 @@
+
+ /* Ops for the plain SSB bus without a host-device (no PCI or PCMCIA). */
+ static const struct ssb_bus_ops ssb_ssb_ops = {
++ .read8 = ssb_ssb_read8,
+ .read16 = ssb_ssb_read16,
+ .read32 = ssb_ssb_read32,
++ .write8 = ssb_ssb_write8,
+ .write16 = ssb_ssb_write16,
+ .write32 = ssb_ssb_write32,
+ };
+--- a/drivers/ssb/pci.c
++++ b/drivers/ssb/pci.c
+@@ -577,6 +577,19 @@
+ }
+ #endif /* DEBUG */
+
++static u8 ssb_pci_read8(struct ssb_device *dev, u16 offset)
++{
++ struct ssb_bus *bus = dev->bus;
++
++ if (unlikely(ssb_pci_assert_buspower(bus)))
++ return 0xFF;
++ if (unlikely(bus->mapped_device != dev)) {
++ if (unlikely(ssb_pci_switch_core(bus, dev)))
++ return 0xFF;
++ }
++ return ioread8(bus->mmio + offset);
++}
++
+ static u16 ssb_pci_read16(struct ssb_device *dev, u16 offset)
+ {
+ struct ssb_bus *bus = dev->bus;
+@@ -603,6 +616,19 @@
+ return ioread32(bus->mmio + offset);
+ }
+
++static void ssb_pci_write8(struct ssb_device *dev, u16 offset, u8 value)
++{
++ struct ssb_bus *bus = dev->bus;
++
++ if (unlikely(ssb_pci_assert_buspower(bus)))
++ return;
++ if (unlikely(bus->mapped_device != dev)) {
++ if (unlikely(ssb_pci_switch_core(bus, dev)))
++ return;
++ }
++ iowrite8(value, bus->mmio + offset);
++}
++
+ static void ssb_pci_write16(struct ssb_device *dev, u16 offset, u16 value)
+ {
+ struct ssb_bus *bus = dev->bus;
+@@ -631,8 +657,10 @@
+
+ /* Not "static", as it's used in main.c */
+ const struct ssb_bus_ops ssb_pci_ops = {
++ .read8 = ssb_pci_read8,
+ .read16 = ssb_pci_read16,
+ .read32 = ssb_pci_read32,
++ .write8 = ssb_pci_write8,
+ .write16 = ssb_pci_write16,
+ .write32 = ssb_pci_write32,
+ };
+--- a/drivers/ssb/pcmcia.c
++++ b/drivers/ssb/pcmcia.c
+@@ -172,6 +172,22 @@
+ return 0;
+ }
+
++static u8 ssb_pcmcia_read8(struct ssb_device *dev, u16 offset)
++{
++ struct ssb_bus *bus = dev->bus;
++ unsigned long flags;
++ int err;
++ u8 value = 0xFF;
++
++ spin_lock_irqsave(&bus->bar_lock, flags);
++ err = select_core_and_segment(dev, &offset);
++ if (likely(!err))
++ value = readb(bus->mmio + offset);
++ spin_unlock_irqrestore(&bus->bar_lock, flags);
++
++ return value;
++}
++
+ static u16 ssb_pcmcia_read16(struct ssb_device *dev, u16 offset)
+ {
+ struct ssb_bus *bus = dev->bus;
+@@ -206,6 +222,20 @@
+ return (lo | (hi << 16));
+ }
+
++static void ssb_pcmcia_write8(struct ssb_device *dev, u16 offset, u8 value)
++{
++ struct ssb_bus *bus = dev->bus;
++ unsigned long flags;
++ int err;
++
++ spin_lock_irqsave(&bus->bar_lock, flags);
++ err = select_core_and_segment(dev, &offset);
++ if (likely(!err))
++ writeb(value, bus->mmio + offset);
++ mmiowb();
++ spin_unlock_irqrestore(&bus->bar_lock, flags);
++}
++
+ static void ssb_pcmcia_write16(struct ssb_device *dev, u16 offset, u16 value)
+ {
+ struct ssb_bus *bus = dev->bus;
+@@ -238,8 +268,10 @@
+
+ /* Not "static", as it's used in main.c */
+ const struct ssb_bus_ops ssb_pcmcia_ops = {
++ .read8 = ssb_pcmcia_read8,
+ .read16 = ssb_pcmcia_read16,
+ .read32 = ssb_pcmcia_read32,
++ .write8 = ssb_pcmcia_write8,
+ .write16 = ssb_pcmcia_write16,
+ .write32 = ssb_pcmcia_write32,
+ };
+--- a/include/linux/ssb/ssb.h
++++ b/include/linux/ssb/ssb.h
+@@ -72,8 +72,10 @@
+ /* Lowlevel read/write operations on the device MMIO.
+ * Internal, don't use that outside of ssb. */
+ struct ssb_bus_ops {
++ u8 (*read8)(struct ssb_device *dev, u16 offset);
+ u16 (*read16)(struct ssb_device *dev, u16 offset);
+ u32 (*read32)(struct ssb_device *dev, u16 offset);
++ void (*write8)(struct ssb_device *dev, u16 offset, u8 value);
+ void (*write16)(struct ssb_device *dev, u16 offset, u16 value);
+ void (*write32)(struct ssb_device *dev, u16 offset, u32 value);
+ };
+@@ -348,6 +350,10 @@
+
+
+ /* Device MMIO register read/write functions. */
++static inline u8 ssb_read8(struct ssb_device *dev, u16 offset)
++{
++ return dev->ops->read8(dev, offset);
++}
+ static inline u16 ssb_read16(struct ssb_device *dev, u16 offset)
+ {
+ return dev->ops->read16(dev, offset);
+@@ -356,6 +362,10 @@
+ {
+ return dev->ops->read32(dev, offset);
+ }
++static inline void ssb_write8(struct ssb_device *dev, u16 offset, u8 value)
++{
++ dev->ops->write8(dev, offset, value);
++}
+ static inline void ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
+ {
+ dev->ops->write16(dev, offset, value);
--- /dev/null
+Allow registering PCI devices after early boot.
+
+This is an ugly hack and needs to be rewritten before going upstream.
+--- a/arch/mips/pci/pci.c
++++ b/arch/mips/pci/pci.c
+@@ -21,6 +21,17 @@
+ */
+ int pci_probe_only;
+
++/*
++ * Indicate whether PCI-bios init was already done.
++ */
++static int pcibios_init_done;
++
++/*
++ * The currently used busnumber.
++ */
++static int next_busno;
++static int need_domain_info;
++
+ #define PCI_ASSIGN_ALL_BUSSES 1
+
+ unsigned int pci_probe = PCI_ASSIGN_ALL_BUSSES;
+@@ -75,8 +86,32 @@
+ res->start = start;
+ }
+
+-void __devinit register_pci_controller(struct pci_controller *hose)
++/* Most MIPS systems have straight-forward swizzling needs. */
++
++static inline u8 bridge_swizzle(u8 pin, u8 slot)
++{
++ return (((pin - 1) + slot) % 4) + 1;
++}
++
++static u8 common_swizzle(struct pci_dev *dev, u8 *pinp)
+ {
++ u8 pin = *pinp;
++
++ while (dev->bus->parent) {
++ pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
++ /* Move up the chain of bridges. */
++ dev = dev->bus->self;
++ }
++ *pinp = pin;
++
++ /* The slot is the slot of the last bridge. */
++ return PCI_SLOT(dev->devfn);
++}
++
++void register_pci_controller(struct pci_controller *hose)
++{
++ struct pci_bus *bus;
++
+ if (request_resource(&iomem_resource, hose->mem_resource) < 0)
+ goto out;
+ if (request_resource(&ioport_resource, hose->io_resource) < 0) {
+@@ -84,9 +119,6 @@
+ goto out;
+ }
+
+- *hose_tail = hose;
+- hose_tail = &hose->next;
+-
+ /*
+ * Do not panic here but later - this might hapen before console init.
+ */
+@@ -94,41 +126,47 @@
+ printk(KERN_WARNING
+ "registering PCI controller with io_map_base unset\n");
+ }
+- return;
+
+-out:
+- printk(KERN_WARNING
+- "Skipping PCI bus scan due to resource conflict\n");
+-}
++ if (pcibios_init_done) {
++ //TODO
+
+-/* Most MIPS systems have straight-forward swizzling needs. */
++ printk(KERN_INFO "Registering a PCI bus after boot\n");
+
+-static inline u8 bridge_swizzle(u8 pin, u8 slot)
+-{
+- return (((pin - 1) + slot) % 4) + 1;
+-}
++ if (!hose->iommu)
++ PCI_DMA_BUS_IS_PHYS = 1;
+
+-static u8 __init common_swizzle(struct pci_dev *dev, u8 *pinp)
+-{
+- u8 pin = *pinp;
++ bus = pci_scan_bus(next_busno, hose->pci_ops, hose);
++ hose->bus = bus;
++ need_domain_info = need_domain_info || hose->index;
++ hose->need_domain_info = need_domain_info;
++ if (bus) {
++ next_busno = bus->subordinate + 1;
++ /* Don't allow 8-bit bus number overflow inside the hose -
++ reserve some space for bridges. */
++ if (next_busno > 224) {
++ next_busno = 0;
++ need_domain_info = 1;
++ }
++ }
++ if (!pci_probe_only)
++ pci_assign_unassigned_resources();
++ pci_fixup_irqs(common_swizzle, pcibios_map_irq);
++ } else {
++ *hose_tail = hose;
++ hose_tail = &hose->next;
++ }
+
+- while (dev->bus->parent) {
+- pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
+- /* Move up the chain of bridges. */
+- dev = dev->bus->self;
+- }
+- *pinp = pin;
++ return;
+
+- /* The slot is the slot of the last bridge. */
+- return PCI_SLOT(dev->devfn);
++out:
++ printk(KERN_WARNING
++ "Skipping PCI bus scan due to resource conflict\n");
+ }
+
+ static int __init pcibios_init(void)
+ {
+ struct pci_controller *hose;
+ struct pci_bus *bus;
+- int next_busno;
+- int need_domain_info = 0;
+
+ /* Scan all of the recorded PCI controllers. */
+ for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
+@@ -157,6 +195,7 @@
+ if (!pci_probe_only)
+ pci_assign_unassigned_resources();
+ pci_fixup_irqs(common_swizzle, pcibios_map_irq);
++ pcibios_init_done = 1;
+
+ return 0;
+ }
+--- a/drivers/ssb/main.c
++++ b/drivers/ssb/main.c
+@@ -1191,9 +1191,7 @@
+ /* ssb must be initialized after PCI but before the ssb drivers.
+ * That means we must use some initcall between subsys_initcall
+ * and device_initcall. */
+-//FIXME on embedded we need to be early to make sure we can register
+-// a new PCI bus, if needed.
+-subsys_initcall(ssb_modinit);
++fs_initcall(ssb_modinit);
+
+ static void __exit ssb_modexit(void)
+ {
--- /dev/null
+--- a/drivers/ssb/Kconfig
++++ b/drivers/ssb/Kconfig
+@@ -125,4 +125,13 @@
+
+ If unsure, say N
+
++config SSB_DRIVER_GIGE
++ bool "SSB Broadcom Gigabit Ethernet driver"
++ depends on SSB_PCIHOST_POSSIBLE && SSB_EMBEDDED && MIPS
++ help
++ Driver for the Sonics Silicon Backplane attached
++ Broadcom Gigabit Ethernet.
++
++ If unsure, say N
++
+ endmenu
+--- a/drivers/ssb/Makefile
++++ b/drivers/ssb/Makefile
+@@ -11,6 +11,7 @@
+ ssb-$(CONFIG_SSB_DRIVER_MIPS) += driver_mipscore.o
+ ssb-$(CONFIG_SSB_DRIVER_EXTIF) += driver_extif.o
+ ssb-$(CONFIG_SSB_DRIVER_PCICORE) += driver_pcicore.o
++ssb-$(CONFIG_SSB_DRIVER_GIGE) += driver_gige.o
+
+ # b43 pci-ssb-bridge driver
+ # Not strictly a part of SSB, but kept here for convenience
+--- /dev/null
++++ b/drivers/ssb/driver_gige.c
+@@ -0,0 +1,294 @@
++/*
++ * Sonics Silicon Backplane
++ * Broadcom Gigabit Ethernet core driver
++ *
++ * Copyright 2008, Broadcom Corporation
++ * Copyright 2008, Michael Buesch <mb@bu3sch.de>
++ *
++ * Licensed under the GNU/GPL. See COPYING for details.
++ */
++
++#include <linux/ssb/ssb.h>
++#include <linux/ssb/ssb_driver_gige.h>
++#include <linux/pci.h>
++#include <linux/pci_regs.h>
++
++
++/*
++MODULE_DESCRIPTION("SSB Broadcom Gigabit Ethernet driver");
++MODULE_AUTHOR("Michael Buesch");
++MODULE_LICENSE("GPL");
++*/
++
++static const struct ssb_device_id ssb_gige_tbl[] = {
++ SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET_GBIT, SSB_ANY_REV),
++ SSB_DEVTABLE_END
++};
++/* MODULE_DEVICE_TABLE(ssb, ssb_gige_tbl); */
++
++
++static inline u8 gige_read8(struct ssb_gige *dev, u16 offset)
++{
++ return ssb_read8(dev->dev, offset);
++}
++
++static inline u16 gige_read16(struct ssb_gige *dev, u16 offset)
++{
++ return ssb_read16(dev->dev, offset);
++}
++
++static inline u32 gige_read32(struct ssb_gige *dev, u16 offset)
++{
++ return ssb_read32(dev->dev, offset);
++}
++
++static inline void gige_write8(struct ssb_gige *dev,
++ u16 offset, u8 value)
++{
++ ssb_write8(dev->dev, offset, value);
++}
++
++static inline void gige_write16(struct ssb_gige *dev,
++ u16 offset, u16 value)
++{
++ ssb_write16(dev->dev, offset, value);
++}
++
++static inline void gige_write32(struct ssb_gige *dev,
++ u16 offset, u32 value)
++{
++ ssb_write32(dev->dev, offset, value);
++}
++
++static inline
++u8 gige_pcicfg_read8(struct ssb_gige *dev, unsigned int offset)
++{
++ BUG_ON(offset >= 256);
++ return gige_read8(dev, SSB_GIGE_PCICFG + offset);
++}
++
++static inline
++u16 gige_pcicfg_read16(struct ssb_gige *dev, unsigned int offset)
++{
++ BUG_ON(offset >= 256);
++ return gige_read16(dev, SSB_GIGE_PCICFG + offset);
++}
++
++static inline
++u32 gige_pcicfg_read32(struct ssb_gige *dev, unsigned int offset)
++{
++ BUG_ON(offset >= 256);
++ return gige_read32(dev, SSB_GIGE_PCICFG + offset);
++}
++
++static inline
++void gige_pcicfg_write8(struct ssb_gige *dev,
++ unsigned int offset, u8 value)
++{
++ BUG_ON(offset >= 256);
++ gige_write8(dev, SSB_GIGE_PCICFG + offset, value);
++}
++
++static inline
++void gige_pcicfg_write16(struct ssb_gige *dev,
++ unsigned int offset, u16 value)
++{
++ BUG_ON(offset >= 256);
++ gige_write16(dev, SSB_GIGE_PCICFG + offset, value);
++}
++
++static inline
++void gige_pcicfg_write32(struct ssb_gige *dev,
++ unsigned int offset, u32 value)
++{
++ BUG_ON(offset >= 256);
++ gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
++}
++
++static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
++ int reg, int size, u32 *val)
++{
++ struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
++ unsigned long flags;
++
++ if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0))
++ return PCIBIOS_DEVICE_NOT_FOUND;
++ if (reg >= 256)
++ return PCIBIOS_DEVICE_NOT_FOUND;
++
++ spin_lock_irqsave(&dev->lock, flags);
++ switch (size) {
++ case 1:
++ *val = gige_pcicfg_read8(dev, reg);
++ break;
++ case 2:
++ *val = gige_pcicfg_read16(dev, reg);
++ break;
++ case 4:
++ *val = gige_pcicfg_read32(dev, reg);
++ break;
++ default:
++ WARN_ON(1);
++ }
++ spin_unlock_irqrestore(&dev->lock, flags);
++
++ return PCIBIOS_SUCCESSFUL;
++}
++
++static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
++ int reg, int size, u32 val)
++{
++ struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
++ unsigned long flags;
++
++ if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0))
++ return PCIBIOS_DEVICE_NOT_FOUND;
++ if (reg >= 256)
++ return PCIBIOS_DEVICE_NOT_FOUND;
++
++ spin_lock_irqsave(&dev->lock, flags);
++ switch (size) {
++ case 1:
++ gige_pcicfg_write8(dev, reg, val);
++ break;
++ case 2:
++ gige_pcicfg_write16(dev, reg, val);
++ break;
++ case 4:
++ gige_pcicfg_write32(dev, reg, val);
++ break;
++ default:
++ WARN_ON(1);
++ }
++ spin_unlock_irqrestore(&dev->lock, flags);
++
++ return PCIBIOS_SUCCESSFUL;
++}
++
++static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
++{
++ struct ssb_gige *dev;
++ u32 base, tmslow, tmshigh;
++
++ dev = kzalloc(sizeof(*dev), GFP_KERNEL);
++ if (!dev)
++ return -ENOMEM;
++ dev->dev = sdev;
++
++ spin_lock_init(&dev->lock);
++ dev->pci_controller.pci_ops = &dev->pci_ops;
++ dev->pci_controller.io_resource = &dev->io_resource;
++ dev->pci_controller.mem_resource = &dev->mem_resource;
++ dev->pci_controller.io_map_base = 0x800;
++ dev->pci_ops.read = ssb_gige_pci_read_config;
++ dev->pci_ops.write = ssb_gige_pci_write_config;
++
++ dev->io_resource.name = SSB_GIGE_IO_RES_NAME;
++ dev->io_resource.start = 0x800;
++ dev->io_resource.end = 0x8FF;
++ dev->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
++
++ if (!ssb_device_is_enabled(sdev))
++ ssb_device_enable(sdev, 0);
++
++ /* Setup BAR0. This is a 64k MMIO region. */
++ base = ssb_admatch_base(ssb_read32(sdev, SSB_ADMATCH1));
++ gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_0, base);
++ gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_1, 0);
++
++ dev->mem_resource.name = SSB_GIGE_MEM_RES_NAME;
++ dev->mem_resource.start = base;
++ dev->mem_resource.end = base + 0x10000 - 1;
++ dev->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
++
++ /* Enable the memory region. */
++ gige_pcicfg_write16(dev, PCI_COMMAND,
++ gige_pcicfg_read16(dev, PCI_COMMAND)
++ | PCI_COMMAND_MEMORY);
++
++ /* Write flushing is controlled by the Flush Status Control register.
++ * We want to flush every register write with a timeout and we want
++ * to disable the IRQ mask while flushing to avoid concurrency.
++ * Note that automatic write flushing does _not_ work from
++ * an IRQ handler. The driver must flush manually by reading a register.
++ */
++ gige_write32(dev, SSB_GIGE_SHIM_FLUSHSTAT, 0x00000068);
++
++ /* Check if we have an RGMII or GMII PHY-bus.
++ * On RGMII do not bypass the DLLs */
++ tmslow = ssb_read32(sdev, SSB_TMSLOW);
++ tmshigh = ssb_read32(sdev, SSB_TMSHIGH);
++ if (tmshigh & SSB_GIGE_TMSHIGH_RGMII) {
++ tmslow &= ~SSB_GIGE_TMSLOW_TXBYPASS;
++ tmslow &= ~SSB_GIGE_TMSLOW_RXBYPASS;
++ dev->has_rgmii = 1;
++ } else {
++ tmslow |= SSB_GIGE_TMSLOW_TXBYPASS;
++ tmslow |= SSB_GIGE_TMSLOW_RXBYPASS;
++ dev->has_rgmii = 0;
++ }
++ tmslow |= SSB_GIGE_TMSLOW_DLLEN;
++ ssb_write32(sdev, SSB_TMSLOW, tmslow);
++
++ ssb_set_drvdata(sdev, dev);
++ register_pci_controller(&dev->pci_controller);
++
++ return 0;
++}
++
++bool pdev_is_ssb_gige_core(struct pci_dev *pdev)
++{
++ if (!pdev->resource[0].name)
++ return 0;
++ return (strcmp(pdev->resource[0].name, SSB_GIGE_MEM_RES_NAME) == 0);
++}
++EXPORT_SYMBOL(pdev_is_ssb_gige_core);
++
++int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
++ struct pci_dev *pdev)
++{
++ struct ssb_gige *dev = ssb_get_drvdata(sdev);
++ struct resource *res;
++
++ if (pdev->bus->ops != &dev->pci_ops) {
++ /* The PCI device is not on this SSB GigE bridge device. */
++ return -ENODEV;
++ }
++
++ /* Fixup the PCI resources. */
++ res = &(pdev->resource[0]);
++ res->flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
++ res->name = dev->mem_resource.name;
++ res->start = dev->mem_resource.start;
++ res->end = dev->mem_resource.end;
++
++ /* Fixup interrupt lines. */
++ pdev->irq = ssb_mips_irq(sdev) + 2;
++ pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, pdev->irq);
++
++ return 0;
++}
++
++int ssb_gige_map_irq(struct ssb_device *sdev,
++ const struct pci_dev *pdev)
++{
++ struct ssb_gige *dev = ssb_get_drvdata(sdev);
++
++ if (pdev->bus->ops != &dev->pci_ops) {
++ /* The PCI device is not on this SSB GigE bridge device. */
++ return -ENODEV;
++ }
++
++ return ssb_mips_irq(sdev) + 2;
++}
++
++static struct ssb_driver ssb_gige_driver = {
++ .name = "BCM-GigE",
++ .id_table = ssb_gige_tbl,
++ .probe = ssb_gige_probe,
++};
++
++int ssb_gige_init(void)
++{
++ return ssb_driver_register(&ssb_gige_driver);
++}
+--- /dev/null
++++ b/include/linux/ssb/ssb_driver_gige.h
+@@ -0,0 +1,174 @@
++#ifndef LINUX_SSB_DRIVER_GIGE_H_
++#define LINUX_SSB_DRIVER_GIGE_H_
++
++#include <linux/ssb/ssb.h>
++#include <linux/pci.h>
++#include <linux/spinlock.h>
++
++
++#ifdef CONFIG_SSB_DRIVER_GIGE
++
++
++#define SSB_GIGE_PCIIO 0x0000 /* PCI I/O Registers (1024 bytes) */
++#define SSB_GIGE_RESERVED 0x0400 /* Reserved (1024 bytes) */
++#define SSB_GIGE_PCICFG 0x0800 /* PCI config space (256 bytes) */
++#define SSB_GIGE_SHIM_FLUSHSTAT 0x0C00 /* PCI to OCP: Flush status control (32bit) */
++#define SSB_GIGE_SHIM_FLUSHRDA 0x0C04 /* PCI to OCP: Flush read address (32bit) */
++#define SSB_GIGE_SHIM_FLUSHTO 0x0C08 /* PCI to OCP: Flush timeout counter (32bit) */
++#define SSB_GIGE_SHIM_BARRIER 0x0C0C /* PCI to OCP: Barrier register (32bit) */
++#define SSB_GIGE_SHIM_MAOCPSI 0x0C10 /* PCI to OCP: MaocpSI Control (32bit) */
++#define SSB_GIGE_SHIM_SIOCPMA 0x0C14 /* PCI to OCP: SiocpMa Control (32bit) */
++
++/* TM Status High flags */
++#define SSB_GIGE_TMSHIGH_RGMII 0x00010000 /* Have an RGMII PHY-bus */
++/* TM Status Low flags */
++#define SSB_GIGE_TMSLOW_TXBYPASS 0x00080000 /* TX bypass (no delay) */
++#define SSB_GIGE_TMSLOW_RXBYPASS 0x00100000 /* RX bypass (no delay) */
++#define SSB_GIGE_TMSLOW_DLLEN 0x01000000 /* Enable DLL controls */
++
++/* Boardflags (low) */
++#define SSB_GIGE_BFL_ROBOSWITCH 0x0010
++
++
++#define SSB_GIGE_MEM_RES_NAME "SSB Broadcom 47xx GigE memory"
++#define SSB_GIGE_IO_RES_NAME "SSB Broadcom 47xx GigE I/O"
++
++struct ssb_gige {
++ struct ssb_device *dev;
++
++ spinlock_t lock;
++
++ /* True, if the device has an RGMII bus.
++ * False, if the device has a GMII bus. */
++ bool has_rgmii;
++
++ /* The PCI controller device. */
++ struct pci_controller pci_controller;
++ struct pci_ops pci_ops;
++ struct resource mem_resource;
++ struct resource io_resource;
++};
++
++/* Check whether a PCI device is a SSB Gigabit Ethernet core. */
++extern bool pdev_is_ssb_gige_core(struct pci_dev *pdev);
++
++/* Convert a pci_dev pointer to a ssb_gige pointer. */
++static inline struct ssb_gige * pdev_to_ssb_gige(struct pci_dev *pdev)
++{
++ if (!pdev_is_ssb_gige_core(pdev))
++ return NULL;
++ return container_of(pdev->bus->ops, struct ssb_gige, pci_ops);
++}
++
++/* Returns whether the PHY is connected by an RGMII bus. */
++static inline bool ssb_gige_is_rgmii(struct pci_dev *pdev)
++{
++ struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
++ return (dev ? dev->has_rgmii : 0);
++}
++
++/* Returns whether we have a Roboswitch. */
++static inline bool ssb_gige_have_roboswitch(struct pci_dev *pdev)
++{
++ struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
++ if (dev)
++ return !!(dev->dev->bus->sprom.boardflags_lo &
++ SSB_GIGE_BFL_ROBOSWITCH);
++ return 0;
++}
++
++/* Returns whether we can only do one DMA at once. */
++static inline bool ssb_gige_one_dma_at_once(struct pci_dev *pdev)
++{
++ struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
++ if (dev)
++ return ((dev->dev->bus->chip_id == 0x4785) &&
++ (dev->dev->bus->chip_rev < 2));
++ return 0;
++}
++
++/* Returns whether we must flush posted writes. */
++static inline bool ssb_gige_must_flush_posted_writes(struct pci_dev *pdev)
++{
++ struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
++ if (dev)
++ return (dev->dev->bus->chip_id == 0x4785);
++ return 0;
++}
++
++extern char * nvram_get(const char *name);
++/* Get the device MAC address */
++static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
++{
++#ifdef CONFIG_BCM947XX
++ char *res = nvram_get("et0macaddr");
++ if (res)
++ memcpy(macaddr, res, 6);
++#endif
++}
++
++extern int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
++ struct pci_dev *pdev);
++extern int ssb_gige_map_irq(struct ssb_device *sdev,
++ const struct pci_dev *pdev);
++
++/* The GigE driver is not a standalone module, because we don't have support
++ * for unregistering the driver. So we could not unload the module anyway. */
++extern int ssb_gige_init(void);
++static inline void ssb_gige_exit(void)
++{
++ /* Currently we can not unregister the GigE driver,
++ * because we can not unregister the PCI bridge. */
++ BUG();
++}
++
++
++#else /* CONFIG_SSB_DRIVER_GIGE */
++/* Gigabit Ethernet driver disabled */
++
++
++static inline int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
++ struct pci_dev *pdev)
++{
++ return -ENOSYS;
++}
++static inline int ssb_gige_map_irq(struct ssb_device *sdev,
++ const struct pci_dev *pdev)
++{
++ return -ENOSYS;
++}
++static inline int ssb_gige_init(void)
++{
++ return 0;
++}
++static inline void ssb_gige_exit(void)
++{
++}
++
++static inline bool pdev_is_ssb_gige_core(struct pci_dev *pdev)
++{
++ return 0;
++}
++static inline struct ssb_gige * pdev_to_ssb_gige(struct pci_dev *pdev)
++{
++ return NULL;
++}
++static inline bool ssb_gige_is_rgmii(struct pci_dev *pdev)
++{
++ return 0;
++}
++static inline bool ssb_gige_have_roboswitch(struct pci_dev *pdev)
++{
++ return 0;
++}
++static inline bool ssb_gige_one_dma_at_once(struct pci_dev *pdev)
++{
++ return 0;
++}
++static inline bool ssb_gige_must_flush_posted_writes(struct pci_dev *pdev)
++{
++ return 0;
++}
++
++#endif /* CONFIG_SSB_DRIVER_GIGE */
++#endif /* LINUX_SSB_DRIVER_GIGE_H_ */
+--- a/drivers/ssb/driver_pcicore.c
++++ b/drivers/ssb/driver_pcicore.c
+@@ -60,78 +60,6 @@
+ /* Core to access the external PCI config space. Can only have one. */
+ static struct ssb_pcicore *extpci_core;
+
+-static u32 ssb_pcicore_pcibus_iobase = 0x100;
+-static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
+-
+-int pcibios_plat_dev_init(struct pci_dev *d)
+-{
+- struct resource *res;
+- int pos, size;
+- u32 *base;
+-
+- ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
+- pci_name(d));
+-
+- /* Fix up resource bases */
+- for (pos = 0; pos < 6; pos++) {
+- res = &d->resource[pos];
+- if (res->flags & IORESOURCE_IO)
+- base = &ssb_pcicore_pcibus_iobase;
+- else
+- base = &ssb_pcicore_pcibus_membase;
+- res->flags |= IORESOURCE_PCI_FIXED;
+- if (res->end) {
+- size = res->end - res->start + 1;
+- if (*base & (size - 1))
+- *base = (*base + size) & ~(size - 1);
+- res->start = *base;
+- res->end = res->start + size - 1;
+- *base += size;
+- pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
+- }
+- /* Fix up PCI bridge BAR0 only */
+- if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
+- break;
+- }
+- /* Fix up interrupt lines */
+- d->irq = ssb_mips_irq(extpci_core->dev) + 2;
+- pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
+-
+- return 0;
+-}
+-
+-static void __init ssb_fixup_pcibridge(struct pci_dev *dev)
+-{
+- u8 lat;
+-
+- if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
+- return;
+-
+- ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
+-
+- /* Enable PCI bridge bus mastering and memory space */
+- pci_set_master(dev);
+- if (pcibios_enable_device(dev, ~0) < 0) {
+- ssb_printk(KERN_ERR "PCI: SSB bridge enable failed\n");
+- return;
+- }
+-
+- /* Enable PCI bridge BAR1 prefetch and burst */
+- pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
+-
+- /* Make sure our latency is high enough to handle the devices behind us */
+- lat = 168;
+- ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
+- pci_name(dev), lat);
+- pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
+-}
+-DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_fixup_pcibridge);
+-
+-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+-{
+- return ssb_mips_irq(extpci_core->dev) + 2;
+-}
+-
+ static u32 get_cfgspace_addr(struct ssb_pcicore *pc,
+ unsigned int bus, unsigned int dev,
+ unsigned int func, unsigned int off)
+@@ -320,6 +248,95 @@
+ .mem_offset = 0x24000000,
+ };
+
++static u32 ssb_pcicore_pcibus_iobase = 0x100;
++static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
++
++/* This function is called when doing a pci_enable_device().
++ * We must first check if the device is a device on the PCI-core bridge. */
++int ssb_pcicore_plat_dev_init(struct pci_dev *d)
++{
++ struct resource *res;
++ int pos, size;
++ u32 *base;
++
++ if (d->bus->ops != &ssb_pcicore_pciops) {
++ /* This is not a device on the PCI-core bridge. */
++ return -ENODEV;
++ }
++
++ ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
++ pci_name(d));
++
++ /* Fix up resource bases */
++ for (pos = 0; pos < 6; pos++) {
++ res = &d->resource[pos];
++ if (res->flags & IORESOURCE_IO)
++ base = &ssb_pcicore_pcibus_iobase;
++ else
++ base = &ssb_pcicore_pcibus_membase;
++ res->flags |= IORESOURCE_PCI_FIXED;
++ if (res->end) {
++ size = res->end - res->start + 1;
++ if (*base & (size - 1))
++ *base = (*base + size) & ~(size - 1);
++ res->start = *base;
++ res->end = res->start + size - 1;
++ *base += size;
++ pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
++ }
++ /* Fix up PCI bridge BAR0 only */
++ if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
++ break;
++ }
++ /* Fix up interrupt lines */
++ d->irq = ssb_mips_irq(extpci_core->dev) + 2;
++ pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
++
++ return 0;
++}
++
++/* Early PCI fixup for a device on the PCI-core bridge. */
++static void ssb_pcicore_fixup_pcibridge(struct pci_dev *dev)
++{
++ u8 lat;
++
++ if (dev->bus->ops != &ssb_pcicore_pciops) {
++ /* This is not a device on the PCI-core bridge. */
++ return;
++ }
++ if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
++ return;
++
++ ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
++
++ /* Enable PCI bridge bus mastering and memory space */
++ pci_set_master(dev);
++ if (pcibios_enable_device(dev, ~0) < 0) {
++ ssb_printk(KERN_ERR "PCI: SSB bridge enable failed\n");
++ return;
++ }
++
++ /* Enable PCI bridge BAR1 prefetch and burst */
++ pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
++
++ /* Make sure our latency is high enough to handle the devices behind us */
++ lat = 168;
++ ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
++ pci_name(dev), lat);
++ pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
++}
++DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_pcicore_fixup_pcibridge);
++
++/* PCI device IRQ mapping. */
++int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
++{
++ if (dev->bus->ops != &ssb_pcicore_pciops) {
++ /* This is not a device on the PCI-core bridge. */
++ return -ENODEV;
++ }
++ return ssb_mips_irq(extpci_core->dev) + 2;
++}
++
+ static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
+ {
+ u32 val;
+--- a/drivers/ssb/embedded.c
++++ b/drivers/ssb/embedded.c
+@@ -10,6 +10,9 @@
+
+ #include <linux/ssb/ssb.h>
+ #include <linux/ssb/ssb_embedded.h>
++#include <linux/ssb/ssb_driver_pci.h>
++#include <linux/ssb/ssb_driver_gige.h>
++#include <linux/pci.h>
+
+ #include "ssb_private.h"
+
+@@ -130,3 +133,90 @@
+ return res;
+ }
+ EXPORT_SYMBOL(ssb_gpio_polarity);
++
++#ifdef CONFIG_SSB_DRIVER_GIGE
++static int gige_pci_init_callback(struct ssb_bus *bus, unsigned long data)
++{
++ struct pci_dev *pdev = (struct pci_dev *)data;
++ struct ssb_device *dev;
++ unsigned int i;
++ int res;
++
++ for (i = 0; i < bus->nr_devices; i++) {
++ dev = &(bus->devices[i]);
++ if (dev->id.coreid != SSB_DEV_ETHERNET_GBIT)
++ continue;
++ if (!dev->dev ||
++ !dev->dev->driver ||
++ !device_is_registered(dev->dev))
++ continue;
++ res = ssb_gige_pcibios_plat_dev_init(dev, pdev);
++ if (res >= 0)
++ return res;
++ }
++
++ return -ENODEV;
++}
++#endif /* CONFIG_SSB_DRIVER_GIGE */
++
++int ssb_pcibios_plat_dev_init(struct pci_dev *dev)
++{
++ int err;
++
++ err = ssb_pcicore_plat_dev_init(dev);
++ if (!err)
++ return 0;
++#ifdef CONFIG_SSB_DRIVER_GIGE
++ err = ssb_for_each_bus_call((unsigned long)dev, gige_pci_init_callback);
++ if (err >= 0)
++ return err;
++#endif
++ /* This is not a PCI device on any SSB device. */
++
++ return -ENODEV;
++}
++
++#ifdef CONFIG_SSB_DRIVER_GIGE
++static int gige_map_irq_callback(struct ssb_bus *bus, unsigned long data)
++{
++ const struct pci_dev *pdev = (const struct pci_dev *)data;
++ struct ssb_device *dev;
++ unsigned int i;
++ int res;
++
++ for (i = 0; i < bus->nr_devices; i++) {
++ dev = &(bus->devices[i]);
++ if (dev->id.coreid != SSB_DEV_ETHERNET_GBIT)
++ continue;
++ if (!dev->dev ||
++ !dev->dev->driver ||
++ !device_is_registered(dev->dev))
++ continue;
++ res = ssb_gige_map_irq(dev, pdev);
++ if (res >= 0)
++ return res;
++ }
++
++ return -ENODEV;
++}
++#endif /* CONFIG_SSB_DRIVER_GIGE */
++
++int ssb_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
++{
++ int res;
++
++ /* Check if this PCI device is a device on a SSB bus or device
++ * and return the IRQ number for it. */
++
++ res = ssb_pcicore_pcibios_map_irq(dev, slot, pin);
++ if (res >= 0)
++ return res;
++#ifdef CONFIG_SSB_DRIVER_GIGE
++ res = ssb_for_each_bus_call((unsigned long)dev, gige_map_irq_callback);
++ if (res >= 0)
++ return res;
++#endif
++ /* This is not a PCI device on any SSB device. */
++
++ return -ENODEV;
++}
+--- a/include/linux/ssb/ssb.h
++++ b/include/linux/ssb/ssb.h
+@@ -426,5 +426,12 @@
+ extern u32 ssb_admatch_base(u32 adm);
+ extern u32 ssb_admatch_size(u32 adm);
+
++/* PCI device mapping and fixup routines.
++ * Called from the architecture pcibios init code.
++ * These are only available on SSB_EMBEDDED configurations. */
++#ifdef CONFIG_SSB_EMBEDDED
++int ssb_pcibios_plat_dev_init(struct pci_dev *dev);
++int ssb_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
++#endif /* CONFIG_SSB_EMBEDDED */
+
+ #endif /* LINUX_SSB_H_ */
+--- a/include/linux/ssb/ssb_driver_pci.h
++++ b/include/linux/ssb/ssb_driver_pci.h
+@@ -1,6 +1,11 @@
+ #ifndef LINUX_SSB_PCICORE_H_
+ #define LINUX_SSB_PCICORE_H_
+
++#include <linux/types.h>
++
++struct pci_dev;
++
++
+ #ifdef CONFIG_SSB_DRIVER_PCICORE
+
+ /* PCI core registers. */
+@@ -88,6 +93,9 @@
+ extern int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
+ struct ssb_device *dev);
+
++int ssb_pcicore_plat_dev_init(struct pci_dev *d);
++int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
++
+
+ #else /* CONFIG_SSB_DRIVER_PCICORE */
+
+@@ -107,5 +115,16 @@
+ return 0;
+ }
+
++static inline
++int ssb_pcicore_plat_dev_init(struct pci_dev *d)
++{
++ return -ENODEV;
++}
++static inline
++int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
++{
++ return -ENODEV;
++}
++
+ #endif /* CONFIG_SSB_DRIVER_PCICORE */
+ #endif /* LINUX_SSB_PCICORE_H_ */
+--- a/drivers/ssb/main.c
++++ b/drivers/ssb/main.c
+@@ -14,6 +14,7 @@
+ #include <linux/io.h>
+ #include <linux/ssb/ssb.h>
+ #include <linux/ssb/ssb_regs.h>
++#include <linux/ssb/ssb_driver_gige.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/pci.h>
+
+@@ -68,6 +69,25 @@
+ }
+ #endif /* CONFIG_SSB_PCIHOST */
+
++int ssb_for_each_bus_call(unsigned long data,
++ int (*func)(struct ssb_bus *bus, unsigned long data))
++{
++ struct ssb_bus *bus;
++ int res;
++
++ ssb_buses_lock();
++ list_for_each_entry(bus, &buses, list) {
++ res = func(bus, data);
++ if (res >= 0) {
++ ssb_buses_unlock();
++ return res;
++ }
++ }
++ ssb_buses_unlock();
++
++ return -ENODEV;
++}
++
+ static struct ssb_device *ssb_device_get(struct ssb_device *dev)
+ {
+ if (dev)
+@@ -1181,7 +1201,14 @@
+ err = b43_pci_ssb_bridge_init();
+ if (err) {
+ ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge "
+- "initialization failed");
++ "initialization failed\n");
++ /* don't fail SSB init because of this */
++ err = 0;
++ }
++ err = ssb_gige_init();
++ if (err) {
++ ssb_printk(KERN_ERR "SSB Broadcom Gigabit Ethernet "
++ "driver initialization failed\n");
+ /* don't fail SSB init because of this */
+ err = 0;
+ }
+@@ -1195,6 +1222,7 @@
+
+ static void __exit ssb_modexit(void)
+ {
++ ssb_gige_exit();
+ b43_pci_ssb_bridge_exit();
+ bus_unregister(&ssb_bustype);
+ }
+--- a/drivers/ssb/ssb_private.h
++++ b/drivers/ssb/ssb_private.h
+@@ -118,6 +118,8 @@
+ extern int ssb_devices_freeze(struct ssb_bus *bus);
+ extern int ssb_devices_thaw(struct ssb_bus *bus);
+ extern struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev);
++int ssb_for_each_bus_call(unsigned long data,
++ int (*func)(struct ssb_bus *bus, unsigned long data));
+
+ /* b43_pci_bridge.c */
+ #ifdef CONFIG_SSB_B43_PCI_BRIDGE
+--- a/drivers/net/tg3.c
++++ b/drivers/net/tg3.c
+@@ -38,6 +38,7 @@
+ #include <linux/workqueue.h>
+ #include <linux/prefetch.h>
+ #include <linux/dma-mapping.h>
++#include <linux/ssb/ssb_driver_gige.h>
+
+ #include <net/checksum.h>
+ #include <net/ip.h>
+@@ -425,8 +426,9 @@
+ static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
+ {
+ tp->write32_mbox(tp, off, val);
+- if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
+- !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
++ if ((tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) ||
++ (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
++ !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND)))
+ tp->read32_mbox(tp, off);
+ }
+
+@@ -706,7 +708,7 @@
+
+ #define PHY_BUSY_LOOPS 5000
+
+-static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
++static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 *val)
+ {
+ u32 frame_val;
+ unsigned int loops;
+@@ -720,7 +722,7 @@
+
+ *val = 0x0;
+
+- frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
++ frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
+ MI_COM_PHY_ADDR_MASK);
+ frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
+ MI_COM_REG_ADDR_MASK);
+@@ -755,7 +757,12 @@
+ return ret;
+ }
+
+-static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
++static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
++{
++ return __tg3_readphy(tp, PHY_ADDR, reg, val);
++}
++
++static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 val)
+ {
+ u32 frame_val;
+ unsigned int loops;
+@@ -771,7 +778,7 @@
+ udelay(80);
+ }
+
+- frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
++ frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
+ MI_COM_PHY_ADDR_MASK);
+ frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
+ MI_COM_REG_ADDR_MASK);
+@@ -804,6 +811,11 @@
+ return ret;
+ }
+
++static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
++{
++ return __tg3_writephy(tp, PHY_ADDR, reg, val);
++}
++
+ static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
+ {
+ tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
+@@ -2250,6 +2262,14 @@
+ }
+ }
+
++ if (tp->tg3_flags & TG3_FLG3_ROBOSWITCH) {
++ current_link_up = 1;
++ current_speed = SPEED_1000; //FIXME
++ current_duplex = DUPLEX_FULL;
++ tp->link_config.active_speed = current_speed;
++ tp->link_config.active_duplex = current_duplex;
++ }
++
+ if (current_link_up == 1 &&
+ tp->link_config.active_duplex == DUPLEX_FULL)
+ tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
+@@ -5197,6 +5217,11 @@
+ int i;
+ u32 val;
+
++ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
++ /* We don't use firmware. */
++ return 0;
++ }
++
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
+ /* Wait up to 20ms for init done. */
+ for (i = 0; i < 200; i++) {
+@@ -5435,6 +5460,14 @@
+ tw32(0x5000, 0x400);
+ }
+
++ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
++ /* BCM4785: In order to avoid repercussions from using potentially
++ * defective internal ROM, stop the Rx RISC CPU, which is not
++ * required. */
++ tg3_stop_fw(tp);
++ tg3_halt_cpu(tp, RX_CPU_BASE);
++ }
++
+ tw32(GRC_MODE, tp->grc_mode);
+
+ if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
+@@ -5704,9 +5737,12 @@
+ return -ENODEV;
+ }
+
+- /* Clear firmware's nvram arbitration. */
+- if (tp->tg3_flags & TG3_FLAG_NVRAM)
+- tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
++ if (!(tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)) {
++ /* Clear firmware's nvram arbitration. */
++ if (tp->tg3_flags & TG3_FLAG_NVRAM)
++ tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
++ }
++
+ return 0;
+ }
+
+@@ -5787,6 +5823,11 @@
+ struct fw_info info;
+ int err, i;
+
++ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
++ /* We don't use firmware. */
++ return 0;
++ }
++
+ info.text_base = TG3_FW_TEXT_ADDR;
+ info.text_len = TG3_FW_TEXT_LEN;
+ info.text_data = &tg3FwText[0];
+@@ -6345,6 +6386,11 @@
+ unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
+ int err, i;
+
++ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
++ /* We don't use firmware. */
++ return 0;
++ }
++
+ if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
+ return 0;
+
+@@ -7306,6 +7352,11 @@
+
+ spin_lock(&tp->lock);
+
++ if (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) {
++ /* BCM4785: Flush posted writes from GbE to host memory. */
++ tr32(HOSTCC_MODE);
++ }
++
+ if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
+ /* All of this garbage is because when using non-tagged
+ * IRQ status the mailbox/status_block protocol the chip
+@@ -8906,6 +8957,11 @@
+ __le32 *buf;
+ int i, j, k, err = 0, size;
+
++ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
++ /* We don't have NVRAM. */
++ return 0;
++ }
++
+ if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
+ return -EIO;
+
+@@ -9689,7 +9745,7 @@
+ return -EAGAIN;
+
+ spin_lock_bh(&tp->lock);
+- err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
++ err = __tg3_readphy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, &mii_regval);
+ spin_unlock_bh(&tp->lock);
+
+ data->val_out = mii_regval;
+@@ -9708,7 +9764,7 @@
+ return -EAGAIN;
+
+ spin_lock_bh(&tp->lock);
+- err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
++ err = __tg3_writephy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
+ spin_unlock_bh(&tp->lock);
+
+ return err;
+@@ -10177,6 +10233,12 @@
+ /* Chips other than 5700/5701 use the NVRAM for fetching info. */
+ static void __devinit tg3_nvram_init(struct tg3 *tp)
+ {
++ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
++ /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
++ tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
++ return;
++ }
++
+ tw32_f(GRC_EEPROM_ADDR,
+ (EEPROM_ADDR_FSM_RESET |
+ (EEPROM_DEFAULT_CLOCK_PERIOD <<
+@@ -10317,6 +10379,9 @@
+ {
+ int ret;
+
++ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
++ return -ENODEV;
++
+ if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
+ return tg3_nvram_read_using_eeprom(tp, offset, val);
+
+@@ -10563,6 +10628,9 @@
+ {
+ int ret;
+
++ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
++ return -ENODEV;
++
+ if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
+ tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
+ ~GRC_LCLCTRL_GPIO_OUTPUT1);
+@@ -11610,7 +11678,6 @@
+ tp->write32 = tg3_write_flush_reg32;
+ }
+
+-
+ if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
+ (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
+ tp->write32_tx_mbox = tg3_write32_tx_mbox;
+@@ -11646,6 +11713,11 @@
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
+ tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
+
++ if (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) {
++ tp->write32_tx_mbox = tg3_write_flush_reg32;
++ tp->write32_rx_mbox = tg3_write_flush_reg32;
++ }
++
+ /* Get eeprom hw config before calling tg3_set_power_state().
+ * In particular, the TG3_FLG2_IS_NIC flag must be
+ * determined before calling tg3_set_power_state() so that
+@@ -12017,6 +12089,10 @@
+ }
+
+ if (!is_valid_ether_addr(&dev->dev_addr[0])) {
++ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
++ ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
++ }
++ if (!is_valid_ether_addr(&dev->dev_addr[0])) {
+ #ifdef CONFIG_SPARC
+ if (!tg3_get_default_macaddr_sparc(tp))
+ return 0;
+@@ -12508,6 +12584,7 @@
+ case PHY_ID_BCM5704: return "5704";
+ case PHY_ID_BCM5705: return "5705";
+ case PHY_ID_BCM5750: return "5750";
++ case PHY_ID_BCM5750_2: return "5750-2";
+ case PHY_ID_BCM5752: return "5752";
+ case PHY_ID_BCM5714: return "5714";
+ case PHY_ID_BCM5780: return "5780";
+@@ -12695,6 +12772,13 @@
+ tp->msg_enable = tg3_debug;
+ else
+ tp->msg_enable = TG3_DEF_MSG_ENABLE;
++ if (pdev_is_ssb_gige_core(pdev)) {
++ tp->tg3_flags3 |= TG3_FLG3_IS_SSB_CORE;
++ if (ssb_gige_must_flush_posted_writes(pdev))
++ tp->tg3_flags3 |= TG3_FLG3_FLUSH_POSTED_WRITES;
++ if (ssb_gige_have_roboswitch(pdev))
++ tp->tg3_flags3 |= TG3_FLG3_ROBOSWITCH;
++ }
+
+ /* The word/byte swap controls here control register access byte
+ * swapping. DMA data byte swapping is controlled in the GRC_MODE
+--- a/drivers/net/tg3.h
++++ b/drivers/net/tg3.h
+@@ -2477,6 +2477,9 @@
+ #define TG3_FLG3_ENABLE_APE 0x00000002
+ #define TG3_FLG3_5761_5784_AX_FIXES 0x00000004
+ #define TG3_FLG3_5701_DMA_BUG 0x00000008
++#define TG3_FLG3_IS_SSB_CORE 0x00000010
++#define TG3_FLG3_FLUSH_POSTED_WRITES 0x00000020
++#define TG3_FLG3_ROBOSWITCH 0x00000040
+
+ struct timer_list timer;
+ u16 timer_counter;
+@@ -2532,6 +2535,7 @@
+ #define PHY_ID_BCM5714 0x60008340
+ #define PHY_ID_BCM5780 0x60008350
+ #define PHY_ID_BCM5755 0xbc050cc0
++#define PHY_ID_BCM5750_2 0xbc050cd0
+ #define PHY_ID_BCM5787 0xbc050ce0
+ #define PHY_ID_BCM5756 0xbc050ed0
+ #define PHY_ID_BCM5784 0xbc050fa0
+@@ -2568,7 +2572,7 @@
+ (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
+ (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \
+ (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM5761 || \
+- (X) == PHY_ID_BCM8002)
++ (X) == PHY_ID_BCM8002 || (X) == PHY_ID_BCM5750_2)
+
+ struct tg3_hw_stats *hw_stats;
+ dma_addr_t stats_mapping;
+--- a/drivers/ssb/driver_mipscore.c
++++ b/drivers/ssb/driver_mipscore.c
+@@ -212,6 +212,7 @@
+ /* fallthrough */
+ case SSB_DEV_PCI:
+ case SSB_DEV_ETHERNET:
++ case SSB_DEV_ETHERNET_GBIT:
+ case SSB_DEV_80211:
+ case SSB_DEV_USB20_HOST:
+ /* These devices get their own IRQ line if available, the rest goes on IRQ0 */
--- /dev/null
+Add gpio_is_valid() for bcm47xx
+--- a/arch/mips/bcm47xx/gpio.c
++++ b/arch/mips/bcm47xx/gpio.c
+@@ -77,3 +77,15 @@
+ }
+ EXPORT_SYMBOL_GPL(bcm47xx_gpio_direction_output);
+
++int bcm47xx_gpio_is_valid(int gpio)
++{
++ if (ssb_bcm47xx.chipco.dev) {
++ if (gpio >= 0 && gpio < BCM47XX_CHIPCO_GPIO_LINES)
++ return 1;
++ } else if (ssb_bcm47xx.extif.dev) {
++ if (gpio >= 0 && gpio < BCM47XX_EXTIF_GPIO_LINES)
++ return 1;
++ }
++ return 0;
++}
++EXPORT_SYMBOL_GPL(bcm47xx_gpio_is_valid);
+--- a/include/asm-mips/mach-bcm47xx/gpio.h
++++ b/include/asm-mips/mach-bcm47xx/gpio.h
+@@ -17,6 +17,7 @@
+ extern void bcm47xx_gpio_set_value(unsigned gpio, int value);
+ extern int bcm47xx_gpio_direction_input(unsigned gpio);
+ extern int bcm47xx_gpio_direction_output(unsigned gpio, int value);
++extern int bcm47xx_gpio_is_valid(int gpio);
+
+ static inline int gpio_request(unsigned gpio, const char *label)
+ {
+@@ -52,6 +53,8 @@
+ return bcm47xx_gpio_direction_output(gpio, value);
+ }
+
++#define gpio_is_valid bcm47xx_gpio_is_valid
++
+
+ /* cansleep wrappers */
+ #include <asm-generic/gpio.h>
--- /dev/null
+--- a/arch/mips/bcm47xx/prom.c
++++ b/arch/mips/bcm47xx/prom.c
+@@ -32,6 +32,7 @@
+ #include <asm/fw/cfe/cfe_error.h>
+
+ static int cfe_cons_handle;
++static void (* __prom_putchar)(char c);
+
+ const char *get_system_type(void)
+ {
+@@ -40,65 +41,40 @@
+
+ void prom_putchar(char c)
+ {
++ if (__prom_putchar)
++ __prom_putchar(c);
++}
++
++void prom_putchar_cfe(char c)
++{
+ while (cfe_write(cfe_cons_handle, &c, 1) == 0)
+ ;
+ }
+
+-static __init void prom_init_cfe(void)
++static __init int prom_init_cfe(void)
+ {
+ uint32_t cfe_ept;
+ uint32_t cfe_handle;
+ uint32_t cfe_eptseal;
+- int argc = fw_arg0;
+- char **envp = (char **) fw_arg2;
+- int *prom_vec = (int *) fw_arg3;
+-
+- /*
+- * Check if a loader was used; if NOT, the 4 arguments are
+- * what CFE gives us (handle, 0, EPT and EPTSEAL)
+- */
+- if (argc < 0) {
+- cfe_handle = (uint32_t)argc;
+- cfe_ept = (uint32_t)envp;
+- cfe_eptseal = (uint32_t)prom_vec;
+- } else {
+- if ((int)prom_vec < 0) {
+- /*
+- * Old loader; all it gives us is the handle,
+- * so use the "known" entrypoint and assume
+- * the seal.
+- */
+- cfe_handle = (uint32_t)prom_vec;
+- cfe_ept = 0xBFC00500;
+- cfe_eptseal = CFE_EPTSEAL;
+- } else {
+- /*
+- * Newer loaders bundle the handle/ept/eptseal
+- * Note: prom_vec is in the loader's useg
+- * which is still alive in the TLB.
+- */
+- cfe_handle = prom_vec[0];
+- cfe_ept = prom_vec[2];
+- cfe_eptseal = prom_vec[3];
+- }
+- }
+
+- if (cfe_eptseal != CFE_EPTSEAL) {
+- /* too early for panic to do any good */
+- printk(KERN_ERR "CFE's entrypoint seal doesn't match.");
+- while (1) ;
+- }
++ cfe_eptseal = (uint32_t) fw_arg3;
++ cfe_handle = (uint32_t) fw_arg0;
++ cfe_ept = (uint32_t) fw_arg2;
++
++ if (cfe_eptseal != CFE_EPTSEAL)
++ return -1;
+
+ cfe_init(cfe_handle, cfe_ept);
++ return 0;
+ }
+
+-static __init void prom_init_console(void)
++static __init void prom_init_console_cfe(void)
+ {
+ /* Initialize CFE console */
+ cfe_cons_handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE);
+ }
+
+-static __init void prom_init_cmdline(void)
++static __init void prom_init_cmdline_cfe(void)
+ {
+ char buf[CL_SIZE];
+
+@@ -146,9 +122,12 @@
+
+ void __init prom_init(void)
+ {
+- prom_init_cfe();
+- prom_init_console();
+- prom_init_cmdline();
++ if (prom_init_cfe() == 0) {
++ //prom_init_console_cfe();
++ //prom_init_cmdline_cfe();
++ __prom_putchar = prom_putchar_cfe;
++ }
++
+ prom_init_mem();
+ }
+
--- /dev/null
+--- linux-2.6.28.9/arch/mips/Kconfig 2009-04-17 10:43:28.000000000 +0200
++++ linux-2.6.28.9.new/arch/mips/Kconfig 2009-04-17 10:43:51.000000000 +0200
+@@ -56,7 +56,6 @@
+ select SSB_B43_PCI_BRIDGE if PCI
+ select SSB_PCICORE_HOSTMODE if PCI
+ select GENERIC_GPIO
+- select SYS_HAS_EARLY_PRINTK
+ select CFE
+ help
+ Support for BCM47XX based boards
+++ /dev/null
-CONFIG_32BIT=y
-# CONFIG_64BIT is not set
-# CONFIG_8139TOO is not set
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_ARCH_POPULATES_NODE_MAP=y
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-CONFIG_ARCH_SUPPORTS_OPROFILE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-# CONFIG_ATM is not set
-CONFIG_BASE_SMALL=0
-# CONFIG_BCM47XX is not set
-CONFIG_BITREVERSE=y
-# CONFIG_BT is not set
-CONFIG_CEVT_R4K=y
-CONFIG_CLASSIC_RCU=y
-CONFIG_CMDLINE="console=ttyS0,9600 rootfstype=squashfs,jffs2 init=/etc/preinit"
-CONFIG_CPU_BIG_ENDIAN=y
-CONFIG_CPU_HAS_LLSC=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_SYNC=y
-# CONFIG_CPU_LITTLE_ENDIAN is not set
-# CONFIG_CPU_LOONGSON2 is not set
-CONFIG_CPU_MIPS32=y
-CONFIG_CPU_MIPS32_R1=y
-# CONFIG_CPU_MIPS32_R2 is not set
-# CONFIG_CPU_MIPS64_R1 is not set
-# CONFIG_CPU_MIPS64_R2 is not set
-CONFIG_CPU_MIPSR1=y
-# CONFIG_CPU_NEVADA is not set
-# CONFIG_CPU_R10000 is not set
-# CONFIG_CPU_R3000 is not set
-# CONFIG_CPU_R4300 is not set
-# CONFIG_CPU_R4X00 is not set
-# CONFIG_CPU_R5000 is not set
-# CONFIG_CPU_R5432 is not set
-# CONFIG_CPU_R6000 is not set
-# CONFIG_CPU_R8000 is not set
-# CONFIG_CPU_RM7000 is not set
-# CONFIG_CPU_RM9000 is not set
-# CONFIG_CPU_SB1 is not set
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-# CONFIG_CPU_TX39XX is not set
-# CONFIG_CPU_TX49XX is not set
-# CONFIG_CPU_VR41XX is not set
-CONFIG_CRYPTO_GF128MUL=m
-CONFIG_CSRC_R4K=y
-CONFIG_DEVPORT=y
-# CONFIG_DM9000 is not set
-CONFIG_DMA_NEED_PCI_MAP_STATE=y
-CONFIG_DMA_NONCOHERENT=y
-# CONFIG_E1000E_ENABLED is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_FS_POSIX_ACL=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-# CONFIG_GENERIC_FIND_FIRST_BIT is not set
-CONFIG_GENERIC_FIND_NEXT_BIT=y
-CONFIG_GENERIC_GPIO=y
-# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
-CONFIG_GPIO_DEVICE=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAVE_DMA_ATTRS is not set
-CONFIG_HAVE_IDE=y
-# CONFIG_HAVE_KPROBES is not set
-# CONFIG_HAVE_KRETPROBES is not set
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_STD_PC_SERIAL_PORT=y
-# CONFIG_HIGH_RES_TIMERS is not set
-# CONFIG_HOSTAP is not set
-CONFIG_HW_HAS_PCI=y
-CONFIG_HW_RANDOM=y
-# CONFIG_I2C is not set
-# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_IBM_NEW_EMAC_RGMII is not set
-# CONFIG_IBM_NEW_EMAC_TAH is not set
-# CONFIG_IBM_NEW_EMAC_ZMII is not set
-# CONFIG_IDE is not set
-CONFIG_IFXMIPS=y
-CONFIG_IFXMIPS_EEPROM=y
-CONFIG_IFXMIPS_GPIO_RST_BTN=y
-# CONFIG_IFXMIPS_MEI is not set
-CONFIG_IFXMIPS_MII0=y
-# CONFIG_IFXMIPS_PROM_ASC0 is not set
-CONFIG_IFXMIPS_PROM_ASC1=y
-CONFIG_IFXMIPS_SSC=y
-CONFIG_IFXMIPS_WDT=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IPV6_NDISC_NODETYPE=y
-CONFIG_IRQ_CPU=y
-# CONFIG_IWLWIFI_LEDS is not set
-CONFIG_KALLSYMS=y
-# CONFIG_LEDS_ALIX is not set
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_IFXMIPS=y
-# CONFIG_LEMOTE_FULONG is not set
-# CONFIG_MACH_ALCHEMY is not set
-# CONFIG_MACH_DECSTATION is not set
-# CONFIG_MACH_JAZZ is not set
-# CONFIG_MACH_VR41XX is not set
-CONFIG_MIPS=y
-# CONFIG_MIPS_ATLAS is not set
-# CONFIG_MIPS_COBALT is not set
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-# CONFIG_MIPS_MALTA is not set
-CONFIG_MIPS_MT_DISABLED=y
-# CONFIG_MIPS_MT_SMP is not set
-# CONFIG_MIPS_MT_SMTC is not set
-# CONFIG_MIPS_SEAD is not set
-# CONFIG_MIPS_SIM is not set
-CONFIG_MTD=y
-# CONFIG_MTD_ABSENT is not set
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_MTD_BLOCK2MTD is not set
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_AMDSTD=y
-# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
-CONFIG_MTD_CFI_GEOMETRY=y
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-# CONFIG_MTD_CFI_INTELEXT is not set
-# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
-CONFIG_MTD_CFI_NOSWAP=y
-# CONFIG_MTD_CFI_STAA is not set
-CONFIG_MTD_CFI_UTIL=y
-CONFIG_MTD_CHAR=y
-# CONFIG_MTD_CMDLINE_PARTS is not set
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-# CONFIG_MTD_CONCAT is not set
-# CONFIG_MTD_DEBUG is not set
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-CONFIG_MTD_GEN_PROBE=y
-CONFIG_MTD_IFXMIPS=y
-# CONFIG_MTD_JEDECPROBE is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_ONENAND is not set
-# CONFIG_MTD_OTP is not set
-CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_PCI is not set
-# CONFIG_MTD_PHRAM is not set
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_BANKWIDTH=0
-CONFIG_MTD_PHYSMAP_LEN=0x0
-CONFIG_MTD_PHYSMAP_START=0x0
-# CONFIG_MTD_PLATRAM is not set
-# CONFIG_MTD_PMC551 is not set
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_NATSEMI is not set
-# CONFIG_NE2K_PCI is not set
-# CONFIG_NET_VENDOR_3COM is not set
-# CONFIG_NO_IOPORT is not set
-# CONFIG_OCF_OCF is not set
-CONFIG_PAGEFLAGS_EXTENDED=y
-# CONFIG_PAGE_SIZE_16KB is not set
-CONFIG_PAGE_SIZE_4KB=y
-# CONFIG_PAGE_SIZE_64KB is not set
-# CONFIG_PAGE_SIZE_8KB is not set
-CONFIG_PCI=y
-# CONFIG_PCIPCWATCHDOG is not set
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCSPKR_PLATFORM=y
-# CONFIG_PMC_MSP is not set
-# CONFIG_PMC_YOSEMITE is not set
-# CONFIG_PNX8550_JBS is not set
-# CONFIG_PNX8550_STB810 is not set
-# CONFIG_R6040 is not set
-CONFIG_RFKILL_LEDS=y
-CONFIG_RTC_LIB=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
-CONFIG_SCSI_WAIT_SCAN=m
-# CONFIG_SERIAL_8250 is not set
-CONFIG_SERIAL_IFXMIPS=y
-# CONFIG_SGI_IP22 is not set
-# CONFIG_SGI_IP27 is not set
-# CONFIG_SGI_IP28 is not set
-# CONFIG_SGI_IP32 is not set
-# CONFIG_SIBYTE_BIGSUR is not set
-# CONFIG_SIBYTE_CARMEL is not set
-# CONFIG_SIBYTE_CRHINE is not set
-# CONFIG_SIBYTE_CRHONE is not set
-# CONFIG_SIBYTE_LITTLESUR is not set
-# CONFIG_SIBYTE_RHONE is not set
-# CONFIG_SIBYTE_SENTOSA is not set
-# CONFIG_SIBYTE_SWARM is not set
-# CONFIG_SOFT_WATCHDOG is not set
-# CONFIG_SPARSEMEM_STATIC is not set
-# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
-CONFIG_SSB_POSSIBLE=y
-CONFIG_SWAP_IO_SPACE=y
-CONFIG_SYSVIPC_SYSCTL=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
-# CONFIG_TC35815 is not set
-# CONFIG_THERMAL is not set
-# CONFIG_THERMAL_HWMON is not set
-# CONFIG_TICK_ONESHOT is not set
-# CONFIG_TOSHIBA_JMR3927 is not set
-# CONFIG_TOSHIBA_RBTX4927 is not set
-# CONFIG_TOSHIBA_RBTX4938 is not set
-CONFIG_TRAD_SIGNALS=y
-CONFIG_USB=m
-# CONFIG_USB_DWC_HCD is not set
-# CONFIG_USB_EHCI_HCD is not set
-# CONFIG_USB_ISIGHTFW is not set
-CONFIG_USB_SUPPORT=y
-# CONFIG_USB_UHCI_HCD is not set
-# CONFIG_VGASTATE is not set
-# CONFIG_VIA_RHINE is not set
-CONFIG_VIDEO_MEDIA=m
-CONFIG_VIDEO_V4L1=m
-CONFIG_VIDEO_V4L2=m
-CONFIG_VIDEO_V4L2_COMMON=m
-CONFIG_ZONE_DMA_FLAG=0
--- /dev/null
+CONFIG_32BIT=y
+# CONFIG_64BIT is not set
+# CONFIG_8139TOO is not set
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_ATM is not set
+CONFIG_BASE_SMALL=0
+# CONFIG_BCM47XX is not set
+CONFIG_BITREVERSE=y
+# CONFIG_BT is not set
+CONFIG_CEVT_R4K=y
+CONFIG_CLASSIC_RCU=y
+CONFIG_CMDLINE="console=ttyS0,9600 rootfstype=squashfs,jffs2 init=/etc/preinit"
+CONFIG_CPU_BIG_ENDIAN=y
+CONFIG_CPU_HAS_LLSC=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_SYNC=y
+# CONFIG_CPU_LITTLE_ENDIAN is not set
+# CONFIG_CPU_LOONGSON2 is not set
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPS32_R1=y
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+CONFIG_CPU_MIPSR1=y
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_VR41XX is not set
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CSRC_R4K=y
+CONFIG_DEVPORT=y
+# CONFIG_DM9000 is not set
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_DMA_NONCOHERENT=y
+# CONFIG_E1000E_ENABLED is not set
+CONFIG_EARLY_PRINTK=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
+CONFIG_GPIO_DEVICE=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+# CONFIG_HAVE_DMA_ATTRS is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_STD_PC_SERIAL_PORT=y
+# CONFIG_HIGH_RES_TIMERS is not set
+# CONFIG_HOSTAP is not set
+CONFIG_HW_HAS_PCI=y
+CONFIG_HW_RANDOM=y
+# CONFIG_I2C is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IDE is not set
+CONFIG_IFXMIPS=y
+CONFIG_IFXMIPS_EEPROM=y
+CONFIG_IFXMIPS_GPIO_RST_BTN=y
+# CONFIG_IFXMIPS_MEI is not set
+CONFIG_IFXMIPS_MII0=y
+# CONFIG_IFXMIPS_PROM_ASC0 is not set
+CONFIG_IFXMIPS_PROM_ASC1=y
+CONFIG_IFXMIPS_SSC=y
+CONFIG_IFXMIPS_WDT=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_IRQ_CPU=y
+# CONFIG_IWLWIFI_LEDS is not set
+CONFIG_KALLSYMS=y
+# CONFIG_LEDS_ALIX is not set
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_IFXMIPS=y
+# CONFIG_LEMOTE_FULONG is not set
+# CONFIG_MACH_ALCHEMY is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_MACH_VR41XX is not set
+CONFIG_MIPS=y
+# CONFIG_MIPS_ATLAS is not set
+# CONFIG_MIPS_COBALT is not set
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+# CONFIG_MIPS_MALTA is not set
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+# CONFIG_MIPS_SEAD is not set
+# CONFIG_MIPS_SIM is not set
+CONFIG_MTD=y
+# CONFIG_MTD_ABSENT is not set
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_MTD_BLOCK2MTD is not set
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_CHAR=y
+# CONFIG_MTD_CMDLINE_PARTS is not set
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_CONCAT is not set
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_IFXMIPS=y
+# CONFIG_MTD_JEDECPROBE is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_ONENAND is not set
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_PCI is not set
+# CONFIG_MTD_PHRAM is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_BANKWIDTH=0
+CONFIG_MTD_PHYSMAP_LEN=0x0
+CONFIG_MTD_PHYSMAP_START=0x0
+# CONFIG_MTD_PLATRAM is not set
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NO_IOPORT is not set
+# CONFIG_OCF_OCF is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+# CONFIG_PAGE_SIZE_16KB is not set
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_64KB is not set
+# CONFIG_PAGE_SIZE_8KB is not set
+CONFIG_PCI=y
+# CONFIG_PCIPCWATCHDOG is not set
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCSPKR_PLATFORM=y
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_R6040 is not set
+CONFIG_RFKILL_LEDS=y
+CONFIG_RTC_LIB=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_SCSI_WAIT_SCAN=m
+# CONFIG_SERIAL_8250 is not set
+CONFIG_SERIAL_IFXMIPS=y
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SSB_POSSIBLE=y
+CONFIG_SWAP_IO_SPACE=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+# CONFIG_TC35815 is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_TOSHIBA_RBTX4927 is not set
+# CONFIG_TOSHIBA_RBTX4938 is not set
+CONFIG_TRAD_SIGNALS=y
+CONFIG_USB=m
+# CONFIG_USB_DWC_HCD is not set
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_ISIGHTFW is not set
+CONFIG_USB_SUPPORT=y
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIA_RHINE is not set
+CONFIG_VIDEO_MEDIA=m
+CONFIG_VIDEO_V4L1=m
+CONFIG_VIDEO_V4L2=m
+CONFIG_VIDEO_V4L2_COMMON=m
+CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
---- a/arch/arm/configs/ixp4xx_defconfig
-+++ b/arch/arm/configs/ixp4xx_defconfig
-@@ -165,6 +165,7 @@
- CONFIG_MACH_NAS100D=y
- CONFIG_MACH_DSMG600=y
- CONFIG_ARCH_IXDP4XX=y
-+CONFIG_MACH_FSG=y
- CONFIG_CPU_IXP46X=y
- CONFIG_CPU_IXP43X=y
- CONFIG_MACH_GTWX5715=y
-@@ -770,7 +771,7 @@
- # CONFIG_SATA_SIL24 is not set
- # CONFIG_SATA_SIS is not set
- # CONFIG_SATA_ULI is not set
--# CONFIG_SATA_VIA is not set
-+CONFIG_SATA_VIA=y
- # CONFIG_SATA_VITESSE is not set
- # CONFIG_SATA_INIC162X is not set
- # CONFIG_PATA_ALI is not set
-@@ -1143,7 +1144,7 @@
- # CONFIG_SENSORS_VIA686A is not set
- # CONFIG_SENSORS_VT1211 is not set
- # CONFIG_SENSORS_VT8231 is not set
--# CONFIG_SENSORS_W83781D is not set
-+CONFIG_SENSORS_W83781D=y
- # CONFIG_SENSORS_W83791D is not set
- # CONFIG_SENSORS_W83792D is not set
- # CONFIG_SENSORS_W83793 is not set
-@@ -1334,8 +1335,8 @@
- #
- # LED drivers
- #
--# CONFIG_LEDS_IXP4XX is not set
- CONFIG_LEDS_GPIO=y
-+CONFIG_LEDS_FSG=y
-
- #
- # LED Triggers
-@@ -1367,7 +1368,7 @@
- # CONFIG_RTC_DRV_DS1672 is not set
- # CONFIG_RTC_DRV_MAX6900 is not set
- # CONFIG_RTC_DRV_RS5C372 is not set
--# CONFIG_RTC_DRV_ISL1208 is not set
-+CONFIG_RTC_DRV_ISL1208=y
- CONFIG_RTC_DRV_X1205=y
- CONFIG_RTC_DRV_PCF8563=y
- # CONFIG_RTC_DRV_PCF8583 is not set
---- a/arch/arm/mach-ixp4xx/Kconfig
-+++ b/arch/arm/mach-ixp4xx/Kconfig
-@@ -125,6 +125,15 @@
- depends on ARCH_IXDP425 || MACH_IXDP465 || MACH_KIXRP435
- default y
-
-+config MACH_FSG
-+ bool
-+ prompt "Freecom FSG-3"
-+ select PCI
-+ help
-+ Say 'Y' here if you want your kernel to support Freecom's
-+ FSG-3 device. For more information on this platform,
-+ see http://www.nslu2-linux.org/wiki/FSG3/HomePage
-+
- #
- # Certain registers and IRQs are only enabled if supporting IXP465 CPUs
- #
---- a/arch/arm/mach-ixp4xx/Makefile
-+++ b/arch/arm/mach-ixp4xx/Makefile
-@@ -15,6 +15,7 @@
- obj-pci-$(CONFIG_MACH_DSMG600) += dsmg600-pci.o
- obj-pci-$(CONFIG_MACH_GATEWAY7001) += gateway7001-pci.o
- obj-pci-$(CONFIG_MACH_WG302V2) += wg302v2-pci.o
-+obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o
-
- obj-y += common.o
-
-@@ -28,6 +29,7 @@
- obj-$(CONFIG_MACH_DSMG600) += dsmg600-setup.o
- obj-$(CONFIG_MACH_GATEWAY7001) += gateway7001-setup.o
- obj-$(CONFIG_MACH_WG302V2) += wg302v2-setup.o
-+obj-$(CONFIG_MACH_FSG) += fsg-setup.o
-
- obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
- obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o
---- /dev/null
-+++ b/arch/arm/mach-ixp4xx/fsg-pci.c
-@@ -0,0 +1,71 @@
-+/*
-+ * arch/arch/mach-ixp4xx/fsg-pci.c
-+ *
-+ * FSG board-level PCI initialization
-+ *
-+ * Author: Rod Whitby <rod@whitby.id.au>
-+ * Maintainer: http://www.nslu2-linux.org/
-+ *
-+ * based on ixdp425-pci.c:
-+ * Copyright (C) 2002 Intel Corporation.
-+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ */
-+
-+#include <linux/pci.h>
-+#include <linux/init.h>
-+#include <linux/irq.h>
-+
-+#include <asm/mach/pci.h>
-+#include <asm/mach-types.h>
-+
-+void __init fsg_pci_preinit(void)
-+{
-+ set_irq_type(IRQ_FSG_PCI_INTA, IRQT_LOW);
-+ set_irq_type(IRQ_FSG_PCI_INTB, IRQT_LOW);
-+ set_irq_type(IRQ_FSG_PCI_INTC, IRQT_LOW);
-+
-+ ixp4xx_pci_preinit();
-+}
-+
-+static int __init fsg_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
-+{
-+ static int pci_irq_table[FSG_PCI_IRQ_LINES] = {
-+ IRQ_FSG_PCI_INTC,
-+ IRQ_FSG_PCI_INTB,
-+ IRQ_FSG_PCI_INTA,
-+ };
-+
-+ int irq = -1;
-+ slot = slot - 11;
-+
-+ if (slot >= 1 && slot <= FSG_PCI_MAX_DEV &&
-+ pin >= 1 && pin <= FSG_PCI_IRQ_LINES)
-+ irq = pci_irq_table[(slot - 1)];
-+ printk(KERN_INFO "%s: Mapped slot %d pin %d to IRQ %d\n",
-+ __func__, slot, pin, irq);
-+
-+ return irq;
-+}
-+
-+struct hw_pci fsg_pci __initdata = {
-+ .nr_controllers = 1,
-+ .preinit = fsg_pci_preinit,
-+ .swizzle = pci_std_swizzle,
-+ .setup = ixp4xx_setup,
-+ .scan = ixp4xx_scan_bus,
-+ .map_irq = fsg_map_irq,
-+};
-+
-+int __init fsg_pci_init(void)
-+{
-+ if (machine_is_fsg())
-+ pci_common_init(&fsg_pci);
-+ return 0;
-+}
-+
-+subsys_initcall(fsg_pci_init);
---- /dev/null
-+++ b/arch/arm/mach-ixp4xx/fsg-setup.c
-@@ -0,0 +1,276 @@
-+/*
-+ * arch/arm/mach-ixp4xx/fsg-setup.c
-+ *
-+ * FSG board-setup
-+ *
-+ * Copyright (C) 2008 Rod Whitby <rod@whitby.id.au>
-+ *
-+ * based on ixdp425-setup.c:
-+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
-+ * based on nslu2-power.c
-+ * Copyright (C) 2005 Tower Technologies
-+ *
-+ * Author: Rod Whitby <rod@whitby.id.au>
-+ * Maintainers: http://www.nslu2-linux.org/
-+ *
-+ */
-+
-+#include <linux/if_ether.h>
-+#include <linux/irq.h>
-+#include <linux/serial.h>
-+#include <linux/serial_8250.h>
-+#include <linux/leds.h>
-+#include <linux/reboot.h>
-+#include <linux/i2c.h>
-+#include <linux/i2c-gpio.h>
-+
-+#include <asm/mach-types.h>
-+#include <asm/mach/arch.h>
-+#include <asm/mach/flash.h>
-+#include <asm/io.h>
-+#include <asm/gpio.h>
-+
-+static struct flash_platform_data fsg_flash_data = {
-+ .map_name = "cfi_probe",
-+ .width = 2,
-+};
-+
-+static struct resource fsg_flash_resource = {
-+ .flags = IORESOURCE_MEM,
-+};
-+
-+static struct platform_device fsg_flash = {
-+ .name = "IXP4XX-Flash",
-+ .id = 0,
-+ .dev = {
-+ .platform_data = &fsg_flash_data,
-+ },
-+ .num_resources = 1,
-+ .resource = &fsg_flash_resource,
-+};
-+
-+static struct i2c_gpio_platform_data fsg_i2c_gpio_data = {
-+ .sda_pin = FSG_SDA_PIN,
-+ .scl_pin = FSG_SCL_PIN,
-+};
-+
-+static struct platform_device fsg_i2c_gpio = {
-+ .name = "i2c-gpio",
-+ .id = 0,
-+ .dev = {
-+ .platform_data = &fsg_i2c_gpio_data,
-+ },
-+};
-+
-+static struct i2c_board_info __initdata fsg_i2c_board_info [] = {
-+ {
-+ I2C_BOARD_INFO("isl1208", 0x6f),
-+ },
-+};
-+
-+static struct resource fsg_uart_resources[] = {
-+ {
-+ .start = IXP4XX_UART1_BASE_PHYS,
-+ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ {
-+ .start = IXP4XX_UART2_BASE_PHYS,
-+ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
-+ .flags = IORESOURCE_MEM,
-+ }
-+};
-+
-+static struct plat_serial8250_port fsg_uart_data[] = {
-+ {
-+ .mapbase = IXP4XX_UART1_BASE_PHYS,
-+ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
-+ .irq = IRQ_IXP4XX_UART1,
-+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
-+ .iotype = UPIO_MEM,
-+ .regshift = 2,
-+ .uartclk = IXP4XX_UART_XTAL,
-+ },
-+ {
-+ .mapbase = IXP4XX_UART2_BASE_PHYS,
-+ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
-+ .irq = IRQ_IXP4XX_UART2,
-+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
-+ .iotype = UPIO_MEM,
-+ .regshift = 2,
-+ .uartclk = IXP4XX_UART_XTAL,
-+ },
-+ { }
-+};
-+
-+static struct platform_device fsg_uart = {
-+ .name = "serial8250",
-+ .id = PLAT8250_DEV_PLATFORM,
-+ .dev = {
-+ .platform_data = fsg_uart_data,
-+ },
-+ .num_resources = ARRAY_SIZE(fsg_uart_resources),
-+ .resource = fsg_uart_resources,
-+};
-+
-+static struct platform_device fsg_leds = {
-+ .name = "fsg-led",
-+ .id = -1,
-+};
-+
-+/* Built-in 10/100 Ethernet MAC interfaces */
-+static struct eth_plat_info fsg_plat_eth[] = {
-+ {
-+ .phy = 5,
-+ .rxq = 3,
-+ .txreadyq = 20,
-+ }, {
-+ .phy = 4,
-+ .rxq = 4,
-+ .txreadyq = 21,
-+ }
-+};
-+
-+static struct platform_device fsg_eth[] = {
-+ {
-+ .name = "ixp4xx_eth",
-+ .id = IXP4XX_ETH_NPEB,
-+ .dev = {
-+ .platform_data = fsg_plat_eth,
-+ },
-+ }, {
-+ .name = "ixp4xx_eth",
-+ .id = IXP4XX_ETH_NPEC,
-+ .dev = {
-+ .platform_data = fsg_plat_eth + 1,
-+ },
-+ }
-+};
-+
-+static struct platform_device *fsg_devices[] __initdata = {
-+ &fsg_i2c_gpio,
-+ &fsg_flash,
-+ &fsg_leds,
-+ &fsg_eth[0],
-+ &fsg_eth[1],
-+};
-+
-+static irqreturn_t fsg_power_handler(int irq, void *dev_id)
-+{
-+ /* Signal init to do the ctrlaltdel action, this will bypass init if
-+ * it hasn't started and do a kernel_restart.
-+ */
-+ ctrl_alt_del();
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static irqreturn_t fsg_reset_handler(int irq, void *dev_id)
-+{
-+ /* This is the paper-clip reset which does an emergency reboot. */
-+ printk(KERN_INFO "Restarting system.\n");
-+ machine_restart(NULL);
-+
-+ /* This should never be reached. */
-+ return IRQ_HANDLED;
-+}
-+
-+static void __init fsg_init(void)
-+{
-+ DECLARE_MAC_BUF(mac_buf);
-+ uint8_t __iomem *f;
-+ int i;
-+
-+ ixp4xx_sys_init();
-+
-+ fsg_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
-+ fsg_flash_resource.end =
-+ IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
-+
-+ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
-+ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
-+
-+ /* Configure CS2 for operation, 8bit and writable */
-+ *IXP4XX_EXP_CS2 = 0xbfff0002;
-+
-+ i2c_register_board_info(0, fsg_i2c_board_info,
-+ ARRAY_SIZE(fsg_i2c_board_info));
-+
-+ /* This is only useful on a modified machine, but it is valuable
-+ * to have it first in order to see debug messages, and so that
-+ * it does *not* get removed if platform_add_devices fails!
-+ */
-+ (void)platform_device_register(&fsg_uart);
-+
-+ platform_add_devices(fsg_devices, ARRAY_SIZE(fsg_devices));
-+
-+ if (request_irq(gpio_to_irq(FSG_RB_GPIO), &fsg_reset_handler,
-+ IRQF_DISABLED | IRQF_TRIGGER_LOW,
-+ "FSG reset button", NULL) < 0) {
-+
-+ printk(KERN_DEBUG "Reset Button IRQ %d not available\n",
-+ gpio_to_irq(FSG_RB_GPIO));
-+ }
-+
-+ if (request_irq(gpio_to_irq(FSG_SB_GPIO), &fsg_power_handler,
-+ IRQF_DISABLED | IRQF_TRIGGER_LOW,
-+ "FSG power button", NULL) < 0) {
-+
-+ printk(KERN_DEBUG "Power Button IRQ %d not available\n",
-+ gpio_to_irq(FSG_SB_GPIO));
-+ }
-+
-+ /*
-+ * Map in a portion of the flash and read the MAC addresses.
-+ * Since it is stored in BE in the flash itself, we need to
-+ * byteswap it if we're in LE mode.
-+ */
-+ f = ioremap(IXP4XX_EXP_BUS_BASE(0), 0x400000);
-+ if (f) {
-+#ifdef __ARMEB__
-+ for (i = 0; i < 6; i++) {
-+ fsg_plat_eth[0].hwaddr[i] = readb(f + 0x3C0422 + i);
-+ fsg_plat_eth[1].hwaddr[i] = readb(f + 0x3C043B + i);
-+ }
-+#else
-+
-+ /*
-+ Endian-swapped reads from unaligned addresses are
-+ required to extract the two MACs from the big-endian
-+ Redboot config area in flash.
-+ */
-+
-+ fsg_plat_eth[0].hwaddr[0] = readb(f + 0x3C0421);
-+ fsg_plat_eth[0].hwaddr[1] = readb(f + 0x3C0420);
-+ fsg_plat_eth[0].hwaddr[2] = readb(f + 0x3C0427);
-+ fsg_plat_eth[0].hwaddr[3] = readb(f + 0x3C0426);
-+ fsg_plat_eth[0].hwaddr[4] = readb(f + 0x3C0425);
-+ fsg_plat_eth[0].hwaddr[5] = readb(f + 0x3C0424);
-+
-+ fsg_plat_eth[1].hwaddr[0] = readb(f + 0x3C0439);
-+ fsg_plat_eth[1].hwaddr[1] = readb(f + 0x3C043F);
-+ fsg_plat_eth[1].hwaddr[2] = readb(f + 0x3C043E);
-+ fsg_plat_eth[1].hwaddr[3] = readb(f + 0x3C043D);
-+ fsg_plat_eth[1].hwaddr[4] = readb(f + 0x3C043C);
-+ fsg_plat_eth[1].hwaddr[5] = readb(f + 0x3C0443);
-+#endif
-+ iounmap(f);
-+ }
-+ printk(KERN_INFO "FSG: Using MAC address %s for port 0\n",
-+ print_mac(mac_buf, fsg_plat_eth[0].hwaddr));
-+ printk(KERN_INFO "FSG: Using MAC address %s for port 1\n",
-+ print_mac(mac_buf, fsg_plat_eth[1].hwaddr));
-+
-+}
-+
-+MACHINE_START(FSG, "Freecom FSG-3")
-+ /* Maintainer: www.nslu2-linux.org */
-+ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
-+ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
-+ .map_io = ixp4xx_map_io,
-+ .init_irq = ixp4xx_init_irq,
-+ .timer = &ixp4xx_timer,
-+ .boot_params = 0x0100,
-+ .init_machine = fsg_init,
-+MACHINE_END
-+
---- /dev/null
-+++ b/include/asm-arm/arch-ixp4xx/fsg.h
-@@ -0,0 +1,50 @@
-+/*
-+ * include/asm-arm/arch-ixp4xx/fsg.h
-+ *
-+ * Freecom FSG-3 platform specific definitions
-+ *
-+ * Author: Rod Whitby <rod@whitby.id.au>
-+ * Author: Tomasz Chmielewski <mangoo@wpkg.org>
-+ * Maintainers: http://www.nslu2-linux.org
-+ *
-+ * Based on coyote.h by
-+ * Copyright 2004 (c) MontaVista, Software, Inc.
-+ *
-+ * This file is licensed under the terms of the GNU General Public
-+ * License version 2. This program is licensed "as is" without any
-+ * warranty of any kind, whether express or implied.
-+ */
-+
-+#ifndef __ASM_ARCH_HARDWARE_H__
-+#error "Do not include this directly, instead #include <asm/hardware.h>"
-+#endif
-+
-+#define FSG_SDA_PIN 12
-+#define FSG_SCL_PIN 13
-+
-+/*
-+ * FSG PCI IRQs
-+ */
-+#define FSG_PCI_MAX_DEV 3
-+#define FSG_PCI_IRQ_LINES 3
-+
-+
-+/* PCI controller GPIO to IRQ pin mappings */
-+#define FSG_PCI_INTA_PIN 6
-+#define FSG_PCI_INTB_PIN 7
-+#define FSG_PCI_INTC_PIN 5
-+
-+/* Buttons */
-+
-+#define FSG_SB_GPIO 4 /* sync button */
-+#define FSG_RB_GPIO 9 /* reset button */
-+#define FSG_UB_GPIO 10 /* usb button */
-+
-+/* LEDs */
-+
-+#define FSG_LED_WLAN_BIT 0
-+#define FSG_LED_WAN_BIT 1
-+#define FSG_LED_SATA_BIT 2
-+#define FSG_LED_USB_BIT 4
-+#define FSG_LED_RING_BIT 5
-+#define FSG_LED_SYNC_BIT 7
---- a/include/asm-arm/arch-ixp4xx/hardware.h
-+++ b/include/asm-arm/arch-ixp4xx/hardware.h
-@@ -45,5 +45,6 @@
- #include "nslu2.h"
- #include "nas100d.h"
- #include "dsmg600.h"
-+#include "fsg.h"
-
- #endif /* _ASM_ARCH_HARDWARE_H */
---- a/include/asm-arm/arch-ixp4xx/irqs.h
-+++ b/include/asm-arm/arch-ixp4xx/irqs.h
-@@ -128,4 +128,11 @@
- #define IRQ_DSMG600_PCI_INTE IRQ_IXP4XX_GPIO7
- #define IRQ_DSMG600_PCI_INTF IRQ_IXP4XX_GPIO6
-
-+/*
-+ * Freecom FSG-3 Board IRQs
-+ */
-+#define IRQ_FSG_PCI_INTA IRQ_IXP4XX_GPIO6
-+#define IRQ_FSG_PCI_INTB IRQ_IXP4XX_GPIO7
-+#define IRQ_FSG_PCI_INTC IRQ_IXP4XX_GPIO5
-+
- #endif
+++ /dev/null
---- a/drivers/char/random.c
-+++ b/drivers/char/random.c
-@@ -258,9 +258,9 @@
- /*
- * Configuration information
- */
--#define INPUT_POOL_WORDS 128
--#define OUTPUT_POOL_WORDS 32
--#define SEC_XFER_SIZE 512
-+#define INPUT_POOL_WORDS 256
-+#define OUTPUT_POOL_WORDS 64
-+#define SEC_XFER_SIZE 1024
-
- /*
- * The minimum number of bits of entropy before we wake up a read on
+++ /dev/null
---- a/arch/arm/mach-ixp4xx/gateway7001-setup.c
-+++ b/arch/arm/mach-ixp4xx/gateway7001-setup.c
-@@ -76,9 +76,35 @@
- .resource = &gateway7001_uart_resource,
- };
-
-+static struct eth_plat_info gateway7001_plat_eth[] = {
-+ {
-+ .phy = 1,
-+ .rxq = 3,
-+ .txreadyq = 20,
-+ }, {
-+ .phy = 2,
-+ .rxq = 4,
-+ .txreadyq = 21,
-+ }
-+};
-+
-+static struct platform_device gateway7001_eth[] = {
-+ {
-+ .name = "ixp4xx_eth",
-+ .id = IXP4XX_ETH_NPEB,
-+ .dev.platform_data = gateway7001_plat_eth,
-+ }, {
-+ .name = "ixp4xx_eth",
-+ .id = IXP4XX_ETH_NPEC,
-+ .dev.platform_data = gateway7001_plat_eth + 1,
-+ }
-+};
-+
- static struct platform_device *gateway7001_devices[] __initdata = {
- &gateway7001_flash,
-- &gateway7001_uart
-+ &gateway7001_uart,
-+ &gateway7001_eth[0],
-+ &gateway7001_eth[1],
- };
-
- static void __init gateway7001_init(void)
---- a/arch/arm/mach-ixp4xx/wg302v2-setup.c
-+++ b/arch/arm/mach-ixp4xx/wg302v2-setup.c
-@@ -77,9 +77,26 @@
- .resource = &wg302v2_uart_resource,
- };
-
-+static struct eth_plat_info wg302v2_plat_eth[] = {
-+ {
-+ .phy = 8,
-+ .rxq = 3,
-+ .txreadyq = 20,
-+ }
-+};
-+
-+static struct platform_device wg302v2_eth[] = {
-+ {
-+ .name = "ixp4xx_eth",
-+ .id = IXP4XX_ETH_NPEB,
-+ .dev.platform_data = wg302v2_plat_eth,
-+ }
-+};
-+
- static struct platform_device *wg302v2_devices[] __initdata = {
- &wg302v2_flash,
- &wg302v2_uart,
-+ &wg302v2_eth[0],
- };
-
- static void __init wg302v2_init(void)
+++ /dev/null
---- a/arch/arm/configs/ixp4xx_defconfig
-+++ b/arch/arm/configs/ixp4xx_defconfig
-@@ -155,6 +155,7 @@
- CONFIG_MACH_LOFT=y
- CONFIG_ARCH_ADI_COYOTE=y
- CONFIG_MACH_GATEWAY7001=y
-+CONFIG_MACH_WG302V1=y
- CONFIG_MACH_WG302V2=y
- CONFIG_ARCH_IXDP425=y
- CONFIG_MACH_IXDPG425=y
---- a/arch/arm/mach-ixp4xx/Kconfig
-+++ b/arch/arm/mach-ixp4xx/Kconfig
-@@ -49,6 +49,14 @@
- 7001 Access Point. For more information on this platform,
- see http://openwrt.org
-
-+config MACH_WG302V1
-+ bool "Netgear WG302 v1 / WAG302 v1"
-+ select PCI
-+ help
-+ Say 'Y' here if you want your kernel to support Netgear's
-+ WG302 v1 or WAG302 v1 Access Points. For more information
-+ on this platform, see http://openwrt.org
-+
- config MACH_WG302V2
- bool "Netgear WG302 v2 / WAG302 v2"
- select PCI
---- a/arch/arm/mach-ixp4xx/Makefile
-+++ b/arch/arm/mach-ixp4xx/Makefile
-@@ -14,6 +14,7 @@
- obj-pci-$(CONFIG_MACH_NAS100D) += nas100d-pci.o
- obj-pci-$(CONFIG_MACH_DSMG600) += dsmg600-pci.o
- obj-pci-$(CONFIG_MACH_GATEWAY7001) += gateway7001-pci.o
-+obj-pci-$(CONFIG_MACH_WG302V1) += wg302v1-pci.o
- obj-pci-$(CONFIG_MACH_WG302V2) += wg302v2-pci.o
- obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o
-
-@@ -28,6 +29,7 @@
- obj-$(CONFIG_MACH_NAS100D) += nas100d-setup.o
- obj-$(CONFIG_MACH_DSMG600) += dsmg600-setup.o
- obj-$(CONFIG_MACH_GATEWAY7001) += gateway7001-setup.o
-+obj-$(CONFIG_MACH_WG302V1) += wg302v1-setup.o
- obj-$(CONFIG_MACH_WG302V2) += wg302v2-setup.o
- obj-$(CONFIG_MACH_FSG) += fsg-setup.o
-
---- /dev/null
-+++ b/arch/arm/mach-ixp4xx/wg302v1-pci.c
-@@ -0,0 +1,64 @@
-+/*
-+ * arch/arch/mach-ixp4xx/wg302v1-pci.c
-+ *
-+ * PCI setup routines for the Netgear WG302 v1 and WAG302 v1
-+ *
-+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-+ *
-+ * based on coyote-pci.c:
-+ * Copyright (C) 2002 Jungo Software Technologies.
-+ * Copyright (C) 2003 MontaVista Software, Inc.
-+ *
-+ * Maintainer: Imre Kaloz <kaloz@openwrt.org>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/pci.h>
-+#include <linux/init.h>
-+#include <linux/irq.h>
-+
-+#include <asm/mach-types.h>
-+#include <asm/hardware.h>
-+
-+#include <asm/mach/pci.h>
-+
-+void __init wg302v1_pci_preinit(void)
-+{
-+ set_irq_type(IRQ_IXP4XX_GPIO8, IRQT_LOW);
-+ set_irq_type(IRQ_IXP4XX_GPIO10, IRQT_LOW);
-+
-+ ixp4xx_pci_preinit();
-+}
-+
-+static int __init wg302v1_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
-+{
-+ if (slot == 1)
-+ return IRQ_IXP4XX_GPIO8;
-+ else if (slot == 2)
-+ return IRQ_IXP4XX_GPIO10;
-+ else
-+ return -1;
-+}
-+
-+struct hw_pci wg302v1_pci __initdata = {
-+ .nr_controllers = 1,
-+ .preinit = wg302v1_pci_preinit,
-+ .swizzle = pci_std_swizzle,
-+ .setup = ixp4xx_setup,
-+ .scan = ixp4xx_scan_bus,
-+ .map_irq = wg302v1_map_irq,
-+};
-+
-+int __init wg302v1_pci_init(void)
-+{
-+ if (machine_is_wg302v1())
-+ pci_common_init(&wg302v1_pci);
-+ return 0;
-+}
-+
-+subsys_initcall(wg302v1_pci_init);
---- /dev/null
-+++ b/arch/arm/mach-ixp4xx/wg302v1-setup.c
-@@ -0,0 +1,142 @@
-+/*
-+ * arch/arm/mach-ixp4xx/wg302v1-setup.c
-+ *
-+ * Board setup for the Netgear WG302 v1 and WAG302 v1
-+ *
-+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-+ *
-+ * based on coyote-setup.c:
-+ * Copyright (C) 2003-2005 MontaVista Software, Inc.
-+ *
-+ * Author: Imre Kaloz <kaloz@openwrt.org>
-+ *
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/device.h>
-+#include <linux/serial.h>
-+#include <linux/tty.h>
-+#include <linux/serial_8250.h>
-+#include <linux/slab.h>
-+#include <linux/types.h>
-+#include <linux/memory.h>
-+
-+#include <asm/setup.h>
-+#include <asm/hardware.h>
-+#include <asm/irq.h>
-+#include <asm/mach-types.h>
-+#include <asm/mach/arch.h>
-+#include <asm/mach/flash.h>
-+
-+static struct flash_platform_data wg302v1_flash_data = {
-+ .map_name = "cfi_probe",
-+ .width = 2,
-+};
-+
-+static struct resource wg302v1_flash_resource = {
-+ .flags = IORESOURCE_MEM,
-+};
-+
-+static struct platform_device wg302v1_flash = {
-+ .name = "IXP4XX-Flash",
-+ .id = 0,
-+ .dev = {
-+ .platform_data = &wg302v1_flash_data,
-+ },
-+ .num_resources = 1,
-+ .resource = &wg302v1_flash_resource,
-+};
-+
-+static struct resource wg302v1_uart_resources[] = {
-+ {
-+ .start = IXP4XX_UART1_BASE_PHYS,
-+ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ {
-+ .start = IXP4XX_UART2_BASE_PHYS,
-+ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
-+ .flags = IORESOURCE_MEM,
-+ }
-+};
-+
-+static struct plat_serial8250_port wg302v1_uart_data[] = {
-+ {
-+ .mapbase = IXP4XX_UART1_BASE_PHYS,
-+ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
-+ .irq = IRQ_IXP4XX_UART1,
-+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
-+ .iotype = UPIO_MEM,
-+ .regshift = 2,
-+ .uartclk = IXP4XX_UART_XTAL,
-+ },
-+ {
-+ .mapbase = IXP4XX_UART2_BASE_PHYS,
-+ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
-+ .irq = IRQ_IXP4XX_UART2,
-+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
-+ .iotype = UPIO_MEM,
-+ .regshift = 2,
-+ .uartclk = IXP4XX_UART_XTAL,
-+ },
-+ { },
-+};
-+
-+static struct platform_device wg302v1_uart = {
-+ .name = "serial8250",
-+ .id = PLAT8250_DEV_PLATFORM,
-+ .dev = {
-+ .platform_data = wg302v1_uart_data,
-+ },
-+ .num_resources = 2,
-+ .resource = wg302v1_uart_resources,
-+};
-+
-+static struct eth_plat_info wg302v1_plat_eth[] = {
-+ {
-+ .phy = 30,
-+ .rxq = 3,
-+ .txreadyq = 20,
-+ }
-+};
-+
-+static struct platform_device wg302v1_eth[] = {
-+ {
-+ .name = "ixp4xx_eth",
-+ .id = IXP4XX_ETH_NPEB,
-+ .dev.platform_data = wg302v1_plat_eth,
-+ }
-+};
-+
-+static struct platform_device *wg302v1_devices[] __initdata = {
-+ &wg302v1_flash,
-+ &wg302v1_uart,
-+ &wg302v1_eth[0],
-+};
-+
-+static void __init wg302v1_init(void)
-+{
-+ ixp4xx_sys_init();
-+
-+ wg302v1_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
-+ wg302v1_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
-+
-+ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
-+ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
-+
-+ platform_add_devices(wg302v1_devices, ARRAY_SIZE(wg302v1_devices));
-+}
-+
-+#ifdef CONFIG_MACH_WG302V1
-+MACHINE_START(WG302V1, "Netgear WG302 v1 / WAG302 v1")
-+ /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
-+ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
-+ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
-+ .map_io = ixp4xx_map_io,
-+ .init_irq = ixp4xx_init_irq,
-+ .timer = &ixp4xx_timer,
-+ .boot_params = 0x0100,
-+ .init_machine = wg302v1_init,
-+MACHINE_END
-+#endif
+++ /dev/null
---- a/arch/arm/configs/ixp4xx_defconfig
-+++ b/arch/arm/configs/ixp4xx_defconfig
-@@ -157,6 +157,8 @@
- CONFIG_MACH_GATEWAY7001=y
- CONFIG_MACH_WG302V1=y
- CONFIG_MACH_WG302V2=y
-+CONFIG_MACH_PRONGHORN=y
-+CONFIG_MACH_PRONGHORNMETRO=y
- CONFIG_ARCH_IXDP425=y
- CONFIG_MACH_IXDPG425=y
- CONFIG_MACH_IXDP465=y
---- a/arch/arm/mach-ixp4xx/Kconfig
-+++ b/arch/arm/mach-ixp4xx/Kconfig
-@@ -65,6 +65,22 @@
- WG302 v2 or WAG302 v2 Access Points. For more information
- on this platform, see http://openwrt.org
-
-+config MACH_PRONGHORN
-+ bool "ADI Pronghorn series"
-+ select PCI
-+ help
-+ Say 'Y' here if you want your kernel to support the ADI
-+ Engineering Pronghorn series. For more
-+ information on this platform, see http://www.adiengineering.com
-+
-+#
-+# There're only minimal differences kernel-wise between the Pronghorn and
-+# Pronghorn Metro boards - they use different chip selects to drive the
-+# CF slot connected to the expansion bus, so we just enable them together.
-+#
-+config MACH_PRONGHORNMETRO
-+ def_bool MACH_PRONGHORN
-+
- config ARCH_IXDP425
- bool "IXDP425"
- help
---- a/arch/arm/mach-ixp4xx/Makefile
-+++ b/arch/arm/mach-ixp4xx/Makefile
-@@ -17,6 +17,7 @@
- obj-pci-$(CONFIG_MACH_WG302V1) += wg302v1-pci.o
- obj-pci-$(CONFIG_MACH_WG302V2) += wg302v2-pci.o
- obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o
-+obj-pci-$(CONFIG_MACH_PRONGHORN) += pronghorn-pci.o
-
- obj-y += common.o
-
-@@ -32,6 +33,7 @@
- obj-$(CONFIG_MACH_WG302V1) += wg302v1-setup.o
- obj-$(CONFIG_MACH_WG302V2) += wg302v2-setup.o
- obj-$(CONFIG_MACH_FSG) += fsg-setup.o
-+obj-$(CONFIG_MACH_PRONGHORN) += pronghorn-setup.o
-
- obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
- obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o
---- /dev/null
-+++ b/arch/arm/mach-ixp4xx/pronghorn-pci.c
-@@ -0,0 +1,70 @@
-+/*
-+ * arch/arch/mach-ixp4xx/pronghorn-pci.c
-+ *
-+ * PCI setup routines for ADI Engineering Pronghorn series
-+ *
-+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-+ *
-+ * based on coyote-pci.c:
-+ * Copyright (C) 2002 Jungo Software Technologies.
-+ * Copyright (C) 2003 MontaVista Softwrae, Inc.
-+ *
-+ * Maintainer: Imre Kaloz <kaloz@openwrt.org>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/pci.h>
-+#include <linux/init.h>
-+#include <linux/irq.h>
-+
-+#include <asm/mach-types.h>
-+#include <asm/hardware.h>
-+
-+#include <asm/mach/pci.h>
-+
-+void __init pronghorn_pci_preinit(void)
-+{
-+ set_irq_type(IRQ_IXP4XX_GPIO4, IRQT_LOW);
-+ set_irq_type(IRQ_IXP4XX_GPIO6, IRQT_LOW);
-+ set_irq_type(IRQ_IXP4XX_GPIO11, IRQT_LOW);
-+ set_irq_type(IRQ_IXP4XX_GPIO1, IRQT_LOW);
-+
-+ ixp4xx_pci_preinit();
-+}
-+
-+static int __init pronghorn_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
-+{
-+ if (slot == 13)
-+ return IRQ_IXP4XX_GPIO4;
-+ else if (slot == 14)
-+ return IRQ_IXP4XX_GPIO6;
-+ else if (slot == 15)
-+ return IRQ_IXP4XX_GPIO11;
-+ else if (slot == 16)
-+ return IRQ_IXP4XX_GPIO1;
-+ else
-+ return -1;
-+}
-+
-+struct hw_pci pronghorn_pci __initdata = {
-+ .nr_controllers = 1,
-+ .preinit = pronghorn_pci_preinit,
-+ .swizzle = pci_std_swizzle,
-+ .setup = ixp4xx_setup,
-+ .scan = ixp4xx_scan_bus,
-+ .map_irq = pronghorn_map_irq,
-+};
-+
-+int __init pronghorn_pci_init(void)
-+{
-+ if (machine_is_pronghorn() || machine_is_pronghorn_metro())
-+ pci_common_init(&pronghorn_pci);
-+ return 0;
-+}
-+
-+subsys_initcall(pronghorn_pci_init);
---- /dev/null
-+++ b/arch/arm/mach-ixp4xx/pronghorn-setup.c
-@@ -0,0 +1,245 @@
-+/*
-+ * arch/arm/mach-ixp4xx/pronghorn-setup.c
-+ *
-+ * Board setup for the ADI Engineering Pronghorn series
-+ *
-+ * Copyright (C) 2008 Imre Kaloz <Kaloz@openwrt.org>
-+ *
-+ * based on coyote-setup.c:
-+ * Copyright (C) 2003-2005 MontaVista Software, Inc.
-+ *
-+ * Author: Imre Kaloz <Kaloz@openwrt.org>
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/device.h>
-+#include <linux/serial.h>
-+#include <linux/tty.h>
-+#include <linux/serial_8250.h>
-+#include <linux/slab.h>
-+#include <linux/types.h>
-+#include <linux/memory.h>
-+#include <linux/i2c-gpio.h>
-+#include <linux/leds.h>
-+
-+#include <asm/setup.h>
-+#include <asm/hardware.h>
-+#include <asm/irq.h>
-+#include <asm/mach-types.h>
-+#include <asm/mach/arch.h>
-+#include <asm/mach/flash.h>
-+
-+static struct flash_platform_data pronghorn_flash_data = {
-+ .map_name = "cfi_probe",
-+ .width = 2,
-+};
-+
-+static struct resource pronghorn_flash_resource = {
-+ .flags = IORESOURCE_MEM,
-+};
-+
-+static struct platform_device pronghorn_flash = {
-+ .name = "IXP4XX-Flash",
-+ .id = 0,
-+ .dev = {
-+ .platform_data = &pronghorn_flash_data,
-+ },
-+ .num_resources = 1,
-+ .resource = &pronghorn_flash_resource,
-+};
-+
-+static struct resource pronghorn_uart_resources [] = {
-+ {
-+ .start = IXP4XX_UART1_BASE_PHYS,
-+ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
-+ .flags = IORESOURCE_MEM
-+ },
-+ {
-+ .start = IXP4XX_UART2_BASE_PHYS,
-+ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
-+ .flags = IORESOURCE_MEM
-+ }
-+};
-+
-+static struct plat_serial8250_port pronghorn_uart_data[] = {
-+ {
-+ .mapbase = IXP4XX_UART1_BASE_PHYS,
-+ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
-+ .irq = IRQ_IXP4XX_UART1,
-+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
-+ .iotype = UPIO_MEM,
-+ .regshift = 2,
-+ .uartclk = IXP4XX_UART_XTAL,
-+ },
-+ {
-+ .mapbase = IXP4XX_UART2_BASE_PHYS,
-+ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
-+ .irq = IRQ_IXP4XX_UART2,
-+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
-+ .iotype = UPIO_MEM,
-+ .regshift = 2,
-+ .uartclk = IXP4XX_UART_XTAL,
-+ },
-+ { },
-+};
-+
-+static struct platform_device pronghorn_uart = {
-+ .name = "serial8250",
-+ .id = PLAT8250_DEV_PLATFORM,
-+ .dev = {
-+ .platform_data = pronghorn_uart_data,
-+ },
-+ .num_resources = 2,
-+ .resource = pronghorn_uart_resources,
-+};
-+
-+static struct i2c_gpio_platform_data pronghorn_i2c_gpio_data = {
-+ .sda_pin = 9,
-+ .scl_pin = 10,
-+};
-+
-+static struct platform_device pronghorn_i2c_gpio = {
-+ .name = "i2c-gpio",
-+ .id = 0,
-+ .dev = {
-+ .platform_data = &pronghorn_i2c_gpio_data,
-+ },
-+};
-+
-+static struct gpio_led pronghorn_led_pin[] = {
-+ {
-+ .name = "pronghorn:green:status",
-+ .gpio = 7,
-+ }
-+};
-+
-+static struct gpio_led_platform_data pronghorn_led_data = {
-+ .num_leds = 1,
-+ .leds = pronghorn_led_pin,
-+};
-+
-+static struct platform_device pronghorn_led = {
-+ .name = "leds-gpio",
-+ .id = -1,
-+ .dev.platform_data = &pronghorn_led_data,
-+};
-+
-+static struct resource pronghorn_pata_resources[] = {
-+ {
-+ .flags = IORESOURCE_MEM
-+ },
-+ {
-+ .flags = IORESOURCE_MEM,
-+ },
-+ {
-+ .name = "intrq",
-+ .start = IRQ_IXP4XX_GPIO0,
-+ .end = IRQ_IXP4XX_GPIO0,
-+ .flags = IORESOURCE_IRQ,
-+ },
-+};
-+
-+static struct ixp4xx_pata_data pronghorn_pata_data = {
-+ .cs0_bits = 0xbfff0043,
-+ .cs1_bits = 0xbfff0043,
-+};
-+
-+static struct platform_device pronghorn_pata = {
-+ .name = "pata_ixp4xx_cf",
-+ .id = 0,
-+ .dev.platform_data = &pronghorn_pata_data,
-+ .num_resources = ARRAY_SIZE(pronghorn_pata_resources),
-+ .resource = pronghorn_pata_resources,
-+};
-+
-+static struct eth_plat_info pronghorn_plat_eth[] = {
-+ {
-+ .phy = 0,
-+ .rxq = 3,
-+ .txreadyq = 20,
-+ }, {
-+ .phy = 1,
-+ .rxq = 4,
-+ .txreadyq = 21,
-+ }
-+};
-+
-+static struct platform_device pronghorn_eth[] = {
-+ {
-+ .name = "ixp4xx_eth",
-+ .id = IXP4XX_ETH_NPEB,
-+ .dev.platform_data = pronghorn_plat_eth,
-+ }, {
-+ .name = "ixp4xx_eth",
-+ .id = IXP4XX_ETH_NPEC,
-+ .dev.platform_data = pronghorn_plat_eth + 1,
-+ }
-+};
-+
-+static struct platform_device *pronghorn_devices[] __initdata = {
-+ &pronghorn_flash,
-+ &pronghorn_uart,
-+ &pronghorn_led,
-+ &pronghorn_eth[0],
-+ &pronghorn_eth[1],
-+};
-+
-+static void __init pronghorn_init(void)
-+{
-+ ixp4xx_sys_init();
-+
-+ pronghorn_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
-+ pronghorn_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
-+
-+ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
-+ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
-+
-+ platform_add_devices(pronghorn_devices, ARRAY_SIZE(pronghorn_devices));
-+
-+ if (machine_is_pronghorn()) {
-+ pronghorn_pata_resources[0].start = IXP4XX_EXP_BUS_BASE(2);
-+ pronghorn_pata_resources[0].end = IXP4XX_EXP_BUS_END(2);
-+
-+ pronghorn_pata_resources[1].start = IXP4XX_EXP_BUS_BASE(3);
-+ pronghorn_pata_resources[1].end = IXP4XX_EXP_BUS_END(3);
-+
-+ pronghorn_pata_data.cs0_cfg = IXP4XX_EXP_CS2;
-+ pronghorn_pata_data.cs1_cfg = IXP4XX_EXP_CS3;
-+ } else {
-+ pronghorn_pata_resources[0].start = IXP4XX_EXP_BUS_BASE(3);
-+ pronghorn_pata_resources[0].end = IXP4XX_EXP_BUS_END(3);
-+
-+ pronghorn_pata_resources[1].start = IXP4XX_EXP_BUS_BASE(4);
-+ pronghorn_pata_resources[1].end = IXP4XX_EXP_BUS_END(4);
-+
-+ pronghorn_pata_data.cs0_cfg = IXP4XX_EXP_CS3;
-+ pronghorn_pata_data.cs1_cfg = IXP4XX_EXP_CS4;
-+
-+ platform_device_register(&pronghorn_i2c_gpio);
-+ }
-+
-+ platform_device_register(&pronghorn_pata);
-+}
-+
-+MACHINE_START(PRONGHORN, "ADI Engineering Pronghorn")
-+ /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
-+ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
-+ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
-+ .map_io = ixp4xx_map_io,
-+ .init_irq = ixp4xx_init_irq,
-+ .timer = &ixp4xx_timer,
-+ .boot_params = 0x0100,
-+ .init_machine = pronghorn_init,
-+MACHINE_END
-+
-+MACHINE_START(PRONGHORNMETRO, "ADI Engineering Pronghorn Metro")
-+ /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
-+ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
-+ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
-+ .map_io = ixp4xx_map_io,
-+ .init_irq = ixp4xx_init_irq,
-+ .timer = &ixp4xx_timer,
-+ .boot_params = 0x0100,
-+ .init_machine = pronghorn_init,
-+MACHINE_END
---- a/include/asm-arm/arch-ixp4xx/uncompress.h
-+++ b/include/asm-arm/arch-ixp4xx/uncompress.h
-@@ -41,7 +41,8 @@
- * Some boards are using UART2 as console
- */
- if (machine_is_adi_coyote() || machine_is_gtwx5715() ||
-- machine_is_gateway7001() || machine_is_wg302v2())
-+ machine_is_gateway7001() || machine_is_wg302v2() ||
-+ machine_is_pronghorn() || machine_is_pronghorn_metro())
- uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS;
- else
- uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS;
+++ /dev/null
---- a/arch/arm/mach-ixp4xx/pronghorn-setup.c
-+++ b/arch/arm/mach-ixp4xx/pronghorn-setup.c
-@@ -51,31 +51,31 @@
-
- static struct resource pronghorn_uart_resources [] = {
- {
-- .start = IXP4XX_UART1_BASE_PHYS,
-- .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
-+ .start = IXP4XX_UART2_BASE_PHYS,
-+ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
- .flags = IORESOURCE_MEM
- },
- {
-- .start = IXP4XX_UART2_BASE_PHYS,
-- .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
-+ .start = IXP4XX_UART1_BASE_PHYS,
-+ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
- .flags = IORESOURCE_MEM
- }
- };
-
- static struct plat_serial8250_port pronghorn_uart_data[] = {
- {
-- .mapbase = IXP4XX_UART1_BASE_PHYS,
-- .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
-- .irq = IRQ_IXP4XX_UART1,
-+ .mapbase = IXP4XX_UART2_BASE_PHYS,
-+ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
-+ .irq = IRQ_IXP4XX_UART2,
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
- .iotype = UPIO_MEM,
- .regshift = 2,
- .uartclk = IXP4XX_UART_XTAL,
- },
- {
-- .mapbase = IXP4XX_UART2_BASE_PHYS,
-- .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
-- .irq = IRQ_IXP4XX_UART2,
-+ .mapbase = IXP4XX_UART1_BASE_PHYS,
-+ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
-+ .irq = IRQ_IXP4XX_UART1,
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
- .iotype = UPIO_MEM,
- .regshift = 2,
+++ /dev/null
-From 60bdaaaf3446b4237566c6e04855186fc7bd766b Mon Sep 17 00:00:00 2001
-From: Imre Kaloz <kaloz@openwrt.org>
-Date: Sun, 13 Jul 2008 22:46:45 +0200
-Subject: [PATCH] Add support for the ADI Sidewinder
-
-Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
----
- arch/arm/mach-ixp4xx/Kconfig | 10 ++-
- arch/arm/mach-ixp4xx/Makefile | 2 +
- arch/arm/mach-ixp4xx/sidewinder-pci.c | 68 ++++++++++++++
- arch/arm/mach-ixp4xx/sidewinder-setup.c | 151 +++++++++++++++++++++++++++++++
- 4 files changed, 230 insertions(+), 1 deletions(-)
- create mode 100644 arch/arm/mach-ixp4xx/sidewinder-pci.c
- create mode 100644 arch/arm/mach-ixp4xx/sidewinder-setup.c
-
---- a/arch/arm/mach-ixp4xx/Kconfig
-+++ b/arch/arm/mach-ixp4xx/Kconfig
-@@ -81,6 +81,14 @@
- config MACH_PRONGHORNMETRO
- def_bool MACH_PRONGHORN
-
-+config MACH_SIDEWINDER
-+ bool "ADI Sidewinder"
-+ select PCI
-+ help
-+ Say 'Y' here if you want your kernel to support the ADI
-+ Engineering Sidewinder board. For more information on this
-+ platform, see http://www.adiengineering.com
-+
- config ARCH_IXDP425
- bool "IXDP425"
- help
-@@ -163,7 +171,7 @@
- #
- config CPU_IXP46X
- bool
-- depends on MACH_IXDP465
-+ depends on MACH_IXDP465 || MACH_SIDEWINDER
- default y
-
- config CPU_IXP43X
---- a/arch/arm/mach-ixp4xx/Makefile
-+++ b/arch/arm/mach-ixp4xx/Makefile
-@@ -18,6 +18,7 @@
- obj-pci-$(CONFIG_MACH_WG302V2) += wg302v2-pci.o
- obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o
- obj-pci-$(CONFIG_MACH_PRONGHORN) += pronghorn-pci.o
-+obj-pci-$(CONFIG_MACH_SIDEWINDER) += sidewinder-pci.o
-
- obj-y += common.o
-
-@@ -34,6 +35,7 @@
- obj-$(CONFIG_MACH_WG302V2) += wg302v2-setup.o
- obj-$(CONFIG_MACH_FSG) += fsg-setup.o
- obj-$(CONFIG_MACH_PRONGHORN) += pronghorn-setup.o
-+obj-$(CONFIG_MACH_SIDEWINDER) += sidewinder-setup.o
-
- obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
- obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o
---- /dev/null
-+++ b/arch/arm/mach-ixp4xx/sidewinder-pci.c
-@@ -0,0 +1,68 @@
-+/*
-+ * arch/arch/mach-ixp4xx/pronghornmetro-pci.c
-+ *
-+ * PCI setup routines for ADI Engineering Sidewinder
-+ *
-+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-+ *
-+ * based on coyote-pci.c:
-+ * Copyright (C) 2002 Jungo Software Technologies.
-+ * Copyright (C) 2003 MontaVista Softwrae, Inc.
-+ *
-+ * Maintainer: Imre Kaloz <kaloz@openwrt.org>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/pci.h>
-+#include <linux/init.h>
-+#include <linux/irq.h>
-+
-+#include <asm/mach-types.h>
-+#include <asm/hardware.h>
-+#include <asm/irq.h>
-+
-+#include <asm/mach/pci.h>
-+
-+void __init sidewinder_pci_preinit(void)
-+{
-+ set_irq_type(IRQ_IXP4XX_GPIO11, IRQT_LOW);
-+ set_irq_type(IRQ_IXP4XX_GPIO10, IRQT_LOW);
-+ set_irq_type(IRQ_IXP4XX_GPIO9, IRQT_LOW);
-+
-+ ixp4xx_pci_preinit();
-+}
-+
-+static int __init sidewinder_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
-+{
-+ if (slot == 1)
-+ return IRQ_IXP4XX_GPIO11;
-+ else if (slot == 2)
-+ return IRQ_IXP4XX_GPIO10;
-+ else if (slot == 3)
-+ return IRQ_IXP4XX_GPIO9;
-+ else
-+ return -1;
-+}
-+
-+struct hw_pci sidewinder_pci __initdata = {
-+ .nr_controllers = 1,
-+ .preinit = sidewinder_pci_preinit,
-+ .swizzle = pci_std_swizzle,
-+ .setup = ixp4xx_setup,
-+ .scan = ixp4xx_scan_bus,
-+ .map_irq = sidewinder_map_irq,
-+};
-+
-+int __init sidewinder_pci_init(void)
-+{
-+ if (machine_is_sidewinder())
-+ pci_common_init(&sidewinder_pci);
-+ return 0;
-+}
-+
-+subsys_initcall(sidewinder_pci_init);
---- /dev/null
-+++ b/arch/arm/mach-ixp4xx/sidewinder-setup.c
-@@ -0,0 +1,149 @@
-+/*
-+ * arch/arm/mach-ixp4xx/sidewinder-setup.c
-+ *
-+ * Board setup for the ADI Engineering Sidewinder
-+ *
-+ * Copyright (C) 2008 Imre Kaloz <Kaloz@openwrt.org>
-+ *
-+ * based on coyote-setup.c:
-+ * Copyright (C) 2003-2005 MontaVista Software, Inc.
-+ *
-+ * Author: Imre Kaloz <Kaloz@openwrt.org>
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/serial.h>
-+#include <linux/serial_8250.h>
-+
-+#include <asm/mach-types.h>
-+#include <asm/mach/arch.h>
-+#include <asm/mach/flash.h>
-+
-+static struct flash_platform_data sidewinder_flash_data = {
-+ .map_name = "cfi_probe",
-+ .width = 2,
-+};
-+
-+static struct resource sidewinder_flash_resource = {
-+ .flags = IORESOURCE_MEM,
-+};
-+
-+static struct platform_device sidewinder_flash = {
-+ .name = "IXP4XX-Flash",
-+ .id = 0,
-+ .dev = {
-+ .platform_data = &sidewinder_flash_data,
-+ },
-+ .num_resources = 1,
-+ .resource = &sidewinder_flash_resource,
-+};
-+
-+static struct resource sidewinder_uart_resources[] = {
-+ {
-+ .start = IXP4XX_UART1_BASE_PHYS,
-+ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ {
-+ .start = IXP4XX_UART2_BASE_PHYS,
-+ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
-+ .flags = IORESOURCE_MEM,
-+ }
-+};
-+
-+static struct plat_serial8250_port sidewinder_uart_data[] = {
-+ {
-+ .mapbase = IXP4XX_UART1_BASE_PHYS,
-+ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
-+ .irq = IRQ_IXP4XX_UART1,
-+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
-+ .iotype = UPIO_MEM,
-+ .regshift = 2,
-+ .uartclk = IXP4XX_UART_XTAL,
-+ },
-+ {
-+ .mapbase = IXP4XX_UART2_BASE_PHYS,
-+ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
-+ .irq = IRQ_IXP4XX_UART2,
-+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
-+ .iotype = UPIO_MEM,
-+ .regshift = 2,
-+ .uartclk = IXP4XX_UART_XTAL,
-+ },
-+ { },
-+};
-+
-+static struct platform_device sidewinder_uart = {
-+ .name = "serial8250",
-+ .id = PLAT8250_DEV_PLATFORM,
-+ .dev = {
-+ .platform_data = sidewinder_uart_data,
-+ },
-+ .num_resources = ARRAY_SIZE(sidewinder_uart_resources),
-+ .resource = sidewinder_uart_resources,
-+};
-+
-+static struct eth_plat_info sidewinder_plat_eth[] = {
-+ {
-+ .phy = 5,
-+ .rxq = 3,
-+ .txreadyq = 20,
-+ }, {
-+ .phy = IXP4XX_ETH_PHY_MAX_ADDR,
-+ .phy_mask = 0x1e,
-+ .rxq = 4,
-+ .txreadyq = 21,
-+ }, {
-+ .phy = 31,
-+ .rxq = 2,
-+ .txreadyq = 19,
-+ }
-+};
-+
-+static struct platform_device sidewinder_eth[] = {
-+ {
-+ .name = "ixp4xx_eth",
-+ .id = IXP4XX_ETH_NPEB,
-+ .dev.platform_data = sidewinder_plat_eth,
-+ }, {
-+ .name = "ixp4xx_eth",
-+ .id = IXP4XX_ETH_NPEC,
-+ .dev.platform_data = sidewinder_plat_eth + 1,
-+ }, {
-+ .name = "ixp4xx_eth",
-+ .id = IXP4XX_ETH_NPEA,
-+ .dev.platform_data = sidewinder_plat_eth + 2,
-+ }
-+};
-+
-+static struct platform_device *sidewinder_devices[] __initdata = {
-+ &sidewinder_flash,
-+ &sidewinder_uart,
-+ &sidewinder_eth[0],
-+ &sidewinder_eth[1],
-+ &sidewinder_eth[2],
-+};
-+
-+static void __init sidewinder_init(void)
-+{
-+ ixp4xx_sys_init();
-+
-+ sidewinder_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
-+ sidewinder_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_64M - 1;
-+
-+ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
-+ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
-+
-+ platform_add_devices(sidewinder_devices, ARRAY_SIZE(sidewinder_devices));
-+}
-+
-+MACHINE_START(SIDEWINDER, "ADI Engineering Sidewinder")
-+ /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
-+ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
-+ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
-+ .map_io = ixp4xx_map_io,
-+ .init_irq = ixp4xx_init_irq,
-+ .timer = &ixp4xx_timer,
-+ .boot_params = 0x0100,
-+ .init_machine = sidewinder_init,
-+MACHINE_END
+++ /dev/null
---- a/drivers/mtd/redboot.c
-+++ b/drivers/mtd/redboot.c
-@@ -15,6 +15,8 @@
-
- #define BOARD_CONFIG_PART "boardconfig"
-
-+#include <asm/mach-types.h>
-+
- struct fis_image_desc {
- unsigned char name[16]; // Null terminated name
- uint32_t flash_base; // Address within FLASH of image
-@@ -32,7 +34,8 @@
- struct fis_list *next;
- };
-
--static int directory = CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK;
-+int directory = CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK;
-+
- module_param(directory, int, 0);
-
- static inline int redboot_checksum(struct fis_image_desc *img)
-@@ -61,6 +64,8 @@
- #ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED
- static char nullstring[] = "unallocated";
- #endif
-+ if (machine_is_sidewinder())
-+ directory = -5;
-
- if ( directory < 0 ) {
- offset = master->size + directory * master->erasesize;
+++ /dev/null
-From 24025a2dcf1248079dd3019fac6ed955252d277f Mon Sep 17 00:00:00 2001
-From: Imre Kaloz <kaloz@openwrt.org>
-Date: Mon, 14 Jul 2008 21:56:34 +0200
-Subject: [PATCH] Add support for the Compex WP18 / NP18A boards
-
-Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
----
- arch/arm/mach-ixp4xx/Kconfig | 8 ++
- arch/arm/mach-ixp4xx/Makefile | 2 +
- arch/arm/mach-ixp4xx/compex-setup.c | 136 +++++++++++++++++++++++++++++++++++
- arch/arm/mach-ixp4xx/ixdp425-pci.c | 3 +-
- arch/arm/tools/mach-types | 2 +-
- 5 files changed, 149 insertions(+), 2 deletions(-)
- create mode 100644 arch/arm/mach-ixp4xx/compex-setup.c
-
---- a/arch/arm/mach-ixp4xx/Kconfig
-+++ b/arch/arm/mach-ixp4xx/Kconfig
-@@ -89,6 +89,14 @@
- Engineering Sidewinder board. For more information on this
- platform, see http://www.adiengineering.com
-
-+config MACH_COMPEX
-+ bool "Compex WP18 / NP18A"
-+ select PCI
-+ help
-+ Say 'Y' here if you want your kernel to support Compex'
-+ WP18 or NP18A boards. For more information on this
-+ platform, see http://www.compex.com.sg/home/OEM/product_ap.htm
-+
- config ARCH_IXDP425
- bool "IXDP425"
- help
---- a/arch/arm/mach-ixp4xx/Makefile
-+++ b/arch/arm/mach-ixp4xx/Makefile
-@@ -19,6 +19,7 @@
- obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o
- obj-pci-$(CONFIG_MACH_PRONGHORN) += pronghorn-pci.o
- obj-pci-$(CONFIG_MACH_SIDEWINDER) += sidewinder-pci.o
-+obj-pci-$(CONFIG_MACH_COMPEX) += ixdp425-pci.o
-
- obj-y += common.o
-
-@@ -36,6 +37,7 @@
- obj-$(CONFIG_MACH_FSG) += fsg-setup.o
- obj-$(CONFIG_MACH_PRONGHORN) += pronghorn-setup.o
- obj-$(CONFIG_MACH_SIDEWINDER) += sidewinder-setup.o
-+obj-$(CONFIG_MACH_COMPEX) += compex-setup.o
-
- obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
- obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o
---- /dev/null
-+++ b/arch/arm/mach-ixp4xx/compex-setup.c
-@@ -0,0 +1,136 @@
-+/*
-+ * arch/arm/mach-ixp4xx/compex-setup.c
-+ *
-+ * Compex WP18 / NP18A board-setup
-+ *
-+ * Copyright (C) 2008 Imre Kaloz <Kaloz@openwrt.org>
-+ *
-+ * based on coyote-setup.c:
-+ * Copyright (C) 2003-2005 MontaVista Software, Inc.
-+ *
-+ * Author: Imre Kaloz <Kaloz@openwrt.org>
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/serial.h>
-+#include <linux/serial_8250.h>
-+
-+#include <asm/mach-types.h>
-+#include <asm/mach/arch.h>
-+#include <asm/mach/flash.h>
-+
-+static struct flash_platform_data compex_flash_data = {
-+ .map_name = "cfi_probe",
-+ .width = 2,
-+};
-+
-+static struct resource compex_flash_resource = {
-+ .flags = IORESOURCE_MEM,
-+};
-+
-+static struct platform_device compex_flash = {
-+ .name = "IXP4XX-Flash",
-+ .id = 0,
-+ .dev = {
-+ .platform_data = &compex_flash_data,
-+ },
-+ .num_resources = 1,
-+ .resource = &compex_flash_resource,
-+};
-+
-+static struct resource compex_uart_resources[] = {
-+ {
-+ .start = IXP4XX_UART1_BASE_PHYS,
-+ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
-+ .flags = IORESOURCE_MEM
-+ },
-+ {
-+ .start = IXP4XX_UART2_BASE_PHYS,
-+ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
-+ .flags = IORESOURCE_MEM
-+ }
-+};
-+
-+static struct plat_serial8250_port compex_uart_data[] = {
-+ {
-+ .mapbase = IXP4XX_UART1_BASE_PHYS,
-+ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
-+ .irq = IRQ_IXP4XX_UART1,
-+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
-+ .iotype = UPIO_MEM,
-+ .regshift = 2,
-+ .uartclk = IXP4XX_UART_XTAL,
-+ },
-+ {
-+ .mapbase = IXP4XX_UART2_BASE_PHYS,
-+ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
-+ .irq = IRQ_IXP4XX_UART2,
-+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
-+ .iotype = UPIO_MEM,
-+ .regshift = 2,
-+ .uartclk = IXP4XX_UART_XTAL,
-+ },
-+ { },
-+};
-+
-+static struct platform_device compex_uart = {
-+ .name = "serial8250",
-+ .id = PLAT8250_DEV_PLATFORM,
-+ .dev.platform_data = compex_uart_data,
-+ .num_resources = 2,
-+ .resource = compex_uart_resources,
-+};
-+
-+static struct eth_plat_info compex_plat_eth[] = {
-+ {
-+ .phy = IXP4XX_ETH_PHY_MAX_ADDR,
-+ .phy_mask = 0xf0000,
-+ .rxq = 3,
-+ .txreadyq = 20,
-+ }, {
-+ .phy = 3,
-+ .rxq = 4,
-+ .txreadyq = 21,
-+ }
-+};
-+
-+static struct platform_device compex_eth[] = {
-+ {
-+ .name = "ixp4xx_eth",
-+ .id = IXP4XX_ETH_NPEB,
-+ .dev.platform_data = compex_plat_eth,
-+ }, {
-+ .name = "ixp4xx_eth",
-+ .id = IXP4XX_ETH_NPEC,
-+ .dev.platform_data = compex_plat_eth + 1,
-+ }
-+};
-+
-+static struct platform_device *compex_devices[] __initdata = {
-+ &compex_flash,
-+ &compex_uart,
-+ &compex_eth[0],
-+ &compex_eth[1],
-+};
-+
-+static void __init compex_init(void)
-+{
-+ ixp4xx_sys_init();
-+
-+ compex_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
-+ compex_flash_resource.end =
-+ IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
-+
-+ platform_add_devices(compex_devices, ARRAY_SIZE(compex_devices));
-+}
-+
-+MACHINE_START(COMPEX, "Compex WP18 / NP18A")
-+ /* Maintainer: Imre Kaloz <Kaloz@openwrt.org> */
-+ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
-+ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
-+ .map_io = ixp4xx_map_io,
-+ .init_irq = ixp4xx_init_irq,
-+ .timer = &ixp4xx_timer,
-+ .boot_params = 0x0100,
-+ .init_machine = compex_init,
-+MACHINE_END
---- a/arch/arm/mach-ixp4xx/ixdp425-pci.c
-+++ b/arch/arm/mach-ixp4xx/ixdp425-pci.c
-@@ -66,7 +66,8 @@
- int __init ixdp425_pci_init(void)
- {
- if (machine_is_ixdp425() || machine_is_ixcdp1100() ||
-- machine_is_ixdp465() || machine_is_kixrp435())
-+ machine_is_ixdp465() || machine_is_kixrp435() ||
-+ machine_is_compex())
- pci_common_init(&ixdp425_pci);
- return 0;
- }
---- a/arch/arm/tools/mach-types
-+++ b/arch/arm/tools/mach-types
-@@ -1276,7 +1276,7 @@
- smdk6400 MACH_SMDK6400 SMDK6400 1270
- nokia_n800 MACH_NOKIA_N800 NOKIA_N800 1271
- greenphone MACH_GREENPHONE GREENPHONE 1272
--compex42x MACH_COMPEXWP18 COMPEXWP18 1273
-+compex MACH_COMPEX COMPEX 1273
- xmate MACH_XMATE XMATE 1274
- energizer MACH_ENERGIZER ENERGIZER 1275
- ime1 MACH_IME1 IME1 1276
+++ /dev/null
---- a/arch/arm/mach-ixp4xx/Kconfig
-+++ b/arch/arm/mach-ixp4xx/Kconfig
-@@ -97,6 +97,14 @@
- WP18 or NP18A boards. For more information on this
- platform, see http://www.compex.com.sg/home/OEM/product_ap.htm
-
-+config MACH_WRT300NV2
-+ bool "Linksys WRT300N v2"
-+ select PCI
-+ help
-+ Say 'Y' here if you want your kernel to support Linksys'
-+ WRT300N v2 router. For more information on this
-+ platform, see http://openwrt.org
-+
- config ARCH_IXDP425
- bool "IXDP425"
- help
---- a/arch/arm/mach-ixp4xx/Makefile
-+++ b/arch/arm/mach-ixp4xx/Makefile
-@@ -20,6 +20,7 @@
- obj-pci-$(CONFIG_MACH_PRONGHORN) += pronghorn-pci.o
- obj-pci-$(CONFIG_MACH_SIDEWINDER) += sidewinder-pci.o
- obj-pci-$(CONFIG_MACH_COMPEX) += ixdp425-pci.o
-+obj-pci-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-pci.o
-
- obj-y += common.o
-
-@@ -38,6 +39,7 @@
- obj-$(CONFIG_MACH_PRONGHORN) += pronghorn-setup.o
- obj-$(CONFIG_MACH_SIDEWINDER) += sidewinder-setup.o
- obj-$(CONFIG_MACH_COMPEX) += compex-setup.o
-+obj-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-setup.o
-
- obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
- obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o
---- /dev/null
-+++ b/arch/arm/mach-ixp4xx/wrt300nv2-pci.c
-@@ -0,0 +1,65 @@
-+/*
-+ * arch/arch/mach-ixp4xx/wrt300nv2-pci.c
-+ *
-+ * PCI setup routines for Linksys WRT300N v2
-+ *
-+ * Copyright (C) 2007 Imre Kaloz <kaloz@openwrt.org>
-+ *
-+ * based on coyote-pci.c:
-+ * Copyright (C) 2002 Jungo Software Technologies.
-+ * Copyright (C) 2003 MontaVista Softwrae, Inc.
-+ *
-+ * Maintainer: Imre Kaloz <kaloz@openwrt.org>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/pci.h>
-+#include <linux/init.h>
-+#include <linux/irq.h>
-+
-+#include <asm/mach-types.h>
-+#include <asm/hardware.h>
-+#include <asm/irq.h>
-+
-+#include <asm/mach/pci.h>
-+
-+extern void ixp4xx_pci_preinit(void);
-+extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
-+extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
-+
-+void __init wrt300nv2_pci_preinit(void)
-+{
-+ set_irq_type(IRQ_IXP4XX_GPIO8, IRQT_LOW);
-+
-+ ixp4xx_pci_preinit();
-+}
-+
-+static int __init wrt300nv2_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
-+{
-+ if (slot == 1)
-+ return IRQ_IXP4XX_GPIO8;
-+ else return -1;
-+}
-+
-+struct hw_pci wrt300nv2_pci __initdata = {
-+ .nr_controllers = 1,
-+ .preinit = wrt300nv2_pci_preinit,
-+ .swizzle = pci_std_swizzle,
-+ .setup = ixp4xx_setup,
-+ .scan = ixp4xx_scan_bus,
-+ .map_irq = wrt300nv2_map_irq,
-+};
-+
-+int __init wrt300nv2_pci_init(void)
-+{
-+ if (machine_is_wrt300nv2())
-+ pci_common_init(&wrt300nv2_pci);
-+ return 0;
-+}
-+
-+subsys_initcall(wrt300nv2_pci_init);
---- /dev/null
-+++ b/arch/arm/mach-ixp4xx/wrt300nv2-setup.c
-@@ -0,0 +1,108 @@
-+/*
-+ * arch/arm/mach-ixp4xx/wrt300nv2-setup.c
-+ *
-+ * Board setup for the Linksys WRT300N v2
-+ *
-+ * Copyright (C) 2007 Imre Kaloz <Kaloz@openwrt.org>
-+ *
-+ * based on coyote-setup.c:
-+ * Copyright (C) 2003-2005 MontaVista Software, Inc.
-+ *
-+ * Author: Imre Kaloz <Kaloz@openwrt.org>
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/device.h>
-+#include <linux/serial.h>
-+#include <linux/tty.h>
-+#include <linux/serial_8250.h>
-+#include <linux/slab.h>
-+
-+#include <asm/types.h>
-+#include <asm/setup.h>
-+#include <asm/memory.h>
-+#include <asm/hardware.h>
-+#include <asm/irq.h>
-+#include <asm/mach-types.h>
-+#include <asm/mach/arch.h>
-+#include <asm/mach/flash.h>
-+
-+static struct flash_platform_data wrt300nv2_flash_data = {
-+ .map_name = "cfi_probe",
-+ .width = 2,
-+};
-+
-+static struct resource wrt300nv2_flash_resource = {
-+ .flags = IORESOURCE_MEM,
-+};
-+
-+static struct platform_device wrt300nv2_flash = {
-+ .name = "IXP4XX-Flash",
-+ .id = 0,
-+ .dev = {
-+ .platform_data = &wrt300nv2_flash_data,
-+ },
-+ .num_resources = 1,
-+ .resource = &wrt300nv2_flash_resource,
-+};
-+
-+static struct resource wrt300nv2_uart_resource = {
-+ .start = IXP4XX_UART2_BASE_PHYS,
-+ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
-+ .flags = IORESOURCE_MEM,
-+};
-+
-+static struct plat_serial8250_port wrt300nv2_uart_data[] = {
-+ {
-+ .mapbase = IXP4XX_UART2_BASE_PHYS,
-+ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
-+ .irq = IRQ_IXP4XX_UART2,
-+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
-+ .iotype = UPIO_MEM,
-+ .regshift = 2,
-+ .uartclk = IXP4XX_UART_XTAL,
-+ },
-+ { },
-+};
-+
-+static struct platform_device wrt300nv2_uart = {
-+ .name = "serial8250",
-+ .id = PLAT8250_DEV_PLATFORM,
-+ .dev = {
-+ .platform_data = wrt300nv2_uart_data,
-+ },
-+ .num_resources = 1,
-+ .resource = &wrt300nv2_uart_resource,
-+};
-+
-+static struct platform_device *wrt300nv2_devices[] __initdata = {
-+ &wrt300nv2_flash,
-+ &wrt300nv2_uart
-+};
-+
-+static void __init wrt300nv2_init(void)
-+{
-+ ixp4xx_sys_init();
-+
-+ wrt300nv2_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
-+ wrt300nv2_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
-+
-+ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
-+ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
-+
-+ platform_add_devices(wrt300nv2_devices, ARRAY_SIZE(wrt300nv2_devices));
-+}
-+
-+#ifdef CONFIG_MACH_WRT300NV2
-+MACHINE_START(WRT300NV2, "Linksys WRT300N v2")
-+ /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
-+ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
-+ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
-+ .map_io = ixp4xx_map_io,
-+ .init_irq = ixp4xx_init_irq,
-+ .timer = &ixp4xx_timer,
-+ .boot_params = 0x0100,
-+ .init_machine = wrt300nv2_init,
-+MACHINE_END
-+#endif
---- a/include/asm-arm/arch-ixp4xx/uncompress.h
-+++ b/include/asm-arm/arch-ixp4xx/uncompress.h
-@@ -42,7 +42,7 @@
- */
- if (machine_is_adi_coyote() || machine_is_gtwx5715() ||
- machine_is_gateway7001() || machine_is_wg302v2() ||
-- machine_is_pronghorn() || machine_is_pronghorn_metro())
-+ machine_is_pronghorn() || machine_is_pronghorn_metro() || machine_is_wrt300nv2())
- uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS;
- else
- uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS;
+++ /dev/null
---- a/arch/arm/mach-ixp4xx/wrt300nv2-setup.c
-+++ b/arch/arm/mach-ixp4xx/wrt300nv2-setup.c
-@@ -76,9 +76,36 @@
- .resource = &wrt300nv2_uart_resource,
- };
-
-+/* Built-in 10/100 Ethernet MAC interfaces */
-+static struct eth_plat_info wrt300nv2_plat_eth[] = {
-+ {
-+ .phy = -1,
-+ .rxq = 3,
-+ .txreadyq = 20,
-+ }, {
-+ .phy = 1,
-+ .rxq = 4,
-+ .txreadyq = 21,
-+ }
-+};
-+
-+static struct platform_device wrt300nv2_eth[] = {
-+ {
-+ .name = "ixp4xx_eth",
-+ .id = IXP4XX_ETH_NPEB,
-+ .dev.platform_data = wrt300nv2_plat_eth,
-+ }, {
-+ .name = "ixp4xx_eth",
-+ .id = IXP4XX_ETH_NPEC,
-+ .dev.platform_data = wrt300nv2_plat_eth + 1,
-+ }
-+};
-+
- static struct platform_device *wrt300nv2_devices[] __initdata = {
- &wrt300nv2_flash,
-- &wrt300nv2_uart
-+ &wrt300nv2_uart,
-+ &wrt300nv2_eth[0],
-+ &wrt300nv2_eth[1],
- };
-
- static void __init wrt300nv2_init(void)
+++ /dev/null
---- /dev/null
-+++ b/arch/arm/mach-ixp4xx/ap1000-setup.c
-@@ -0,0 +1,151 @@
-+/*
-+ * arch/arm/mach-ixp4xx/ap1000-setup.c
-+ *
-+ * Lanready AP-1000
-+ *
-+ * Copyright (C) 2007 Imre Kaloz <Kaloz@openwrt.org>
-+ *
-+ * based on ixdp425-setup.c:
-+ * Copyright (C) 2003-2005 MontaVista Software, Inc.
-+ *
-+ * Author: Imre Kaloz <Kaloz@openwrt.org>
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/device.h>
-+#include <linux/serial.h>
-+#include <linux/tty.h>
-+#include <linux/serial_8250.h>
-+#include <linux/slab.h>
-+
-+#include <asm/types.h>
-+#include <asm/setup.h>
-+#include <asm/memory.h>
-+#include <asm/hardware.h>
-+#include <asm/mach-types.h>
-+#include <asm/irq.h>
-+#include <asm/mach/arch.h>
-+#include <asm/mach/flash.h>
-+
-+static struct flash_platform_data ap1000_flash_data = {
-+ .map_name = "cfi_probe",
-+ .width = 2,
-+};
-+
-+static struct resource ap1000_flash_resource = {
-+ .flags = IORESOURCE_MEM,
-+};
-+
-+static struct platform_device ap1000_flash = {
-+ .name = "IXP4XX-Flash",
-+ .id = 0,
-+ .dev = {
-+ .platform_data = &ap1000_flash_data,
-+ },
-+ .num_resources = 1,
-+ .resource = &ap1000_flash_resource,
-+};
-+
-+static struct resource ap1000_uart_resources[] = {
-+ {
-+ .start = IXP4XX_UART1_BASE_PHYS,
-+ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
-+ .flags = IORESOURCE_MEM
-+ },
-+ {
-+ .start = IXP4XX_UART2_BASE_PHYS,
-+ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
-+ .flags = IORESOURCE_MEM
-+ }
-+};
-+
-+static struct plat_serial8250_port ap1000_uart_data[] = {
-+ {
-+ .mapbase = IXP4XX_UART1_BASE_PHYS,
-+ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
-+ .irq = IRQ_IXP4XX_UART1,
-+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
-+ .iotype = UPIO_MEM,
-+ .regshift = 2,
-+ .uartclk = IXP4XX_UART_XTAL,
-+ },
-+ {
-+ .mapbase = IXP4XX_UART2_BASE_PHYS,
-+ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
-+ .irq = IRQ_IXP4XX_UART2,
-+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
-+ .iotype = UPIO_MEM,
-+ .regshift = 2,
-+ .uartclk = IXP4XX_UART_XTAL,
-+ },
-+ { },
-+};
-+
-+static struct platform_device ap1000_uart = {
-+ .name = "serial8250",
-+ .id = PLAT8250_DEV_PLATFORM,
-+ .dev.platform_data = ap1000_uart_data,
-+ .num_resources = 2,
-+ .resource = ap1000_uart_resources
-+};
-+
-+static struct platform_device *ap1000_devices[] __initdata = {
-+ &ap1000_flash,
-+ &ap1000_uart
-+};
-+
-+static char ap1000_mem_fixup[] __initdata = "mem=64M ";
-+
-+static void __init ap1000_fixup(struct machine_desc *desc,
-+ struct tag *tags, char **cmdline, struct meminfo *mi)
-+
-+{
-+ struct tag *t = tags;
-+ char *p = *cmdline;
-+
-+ /* Find the end of the tags table, taking note of any cmdline tag. */
-+ for (; t->hdr.size; t = tag_next(t)) {
-+ if (t->hdr.tag == ATAG_CMDLINE) {
-+ p = t->u.cmdline.cmdline;
-+ }
-+ }
-+
-+ /* Overwrite the end of the table with a new cmdline tag. */
-+ t->hdr.tag = ATAG_CMDLINE;
-+ t->hdr.size = (sizeof (struct tag_header) +
-+ strlen(ap1000_mem_fixup) + strlen(p) + 1 + 4) >> 2;
-+ strlcpy(t->u.cmdline.cmdline, ap1000_mem_fixup, COMMAND_LINE_SIZE);
-+ strlcpy(t->u.cmdline.cmdline + strlen(ap1000_mem_fixup), p,
-+ COMMAND_LINE_SIZE - strlen(ap1000_mem_fixup));
-+
-+ /* Terminate the table. */
-+ t = tag_next(t);
-+ t->hdr.tag = ATAG_NONE;
-+ t->hdr.size = 0;
-+}
-+
-+static void __init ap1000_init(void)
-+{
-+ ixp4xx_sys_init();
-+
-+ ap1000_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
-+ ap1000_flash_resource.end =
-+ IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
-+
-+ platform_add_devices(ap1000_devices, ARRAY_SIZE(ap1000_devices));
-+}
-+
-+#ifdef CONFIG_MACH_AP1000
-+MACHINE_START(AP1000, "Lanready AP-1000")
-+ /* Maintainer: Imre Kaloz <Kaloz@openwrt.org> */
-+ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
-+ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
-+ .fixup = ap1000_fixup,
-+ .map_io = ixp4xx_map_io,
-+ .init_irq = ixp4xx_init_irq,
-+ .timer = &ixp4xx_timer,
-+ .boot_params = 0x0100,
-+ .init_machine = ap1000_init,
-+MACHINE_END
-+#endif
---- a/arch/arm/mach-ixp4xx/ixdp425-pci.c
-+++ b/arch/arm/mach-ixp4xx/ixdp425-pci.c
-@@ -67,7 +67,7 @@
- {
- if (machine_is_ixdp425() || machine_is_ixcdp1100() ||
- machine_is_ixdp465() || machine_is_kixrp435() ||
-- machine_is_compex())
-+ machine_is_compex() || machine_is_ap1000())
- pci_common_init(&ixdp425_pci);
- return 0;
- }
---- a/arch/arm/mach-ixp4xx/Kconfig
-+++ b/arch/arm/mach-ixp4xx/Kconfig
-@@ -105,6 +105,14 @@
- WRT300N v2 router. For more information on this
- platform, see http://openwrt.org
-
-+config MACH_AP1000
-+ bool "Lanready AP-1000"
-+ select PCI
-+ help
-+ Say 'Y' here if you want your kernel to support Lanready's
-+ AP1000 board. For more information on this
-+ platform, see http://openwrt.org
-+
- config ARCH_IXDP425
- bool "IXDP425"
- help
---- a/arch/arm/mach-ixp4xx/Makefile
-+++ b/arch/arm/mach-ixp4xx/Makefile
-@@ -21,6 +21,7 @@
- obj-pci-$(CONFIG_MACH_SIDEWINDER) += sidewinder-pci.o
- obj-pci-$(CONFIG_MACH_COMPEX) += ixdp425-pci.o
- obj-pci-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-pci.o
-+obj-pci-$(CONFIG_MACH_AP1000) += ixdp425-pci.o
-
- obj-y += common.o
-
-@@ -40,6 +41,7 @@
- obj-$(CONFIG_MACH_SIDEWINDER) += sidewinder-setup.o
- obj-$(CONFIG_MACH_COMPEX) += compex-setup.o
- obj-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-setup.o
-+obj-$(CONFIG_MACH_AP1000) += ap1000-setup.o
-
- obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
- obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o
+++ /dev/null
---- a/arch/arm/mach-ixp4xx/ap1000-setup.c
-+++ b/arch/arm/mach-ixp4xx/ap1000-setup.c
-@@ -90,9 +90,37 @@
- .resource = ap1000_uart_resources
- };
-
-+/* Built-in 10/100 Ethernet MAC interfaces */
-+static struct eth_plat_info ap1000_plat_eth[] = {
-+ {
-+ .phy = IXP4XX_ETH_PHY_MAX_ADDR,
-+ .phy_mask = 0x1e,
-+ .rxq = 3,
-+ .txreadyq = 20,
-+ }, {
-+ .phy = 5,
-+ .rxq = 4,
-+ .txreadyq = 21,
-+ }
-+};
-+
-+static struct platform_device ap1000_eth[] = {
-+ {
-+ .name = "ixp4xx_eth",
-+ .id = IXP4XX_ETH_NPEB,
-+ .dev.platform_data = ap1000_plat_eth,
-+ }, {
-+ .name = "ixp4xx_eth",
-+ .id = IXP4XX_ETH_NPEC,
-+ .dev.platform_data = ap1000_plat_eth + 1,
-+ }
-+};
-+
- static struct platform_device *ap1000_devices[] __initdata = {
- &ap1000_flash,
-- &ap1000_uart
-+ &ap1000_uart,
-+ &ap1000_eth[0],
-+ &ap1000_eth[1],
- };
-
- static char ap1000_mem_fixup[] __initdata = "mem=64M ";
+++ /dev/null
---- a/arch/arm/mach-ixp4xx/wg302v1-setup.c
-+++ b/arch/arm/mach-ixp4xx/wg302v1-setup.c
-@@ -115,6 +115,36 @@
- &wg302v1_eth[0],
- };
-
-+static char wg302v1_mem_fixup[] __initdata = "mem=32M ";
-+
-+static void __init wg302v1_fixup(struct machine_desc *desc,
-+ struct tag *tags, char **cmdline, struct meminfo *mi)
-+
-+{
-+ struct tag *t = tags;
-+ char *p = *cmdline;
-+
-+ /* Find the end of the tags table, taking note of any cmdline tag. */
-+ for (; t->hdr.size; t = tag_next(t)) {
-+ if (t->hdr.tag == ATAG_CMDLINE) {
-+ p = t->u.cmdline.cmdline;
-+ }
-+ }
-+
-+ /* Overwrite the end of the table with a new cmdline tag. */
-+ t->hdr.tag = ATAG_CMDLINE;
-+ t->hdr.size = (sizeof (struct tag_header) +
-+ strlen(wg302v1_mem_fixup) + strlen(p) + 1 + 4) >> 2;
-+ strlcpy(t->u.cmdline.cmdline, wg302v1_mem_fixup, COMMAND_LINE_SIZE);
-+ strlcpy(t->u.cmdline.cmdline + strlen(wg302v1_mem_fixup), p,
-+ COMMAND_LINE_SIZE - strlen(wg302v1_mem_fixup));
-+
-+ /* Terminate the table. */
-+ t = tag_next(t);
-+ t->hdr.tag = ATAG_NONE;
-+ t->hdr.size = 0;
-+}
-+
- static void __init wg302v1_init(void)
- {
- ixp4xx_sys_init();
-@@ -133,6 +163,7 @@
- /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
- .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
- .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
-+ .fixup = wg302v1_fixup,
- .map_io = ixp4xx_map_io,
- .init_irq = ixp4xx_init_irq,
- .timer = &ixp4xx_timer,
+++ /dev/null
---- a/arch/arm/mach-ixp4xx/coyote-setup.c
-+++ b/arch/arm/mach-ixp4xx/coyote-setup.c
-@@ -73,9 +73,37 @@
- .resource = &coyote_uart_resource,
- };
-
-+/* Built-in 10/100 Ethernet MAC interfaces */
-+static struct eth_plat_info ixdpg425_plat_eth[] = {
-+ {
-+ .phy = 5,
-+ .rxq = 3,
-+ .txreadyq = 20,
-+ }, {
-+ .phy = 4,
-+ .rxq = 4,
-+ .txreadyq = 21,
-+ }
-+};
-+
-+static struct platform_device ixdpg425_eth[] = {
-+ {
-+ .name = "ixp4xx_eth",
-+ .id = IXP4XX_ETH_NPEB,
-+ .dev.platform_data = ixdpg425_plat_eth,
-+ }, {
-+ .name = "ixp4xx_eth",
-+ .id = IXP4XX_ETH_NPEC,
-+ .dev.platform_data = ixdpg425_plat_eth + 1,
-+ }
-+};
-+
-+
- static struct platform_device *coyote_devices[] __initdata = {
- &coyote_flash,
-- &coyote_uart
-+ &coyote_uart,
-+ &ixdpg425_eth[0],
-+ &ixdpg425_eth[1],
- };
-
- static void __init coyote_init(void)
+++ /dev/null
---- a/arch/arm/mach-ixp4xx/Kconfig
-+++ b/arch/arm/mach-ixp4xx/Kconfig
-@@ -158,6 +158,14 @@
- PrPCM1100 Processor Mezanine Module. For more information on
- this platform, see <file:Documentation/arm/IXP4xx>.
-
-+config MACH_TW5334
-+ bool "Titan Wireless TW-533-4"
-+ select PCI
-+ help
-+ Say 'Y' here if you want your kernel to support the Titan
-+ Wireless TW533-4. For more information on this platform,
-+ see http://openwrt.org
-+
- config MACH_NAS100D
- bool
- prompt "NAS100D"
---- a/arch/arm/mach-ixp4xx/Makefile
-+++ b/arch/arm/mach-ixp4xx/Makefile
-@@ -22,6 +22,7 @@
- obj-pci-$(CONFIG_MACH_COMPEX) += ixdp425-pci.o
- obj-pci-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-pci.o
- obj-pci-$(CONFIG_MACH_AP1000) += ixdp425-pci.o
-+obj-pci-$(CONFIG_MACH_TW5334) += tw5334-pci.o
-
- obj-y += common.o
-
-@@ -42,6 +43,7 @@
- obj-$(CONFIG_MACH_COMPEX) += compex-setup.o
- obj-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-setup.o
- obj-$(CONFIG_MACH_AP1000) += ap1000-setup.o
-+obj-$(CONFIG_MACH_TW5334) += tw5334-setup.o
-
- obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
- obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o
---- /dev/null
-+++ b/arch/arm/mach-ixp4xx/tw5334-setup.c
-@@ -0,0 +1,162 @@
-+/*
-+ * arch/arm/mach-ixp4xx/tw5334-setup.c
-+ *
-+ * Board setup for the Titan Wireless TW-533-4
-+ *
-+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-+ *
-+ * based on coyote-setup.c:
-+ * Copyright (C) 2003-2005 MontaVista Software, Inc.
-+ *
-+ * Author: Imre Kaloz <Kaloz@openwrt.org>
-+ */
-+
-+#include <linux/if_ether.h>
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/device.h>
-+#include <linux/serial.h>
-+#include <linux/tty.h>
-+#include <linux/serial_8250.h>
-+#include <linux/slab.h>
-+
-+#include <asm/types.h>
-+#include <asm/setup.h>
-+#include <asm/memory.h>
-+#include <asm/hardware.h>
-+#include <asm/irq.h>
-+#include <asm/mach-types.h>
-+#include <asm/mach/arch.h>
-+#include <asm/mach/flash.h>
-+
-+static struct flash_platform_data tw5334_flash_data = {
-+ .map_name = "cfi_probe",
-+ .width = 2,
-+};
-+
-+static struct resource tw5334_flash_resource = {
-+ .flags = IORESOURCE_MEM,
-+};
-+
-+static struct platform_device tw5334_flash = {
-+ .name = "IXP4XX-Flash",
-+ .id = 0,
-+ .dev = {
-+ .platform_data = &tw5334_flash_data,
-+ },
-+ .num_resources = 1,
-+ .resource = &tw5334_flash_resource,
-+};
-+
-+static struct resource tw5334_uart_resource = {
-+ .start = IXP4XX_UART2_BASE_PHYS,
-+ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
-+ .flags = IORESOURCE_MEM,
-+};
-+
-+static struct plat_serial8250_port tw5334_uart_data[] = {
-+ {
-+ .mapbase = IXP4XX_UART2_BASE_PHYS,
-+ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
-+ .irq = IRQ_IXP4XX_UART2,
-+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
-+ .iotype = UPIO_MEM,
-+ .regshift = 2,
-+ .uartclk = IXP4XX_UART_XTAL,
-+ },
-+ { },
-+};
-+
-+static struct platform_device tw5334_uart = {
-+ .name = "serial8250",
-+ .id = PLAT8250_DEV_PLATFORM,
-+ .dev = {
-+ .platform_data = tw5334_uart_data,
-+ },
-+ .num_resources = 1,
-+ .resource = &tw5334_uart_resource,
-+};
-+
-+/* Built-in 10/100 Ethernet MAC interfaces */
-+static struct eth_plat_info tw5334_plat_eth[] = {
-+ {
-+ .phy = 0,
-+ .rxq = 3,
-+ .txreadyq = 20,
-+ }, {
-+ .phy = 1,
-+ .rxq = 4,
-+ .txreadyq = 21,
-+ }
-+};
-+
-+static struct platform_device tw5334_eth[] = {
-+ {
-+ .name = "ixp4xx_eth",
-+ .id = IXP4XX_ETH_NPEB,
-+ .dev.platform_data = tw5334_plat_eth,
-+ }, {
-+ .name = "ixp4xx_eth",
-+ .id = IXP4XX_ETH_NPEC,
-+ .dev.platform_data = tw5334_plat_eth + 1,
-+ }
-+};
-+
-+static struct platform_device *tw5334_devices[] __initdata = {
-+ &tw5334_flash,
-+ &tw5334_uart,
-+ &tw5334_eth[0],
-+ &tw5334_eth[1],
-+};
-+
-+static void __init tw5334_init(void)
-+{
-+ DECLARE_MAC_BUF(mac_buf);
-+ uint8_t __iomem *f;
-+ int i;
-+
-+ ixp4xx_sys_init();
-+
-+ tw5334_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
-+ tw5334_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
-+
-+ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
-+ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
-+
-+ platform_add_devices(tw5334_devices, ARRAY_SIZE(tw5334_devices));
-+
-+ /*
-+ * Map in a portion of the flash and read the MAC addresses.
-+ * Since it is stored in BE in the flash itself, we need to
-+ * byteswap it if we're in LE mode.
-+ */
-+ f = ioremap(IXP4XX_EXP_BUS_BASE(0), 0x1000000);
-+ if (f) {
-+ for (i = 0; i < 6; i++)
-+#ifdef __ARMEB__
-+ tw5334_plat_eth[0].hwaddr[i] = readb(f + 0xFC0422 + i);
-+ tw5334_plat_eth[1].hwaddr[i] = readb(f + 0xFC043B + i);
-+#else
-+ tw5334_plat_eth[0].hwaddr[i] = readb(f + 0xFC0422 + (i^3));
-+ tw5334_plat_eth[1].hwaddr[i] = readb(f + 0xFC043B + (i^3));
-+#endif
-+ iounmap(f);
-+ }
-+ printk(KERN_INFO "TW-533-4: Using MAC address %s for port 0\n",
-+ print_mac(mac_buf, tw5334_plat_eth[0].hwaddr));
-+ printk(KERN_INFO "TW-533-4: Using MAC address %s for port 1\n",
-+ print_mac(mac_buf, tw5334_plat_eth[1].hwaddr));
-+}
-+
-+#ifdef CONFIG_MACH_TW5334
-+MACHINE_START(TW5334, "Titan Wireless TW-533-4")
-+ /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
-+ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
-+ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
-+ .map_io = ixp4xx_map_io,
-+ .init_irq = ixp4xx_init_irq,
-+ .timer = &ixp4xx_timer,
-+ .boot_params = 0x0100,
-+ .init_machine = tw5334_init,
-+MACHINE_END
-+#endif
---- /dev/null
-+++ b/arch/arm/mach-ixp4xx/tw5334-pci.c
-@@ -0,0 +1,69 @@
-+/*
-+ * arch/arch/mach-ixp4xx/tw5334-pci.c
-+ *
-+ * PCI setup routines for the Titan Wireless TW-533-4
-+ *
-+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-+ *
-+ * based on coyote-pci.c:
-+ * Copyright (C) 2002 Jungo Software Technologies.
-+ * Copyright (C) 2003 MontaVista Softwrae, Inc.
-+ *
-+ * Maintainer: Imre Kaloz <kaloz@openwrt.org>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/pci.h>
-+#include <linux/init.h>
-+#include <linux/irq.h>
-+
-+#include <asm/mach-types.h>
-+#include <asm/hardware.h>
-+
-+#include <asm/mach/pci.h>
-+
-+void __init tw5334_pci_preinit(void)
-+{
-+ set_irq_type(IRQ_IXP4XX_GPIO6, IRQT_LOW);
-+ set_irq_type(IRQ_IXP4XX_GPIO2, IRQT_LOW);
-+ set_irq_type(IRQ_IXP4XX_GPIO1, IRQT_LOW);
-+ set_irq_type(IRQ_IXP4XX_GPIO0, IRQT_LOW);
-+
-+ ixp4xx_pci_preinit();
-+}
-+
-+static int __init tw5334_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
-+{
-+ if (slot == 12)
-+ return IRQ_IXP4XX_GPIO6;
-+ else if (slot == 13)
-+ return IRQ_IXP4XX_GPIO2;
-+ else if (slot == 14)
-+ return IRQ_IXP4XX_GPIO1;
-+ else if (slot == 15)
-+ return IRQ_IXP4XX_GPIO0;
-+ else return -1;
-+}
-+
-+struct hw_pci tw5334_pci __initdata = {
-+ .nr_controllers = 1,
-+ .preinit = tw5334_pci_preinit,
-+ .swizzle = pci_std_swizzle,
-+ .setup = ixp4xx_setup,
-+ .scan = ixp4xx_scan_bus,
-+ .map_irq = tw5334_map_irq,
-+};
-+
-+int __init tw5334_pci_init(void)
-+{
-+ if (machine_is_tw5334())
-+ pci_common_init(&tw5334_pci);
-+ return 0;
-+}
-+
-+subsys_initcall(tw5334_pci_init);
---- a/include/asm-arm/arch-ixp4xx/uncompress.h
-+++ b/include/asm-arm/arch-ixp4xx/uncompress.h
-@@ -42,7 +42,8 @@
- */
- if (machine_is_adi_coyote() || machine_is_gtwx5715() ||
- machine_is_gateway7001() || machine_is_wg302v2() ||
-- machine_is_pronghorn() || machine_is_pronghorn_metro() || machine_is_wrt300nv2())
-+ machine_is_pronghorn() || machine_is_pronghorn_metro() || machine_is_wrt300nv2() ||
-+ machine_is_tw5334())
- uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS;
- else
- uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS;
+++ /dev/null
---- a/arch/arm/mach-ixp4xx/Kconfig
-+++ b/arch/arm/mach-ixp4xx/Kconfig
-@@ -25,6 +25,14 @@
- Avila Network Platform. For more information on this platform,
- see <file:Documentation/arm/IXP4xx>.
-
-+config MACH_CAMBRIA
-+ bool "Cambria"
-+ select PCI
-+ help
-+ Say 'Y' here if you want your kernel to support the Gateworks
-+ Cambria series. For more information on this platform,
-+ see <file:Documentation/arm/IXP4xx>.
-+
- config MACH_LOFT
- bool "Loft"
- depends on MACH_AVILA
-@@ -208,7 +216,7 @@
-
- config CPU_IXP43X
- bool
-- depends on MACH_KIXRP435
-+ depends on MACH_KIXRP435 || MACH_CAMBRIA
- default y
-
- config MACH_GTWX5715
---- a/arch/arm/mach-ixp4xx/Makefile
-+++ b/arch/arm/mach-ixp4xx/Makefile
-@@ -7,6 +7,7 @@
-
- obj-pci-$(CONFIG_ARCH_IXDP4XX) += ixdp425-pci.o
- obj-pci-$(CONFIG_MACH_AVILA) += avila-pci.o
-+obj-pci-$(CONFIG_MACH_CAMBRIA) += cambria-pci.o
- obj-pci-$(CONFIG_MACH_IXDPG425) += ixdpg425-pci.o
- obj-pci-$(CONFIG_ARCH_ADI_COYOTE) += coyote-pci.o
- obj-pci-$(CONFIG_MACH_GTWX5715) += gtwx5715-pci.o
-@@ -28,6 +29,7 @@
-
- obj-$(CONFIG_ARCH_IXDP4XX) += ixdp425-setup.o
- obj-$(CONFIG_MACH_AVILA) += avila-setup.o
-+obj-$(CONFIG_MACH_CAMBRIA) += cambria-setup.o
- obj-$(CONFIG_MACH_IXDPG425) += coyote-setup.o
- obj-$(CONFIG_ARCH_ADI_COYOTE) += coyote-setup.o
- obj-$(CONFIG_MACH_GTWX5715) += gtwx5715-setup.o
---- /dev/null
-+++ b/arch/arm/mach-ixp4xx/cambria-pci.c
-@@ -0,0 +1,74 @@
-+/*
-+ * arch/arch/mach-ixp4xx/cambria-pci.c
-+ *
-+ * PCI setup routines for Gateworks Cambria series
-+ *
-+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-+ *
-+ * based on coyote-pci.c:
-+ * Copyright (C) 2002 Jungo Software Technologies.
-+ * Copyright (C) 2003 MontaVista Softwrae, Inc.
-+ *
-+ * Maintainer: Imre Kaloz <kaloz@openwrt.org>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/pci.h>
-+#include <linux/init.h>
-+#include <linux/irq.h>
-+
-+#include <asm/mach-types.h>
-+#include <asm/hardware.h>
-+#include <asm/irq.h>
-+
-+#include <asm/mach/pci.h>
-+
-+extern void ixp4xx_pci_preinit(void);
-+extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
-+extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
-+
-+void __init cambria_pci_preinit(void)
-+{
-+ set_irq_type(IRQ_IXP4XX_GPIO11, IRQT_LOW);
-+ set_irq_type(IRQ_IXP4XX_GPIO10, IRQT_LOW);
-+ set_irq_type(IRQ_IXP4XX_GPIO9, IRQT_LOW);
-+ set_irq_type(IRQ_IXP4XX_GPIO8, IRQT_LOW);
-+
-+ ixp4xx_pci_preinit();
-+}
-+
-+static int __init cambria_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
-+{
-+ if (slot == 1)
-+ return IRQ_IXP4XX_GPIO11;
-+ else if (slot == 2)
-+ return IRQ_IXP4XX_GPIO10;
-+ else if (slot == 3)
-+ return IRQ_IXP4XX_GPIO9;
-+ else if (slot == 4)
-+ return IRQ_IXP4XX_GPIO8;
-+ else return -1;
-+}
-+
-+struct hw_pci cambria_pci __initdata = {
-+ .nr_controllers = 1,
-+ .preinit = cambria_pci_preinit,
-+ .swizzle = pci_std_swizzle,
-+ .setup = ixp4xx_setup,
-+ .scan = ixp4xx_scan_bus,
-+ .map_irq = cambria_map_irq,
-+};
-+
-+int __init cambria_pci_init(void)
-+{
-+ if (machine_is_cambria())
-+ pci_common_init(&cambria_pci);
-+ return 0;
-+}
-+
-+subsys_initcall(cambria_pci_init);
---- /dev/null
-+++ b/arch/arm/mach-ixp4xx/cambria-setup.c
-@@ -0,0 +1,444 @@
-+/*
-+ * arch/arm/mach-ixp4xx/cambria-setup.c
-+ *
-+ * Board setup for the Gateworks Cambria series
-+ *
-+ * Copyright (C) 2008 Imre Kaloz <Kaloz@openwrt.org>
-+ *
-+ * based on coyote-setup.c:
-+ * Copyright (C) 2003-2005 MontaVista Software, Inc.
-+ *
-+ * Author: Imre Kaloz <Kaloz@openwrt.org>
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/device.h>
-+#include <linux/if_ether.h>
-+#include <linux/socket.h>
-+#include <linux/netdevice.h>
-+#include <linux/serial.h>
-+#include <linux/tty.h>
-+#include <linux/serial_8250.h>
-+#include <linux/slab.h>
-+#ifdef CONFIG_SENSORS_EEPROM
-+# include <linux/i2c.h>
-+# include <linux/eeprom.h>
-+#endif
-+
-+#include <linux/leds.h>
-+#include <linux/i2c-gpio.h>
-+#include <asm/types.h>
-+#include <asm/setup.h>
-+#include <asm/memory.h>
-+#include <asm/hardware.h>
-+#include <asm/irq.h>
-+#include <asm/mach-types.h>
-+#include <asm/mach/arch.h>
-+#include <asm/mach/flash.h>
-+
-+struct cambria_board_info {
-+ unsigned char *model;
-+ void (* setup)(void);
-+};
-+
-+static struct cambria_board_info *cambria_info __initdata;
-+
-+static struct flash_platform_data cambria_flash_data = {
-+ .map_name = "cfi_probe",
-+ .width = 2,
-+};
-+
-+static struct resource cambria_flash_resource = {
-+ .flags = IORESOURCE_MEM,
-+};
-+
-+static struct platform_device cambria_flash = {
-+ .name = "IXP4XX-Flash",
-+ .id = 0,
-+ .dev = {
-+ .platform_data = &cambria_flash_data,
-+ },
-+ .num_resources = 1,
-+ .resource = &cambria_flash_resource,
-+};
-+
-+static struct i2c_gpio_platform_data cambria_i2c_gpio_data = {
-+ .sda_pin = 7,
-+ .scl_pin = 6,
-+};
-+
-+static struct platform_device cambria_i2c_gpio = {
-+ .name = "i2c-gpio",
-+ .id = 0,
-+ .dev = {
-+ .platform_data = &cambria_i2c_gpio_data,
-+ },
-+};
-+
-+static struct resource cambria_uart_resource = {
-+ .start = IXP4XX_UART1_BASE_PHYS,
-+ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
-+ .flags = IORESOURCE_MEM,
-+};
-+
-+static struct plat_serial8250_port cambria_uart_data[] = {
-+ {
-+ .mapbase = IXP4XX_UART1_BASE_PHYS,
-+ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
-+ .irq = IRQ_IXP4XX_UART1,
-+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
-+ .iotype = UPIO_MEM,
-+ .regshift = 2,
-+ .uartclk = IXP4XX_UART_XTAL,
-+ },
-+ { },
-+};
-+
-+static struct platform_device cambria_uart = {
-+ .name = "serial8250",
-+ .id = PLAT8250_DEV_PLATFORM,
-+ .dev = {
-+ .platform_data = cambria_uart_data,
-+ },
-+ .num_resources = 1,
-+ .resource = &cambria_uart_resource,
-+};
-+
-+static struct resource cambria_pata_resources[] = {
-+ {
-+ .flags = IORESOURCE_MEM
-+ },
-+ {
-+ .flags = IORESOURCE_MEM,
-+ },
-+ {
-+ .name = "intrq",
-+ .start = IRQ_IXP4XX_GPIO12,
-+ .end = IRQ_IXP4XX_GPIO12,
-+ .flags = IORESOURCE_IRQ,
-+ },
-+};
-+
-+static struct ixp4xx_pata_data cambria_pata_data = {
-+ .cs0_bits = 0xbfff3c03,
-+ .cs1_bits = 0xbfff3c03,
-+};
-+
-+static struct platform_device cambria_pata = {
-+ .name = "pata_ixp4xx_cf",
-+ .id = 0,
-+ .dev.platform_data = &cambria_pata_data,
-+ .num_resources = ARRAY_SIZE(cambria_pata_resources),
-+ .resource = cambria_pata_resources,
-+};
-+
-+static struct eth_plat_info cambria_npec_data = {
-+ .phy = 1,
-+ .rxq = 4,
-+ .txreadyq = 21,
-+};
-+
-+static struct eth_plat_info cambria_npea_data = {
-+ .phy = 2,
-+ .rxq = 2,
-+ .txreadyq = 19,
-+};
-+
-+static struct platform_device cambria_npec_device = {
-+ .name = "ixp4xx_eth",
-+ .id = IXP4XX_ETH_NPEC,
-+ .dev.platform_data = &cambria_npec_data,
-+};
-+
-+static struct platform_device cambria_npea_device = {
-+ .name = "ixp4xx_eth",
-+ .id = IXP4XX_ETH_NPEA,
-+ .dev.platform_data = &cambria_npea_data,
-+};
-+
-+static struct gpio_led cambria_gpio_leds[] = {
-+ {
-+ .name = "user", /* green led */
-+ .gpio = 5,
-+ .active_low = 1,
-+ }
-+};
-+
-+static struct gpio_led_platform_data cambria_gpio_leds_data = {
-+ .num_leds = 1,
-+ .leds = cambria_gpio_leds,
-+};
-+
-+static struct platform_device cambria_gpio_leds_device = {
-+ .name = "leds-gpio",
-+ .id = -1,
-+ .dev.platform_data = &cambria_gpio_leds_data,
-+};
-+
-+
-+static struct latch_led cambria_latch_leds[] = {
-+ {
-+ .name = "ledA", /* green led */
-+ .bit = 0,
-+ },
-+ {
-+ .name = "ledB", /* green led */
-+ .bit = 1,
-+ },
-+ {
-+ .name = "ledC", /* green led */
-+ .bit = 2,
-+ },
-+ {
-+ .name = "ledD", /* green led */
-+ .bit = 3,
-+ },
-+ {
-+ .name = "ledE", /* green led */
-+ .bit = 4,
-+ },
-+ {
-+ .name = "ledF", /* green led */
-+ .bit = 5,
-+ },
-+ {
-+ .name = "ledG", /* green led */
-+ .bit = 6,
-+ },
-+ {
-+ .name = "ledH", /* green led */
-+ .bit = 7,
-+ }
-+};
-+
-+static struct latch_led_platform_data cambria_latch_leds_data = {
-+ .num_leds = 8,
-+ .leds = cambria_latch_leds,
-+ .mem = 0x53F40000,
-+};
-+
-+static struct platform_device cambria_latch_leds_device = {
-+ .name = "leds-latch",
-+ .id = -1,
-+ .dev.platform_data = &cambria_latch_leds_data,
-+};
-+
-+static struct resource cambria_usb0_resources[] = {
-+ {
-+ .start = 0xCD000000,
-+ .end = 0xCD000300,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ {
-+ .start = 32,
-+ .flags = IORESOURCE_IRQ,
-+ },
-+};
-+
-+static struct resource cambria_usb1_resources[] = {
-+ {
-+ .start = 0xCE000000,
-+ .end = 0xCE000300,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ {
-+ .start = 33,
-+ .flags = IORESOURCE_IRQ,
-+ },
-+};
-+
-+static u64 ehci_dma_mask = ~(u32)0;
-+
-+static struct platform_device cambria_usb0_device = {
-+ .name = "ixp4xx-ehci",
-+ .id = 0,
-+ .resource = cambria_usb0_resources,
-+ .num_resources = ARRAY_SIZE(cambria_usb0_resources),
-+ .dev = {
-+ .dma_mask = &ehci_dma_mask,
-+ .coherent_dma_mask = 0xffffffff,
-+ },
-+};
-+
-+static struct platform_device cambria_usb1_device = {
-+ .name = "ixp4xx-ehci",
-+ .id = 1,
-+ .resource = cambria_usb1_resources,
-+ .num_resources = ARRAY_SIZE(cambria_usb1_resources),
-+ .dev = {
-+ .dma_mask = &ehci_dma_mask,
-+ .coherent_dma_mask = 0xffffffff,
-+ },
-+};
-+
-+static struct platform_device *cambria_devices[] __initdata = {
-+ &cambria_i2c_gpio,
-+ &cambria_flash,
-+ &cambria_uart,
-+};
-+
-+static void __init cambria_gw23xx_setup(void)
-+{
-+ platform_device_register(&cambria_npec_device);
-+ platform_device_register(&cambria_npea_device);
-+}
-+
-+#ifdef CONFIG_SENSORS_EEPROM
-+static void __init cambria_gw2350_setup(void)
-+{
-+ platform_device_register(&cambria_npec_device);
-+ platform_device_register(&cambria_npea_device);
-+
-+ platform_device_register(&cambria_usb0_device);
-+ platform_device_register(&cambria_usb1_device);
-+
-+ platform_device_register(&cambria_gpio_leds_device);
-+}
-+
-+static void __init cambria_gw2358_setup(void)
-+{
-+ platform_device_register(&cambria_npec_device);
-+ platform_device_register(&cambria_npea_device);
-+
-+ platform_device_register(&cambria_usb0_device);
-+ platform_device_register(&cambria_usb1_device);
-+
-+ platform_device_register(&cambria_pata);
-+
-+ platform_device_register(&cambria_latch_leds_device);
-+}
-+
-+static struct cambria_board_info cambria_boards[] __initdata = {
-+ {
-+ .model = "GW2350",
-+ .setup = cambria_gw2350_setup,
-+ }, {
-+ .model = "GW2358",
-+ .setup = cambria_gw2358_setup,
-+ }
-+};
-+
-+static struct cambria_board_info * __init cambria_find_board_info(char *model)
-+{
-+ int i;
-+
-+ for (i = 0; i < ARRAY_SIZE(cambria_boards); i++) {
-+ struct cambria_board_info *info = &cambria_boards[i];
-+ if (strncmp(info->model, model, strlen(info->model)) == 0)
-+ return info;
-+ }
-+
-+ return NULL;
-+}
-+
-+struct cambria_eeprom_header {
-+ unsigned char mac0[ETH_ALEN];
-+ unsigned char mac1[ETH_ALEN];
-+ unsigned char res0[4];
-+ unsigned char magic[2];
-+ unsigned char config[14];
-+ unsigned char model[16];
-+};
-+
-+static int __init cambria_eeprom_notify(struct notifier_block *self,
-+ unsigned long event, void *t)
-+{
-+ struct eeprom_data *ee = t;
-+ struct cambria_eeprom_header hdr;
-+
-+ if (cambria_info)
-+ return NOTIFY_DONE;
-+
-+ /* The eeprom is at address 0x51 */
-+ if (event != EEPROM_REGISTER || ee->client.addr != 0x51)
-+ return NOTIFY_DONE;
-+
-+ ee->attr->read(&ee->client.dev.kobj, ee->attr, (char *)&hdr,
-+ 0, sizeof(hdr));
-+
-+ if (hdr.magic[0] != 'G' || hdr.magic[1] != 'W')
-+ return NOTIFY_DONE;
-+
-+ memcpy(&cambria_npec_data.hwaddr, hdr.mac0, ETH_ALEN);
-+ memcpy(&cambria_npea_data.hwaddr, hdr.mac1, ETH_ALEN);
-+
-+ cambria_info = cambria_find_board_info(hdr.model);
-+
-+ return NOTIFY_OK;
-+}
-+
-+static struct notifier_block cambria_eeprom_notifier __initdata = {
-+ .notifier_call = cambria_eeprom_notify
-+};
-+
-+static void __init cambria_register_eeprom_notifier(void)
-+{
-+ register_eeprom_notifier(&cambria_eeprom_notifier);
-+}
-+
-+static void __init cambria_unregister_eeprom_notifier(void)
-+{
-+ unregister_eeprom_notifier(&cambria_eeprom_notifier);
-+}
-+#else /* CONFIG_SENSORS_EEPROM */
-+static inline void cambria_register_eeprom_notifier(void) {};
-+static inline void cambria_unregister_eeprom_notifier(void) {};
-+#endif /* CONFIG_SENSORS_EEPROM */
-+
-+static void __init cambria_init(void)
-+{
-+ ixp4xx_sys_init();
-+
-+ cambria_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
-+ cambria_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
-+
-+ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
-+ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
-+
-+ platform_add_devices(cambria_devices, ARRAY_SIZE(cambria_devices));
-+
-+ cambria_pata_resources[0].start = 0x53e00000;
-+ cambria_pata_resources[0].end = 0x53e3ffff;
-+
-+ cambria_pata_resources[1].start = 0x53e40000;
-+ cambria_pata_resources[1].end = 0x53e7ffff;
-+
-+ cambria_pata_data.cs0_cfg = IXP4XX_EXP_CS3;
-+ cambria_pata_data.cs1_cfg = IXP4XX_EXP_CS3;
-+
-+ cambria_register_eeprom_notifier();
-+}
-+
-+static int __init cambria_model_setup(void)
-+{
-+ if (!machine_is_cambria())
-+ return 0;
-+
-+ if (cambria_info) {
-+ printk(KERN_DEBUG "Running on Gateworks Cambria %s\n",
-+ cambria_info->model);
-+ cambria_info->setup();
-+ } else {
-+ printk(KERN_INFO "Unknown/missing Cambria model number"
-+ " -- defaults will be used\n");
-+ cambria_gw23xx_setup();
-+ }
-+
-+ cambria_unregister_eeprom_notifier();
-+ return 0;
-+}
-+late_initcall(cambria_model_setup);
-+
-+#ifdef CONFIG_MACH_CAMBRIA
-+MACHINE_START(CAMBRIA, "Gateworks Cambria series")
-+ /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
-+ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
-+ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
-+ .map_io = ixp4xx_map_io,
-+ .init_irq = ixp4xx_init_irq,
-+ .timer = &ixp4xx_timer,
-+ .boot_params = 0x0100,
-+ .init_machine = cambria_init,
-+MACHINE_END
-+#endif
---- a/include/asm-arm/arch-ixp4xx/hardware.h
-+++ b/include/asm-arm/arch-ixp4xx/hardware.h
-@@ -18,7 +18,7 @@
- #define __ASM_ARCH_HARDWARE_H__
-
- #define PCIBIOS_MIN_IO 0x00001000
--#define PCIBIOS_MIN_MEM (cpu_is_ixp43x() ? 0x40000000 : 0x48000000)
-+#define PCIBIOS_MIN_MEM (cpu_is_ixp43x() ? 0x48000000 : 0x48000000)
-
- /*
- * We override the standard dma-mask routines for bouncing.
+++ /dev/null
---- a/arch/arm/mach-ixp4xx/cambria-setup.c
-+++ b/arch/arm/mach-ixp4xx/cambria-setup.c
-@@ -36,6 +36,7 @@
- #include <asm/mach-types.h>
- #include <asm/mach/arch.h>
- #include <asm/mach/flash.h>
-+#include <linux/irq.h>
-
- struct cambria_board_info {
- unsigned char *model;
-@@ -105,6 +106,43 @@
- .resource = &cambria_uart_resource,
- };
-
-+static struct resource cambria_optional_uart_resources[] = {
-+ {
-+ .start = 0x52000000,
-+ .end = 0x52000fff,
-+ .flags = IORESOURCE_MEM
-+ },
-+ {
-+ .start = 0x53000000,
-+ .end = 0x53000fff,
-+ .flags = IORESOURCE_MEM
-+ }
-+};
-+
-+static struct plat_serial8250_port cambria_optional_uart_data[] = {
-+ {
-+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_BUGGY_UART,
-+ .iotype = UPIO_MEM,
-+ .regshift = 0,
-+ .uartclk = 1843200,
-+ },
-+ {
-+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_BUGGY_UART,
-+ .iotype = UPIO_MEM,
-+ .regshift = 0,
-+ .uartclk = 1843200,
-+ },
-+ { },
-+};
-+
-+static struct platform_device cambria_optional_uart = {
-+ .name = "serial8250",
-+ .id = PLAT8250_DEV_PLATFORM1,
-+ .dev.platform_data = cambria_optional_uart_data,
-+ .num_resources = 2,
-+ .resource = cambria_optional_uart_resources,
-+};
-+
- static struct resource cambria_pata_resources[] = {
- {
- .flags = IORESOURCE_MEM
-@@ -287,6 +325,19 @@
- #ifdef CONFIG_SENSORS_EEPROM
- static void __init cambria_gw2350_setup(void)
- {
-+ *IXP4XX_EXP_CS2 = 0xbfff0003;
-+ set_irq_type(IRQ_IXP4XX_GPIO3, IRQT_RISING);
-+ cambria_optional_uart_data[0].mapbase = 0x52FF0000;
-+ cambria_optional_uart_data[0].membase = (void __iomem *)ioremap(0x52FF0000, 0x0fff);
-+ cambria_optional_uart_data[0].irq = IRQ_IXP4XX_GPIO3;
-+
-+ *IXP4XX_EXP_CS3 = 0xbfff0003;
-+ set_irq_type(IRQ_IXP4XX_GPIO4, IRQT_RISING);
-+ cambria_optional_uart_data[1].mapbase = 0x53FF0000;
-+ cambria_optional_uart_data[1].membase = (void __iomem *)ioremap(0x53FF0000, 0x0fff);
-+ cambria_optional_uart_data[1].irq = IRQ_IXP4XX_GPIO4;
-+
-+ platform_device_register(&cambria_optional_uart);
- platform_device_register(&cambria_npec_device);
- platform_device_register(&cambria_npea_device);
-
-@@ -294,10 +345,26 @@
- platform_device_register(&cambria_usb1_device);
-
- platform_device_register(&cambria_gpio_leds_device);
-+
-+ *IXP4XX_EXP_CS2 = 0xBFFF3C43;
-+ *IXP4XX_EXP_CS3 = 0xBFFF3C43;
- }
-
- static void __init cambria_gw2358_setup(void)
- {
-+ *IXP4XX_EXP_CS3 = 0xbfff0003;
-+ set_irq_type(IRQ_IXP4XX_GPIO3, IRQT_RISING);
-+ cambria_optional_uart_data[0].mapbase = 0x53FC0000;
-+ cambria_optional_uart_data[0].membase = (void __iomem *)ioremap(0x53FC0000, 0x0fff);
-+ cambria_optional_uart_data[0].irq = IRQ_IXP4XX_GPIO3;
-+
-+ set_irq_type(IRQ_IXP4XX_GPIO4, IRQT_RISING);
-+ cambria_optional_uart_data[1].mapbase = 0x53F80000;
-+ cambria_optional_uart_data[1].membase = (void __iomem *)ioremap(0x53F80000, 0x0fff);
-+ cambria_optional_uart_data[1].irq = IRQ_IXP4XX_GPIO4;
-+
-+ platform_device_register(&cambria_optional_uart);
-+
- platform_device_register(&cambria_npec_device);
- platform_device_register(&cambria_npea_device);
-
+++ /dev/null
---- a/arch/arm/mach-ixp4xx/cambria-setup.c
-+++ b/arch/arm/mach-ixp4xx/cambria-setup.c
-@@ -214,6 +214,21 @@
- .dev.platform_data = &cambria_gpio_leds_data,
- };
-
-+static struct resource cambria_gpio_resources[] = {
-+ {
-+ .name = "gpio",
-+ .flags = 0,
-+ },
-+};
-+
-+static struct platform_device cambria_gpio = {
-+ .name = "GPIODEV",
-+ .id = -1,
-+ .num_resources = ARRAY_SIZE(cambria_gpio_resources),
-+ .resource = cambria_gpio_resources,
-+};
-+
-+
-
- static struct latch_led cambria_latch_leds[] = {
- {
-@@ -337,6 +352,11 @@
- cambria_optional_uart_data[1].membase = (void __iomem *)ioremap(0x53FF0000, 0x0fff);
- cambria_optional_uart_data[1].irq = IRQ_IXP4XX_GPIO4;
-
-+ cambria_gpio_resources[0].start = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4) |\
-+ (1 << 5) | (1 << 8) | (1 << 9) | (1 << 12);
-+ cambria_gpio_resources[0].end = cambria_gpio_resources[0].start;
-+
-+ platform_device_register(&cambria_gpio);
- platform_device_register(&cambria_optional_uart);
- platform_device_register(&cambria_npec_device);
- platform_device_register(&cambria_npea_device);
-@@ -363,6 +383,10 @@
- cambria_optional_uart_data[1].membase = (void __iomem *)ioremap(0x53F80000, 0x0fff);
- cambria_optional_uart_data[1].irq = IRQ_IXP4XX_GPIO4;
-
-+ cambria_gpio_resources[0].start = (1 << 14);
-+ cambria_gpio_resources[0].end = cambria_gpio_resources[0].start;
-+
-+ platform_device_register(&cambria_gpio);
- platform_device_register(&cambria_optional_uart);
-
- platform_device_register(&cambria_npec_device);
+++ /dev/null
---- a/arch/arm/mach-ixp4xx/ixp4xx_npe.c
-+++ b/arch/arm/mach-ixp4xx/ixp4xx_npe.c
-@@ -592,6 +592,8 @@
- npe_reset(npe);
- #endif
-
-+ print_npe(KERN_INFO, npe, "firmware's license can be found in /usr/share/doc/LICENSE.IPL\n");
-+
- print_npe(KERN_INFO, npe, "firmware functionality 0x%X, "
- "revision 0x%X:%X\n", (image->id >> 16) & 0xFF,
- (image->id >> 8) & 0xFF, image->id & 0xFF);
+++ /dev/null
---- a/drivers/net/arm/ixp4xx_eth.c
-+++ b/drivers/net/arm/ixp4xx_eth.c
-@@ -165,14 +165,15 @@
- struct net_device *netdev;
- struct napi_struct napi;
- struct net_device_stats stat;
-- struct mii_if_info mii;
-+ struct mii_if_info mii[IXP4XX_ETH_PHY_MAX_ADDR];
- struct delayed_work mdio_thread;
- struct eth_plat_info *plat;
- buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
- struct desc *desc_tab; /* coherent */
- u32 desc_tab_phys;
- int id; /* logical port ID */
-- u16 mii_bmcr;
-+ u16 mii_bmcr[IXP4XX_ETH_PHY_MAX_ADDR];
-+ int phy_count;
- };
-
- /* NPE message structure */
-@@ -316,12 +317,13 @@
- spin_unlock_irqrestore(&mdio_lock, flags);
- }
-
--static void phy_reset(struct net_device *dev, int phy_id)
-+static void phy_reset(struct net_device *dev, int idx)
- {
- struct port *port = netdev_priv(dev);
-+ int phy_id = port->mii[idx].phy_id;
- int cycles = 0;
-
-- mdio_write(dev, phy_id, MII_BMCR, port->mii_bmcr | BMCR_RESET);
-+ mdio_write(dev, phy_id, MII_BMCR, port->mii_bmcr[idx] | BMCR_RESET);
-
- while (cycles < MAX_MII_RESET_RETRIES) {
- if (!(mdio_read(dev, phy_id, MII_BMCR) & BMCR_RESET)) {
-@@ -335,12 +337,12 @@
- cycles++;
- }
-
-- printk(KERN_ERR "%s: MII reset failed\n", dev->name);
-+ printk(KERN_ERR "%s: MII reset failed on PHY%2d\n", dev->name, phy_id);
- }
-
--static void eth_set_duplex(struct port *port)
-+static void eth_set_duplex(struct port *port, int full_duplex)
- {
-- if (port->mii.full_duplex)
-+ if (full_duplex)
- __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX,
- &port->regs->tx_control[0]);
- else
-@@ -348,7 +350,7 @@
- &port->regs->tx_control[0]);
- }
-
--
-+#if 0
- static void phy_check_media(struct port *port, int init)
- {
- if (mii_check_media(&port->mii, 1, init))
-@@ -367,7 +369,63 @@
- }
- }
- }
-+#else
-+static void phy_update_link(struct net_device *dev, int link)
-+{
-+ int prev_link = netif_carrier_ok(dev);
-+
-+ if (!prev_link && link) {
-+ printk(KERN_INFO "%s: link up\n", dev->name);
-+ netif_carrier_on(dev);
-+ } else if (prev_link && !link) {
-+ printk(KERN_INFO "%s: link down\n", dev->name);
-+ netif_carrier_off(dev);
-+ }
-+}
-+
-+static void phy_check_media(struct port *port, int init)
-+{
-+ struct net_device *dev = port->netdev;
-+
-+ if (port->phy_count == 1) {
-+ struct mii_if_info *mii = &port->mii[0];
-+
-+ if (mii_check_media(mii, 1, init))
-+ eth_set_duplex(port, mii->full_duplex);
-+
-+ if (mii->force_media) /* mii_check_media() doesn't work */
-+ phy_update_link(dev, mii_link_ok(mii));
-+ } else {
-+ int cur_link = 0;
-+ int i;
-+
-+ if (init)
-+ eth_set_duplex(port, 1);
-+
-+ for (i = 0; i < port->phy_count; i++)
-+ cur_link |= mii_link_ok(&port->mii[i]);
-+
-+ phy_update_link(dev, cur_link);
-+ }
-+}
-+#endif
-+
-+static void phy_power_down(struct net_device *dev, int idx)
-+{
-+ struct port *port = netdev_priv(dev);
-+ int phy_id = port->mii[idx].phy_id;
-+
-+ port->mii_bmcr[idx] = mdio_read(dev, phy_id, MII_BMCR) &
-+ ~(BMCR_RESET | BMCR_PDOWN);
-+ mdio_write(dev, phy_id, MII_BMCR, port->mii_bmcr[idx] | BMCR_PDOWN);
-+}
-+
-+static void phy_power_up(struct net_device *dev, int idx)
-+{
-+ struct port *port = netdev_priv(dev);
-
-+ mdio_write(dev, port->mii[idx].phy_id, MII_BMCR, port->mii_bmcr[idx]);
-+}
-
- static void mdio_thread(struct work_struct *work)
- {
-@@ -792,9 +850,12 @@
-
- if (!netif_running(dev))
- return -EINVAL;
-- err = generic_mii_ioctl(&port->mii, if_mii(req), cmd, &duplex_chg);
-+ if (port->phy_count != 1)
-+ return -EOPNOTSUPP;
-+
-+ err = generic_mii_ioctl(&port->mii[0], if_mii(req), cmd, &duplex_chg);
- if (duplex_chg)
-- eth_set_duplex(port);
-+ eth_set_duplex(port, port->mii[0].full_duplex);
- return err;
- }
-
-@@ -947,7 +1008,8 @@
- }
- }
-
-- mdio_write(dev, port->plat->phy, MII_BMCR, port->mii_bmcr);
-+ for (i = 0; i < port->phy_count; i++)
-+ phy_power_up(dev, i);
-
- memset(&msg, 0, sizeof(msg));
- msg.cmd = NPE_VLAN_SETRXQOSENTRY;
-@@ -1107,10 +1169,8 @@
- printk(KERN_CRIT "%s: unable to disable loopback\n",
- dev->name);
-
-- port->mii_bmcr = mdio_read(dev, port->plat->phy, MII_BMCR) &
-- ~(BMCR_RESET | BMCR_PDOWN); /* may have been altered */
-- mdio_write(dev, port->plat->phy, MII_BMCR,
-- port->mii_bmcr | BMCR_PDOWN);
-+ for (i = 0; i < port->phy_count; i++)
-+ phy_power_down(dev, i);
-
- if (!ports_open)
- qmgr_disable_irq(TXDONE_QUEUE);
-@@ -1120,6 +1180,42 @@
- return 0;
- }
-
-+static void eth_add_phy(struct net_device *dev, int phy_id)
-+{
-+ struct port *port = netdev_priv(dev);
-+ int i;
-+
-+ i = port->phy_count++;
-+
-+ port->mii[i].dev = dev;
-+ port->mii[i].mdio_read = mdio_read;
-+ port->mii[i].mdio_write = mdio_write;
-+ port->mii[i].phy_id = phy_id;
-+ port->mii[i].phy_id_mask = 0x1F;
-+ port->mii[i].reg_num_mask = 0x1F;
-+
-+ printk(KERN_INFO "%s: MII PHY %i on %s\n", dev->name, phy_id,
-+ npe_name(port->npe));
-+
-+ phy_reset(dev, i);
-+ phy_power_down(dev, i);
-+}
-+
-+static void eth_init_mii(struct net_device *dev)
-+{
-+ struct port *port = netdev_priv(dev);
-+
-+ if (port->plat->phy < IXP4XX_ETH_PHY_MAX_ADDR) {
-+ eth_add_phy(dev, port->plat->phy);
-+ } else {
-+ int i;
-+ for (i = 0; i < IXP4XX_ETH_PHY_MAX_ADDR; i++)
-+ if (port->plat->phy_mask & (1U << i))
-+ eth_add_phy(dev, i);
-+ }
-+
-+}
-+
- static int __devinit eth_init_one(struct platform_device *pdev)
- {
- struct port *port;
-@@ -1192,20 +1288,7 @@
- __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control);
- udelay(50);
-
-- port->mii.dev = dev;
-- port->mii.mdio_read = mdio_read;
-- port->mii.mdio_write = mdio_write;
-- port->mii.phy_id = plat->phy;
-- port->mii.phy_id_mask = 0x1F;
-- port->mii.reg_num_mask = 0x1F;
--
-- printk(KERN_INFO "%s: MII PHY %i on %s\n", dev->name, plat->phy,
-- npe_name(port->npe));
--
-- phy_reset(dev, plat->phy);
-- port->mii_bmcr = mdio_read(dev, plat->phy, MII_BMCR) &
-- ~(BMCR_RESET | BMCR_PDOWN);
-- mdio_write(dev, plat->phy, MII_BMCR, port->mii_bmcr | BMCR_PDOWN);
-+ eth_init_mii(dev);
-
- INIT_DELAYED_WORK(&port->mdio_thread, mdio_thread);
- return 0;
---- a/include/asm-arm/arch-ixp4xx/platform.h
-+++ b/include/asm-arm/arch-ixp4xx/platform.h
-@@ -95,12 +95,15 @@
- #define IXP4XX_ETH_NPEB 0x10
- #define IXP4XX_ETH_NPEC 0x20
-
-+#define IXP4XX_ETH_PHY_MAX_ADDR 32
-+
- /* Information about built-in Ethernet MAC interfaces */
- struct eth_plat_info {
- u8 phy; /* MII PHY ID, 0 - 31 */
- u8 rxq; /* configurable, currently 0 - 31 only */
- u8 txreadyq;
- u8 hwaddr[6];
-+ u32 phy_mask;
- };
-
- /* Information about built-in HSS (synchronous serial) interfaces */
+++ /dev/null
---- a/drivers/net/arm/ixp4xx_eth.c
-+++ b/drivers/net/arm/ixp4xx_eth.c
-@@ -322,8 +322,12 @@
- struct port *port = netdev_priv(dev);
- int phy_id = port->mii[idx].phy_id;
- int cycles = 0;
-+ u16 bmcr;
-
-- mdio_write(dev, phy_id, MII_BMCR, port->mii_bmcr[idx] | BMCR_RESET);
-+ /* reset the PHY */
-+ bmcr = mdio_read(dev, phy_id, MII_BMCR);
-+ bmcr |= BMCR_ANENABLE;
-+ mdio_write(dev, phy_id, MII_BMCR, bmcr | BMCR_RESET);
-
- while (cycles < MAX_MII_RESET_RETRIES) {
- if (!(mdio_read(dev, phy_id, MII_BMCR) & BMCR_RESET)) {
-@@ -331,13 +335,23 @@
- printk(KERN_DEBUG "%s: phy_reset() took %i cycles\n",
- dev->name, cycles);
- #endif
-- return;
-+ break;
- }
- udelay(1);
- cycles++;
- }
-
-- printk(KERN_ERR "%s: MII reset failed on PHY%2d\n", dev->name, phy_id);
-+ if (cycles == MAX_MII_RESET_RETRIES) {
-+ printk(KERN_ERR "%s: MII reset failed on PHY%2d\n", dev->name,
-+ phy_id);
-+ return;
-+ }
-+
-+ /* restart auto negotiation */
-+ bmcr = mdio_read(dev, phy_id, MII_BMCR);
-+ bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
-+ mdio_write(dev, phy_id, MII_BMCR, bmcr);
-+
- }
-
- static void eth_set_duplex(struct port *port, int full_duplex)
+++ /dev/null
-From cba5c286f3ea34ea4767fc00c705434a00fe2c37 Mon Sep 17 00:00:00 2001
-From: Imre Kaloz <kaloz@openwrt.org>
-Date: Thu, 26 Jun 2008 01:58:02 +0200
-Subject: [PATCH] Add support for the ethernet ports on IXP43x
-
----
- arch/arm/mach-ixp4xx/ixp4xx_npe.c | 6 +++---
- drivers/net/arm/ixp4xx_eth.c | 13 +++++++++----
- include/asm-arm/arch-ixp4xx/cpu.h | 2 ++
- include/asm-arm/arch-ixp4xx/ixp4xx-regs.h | 7 ++++---
- 4 files changed, 18 insertions(+), 10 deletions(-)
-
---- a/arch/arm/mach-ixp4xx/ixp4xx_npe.c
-+++ b/arch/arm/mach-ixp4xx/ixp4xx_npe.c
-@@ -575,8 +575,8 @@
- for (i = 0; i < image->size; i++)
- image->data[i] = swab32(image->data[i]);
-
-- if (!cpu_is_ixp46x() && ((image->id >> 28) & 0xF /* device ID */)) {
-- print_npe(KERN_INFO, npe, "IXP46x firmware ignored on "
-+ if (cpu_is_ixp42x() && ((image->id >> 28) & 0xF /* device ID */)) {
-+ print_npe(KERN_INFO, npe, "IXP46x/IXP43x firmware ignored on "
- "IXP42x\n");
- goto err;
- }
-@@ -598,7 +598,7 @@
- "revision 0x%X:%X\n", (image->id >> 16) & 0xFF,
- (image->id >> 8) & 0xFF, image->id & 0xFF);
-
-- if (!cpu_is_ixp46x()) {
-+ if (cpu_is_ixp42x()) {
- if (!npe->id)
- instr_size = NPE_A_42X_INSTR_SIZE;
- else
---- a/drivers/net/arm/ixp4xx_eth.c
-+++ b/drivers/net/arm/ixp4xx_eth.c
-@@ -32,6 +32,7 @@
- #include <linux/kernel.h>
- #include <linux/mii.h>
- #include <linux/platform_device.h>
-+#include <asm/arch/cpu.h>
- #include <asm/arch/npe.h>
- #include <asm/arch/qmgr.h>
-
-@@ -1338,12 +1339,16 @@
-
- static int __init eth_init_module(void)
- {
-- if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEB_ETH0))
-- return -ENOSYS;
-
-- /* All MII PHY accesses use NPE-B Ethernet registers */
- spin_lock_init(&mdio_lock);
-- mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
-+ if (!cpu_is_ixp43x())
-+ /* All MII PHY accesses use NPE-B Ethernet registers */
-+ mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
-+
-+ else
-+ /* IXP43x lacks NPE-B and uses NPE-C for MII PHY access */
-+ mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT;
-+
- __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control);
-
- return platform_driver_register(&drv);
---- a/include/asm-arm/arch-ixp4xx/cpu.h
-+++ b/include/asm-arm/arch-ixp4xx/cpu.h
-@@ -34,6 +34,8 @@
- val &= ~IXP4XX_FEATURE_RESERVED;
- if (!cpu_is_ixp46x())
- val &= ~IXP4XX_FEATURE_IXP46X_ONLY;
-+ if (cpu_is_ixp42x())
-+ val &= ~IXP4XX_FEATURE_IXP43X_46X;
-
- return val;
- }
---- a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
-+++ b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
-@@ -628,11 +628,12 @@
- #define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22)
- #define IXP4XX_FEATURE_RESERVED (0xFF << 24)
-
--#define IXP4XX_FEATURE_IXP46X_ONLY (IXP4XX_FEATURE_ECC_TIMESYNC | \
-+#define IXP4XX_FEATURE_IXP43X_46X (IXP4XX_FEATURE_ECC_TIMESYNC | \
- IXP4XX_FEATURE_USB_HOST | \
- IXP4XX_FEATURE_NPEA_ETH | \
-- IXP4XX_FEATURE_NPEB_ETH_1_TO_3 | \
-- IXP4XX_FEATURE_RSA | \
- IXP4XX_FEATURE_XSCALE_MAX_FREQ)
-
-+#define IXP4XX_FEATURE_IXP46X_ONLY (IXP4XX_FEATURE_NPEB_ETH_1_TO_3 | \
-+ IXP4XX_FEATURE_RSA)
-+
- #endif
+++ /dev/null
---- a/drivers/net/wan/Kconfig
-+++ b/drivers/net/wan/Kconfig
-@@ -336,6 +336,15 @@
-
- Say Y if your card supports this feature.
-
-+config IXP4XX_HSS
-+ tristate "IXP4xx HSS (synchronous serial port) support"
-+ depends on HDLC && ARM && ARCH_IXP4XX
-+ select IXP4XX_NPE
-+ select IXP4XX_QMGR
-+ help
-+ Say Y here if you want to use built-in HSS ports
-+ on IXP4xx processor.
-+
- config DLCI
- tristate "Frame Relay DLCI support"
- ---help---
---- a/drivers/net/wan/Makefile
-+++ b/drivers/net/wan/Makefile
-@@ -42,6 +42,7 @@
- obj-$(CONFIG_WANXL) += wanxl.o
- obj-$(CONFIG_PCI200SYN) += pci200syn.o
- obj-$(CONFIG_PC300TOO) += pc300too.o
-+obj-$(CONFIG_IXP4XX_HSS) += ixp4xx_hss.o
-
- clean-files := wanxlfw.inc
- $(obj)/wanxl.o: $(obj)/wanxlfw.inc
---- /dev/null
-+++ b/drivers/net/wan/ixp4xx_hss.c
-@@ -0,0 +1,2886 @@
-+/*
-+ * Intel IXP4xx HSS (synchronous serial port) driver for Linux
-+ *
-+ * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License
-+ * as published by the Free Software Foundation.
-+ */
-+
-+#include <linux/bitops.h>
-+#include <linux/cdev.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/dmapool.h>
-+#include <linux/fs.h>
-+#include <linux/io.h>
-+#include <linux/kernel.h>
-+#include <linux/hdlc.h>
-+#include <linux/platform_device.h>
-+#include <linux/poll.h>
-+#include <asm/arch/npe.h>
-+#include <asm/arch/qmgr.h>
-+
-+#define DEBUG_QUEUES 0
-+#define DEBUG_DESC 0
-+#define DEBUG_RX 0
-+#define DEBUG_TX 0
-+#define DEBUG_PKT_BYTES 0
-+#define DEBUG_CLOSE 0
-+#define DEBUG_FRAMER 0
-+
-+#define DRV_NAME "ixp4xx_hss"
-+
-+#define PKT_EXTRA_FLAGS 0 /* orig 1 */
-+#define TX_FRAME_SYNC_OFFSET 0 /* channelized */
-+#define PKT_NUM_PIPES 1 /* 1, 2 or 4 */
-+#define PKT_PIPE_FIFO_SIZEW 4 /* total 4 dwords per HSS */
-+
-+#define RX_DESCS 16 /* also length of all RX queues */
-+#define TX_DESCS 16 /* also length of all TX queues */
-+
-+#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
-+#define RX_SIZE (HDLC_MAX_MRU + 4) /* NPE needs more space */
-+#define MAX_CLOSE_WAIT 1000 /* microseconds */
-+#define HSS_COUNT 2
-+#define MIN_FRAME_SIZE 16 /* bits */
-+#define MAX_FRAME_SIZE 257 /* 256 bits + framing bit */
-+#define MAX_CHANNELS (MAX_FRAME_SIZE / 8)
-+#define MAX_CHAN_DEVICES 32
-+#define CHANNEL_HDLC 0xFE
-+#define CHANNEL_UNUSED 0xFF
-+
-+#define NAPI_WEIGHT 16
-+#define CHAN_RX_TRIGGER 16 /* 8 RX frames = 1 ms @ E1 */
-+#define CHAN_RX_FRAMES 64
-+#define MAX_CHAN_RX_BAD_SYNC (CHAN_RX_TRIGGER / 2 /* pairs */ - 3)
-+#define CHAN_TX_LIST_FRAMES 16 /* bytes/channel per list, 16 - 48 */
-+#define CHAN_TX_LISTS 8
-+#define CHAN_TX_FRAMES (CHAN_TX_LIST_FRAMES * CHAN_TX_LISTS)
-+#define CHAN_QUEUE_LEN 16 /* minimum possible */
-+
-+
-+/* Queue IDs */
-+#define HSS0_CHL_RXTRIG_QUEUE 12 /* orig size = 32 dwords */
-+#define HSS0_PKT_RX_QUEUE 13 /* orig size = 32 dwords */
-+#define HSS0_PKT_TX0_QUEUE 14 /* orig size = 16 dwords */
-+#define HSS0_PKT_TX1_QUEUE 15
-+#define HSS0_PKT_TX2_QUEUE 16
-+#define HSS0_PKT_TX3_QUEUE 17
-+#define HSS0_PKT_RXFREE0_QUEUE 18 /* orig size = 16 dwords */
-+#define HSS0_PKT_RXFREE1_QUEUE 19
-+#define HSS0_PKT_RXFREE2_QUEUE 20
-+#define HSS0_PKT_RXFREE3_QUEUE 21
-+#define HSS0_PKT_TXDONE_QUEUE 22 /* orig size = 64 dwords */
-+
-+#define HSS1_CHL_RXTRIG_QUEUE 10
-+#define HSS1_PKT_RX_QUEUE 0
-+#define HSS1_PKT_TX0_QUEUE 5
-+#define HSS1_PKT_TX1_QUEUE 6
-+#define HSS1_PKT_TX2_QUEUE 7
-+#define HSS1_PKT_TX3_QUEUE 8
-+#define HSS1_PKT_RXFREE0_QUEUE 1
-+#define HSS1_PKT_RXFREE1_QUEUE 2
-+#define HSS1_PKT_RXFREE2_QUEUE 3
-+#define HSS1_PKT_RXFREE3_QUEUE 4
-+#define HSS1_PKT_TXDONE_QUEUE 9
-+
-+#define NPE_PKT_MODE_HDLC 0
-+#define NPE_PKT_MODE_RAW 1
-+#define NPE_PKT_MODE_56KMODE 2
-+#define NPE_PKT_MODE_56KENDIAN_MSB 4
-+
-+/* PKT_PIPE_HDLC_CFG_WRITE flags */
-+#define PKT_HDLC_IDLE_ONES 0x1 /* default = flags */
-+#define PKT_HDLC_CRC_32 0x2 /* default = CRC-16 */
-+#define PKT_HDLC_MSB_ENDIAN 0x4 /* default = LE */
-+
-+
-+/* hss_config, PCRs */
-+/* Frame sync sampling, default = active low */
-+#define PCR_FRM_SYNC_ACTIVE_HIGH 0x40000000
-+#define PCR_FRM_SYNC_FALLINGEDGE 0x80000000
-+#define PCR_FRM_SYNC_RISINGEDGE 0xC0000000
-+
-+/* Frame sync pin: input (default) or output generated off a given clk edge */
-+#define PCR_FRM_SYNC_OUTPUT_FALLING 0x20000000
-+#define PCR_FRM_SYNC_OUTPUT_RISING 0x30000000
-+
-+/* Frame and data clock sampling on edge, default = falling */
-+#define PCR_FCLK_EDGE_RISING 0x08000000
-+#define PCR_DCLK_EDGE_RISING 0x04000000
-+
-+/* Clock direction, default = input */
-+#define PCR_SYNC_CLK_DIR_OUTPUT 0x02000000
-+
-+/* Generate/Receive frame pulses, default = enabled */
-+#define PCR_FRM_PULSE_DISABLED 0x01000000
-+
-+ /* Data rate is full (default) or half the configured clk speed */
-+#define PCR_HALF_CLK_RATE 0x00200000
-+
-+/* Invert data between NPE and HSS FIFOs? (default = no) */
-+#define PCR_DATA_POLARITY_INVERT 0x00100000
-+
-+/* TX/RX endianness, default = LSB */
-+#define PCR_MSB_ENDIAN 0x00080000
-+
-+/* Normal (default) / open drain mode (TX only) */
-+#define PCR_TX_PINS_OPEN_DRAIN 0x00040000
-+
-+/* No framing bit transmitted and expected on RX? (default = framing bit) */
-+#define PCR_SOF_NO_FBIT 0x00020000
-+
-+/* Drive data pins? */
-+#define PCR_TX_DATA_ENABLE 0x00010000
-+
-+/* Voice 56k type: drive the data pins low (default), high, high Z */
-+#define PCR_TX_V56K_HIGH 0x00002000
-+#define PCR_TX_V56K_HIGH_IMP 0x00004000
-+
-+/* Unassigned type: drive the data pins low (default), high, high Z */
-+#define PCR_TX_UNASS_HIGH 0x00000800
-+#define PCR_TX_UNASS_HIGH_IMP 0x00001000
-+
-+/* T1 @ 1.544MHz only: Fbit dictated in FIFO (default) or high Z */
-+#define PCR_TX_FB_HIGH_IMP 0x00000400
-+
-+/* 56k data endiannes - which bit unused: high (default) or low */
-+#define PCR_TX_56KE_BIT_0_UNUSED 0x00000200
-+
-+/* 56k data transmission type: 32/8 bit data (default) or 56K data */
-+#define PCR_TX_56KS_56K_DATA 0x00000100
-+
-+/* hss_config, cCR */
-+/* Number of packetized clients, default = 1 */
-+#define CCR_NPE_HFIFO_2_HDLC 0x04000000
-+#define CCR_NPE_HFIFO_3_OR_4HDLC 0x08000000
-+
-+/* default = no loopback */
-+#define CCR_LOOPBACK 0x02000000
-+
-+/* HSS number, default = 0 (first) */
-+#define CCR_SECOND_HSS 0x01000000
-+
-+
-+/* hss_config, clkCR: main:10, num:10, denom:12 */
-+#define CLK42X_SPEED_EXP ((0x3FF << 22) | ( 2 << 12) | 15) /*65 KHz*/
-+
-+#define CLK42X_SPEED_512KHZ (( 130 << 22) | ( 2 << 12) | 15)
-+#define CLK42X_SPEED_1536KHZ (( 43 << 22) | ( 18 << 12) | 47)
-+#define CLK42X_SPEED_1544KHZ (( 43 << 22) | ( 33 << 12) | 192)
-+#define CLK42X_SPEED_2048KHZ (( 32 << 22) | ( 34 << 12) | 63)
-+#define CLK42X_SPEED_4096KHZ (( 16 << 22) | ( 34 << 12) | 127)
-+#define CLK42X_SPEED_8192KHZ (( 8 << 22) | ( 34 << 12) | 255)
-+
-+#define CLK46X_SPEED_512KHZ (( 130 << 22) | ( 24 << 12) | 127)
-+#define CLK46X_SPEED_1536KHZ (( 43 << 22) | (152 << 12) | 383)
-+#define CLK46X_SPEED_1544KHZ (( 43 << 22) | ( 66 << 12) | 385)
-+#define CLK46X_SPEED_2048KHZ (( 32 << 22) | (280 << 12) | 511)
-+#define CLK46X_SPEED_4096KHZ (( 16 << 22) | (280 << 12) | 1023)
-+#define CLK46X_SPEED_8192KHZ (( 8 << 22) | (280 << 12) | 2047)
-+
-+
-+/* hss_config, LUT entries */
-+#define TDMMAP_UNASSIGNED 0
-+#define TDMMAP_HDLC 1 /* HDLC - packetized */
-+#define TDMMAP_VOICE56K 2 /* Voice56K - 7-bit channelized */
-+#define TDMMAP_VOICE64K 3 /* Voice64K - 8-bit channelized */
-+
-+/* offsets into HSS config */
-+#define HSS_CONFIG_TX_PCR 0x00 /* port configuration registers */
-+#define HSS_CONFIG_RX_PCR 0x04
-+#define HSS_CONFIG_CORE_CR 0x08 /* loopback control, HSS# */
-+#define HSS_CONFIG_CLOCK_CR 0x0C /* clock generator control */
-+#define HSS_CONFIG_TX_FCR 0x10 /* frame configuration registers */
-+#define HSS_CONFIG_RX_FCR 0x14
-+#define HSS_CONFIG_TX_LUT 0x18 /* channel look-up tables */
-+#define HSS_CONFIG_RX_LUT 0x38
-+
-+
-+/* NPE command codes */
-+/* writes the ConfigWord value to the location specified by offset */
-+#define PORT_CONFIG_WRITE 0x40
-+
-+/* triggers the NPE to load the contents of the configuration table */
-+#define PORT_CONFIG_LOAD 0x41
-+
-+/* triggers the NPE to return an HssErrorReadResponse message */
-+#define PORT_ERROR_READ 0x42
-+
-+/* reset NPE internal status and enable the HssChannelized operation */
-+#define CHAN_FLOW_ENABLE 0x43
-+#define CHAN_FLOW_DISABLE 0x44
-+#define CHAN_IDLE_PATTERN_WRITE 0x45
-+#define CHAN_NUM_CHANS_WRITE 0x46
-+#define CHAN_RX_BUF_ADDR_WRITE 0x47
-+#define CHAN_RX_BUF_CFG_WRITE 0x48
-+#define CHAN_TX_BLK_CFG_WRITE 0x49
-+#define CHAN_TX_BUF_ADDR_WRITE 0x4A
-+#define CHAN_TX_BUF_SIZE_WRITE 0x4B
-+#define CHAN_TSLOTSWITCH_ENABLE 0x4C
-+#define CHAN_TSLOTSWITCH_DISABLE 0x4D
-+
-+/* downloads the gainWord value for a timeslot switching channel associated
-+ with bypassNum */
-+#define CHAN_TSLOTSWITCH_GCT_DOWNLOAD 0x4E
-+
-+/* triggers the NPE to reset internal status and enable the HssPacketized
-+ operation for the flow specified by pPipe */
-+#define PKT_PIPE_FLOW_ENABLE 0x50
-+#define PKT_PIPE_FLOW_DISABLE 0x51
-+#define PKT_NUM_PIPES_WRITE 0x52
-+#define PKT_PIPE_FIFO_SIZEW_WRITE 0x53
-+#define PKT_PIPE_HDLC_CFG_WRITE 0x54
-+#define PKT_PIPE_IDLE_PATTERN_WRITE 0x55
-+#define PKT_PIPE_RX_SIZE_WRITE 0x56
-+#define PKT_PIPE_MODE_WRITE 0x57
-+
-+/* HDLC packet status values - desc->status */
-+#define ERR_SHUTDOWN 1 /* stop or shutdown occurrance */
-+#define ERR_HDLC_ALIGN 2 /* HDLC alignment error */
-+#define ERR_HDLC_FCS 3 /* HDLC Frame Check Sum error */
-+#define ERR_RXFREE_Q_EMPTY 4 /* RX-free queue became empty while receiving
-+ this packet (if buf_len < pkt_len) */
-+#define ERR_HDLC_TOO_LONG 5 /* HDLC frame size too long */
-+#define ERR_HDLC_ABORT 6 /* abort sequence received */
-+#define ERR_DISCONNECTING 7 /* disconnect is in progress */
-+
-+
-+enum mode {MODE_HDLC = 0, MODE_RAW, MODE_G704};
-+enum error_bit {TX_ERROR_BIT = 0, RX_ERROR_BIT = 1};
-+enum alignment { NOT_ALIGNED = 0, EVEN_FIRST, ODD_FIRST };
-+
-+#ifdef __ARMEB__
-+typedef struct sk_buff buffer_t;
-+#define free_buffer dev_kfree_skb
-+#define free_buffer_irq dev_kfree_skb_irq
-+#else
-+typedef void buffer_t;
-+#define free_buffer kfree
-+#define free_buffer_irq kfree
-+#endif
-+
-+struct chan_device {
-+ struct cdev cdev;
-+ struct device *dev;
-+ struct port *port;
-+ unsigned int open_count, excl_open;
-+ unsigned int tx_first, tx_count, rx_first, rx_count; /* bytes */
-+ unsigned long errors_bitmap;
-+ u8 id, chan_count;
-+ u8 log_channels[MAX_CHANNELS];
-+};
-+
-+struct port {
-+ struct device *dev;
-+ struct npe *npe;
-+ struct net_device *netdev;
-+ struct napi_struct napi;
-+ struct hss_plat_info *plat;
-+ buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
-+ struct desc *desc_tab; /* coherent */
-+ u32 desc_tab_phys;
-+ unsigned int id;
-+ atomic_t chan_tx_irq_number, chan_rx_irq_number;
-+ wait_queue_head_t chan_tx_waitq, chan_rx_waitq;
-+ u8 hdlc_cfg;
-+
-+ /* the following fields must be protected by npe_lock */
-+ enum mode mode;
-+ unsigned int clock_type, clock_rate, loopback;
-+ unsigned int frame_size, frame_sync_offset;
-+
-+ struct chan_device *chan_devices[MAX_CHAN_DEVICES];
-+ u8 *chan_buf;
-+ u32 chan_tx_buf_phys, chan_rx_buf_phys;
-+ unsigned int chan_open_count, hdlc_open;
-+ unsigned int chan_started, initialized, just_set_offset;
-+ enum alignment aligned, carrier;
-+ unsigned int chan_last_rx, chan_last_tx;
-+ /* assigned channels, may be invalid with given frame length or mode */
-+ u8 channels[MAX_CHANNELS];
-+ int msg_count;
-+};
-+
-+/* NPE message structure */
-+struct msg {
-+#ifdef __ARMEB__
-+ u8 cmd, unused, hss_port, index;
-+ union {
-+ struct { u8 data8a, data8b, data8c, data8d; };
-+ struct { u16 data16a, data16b; };
-+ struct { u32 data32; };
-+ };
-+#else
-+ u8 index, hss_port, unused, cmd;
-+ union {
-+ struct { u8 data8d, data8c, data8b, data8a; };
-+ struct { u16 data16b, data16a; };
-+ struct { u32 data32; };
-+ };
-+#endif
-+};
-+
-+/* HDLC packet descriptor */
-+struct desc {
-+ u32 next; /* pointer to next buffer, unused */
-+
-+#ifdef __ARMEB__
-+ u16 buf_len; /* buffer length */
-+ u16 pkt_len; /* packet length */
-+ u32 data; /* pointer to data buffer in RAM */
-+ u8 status;
-+ u8 error_count;
-+ u16 __reserved;
-+#else
-+ u16 pkt_len; /* packet length */
-+ u16 buf_len; /* buffer length */
-+ u32 data; /* pointer to data buffer in RAM */
-+ u16 __reserved;
-+ u8 error_count;
-+ u8 status;
-+#endif
-+ u32 __reserved1[4];
-+};
-+
-+
-+#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
-+ (n) * sizeof(struct desc))
-+#define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
-+
-+#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
-+ ((n) + RX_DESCS) * sizeof(struct desc))
-+#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
-+
-+#define chan_tx_buf_len(port) (port->frame_size / 8 * CHAN_TX_FRAMES)
-+#define chan_tx_lists_len(port) (port->frame_size / 8 * CHAN_TX_LISTS * \
-+ sizeof(u32))
-+#define chan_rx_buf_len(port) (port->frame_size / 8 * CHAN_RX_FRAMES)
-+
-+#define chan_tx_buf(port) ((port)->chan_buf)
-+#define chan_tx_lists(port) (chan_tx_buf(port) + chan_tx_buf_len(port))
-+#define chan_rx_buf(port) (chan_tx_lists(port) + chan_tx_lists_len(port))
-+
-+#define chan_tx_lists_phys(port) ((port)->chan_tx_buf_phys + \
-+ chan_tx_buf_len(port))
-+
-+static int hss_prepare_chan(struct port *port);
-+void hss_chan_stop(struct port *port);
-+
-+/*****************************************************************************
-+ * global variables
-+ ****************************************************************************/
-+
-+static struct class *hss_class;
-+static int chan_major;
-+static int ports_open;
-+static struct dma_pool *dma_pool;
-+static spinlock_t npe_lock;
-+
-+static const struct {
-+ int tx, txdone, rx, rxfree, chan;
-+}queue_ids[2] = {{HSS0_PKT_TX0_QUEUE, HSS0_PKT_TXDONE_QUEUE, HSS0_PKT_RX_QUEUE,
-+ HSS0_PKT_RXFREE0_QUEUE, HSS0_CHL_RXTRIG_QUEUE},
-+ {HSS1_PKT_TX0_QUEUE, HSS1_PKT_TXDONE_QUEUE, HSS1_PKT_RX_QUEUE,
-+ HSS1_PKT_RXFREE0_QUEUE, HSS1_CHL_RXTRIG_QUEUE},
-+};
-+
-+/*****************************************************************************
-+ * utility functions
-+ ****************************************************************************/
-+
-+static inline struct port* dev_to_port(struct net_device *dev)
-+{
-+ return dev_to_hdlc(dev)->priv;
-+}
-+
-+static inline struct chan_device* inode_to_chan_dev(struct inode *inode)
-+{
-+ return container_of(inode->i_cdev, struct chan_device, cdev);
-+}
-+
-+#ifndef __ARMEB__
-+static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
-+{
-+ int i;
-+ for (i = 0; i < cnt; i++)
-+ dest[i] = swab32(src[i]);
-+}
-+#endif
-+
-+static int get_number(const char **buf, size_t *len, unsigned int *ptr,
-+ unsigned int min, unsigned int max)
-+{
-+ char *endp;
-+ unsigned long val = simple_strtoul(*buf, &endp, 10);
-+
-+ if (endp == *buf || endp - *buf > *len || val < min || val > max)
-+ return -EINVAL;
-+ *len -= endp - *buf;
-+ *buf = endp;
-+ *ptr = val;
-+ return 0;
-+}
-+
-+static int parse_channels(const char **buf, size_t *len, u8 *channels)
-+{
-+ unsigned int ch, next = 0;
-+
-+ if (*len && (*buf)[*len - 1] == '\n')
-+ (*len)--;
-+
-+ memset(channels, 0, MAX_CHANNELS);
-+
-+ if (!*len)
-+ return 0;
-+
-+ /* Format: "A,B-C,...", A > B > C */
-+ while (1) {
-+ if (get_number(buf, len, &ch, next, MAX_CHANNELS - 1))
-+ return -EINVAL;
-+ channels[ch] = 1;
-+ next = ch + 1;
-+ if (!*len)
-+ break;
-+ if (**buf == ',') {
-+ (*buf)++;
-+ (*len)--;
-+ continue;
-+ }
-+ if (**buf != '-')
-+ return -EINVAL;
-+ (*buf)++;
-+ (*len)--;
-+ if (get_number(buf, len, &ch, next, MAX_CHANNELS - 1))
-+ return -EINVAL;
-+ while (next <= ch)
-+ channels[next++] = 1;
-+ if (!*len)
-+ break;
-+ if (**buf != ',')
-+ return -EINVAL;
-+ (*buf)++;
-+ (*len)--;
-+ }
-+ return 1;
-+}
-+
-+static size_t print_channels(struct port *port, char *buf, u8 id)
-+{
-+ unsigned int ch, cnt = 0;
-+ size_t len = 0;
-+
-+ for (ch = 0; ch < MAX_CHANNELS; ch++)
-+ if (port->channels[ch] == id) {
-+ if (cnt == 0) {
-+ sprintf(buf + len, "%s%u", len ? "," : "", ch);
-+ len += strlen(buf + len);
-+ }
-+ cnt++;
-+ } else {
-+ if (cnt > 1) {
-+ sprintf(buf + len, "-%u", ch - 1);
-+ len += strlen(buf + len);
-+ }
-+ cnt = 0;
-+ }
-+ if (cnt > 1) {
-+ sprintf(buf + len, "-%u", ch - 1);
-+ len += strlen(buf + len);
-+ }
-+
-+ buf[len++] = '\n';
-+ return len;
-+}
-+
-+static inline unsigned int sub_offset(unsigned int a, unsigned int b,
-+ unsigned int modulo)
-+{
-+ return (modulo /* make sure the result >= 0 */ + a - b) % modulo;
-+}
-+
-+/*****************************************************************************
-+ * HSS access
-+ ****************************************************************************/
-+
-+static void hss_config_load(struct port *port)
-+{
-+ struct msg msg;
-+
-+ do {
-+ memset(&msg, 0, sizeof(msg));
-+ msg.cmd = PORT_CONFIG_LOAD;
-+ msg.hss_port = port->id;
-+ if (npe_send_message(port->npe, &msg, "HSS_LOAD_CONFIG"))
-+ break;
-+ if (npe_recv_message(port->npe, &msg, "HSS_LOAD_CONFIG"))
-+ break;
-+
-+ /* HSS_LOAD_CONFIG for port #1 returns port_id = #4 */
-+ if (msg.cmd != PORT_CONFIG_LOAD || msg.data32)
-+ break;
-+
-+ /* HDLC may stop working without this */
-+ npe_recv_message(port->npe, &msg, "FLUSH_IT");
-+ return;
-+ } while (0);
-+
-+ printk(KERN_CRIT "HSS-%i: unable to reload HSS configuration\n",
-+ port->id);
-+ BUG();
-+}
-+
-+static void hss_config_set_pcr(struct port *port)
-+{
-+ struct msg msg;
-+
-+ do {
-+ memset(&msg, 0, sizeof(msg));
-+ msg.cmd = PORT_CONFIG_WRITE;
-+ msg.hss_port = port->id;
-+ msg.index = HSS_CONFIG_TX_PCR;
-+ msg.data32 = PCR_FRM_SYNC_OUTPUT_RISING | PCR_MSB_ENDIAN |
-+ PCR_TX_DATA_ENABLE;
-+ if (port->frame_size % 8 == 0)
-+ msg.data32 |= PCR_SOF_NO_FBIT;
-+ if (port->clock_type == CLOCK_INT)
-+ msg.data32 |= PCR_SYNC_CLK_DIR_OUTPUT;
-+ if (npe_send_message(port->npe, &msg, "HSS_SET_TX_PCR"))
-+ break;
-+
-+ msg.index = HSS_CONFIG_RX_PCR;
-+ msg.data32 ^= PCR_TX_DATA_ENABLE | PCR_DCLK_EDGE_RISING;
-+ if (npe_send_message(port->npe, &msg, "HSS_SET_RX_PCR"))
-+ break;
-+ return;
-+ } while (0);
-+
-+ printk(KERN_CRIT "HSS-%i: unable to set HSS PCR registers\n", port->id);
-+ BUG();
-+}
-+
-+static void hss_config_set_hdlc_cfg(struct port *port)
-+{
-+ struct msg msg;
-+
-+ memset(&msg, 0, sizeof(msg));
-+ msg.cmd = PKT_PIPE_HDLC_CFG_WRITE;
-+ msg.hss_port = port->id;
-+ msg.data8a = port->hdlc_cfg; /* rx_cfg */
-+ msg.data8b = port->hdlc_cfg | (PKT_EXTRA_FLAGS << 3); /* tx_cfg */
-+ if (npe_send_message(port->npe, &msg, "HSS_SET_HDLC_CFG")) {
-+ printk(KERN_CRIT "HSS-%i: unable to set HSS HDLC"
-+ " configuration\n", port->id);
-+ BUG();
-+ }
-+}
-+
-+static void hss_config_set_core(struct port *port)
-+{
-+ struct msg msg;
-+
-+ memset(&msg, 0, sizeof(msg));
-+ msg.cmd = PORT_CONFIG_WRITE;
-+ msg.hss_port = port->id;
-+ msg.index = HSS_CONFIG_CORE_CR;
-+ msg.data32 = (port->loopback ? CCR_LOOPBACK : 0) |
-+ (port->id ? CCR_SECOND_HSS : 0);
-+ if (npe_send_message(port->npe, &msg, "HSS_SET_CORE_CR")) {
-+ printk(KERN_CRIT "HSS-%i: unable to set HSS core control"
-+ " register\n", port->id);
-+ BUG();
-+ }
-+}
-+
-+static void hss_config_set_line(struct port *port)
-+{
-+ struct msg msg;
-+
-+ hss_config_set_pcr(port);
-+ hss_config_set_core(port);
-+
-+ memset(&msg, 0, sizeof(msg));
-+ msg.cmd = PORT_CONFIG_WRITE;
-+ msg.hss_port = port->id;
-+ msg.index = HSS_CONFIG_CLOCK_CR;
-+ msg.data32 = CLK42X_SPEED_2048KHZ /* FIXME */;
-+ if (npe_send_message(port->npe, &msg, "HSS_SET_CLOCK_CR")) {
-+ printk(KERN_CRIT "HSS-%i: unable to set HSS clock control"
-+ " register\n", port->id);
-+ BUG();
-+ }
-+}
-+
-+static void hss_config_set_rx_frame(struct port *port)
-+{
-+ struct msg msg;
-+
-+ memset(&msg, 0, sizeof(msg));
-+ msg.cmd = PORT_CONFIG_WRITE;
-+ msg.hss_port = port->id;
-+ msg.index = HSS_CONFIG_RX_FCR;
-+ msg.data16a = port->frame_sync_offset;
-+ msg.data16b = port->frame_size - 1;
-+ if (npe_send_message(port->npe, &msg, "HSS_SET_RX_FCR")) {
-+ printk(KERN_CRIT "HSS-%i: unable to set HSS RX frame size"
-+ " and offset\n", port->id);
-+ BUG();
-+ }
-+}
-+
-+static void hss_config_set_frame(struct port *port)
-+{
-+ struct msg msg;
-+
-+ memset(&msg, 0, sizeof(msg));
-+ msg.cmd = PORT_CONFIG_WRITE;
-+ msg.hss_port = port->id;
-+ msg.index = HSS_CONFIG_TX_FCR;
-+ msg.data16a = TX_FRAME_SYNC_OFFSET;
-+ msg.data16b = port->frame_size - 1;
-+ if (npe_send_message(port->npe, &msg, "HSS_SET_TX_FCR")) {
-+ printk(KERN_CRIT "HSS-%i: unable to set HSS TX frame size"
-+ " and offset\n", port->id);
-+ BUG();
-+ }
-+ hss_config_set_rx_frame(port);
-+}
-+
-+static void hss_config_set_lut(struct port *port)
-+{
-+ struct msg msg;
-+ int chan_count = 0, log_chan = 0, i, ch;
-+ u32 lut[MAX_CHANNELS / 4];
-+
-+ memset(lut, 0, sizeof(lut));
-+ for (i = 0; i < MAX_CHAN_DEVICES; i++)
-+ if (port->chan_devices[i])
-+ port->chan_devices[i]->chan_count = 0;
-+
-+ memset(&msg, 0, sizeof(msg));
-+ msg.cmd = PORT_CONFIG_WRITE;
-+ msg.hss_port = port->id;
-+
-+ for (ch = 0; ch < MAX_CHANNELS; ch++) {
-+ struct chan_device *chdev = NULL;
-+ unsigned int entry;
-+
-+ if (port->channels[ch] < MAX_CHAN_DEVICES /* assigned */)
-+ chdev = port->chan_devices[port->channels[ch]];
-+
-+ if (port->mode == MODE_G704 && ch == 0)
-+ entry = TDMMAP_VOICE64K; /* PCM-31 pattern */
-+ else if (port->mode == MODE_HDLC ||
-+ port->channels[ch] == CHANNEL_HDLC)
-+ entry = TDMMAP_HDLC;
-+ else if (chdev && chdev->open_count) {
-+ entry = TDMMAP_VOICE64K;
-+ chdev->log_channels[chdev->chan_count++] = log_chan;
-+ } else
-+ entry = TDMMAP_UNASSIGNED;
-+ if (entry == TDMMAP_VOICE64K) {
-+ chan_count++;
-+ log_chan++;
-+ }
-+
-+ msg.data32 >>= 2;
-+ msg.data32 |= entry << 30;
-+
-+ if (ch % 16 == 15) {
-+ msg.index = HSS_CONFIG_TX_LUT + ((ch / 4) & ~3);
-+ if (npe_send_message(port->npe, &msg, "HSS_SET_TX_LUT"))
-+ break;
-+
-+ msg.index += HSS_CONFIG_RX_LUT - HSS_CONFIG_TX_LUT;
-+ if (npe_send_message(port->npe, &msg, "HSS_SET_RX_LUT"))
-+ break;
-+ }
-+ }
-+ if (ch != MAX_CHANNELS) {
-+ printk(KERN_CRIT "HSS-%i: unable to set HSS channel look-up"
-+ " table\n", port->id);
-+ BUG();
-+ }
-+
-+ hss_config_set_frame(port);
-+
-+ if (!chan_count)
-+ return;
-+
-+ memset(&msg, 0, sizeof(msg));
-+ msg.cmd = CHAN_NUM_CHANS_WRITE;
-+ msg.hss_port = port->id;
-+ msg.data8a = chan_count;
-+ if (npe_send_message(port->npe, &msg, "CHAN_NUM_CHANS_WRITE")) {
-+ printk(KERN_CRIT "HSS-%i: unable to set HSS channel count\n",
-+ port->id);
-+ BUG();
-+ }
-+
-+ /* don't leak data */
-+ // FIXME memset(chan_tx_buf(port), 0, CHAN_TX_FRAMES * chan_count);
-+ if (port->mode == MODE_G704) /* G.704 PCM-31 sync pattern */
-+ for (i = 0; i < CHAN_TX_FRAMES; i += 4)
-+ *(u32*)(chan_tx_buf(port) + i) = 0x9BDF9BDF;
-+
-+ for (i = 0; i < CHAN_TX_LISTS; i++) {
-+ u32 phys = port->chan_tx_buf_phys + i * CHAN_TX_LIST_FRAMES;
-+ u32 *list = ((u32 *)chan_tx_lists(port)) + i * chan_count;
-+ for (ch = 0; ch < chan_count; ch++)
-+ list[ch] = phys + ch * CHAN_TX_FRAMES;
-+ }
-+ dma_sync_single(port->dev, port->chan_tx_buf_phys,
-+ chan_tx_buf_len(port) + chan_tx_lists_len(port),
-+ DMA_TO_DEVICE);
-+}
-+
-+static u32 hss_config_get_status(struct port *port)
-+{
-+ struct msg msg;
-+
-+ do {
-+ memset(&msg, 0, sizeof(msg));
-+ msg.cmd = PORT_ERROR_READ;
-+ msg.hss_port = port->id;
-+ if (npe_send_message(port->npe, &msg, "PORT_ERROR_READ"))
-+ break;
-+ if (npe_recv_message(port->npe, &msg, "PORT_ERROR_READ"))
-+ break;
-+
-+ return msg.data32;
-+ } while (0);
-+
-+ printk(KERN_CRIT "HSS-%i: unable to read HSS status\n", port->id);
-+ BUG();
-+}
-+
-+static void hss_config_start_chan(struct port *port)
-+{
-+ struct msg msg;
-+
-+ port->chan_last_tx = 0;
-+ port->chan_last_rx = 0;
-+
-+ do {
-+ memset(&msg, 0, sizeof(msg));
-+ msg.cmd = CHAN_RX_BUF_ADDR_WRITE;
-+ msg.hss_port = port->id;
-+ msg.data32 = port->chan_rx_buf_phys;
-+ if (npe_send_message(port->npe, &msg, "CHAN_RX_BUF_ADDR_WRITE"))
-+ break;
-+
-+ memset(&msg, 0, sizeof(msg));
-+ msg.cmd = CHAN_TX_BUF_ADDR_WRITE;
-+ msg.hss_port = port->id;
-+ msg.data32 = chan_tx_lists_phys(port);
-+ if (npe_send_message(port->npe, &msg, "CHAN_TX_BUF_ADDR_WRITE"))
-+ break;
-+
-+ memset(&msg, 0, sizeof(msg));
-+ msg.cmd = CHAN_FLOW_ENABLE;
-+ msg.hss_port = port->id;
-+ if (npe_send_message(port->npe, &msg, "CHAN_FLOW_ENABLE"))
-+ break;
-+ port->chan_started = 1;
-+ return;
-+ } while (0);
-+
-+ printk(KERN_CRIT "HSS-%i: unable to start channelized flow\n",
-+ port->id);
-+ BUG();
-+}
-+
-+static void hss_config_stop_chan(struct port *port)
-+{
-+ struct msg msg;
-+
-+ if (!port->chan_started)
-+ return;
-+
-+ memset(&msg, 0, sizeof(msg));
-+ msg.cmd = CHAN_FLOW_DISABLE;
-+ msg.hss_port = port->id;
-+ if (npe_send_message(port->npe, &msg, "CHAN_FLOW_DISABLE")) {
-+ printk(KERN_CRIT "HSS-%i: unable to stop channelized flow\n",
-+ port->id);
-+ BUG();
-+ }
-+ hss_config_get_status(port); /* make sure it's halted */
-+}
-+
-+static void hss_config_start_hdlc(struct port *port)
-+{
-+ struct msg msg;
-+
-+ memset(&msg, 0, sizeof(msg));
-+ msg.cmd = PKT_PIPE_FLOW_ENABLE;
-+ msg.hss_port = port->id;
-+ msg.data32 = 0;
-+ if (npe_send_message(port->npe, &msg, "HSS_ENABLE_PKT_PIPE")) {
-+ printk(KERN_CRIT "HSS-%i: unable to stop packetized flow\n",
-+ port->id);
-+ BUG();
-+ }
-+}
-+
-+static void hss_config_stop_hdlc(struct port *port)
-+{
-+ struct msg msg;
-+
-+ memset(&msg, 0, sizeof(msg));
-+ msg.cmd = PKT_PIPE_FLOW_DISABLE;
-+ msg.hss_port = port->id;
-+ if (npe_send_message(port->npe, &msg, "HSS_DISABLE_PKT_PIPE")) {
-+ printk(KERN_CRIT "HSS-%i: unable to stop packetized flow\n",
-+ port->id);
-+ BUG();
-+ }
-+ hss_config_get_status(port); /* make sure it's halted */
-+}
-+
-+static int hss_config_load_firmware(struct port *port)
-+{
-+ struct msg msg;
-+
-+ if (port->initialized)
-+ return 0;
-+
-+ if (!npe_running(port->npe)) {
-+ int err;
-+ if ((err = npe_load_firmware(port->npe, npe_name(port->npe),
-+ port->dev)))
-+ return err;
-+ }
-+
-+ do {
-+ /* HSS main configuration */
-+ hss_config_set_line(port);
-+
-+ hss_config_set_frame(port);
-+
-+ /* HDLC mode configuration */
-+ memset(&msg, 0, sizeof(msg));
-+ msg.cmd = PKT_NUM_PIPES_WRITE;
-+ msg.hss_port = port->id;
-+ msg.data8a = PKT_NUM_PIPES;
-+ if (npe_send_message(port->npe, &msg, "HSS_SET_PKT_PIPES"))
-+ break;
-+
-+ msg.cmd = PKT_PIPE_FIFO_SIZEW_WRITE;
-+ msg.data8a = PKT_PIPE_FIFO_SIZEW;
-+ if (npe_send_message(port->npe, &msg, "HSS_SET_PKT_FIFO"))
-+ break;
-+
-+ msg.cmd = PKT_PIPE_MODE_WRITE;
-+ msg.data8a = NPE_PKT_MODE_HDLC;
-+ /* msg.data8b = inv_mask */
-+ /* msg.data8c = or_mask */
-+ if (npe_send_message(port->npe, &msg, "HSS_SET_PKT_MODE"))
-+ break;
-+
-+ msg.cmd = PKT_PIPE_RX_SIZE_WRITE;
-+ msg.data16a = HDLC_MAX_MRU; /* including CRC */
-+ if (npe_send_message(port->npe, &msg, "HSS_SET_PKT_RX_SIZE"))
-+ break;
-+
-+ msg.cmd = PKT_PIPE_IDLE_PATTERN_WRITE;
-+ msg.data32 = 0x7F7F7F7F; /* ??? FIXME */
-+ if (npe_send_message(port->npe, &msg, "HSS_SET_PKT_IDLE"))
-+ break;
-+
-+ /* Channelized operation settings */
-+ memset(&msg, 0, sizeof(msg));
-+ msg.cmd = CHAN_TX_BLK_CFG_WRITE;
-+ msg.hss_port = port->id;
-+ msg.data8b = (CHAN_TX_LIST_FRAMES & ~7) / 2;
-+ msg.data8a = msg.data8b / 4;
-+ msg.data8d = CHAN_TX_LIST_FRAMES - msg.data8b;
-+ msg.data8c = msg.data8d / 4;
-+ if (npe_send_message(port->npe, &msg, "CHAN_TX_BLK_CFG_WRITE"))
-+ break;
-+
-+ memset(&msg, 0, sizeof(msg));
-+ msg.cmd = CHAN_RX_BUF_CFG_WRITE;
-+ msg.hss_port = port->id;
-+ msg.data8a = CHAN_RX_TRIGGER / 8;
-+ msg.data8b = CHAN_RX_FRAMES;
-+ if (npe_send_message(port->npe, &msg, "CHAN_RX_BUF_CFG_WRITE"))
-+ break;
-+
-+ memset(&msg, 0, sizeof(msg));
-+ msg.cmd = CHAN_TX_BUF_SIZE_WRITE;
-+ msg.hss_port = port->id;
-+ msg.data8a = CHAN_TX_LISTS;
-+ if (npe_send_message(port->npe, &msg, "CHAN_TX_BUF_SIZE_WRITE"))
-+ break;
-+
-+ port->initialized = 1;
-+ return 0;
-+ } while (0);
-+
-+ printk(KERN_CRIT "HSS-%i: unable to start HSS operation\n", port->id);
-+ BUG();
-+}
-+
-+/*****************************************************************************
-+ * packetized (HDLC) operation
-+ ****************************************************************************/
-+
-+static inline void debug_pkt(struct net_device *dev, const char *func,
-+ u8 *data, int len)
-+{
-+#if DEBUG_PKT_BYTES
-+ int i;
-+
-+ printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len);
-+ for (i = 0; i < len; i++) {
-+ if (i >= DEBUG_PKT_BYTES)
-+ break;
-+ printk(KERN_DEBUG "%s%02X", !(i % 4) ? " " : "", data[i]);
-+ }
-+ printk(KERN_DEBUG "\n");
-+#endif
-+}
-+
-+
-+static inline void debug_desc(u32 phys, struct desc *desc)
-+{
-+#if DEBUG_DESC
-+ printk(KERN_DEBUG "%X: %X %3X %3X %08X %X %X\n",
-+ phys, desc->next, desc->buf_len, desc->pkt_len,
-+ desc->data, desc->status, desc->error_count);
-+#endif
-+}
-+
-+static inline void debug_queue(unsigned int queue, int is_get, u32 phys)
-+{
-+#if DEBUG_QUEUES
-+ static struct {
-+ int queue;
-+ char *name;
-+ } names[] = {
-+ { HSS0_PKT_TX0_QUEUE, "TX#0 " },
-+ { HSS0_PKT_TXDONE_QUEUE, "TX-done#0 " },
-+ { HSS0_PKT_RX_QUEUE, "RX#0 " },
-+ { HSS0_PKT_RXFREE0_QUEUE, "RX-free#0 " },
-+ { HSS1_PKT_TX0_QUEUE, "TX#1 " },
-+ { HSS1_PKT_TXDONE_QUEUE, "TX-done#1 " },
-+ { HSS1_PKT_RX_QUEUE, "RX#1 " },
-+ { HSS1_PKT_RXFREE0_QUEUE, "RX-free#1 " },
-+ };
-+ int i;
-+
-+ for (i = 0; i < ARRAY_SIZE(names); i++)
-+ if (names[i].queue == queue)
-+ break;
-+
-+ printk(KERN_DEBUG "Queue %i %s%s %X\n", queue,
-+ i < ARRAY_SIZE(names) ? names[i].name : "",
-+ is_get ? "->" : "<-", phys);
-+#endif
-+}
-+
-+static inline u32 queue_get_entry(unsigned int queue)
-+{
-+ u32 phys = qmgr_get_entry(queue);
-+ debug_queue(queue, 1, phys);
-+ return phys;
-+}
-+
-+static inline int queue_get_desc(unsigned int queue, struct port *port,
-+ int is_tx)
-+{
-+ u32 phys, tab_phys, n_desc;
-+ struct desc *tab;
-+
-+ if (!(phys = queue_get_entry(queue)))
-+ return -1;
-+
-+ BUG_ON(phys & 0x1F);
-+ tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
-+ tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
-+ n_desc = (phys - tab_phys) / sizeof(struct desc);
-+ BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
-+ debug_desc(phys, &tab[n_desc]);
-+ BUG_ON(tab[n_desc].next);
-+ return n_desc;
-+}
-+
-+static inline void queue_put_desc(unsigned int queue, u32 phys,
-+ struct desc *desc)
-+{
-+ debug_queue(queue, 0, phys);
-+ debug_desc(phys, desc);
-+ BUG_ON(phys & 0x1F);
-+ qmgr_put_entry(queue, phys);
-+ BUG_ON(qmgr_stat_overflow(queue));
-+}
-+
-+
-+static inline void dma_unmap_tx(struct port *port, struct desc *desc)
-+{
-+#ifdef __ARMEB__
-+ dma_unmap_single(&port->netdev->dev, desc->data,
-+ desc->buf_len, DMA_TO_DEVICE);
-+#else
-+ dma_unmap_single(&port->netdev->dev, desc->data & ~3,
-+ ALIGN((desc->data & 3) + desc->buf_len, 4),
-+ DMA_TO_DEVICE);
-+#endif
-+}
-+
-+
-+static void hss_hdlc_set_carrier(void *pdev, int carrier)
-+{
-+ struct net_device *netdev = pdev;
-+ struct port *port = dev_to_port(netdev);
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&npe_lock, flags);
-+ port->carrier = carrier;
-+ if (!port->loopback) {
-+ if (carrier)
-+ netif_carrier_on(netdev);
-+ else
-+ netif_carrier_off(netdev);
-+ }
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+}
-+
-+static void hss_hdlc_rx_irq(void *pdev)
-+{
-+ struct net_device *dev = pdev;
-+ struct port *port = dev_to_port(dev);
-+
-+#if DEBUG_RX
-+ printk(KERN_DEBUG "%s: hss_hdlc_rx_irq\n", dev->name);
-+#endif
-+ qmgr_disable_irq(queue_ids[port->id].rx);
-+ netif_rx_schedule(dev, &port->napi);
-+}
-+
-+static int hss_hdlc_poll(struct napi_struct *napi, int budget)
-+{
-+ struct port *port = container_of(napi, struct port, napi);
-+ struct net_device *dev = port->netdev;
-+ unsigned int rxq = queue_ids[port->id].rx;
-+ unsigned int rxfreeq = queue_ids[port->id].rxfree;
-+ struct net_device_stats *stats = hdlc_stats(dev);
-+ int received = 0;
-+
-+#if DEBUG_RX
-+ printk(KERN_DEBUG "%s: hss_hdlc_poll\n", dev->name);
-+#endif
-+
-+ while (received < budget) {
-+ struct sk_buff *skb;
-+ struct desc *desc;
-+ int n;
-+#ifdef __ARMEB__
-+ struct sk_buff *temp;
-+ u32 phys;
-+#endif
-+
-+ if ((n = queue_get_desc(rxq, port, 0)) < 0) {
-+ received = 0; /* No packet received */
-+#if DEBUG_RX
-+ printk(KERN_DEBUG "%s: hss_hdlc_poll"
-+ " netif_rx_complete\n", dev->name);
-+#endif
-+ netif_rx_complete(dev, napi);
-+ qmgr_enable_irq(rxq);
-+ if (!qmgr_stat_empty(rxq) &&
-+ netif_rx_reschedule(dev, napi)) {
-+#if DEBUG_RX
-+ printk(KERN_DEBUG "%s: hss_hdlc_poll"
-+ " netif_rx_reschedule succeeded\n",
-+ dev->name);
-+#endif
-+ qmgr_disable_irq(rxq);
-+ continue;
-+ }
-+#if DEBUG_RX
-+ printk(KERN_DEBUG "%s: hss_hdlc_poll all done\n",
-+ dev->name);
-+#endif
-+ return 0; /* all work done */
-+ }
-+
-+ desc = rx_desc_ptr(port, n);
-+#if 0 /* FIXME - error_count counts modulo 256, perhaps we should use it */
-+ if (desc->error_count)
-+ printk(KERN_DEBUG "%s: hss_hdlc_poll status 0x%02X"
-+ " errors %u\n", dev->name, desc->status,
-+ desc->error_count);
-+#endif
-+ skb = NULL;
-+ switch (desc->status) {
-+ case 0:
-+#ifdef __ARMEB__
-+ if ((skb = netdev_alloc_skb(dev, RX_SIZE)) != NULL) {
-+ phys = dma_map_single(&dev->dev, skb->data,
-+ RX_SIZE,
-+ DMA_FROM_DEVICE);
-+ if (dma_mapping_error(phys)) {
-+ dev_kfree_skb(skb);
-+ skb = NULL;
-+ }
-+ }
-+#else
-+ skb = netdev_alloc_skb(dev, desc->pkt_len);
-+#endif
-+ if (!skb)
-+ stats->rx_dropped++;
-+ break;
-+ case ERR_HDLC_ALIGN:
-+ case ERR_HDLC_ABORT:
-+ stats->rx_frame_errors++;
-+ stats->rx_errors++;
-+ break;
-+ case ERR_HDLC_FCS:
-+ stats->rx_crc_errors++;
-+ stats->rx_errors++;
-+ break;
-+ case ERR_HDLC_TOO_LONG:
-+ stats->rx_length_errors++;
-+ stats->rx_errors++;
-+ break;
-+ default: /* FIXME - remove printk */
-+ printk(KERN_ERR "%s: hss_hdlc_poll: status 0x%02X"
-+ " errors %u\n", dev->name, desc->status,
-+ desc->error_count);
-+ stats->rx_errors++;
-+ }
-+
-+ if (!skb) {
-+ /* put the desc back on RX-ready queue */
-+ desc->buf_len = RX_SIZE;
-+ desc->pkt_len = desc->status = 0;
-+ queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
-+ continue;
-+ }
-+
-+ /* process received frame */
-+#ifdef __ARMEB__
-+ temp = skb;
-+ skb = port->rx_buff_tab[n];
-+ dma_unmap_single(&dev->dev, desc->data,
-+ RX_SIZE, DMA_FROM_DEVICE);
-+#else
-+ dma_sync_single(&dev->dev, desc->data,
-+ RX_SIZE, DMA_FROM_DEVICE);
-+ memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
-+ ALIGN(desc->pkt_len, 4) / 4);
-+#endif
-+ skb_put(skb, desc->pkt_len);
-+
-+ debug_pkt(dev, "hss_hdlc_poll", skb->data, skb->len);
-+
-+ skb->protocol = hdlc_type_trans(skb, dev);
-+ dev->last_rx = jiffies;
-+ stats->rx_packets++;
-+ stats->rx_bytes += skb->len;
-+ netif_receive_skb(skb);
-+
-+ /* put the new buffer on RX-free queue */
-+#ifdef __ARMEB__
-+ port->rx_buff_tab[n] = temp;
-+ desc->data = phys;
-+#endif
-+ desc->buf_len = RX_SIZE;
-+ desc->pkt_len = 0;
-+ queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
-+ received++;
-+ }
-+#if DEBUG_RX
-+ printk(KERN_DEBUG "hss_hdlc_poll: end, not all work done\n");
-+#endif
-+ return received; /* not all work done */
-+}
-+
-+
-+static void hss_hdlc_txdone_irq(void *pdev)
-+{
-+ struct net_device *dev = pdev;
-+ struct port *port = dev_to_port(dev);
-+ struct net_device_stats *stats = hdlc_stats(dev);
-+ int n_desc;
-+
-+#if DEBUG_TX
-+ printk(KERN_DEBUG DRV_NAME ": hss_hdlc_txdone_irq\n");
-+#endif
-+ while ((n_desc = queue_get_desc(queue_ids[port->id].txdone,
-+ port, 1)) >= 0) {
-+ struct desc *desc;
-+ int start;
-+
-+ desc = tx_desc_ptr(port, n_desc);
-+
-+ stats->tx_packets++;
-+ stats->tx_bytes += desc->pkt_len;
-+
-+ dma_unmap_tx(port, desc);
-+#if DEBUG_TX
-+ printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq free %p\n",
-+ dev->name, port->tx_buff_tab[n_desc]);
-+#endif
-+ free_buffer_irq(port->tx_buff_tab[n_desc]);
-+ port->tx_buff_tab[n_desc] = NULL;
-+
-+ start = qmgr_stat_empty(port->plat->txreadyq);
-+ queue_put_desc(port->plat->txreadyq,
-+ tx_desc_phys(port, n_desc), desc);
-+ if (start) {
-+#if DEBUG_TX
-+ printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq xmit"
-+ " ready\n", dev->name);
-+#endif
-+ netif_wake_queue(dev);
-+ }
-+ }
-+}
-+
-+static int hss_hdlc_xmit(struct sk_buff *skb, struct net_device *dev)
-+{
-+ struct port *port = dev_to_port(dev);
-+ struct net_device_stats *stats = hdlc_stats(dev);
-+ unsigned int txreadyq = port->plat->txreadyq;
-+ int len, offset, bytes, n;
-+ void *mem;
-+ u32 phys;
-+ struct desc *desc;
-+
-+#if DEBUG_TX
-+ printk(KERN_DEBUG "%s: hss_hdlc_xmit\n", dev->name);
-+#endif
-+
-+ if (unlikely(skb->len > HDLC_MAX_MRU)) {
-+ dev_kfree_skb(skb);
-+ stats->tx_errors++;
-+ return NETDEV_TX_OK;
-+ }
-+
-+ debug_pkt(dev, "hss_hdlc_xmit", skb->data, skb->len);
-+
-+ len = skb->len;
-+#ifdef __ARMEB__
-+ offset = 0; /* no need to keep alignment */
-+ bytes = len;
-+ mem = skb->data;
-+#else
-+ offset = (int)skb->data & 3; /* keep 32-bit alignment */
-+ bytes = ALIGN(offset + len, 4);
-+ if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
-+ dev_kfree_skb(skb);
-+ stats->tx_dropped++;
-+ return NETDEV_TX_OK;
-+ }
-+ memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
-+ dev_kfree_skb(skb);
-+#endif
-+
-+ phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
-+ if (dma_mapping_error(phys)) {
-+#ifdef __ARMEB__
-+ dev_kfree_skb(skb);
-+#else
-+ kfree(mem);
-+#endif
-+ stats->tx_dropped++;
-+ return NETDEV_TX_OK;
-+ }
-+
-+ n = queue_get_desc(txreadyq, port, 1);
-+ BUG_ON(n < 0);
-+ desc = tx_desc_ptr(port, n);
-+
-+#ifdef __ARMEB__
-+ port->tx_buff_tab[n] = skb;
-+#else
-+ port->tx_buff_tab[n] = mem;
-+#endif
-+ desc->data = phys + offset;
-+ desc->buf_len = desc->pkt_len = len;
-+
-+ wmb();
-+ queue_put_desc(queue_ids[port->id].tx, tx_desc_phys(port, n), desc);
-+ dev->trans_start = jiffies;
-+
-+ if (qmgr_stat_empty(txreadyq)) {
-+#if DEBUG_TX
-+ printk(KERN_DEBUG "%s: hss_hdlc_xmit queue full\n", dev->name);
-+#endif
-+ netif_stop_queue(dev);
-+ /* we could miss TX ready interrupt */
-+ if (!qmgr_stat_empty(txreadyq)) {
-+#if DEBUG_TX
-+ printk(KERN_DEBUG "%s: hss_hdlc_xmit ready again\n",
-+ dev->name);
-+#endif
-+ netif_wake_queue(dev);
-+ }
-+ }
-+
-+#if DEBUG_TX
-+ printk(KERN_DEBUG "%s: hss_hdlc_xmit end\n", dev->name);
-+#endif
-+ return NETDEV_TX_OK;
-+}
-+
-+
-+static int request_hdlc_queues(struct port *port)
-+{
-+ int err;
-+
-+ err = qmgr_request_queue(queue_ids[port->id].rxfree, RX_DESCS, 0, 0);
-+ if (err)
-+ return err;
-+
-+ err = qmgr_request_queue(queue_ids[port->id].rx, RX_DESCS, 0, 0);
-+ if (err)
-+ goto rel_rxfree;
-+
-+ err = qmgr_request_queue(queue_ids[port->id].tx, TX_DESCS, 0, 0);
-+ if (err)
-+ goto rel_rx;
-+
-+ err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0);
-+ if (err)
-+ goto rel_tx;
-+
-+ err = qmgr_request_queue(queue_ids[port->id].txdone, TX_DESCS, 0, 0);
-+ if (err)
-+ goto rel_txready;
-+ return 0;
-+
-+rel_txready:
-+ qmgr_release_queue(port->plat->txreadyq);
-+rel_tx:
-+ qmgr_release_queue(queue_ids[port->id].tx);
-+rel_rx:
-+ qmgr_release_queue(queue_ids[port->id].rx);
-+rel_rxfree:
-+ qmgr_release_queue(queue_ids[port->id].rxfree);
-+ printk(KERN_DEBUG "%s: unable to request hardware queues\n",
-+ port->netdev->name);
-+ return err;
-+}
-+
-+static void release_hdlc_queues(struct port *port)
-+{
-+ qmgr_release_queue(queue_ids[port->id].rxfree);
-+ qmgr_release_queue(queue_ids[port->id].rx);
-+ qmgr_release_queue(queue_ids[port->id].txdone);
-+ qmgr_release_queue(queue_ids[port->id].tx);
-+ qmgr_release_queue(port->plat->txreadyq);
-+}
-+
-+static int init_hdlc_queues(struct port *port)
-+{
-+ int i;
-+
-+ if (!ports_open)
-+ if (!(dma_pool = dma_pool_create(DRV_NAME, NULL,
-+ POOL_ALLOC_SIZE, 32, 0)))
-+ return -ENOMEM;
-+
-+ if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
-+ &port->desc_tab_phys)))
-+ return -ENOMEM;
-+ memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
-+ memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
-+ memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
-+
-+ /* Setup RX buffers */
-+ for (i = 0; i < RX_DESCS; i++) {
-+ struct desc *desc = rx_desc_ptr(port, i);
-+ buffer_t *buff;
-+ void *data;
-+#ifdef __ARMEB__
-+ if (!(buff = netdev_alloc_skb(port->netdev, RX_SIZE)))
-+ return -ENOMEM;
-+ data = buff->data;
-+#else
-+ if (!(buff = kmalloc(RX_SIZE, GFP_KERNEL)))
-+ return -ENOMEM;
-+ data = buff;
-+#endif
-+ desc->buf_len = RX_SIZE;
-+ desc->data = dma_map_single(&port->netdev->dev, data,
-+ RX_SIZE, DMA_FROM_DEVICE);
-+ if (dma_mapping_error(desc->data)) {
-+ free_buffer(buff);
-+ return -EIO;
-+ }
-+ port->rx_buff_tab[i] = buff;
-+ }
-+
-+ return 0;
-+}
-+
-+static void destroy_hdlc_queues(struct port *port)
-+{
-+ int i;
-+
-+ if (port->desc_tab) {
-+ for (i = 0; i < RX_DESCS; i++) {
-+ struct desc *desc = rx_desc_ptr(port, i);
-+ buffer_t *buff = port->rx_buff_tab[i];
-+ if (buff) {
-+ dma_unmap_single(&port->netdev->dev,
-+ desc->data, RX_SIZE,
-+ DMA_FROM_DEVICE);
-+ free_buffer(buff);
-+ }
-+ }
-+ for (i = 0; i < TX_DESCS; i++) {
-+ struct desc *desc = tx_desc_ptr(port, i);
-+ buffer_t *buff = port->tx_buff_tab[i];
-+ if (buff) {
-+ dma_unmap_tx(port, desc);
-+ free_buffer(buff);
-+ }
-+ }
-+ dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
-+ port->desc_tab = NULL;
-+ }
-+
-+ if (!ports_open && dma_pool) {
-+ dma_pool_destroy(dma_pool);
-+ dma_pool = NULL;
-+ }
-+}
-+
-+static int hss_hdlc_open(struct net_device *dev)
-+{
-+ struct port *port = dev_to_port(dev);
-+ unsigned long flags;
-+ int i, err = 0;
-+
-+ if ((err = hdlc_open(dev)))
-+ return err;
-+
-+ if ((err = request_hdlc_queues(port)))
-+ goto err_hdlc_close;
-+
-+ if ((err = init_hdlc_queues(port)))
-+ goto err_destroy_queues;
-+
-+ spin_lock_irqsave(&npe_lock, flags);
-+
-+ if (port->mode == MODE_G704 && port->channels[0] == CHANNEL_HDLC) {
-+ err = -EBUSY; /* channel #0 is used for G.704 framing */
-+ goto err_unlock;
-+ }
-+ if (port->mode != MODE_HDLC)
-+ for (i = port->frame_size / 8; i < MAX_CHANNELS; i++)
-+ if (port->channels[i] == CHANNEL_HDLC) {
-+ err = -ECHRNG; /* frame too short */
-+ goto err_unlock;
-+ }
-+
-+ if ((err = hss_config_load_firmware(port)))
-+ goto err_unlock;
-+
-+ if (!port->chan_open_count && port->plat->open)
-+ if ((err = port->plat->open(port->id, dev,
-+ hss_hdlc_set_carrier)))
-+ goto err_unlock;
-+
-+ if (port->mode == MODE_G704 && !port->chan_open_count)
-+ if ((err = hss_prepare_chan(port)))
-+ goto err_plat_close;
-+
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+
-+ /* Populate queues with buffers, no failure after this point */
-+ for (i = 0; i < TX_DESCS; i++)
-+ queue_put_desc(port->plat->txreadyq,
-+ tx_desc_phys(port, i), tx_desc_ptr(port, i));
-+
-+ for (i = 0; i < RX_DESCS; i++)
-+ queue_put_desc(queue_ids[port->id].rxfree,
-+ rx_desc_phys(port, i), rx_desc_ptr(port, i));
-+
-+ napi_enable(&port->napi);
-+ netif_start_queue(dev);
-+
-+ qmgr_set_irq(queue_ids[port->id].rx, QUEUE_IRQ_SRC_NOT_EMPTY,
-+ hss_hdlc_rx_irq, dev);
-+
-+ qmgr_set_irq(queue_ids[port->id].txdone, QUEUE_IRQ_SRC_NOT_EMPTY,
-+ hss_hdlc_txdone_irq, dev);
-+ qmgr_enable_irq(queue_ids[port->id].txdone);
-+
-+ ports_open++;
-+ port->hdlc_open = 1;
-+
-+ hss_config_set_hdlc_cfg(port);
-+ hss_config_set_lut(port);
-+ hss_config_load(port);
-+
-+ if (port->mode == MODE_G704 && !port->chan_open_count)
-+ hss_config_start_chan(port);
-+
-+ hss_config_start_hdlc(port);
-+
-+ /* we may already have RX data, enables IRQ */
-+ netif_rx_schedule(dev, &port->napi);
-+ return 0;
-+
-+err_plat_close:
-+ if (!port->chan_open_count && port->plat->close)
-+ port->plat->close(port->id, dev);
-+err_unlock:
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+err_destroy_queues:
-+ destroy_hdlc_queues(port);
-+ release_hdlc_queues(port);
-+err_hdlc_close:
-+ hdlc_close(dev);
-+ return err;
-+}
-+
-+static int hss_hdlc_close(struct net_device *dev)
-+{
-+ struct port *port = dev_to_port(dev);
-+ unsigned long flags;
-+ int i, buffs = RX_DESCS; /* allocated RX buffers */
-+
-+ spin_lock_irqsave(&npe_lock, flags);
-+ ports_open--;
-+ port->hdlc_open = 0;
-+ qmgr_disable_irq(queue_ids[port->id].rx);
-+ netif_stop_queue(dev);
-+ napi_disable(&port->napi);
-+
-+ hss_config_stop_hdlc(port);
-+
-+ if (port->mode == MODE_G704 && !port->chan_open_count)
-+ hss_chan_stop(port);
-+
-+ while (queue_get_desc(queue_ids[port->id].rxfree, port, 0) >= 0)
-+ buffs--;
-+ while (queue_get_desc(queue_ids[port->id].rx, port, 0) >= 0)
-+ buffs--;
-+
-+ if (buffs)
-+ printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)"
-+ " left in NPE\n", dev->name, buffs);
-+
-+ buffs = TX_DESCS;
-+ while (queue_get_desc(queue_ids[port->id].tx, port, 1) >= 0)
-+ buffs--; /* cancel TX */
-+
-+ i = 0;
-+ do {
-+ while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
-+ buffs--;
-+ if (!buffs)
-+ break;
-+ } while (++i < MAX_CLOSE_WAIT);
-+
-+ if (buffs)
-+ printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) "
-+ "left in NPE\n", dev->name, buffs);
-+#if DEBUG_CLOSE
-+ if (!buffs)
-+ printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
-+#endif
-+ qmgr_disable_irq(queue_ids[port->id].txdone);
-+
-+ if (!port->chan_open_count && port->plat->close)
-+ port->plat->close(port->id, dev);
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+
-+ destroy_hdlc_queues(port);
-+ release_hdlc_queues(port);
-+ hdlc_close(dev);
-+ return 0;
-+}
-+
-+
-+static int hss_hdlc_attach(struct net_device *dev, unsigned short encoding,
-+ unsigned short parity)
-+{
-+ struct port *port = dev_to_port(dev);
-+
-+ if (encoding != ENCODING_NRZ)
-+ return -EINVAL;
-+
-+ switch(parity) {
-+ case PARITY_CRC16_PR1_CCITT:
-+ port->hdlc_cfg = 0;
-+ return 0;
-+
-+ case PARITY_CRC32_PR1_CCITT:
-+ port->hdlc_cfg = PKT_HDLC_CRC_32;
-+ return 0;
-+
-+ default:
-+ return -EINVAL;
-+ }
-+}
-+
-+
-+static int hss_hdlc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
-+{
-+ const size_t size = sizeof(sync_serial_settings);
-+ sync_serial_settings new_line;
-+ sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
-+ struct port *port = dev_to_port(dev);
-+ unsigned long flags;
-+ int i, clk;
-+
-+ if (cmd != SIOCWANDEV)
-+ return hdlc_ioctl(dev, ifr, cmd);
-+
-+ switch(ifr->ifr_settings.type) {
-+ case IF_GET_IFACE:
-+ ifr->ifr_settings.type = IF_IFACE_V35;
-+ if (ifr->ifr_settings.size < size) {
-+ ifr->ifr_settings.size = size; /* data size wanted */
-+ return -ENOBUFS;
-+ }
-+ memset(&new_line, 0, sizeof(new_line));
-+ new_line.clock_type = port->clock_type;
-+ new_line.clock_rate = port->clock_rate;
-+ new_line.loopback = port->loopback;
-+ if (copy_to_user(line, &new_line, size))
-+ return -EFAULT;
-+
-+ if (!port->chan_buf)
-+ return 0;
-+
-+ dma_sync_single(&dev->dev, port->chan_rx_buf_phys,
-+ chan_rx_buf_len(port), DMA_FROM_DEVICE);
-+ printk(KERN_DEBUG "RX:\n");
-+ for (i = 0; i < chan_rx_buf_len(port); i++) {
-+ if (i % 32 == 0)
-+ printk(KERN_DEBUG "%03X ", i);
-+ printk("%02X%c", chan_rx_buf(port)[i],
-+ (i + 1) % 32 ? ' ' : '\n');
-+ }
-+
-+#if 0
-+ printk(KERN_DEBUG "TX:\n");
-+ for (i = 0; i < /*CHAN_TX_FRAMES * 2*/ chan_tx_buf_len(port)
-+ + chan_tx_lists_len(port); i++) {
-+ if (i % 32 == 0)
-+ printk(KERN_DEBUG "%03X ", i);
-+ printk("%02X%c", chan_tx_buf(port)[i],
-+ (i + 1) % 32 ? ' ' : '\n');
-+ }
-+#endif
-+ port->msg_count = 10;
-+ return 0;
-+
-+ case IF_IFACE_SYNC_SERIAL:
-+ case IF_IFACE_V35:
-+ if(!capable(CAP_NET_ADMIN))
-+ return -EPERM;
-+ if (copy_from_user(&new_line, line, size))
-+ return -EFAULT;
-+
-+ clk = new_line.clock_type;
-+ if (port->plat->set_clock)
-+ clk = port->plat->set_clock(port->id, clk);
-+
-+ if (clk != CLOCK_EXT && clk != CLOCK_INT)
-+ return -EINVAL; /* No such clock setting */
-+
-+ if (new_line.loopback != 0 && new_line.loopback != 1)
-+ return -EINVAL;
-+
-+ port->clock_type = clk; /* Update settings */
-+ /* FIXME port->clock_rate = new_line.clock_rate */;
-+ port->loopback = new_line.loopback;
-+
-+ spin_lock_irqsave(&npe_lock, flags);
-+
-+ if (port->chan_open_count || port->hdlc_open) {
-+ hss_config_set_line(port);
-+ hss_config_load(port);
-+ }
-+ if (port->loopback || port->carrier)
-+ netif_carrier_on(port->netdev);
-+ else
-+ netif_carrier_off(port->netdev);
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+
-+ return 0;
-+
-+ default:
-+ return hdlc_ioctl(dev, ifr, cmd);
-+ }
-+}
-+
-+/*****************************************************************************
-+ * channelized (G.704) operation
-+ ****************************************************************************/
-+
-+static void g704_rx_framer(struct port *port, unsigned int offset)
-+{
-+ u8 *data = chan_rx_buf(port) + sub_offset(offset, CHAN_RX_TRIGGER,
-+ CHAN_RX_FRAMES);
-+ unsigned int bit, frame, bad_even = 0, bad_odd = 0, cnt;
-+ unsigned int is_first = port->just_set_offset;
-+ u8 zeros_even, zeros_odd, ones_even, ones_odd;
-+ enum alignment aligned;
-+
-+ port->just_set_offset = 0;
-+ dma_sync_single(port->dev, port->chan_rx_buf_phys, CHAN_RX_FRAMES,
-+ DMA_FROM_DEVICE);
-+
-+ /* check if aligned first */
-+ for (frame = 0; frame < CHAN_RX_TRIGGER &&
-+ (bad_even <= MAX_CHAN_RX_BAD_SYNC ||
-+ bad_odd <= MAX_CHAN_RX_BAD_SYNC); frame += 2) {
-+ u8 ve = data[frame];
-+ u8 vo = data[frame + 1];
-+
-+ if ((ve & 0x7F) != 0x1B || !(vo & 0x40))
-+ bad_even++;
-+
-+ if ((vo & 0x7F) != 0x1B || !(ve & 0x40))
-+ bad_odd++;
-+ }
-+
-+ if (bad_even <= MAX_CHAN_RX_BAD_SYNC)
-+ aligned = EVEN_FIRST;
-+ else if (bad_odd <= MAX_CHAN_RX_BAD_SYNC)
-+ aligned = ODD_FIRST;
-+ else
-+ aligned = NOT_ALIGNED;
-+
-+ if (aligned != NOT_ALIGNED) {
-+ if (aligned == port->aligned)
-+ return; /* no change */
-+ if (printk_ratelimit())
-+ printk(KERN_INFO "HSS-%i: synchronized at %u (%s frame"
-+ " first)\n", port->id, port->frame_sync_offset,
-+ aligned == EVEN_FIRST ? "even" : "odd");
-+ port->aligned = aligned;
-+
-+ atomic_inc(&port->chan_tx_irq_number);
-+ wake_up_interruptible(&port->chan_tx_waitq);
-+ atomic_inc(&port->chan_rx_irq_number);
-+ wake_up_interruptible(&port->chan_rx_waitq);
-+ return;
-+ }
-+
-+ /* not aligned */
-+ if (port->aligned != NOT_ALIGNED && printk_ratelimit()) {
-+ printk(KERN_INFO "HSS-%i: lost alignment\n", port->id);
-+ port->aligned = NOT_ALIGNED;
-+#if DEBUG_FRAMER
-+ for (cnt = 0; cnt < CHAN_RX_FRAMES; cnt++)
-+ printk("%c%02X%s", cnt == offset ? '>' : ' ',
-+ chan_rx_buf(port)[cnt],
-+ (cnt + 1) % 32 ? "" : "\n");
-+#endif
-+
-+ for (cnt = 0; cnt < MAX_CHAN_DEVICES; cnt++)
-+ if (port->chan_devices[cnt]) {
-+ set_bit(TX_ERROR_BIT, &port->chan_devices[cnt]
-+ ->errors_bitmap);
-+ set_bit(RX_ERROR_BIT, &port->chan_devices[cnt]
-+ ->errors_bitmap);
-+ }
-+ atomic_inc(&port->chan_tx_irq_number);
-+ wake_up_interruptible(&port->chan_tx_waitq);
-+ atomic_inc(&port->chan_rx_irq_number);
-+ wake_up_interruptible(&port->chan_rx_waitq);
-+ }
-+
-+ if (is_first)
-+ return;
-+
-+ zeros_even = zeros_odd = 0;
-+ ones_even = ones_odd = 0xFF;
-+ for (frame = 0; frame < CHAN_RX_TRIGGER; frame += 2) {
-+ zeros_even |= data[frame];
-+ zeros_odd |= data[frame + 1];
-+ ones_even &= data[frame];
-+ ones_odd &= data[frame + 1];
-+ }
-+
-+ for (bit = 0; bit < 7; bit++) {
-+ if ((zeros_even & ~0x9B) == 0 && (ones_even & 0x1B) == 0x1B &&
-+ (ones_odd & 0x40) == 0x40) {
-+ aligned = EVEN_FIRST; /* maybe */
-+ break;
-+ }
-+ if ((zeros_odd & ~0x9B) == 0 && (ones_odd & 0x1B) == 0x1B &&
-+ (ones_even & 0x40) == 0x40) {
-+ aligned = ODD_FIRST; /* maybe */
-+ break;
-+ }
-+ zeros_even <<= 1;
-+ ones_even = ones_even << 1 | 1;
-+ zeros_odd <<= 1;
-+ ones_odd = ones_odd << 1 | 1;
-+ }
-+
-+ port->frame_sync_offset += port->frame_size - bit;
-+ port->frame_sync_offset %= port->frame_size;
-+ port->just_set_offset = 1;
-+
-+#if DEBUG_FRAMER
-+ if (bit == 7)
-+ printk(KERN_DEBUG "HSS-%i: trying frame sync at %u\n",
-+ port->id, port->frame_sync_offset);
-+ else
-+ printk(KERN_DEBUG "HSS-%i: found possible frame sync pattern at"
-+ " %u (%s frame first)\n", port->id,
-+ port->frame_sync_offset,
-+ aligned == EVEN_FIRST ? "even" : "odd");
-+#endif
-+
-+ hss_config_set_rx_frame(port);
-+ hss_config_load(port);
-+}
-+
-+static void chan_process_tx_irq(struct chan_device *chan_dev, int offset)
-+{
-+ /* in bytes */
-+ unsigned int buff_len = CHAN_TX_FRAMES * chan_dev->chan_count;
-+ unsigned int list_len = CHAN_TX_LIST_FRAMES * chan_dev->chan_count;
-+ int eaten, last_offset = chan_dev->port->chan_last_tx * list_len;
-+
-+ offset *= list_len;
-+ eaten = sub_offset(offset, last_offset, buff_len);
-+
-+ if (chan_dev->tx_count > eaten + 2 * list_len) {
-+ /* two pages must be reserved for the transmitter */
-+ chan_dev->tx_first += eaten;
-+ chan_dev->tx_first %= buff_len;
-+ chan_dev->tx_count -= eaten;
-+ } else {
-+ /* FIXME check
-+ 0
-+ 1 tx_first (may still be transmited)
-+ 2 tx_offset (currently reported by the NPE)
-+ 3 tx_first + 2 * list_len (free to write here)
-+ 4
-+ 5
-+ */
-+
-+ /* printk(KERN_DEBUG "TX buffer underflow\n"); */
-+ chan_dev->tx_first = sub_offset(offset, list_len, buff_len);
-+ chan_dev->tx_count = 2 * list_len; /* reserve */
-+ set_bit(TX_ERROR_BIT, &chan_dev->errors_bitmap);
-+ }
-+}
-+
-+static void chan_process_rx_irq(struct chan_device *chan_dev, int offset)
-+{
-+ /* in bytes */
-+ unsigned int buff_len = CHAN_RX_FRAMES * chan_dev->chan_count;
-+ unsigned int trig_len = CHAN_RX_TRIGGER * chan_dev->chan_count;
-+ int last_offset = chan_dev->port->chan_last_rx * chan_dev->chan_count;
-+
-+ offset *= chan_dev->chan_count;
-+ chan_dev->rx_count += sub_offset(offset, last_offset + trig_len,
-+ buff_len) + trig_len;
-+ if (chan_dev->rx_count > buff_len - 2 * trig_len) {
-+ /* two pages - offset[0] and offset[1] are lost - FIXME check */
-+ /* printk(KERN_DEBUG "RX buffer overflow\n"); */
-+ chan_dev->rx_first = (offset + 2 * trig_len) % buff_len;
-+ chan_dev->rx_count = buff_len - 2 * trig_len;
-+ set_bit(RX_ERROR_BIT, &chan_dev->errors_bitmap);
-+ }
-+}
-+
-+static void hss_chan_irq(void *pdev)
-+{
-+ struct port *port = pdev;
-+ u32 v;
-+
-+#if DEBUG_RX
-+ printk(KERN_DEBUG DRV_NAME ": hss_chan_irq\n");
-+#endif
-+ spin_lock(&npe_lock);
-+ while ((v = qmgr_get_entry(queue_ids[port->id].chan))) {
-+ unsigned int first, errors, tx_list, rx_frame;
-+ int i, bad;
-+
-+ first = v >> 24;
-+ errors = (v >> 16) & 0xFF;
-+ tx_list = (v >> 8) & 0xFF;
-+ rx_frame = v & 0xFF;
-+
-+ if (port->msg_count) {
-+ printk(KERN_DEBUG "chan_irq hss %i jiffies %lu first"
-+ " 0x%02X errors 0x%02X tx_list 0x%02X rx_frame"
-+ " 0x%02X\n", port->id, jiffies, first, errors,
-+ tx_list, rx_frame);
-+ port->msg_count--;
-+ }
-+
-+ BUG_ON(rx_frame % CHAN_RX_TRIGGER);
-+ BUG_ON(rx_frame >= CHAN_RX_FRAMES);
-+ BUG_ON(tx_list >= CHAN_TX_LISTS);
-+
-+ bad = port->mode == MODE_G704 && port->aligned == NOT_ALIGNED;
-+ if (!bad && tx_list != port->chan_last_tx) {
-+ if (tx_list != (port->chan_last_tx + 1) % CHAN_TX_LISTS)
-+ printk(KERN_DEBUG "Skipped an IRQ? Tx last %i"
-+ " current %i\n", port->chan_last_tx,
-+ tx_list);
-+ for (i = 0; i < MAX_CHAN_DEVICES; i++) {
-+ if (!port->chan_devices[i] ||
-+ !port->chan_devices[i]->open_count)
-+ continue;
-+ chan_process_tx_irq(port->chan_devices[i],
-+ tx_list);
-+ }
-+ atomic_inc(&port->chan_tx_irq_number);
-+#if 0
-+ printk(KERN_DEBUG "wakeing up TX jiff %lu\n",
-+ jiffies, errors);
-+#endif
-+ wake_up_interruptible(&port->chan_tx_waitq);
-+ }
-+
-+ if (rx_frame != (port->chan_last_rx + CHAN_RX_TRIGGER) %
-+ CHAN_RX_FRAMES)
-+ printk(KERN_DEBUG "Skipped an IRQ? Rx last %i"
-+ " current %i\n", port->chan_last_rx, rx_frame);
-+
-+ if (port->mode == MODE_G704)
-+ g704_rx_framer(port, rx_frame);
-+
-+ if (!bad &&
-+ (port->mode != MODE_G704 || port->aligned != NOT_ALIGNED)) {
-+ for (i = 0; i < MAX_CHAN_DEVICES; i++) {
-+ if (!port->chan_devices[i] ||
-+ !port->chan_devices[i]->open_count)
-+ continue;
-+ chan_process_rx_irq(port->chan_devices[i],
-+ rx_frame);
-+ }
-+ atomic_inc(&port->chan_rx_irq_number);
-+ wake_up_interruptible(&port->chan_rx_waitq);
-+ }
-+ port->chan_last_tx = tx_list;
-+ port->chan_last_rx = rx_frame;
-+ }
-+ spin_unlock(&npe_lock);
-+}
-+
-+
-+static int hss_prepare_chan(struct port *port)
-+{
-+ int err;
-+
-+ if ((err = hss_config_load_firmware(port)))
-+ return err;
-+
-+ if ((err = qmgr_request_queue(queue_ids[port->id].chan,
-+ CHAN_QUEUE_LEN, 0, 0)))
-+ return err;
-+
-+ if (!(port->chan_buf = kmalloc(chan_tx_buf_len(port) +
-+ chan_tx_lists_len(port) +
-+ chan_rx_buf_len(port), GFP_KERNEL))) {
-+ goto release_queue;
-+ err = -ENOBUFS;
-+ }
-+
-+ port->chan_tx_buf_phys = dma_map_single(port->dev, chan_tx_buf(port),
-+ chan_tx_buf_len(port) +
-+ chan_tx_lists_len(port),
-+ DMA_TO_DEVICE);
-+ if (dma_mapping_error(port->chan_tx_buf_phys)) {
-+ err = -EIO;
-+ goto free;
-+ }
-+
-+ port->chan_rx_buf_phys = dma_map_single(port->dev, chan_rx_buf(port),
-+ chan_rx_buf_len(port),
-+ DMA_FROM_DEVICE);
-+ if (dma_mapping_error(port->chan_rx_buf_phys)) {
-+ err = -EIO;
-+ goto unmap_tx;
-+ }
-+
-+ qmgr_set_irq(queue_ids[port->id].chan, QUEUE_IRQ_SRC_NOT_EMPTY,
-+ hss_chan_irq, port);
-+ qmgr_enable_irq(queue_ids[port->id].chan);
-+ hss_chan_irq(port);
-+ return 0;
-+
-+unmap_tx:
-+ dma_unmap_single(port->dev, port->chan_tx_buf_phys,
-+ chan_tx_buf_len(port) + chan_tx_lists_len(port),
-+ DMA_TO_DEVICE);
-+free:
-+ kfree(port->chan_buf);
-+ port->chan_buf = NULL;
-+release_queue:
-+ qmgr_release_queue(queue_ids[port->id].chan);
-+ return err;
-+}
-+
-+void hss_chan_stop(struct port *port)
-+{
-+ if (!port->chan_open_count && !port->hdlc_open)
-+ qmgr_disable_irq(queue_ids[port->id].chan);
-+
-+ hss_config_stop_chan(port);
-+ hss_config_set_lut(port);
-+ hss_config_load(port);
-+
-+ if (!port->chan_open_count && !port->hdlc_open) {
-+ dma_unmap_single(port->dev, port->chan_tx_buf_phys,
-+ chan_tx_buf_len(port) +
-+ chan_tx_lists_len(port), DMA_TO_DEVICE);
-+ dma_unmap_single(port->dev, port->chan_rx_buf_phys,
-+ chan_rx_buf_len(port), DMA_FROM_DEVICE);
-+ kfree(port->chan_buf);
-+ port->chan_buf = NULL;
-+ qmgr_release_queue(queue_ids[port->id].chan);
-+ }
-+}
-+
-+static int hss_chan_open(struct inode *inode, struct file *file)
-+{
-+ struct chan_device *chan_dev = inode_to_chan_dev(inode);
-+ struct port *port = chan_dev->port;
-+ unsigned long flags;
-+ int i, err = 0;
-+
-+ spin_lock_irqsave(&npe_lock, flags);
-+
-+ if (chan_dev->open_count) {
-+ if (chan_dev->excl_open || (file->f_flags & O_EXCL))
-+ err = -EBUSY;
-+ else
-+ chan_dev->open_count++;
-+ goto out;
-+ }
-+
-+ if (port->mode == MODE_HDLC) {
-+ err = -ENOSYS;
-+ goto out;
-+ }
-+
-+ if (port->mode == MODE_G704 && port->channels[0] == chan_dev->id) {
-+ err = -EBUSY; /* channel #0 is used for G.704 signaling */
-+ goto out;
-+ }
-+ for (i = MAX_CHANNELS; i > port->frame_size / 8; i--)
-+ if (port->channels[i - 1] == chan_dev->id) {
-+ err = -ECHRNG; /* frame too short */
-+ goto out;
-+ }
-+
-+ chan_dev->rx_first = chan_dev->tx_first = 0;
-+ chan_dev->rx_count = chan_dev->tx_count = 0;
-+ clear_bit(TX_ERROR_BIT, &chan_dev->errors_bitmap);
-+ clear_bit(RX_ERROR_BIT, &chan_dev->errors_bitmap);
-+
-+ if (!port->chan_open_count && !port->hdlc_open) {
-+ if (port->plat->open)
-+ if ((err = port->plat->open(port->id, port->netdev,
-+ hss_hdlc_set_carrier)))
-+ goto out;
-+ if ((err = hss_prepare_chan(port))) {
-+ if (port->plat->close)
-+ port->plat->close(port->id, port->netdev);
-+ goto out;
-+ }
-+ }
-+
-+ hss_config_stop_chan(port);
-+ chan_dev->open_count++;
-+ port->chan_open_count++;
-+ chan_dev->excl_open = !!file->f_flags & O_EXCL;
-+
-+ hss_config_set_lut(port);
-+ hss_config_load(port);
-+ hss_config_start_chan(port);
-+out:
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+ return err;
-+}
-+
-+static int hss_chan_release(struct inode *inode, struct file *file)
-+{
-+ struct chan_device *chan_dev = inode_to_chan_dev(inode);
-+ struct port *port = chan_dev->port;
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&npe_lock, flags);
-+
-+ if (!--chan_dev->open_count) {
-+ if (!--port->chan_open_count && !port->hdlc_open) {
-+ hss_chan_stop(port);
-+ if (port->plat->close)
-+ port->plat->close(port->id, port->netdev);
-+ } else {
-+ hss_config_stop_chan(port);
-+ hss_config_set_lut(port);
-+ hss_config_set_line(port); //
-+ hss_config_start_chan(port);
-+ }
-+ }
-+
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+ return 0;
-+}
-+
-+static ssize_t hss_chan_read(struct file *file, char __user *buf, size_t count,
-+ loff_t *f_pos)
-+{
-+ struct chan_device *chan_dev = inode_to_chan_dev
-+ (file->f_path.dentry->d_inode);
-+ struct port *port = chan_dev->port;
-+ unsigned long flags;
-+ u8 *rx_buf;
-+ int res = 0, loops = 0;
-+
-+ spin_lock_irqsave(&npe_lock, flags);
-+
-+ while (1) {
-+ int prev_irq = atomic_read(&port->chan_rx_irq_number);
-+#if 0
-+ if (test_and_clear_bit(RX_ERROR_BIT, &chan_dev->errors_bitmap)
-+ || (port->mode == G704 && port->aligned == NOT_ALIGNED)) {
-+ res = -EIO;
-+ goto out;
-+ }
-+#endif
-+ if (count == 0)
-+ goto out; /* no need to wait */
-+
-+ if (chan_dev->rx_count)
-+ break;
-+
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+ loops++;
-+ if ((res = wait_event_interruptible
-+ (port->chan_rx_waitq,
-+ atomic_read(&port->chan_rx_irq_number) != prev_irq)))
-+ goto out;
-+ spin_lock_irqsave(&npe_lock, flags);
-+ continue;
-+ }
-+
-+ dma_sync_single(port->dev, port->chan_rx_buf_phys,
-+ chan_rx_buf_len(port), DMA_FROM_DEVICE);
-+
-+#if 0
-+ if (loops > 1)
-+ printk(KERN_DEBUG "ENTRY rx_first %u rx_count %u count %i"
-+ " last_rx %u loops %i\n", chan_dev->rx_first,
-+ chan_dev->rx_count, count, port->chan_last_rx, loops);
-+#endif
-+ rx_buf = chan_rx_buf(port);
-+ while (chan_dev->rx_count > 0 && res < count) {
-+ unsigned int chan = chan_dev->rx_first % chan_dev->chan_count;
-+ unsigned int frame = chan_dev->rx_first / chan_dev->chan_count;
-+
-+ chan = chan_dev->log_channels[chan];
-+ if (put_user(rx_buf[chan * CHAN_RX_FRAMES + frame], buf++)) {
-+ res = -EFAULT;
-+ goto out;
-+ }
-+ chan_dev->rx_first++;
-+ chan_dev->rx_first %= CHAN_RX_FRAMES * chan_dev->chan_count;
-+ chan_dev->rx_count--;
-+ res++;
-+ }
-+out:
-+#if 0
-+ printk(KERN_DEBUG "EXIT rx_first %u rx_count %u res %i\n",
-+ chan_dev->rx_first, chan_dev->rx_count, res);
-+#endif
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+ return res;
-+}
-+
-+static ssize_t hss_chan_write(struct file *file, const char __user *buf,
-+ size_t count, loff_t *f_pos)
-+{
-+ struct chan_device *chan_dev = inode_to_chan_dev
-+ (file->f_path.dentry->d_inode);
-+ struct port *port = chan_dev->port;
-+ unsigned long flags;
-+ u8 *tx_buf;
-+ int res = 0, loops = 0;
-+
-+ spin_lock_irqsave(&npe_lock, flags);
-+ while (1) {
-+ int prev_irq = atomic_read(&port->chan_tx_irq_number);
-+#if 0
-+ if (test_and_clear_bit(TX_ERROR_BIT, &chan_dev->errors_bitmap)
-+ || (port->mode == G704 && port->aligned == NOT_ALIGNED)) {
-+ res = -EIO;
-+ goto out;
-+ }
-+#endif
-+ if (count == 0)
-+ goto out; /* no need to wait */
-+
-+ if (chan_dev->tx_count < CHAN_TX_FRAMES * chan_dev->chan_count)
-+ break;
-+
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+ loops++;
-+ if ((res = wait_event_interruptible
-+ (port->chan_tx_waitq,
-+ atomic_read (&port->chan_tx_irq_number) != prev_irq)))
-+ goto out;
-+ spin_lock_irqsave(&npe_lock, flags);
-+ continue;
-+ }
-+
-+#if 0
-+ if (loops > 1)
-+ printk(KERN_DEBUG "ENTRY TX_first %u tx_count %u count %i"
-+ " last_tx %u loops %i\n", chan_dev->tx_first,
-+ chan_dev->tx_count, count, port->chan_last_tx, loops);
-+#endif
-+ tx_buf = chan_tx_buf(port);
-+ while (chan_dev->tx_count < CHAN_TX_FRAMES * chan_dev->chan_count &&
-+ res < count) {
-+ unsigned int tail, chan, frame;
-+
-+ tail = (chan_dev->tx_first + chan_dev->tx_count) %
-+ (CHAN_TX_FRAMES * chan_dev->chan_count);
-+ chan = tail % chan_dev->chan_count;
-+ frame = tail / chan_dev->chan_count;
-+ chan = chan_dev->log_channels[chan];
-+
-+ if (get_user(tx_buf[chan * CHAN_TX_FRAMES + frame], buf++)) {
-+ printk(KERN_DEBUG "BUG? TX %u %u %u\n",
-+ tail, chan, frame);
-+ res = -EFAULT;
-+ goto out_sync;
-+ }
-+ chan_dev->tx_count++;
-+ res++;
-+ }
-+out_sync:
-+ dma_sync_single(port->dev, port->chan_tx_buf_phys,
-+ chan_tx_buf_len(port), DMA_TO_DEVICE);
-+out:
-+#if 0
-+ printk(KERN_DEBUG "EXIT TX_first %u tx_count %u res %i\n",
-+ chan_dev->tx_first, chan_dev->tx_count, res);
-+#endif
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+ return res;
-+}
-+
-+
-+static unsigned int hss_chan_poll(struct file *file, poll_table *wait)
-+{
-+ struct chan_device *chan_dev = inode_to_chan_dev
-+ (file->f_path.dentry->d_inode);
-+ struct port *port = chan_dev->port;
-+ unsigned long flags;
-+ unsigned int mask = 0;
-+
-+ spin_lock_irqsave(&npe_lock, flags);
-+ poll_wait(file, &port->chan_tx_waitq, wait);
-+ poll_wait(file, &port->chan_rx_waitq, wait);
-+
-+ if (chan_dev->tx_count < CHAN_TX_FRAMES * chan_dev->chan_count)
-+ mask |= POLLOUT | POLLWRNORM;
-+ if (chan_dev->rx_count)
-+ mask |= POLLIN | POLLRDNORM;
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+ return mask;
-+}
-+
-+/*****************************************************************************
-+ * channelized device sysfs attributes
-+ ****************************************************************************/
-+
-+static ssize_t chan_show_chan(struct device *dev, struct device_attribute *attr,
-+ char *buf)
-+{
-+ struct chan_device *chan_dev = dev_get_drvdata(dev);
-+
-+ return print_channels(chan_dev->port, buf, chan_dev->id);
-+}
-+
-+static ssize_t chan_set_chan(struct device *dev, struct device_attribute *attr,
-+ const char *buf, size_t len)
-+{
-+ struct chan_device *chan_dev = dev_get_drvdata(dev);
-+ struct port *port = chan_dev->port;
-+ unsigned long flags;
-+ unsigned int ch;
-+ size_t orig_len = len;
-+ int err;
-+
-+ if (len && buf[len - 1] == '\n')
-+ len--;
-+
-+ if (len != 7 || memcmp(buf, "destroy", 7))
-+ return -EINVAL;
-+
-+ spin_lock_irqsave(&npe_lock, flags);
-+ cdev_del(&chan_dev->cdev);
-+
-+ for (ch = 0; ch < MAX_CHANNELS; ch++)
-+ if (port->channels[ch] == chan_dev->id)
-+ port->channels[ch] = CHANNEL_UNUSED;
-+ port->chan_devices[chan_dev->id] = NULL;
-+ kfree(chan_dev);
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+
-+ if ((err = device_schedule_callback(dev, device_unregister)))
-+ return err;
-+ return orig_len;
-+}
-+
-+static struct device_attribute chan_attr =
-+ __ATTR(channels, 0644, chan_show_chan, chan_set_chan);
-+
-+/*****************************************************************************
-+ * main sysfs attributes
-+ ****************************************************************************/
-+
-+static const struct file_operations chan_fops = {
-+ .owner = THIS_MODULE,
-+ .llseek = no_llseek,
-+ .read = hss_chan_read,
-+ .write = hss_chan_write,
-+ .poll = hss_chan_poll,
-+ .open = hss_chan_open,
-+ .release = hss_chan_release,
-+};
-+
-+static ssize_t create_chan(struct device *dev, struct device_attribute *attr,
-+ const char *buf, size_t len)
-+{
-+ struct port *port = dev_get_drvdata(dev);
-+ struct chan_device *chan_dev;
-+ u8 channels[MAX_CHANNELS];
-+ size_t orig_len = len;
-+ unsigned long flags;
-+ unsigned int ch, id;
-+ int minor, err;
-+
-+ if ((err = parse_channels(&buf, &len, channels)) < 1)
-+ return err;
-+
-+ if (!(chan_dev = kzalloc(sizeof(struct chan_device), GFP_KERNEL)))
-+ return -ENOBUFS;
-+
-+ spin_lock_irqsave(&npe_lock, flags);
-+
-+ if (port->mode != MODE_RAW && port->mode != MODE_G704) {
-+ err = -EINVAL;
-+ goto free;
-+ }
-+
-+ for (ch = 0; ch < MAX_CHANNELS; ch++)
-+ if (channels[ch] && port->channels[ch] != CHANNEL_UNUSED) {
-+ printk(KERN_DEBUG "Channel #%i already in use\n", ch);
-+ err = -EBUSY;
-+ goto free;
-+ }
-+
-+ for (id = 0; id < MAX_CHAN_DEVICES; id++)
-+ if (port->chan_devices[id] == NULL)
-+ break;
-+
-+ if (id == MAX_CHAN_DEVICES) {
-+ err = -EBUSY;
-+ goto free;
-+ }
-+
-+ for (ch = 0; ch < MAX_CHANNELS; ch++)
-+ if (channels[ch])
-+ break;
-+
-+ minor = port->id * MAX_CHAN_DEVICES + ch;
-+ chan_dev->id = id;
-+ chan_dev->port = port;
-+ chan_dev->dev = device_create(hss_class, dev, MKDEV(chan_major, minor),
-+ "hss%uch%u", port->id, ch);
-+ if (IS_ERR(chan_dev->dev)) {
-+ err = PTR_ERR(chan_dev->dev);
-+ goto free;
-+ }
-+
-+ cdev_init(&chan_dev->cdev, &chan_fops);
-+ chan_dev->cdev.owner = THIS_MODULE;
-+ if ((err = cdev_add(&chan_dev->cdev, MKDEV(chan_major, minor), 1)))
-+ goto destroy_device;
-+
-+ for (ch = 0; ch < MAX_CHANNELS; ch++)
-+ if (channels[ch])
-+ port->channels[ch] = id;
-+ port->chan_devices[id] = chan_dev;
-+ dev_set_drvdata(chan_dev->dev, chan_dev);
-+ BUG_ON(device_create_file(chan_dev->dev, &chan_attr));
-+
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+ return orig_len;
-+
-+destroy_device:
-+ device_unregister(chan_dev->dev);
-+free:
-+ kfree(chan_dev);
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+ return err;
-+}
-+
-+static ssize_t show_hdlc_chan(struct device *dev, struct device_attribute *attr,
-+ char *buf)
-+{
-+ return print_channels(dev_get_drvdata(dev), buf, CHANNEL_HDLC);
-+}
-+
-+static ssize_t set_hdlc_chan(struct device *dev, struct device_attribute *attr,
-+ const char *buf, size_t len)
-+{
-+ struct port *port = dev_get_drvdata(dev);
-+ u8 channels[MAX_CHANNELS];
-+ size_t orig_len = len;
-+ unsigned long flags;
-+ unsigned int ch;
-+ int err;
-+
-+ if ((err = parse_channels(&buf, &len, channels)) < 0)
-+ return err;
-+
-+ spin_lock_irqsave(&npe_lock, flags);
-+
-+ if (port->mode != MODE_RAW && port->mode != MODE_G704) {
-+ err = -EINVAL;
-+ goto err;
-+ }
-+
-+ for (ch = 0; ch < MAX_CHANNELS; ch++)
-+ if (channels[ch] &&
-+ port->channels[ch] != CHANNEL_UNUSED &&
-+ port->channels[ch] != CHANNEL_HDLC) {
-+ printk(KERN_DEBUG "Channel #%i already in use\n", ch);
-+ err = -EBUSY;
-+ goto err;
-+ }
-+
-+ for (ch = 0; ch < MAX_CHANNELS; ch++)
-+ if (channels[ch])
-+ port->channels[ch] = CHANNEL_HDLC;
-+ else if (port->channels[ch] == CHANNEL_HDLC)
-+ port->channels[ch] = CHANNEL_UNUSED;
-+
-+ if (port->chan_open_count || port->hdlc_open) {
-+ hss_config_set_lut(port);
-+ hss_config_load(port);
-+ }
-+
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+ return orig_len;
-+
-+err:
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+ return err;
-+}
-+
-+static ssize_t show_clock_type(struct device *dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ struct port *port = dev_get_drvdata(dev);
-+
-+ strcpy(buf, port->clock_type == CLOCK_INT ? "int\n" : "ext\n");
-+ return 5;
-+}
-+
-+static ssize_t set_clock_type(struct device *dev, struct device_attribute *attr,
-+ const char *buf, size_t len)
-+{
-+ struct port *port = dev_get_drvdata(dev);
-+ size_t orig_len = len;
-+ unsigned long flags;
-+ unsigned int clk, err;
-+
-+ if (len && buf[len - 1] == '\n')
-+ len--;
-+
-+ if (len != 3)
-+ return -EINVAL;
-+ if (!memcmp(buf, "ext", 3))
-+ clk = CLOCK_EXT;
-+ else if (!memcmp(buf, "int", 3))
-+ clk = CLOCK_INT;
-+ else
-+ return -EINVAL;
-+
-+ spin_lock_irqsave(&npe_lock, flags);
-+ if (port->plat->set_clock)
-+ clk = port->plat->set_clock(port->id, clk);
-+ if (clk != CLOCK_EXT && clk != CLOCK_INT) {
-+ err = -EINVAL; /* plat->set_clock shouldn't change the state */
-+ goto err;
-+ }
-+ port->clock_type = clk;
-+ if (port->chan_open_count || port->hdlc_open) {
-+ hss_config_set_line(port);
-+ hss_config_load(port);
-+ }
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+
-+ return orig_len;
-+err:
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+ return err;
-+}
-+
-+static ssize_t show_clock_rate(struct device *dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ struct port *port = dev_get_drvdata(dev);
-+
-+ sprintf(buf, "%u\n", port->clock_rate);
-+ return strlen(buf) + 1;
-+}
-+
-+static ssize_t set_clock_rate(struct device *dev, struct device_attribute *attr,
-+ const char *buf, size_t len)
-+{
-+#if 0
-+ struct port *port = dev_get_drvdata(dev);
-+ size_t orig_len = len;
-+ unsigned long flags;
-+ unsigned int rate;
-+
-+ if (len && buf[len - 1] == '\n')
-+ len--;
-+
-+ if (get_number(&buf, &len, &rate, 1, 0xFFFFFFFFu))
-+ return -EINVAL;
-+ if (len)
-+ return -EINVAL;
-+
-+ spin_lock_irqsave(&npe_lock, flags);
-+ port->clock_rate = rate;
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+ return orig_len;
-+#endif
-+ return -EINVAL; /* FIXME not yet supported */
-+}
-+
-+static ssize_t show_frame_size(struct device *dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ struct port *port = dev_get_drvdata(dev);
-+
-+ if (port->mode != MODE_RAW && port->mode != MODE_G704)
-+ return -EINVAL;
-+
-+ sprintf(buf, "%u\n", port->frame_size);
-+ return strlen(buf) + 1;
-+}
-+
-+static ssize_t set_frame_size(struct device *dev, struct device_attribute *attr,
-+ const char *buf, size_t len)
-+{
-+ struct port *port = dev_get_drvdata(dev);
-+ size_t ret = len;
-+ unsigned long flags;
-+ unsigned int size;
-+
-+ if (len && buf[len - 1] == '\n')
-+ len--;
-+
-+ if (get_number(&buf, &len, &size, MIN_FRAME_SIZE, MAX_FRAME_SIZE))
-+ return -EINVAL;
-+ if (len || size % 8 > 1)
-+ return -EINVAL;
-+
-+ spin_lock_irqsave(&npe_lock, flags);
-+ if (port->mode != MODE_RAW && port->mode != MODE_G704)
-+ ret = -EINVAL;
-+ else if (!port->chan_open_count && !port->hdlc_open)
-+ ret = -EBUSY;
-+ else {
-+ port->frame_size = size;
-+ port->frame_sync_offset = 0;
-+ }
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+ return ret;
-+}
-+
-+static ssize_t show_frame_offset(struct device *dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ struct port *port = dev_get_drvdata(dev);
-+
-+ sprintf(buf, "%u\n", port->frame_sync_offset);
-+ return strlen(buf) + 1;
-+}
-+
-+static ssize_t set_frame_offset(struct device *dev,
-+ struct device_attribute *attr,
-+ const char *buf, size_t len)
-+{
-+ struct port *port = dev_get_drvdata(dev);
-+ size_t orig_len = len;
-+ unsigned long flags;
-+ unsigned int offset;
-+
-+ if (len && buf[len - 1] == '\n')
-+ len--;
-+
-+ if (get_number(&buf, &len, &offset, 0, port->frame_size - 1))
-+ return -EINVAL;
-+ if (len)
-+ return -EINVAL;
-+
-+ spin_lock_irqsave(&npe_lock, flags);
-+
-+ port->frame_sync_offset = offset;
-+ if (port->chan_open_count || port->hdlc_open) {
-+ hss_config_set_rx_frame(port);
-+ hss_config_load(port);
-+ }
-+
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+ return orig_len;
-+}
-+
-+static ssize_t show_loopback(struct device *dev, struct device_attribute *attr,
-+ char *buf)
-+{
-+ struct port *port = dev_get_drvdata(dev);
-+
-+ sprintf(buf, "%u\n", port->loopback);
-+ return strlen(buf) + 1;
-+}
-+
-+static ssize_t set_loopback(struct device *dev, struct device_attribute *attr,
-+ const char *buf, size_t len)
-+{
-+ struct port *port = dev_get_drvdata(dev);
-+ size_t orig_len = len;
-+ unsigned long flags;
-+ unsigned int lb;
-+
-+ if (len && buf[len - 1] == '\n')
-+ len--;
-+
-+ if (get_number(&buf, &len, &lb, 0, 1))
-+ return -EINVAL;
-+ if (len)
-+ return -EINVAL;
-+
-+ spin_lock_irqsave(&npe_lock, flags);
-+
-+ if (port->loopback != lb) {
-+ port->loopback = lb;
-+ if (port->chan_open_count || port->hdlc_open) {
-+ hss_config_set_core(port);
-+ hss_config_load(port);
-+ }
-+ if (port->loopback || port->carrier)
-+ netif_carrier_on(port->netdev);
-+ else
-+ netif_carrier_off(port->netdev);
-+ }
-+
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+ return orig_len;
-+}
-+
-+static ssize_t show_mode(struct device *dev, struct device_attribute *attr,
-+ char *buf)
-+{
-+ struct port *port = dev_get_drvdata(dev);
-+
-+ switch(port->mode) {
-+ case MODE_RAW:
-+ strcpy(buf, "raw\n");
-+ break;
-+ case MODE_G704:
-+ strcpy(buf, "g704\n");
-+ break;
-+ default:
-+ strcpy(buf, "hdlc\n");
-+ break;
-+ }
-+ return strlen(buf) + 1;
-+}
-+
-+static ssize_t set_mode(struct device *dev, struct device_attribute *attr,
-+ const char *buf, size_t len)
-+{
-+ struct port *port = dev_get_drvdata(dev);
-+ size_t ret = len;
-+ unsigned long flags;
-+
-+ if (len && buf[len - 1] == '\n')
-+ len--;
-+
-+ spin_lock_irqsave(&npe_lock, flags);
-+
-+ if (port->chan_open_count || port->hdlc_open) {
-+ ret = -EBUSY;
-+ } else if (len == 4 && !memcmp(buf, "hdlc", 4))
-+ port->mode = MODE_HDLC;
-+ else if (len == 3 && !memcmp(buf, "raw", 3))
-+ port->mode = MODE_RAW;
-+ else if (len == 4 && !memcmp(buf, "g704", 4))
-+ port->mode = MODE_G704;
-+ else
-+ ret = -EINVAL;
-+
-+ spin_unlock_irqrestore(&npe_lock, flags);
-+ return ret;
-+}
-+
-+static struct device_attribute hss_attrs[] = {
-+ __ATTR(create_chan, 0200, NULL, create_chan),
-+ __ATTR(hdlc_chan, 0644, show_hdlc_chan, set_hdlc_chan),
-+ __ATTR(clock_type, 0644, show_clock_type, set_clock_type),
-+ __ATTR(clock_rate, 0644, show_clock_rate, set_clock_rate),
-+ __ATTR(frame_size, 0644, show_frame_size, set_frame_size),
-+ __ATTR(frame_offset, 0644, show_frame_offset, set_frame_offset),
-+ __ATTR(loopback, 0644, show_loopback, set_loopback),
-+ __ATTR(mode, 0644, show_mode, set_mode),
-+};
-+
-+/*****************************************************************************
-+ * initialization
-+ ****************************************************************************/
-+
-+static int __devinit hss_init_one(struct platform_device *pdev)
-+{
-+ struct port *port;
-+ struct net_device *dev;
-+ hdlc_device *hdlc;
-+ int i, err;
-+
-+ if ((port = kzalloc(sizeof(*port), GFP_KERNEL)) == NULL)
-+ return -ENOMEM;
-+ platform_set_drvdata(pdev, port);
-+ port->id = pdev->id;
-+
-+ if ((port->npe = npe_request(0)) == NULL) {
-+ err = -ENOSYS;
-+ goto err_free;
-+ }
-+
-+ port->dev = &pdev->dev;
-+ port->plat = pdev->dev.platform_data;
-+ if ((port->netdev = dev = alloc_hdlcdev(port)) == NULL) {
-+ err = -ENOMEM;
-+ goto err_plat;
-+ }
-+
-+ SET_NETDEV_DEV(dev, &pdev->dev);
-+ hdlc = dev_to_hdlc(dev);
-+ hdlc->attach = hss_hdlc_attach;
-+ hdlc->xmit = hss_hdlc_xmit;
-+ dev->open = hss_hdlc_open;
-+ dev->stop = hss_hdlc_close;
-+ dev->do_ioctl = hss_hdlc_ioctl;
-+ dev->tx_queue_len = 100;
-+ port->clock_type = CLOCK_EXT;
-+ port->clock_rate = 2048000;
-+ port->frame_size = 256; /* E1 */
-+ memset(port->channels, CHANNEL_UNUSED, sizeof(port->channels));
-+ init_waitqueue_head(&port->chan_tx_waitq);
-+ init_waitqueue_head(&port->chan_rx_waitq);
-+ netif_napi_add(dev, &port->napi, hss_hdlc_poll, NAPI_WEIGHT);
-+
-+ if ((err = register_hdlc_device(dev))) /* HDLC mode by default */
-+ goto err_free_netdev;
-+
-+ for (i = 0; i < ARRAY_SIZE(hss_attrs); i++)
-+ BUG_ON(device_create_file(port->dev, &hss_attrs[i]));
-+
-+ printk(KERN_INFO "%s: HSS-%i\n", dev->name, port->id);
-+ return 0;
-+
-+err_free_netdev:
-+ free_netdev(dev);
-+err_plat:
-+ npe_release(port->npe);
-+ platform_set_drvdata(pdev, NULL);
-+err_free:
-+ kfree(port);
-+ return err;
-+}
-+
-+static int __devexit hss_remove_one(struct platform_device *pdev)
-+{
-+ struct port *port = platform_get_drvdata(pdev);
-+ int i;
-+
-+ for (i = 0; i < ARRAY_SIZE(hss_attrs); i++)
-+ device_remove_file(port->dev, &hss_attrs[i]);
-+
-+ unregister_hdlc_device(port->netdev);
-+ free_netdev(port->netdev);
-+ npe_release(port->npe);
-+ platform_set_drvdata(pdev, NULL);
-+ kfree(port);
-+ return 0;
-+}
-+
-+static struct platform_driver drv = {
-+ .driver.name = DRV_NAME,
-+ .probe = hss_init_one,
-+ .remove = hss_remove_one,
-+};
-+
-+static int __init hss_init_module(void)
-+{
-+ int err;
-+ dev_t rdev;
-+
-+ if ((ixp4xx_read_feature_bits() &
-+ (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) !=
-+ (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS))
-+ return -ENOSYS;
-+
-+ if ((err = alloc_chrdev_region(&rdev, 0, HSS_COUNT * MAX_CHAN_DEVICES,
-+ "hss")))
-+ return err;
-+
-+ spin_lock_init(&npe_lock);
-+
-+ if (IS_ERR(hss_class = class_create(THIS_MODULE, "hss"))) {
-+ printk(KERN_ERR "Can't register device class 'hss'\n");
-+ err = PTR_ERR(hss_class);
-+ goto free_chrdev;
-+ }
-+ if ((err = platform_driver_register(&drv)))
-+ goto destroy_class;
-+
-+ chan_major = MAJOR(rdev);
-+ return 0;
-+
-+destroy_class:
-+ class_destroy(hss_class);
-+free_chrdev:
-+ unregister_chrdev_region(MKDEV(chan_major, 0),
-+ HSS_COUNT * MAX_CHAN_DEVICES);
-+ return err;
-+}
-+
-+static void __exit hss_cleanup_module(void)
-+{
-+ platform_driver_unregister(&drv);
-+ class_destroy(hss_class);
-+ unregister_chrdev_region(MKDEV(chan_major, 0),
-+ HSS_COUNT * MAX_CHAN_DEVICES);
-+}
-+
-+MODULE_AUTHOR("Krzysztof Halasa");
-+MODULE_DESCRIPTION("Intel IXP4xx HSS driver");
-+MODULE_LICENSE("GPL v2");
-+MODULE_ALIAS("platform:ixp4xx_hss");
-+module_init(hss_init_module);
-+module_exit(hss_cleanup_module);
+++ /dev/null
---- a/drivers/i2c/chips/eeprom.c
-+++ b/drivers/i2c/chips/eeprom.c
-@@ -33,6 +33,8 @@
- #include <linux/jiffies.h>
- #include <linux/i2c.h>
- #include <linux/mutex.h>
-+#include <linux/notifier.h>
-+#include <linux/eeprom.h>
-
- /* Addresses to scan */
- static const unsigned short normal_i2c[] = { 0x50, 0x51, 0x52, 0x53, 0x54,
-@@ -41,26 +43,7 @@
- /* Insmod parameters */
- I2C_CLIENT_INSMOD_1(eeprom);
-
--
--/* Size of EEPROM in bytes */
--#define EEPROM_SIZE 256
--
--/* possible types of eeprom devices */
--enum eeprom_nature {
-- UNKNOWN,
-- VAIO,
--};
--
--/* Each client has this additional data */
--struct eeprom_data {
-- struct i2c_client client;
-- struct mutex update_lock;
-- u8 valid; /* bitfield, bit!=0 if slice is valid */
-- unsigned long last_updated[8]; /* In jiffies, 8 slices */
-- u8 data[EEPROM_SIZE]; /* Register values */
-- enum eeprom_nature nature;
--};
--
-+ATOMIC_NOTIFIER_HEAD(eeprom_chain);
-
- static int eeprom_attach_adapter(struct i2c_adapter *adapter);
- static int eeprom_detect(struct i2c_adapter *adapter, int address, int kind);
-@@ -197,6 +180,7 @@
- data->valid = 0;
- mutex_init(&data->update_lock);
- data->nature = UNKNOWN;
-+ data->attr = &eeprom_attr;
-
- /* Tell the I2C layer a new client has arrived */
- if ((err = i2c_attach_client(new_client)))
-@@ -224,6 +208,9 @@
- if (err)
- goto exit_detach;
-
-+ /* call the notifier chain */
-+ atomic_notifier_call_chain(&eeprom_chain, EEPROM_REGISTER, data);
-+
- return 0;
-
- exit_detach:
-@@ -249,6 +236,41 @@
- return 0;
- }
-
-+/**
-+ * register_eeprom_notifier - register a 'user' of EEPROM devices.
-+ * @nb: pointer to notifier info structure
-+ *
-+ * Registers a callback function to be called upon detection
-+ * of an EEPROM device. Detection invokes the 'add' callback
-+ * with the kobj of the mutex and a bin_attribute which allows
-+ * read from the EEPROM. The intention is that the notifier
-+ * will be able to read system configuration from the notifier.
-+ *
-+ * Only EEPROMs detected *after* the addition of the notifier
-+ * are notified. I.e. EEPROMs already known to the system
-+ * will not be notified - add the notifier from board level
-+ * code!
-+ */
-+int register_eeprom_notifier(struct notifier_block *nb)
-+{
-+ return atomic_notifier_chain_register(&eeprom_chain, nb);
-+}
-+
-+/**
-+ * unregister_eeprom_notifier - unregister a 'user' of EEPROM devices.
-+ * @old: pointer to notifier info structure
-+ *
-+ * Removes a callback function from the list of 'users' to be
-+ * notified upon detection of EEPROM devices.
-+ */
-+int unregister_eeprom_notifier(struct notifier_block *nb)
-+{
-+ return atomic_notifier_chain_unregister(&eeprom_chain, nb);
-+}
-+
-+EXPORT_SYMBOL_GPL(register_eeprom_notifier);
-+EXPORT_SYMBOL_GPL(unregister_eeprom_notifier);
-+
- static int __init eeprom_init(void)
- {
- return i2c_add_driver(&eeprom_driver);
---- /dev/null
-+++ b/include/linux/eeprom.h
-@@ -0,0 +1,71 @@
-+#ifndef _LINUX_EEPROM_H
-+#define _LINUX_EEPROM_H
-+/*
-+ * EEPROM notifier header
-+ *
-+ * Copyright (C) 2006 John Bowler
-+ */
-+
-+/*
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#ifndef __KERNEL__
-+#error This is a kernel header
-+#endif
-+
-+#include <linux/list.h>
-+#include <linux/kobject.h>
-+#include <linux/sysfs.h>
-+
-+/* Size of EEPROM in bytes */
-+#define EEPROM_SIZE 256
-+
-+/* possible types of eeprom devices */
-+enum eeprom_nature {
-+ UNKNOWN,
-+ VAIO,
-+};
-+
-+/* Each client has this additional data */
-+struct eeprom_data {
-+ struct i2c_client client;
-+ struct mutex update_lock;
-+ u8 valid; /* bitfield, bit!=0 if slice is valid */
-+ unsigned long last_updated[8]; /* In jiffies, 8 slices */
-+ u8 data[EEPROM_SIZE]; /* Register values */
-+ enum eeprom_nature nature;
-+ struct bin_attribute *attr;
-+};
-+
-+/*
-+ * This is very basic.
-+ *
-+ * If an EEPROM is detected on the I2C bus (this only works for
-+ * I2C EEPROMs) the notifier chain is called with
-+ * both the I2C information and the kobject for the sysfs
-+ * device which has been registers. It is then possible to
-+ * read from the device via the bin_attribute::read method
-+ * to extract configuration information.
-+ *
-+ * Register the notifier in the board level code, there is no
-+ * need to unregister it but you can if you want (it will save
-+ * a little bit or kernel memory to do so).
-+ */
-+
-+extern int register_eeprom_notifier(struct notifier_block *nb);
-+extern int unregister_eeprom_notifier(struct notifier_block *nb);
-+
-+#endif /* _LINUX_EEPROM_H */
---- a/include/linux/notifier.h
-+++ b/include/linux/notifier.h
-@@ -253,5 +253,8 @@
- #define VT_UPDATE 0x0004 /* A bigger update occurred */
- #define VT_PREWRITE 0x0005 /* A char is about to be written to the console */
-
-+/* eeprom notifier chain */
-+#define EEPROM_REGISTER 0x0001
-+
- #endif /* __KERNEL__ */
- #endif /* _LINUX_NOTIFIER_H */
+++ /dev/null
---- a/drivers/leds/Kconfig
-+++ b/drivers/leds/Kconfig
-@@ -117,6 +117,12 @@
- outputs. To be useful the particular board must have LEDs
- and they must be connected to the GPIO lines.
-
-+config LEDS_LATCH
-+ tristate "LED Support for Memory Latched LEDs"
-+ depends on LEDS_CLASS
-+ help
-+ -- To Do --
-+
- config LEDS_CM_X270
- tristate "LED Support for the CM-X270 LEDs"
- depends on LEDS_CLASS && MACH_ARMCORE
---- /dev/null
-+++ b/drivers/leds/leds-latch.c
-@@ -0,0 +1,141 @@
-+/*
-+ * LEDs driver for Memory Latched Devices
-+ *
-+ * Copyright (C) 2008 Gateworks Corp.
-+ * Chris Lang <clang@gateworks.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ */
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/platform_device.h>
-+#include <linux/leds.h>
-+#include <linux/workqueue.h>
-+#include <asm/io.h>
-+#include <linux/spinlock.h>
-+
-+static unsigned int mem_keep = 0xFF;
-+static spinlock_t mem_lock;
-+static unsigned char *iobase;
-+
-+struct latch_led_data {
-+ struct led_classdev cdev;
-+ struct work_struct work;
-+ u8 new_level;
-+ u8 bit;
-+};
-+
-+static void latch_led_set(struct led_classdev *led_cdev,
-+ enum led_brightness value)
-+{
-+ struct latch_led_data *led_dat =
-+ container_of(led_cdev, struct latch_led_data, cdev);
-+
-+ spin_lock(mem_lock);
-+
-+ if (value == LED_OFF)
-+ mem_keep |= (0x1 << led_dat->bit);
-+ else
-+ mem_keep &= ~(0x1 << led_dat->bit);
-+
-+ writeb(mem_keep, iobase);
-+
-+ spin_unlock(mem_lock);
-+}
-+
-+static int latch_led_probe(struct platform_device *pdev)
-+{
-+ struct latch_led_platform_data *pdata = pdev->dev.platform_data;
-+ struct latch_led *cur_led;
-+ struct latch_led_data *leds_data, *led_dat;
-+ int i, ret = 0;
-+
-+ if (!pdata)
-+ return -EBUSY;
-+
-+ leds_data = kzalloc(sizeof(struct latch_led_data) * pdata->num_leds,
-+ GFP_KERNEL);
-+ if (!leds_data)
-+ return -ENOMEM;
-+
-+ iobase = ioremap_nocache(pdata->mem, 0x1000);
-+ writeb(0xFF, iobase);
-+
-+ for (i = 0; i < pdata->num_leds; i++) {
-+ cur_led = &pdata->leds[i];
-+ led_dat = &leds_data[i];
-+
-+ led_dat->cdev.name = cur_led->name;
-+ led_dat->cdev.default_trigger = cur_led->default_trigger;
-+ led_dat->cdev.brightness_set = latch_led_set;
-+ led_dat->cdev.brightness = LED_OFF;
-+ led_dat->bit = cur_led->bit;
-+
-+ ret = led_classdev_register(&pdev->dev, &led_dat->cdev);
-+ if (ret < 0) {
-+ goto err;
-+ }
-+ }
-+
-+ platform_set_drvdata(pdev, leds_data);
-+
-+ return 0;
-+
-+err:
-+ if (i > 0) {
-+ for (i = i - 1; i >= 0; i--) {
-+ led_classdev_unregister(&leds_data[i].cdev);
-+ }
-+ }
-+
-+ kfree(leds_data);
-+
-+ return ret;
-+}
-+
-+static int __devexit latch_led_remove(struct platform_device *pdev)
-+{
-+ int i;
-+ struct latch_led_platform_data *pdata = pdev->dev.platform_data;
-+ struct latch_led_data *leds_data;
-+
-+ leds_data = platform_get_drvdata(pdev);
-+
-+ for (i = 0; i < pdata->num_leds; i++) {
-+ led_classdev_unregister(&leds_data[i].cdev);
-+ cancel_work_sync(&leds_data[i].work);
-+ }
-+
-+ kfree(leds_data);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver latch_led_driver = {
-+ .probe = latch_led_probe,
-+ .remove = __devexit_p(latch_led_remove),
-+ .driver = {
-+ .name = "leds-latch",
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+static int __init latch_led_init(void)
-+{
-+ return platform_driver_register(&latch_led_driver);
-+}
-+
-+static void __exit latch_led_exit(void)
-+{
-+ platform_driver_unregister(&latch_led_driver);
-+}
-+
-+module_init(latch_led_init);
-+module_exit(latch_led_exit);
-+
-+MODULE_AUTHOR("Chris Lang <clang@gateworks.com>");
-+MODULE_DESCRIPTION("Latch LED driver");
-+MODULE_LICENSE("GPL");
---- a/drivers/leds/Makefile
-+++ b/drivers/leds/Makefile
-@@ -18,6 +18,7 @@
- obj-$(CONFIG_LEDS_COBALT_QUBE) += leds-cobalt-qube.o
- obj-$(CONFIG_LEDS_COBALT_RAQ) += leds-cobalt-raq.o
- obj-$(CONFIG_LEDS_GPIO) += leds-gpio.o
-+obj-$(CONFIG_LEDS_LATCH) += leds-latch.o
- obj-$(CONFIG_LEDS_CM_X270) += leds-cm-x270.o
- obj-$(CONFIG_LEDS_CLEVO_MAIL) += leds-clevo-mail.o
- obj-$(CONFIG_LEDS_HP6XX) += leds-hp6xx.o
---- a/include/linux/leds.h
-+++ b/include/linux/leds.h
-@@ -134,5 +134,18 @@
- unsigned long *delay_off);
- };
-
-+/* For the leds-latch driver */
-+struct latch_led {
-+ const char *name;
-+ char *default_trigger;
-+ unsigned bit;
-+};
-+
-+struct latch_led_platform_data {
-+ int num_leds;
-+ u32 mem;
-+ struct latch_led *leds;
-+};
-+
-
- #endif /* __LINUX_LEDS_H_INCLUDED */
+++ /dev/null
---- a/arch/arm/mach-ixp4xx/avila-setup.c
-+++ b/arch/arm/mach-ixp4xx/avila-setup.c
-@@ -132,6 +132,31 @@
- .resource = avila_pata_resources,
- };
-
-+/* Built-in 10/100 Ethernet MAC interfaces */
-+static struct eth_plat_info avila_npeb_data = {
-+ .phy = 0,
-+ .rxq = 3,
-+ .txreadyq = 20,
-+};
-+
-+static struct eth_plat_info avila_npec_data = {
-+ .phy = 1,
-+ .rxq = 4,
-+ .txreadyq = 21,
-+};
-+
-+static struct platform_device avila_npeb_device = {
-+ .name = "ixp4xx_eth",
-+ .id = IXP4XX_ETH_NPEB,
-+ .dev.platform_data = &avila_npeb_data,
-+};
-+
-+static struct platform_device avila_npec_device = {
-+ .name = "ixp4xx_eth",
-+ .id = IXP4XX_ETH_NPEC,
-+ .dev.platform_data = &avila_npec_data,
-+};
-+
- static struct platform_device *avila_devices[] __initdata = {
- &avila_i2c_gpio,
- &avila_flash,
-@@ -159,6 +184,8 @@
-
- platform_device_register(&avila_pata);
-
-+ platform_device_register(avila_npeb_device);
-+ platform_device_register(avila_npec_device);
- }
-
- MACHINE_START(AVILA, "Gateworks Avila Network Platform")
+++ /dev/null
---- a/arch/arm/mach-ixp4xx/avila-setup.c
-+++ b/arch/arm/mach-ixp4xx/avila-setup.c
-@@ -14,10 +14,18 @@
- #include <linux/kernel.h>
- #include <linux/init.h>
- #include <linux/device.h>
-+#include <linux/if_ether.h>
-+#include <linux/socket.h>
-+#include <linux/netdevice.h>
- #include <linux/serial.h>
- #include <linux/tty.h>
- #include <linux/serial_8250.h>
- #include <linux/slab.h>
-+#ifdef CONFIG_SENSORS_EEPROM
-+# include <linux/i2c.h>
-+# include <linux/eeprom.h>
-+#endif
-+
- #include <linux/i2c-gpio.h>
-
- #include <asm/types.h>
-@@ -29,6 +37,13 @@
- #include <asm/mach/arch.h>
- #include <asm/mach/flash.h>
-
-+struct avila_board_info {
-+ unsigned char *model;
-+ void (* setup)(void);
-+};
-+
-+static struct avila_board_info *avila_info __initdata;
-+
- static struct flash_platform_data avila_flash_data = {
- .map_name = "cfi_probe",
- .width = 2,
-@@ -163,10 +178,160 @@
- &avila_uart
- };
-
-+static void __init avila_gw23xx_setup(void)
-+{
-+ platform_device_register(&avila_npeb_device);
-+ platform_device_register(&avila_npec_device);
-+}
-+
-+#ifdef CONFIG_SENSORS_EEPROM
-+static void __init avila_gw2342_setup(void)
-+{
-+ platform_device_register(&avila_npeb_device);
-+ platform_device_register(&avila_npec_device);
-+}
-+
-+static void __init avila_gw2345_setup(void)
-+{
-+ avila_npeb_data.phy = IXP4XX_ETH_PHY_MAX_ADDR;
-+ avila_npeb_data.phy_mask = 0x1e; /* ports 1-4 of the KS8995 switch */
-+ platform_device_register(&avila_npeb_device);
-+
-+ avila_npec_data.phy = 5; /* port 5 of the KS8995 switch */
-+ platform_device_register(&avila_npec_device);
-+}
-+
-+static void __init avila_gw2347_setup(void)
-+{
-+ platform_device_register(&avila_npeb_device);
-+}
-+
-+static void __init avila_gw2348_setup(void)
-+{
-+ platform_device_register(&avila_npeb_device);
-+ platform_device_register(&avila_npec_device);
-+}
-+
-+static void __init avila_gw2353_setup(void)
-+{
-+ platform_device_register(&avila_npeb_device);
-+}
-+
-+static void __init avila_gw2355_setup(void)
-+{
-+ avila_npeb_data.phy = IXP4XX_ETH_PHY_MAX_ADDR;
-+ avila_npeb_data.phy_mask = 0x1e; /* ports 1-4 of the KS8995 switch */
-+ platform_device_register(&avila_npeb_device);
-+
-+ avila_npec_data.phy = 16;
-+ platform_device_register(&avila_npec_device);
-+}
-+
-+static void __init avila_gw2357_setup(void)
-+{
-+ platform_device_register(&avila_npeb_device);
-+}
-+
-+static struct avila_board_info avila_boards[] __initdata = {
-+ {
-+ .model = "GW2342",
-+ .setup = avila_gw2342_setup,
-+ }, {
-+ .model = "GW2345",
-+ .setup = avila_gw2345_setup,
-+ }, {
-+ .model = "GW2347",
-+ .setup = avila_gw2347_setup,
-+ }, {
-+ .model = "GW2348",
-+ .setup = avila_gw2348_setup,
-+ }, {
-+ .model = "GW2353",
-+ .setup = avila_gw2353_setup,
-+ }, {
-+ .model = "GW2355",
-+ .setup = avila_gw2355_setup,
-+ }, {
-+ .model = "GW2357",
-+ .setup = avila_gw2357_setup,
-+ }
-+};
-+
-+static struct avila_board_info * __init avila_find_board_info(char *model)
-+{
-+ int i;
-+
-+ for (i = 0; i < ARRAY_SIZE(avila_boards); i++) {
-+ struct avila_board_info *info = &avila_boards[i];
-+ if (strncmp(info->model, model, strlen(info->model)) == 0)
-+ return info;
-+ }
-+
-+ return NULL;
-+}
-+
-+struct avila_eeprom_header {
-+ unsigned char mac0[ETH_ALEN];
-+ unsigned char mac1[ETH_ALEN];
-+ unsigned char res0[4];
-+ unsigned char magic[2];
-+ unsigned char config[14];
-+ unsigned char model[16];
-+};
-+
-+static int __init avila_eeprom_notify(struct notifier_block *self,
-+ unsigned long event, void *t)
-+{
-+ struct eeprom_data *ee = t;
-+ struct avila_eeprom_header hdr;
-+
-+ if (avila_info)
-+ return NOTIFY_DONE;
-+
-+ /* The eeprom is at address 0x51 */
-+ if (event != EEPROM_REGISTER || ee->client.addr != 0x51)
-+ return NOTIFY_DONE;
-+
-+ ee->attr->read(&ee->client.dev.kobj, ee->attr, (char *)&hdr,
-+ 0, sizeof(hdr));
-+
-+ if (hdr.magic[0] != 'G' || hdr.magic[1] != 'W')
-+ return NOTIFY_DONE;
-+
-+ memcpy(&avila_npeb_data.hwaddr, hdr.mac0, ETH_ALEN);
-+ memcpy(&avila_npec_data.hwaddr, hdr.mac1, ETH_ALEN);
-+
-+ avila_info = avila_find_board_info(hdr.model);
-+
-+ return NOTIFY_OK;
-+}
-+
-+static struct notifier_block avila_eeprom_notifier __initdata = {
-+ .notifier_call = avila_eeprom_notify
-+};
-+
-+static void __init avila_register_eeprom_notifier(void)
-+{
-+ register_eeprom_notifier(&avila_eeprom_notifier);
-+}
-+
-+static void __init avila_unregister_eeprom_notifier(void)
-+{
-+ unregister_eeprom_notifier(&avila_eeprom_notifier);
-+}
-+#else /* CONFIG_SENSORS_EEPROM */
-+static inline void avila_register_eeprom_notifier(void) {};
-+static inline void avila_unregister_eeprom_notifier(void) {};
-+#endif /* CONFIG_SENSORS_EEPROM */
-+
- static void __init avila_init(void)
- {
- ixp4xx_sys_init();
-
-+ /*
-+ * These devices are present on all Avila models and don't need any
-+ * model specific setup.
-+ */
- avila_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
- avila_flash_resource.end =
- IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
-@@ -184,9 +349,28 @@
-
- platform_device_register(&avila_pata);
-
-- platform_device_register(avila_npeb_device);
-- platform_device_register(avila_npec_device);
-+ avila_register_eeprom_notifier();
-+}
-+
-+static int __init avila_model_setup(void)
-+{
-+ if (!machine_is_avila())
-+ return 0;
-+
-+ if (avila_info) {
-+ printk(KERN_DEBUG "Running on Gateworks Avila %s\n",
-+ avila_info->model);
-+ avila_info->setup();
-+ } else {
-+ printk(KERN_INFO "Unknown/missing Avila model number"
-+ " -- defaults will be used\n");
-+ avila_gw23xx_setup();
-+ }
-+
-+ avila_unregister_eeprom_notifier();
-+ return 0;
- }
-+late_initcall(avila_model_setup);
-
- MACHINE_START(AVILA, "Gateworks Avila Network Platform")
- /* Maintainer: Deepak Saxena <dsaxena@plexity.net> */
+++ /dev/null
---- a/arch/arm/mach-ixp4xx/avila-setup.c
-+++ b/arch/arm/mach-ixp4xx/avila-setup.c
-@@ -26,6 +26,7 @@
- # include <linux/eeprom.h>
- #endif
-
-+#include <linux/leds.h>
- #include <linux/i2c-gpio.h>
-
- #include <asm/types.h>
-@@ -172,6 +173,72 @@
- .dev.platform_data = &avila_npec_data,
- };
-
-+static struct gpio_led avila_gpio_leds[] = {
-+ {
-+ .name = "user", /* green led */
-+ .gpio = AVILA_GW23XX_LED_USER_GPIO,
-+ .active_low = 1,
-+ }
-+};
-+
-+static struct gpio_led_platform_data avila_gpio_leds_data = {
-+ .num_leds = 1,
-+ .leds = avila_gpio_leds,
-+};
-+
-+static struct platform_device avila_gpio_leds_device = {
-+ .name = "leds-gpio",
-+ .id = -1,
-+ .dev.platform_data = &avila_gpio_leds_data,
-+};
-+
-+static struct latch_led avila_latch_leds[] = {
-+ {
-+ .name = "led0", /* green led */
-+ .bit = 0,
-+ },
-+ {
-+ .name = "led1", /* green led */
-+ .bit = 1,
-+ },
-+ {
-+ .name = "led2", /* green led */
-+ .bit = 2,
-+ },
-+ {
-+ .name = "led3", /* green led */
-+ .bit = 3,
-+ },
-+ {
-+ .name = "led4", /* green led */
-+ .bit = 4,
-+ },
-+ {
-+ .name = "led5", /* green led */
-+ .bit = 5,
-+ },
-+ {
-+ .name = "led6", /* green led */
-+ .bit = 6,
-+ },
-+ {
-+ .name = "led7", /* green led */
-+ .bit = 7,
-+ }
-+};
-+
-+static struct latch_led_platform_data avila_latch_leds_data = {
-+ .num_leds = 8,
-+ .leds = avila_latch_leds,
-+ .mem = 0x51000000,
-+};
-+
-+static struct platform_device avila_latch_leds_device = {
-+ .name = "leds-latch",
-+ .id = -1,
-+ .dev.platform_data = &avila_latch_leds_data,
-+};
-+
- static struct platform_device *avila_devices[] __initdata = {
- &avila_i2c_gpio,
- &avila_flash,
-@@ -182,6 +249,8 @@
- {
- platform_device_register(&avila_npeb_device);
- platform_device_register(&avila_npec_device);
-+
-+ platform_device_register(&avila_gpio_leds_device);
- }
-
- #ifdef CONFIG_SENSORS_EEPROM
-@@ -189,6 +258,8 @@
- {
- platform_device_register(&avila_npeb_device);
- platform_device_register(&avila_npec_device);
-+
-+ platform_device_register(&avila_gpio_leds_device);
- }
-
- static void __init avila_gw2345_setup(void)
-@@ -199,22 +270,30 @@
-
- avila_npec_data.phy = 5; /* port 5 of the KS8995 switch */
- platform_device_register(&avila_npec_device);
-+
-+ platform_device_register(&avila_gpio_leds_device);
- }
-
- static void __init avila_gw2347_setup(void)
- {
- platform_device_register(&avila_npeb_device);
-+
-+ avila_gpio_leds[0].gpio = AVILA_GW23X7_LED_USER_GPIO;
-+ platform_device_register(&avila_gpio_leds_device);
- }
-
- static void __init avila_gw2348_setup(void)
- {
- platform_device_register(&avila_npeb_device);
- platform_device_register(&avila_npec_device);
-+
-+ platform_device_register(&avila_gpio_leds_device);
- }
-
- static void __init avila_gw2353_setup(void)
- {
- platform_device_register(&avila_npeb_device);
-+ platform_device_register(&avila_gpio_leds_device);
- }
-
- static void __init avila_gw2355_setup(void)
-@@ -225,11 +304,29 @@
-
- avila_npec_data.phy = 16;
- platform_device_register(&avila_npec_device);
-+
-+ platform_device_register(&avila_gpio_leds_device);
-+
-+ *IXP4XX_EXP_CS4 |= 0xbfff3c03;
-+ avila_latch_leds[0].name = "RXD";
-+ avila_latch_leds[1].name = "TXD";
-+ avila_latch_leds[2].name = "POL";
-+ avila_latch_leds[3].name = "LNK";
-+ avila_latch_leds[4].name = "ERR";
-+ avila_latch_leds_data.num_leds = 5;
-+ avila_latch_leds_data.mem = 0x54000000;
-+ platform_device_register(&avila_latch_leds_device);
- }
-
- static void __init avila_gw2357_setup(void)
- {
- platform_device_register(&avila_npeb_device);
-+
-+ avila_gpio_leds[0].gpio = AVILA_GW23X7_LED_USER_GPIO;
-+ platform_device_register(&avila_gpio_leds_device);
-+
-+ *IXP4XX_EXP_CS1 |= 0xbfff3c03;
-+ platform_device_register(&avila_latch_leds_device);
- }
-
- static struct avila_board_info avila_boards[] __initdata = {
---- a/include/asm-arm/arch-ixp4xx/avila.h
-+++ b/include/asm-arm/arch-ixp4xx/avila.h
-@@ -36,4 +36,6 @@
- #define AVILA_PCI_INTC_PIN 9
- #define AVILA_PCI_INTD_PIN 8
-
--
-+/* User LEDs */
-+#define AVILA_GW23XX_LED_USER_GPIO 3
-+#define AVILA_GW23X7_LED_USER_GPIO 4
+++ /dev/null
---- a/arch/arm/mach-ixp4xx/avila-setup.c
-+++ b/arch/arm/mach-ixp4xx/avila-setup.c
-@@ -239,10 +239,28 @@
- .dev.platform_data = &avila_latch_leds_data,
- };
-
-+static struct resource avila_gpio_resources[] = {
-+ {
-+ .name = "gpio",
-+ /* FIXME: gpio mask should be model specific */
-+ .start = AVILA_GPIO_MASK,
-+ .end = AVILA_GPIO_MASK,
-+ .flags = 0,
-+ },
-+};
-+
-+static struct platform_device avila_gpio = {
-+ .name = "GPIODEV",
-+ .id = -1,
-+ .num_resources = ARRAY_SIZE(avila_gpio_resources),
-+ .resource = avila_gpio_resources,
-+};
-+
- static struct platform_device *avila_devices[] __initdata = {
- &avila_i2c_gpio,
- &avila_flash,
-- &avila_uart
-+ &avila_uart,
-+ &avila_gpio,
- };
-
- static void __init avila_gw23xx_setup(void)
---- a/include/asm-arm/arch-ixp4xx/avila.h
-+++ b/include/asm-arm/arch-ixp4xx/avila.h
-@@ -39,3 +39,6 @@
- /* User LEDs */
- #define AVILA_GW23XX_LED_USER_GPIO 3
- #define AVILA_GW23X7_LED_USER_GPIO 4
-+
-+/* gpio mask used by platform device */
-+#define AVILA_GPIO_MASK (1 << 1) | (1 << 3) | (1 << 5) | (1 << 7) | (1 << 9)
+++ /dev/null
---- a/arch/arm/mach-ixp4xx/avila-setup.c
-+++ b/arch/arm/mach-ixp4xx/avila-setup.c
-@@ -294,6 +294,7 @@
-
- static void __init avila_gw2347_setup(void)
- {
-+ avila_npeb_data.quirks |= IXP4XX_ETH_QUIRK_GW23X7;
- platform_device_register(&avila_npeb_device);
-
- avila_gpio_leds[0].gpio = AVILA_GW23X7_LED_USER_GPIO;
-@@ -338,6 +339,7 @@
-
- static void __init avila_gw2357_setup(void)
- {
-+ avila_npeb_data.quirks |= IXP4XX_ETH_QUIRK_GW23X7;
- platform_device_register(&avila_npeb_device);
-
- avila_gpio_leds[0].gpio = AVILA_GW23X7_LED_USER_GPIO;
---- a/drivers/net/arm/ixp4xx_eth.c
-+++ b/drivers/net/arm/ixp4xx_eth.c
-@@ -348,6 +348,14 @@
- return;
- }
-
-+ if (port->plat->quirks & IXP4XX_ETH_QUIRK_GW23X7) {
-+ mdio_write(dev, 1, 0x19,
-+ (mdio_read(dev, 1, 0x19) & 0xfffe) | 0x8000);
-+
-+ printk(KERN_DEBUG "%s: phy_id of the DP83848 changed to 0\n",
-+ dev->name);
-+ }
-+
- /* restart auto negotiation */
- bmcr = mdio_read(dev, phy_id, MII_BMCR);
- bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
---- a/include/asm-arm/arch-ixp4xx/platform.h
-+++ b/include/asm-arm/arch-ixp4xx/platform.h
-@@ -104,6 +104,8 @@
- u8 txreadyq;
- u8 hwaddr[6];
- u32 phy_mask;
-+ u32 quirks;
-+#define IXP4XX_ETH_QUIRK_GW23X7 0x00000001
- };
-
- /* Information about built-in HSS (synchronous serial) interfaces */
+++ /dev/null
---- a/arch/arm/mach-ixp4xx/gtwx5715-setup.c
-+++ b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
-@@ -29,6 +29,8 @@
- #include <linux/serial_8250.h>
- #include <linux/slab.h>
-
-+#include <linux/spi/spi_gpio.h>
-+
- #include <asm/types.h>
- #include <asm/setup.h>
- #include <asm/memory.h>
-@@ -121,9 +123,41 @@
- .resource = >wx5715_flash_resource,
- };
-
-+static int gtwx5715_spi_boardinfo_setup(struct spi_board_info *bi,
-+ struct spi_master *master, void *data)
-+{
-+
-+ strlcpy(bi->modalias, "spi-ks8995", sizeof(bi->modalias));
-+
-+ bi->max_speed_hz = 5000000 /* Hz */;
-+ bi->bus_num = master->bus_num;
-+ bi->mode = SPI_MODE_0;
-+
-+ return 0;
-+}
-+
-+static struct spi_gpio_platform_data gtwx5715_spi_bus_data = {
-+ .pin_cs = GTWX5715_KSSPI_SELECT,
-+ .pin_clk = GTWX5715_KSSPI_CLOCK,
-+ .pin_miso = GTWX5715_KSSPI_RXD,
-+ .pin_mosi = GTWX5715_KSSPI_TXD,
-+ .cs_activelow = 1,
-+ .no_spi_delay = 1,
-+ .boardinfo_setup = gtwx5715_spi_boardinfo_setup,
-+};
-+
-+static struct platform_device gtwx5715_spi_bus = {
-+ .name = "spi-gpio",
-+ .id = 0,
-+ .dev = {
-+ .platform_data = >wx5715_spi_bus_data,
-+ },
-+};
-+
- static struct platform_device *gtwx5715_devices[] __initdata = {
- >wx5715_uart_device,
- >wx5715_flash,
-+ >wx5715_spi_bus,
- };
-
- static void __init gtwx5715_init(void)
+++ /dev/null
---- a/arch/arm/mach-ixp4xx/gtwx5715-setup.c
-+++ b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
-@@ -154,10 +154,37 @@
- },
- };
-
-+static struct eth_plat_info gtwx5715_npeb_data = {
-+ .phy = IXP4XX_ETH_PHY_MAX_ADDR,
-+ .phy_mask = 0x1e, /* ports 1-4 of the KS8995 switch */
-+ .rxq = 3,
-+ .txreadyq = 20,
-+};
-+
-+static struct eth_plat_info gtwx5715_npec_data = {
-+ .phy = 5, /* port 5 of the KS8995 switch */
-+ .rxq = 4,
-+ .txreadyq = 21,
-+};
-+
-+static struct platform_device gtwx5715_npeb_device = {
-+ .name = "ixp4xx_eth",
-+ .id = IXP4XX_ETH_NPEB,
-+ .dev.platform_data = >wx5715_npeb_data,
-+};
-+
-+static struct platform_device gtwx5715_npec_device = {
-+ .name = "ixp4xx_eth",
-+ .id = IXP4XX_ETH_NPEC,
-+ .dev.platform_data = >wx5715_npec_data,
-+};
-+
- static struct platform_device *gtwx5715_devices[] __initdata = {
- >wx5715_uart_device,
- >wx5715_flash,
- >wx5715_spi_bus,
-+ >wx5715_npeb_device,
-+ >wx5715_npec_device,
- };
-
- static void __init gtwx5715_init(void)
+++ /dev/null
---- a/drivers/ata/pata_ixp4xx_cf.c
-+++ b/drivers/ata/pata_ixp4xx_cf.c
-@@ -24,17 +24,58 @@
- #include <scsi/scsi_host.h>
-
- #define DRV_NAME "pata_ixp4xx_cf"
--#define DRV_VERSION "0.2"
-+#define DRV_VERSION "0.3"
-
- static int ixp4xx_set_mode(struct ata_link *link, struct ata_device **error)
- {
- struct ata_device *dev;
-+ struct ixp4xx_pata_data *data = link->ap->host->dev->platform_data;
-+ unsigned int pio_mask;
-
- ata_link_for_each_dev(dev, link) {
-+ if (dev->id[ATA_ID_FIELD_VALID] & (1 << 1)){
-+ pio_mask = dev->id[ATA_ID_PIO_MODES] & 0x03;
-+ if (pio_mask & (1 << 1)){
-+ pio_mask = 4;
-+ }else{
-+ pio_mask = 3;
-+ }
-+ }else{
-+ pio_mask = (dev->id[ATA_ID_OLD_PIO_MODES] >> 8);
-+ }
-+ switch (pio_mask){
-+ case 0:
-+ ata_dev_printk(dev, KERN_INFO, "configured for PIO0\n");
-+ dev->pio_mode = XFER_PIO_0;
-+ dev->xfer_mode = XFER_PIO_0;
-+ *data->cs0_cfg = 0x8a473c03;
-+ break;
-+ case 1:
-+ ata_dev_printk(dev, KERN_INFO, "configured for PIO1\n");
-+ dev->pio_mode = XFER_PIO_1;
-+ dev->xfer_mode = XFER_PIO_1;
-+ *data->cs0_cfg = 0x86433c03;
-+ break;
-+ case 2:
-+ ata_dev_printk(dev, KERN_INFO, "configured for PIO2\n");
-+ dev->pio_mode = XFER_PIO_2;
-+ dev->xfer_mode = XFER_PIO_2;
-+ *data->cs0_cfg = 0x82413c03;
-+ break;
-+ case 3:
-+ ata_dev_printk(dev, KERN_INFO, "configured for PIO3\n");
-+ dev->pio_mode = XFER_PIO_3;
-+ dev->xfer_mode = XFER_PIO_3;
-+ *data->cs0_cfg = 0x80823c03;
-+ break;
-+ case 4:
-+ ata_dev_printk(dev, KERN_INFO, "configured for PIO4\n");
-+ dev->pio_mode = XFER_PIO_4;
-+ dev->xfer_mode = XFER_PIO_4;
-+ *data->cs0_cfg = 0x80403c03;
-+ break;
-+ }
- if (ata_dev_enabled(dev)) {
-- ata_dev_printk(dev, KERN_INFO, "configured for PIO0\n");
-- dev->pio_mode = XFER_PIO_0;
-- dev->xfer_mode = XFER_PIO_0;
- dev->xfer_shift = ATA_SHIFT_PIO;
- dev->flags |= ATA_DFLAG_PIO;
- }
-@@ -48,6 +89,7 @@
- unsigned int i;
- unsigned int words = buflen >> 1;
- u16 *buf16 = (u16 *) buf;
-+ unsigned int pio_mask;
- struct ata_port *ap = dev->link->ap;
- void __iomem *mmio = ap->ioaddr.data_addr;
- struct ixp4xx_pata_data *data = ap->host->dev->platform_data;
-@@ -55,8 +97,34 @@
- /* set the expansion bus in 16bit mode and restore
- * 8 bit mode after the transaction.
- */
-- *data->cs0_cfg &= ~(0x01);
-- udelay(100);
-+ if (dev->id[ATA_ID_FIELD_VALID] & (1 << 1)){
-+ pio_mask = dev->id[ATA_ID_PIO_MODES] & 0x03;
-+ if (pio_mask & (1 << 1)){
-+ pio_mask = 4;
-+ }else{
-+ pio_mask = 3;
-+ }
-+ }else{
-+ pio_mask = (dev->id[ATA_ID_OLD_PIO_MODES] >> 8);
-+ }
-+ switch (pio_mask){
-+ case 0:
-+ *data->cs0_cfg = 0xa9643c42;
-+ break;
-+ case 1:
-+ *data->cs0_cfg = 0x85033c42;
-+ break;
-+ case 2:
-+ *data->cs0_cfg = 0x80b23c42;
-+ break;
-+ case 3:
-+ *data->cs0_cfg = 0x80823c42;
-+ break;
-+ case 4:
-+ *data->cs0_cfg = 0x80403c42;
-+ break;
-+ }
-+ udelay(5);
-
- /* Transfer multiple of 2 bytes */
- if (rw == READ)
-@@ -81,8 +149,24 @@
- words++;
- }
-
-- udelay(100);
-- *data->cs0_cfg |= 0x01;
-+ udelay(5);
-+ switch (pio_mask){
-+ case 0:
-+ *data->cs0_cfg = 0x8a473c03;
-+ break;
-+ case 1:
-+ *data->cs0_cfg = 0x86433c03;
-+ break;
-+ case 2:
-+ *data->cs0_cfg = 0x82413c03;
-+ break;
-+ case 3:
-+ *data->cs0_cfg = 0x80823c03;
-+ break;
-+ case 4:
-+ *data->cs0_cfg = 0x80403c03;
-+ break;
-+ }
-
- return words << 1;
- }
+++ /dev/null
---- a/arch/arm/common/dmabounce.c
-+++ b/arch/arm/common/dmabounce.c
-@@ -117,6 +117,10 @@
- } else if (size <= device_info->large.size) {
- pool = &device_info->large;
- } else {
-+#ifdef CONFIG_DMABOUNCE_DEBUG
-+ printk(KERN_INFO "A dma bounce buffer outside the pool size was requested. Requested size was 0x%08X\nThe calling code was :\n", size);
-+ dump_stack();
-+#endif
- pool = NULL;
- }
-
---- a/arch/arm/mach-ixp4xx/Kconfig
-+++ b/arch/arm/mach-ixp4xx/Kconfig
-@@ -244,6 +244,11 @@
- default y
- depends on PCI
-
-+config DMABOUNCE_DEBUG
-+ bool "Enable DMABounce debuging"
-+ default n
-+ depends on DMABOUNCE
-+
- config IXP4XX_INDIRECT_PCI
- bool "Use indirect PCI memory access"
- depends on PCI
+++ /dev/null
---- a/include/asm-arm/arch-ixp4xx/avila.h
-+++ b/include/asm-arm/arch-ixp4xx/avila.h
-@@ -25,7 +25,7 @@
- /*
- * AVILA PCI IRQs
- */
--#define AVILA_PCI_MAX_DEV 4
-+#define AVILA_PCI_MAX_DEV 6
- #define LOFT_PCI_MAX_DEV 6
- #define AVILA_PCI_IRQ_LINES 4
-
--- /dev/null
+--- a/arch/arm/configs/ixp4xx_defconfig
++++ b/arch/arm/configs/ixp4xx_defconfig
+@@ -165,6 +165,7 @@
+ CONFIG_MACH_NAS100D=y
+ CONFIG_MACH_DSMG600=y
+ CONFIG_ARCH_IXDP4XX=y
++CONFIG_MACH_FSG=y
+ CONFIG_CPU_IXP46X=y
+ CONFIG_CPU_IXP43X=y
+ CONFIG_MACH_GTWX5715=y
+@@ -770,7 +771,7 @@
+ # CONFIG_SATA_SIL24 is not set
+ # CONFIG_SATA_SIS is not set
+ # CONFIG_SATA_ULI is not set
+-# CONFIG_SATA_VIA is not set
++CONFIG_SATA_VIA=y
+ # CONFIG_SATA_VITESSE is not set
+ # CONFIG_SATA_INIC162X is not set
+ # CONFIG_PATA_ALI is not set
+@@ -1143,7 +1144,7 @@
+ # CONFIG_SENSORS_VIA686A is not set
+ # CONFIG_SENSORS_VT1211 is not set
+ # CONFIG_SENSORS_VT8231 is not set
+-# CONFIG_SENSORS_W83781D is not set
++CONFIG_SENSORS_W83781D=y
+ # CONFIG_SENSORS_W83791D is not set
+ # CONFIG_SENSORS_W83792D is not set
+ # CONFIG_SENSORS_W83793 is not set
+@@ -1334,8 +1335,8 @@
+ #
+ # LED drivers
+ #
+-# CONFIG_LEDS_IXP4XX is not set
+ CONFIG_LEDS_GPIO=y
++CONFIG_LEDS_FSG=y
+
+ #
+ # LED Triggers
+@@ -1367,7 +1368,7 @@
+ # CONFIG_RTC_DRV_DS1672 is not set
+ # CONFIG_RTC_DRV_MAX6900 is not set
+ # CONFIG_RTC_DRV_RS5C372 is not set
+-# CONFIG_RTC_DRV_ISL1208 is not set
++CONFIG_RTC_DRV_ISL1208=y
+ CONFIG_RTC_DRV_X1205=y
+ CONFIG_RTC_DRV_PCF8563=y
+ # CONFIG_RTC_DRV_PCF8583 is not set
+--- a/arch/arm/mach-ixp4xx/Kconfig
++++ b/arch/arm/mach-ixp4xx/Kconfig
+@@ -125,6 +125,15 @@
+ depends on ARCH_IXDP425 || MACH_IXDP465 || MACH_KIXRP435
+ default y
+
++config MACH_FSG
++ bool
++ prompt "Freecom FSG-3"
++ select PCI
++ help
++ Say 'Y' here if you want your kernel to support Freecom's
++ FSG-3 device. For more information on this platform,
++ see http://www.nslu2-linux.org/wiki/FSG3/HomePage
++
+ #
+ # Certain registers and IRQs are only enabled if supporting IXP465 CPUs
+ #
+--- a/arch/arm/mach-ixp4xx/Makefile
++++ b/arch/arm/mach-ixp4xx/Makefile
+@@ -15,6 +15,7 @@
+ obj-pci-$(CONFIG_MACH_DSMG600) += dsmg600-pci.o
+ obj-pci-$(CONFIG_MACH_GATEWAY7001) += gateway7001-pci.o
+ obj-pci-$(CONFIG_MACH_WG302V2) += wg302v2-pci.o
++obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o
+
+ obj-y += common.o
+
+@@ -28,6 +29,7 @@
+ obj-$(CONFIG_MACH_DSMG600) += dsmg600-setup.o
+ obj-$(CONFIG_MACH_GATEWAY7001) += gateway7001-setup.o
+ obj-$(CONFIG_MACH_WG302V2) += wg302v2-setup.o
++obj-$(CONFIG_MACH_FSG) += fsg-setup.o
+
+ obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
+ obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o
+--- /dev/null
++++ b/arch/arm/mach-ixp4xx/fsg-pci.c
+@@ -0,0 +1,71 @@
++/*
++ * arch/arch/mach-ixp4xx/fsg-pci.c
++ *
++ * FSG board-level PCI initialization
++ *
++ * Author: Rod Whitby <rod@whitby.id.au>
++ * Maintainer: http://www.nslu2-linux.org/
++ *
++ * based on ixdp425-pci.c:
++ * Copyright (C) 2002 Intel Corporation.
++ * Copyright (C) 2003-2004 MontaVista Software, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include <linux/pci.h>
++#include <linux/init.h>
++#include <linux/irq.h>
++
++#include <asm/mach/pci.h>
++#include <asm/mach-types.h>
++
++void __init fsg_pci_preinit(void)
++{
++ set_irq_type(IRQ_FSG_PCI_INTA, IRQT_LOW);
++ set_irq_type(IRQ_FSG_PCI_INTB, IRQT_LOW);
++ set_irq_type(IRQ_FSG_PCI_INTC, IRQT_LOW);
++
++ ixp4xx_pci_preinit();
++}
++
++static int __init fsg_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
++{
++ static int pci_irq_table[FSG_PCI_IRQ_LINES] = {
++ IRQ_FSG_PCI_INTC,
++ IRQ_FSG_PCI_INTB,
++ IRQ_FSG_PCI_INTA,
++ };
++
++ int irq = -1;
++ slot = slot - 11;
++
++ if (slot >= 1 && slot <= FSG_PCI_MAX_DEV &&
++ pin >= 1 && pin <= FSG_PCI_IRQ_LINES)
++ irq = pci_irq_table[(slot - 1)];
++ printk(KERN_INFO "%s: Mapped slot %d pin %d to IRQ %d\n",
++ __func__, slot, pin, irq);
++
++ return irq;
++}
++
++struct hw_pci fsg_pci __initdata = {
++ .nr_controllers = 1,
++ .preinit = fsg_pci_preinit,
++ .swizzle = pci_std_swizzle,
++ .setup = ixp4xx_setup,
++ .scan = ixp4xx_scan_bus,
++ .map_irq = fsg_map_irq,
++};
++
++int __init fsg_pci_init(void)
++{
++ if (machine_is_fsg())
++ pci_common_init(&fsg_pci);
++ return 0;
++}
++
++subsys_initcall(fsg_pci_init);
+--- /dev/null
++++ b/arch/arm/mach-ixp4xx/fsg-setup.c
+@@ -0,0 +1,276 @@
++/*
++ * arch/arm/mach-ixp4xx/fsg-setup.c
++ *
++ * FSG board-setup
++ *
++ * Copyright (C) 2008 Rod Whitby <rod@whitby.id.au>
++ *
++ * based on ixdp425-setup.c:
++ * Copyright (C) 2003-2004 MontaVista Software, Inc.
++ * based on nslu2-power.c
++ * Copyright (C) 2005 Tower Technologies
++ *
++ * Author: Rod Whitby <rod@whitby.id.au>
++ * Maintainers: http://www.nslu2-linux.org/
++ *
++ */
++
++#include <linux/if_ether.h>
++#include <linux/irq.h>
++#include <linux/serial.h>
++#include <linux/serial_8250.h>
++#include <linux/leds.h>
++#include <linux/reboot.h>
++#include <linux/i2c.h>
++#include <linux/i2c-gpio.h>
++
++#include <asm/mach-types.h>
++#include <asm/mach/arch.h>
++#include <asm/mach/flash.h>
++#include <asm/io.h>
++#include <asm/gpio.h>
++
++static struct flash_platform_data fsg_flash_data = {
++ .map_name = "cfi_probe",
++ .width = 2,
++};
++
++static struct resource fsg_flash_resource = {
++ .flags = IORESOURCE_MEM,
++};
++
++static struct platform_device fsg_flash = {
++ .name = "IXP4XX-Flash",
++ .id = 0,
++ .dev = {
++ .platform_data = &fsg_flash_data,
++ },
++ .num_resources = 1,
++ .resource = &fsg_flash_resource,
++};
++
++static struct i2c_gpio_platform_data fsg_i2c_gpio_data = {
++ .sda_pin = FSG_SDA_PIN,
++ .scl_pin = FSG_SCL_PIN,
++};
++
++static struct platform_device fsg_i2c_gpio = {
++ .name = "i2c-gpio",
++ .id = 0,
++ .dev = {
++ .platform_data = &fsg_i2c_gpio_data,
++ },
++};
++
++static struct i2c_board_info __initdata fsg_i2c_board_info [] = {
++ {
++ I2C_BOARD_INFO("isl1208", 0x6f),
++ },
++};
++
++static struct resource fsg_uart_resources[] = {
++ {
++ .start = IXP4XX_UART1_BASE_PHYS,
++ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .start = IXP4XX_UART2_BASE_PHYS,
++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
++ .flags = IORESOURCE_MEM,
++ }
++};
++
++static struct plat_serial8250_port fsg_uart_data[] = {
++ {
++ .mapbase = IXP4XX_UART1_BASE_PHYS,
++ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
++ .irq = IRQ_IXP4XX_UART1,
++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
++ .iotype = UPIO_MEM,
++ .regshift = 2,
++ .uartclk = IXP4XX_UART_XTAL,
++ },
++ {
++ .mapbase = IXP4XX_UART2_BASE_PHYS,
++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
++ .irq = IRQ_IXP4XX_UART2,
++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
++ .iotype = UPIO_MEM,
++ .regshift = 2,
++ .uartclk = IXP4XX_UART_XTAL,
++ },
++ { }
++};
++
++static struct platform_device fsg_uart = {
++ .name = "serial8250",
++ .id = PLAT8250_DEV_PLATFORM,
++ .dev = {
++ .platform_data = fsg_uart_data,
++ },
++ .num_resources = ARRAY_SIZE(fsg_uart_resources),
++ .resource = fsg_uart_resources,
++};
++
++static struct platform_device fsg_leds = {
++ .name = "fsg-led",
++ .id = -1,
++};
++
++/* Built-in 10/100 Ethernet MAC interfaces */
++static struct eth_plat_info fsg_plat_eth[] = {
++ {
++ .phy = 5,
++ .rxq = 3,
++ .txreadyq = 20,
++ }, {
++ .phy = 4,
++ .rxq = 4,
++ .txreadyq = 21,
++ }
++};
++
++static struct platform_device fsg_eth[] = {
++ {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEB,
++ .dev = {
++ .platform_data = fsg_plat_eth,
++ },
++ }, {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEC,
++ .dev = {
++ .platform_data = fsg_plat_eth + 1,
++ },
++ }
++};
++
++static struct platform_device *fsg_devices[] __initdata = {
++ &fsg_i2c_gpio,
++ &fsg_flash,
++ &fsg_leds,
++ &fsg_eth[0],
++ &fsg_eth[1],
++};
++
++static irqreturn_t fsg_power_handler(int irq, void *dev_id)
++{
++ /* Signal init to do the ctrlaltdel action, this will bypass init if
++ * it hasn't started and do a kernel_restart.
++ */
++ ctrl_alt_del();
++
++ return IRQ_HANDLED;
++}
++
++static irqreturn_t fsg_reset_handler(int irq, void *dev_id)
++{
++ /* This is the paper-clip reset which does an emergency reboot. */
++ printk(KERN_INFO "Restarting system.\n");
++ machine_restart(NULL);
++
++ /* This should never be reached. */
++ return IRQ_HANDLED;
++}
++
++static void __init fsg_init(void)
++{
++ DECLARE_MAC_BUF(mac_buf);
++ uint8_t __iomem *f;
++ int i;
++
++ ixp4xx_sys_init();
++
++ fsg_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
++ fsg_flash_resource.end =
++ IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
++
++ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
++ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
++
++ /* Configure CS2 for operation, 8bit and writable */
++ *IXP4XX_EXP_CS2 = 0xbfff0002;
++
++ i2c_register_board_info(0, fsg_i2c_board_info,
++ ARRAY_SIZE(fsg_i2c_board_info));
++
++ /* This is only useful on a modified machine, but it is valuable
++ * to have it first in order to see debug messages, and so that
++ * it does *not* get removed if platform_add_devices fails!
++ */
++ (void)platform_device_register(&fsg_uart);
++
++ platform_add_devices(fsg_devices, ARRAY_SIZE(fsg_devices));
++
++ if (request_irq(gpio_to_irq(FSG_RB_GPIO), &fsg_reset_handler,
++ IRQF_DISABLED | IRQF_TRIGGER_LOW,
++ "FSG reset button", NULL) < 0) {
++
++ printk(KERN_DEBUG "Reset Button IRQ %d not available\n",
++ gpio_to_irq(FSG_RB_GPIO));
++ }
++
++ if (request_irq(gpio_to_irq(FSG_SB_GPIO), &fsg_power_handler,
++ IRQF_DISABLED | IRQF_TRIGGER_LOW,
++ "FSG power button", NULL) < 0) {
++
++ printk(KERN_DEBUG "Power Button IRQ %d not available\n",
++ gpio_to_irq(FSG_SB_GPIO));
++ }
++
++ /*
++ * Map in a portion of the flash and read the MAC addresses.
++ * Since it is stored in BE in the flash itself, we need to
++ * byteswap it if we're in LE mode.
++ */
++ f = ioremap(IXP4XX_EXP_BUS_BASE(0), 0x400000);
++ if (f) {
++#ifdef __ARMEB__
++ for (i = 0; i < 6; i++) {
++ fsg_plat_eth[0].hwaddr[i] = readb(f + 0x3C0422 + i);
++ fsg_plat_eth[1].hwaddr[i] = readb(f + 0x3C043B + i);
++ }
++#else
++
++ /*
++ Endian-swapped reads from unaligned addresses are
++ required to extract the two MACs from the big-endian
++ Redboot config area in flash.
++ */
++
++ fsg_plat_eth[0].hwaddr[0] = readb(f + 0x3C0421);
++ fsg_plat_eth[0].hwaddr[1] = readb(f + 0x3C0420);
++ fsg_plat_eth[0].hwaddr[2] = readb(f + 0x3C0427);
++ fsg_plat_eth[0].hwaddr[3] = readb(f + 0x3C0426);
++ fsg_plat_eth[0].hwaddr[4] = readb(f + 0x3C0425);
++ fsg_plat_eth[0].hwaddr[5] = readb(f + 0x3C0424);
++
++ fsg_plat_eth[1].hwaddr[0] = readb(f + 0x3C0439);
++ fsg_plat_eth[1].hwaddr[1] = readb(f + 0x3C043F);
++ fsg_plat_eth[1].hwaddr[2] = readb(f + 0x3C043E);
++ fsg_plat_eth[1].hwaddr[3] = readb(f + 0x3C043D);
++ fsg_plat_eth[1].hwaddr[4] = readb(f + 0x3C043C);
++ fsg_plat_eth[1].hwaddr[5] = readb(f + 0x3C0443);
++#endif
++ iounmap(f);
++ }
++ printk(KERN_INFO "FSG: Using MAC address %s for port 0\n",
++ print_mac(mac_buf, fsg_plat_eth[0].hwaddr));
++ printk(KERN_INFO "FSG: Using MAC address %s for port 1\n",
++ print_mac(mac_buf, fsg_plat_eth[1].hwaddr));
++
++}
++
++MACHINE_START(FSG, "Freecom FSG-3")
++ /* Maintainer: www.nslu2-linux.org */
++ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
++ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
++ .map_io = ixp4xx_map_io,
++ .init_irq = ixp4xx_init_irq,
++ .timer = &ixp4xx_timer,
++ .boot_params = 0x0100,
++ .init_machine = fsg_init,
++MACHINE_END
++
+--- /dev/null
++++ b/include/asm-arm/arch-ixp4xx/fsg.h
+@@ -0,0 +1,50 @@
++/*
++ * include/asm-arm/arch-ixp4xx/fsg.h
++ *
++ * Freecom FSG-3 platform specific definitions
++ *
++ * Author: Rod Whitby <rod@whitby.id.au>
++ * Author: Tomasz Chmielewski <mangoo@wpkg.org>
++ * Maintainers: http://www.nslu2-linux.org
++ *
++ * Based on coyote.h by
++ * Copyright 2004 (c) MontaVista, Software, Inc.
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2. This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++
++#ifndef __ASM_ARCH_HARDWARE_H__
++#error "Do not include this directly, instead #include <asm/hardware.h>"
++#endif
++
++#define FSG_SDA_PIN 12
++#define FSG_SCL_PIN 13
++
++/*
++ * FSG PCI IRQs
++ */
++#define FSG_PCI_MAX_DEV 3
++#define FSG_PCI_IRQ_LINES 3
++
++
++/* PCI controller GPIO to IRQ pin mappings */
++#define FSG_PCI_INTA_PIN 6
++#define FSG_PCI_INTB_PIN 7
++#define FSG_PCI_INTC_PIN 5
++
++/* Buttons */
++
++#define FSG_SB_GPIO 4 /* sync button */
++#define FSG_RB_GPIO 9 /* reset button */
++#define FSG_UB_GPIO 10 /* usb button */
++
++/* LEDs */
++
++#define FSG_LED_WLAN_BIT 0
++#define FSG_LED_WAN_BIT 1
++#define FSG_LED_SATA_BIT 2
++#define FSG_LED_USB_BIT 4
++#define FSG_LED_RING_BIT 5
++#define FSG_LED_SYNC_BIT 7
+--- a/include/asm-arm/arch-ixp4xx/hardware.h
++++ b/include/asm-arm/arch-ixp4xx/hardware.h
+@@ -45,5 +45,6 @@
+ #include "nslu2.h"
+ #include "nas100d.h"
+ #include "dsmg600.h"
++#include "fsg.h"
+
+ #endif /* _ASM_ARCH_HARDWARE_H */
+--- a/include/asm-arm/arch-ixp4xx/irqs.h
++++ b/include/asm-arm/arch-ixp4xx/irqs.h
+@@ -128,4 +128,11 @@
+ #define IRQ_DSMG600_PCI_INTE IRQ_IXP4XX_GPIO7
+ #define IRQ_DSMG600_PCI_INTF IRQ_IXP4XX_GPIO6
+
++/*
++ * Freecom FSG-3 Board IRQs
++ */
++#define IRQ_FSG_PCI_INTA IRQ_IXP4XX_GPIO6
++#define IRQ_FSG_PCI_INTB IRQ_IXP4XX_GPIO7
++#define IRQ_FSG_PCI_INTC IRQ_IXP4XX_GPIO5
++
+ #endif
--- /dev/null
+--- a/drivers/char/random.c
++++ b/drivers/char/random.c
+@@ -258,9 +258,9 @@
+ /*
+ * Configuration information
+ */
+-#define INPUT_POOL_WORDS 128
+-#define OUTPUT_POOL_WORDS 32
+-#define SEC_XFER_SIZE 512
++#define INPUT_POOL_WORDS 256
++#define OUTPUT_POOL_WORDS 64
++#define SEC_XFER_SIZE 1024
+
+ /*
+ * The minimum number of bits of entropy before we wake up a read on
--- /dev/null
+--- a/arch/arm/mach-ixp4xx/gateway7001-setup.c
++++ b/arch/arm/mach-ixp4xx/gateway7001-setup.c
+@@ -76,9 +76,35 @@
+ .resource = &gateway7001_uart_resource,
+ };
+
++static struct eth_plat_info gateway7001_plat_eth[] = {
++ {
++ .phy = 1,
++ .rxq = 3,
++ .txreadyq = 20,
++ }, {
++ .phy = 2,
++ .rxq = 4,
++ .txreadyq = 21,
++ }
++};
++
++static struct platform_device gateway7001_eth[] = {
++ {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEB,
++ .dev.platform_data = gateway7001_plat_eth,
++ }, {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEC,
++ .dev.platform_data = gateway7001_plat_eth + 1,
++ }
++};
++
+ static struct platform_device *gateway7001_devices[] __initdata = {
+ &gateway7001_flash,
+- &gateway7001_uart
++ &gateway7001_uart,
++ &gateway7001_eth[0],
++ &gateway7001_eth[1],
+ };
+
+ static void __init gateway7001_init(void)
+--- a/arch/arm/mach-ixp4xx/wg302v2-setup.c
++++ b/arch/arm/mach-ixp4xx/wg302v2-setup.c
+@@ -77,9 +77,26 @@
+ .resource = &wg302v2_uart_resource,
+ };
+
++static struct eth_plat_info wg302v2_plat_eth[] = {
++ {
++ .phy = 8,
++ .rxq = 3,
++ .txreadyq = 20,
++ }
++};
++
++static struct platform_device wg302v2_eth[] = {
++ {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEB,
++ .dev.platform_data = wg302v2_plat_eth,
++ }
++};
++
+ static struct platform_device *wg302v2_devices[] __initdata = {
+ &wg302v2_flash,
+ &wg302v2_uart,
++ &wg302v2_eth[0],
+ };
+
+ static void __init wg302v2_init(void)
--- /dev/null
+--- a/arch/arm/configs/ixp4xx_defconfig
++++ b/arch/arm/configs/ixp4xx_defconfig
+@@ -155,6 +155,7 @@
+ CONFIG_MACH_LOFT=y
+ CONFIG_ARCH_ADI_COYOTE=y
+ CONFIG_MACH_GATEWAY7001=y
++CONFIG_MACH_WG302V1=y
+ CONFIG_MACH_WG302V2=y
+ CONFIG_ARCH_IXDP425=y
+ CONFIG_MACH_IXDPG425=y
+--- a/arch/arm/mach-ixp4xx/Kconfig
++++ b/arch/arm/mach-ixp4xx/Kconfig
+@@ -49,6 +49,14 @@
+ 7001 Access Point. For more information on this platform,
+ see http://openwrt.org
+
++config MACH_WG302V1
++ bool "Netgear WG302 v1 / WAG302 v1"
++ select PCI
++ help
++ Say 'Y' here if you want your kernel to support Netgear's
++ WG302 v1 or WAG302 v1 Access Points. For more information
++ on this platform, see http://openwrt.org
++
+ config MACH_WG302V2
+ bool "Netgear WG302 v2 / WAG302 v2"
+ select PCI
+--- a/arch/arm/mach-ixp4xx/Makefile
++++ b/arch/arm/mach-ixp4xx/Makefile
+@@ -14,6 +14,7 @@
+ obj-pci-$(CONFIG_MACH_NAS100D) += nas100d-pci.o
+ obj-pci-$(CONFIG_MACH_DSMG600) += dsmg600-pci.o
+ obj-pci-$(CONFIG_MACH_GATEWAY7001) += gateway7001-pci.o
++obj-pci-$(CONFIG_MACH_WG302V1) += wg302v1-pci.o
+ obj-pci-$(CONFIG_MACH_WG302V2) += wg302v2-pci.o
+ obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o
+
+@@ -28,6 +29,7 @@
+ obj-$(CONFIG_MACH_NAS100D) += nas100d-setup.o
+ obj-$(CONFIG_MACH_DSMG600) += dsmg600-setup.o
+ obj-$(CONFIG_MACH_GATEWAY7001) += gateway7001-setup.o
++obj-$(CONFIG_MACH_WG302V1) += wg302v1-setup.o
+ obj-$(CONFIG_MACH_WG302V2) += wg302v2-setup.o
+ obj-$(CONFIG_MACH_FSG) += fsg-setup.o
+
+--- /dev/null
++++ b/arch/arm/mach-ixp4xx/wg302v1-pci.c
+@@ -0,0 +1,64 @@
++/*
++ * arch/arch/mach-ixp4xx/wg302v1-pci.c
++ *
++ * PCI setup routines for the Netgear WG302 v1 and WAG302 v1
++ *
++ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
++ *
++ * based on coyote-pci.c:
++ * Copyright (C) 2002 Jungo Software Technologies.
++ * Copyright (C) 2003 MontaVista Software, Inc.
++ *
++ * Maintainer: Imre Kaloz <kaloz@openwrt.org>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include <linux/kernel.h>
++#include <linux/pci.h>
++#include <linux/init.h>
++#include <linux/irq.h>
++
++#include <asm/mach-types.h>
++#include <asm/hardware.h>
++
++#include <asm/mach/pci.h>
++
++void __init wg302v1_pci_preinit(void)
++{
++ set_irq_type(IRQ_IXP4XX_GPIO8, IRQT_LOW);
++ set_irq_type(IRQ_IXP4XX_GPIO10, IRQT_LOW);
++
++ ixp4xx_pci_preinit();
++}
++
++static int __init wg302v1_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
++{
++ if (slot == 1)
++ return IRQ_IXP4XX_GPIO8;
++ else if (slot == 2)
++ return IRQ_IXP4XX_GPIO10;
++ else
++ return -1;
++}
++
++struct hw_pci wg302v1_pci __initdata = {
++ .nr_controllers = 1,
++ .preinit = wg302v1_pci_preinit,
++ .swizzle = pci_std_swizzle,
++ .setup = ixp4xx_setup,
++ .scan = ixp4xx_scan_bus,
++ .map_irq = wg302v1_map_irq,
++};
++
++int __init wg302v1_pci_init(void)
++{
++ if (machine_is_wg302v1())
++ pci_common_init(&wg302v1_pci);
++ return 0;
++}
++
++subsys_initcall(wg302v1_pci_init);
+--- /dev/null
++++ b/arch/arm/mach-ixp4xx/wg302v1-setup.c
+@@ -0,0 +1,142 @@
++/*
++ * arch/arm/mach-ixp4xx/wg302v1-setup.c
++ *
++ * Board setup for the Netgear WG302 v1 and WAG302 v1
++ *
++ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
++ *
++ * based on coyote-setup.c:
++ * Copyright (C) 2003-2005 MontaVista Software, Inc.
++ *
++ * Author: Imre Kaloz <kaloz@openwrt.org>
++ *
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/device.h>
++#include <linux/serial.h>
++#include <linux/tty.h>
++#include <linux/serial_8250.h>
++#include <linux/slab.h>
++#include <linux/types.h>
++#include <linux/memory.h>
++
++#include <asm/setup.h>
++#include <asm/hardware.h>
++#include <asm/irq.h>
++#include <asm/mach-types.h>
++#include <asm/mach/arch.h>
++#include <asm/mach/flash.h>
++
++static struct flash_platform_data wg302v1_flash_data = {
++ .map_name = "cfi_probe",
++ .width = 2,
++};
++
++static struct resource wg302v1_flash_resource = {
++ .flags = IORESOURCE_MEM,
++};
++
++static struct platform_device wg302v1_flash = {
++ .name = "IXP4XX-Flash",
++ .id = 0,
++ .dev = {
++ .platform_data = &wg302v1_flash_data,
++ },
++ .num_resources = 1,
++ .resource = &wg302v1_flash_resource,
++};
++
++static struct resource wg302v1_uart_resources[] = {
++ {
++ .start = IXP4XX_UART1_BASE_PHYS,
++ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .start = IXP4XX_UART2_BASE_PHYS,
++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
++ .flags = IORESOURCE_MEM,
++ }
++};
++
++static struct plat_serial8250_port wg302v1_uart_data[] = {
++ {
++ .mapbase = IXP4XX_UART1_BASE_PHYS,
++ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
++ .irq = IRQ_IXP4XX_UART1,
++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
++ .iotype = UPIO_MEM,
++ .regshift = 2,
++ .uartclk = IXP4XX_UART_XTAL,
++ },
++ {
++ .mapbase = IXP4XX_UART2_BASE_PHYS,
++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
++ .irq = IRQ_IXP4XX_UART2,
++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
++ .iotype = UPIO_MEM,
++ .regshift = 2,
++ .uartclk = IXP4XX_UART_XTAL,
++ },
++ { },
++};
++
++static struct platform_device wg302v1_uart = {
++ .name = "serial8250",
++ .id = PLAT8250_DEV_PLATFORM,
++ .dev = {
++ .platform_data = wg302v1_uart_data,
++ },
++ .num_resources = 2,
++ .resource = wg302v1_uart_resources,
++};
++
++static struct eth_plat_info wg302v1_plat_eth[] = {
++ {
++ .phy = 30,
++ .rxq = 3,
++ .txreadyq = 20,
++ }
++};
++
++static struct platform_device wg302v1_eth[] = {
++ {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEB,
++ .dev.platform_data = wg302v1_plat_eth,
++ }
++};
++
++static struct platform_device *wg302v1_devices[] __initdata = {
++ &wg302v1_flash,
++ &wg302v1_uart,
++ &wg302v1_eth[0],
++};
++
++static void __init wg302v1_init(void)
++{
++ ixp4xx_sys_init();
++
++ wg302v1_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
++ wg302v1_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
++
++ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
++ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
++
++ platform_add_devices(wg302v1_devices, ARRAY_SIZE(wg302v1_devices));
++}
++
++#ifdef CONFIG_MACH_WG302V1
++MACHINE_START(WG302V1, "Netgear WG302 v1 / WAG302 v1")
++ /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
++ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
++ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
++ .map_io = ixp4xx_map_io,
++ .init_irq = ixp4xx_init_irq,
++ .timer = &ixp4xx_timer,
++ .boot_params = 0x0100,
++ .init_machine = wg302v1_init,
++MACHINE_END
++#endif
--- /dev/null
+--- a/arch/arm/configs/ixp4xx_defconfig
++++ b/arch/arm/configs/ixp4xx_defconfig
+@@ -157,6 +157,8 @@
+ CONFIG_MACH_GATEWAY7001=y
+ CONFIG_MACH_WG302V1=y
+ CONFIG_MACH_WG302V2=y
++CONFIG_MACH_PRONGHORN=y
++CONFIG_MACH_PRONGHORNMETRO=y
+ CONFIG_ARCH_IXDP425=y
+ CONFIG_MACH_IXDPG425=y
+ CONFIG_MACH_IXDP465=y
+--- a/arch/arm/mach-ixp4xx/Kconfig
++++ b/arch/arm/mach-ixp4xx/Kconfig
+@@ -65,6 +65,22 @@
+ WG302 v2 or WAG302 v2 Access Points. For more information
+ on this platform, see http://openwrt.org
+
++config MACH_PRONGHORN
++ bool "ADI Pronghorn series"
++ select PCI
++ help
++ Say 'Y' here if you want your kernel to support the ADI
++ Engineering Pronghorn series. For more
++ information on this platform, see http://www.adiengineering.com
++
++#
++# There're only minimal differences kernel-wise between the Pronghorn and
++# Pronghorn Metro boards - they use different chip selects to drive the
++# CF slot connected to the expansion bus, so we just enable them together.
++#
++config MACH_PRONGHORNMETRO
++ def_bool MACH_PRONGHORN
++
+ config ARCH_IXDP425
+ bool "IXDP425"
+ help
+--- a/arch/arm/mach-ixp4xx/Makefile
++++ b/arch/arm/mach-ixp4xx/Makefile
+@@ -17,6 +17,7 @@
+ obj-pci-$(CONFIG_MACH_WG302V1) += wg302v1-pci.o
+ obj-pci-$(CONFIG_MACH_WG302V2) += wg302v2-pci.o
+ obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o
++obj-pci-$(CONFIG_MACH_PRONGHORN) += pronghorn-pci.o
+
+ obj-y += common.o
+
+@@ -32,6 +33,7 @@
+ obj-$(CONFIG_MACH_WG302V1) += wg302v1-setup.o
+ obj-$(CONFIG_MACH_WG302V2) += wg302v2-setup.o
+ obj-$(CONFIG_MACH_FSG) += fsg-setup.o
++obj-$(CONFIG_MACH_PRONGHORN) += pronghorn-setup.o
+
+ obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
+ obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o
+--- /dev/null
++++ b/arch/arm/mach-ixp4xx/pronghorn-pci.c
+@@ -0,0 +1,70 @@
++/*
++ * arch/arch/mach-ixp4xx/pronghorn-pci.c
++ *
++ * PCI setup routines for ADI Engineering Pronghorn series
++ *
++ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
++ *
++ * based on coyote-pci.c:
++ * Copyright (C) 2002 Jungo Software Technologies.
++ * Copyright (C) 2003 MontaVista Softwrae, Inc.
++ *
++ * Maintainer: Imre Kaloz <kaloz@openwrt.org>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include <linux/kernel.h>
++#include <linux/pci.h>
++#include <linux/init.h>
++#include <linux/irq.h>
++
++#include <asm/mach-types.h>
++#include <asm/hardware.h>
++
++#include <asm/mach/pci.h>
++
++void __init pronghorn_pci_preinit(void)
++{
++ set_irq_type(IRQ_IXP4XX_GPIO4, IRQT_LOW);
++ set_irq_type(IRQ_IXP4XX_GPIO6, IRQT_LOW);
++ set_irq_type(IRQ_IXP4XX_GPIO11, IRQT_LOW);
++ set_irq_type(IRQ_IXP4XX_GPIO1, IRQT_LOW);
++
++ ixp4xx_pci_preinit();
++}
++
++static int __init pronghorn_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
++{
++ if (slot == 13)
++ return IRQ_IXP4XX_GPIO4;
++ else if (slot == 14)
++ return IRQ_IXP4XX_GPIO6;
++ else if (slot == 15)
++ return IRQ_IXP4XX_GPIO11;
++ else if (slot == 16)
++ return IRQ_IXP4XX_GPIO1;
++ else
++ return -1;
++}
++
++struct hw_pci pronghorn_pci __initdata = {
++ .nr_controllers = 1,
++ .preinit = pronghorn_pci_preinit,
++ .swizzle = pci_std_swizzle,
++ .setup = ixp4xx_setup,
++ .scan = ixp4xx_scan_bus,
++ .map_irq = pronghorn_map_irq,
++};
++
++int __init pronghorn_pci_init(void)
++{
++ if (machine_is_pronghorn() || machine_is_pronghorn_metro())
++ pci_common_init(&pronghorn_pci);
++ return 0;
++}
++
++subsys_initcall(pronghorn_pci_init);
+--- /dev/null
++++ b/arch/arm/mach-ixp4xx/pronghorn-setup.c
+@@ -0,0 +1,245 @@
++/*
++ * arch/arm/mach-ixp4xx/pronghorn-setup.c
++ *
++ * Board setup for the ADI Engineering Pronghorn series
++ *
++ * Copyright (C) 2008 Imre Kaloz <Kaloz@openwrt.org>
++ *
++ * based on coyote-setup.c:
++ * Copyright (C) 2003-2005 MontaVista Software, Inc.
++ *
++ * Author: Imre Kaloz <Kaloz@openwrt.org>
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/device.h>
++#include <linux/serial.h>
++#include <linux/tty.h>
++#include <linux/serial_8250.h>
++#include <linux/slab.h>
++#include <linux/types.h>
++#include <linux/memory.h>
++#include <linux/i2c-gpio.h>
++#include <linux/leds.h>
++
++#include <asm/setup.h>
++#include <asm/hardware.h>
++#include <asm/irq.h>
++#include <asm/mach-types.h>
++#include <asm/mach/arch.h>
++#include <asm/mach/flash.h>
++
++static struct flash_platform_data pronghorn_flash_data = {
++ .map_name = "cfi_probe",
++ .width = 2,
++};
++
++static struct resource pronghorn_flash_resource = {
++ .flags = IORESOURCE_MEM,
++};
++
++static struct platform_device pronghorn_flash = {
++ .name = "IXP4XX-Flash",
++ .id = 0,
++ .dev = {
++ .platform_data = &pronghorn_flash_data,
++ },
++ .num_resources = 1,
++ .resource = &pronghorn_flash_resource,
++};
++
++static struct resource pronghorn_uart_resources [] = {
++ {
++ .start = IXP4XX_UART1_BASE_PHYS,
++ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
++ .flags = IORESOURCE_MEM
++ },
++ {
++ .start = IXP4XX_UART2_BASE_PHYS,
++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
++ .flags = IORESOURCE_MEM
++ }
++};
++
++static struct plat_serial8250_port pronghorn_uart_data[] = {
++ {
++ .mapbase = IXP4XX_UART1_BASE_PHYS,
++ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
++ .irq = IRQ_IXP4XX_UART1,
++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
++ .iotype = UPIO_MEM,
++ .regshift = 2,
++ .uartclk = IXP4XX_UART_XTAL,
++ },
++ {
++ .mapbase = IXP4XX_UART2_BASE_PHYS,
++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
++ .irq = IRQ_IXP4XX_UART2,
++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
++ .iotype = UPIO_MEM,
++ .regshift = 2,
++ .uartclk = IXP4XX_UART_XTAL,
++ },
++ { },
++};
++
++static struct platform_device pronghorn_uart = {
++ .name = "serial8250",
++ .id = PLAT8250_DEV_PLATFORM,
++ .dev = {
++ .platform_data = pronghorn_uart_data,
++ },
++ .num_resources = 2,
++ .resource = pronghorn_uart_resources,
++};
++
++static struct i2c_gpio_platform_data pronghorn_i2c_gpio_data = {
++ .sda_pin = 9,
++ .scl_pin = 10,
++};
++
++static struct platform_device pronghorn_i2c_gpio = {
++ .name = "i2c-gpio",
++ .id = 0,
++ .dev = {
++ .platform_data = &pronghorn_i2c_gpio_data,
++ },
++};
++
++static struct gpio_led pronghorn_led_pin[] = {
++ {
++ .name = "pronghorn:green:status",
++ .gpio = 7,
++ }
++};
++
++static struct gpio_led_platform_data pronghorn_led_data = {
++ .num_leds = 1,
++ .leds = pronghorn_led_pin,
++};
++
++static struct platform_device pronghorn_led = {
++ .name = "leds-gpio",
++ .id = -1,
++ .dev.platform_data = &pronghorn_led_data,
++};
++
++static struct resource pronghorn_pata_resources[] = {
++ {
++ .flags = IORESOURCE_MEM
++ },
++ {
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "intrq",
++ .start = IRQ_IXP4XX_GPIO0,
++ .end = IRQ_IXP4XX_GPIO0,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct ixp4xx_pata_data pronghorn_pata_data = {
++ .cs0_bits = 0xbfff0043,
++ .cs1_bits = 0xbfff0043,
++};
++
++static struct platform_device pronghorn_pata = {
++ .name = "pata_ixp4xx_cf",
++ .id = 0,
++ .dev.platform_data = &pronghorn_pata_data,
++ .num_resources = ARRAY_SIZE(pronghorn_pata_resources),
++ .resource = pronghorn_pata_resources,
++};
++
++static struct eth_plat_info pronghorn_plat_eth[] = {
++ {
++ .phy = 0,
++ .rxq = 3,
++ .txreadyq = 20,
++ }, {
++ .phy = 1,
++ .rxq = 4,
++ .txreadyq = 21,
++ }
++};
++
++static struct platform_device pronghorn_eth[] = {
++ {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEB,
++ .dev.platform_data = pronghorn_plat_eth,
++ }, {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEC,
++ .dev.platform_data = pronghorn_plat_eth + 1,
++ }
++};
++
++static struct platform_device *pronghorn_devices[] __initdata = {
++ &pronghorn_flash,
++ &pronghorn_uart,
++ &pronghorn_led,
++ &pronghorn_eth[0],
++ &pronghorn_eth[1],
++};
++
++static void __init pronghorn_init(void)
++{
++ ixp4xx_sys_init();
++
++ pronghorn_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
++ pronghorn_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
++
++ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
++ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
++
++ platform_add_devices(pronghorn_devices, ARRAY_SIZE(pronghorn_devices));
++
++ if (machine_is_pronghorn()) {
++ pronghorn_pata_resources[0].start = IXP4XX_EXP_BUS_BASE(2);
++ pronghorn_pata_resources[0].end = IXP4XX_EXP_BUS_END(2);
++
++ pronghorn_pata_resources[1].start = IXP4XX_EXP_BUS_BASE(3);
++ pronghorn_pata_resources[1].end = IXP4XX_EXP_BUS_END(3);
++
++ pronghorn_pata_data.cs0_cfg = IXP4XX_EXP_CS2;
++ pronghorn_pata_data.cs1_cfg = IXP4XX_EXP_CS3;
++ } else {
++ pronghorn_pata_resources[0].start = IXP4XX_EXP_BUS_BASE(3);
++ pronghorn_pata_resources[0].end = IXP4XX_EXP_BUS_END(3);
++
++ pronghorn_pata_resources[1].start = IXP4XX_EXP_BUS_BASE(4);
++ pronghorn_pata_resources[1].end = IXP4XX_EXP_BUS_END(4);
++
++ pronghorn_pata_data.cs0_cfg = IXP4XX_EXP_CS3;
++ pronghorn_pata_data.cs1_cfg = IXP4XX_EXP_CS4;
++
++ platform_device_register(&pronghorn_i2c_gpio);
++ }
++
++ platform_device_register(&pronghorn_pata);
++}
++
++MACHINE_START(PRONGHORN, "ADI Engineering Pronghorn")
++ /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
++ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
++ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
++ .map_io = ixp4xx_map_io,
++ .init_irq = ixp4xx_init_irq,
++ .timer = &ixp4xx_timer,
++ .boot_params = 0x0100,
++ .init_machine = pronghorn_init,
++MACHINE_END
++
++MACHINE_START(PRONGHORNMETRO, "ADI Engineering Pronghorn Metro")
++ /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
++ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
++ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
++ .map_io = ixp4xx_map_io,
++ .init_irq = ixp4xx_init_irq,
++ .timer = &ixp4xx_timer,
++ .boot_params = 0x0100,
++ .init_machine = pronghorn_init,
++MACHINE_END
+--- a/include/asm-arm/arch-ixp4xx/uncompress.h
++++ b/include/asm-arm/arch-ixp4xx/uncompress.h
+@@ -41,7 +41,8 @@
+ * Some boards are using UART2 as console
+ */
+ if (machine_is_adi_coyote() || machine_is_gtwx5715() ||
+- machine_is_gateway7001() || machine_is_wg302v2())
++ machine_is_gateway7001() || machine_is_wg302v2() ||
++ machine_is_pronghorn() || machine_is_pronghorn_metro())
+ uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS;
+ else
+ uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS;
--- /dev/null
+--- a/arch/arm/mach-ixp4xx/pronghorn-setup.c
++++ b/arch/arm/mach-ixp4xx/pronghorn-setup.c
+@@ -51,31 +51,31 @@
+
+ static struct resource pronghorn_uart_resources [] = {
+ {
+- .start = IXP4XX_UART1_BASE_PHYS,
+- .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
++ .start = IXP4XX_UART2_BASE_PHYS,
++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
+ .flags = IORESOURCE_MEM
+ },
+ {
+- .start = IXP4XX_UART2_BASE_PHYS,
+- .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
++ .start = IXP4XX_UART1_BASE_PHYS,
++ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
+ .flags = IORESOURCE_MEM
+ }
+ };
+
+ static struct plat_serial8250_port pronghorn_uart_data[] = {
+ {
+- .mapbase = IXP4XX_UART1_BASE_PHYS,
+- .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
+- .irq = IRQ_IXP4XX_UART1,
++ .mapbase = IXP4XX_UART2_BASE_PHYS,
++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
++ .irq = IRQ_IXP4XX_UART2,
+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+ .iotype = UPIO_MEM,
+ .regshift = 2,
+ .uartclk = IXP4XX_UART_XTAL,
+ },
+ {
+- .mapbase = IXP4XX_UART2_BASE_PHYS,
+- .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
+- .irq = IRQ_IXP4XX_UART2,
++ .mapbase = IXP4XX_UART1_BASE_PHYS,
++ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
++ .irq = IRQ_IXP4XX_UART1,
+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+ .iotype = UPIO_MEM,
+ .regshift = 2,
--- /dev/null
+From 60bdaaaf3446b4237566c6e04855186fc7bd766b Mon Sep 17 00:00:00 2001
+From: Imre Kaloz <kaloz@openwrt.org>
+Date: Sun, 13 Jul 2008 22:46:45 +0200
+Subject: [PATCH] Add support for the ADI Sidewinder
+
+Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
+---
+ arch/arm/mach-ixp4xx/Kconfig | 10 ++-
+ arch/arm/mach-ixp4xx/Makefile | 2 +
+ arch/arm/mach-ixp4xx/sidewinder-pci.c | 68 ++++++++++++++
+ arch/arm/mach-ixp4xx/sidewinder-setup.c | 151 +++++++++++++++++++++++++++++++
+ 4 files changed, 230 insertions(+), 1 deletions(-)
+ create mode 100644 arch/arm/mach-ixp4xx/sidewinder-pci.c
+ create mode 100644 arch/arm/mach-ixp4xx/sidewinder-setup.c
+
+--- a/arch/arm/mach-ixp4xx/Kconfig
++++ b/arch/arm/mach-ixp4xx/Kconfig
+@@ -81,6 +81,14 @@
+ config MACH_PRONGHORNMETRO
+ def_bool MACH_PRONGHORN
+
++config MACH_SIDEWINDER
++ bool "ADI Sidewinder"
++ select PCI
++ help
++ Say 'Y' here if you want your kernel to support the ADI
++ Engineering Sidewinder board. For more information on this
++ platform, see http://www.adiengineering.com
++
+ config ARCH_IXDP425
+ bool "IXDP425"
+ help
+@@ -163,7 +171,7 @@
+ #
+ config CPU_IXP46X
+ bool
+- depends on MACH_IXDP465
++ depends on MACH_IXDP465 || MACH_SIDEWINDER
+ default y
+
+ config CPU_IXP43X
+--- a/arch/arm/mach-ixp4xx/Makefile
++++ b/arch/arm/mach-ixp4xx/Makefile
+@@ -18,6 +18,7 @@
+ obj-pci-$(CONFIG_MACH_WG302V2) += wg302v2-pci.o
+ obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o
+ obj-pci-$(CONFIG_MACH_PRONGHORN) += pronghorn-pci.o
++obj-pci-$(CONFIG_MACH_SIDEWINDER) += sidewinder-pci.o
+
+ obj-y += common.o
+
+@@ -34,6 +35,7 @@
+ obj-$(CONFIG_MACH_WG302V2) += wg302v2-setup.o
+ obj-$(CONFIG_MACH_FSG) += fsg-setup.o
+ obj-$(CONFIG_MACH_PRONGHORN) += pronghorn-setup.o
++obj-$(CONFIG_MACH_SIDEWINDER) += sidewinder-setup.o
+
+ obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
+ obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o
+--- /dev/null
++++ b/arch/arm/mach-ixp4xx/sidewinder-pci.c
+@@ -0,0 +1,68 @@
++/*
++ * arch/arch/mach-ixp4xx/pronghornmetro-pci.c
++ *
++ * PCI setup routines for ADI Engineering Sidewinder
++ *
++ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
++ *
++ * based on coyote-pci.c:
++ * Copyright (C) 2002 Jungo Software Technologies.
++ * Copyright (C) 2003 MontaVista Softwrae, Inc.
++ *
++ * Maintainer: Imre Kaloz <kaloz@openwrt.org>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include <linux/kernel.h>
++#include <linux/pci.h>
++#include <linux/init.h>
++#include <linux/irq.h>
++
++#include <asm/mach-types.h>
++#include <asm/hardware.h>
++#include <asm/irq.h>
++
++#include <asm/mach/pci.h>
++
++void __init sidewinder_pci_preinit(void)
++{
++ set_irq_type(IRQ_IXP4XX_GPIO11, IRQT_LOW);
++ set_irq_type(IRQ_IXP4XX_GPIO10, IRQT_LOW);
++ set_irq_type(IRQ_IXP4XX_GPIO9, IRQT_LOW);
++
++ ixp4xx_pci_preinit();
++}
++
++static int __init sidewinder_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
++{
++ if (slot == 1)
++ return IRQ_IXP4XX_GPIO11;
++ else if (slot == 2)
++ return IRQ_IXP4XX_GPIO10;
++ else if (slot == 3)
++ return IRQ_IXP4XX_GPIO9;
++ else
++ return -1;
++}
++
++struct hw_pci sidewinder_pci __initdata = {
++ .nr_controllers = 1,
++ .preinit = sidewinder_pci_preinit,
++ .swizzle = pci_std_swizzle,
++ .setup = ixp4xx_setup,
++ .scan = ixp4xx_scan_bus,
++ .map_irq = sidewinder_map_irq,
++};
++
++int __init sidewinder_pci_init(void)
++{
++ if (machine_is_sidewinder())
++ pci_common_init(&sidewinder_pci);
++ return 0;
++}
++
++subsys_initcall(sidewinder_pci_init);
+--- /dev/null
++++ b/arch/arm/mach-ixp4xx/sidewinder-setup.c
+@@ -0,0 +1,149 @@
++/*
++ * arch/arm/mach-ixp4xx/sidewinder-setup.c
++ *
++ * Board setup for the ADI Engineering Sidewinder
++ *
++ * Copyright (C) 2008 Imre Kaloz <Kaloz@openwrt.org>
++ *
++ * based on coyote-setup.c:
++ * Copyright (C) 2003-2005 MontaVista Software, Inc.
++ *
++ * Author: Imre Kaloz <Kaloz@openwrt.org>
++ */
++
++#include <linux/kernel.h>
++#include <linux/serial.h>
++#include <linux/serial_8250.h>
++
++#include <asm/mach-types.h>
++#include <asm/mach/arch.h>
++#include <asm/mach/flash.h>
++
++static struct flash_platform_data sidewinder_flash_data = {
++ .map_name = "cfi_probe",
++ .width = 2,
++};
++
++static struct resource sidewinder_flash_resource = {
++ .flags = IORESOURCE_MEM,
++};
++
++static struct platform_device sidewinder_flash = {
++ .name = "IXP4XX-Flash",
++ .id = 0,
++ .dev = {
++ .platform_data = &sidewinder_flash_data,
++ },
++ .num_resources = 1,
++ .resource = &sidewinder_flash_resource,
++};
++
++static struct resource sidewinder_uart_resources[] = {
++ {
++ .start = IXP4XX_UART1_BASE_PHYS,
++ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .start = IXP4XX_UART2_BASE_PHYS,
++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
++ .flags = IORESOURCE_MEM,
++ }
++};
++
++static struct plat_serial8250_port sidewinder_uart_data[] = {
++ {
++ .mapbase = IXP4XX_UART1_BASE_PHYS,
++ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
++ .irq = IRQ_IXP4XX_UART1,
++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
++ .iotype = UPIO_MEM,
++ .regshift = 2,
++ .uartclk = IXP4XX_UART_XTAL,
++ },
++ {
++ .mapbase = IXP4XX_UART2_BASE_PHYS,
++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
++ .irq = IRQ_IXP4XX_UART2,
++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
++ .iotype = UPIO_MEM,
++ .regshift = 2,
++ .uartclk = IXP4XX_UART_XTAL,
++ },
++ { },
++};
++
++static struct platform_device sidewinder_uart = {
++ .name = "serial8250",
++ .id = PLAT8250_DEV_PLATFORM,
++ .dev = {
++ .platform_data = sidewinder_uart_data,
++ },
++ .num_resources = ARRAY_SIZE(sidewinder_uart_resources),
++ .resource = sidewinder_uart_resources,
++};
++
++static struct eth_plat_info sidewinder_plat_eth[] = {
++ {
++ .phy = 5,
++ .rxq = 3,
++ .txreadyq = 20,
++ }, {
++ .phy = IXP4XX_ETH_PHY_MAX_ADDR,
++ .phy_mask = 0x1e,
++ .rxq = 4,
++ .txreadyq = 21,
++ }, {
++ .phy = 31,
++ .rxq = 2,
++ .txreadyq = 19,
++ }
++};
++
++static struct platform_device sidewinder_eth[] = {
++ {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEB,
++ .dev.platform_data = sidewinder_plat_eth,
++ }, {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEC,
++ .dev.platform_data = sidewinder_plat_eth + 1,
++ }, {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEA,
++ .dev.platform_data = sidewinder_plat_eth + 2,
++ }
++};
++
++static struct platform_device *sidewinder_devices[] __initdata = {
++ &sidewinder_flash,
++ &sidewinder_uart,
++ &sidewinder_eth[0],
++ &sidewinder_eth[1],
++ &sidewinder_eth[2],
++};
++
++static void __init sidewinder_init(void)
++{
++ ixp4xx_sys_init();
++
++ sidewinder_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
++ sidewinder_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_64M - 1;
++
++ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
++ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
++
++ platform_add_devices(sidewinder_devices, ARRAY_SIZE(sidewinder_devices));
++}
++
++MACHINE_START(SIDEWINDER, "ADI Engineering Sidewinder")
++ /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
++ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
++ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
++ .map_io = ixp4xx_map_io,
++ .init_irq = ixp4xx_init_irq,
++ .timer = &ixp4xx_timer,
++ .boot_params = 0x0100,
++ .init_machine = sidewinder_init,
++MACHINE_END
--- /dev/null
+--- a/drivers/mtd/redboot.c
++++ b/drivers/mtd/redboot.c
+@@ -15,6 +15,8 @@
+
+ #define BOARD_CONFIG_PART "boardconfig"
+
++#include <asm/mach-types.h>
++
+ struct fis_image_desc {
+ unsigned char name[16]; // Null terminated name
+ uint32_t flash_base; // Address within FLASH of image
+@@ -32,7 +34,8 @@
+ struct fis_list *next;
+ };
+
+-static int directory = CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK;
++int directory = CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK;
++
+ module_param(directory, int, 0);
+
+ static inline int redboot_checksum(struct fis_image_desc *img)
+@@ -61,6 +64,8 @@
+ #ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED
+ static char nullstring[] = "unallocated";
+ #endif
++ if (machine_is_sidewinder())
++ directory = -5;
+
+ if ( directory < 0 ) {
+ offset = master->size + directory * master->erasesize;
--- /dev/null
+From 24025a2dcf1248079dd3019fac6ed955252d277f Mon Sep 17 00:00:00 2001
+From: Imre Kaloz <kaloz@openwrt.org>
+Date: Mon, 14 Jul 2008 21:56:34 +0200
+Subject: [PATCH] Add support for the Compex WP18 / NP18A boards
+
+Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
+---
+ arch/arm/mach-ixp4xx/Kconfig | 8 ++
+ arch/arm/mach-ixp4xx/Makefile | 2 +
+ arch/arm/mach-ixp4xx/compex-setup.c | 136 +++++++++++++++++++++++++++++++++++
+ arch/arm/mach-ixp4xx/ixdp425-pci.c | 3 +-
+ arch/arm/tools/mach-types | 2 +-
+ 5 files changed, 149 insertions(+), 2 deletions(-)
+ create mode 100644 arch/arm/mach-ixp4xx/compex-setup.c
+
+--- a/arch/arm/mach-ixp4xx/Kconfig
++++ b/arch/arm/mach-ixp4xx/Kconfig
+@@ -89,6 +89,14 @@
+ Engineering Sidewinder board. For more information on this
+ platform, see http://www.adiengineering.com
+
++config MACH_COMPEX
++ bool "Compex WP18 / NP18A"
++ select PCI
++ help
++ Say 'Y' here if you want your kernel to support Compex'
++ WP18 or NP18A boards. For more information on this
++ platform, see http://www.compex.com.sg/home/OEM/product_ap.htm
++
+ config ARCH_IXDP425
+ bool "IXDP425"
+ help
+--- a/arch/arm/mach-ixp4xx/Makefile
++++ b/arch/arm/mach-ixp4xx/Makefile
+@@ -19,6 +19,7 @@
+ obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o
+ obj-pci-$(CONFIG_MACH_PRONGHORN) += pronghorn-pci.o
+ obj-pci-$(CONFIG_MACH_SIDEWINDER) += sidewinder-pci.o
++obj-pci-$(CONFIG_MACH_COMPEX) += ixdp425-pci.o
+
+ obj-y += common.o
+
+@@ -36,6 +37,7 @@
+ obj-$(CONFIG_MACH_FSG) += fsg-setup.o
+ obj-$(CONFIG_MACH_PRONGHORN) += pronghorn-setup.o
+ obj-$(CONFIG_MACH_SIDEWINDER) += sidewinder-setup.o
++obj-$(CONFIG_MACH_COMPEX) += compex-setup.o
+
+ obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
+ obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o
+--- /dev/null
++++ b/arch/arm/mach-ixp4xx/compex-setup.c
+@@ -0,0 +1,136 @@
++/*
++ * arch/arm/mach-ixp4xx/compex-setup.c
++ *
++ * Compex WP18 / NP18A board-setup
++ *
++ * Copyright (C) 2008 Imre Kaloz <Kaloz@openwrt.org>
++ *
++ * based on coyote-setup.c:
++ * Copyright (C) 2003-2005 MontaVista Software, Inc.
++ *
++ * Author: Imre Kaloz <Kaloz@openwrt.org>
++ */
++
++#include <linux/kernel.h>
++#include <linux/serial.h>
++#include <linux/serial_8250.h>
++
++#include <asm/mach-types.h>
++#include <asm/mach/arch.h>
++#include <asm/mach/flash.h>
++
++static struct flash_platform_data compex_flash_data = {
++ .map_name = "cfi_probe",
++ .width = 2,
++};
++
++static struct resource compex_flash_resource = {
++ .flags = IORESOURCE_MEM,
++};
++
++static struct platform_device compex_flash = {
++ .name = "IXP4XX-Flash",
++ .id = 0,
++ .dev = {
++ .platform_data = &compex_flash_data,
++ },
++ .num_resources = 1,
++ .resource = &compex_flash_resource,
++};
++
++static struct resource compex_uart_resources[] = {
++ {
++ .start = IXP4XX_UART1_BASE_PHYS,
++ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
++ .flags = IORESOURCE_MEM
++ },
++ {
++ .start = IXP4XX_UART2_BASE_PHYS,
++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
++ .flags = IORESOURCE_MEM
++ }
++};
++
++static struct plat_serial8250_port compex_uart_data[] = {
++ {
++ .mapbase = IXP4XX_UART1_BASE_PHYS,
++ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
++ .irq = IRQ_IXP4XX_UART1,
++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
++ .iotype = UPIO_MEM,
++ .regshift = 2,
++ .uartclk = IXP4XX_UART_XTAL,
++ },
++ {
++ .mapbase = IXP4XX_UART2_BASE_PHYS,
++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
++ .irq = IRQ_IXP4XX_UART2,
++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
++ .iotype = UPIO_MEM,
++ .regshift = 2,
++ .uartclk = IXP4XX_UART_XTAL,
++ },
++ { },
++};
++
++static struct platform_device compex_uart = {
++ .name = "serial8250",
++ .id = PLAT8250_DEV_PLATFORM,
++ .dev.platform_data = compex_uart_data,
++ .num_resources = 2,
++ .resource = compex_uart_resources,
++};
++
++static struct eth_plat_info compex_plat_eth[] = {
++ {
++ .phy = IXP4XX_ETH_PHY_MAX_ADDR,
++ .phy_mask = 0xf0000,
++ .rxq = 3,
++ .txreadyq = 20,
++ }, {
++ .phy = 3,
++ .rxq = 4,
++ .txreadyq = 21,
++ }
++};
++
++static struct platform_device compex_eth[] = {
++ {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEB,
++ .dev.platform_data = compex_plat_eth,
++ }, {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEC,
++ .dev.platform_data = compex_plat_eth + 1,
++ }
++};
++
++static struct platform_device *compex_devices[] __initdata = {
++ &compex_flash,
++ &compex_uart,
++ &compex_eth[0],
++ &compex_eth[1],
++};
++
++static void __init compex_init(void)
++{
++ ixp4xx_sys_init();
++
++ compex_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
++ compex_flash_resource.end =
++ IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
++
++ platform_add_devices(compex_devices, ARRAY_SIZE(compex_devices));
++}
++
++MACHINE_START(COMPEX, "Compex WP18 / NP18A")
++ /* Maintainer: Imre Kaloz <Kaloz@openwrt.org> */
++ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
++ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
++ .map_io = ixp4xx_map_io,
++ .init_irq = ixp4xx_init_irq,
++ .timer = &ixp4xx_timer,
++ .boot_params = 0x0100,
++ .init_machine = compex_init,
++MACHINE_END
+--- a/arch/arm/mach-ixp4xx/ixdp425-pci.c
++++ b/arch/arm/mach-ixp4xx/ixdp425-pci.c
+@@ -66,7 +66,8 @@
+ int __init ixdp425_pci_init(void)
+ {
+ if (machine_is_ixdp425() || machine_is_ixcdp1100() ||
+- machine_is_ixdp465() || machine_is_kixrp435())
++ machine_is_ixdp465() || machine_is_kixrp435() ||
++ machine_is_compex())
+ pci_common_init(&ixdp425_pci);
+ return 0;
+ }
+--- a/arch/arm/tools/mach-types
++++ b/arch/arm/tools/mach-types
+@@ -1276,7 +1276,7 @@
+ smdk6400 MACH_SMDK6400 SMDK6400 1270
+ nokia_n800 MACH_NOKIA_N800 NOKIA_N800 1271
+ greenphone MACH_GREENPHONE GREENPHONE 1272
+-compex42x MACH_COMPEXWP18 COMPEXWP18 1273
++compex MACH_COMPEX COMPEX 1273
+ xmate MACH_XMATE XMATE 1274
+ energizer MACH_ENERGIZER ENERGIZER 1275
+ ime1 MACH_IME1 IME1 1276
--- /dev/null
+--- a/arch/arm/mach-ixp4xx/Kconfig
++++ b/arch/arm/mach-ixp4xx/Kconfig
+@@ -97,6 +97,14 @@
+ WP18 or NP18A boards. For more information on this
+ platform, see http://www.compex.com.sg/home/OEM/product_ap.htm
+
++config MACH_WRT300NV2
++ bool "Linksys WRT300N v2"
++ select PCI
++ help
++ Say 'Y' here if you want your kernel to support Linksys'
++ WRT300N v2 router. For more information on this
++ platform, see http://openwrt.org
++
+ config ARCH_IXDP425
+ bool "IXDP425"
+ help
+--- a/arch/arm/mach-ixp4xx/Makefile
++++ b/arch/arm/mach-ixp4xx/Makefile
+@@ -20,6 +20,7 @@
+ obj-pci-$(CONFIG_MACH_PRONGHORN) += pronghorn-pci.o
+ obj-pci-$(CONFIG_MACH_SIDEWINDER) += sidewinder-pci.o
+ obj-pci-$(CONFIG_MACH_COMPEX) += ixdp425-pci.o
++obj-pci-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-pci.o
+
+ obj-y += common.o
+
+@@ -38,6 +39,7 @@
+ obj-$(CONFIG_MACH_PRONGHORN) += pronghorn-setup.o
+ obj-$(CONFIG_MACH_SIDEWINDER) += sidewinder-setup.o
+ obj-$(CONFIG_MACH_COMPEX) += compex-setup.o
++obj-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-setup.o
+
+ obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
+ obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o
+--- /dev/null
++++ b/arch/arm/mach-ixp4xx/wrt300nv2-pci.c
+@@ -0,0 +1,65 @@
++/*
++ * arch/arch/mach-ixp4xx/wrt300nv2-pci.c
++ *
++ * PCI setup routines for Linksys WRT300N v2
++ *
++ * Copyright (C) 2007 Imre Kaloz <kaloz@openwrt.org>
++ *
++ * based on coyote-pci.c:
++ * Copyright (C) 2002 Jungo Software Technologies.
++ * Copyright (C) 2003 MontaVista Softwrae, Inc.
++ *
++ * Maintainer: Imre Kaloz <kaloz@openwrt.org>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include <linux/kernel.h>
++#include <linux/pci.h>
++#include <linux/init.h>
++#include <linux/irq.h>
++
++#include <asm/mach-types.h>
++#include <asm/hardware.h>
++#include <asm/irq.h>
++
++#include <asm/mach/pci.h>
++
++extern void ixp4xx_pci_preinit(void);
++extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
++extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
++
++void __init wrt300nv2_pci_preinit(void)
++{
++ set_irq_type(IRQ_IXP4XX_GPIO8, IRQT_LOW);
++
++ ixp4xx_pci_preinit();
++}
++
++static int __init wrt300nv2_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
++{
++ if (slot == 1)
++ return IRQ_IXP4XX_GPIO8;
++ else return -1;
++}
++
++struct hw_pci wrt300nv2_pci __initdata = {
++ .nr_controllers = 1,
++ .preinit = wrt300nv2_pci_preinit,
++ .swizzle = pci_std_swizzle,
++ .setup = ixp4xx_setup,
++ .scan = ixp4xx_scan_bus,
++ .map_irq = wrt300nv2_map_irq,
++};
++
++int __init wrt300nv2_pci_init(void)
++{
++ if (machine_is_wrt300nv2())
++ pci_common_init(&wrt300nv2_pci);
++ return 0;
++}
++
++subsys_initcall(wrt300nv2_pci_init);
+--- /dev/null
++++ b/arch/arm/mach-ixp4xx/wrt300nv2-setup.c
+@@ -0,0 +1,108 @@
++/*
++ * arch/arm/mach-ixp4xx/wrt300nv2-setup.c
++ *
++ * Board setup for the Linksys WRT300N v2
++ *
++ * Copyright (C) 2007 Imre Kaloz <Kaloz@openwrt.org>
++ *
++ * based on coyote-setup.c:
++ * Copyright (C) 2003-2005 MontaVista Software, Inc.
++ *
++ * Author: Imre Kaloz <Kaloz@openwrt.org>
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/device.h>
++#include <linux/serial.h>
++#include <linux/tty.h>
++#include <linux/serial_8250.h>
++#include <linux/slab.h>
++
++#include <asm/types.h>
++#include <asm/setup.h>
++#include <asm/memory.h>
++#include <asm/hardware.h>
++#include <asm/irq.h>
++#include <asm/mach-types.h>
++#include <asm/mach/arch.h>
++#include <asm/mach/flash.h>
++
++static struct flash_platform_data wrt300nv2_flash_data = {
++ .map_name = "cfi_probe",
++ .width = 2,
++};
++
++static struct resource wrt300nv2_flash_resource = {
++ .flags = IORESOURCE_MEM,
++};
++
++static struct platform_device wrt300nv2_flash = {
++ .name = "IXP4XX-Flash",
++ .id = 0,
++ .dev = {
++ .platform_data = &wrt300nv2_flash_data,
++ },
++ .num_resources = 1,
++ .resource = &wrt300nv2_flash_resource,
++};
++
++static struct resource wrt300nv2_uart_resource = {
++ .start = IXP4XX_UART2_BASE_PHYS,
++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
++ .flags = IORESOURCE_MEM,
++};
++
++static struct plat_serial8250_port wrt300nv2_uart_data[] = {
++ {
++ .mapbase = IXP4XX_UART2_BASE_PHYS,
++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
++ .irq = IRQ_IXP4XX_UART2,
++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
++ .iotype = UPIO_MEM,
++ .regshift = 2,
++ .uartclk = IXP4XX_UART_XTAL,
++ },
++ { },
++};
++
++static struct platform_device wrt300nv2_uart = {
++ .name = "serial8250",
++ .id = PLAT8250_DEV_PLATFORM,
++ .dev = {
++ .platform_data = wrt300nv2_uart_data,
++ },
++ .num_resources = 1,
++ .resource = &wrt300nv2_uart_resource,
++};
++
++static struct platform_device *wrt300nv2_devices[] __initdata = {
++ &wrt300nv2_flash,
++ &wrt300nv2_uart
++};
++
++static void __init wrt300nv2_init(void)
++{
++ ixp4xx_sys_init();
++
++ wrt300nv2_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
++ wrt300nv2_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
++
++ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
++ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
++
++ platform_add_devices(wrt300nv2_devices, ARRAY_SIZE(wrt300nv2_devices));
++}
++
++#ifdef CONFIG_MACH_WRT300NV2
++MACHINE_START(WRT300NV2, "Linksys WRT300N v2")
++ /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
++ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
++ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
++ .map_io = ixp4xx_map_io,
++ .init_irq = ixp4xx_init_irq,
++ .timer = &ixp4xx_timer,
++ .boot_params = 0x0100,
++ .init_machine = wrt300nv2_init,
++MACHINE_END
++#endif
+--- a/include/asm-arm/arch-ixp4xx/uncompress.h
++++ b/include/asm-arm/arch-ixp4xx/uncompress.h
+@@ -42,7 +42,7 @@
+ */
+ if (machine_is_adi_coyote() || machine_is_gtwx5715() ||
+ machine_is_gateway7001() || machine_is_wg302v2() ||
+- machine_is_pronghorn() || machine_is_pronghorn_metro())
++ machine_is_pronghorn() || machine_is_pronghorn_metro() || machine_is_wrt300nv2())
+ uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS;
+ else
+ uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS;
--- /dev/null
+--- a/arch/arm/mach-ixp4xx/wrt300nv2-setup.c
++++ b/arch/arm/mach-ixp4xx/wrt300nv2-setup.c
+@@ -76,9 +76,36 @@
+ .resource = &wrt300nv2_uart_resource,
+ };
+
++/* Built-in 10/100 Ethernet MAC interfaces */
++static struct eth_plat_info wrt300nv2_plat_eth[] = {
++ {
++ .phy = -1,
++ .rxq = 3,
++ .txreadyq = 20,
++ }, {
++ .phy = 1,
++ .rxq = 4,
++ .txreadyq = 21,
++ }
++};
++
++static struct platform_device wrt300nv2_eth[] = {
++ {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEB,
++ .dev.platform_data = wrt300nv2_plat_eth,
++ }, {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEC,
++ .dev.platform_data = wrt300nv2_plat_eth + 1,
++ }
++};
++
+ static struct platform_device *wrt300nv2_devices[] __initdata = {
+ &wrt300nv2_flash,
+- &wrt300nv2_uart
++ &wrt300nv2_uart,
++ &wrt300nv2_eth[0],
++ &wrt300nv2_eth[1],
+ };
+
+ static void __init wrt300nv2_init(void)
--- /dev/null
+--- /dev/null
++++ b/arch/arm/mach-ixp4xx/ap1000-setup.c
+@@ -0,0 +1,151 @@
++/*
++ * arch/arm/mach-ixp4xx/ap1000-setup.c
++ *
++ * Lanready AP-1000
++ *
++ * Copyright (C) 2007 Imre Kaloz <Kaloz@openwrt.org>
++ *
++ * based on ixdp425-setup.c:
++ * Copyright (C) 2003-2005 MontaVista Software, Inc.
++ *
++ * Author: Imre Kaloz <Kaloz@openwrt.org>
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/device.h>
++#include <linux/serial.h>
++#include <linux/tty.h>
++#include <linux/serial_8250.h>
++#include <linux/slab.h>
++
++#include <asm/types.h>
++#include <asm/setup.h>
++#include <asm/memory.h>
++#include <asm/hardware.h>
++#include <asm/mach-types.h>
++#include <asm/irq.h>
++#include <asm/mach/arch.h>
++#include <asm/mach/flash.h>
++
++static struct flash_platform_data ap1000_flash_data = {
++ .map_name = "cfi_probe",
++ .width = 2,
++};
++
++static struct resource ap1000_flash_resource = {
++ .flags = IORESOURCE_MEM,
++};
++
++static struct platform_device ap1000_flash = {
++ .name = "IXP4XX-Flash",
++ .id = 0,
++ .dev = {
++ .platform_data = &ap1000_flash_data,
++ },
++ .num_resources = 1,
++ .resource = &ap1000_flash_resource,
++};
++
++static struct resource ap1000_uart_resources[] = {
++ {
++ .start = IXP4XX_UART1_BASE_PHYS,
++ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
++ .flags = IORESOURCE_MEM
++ },
++ {
++ .start = IXP4XX_UART2_BASE_PHYS,
++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
++ .flags = IORESOURCE_MEM
++ }
++};
++
++static struct plat_serial8250_port ap1000_uart_data[] = {
++ {
++ .mapbase = IXP4XX_UART1_BASE_PHYS,
++ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
++ .irq = IRQ_IXP4XX_UART1,
++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
++ .iotype = UPIO_MEM,
++ .regshift = 2,
++ .uartclk = IXP4XX_UART_XTAL,
++ },
++ {
++ .mapbase = IXP4XX_UART2_BASE_PHYS,
++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
++ .irq = IRQ_IXP4XX_UART2,
++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
++ .iotype = UPIO_MEM,
++ .regshift = 2,
++ .uartclk = IXP4XX_UART_XTAL,
++ },
++ { },
++};
++
++static struct platform_device ap1000_uart = {
++ .name = "serial8250",
++ .id = PLAT8250_DEV_PLATFORM,
++ .dev.platform_data = ap1000_uart_data,
++ .num_resources = 2,
++ .resource = ap1000_uart_resources
++};
++
++static struct platform_device *ap1000_devices[] __initdata = {
++ &ap1000_flash,
++ &ap1000_uart
++};
++
++static char ap1000_mem_fixup[] __initdata = "mem=64M ";
++
++static void __init ap1000_fixup(struct machine_desc *desc,
++ struct tag *tags, char **cmdline, struct meminfo *mi)
++
++{
++ struct tag *t = tags;
++ char *p = *cmdline;
++
++ /* Find the end of the tags table, taking note of any cmdline tag. */
++ for (; t->hdr.size; t = tag_next(t)) {
++ if (t->hdr.tag == ATAG_CMDLINE) {
++ p = t->u.cmdline.cmdline;
++ }
++ }
++
++ /* Overwrite the end of the table with a new cmdline tag. */
++ t->hdr.tag = ATAG_CMDLINE;
++ t->hdr.size = (sizeof (struct tag_header) +
++ strlen(ap1000_mem_fixup) + strlen(p) + 1 + 4) >> 2;
++ strlcpy(t->u.cmdline.cmdline, ap1000_mem_fixup, COMMAND_LINE_SIZE);
++ strlcpy(t->u.cmdline.cmdline + strlen(ap1000_mem_fixup), p,
++ COMMAND_LINE_SIZE - strlen(ap1000_mem_fixup));
++
++ /* Terminate the table. */
++ t = tag_next(t);
++ t->hdr.tag = ATAG_NONE;
++ t->hdr.size = 0;
++}
++
++static void __init ap1000_init(void)
++{
++ ixp4xx_sys_init();
++
++ ap1000_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
++ ap1000_flash_resource.end =
++ IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
++
++ platform_add_devices(ap1000_devices, ARRAY_SIZE(ap1000_devices));
++}
++
++#ifdef CONFIG_MACH_AP1000
++MACHINE_START(AP1000, "Lanready AP-1000")
++ /* Maintainer: Imre Kaloz <Kaloz@openwrt.org> */
++ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
++ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
++ .fixup = ap1000_fixup,
++ .map_io = ixp4xx_map_io,
++ .init_irq = ixp4xx_init_irq,
++ .timer = &ixp4xx_timer,
++ .boot_params = 0x0100,
++ .init_machine = ap1000_init,
++MACHINE_END
++#endif
+--- a/arch/arm/mach-ixp4xx/ixdp425-pci.c
++++ b/arch/arm/mach-ixp4xx/ixdp425-pci.c
+@@ -67,7 +67,7 @@
+ {
+ if (machine_is_ixdp425() || machine_is_ixcdp1100() ||
+ machine_is_ixdp465() || machine_is_kixrp435() ||
+- machine_is_compex())
++ machine_is_compex() || machine_is_ap1000())
+ pci_common_init(&ixdp425_pci);
+ return 0;
+ }
+--- a/arch/arm/mach-ixp4xx/Kconfig
++++ b/arch/arm/mach-ixp4xx/Kconfig
+@@ -105,6 +105,14 @@
+ WRT300N v2 router. For more information on this
+ platform, see http://openwrt.org
+
++config MACH_AP1000
++ bool "Lanready AP-1000"
++ select PCI
++ help
++ Say 'Y' here if you want your kernel to support Lanready's
++ AP1000 board. For more information on this
++ platform, see http://openwrt.org
++
+ config ARCH_IXDP425
+ bool "IXDP425"
+ help
+--- a/arch/arm/mach-ixp4xx/Makefile
++++ b/arch/arm/mach-ixp4xx/Makefile
+@@ -21,6 +21,7 @@
+ obj-pci-$(CONFIG_MACH_SIDEWINDER) += sidewinder-pci.o
+ obj-pci-$(CONFIG_MACH_COMPEX) += ixdp425-pci.o
+ obj-pci-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-pci.o
++obj-pci-$(CONFIG_MACH_AP1000) += ixdp425-pci.o
+
+ obj-y += common.o
+
+@@ -40,6 +41,7 @@
+ obj-$(CONFIG_MACH_SIDEWINDER) += sidewinder-setup.o
+ obj-$(CONFIG_MACH_COMPEX) += compex-setup.o
+ obj-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-setup.o
++obj-$(CONFIG_MACH_AP1000) += ap1000-setup.o
+
+ obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
+ obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o
--- /dev/null
+--- a/arch/arm/mach-ixp4xx/ap1000-setup.c
++++ b/arch/arm/mach-ixp4xx/ap1000-setup.c
+@@ -90,9 +90,37 @@
+ .resource = ap1000_uart_resources
+ };
+
++/* Built-in 10/100 Ethernet MAC interfaces */
++static struct eth_plat_info ap1000_plat_eth[] = {
++ {
++ .phy = IXP4XX_ETH_PHY_MAX_ADDR,
++ .phy_mask = 0x1e,
++ .rxq = 3,
++ .txreadyq = 20,
++ }, {
++ .phy = 5,
++ .rxq = 4,
++ .txreadyq = 21,
++ }
++};
++
++static struct platform_device ap1000_eth[] = {
++ {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEB,
++ .dev.platform_data = ap1000_plat_eth,
++ }, {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEC,
++ .dev.platform_data = ap1000_plat_eth + 1,
++ }
++};
++
+ static struct platform_device *ap1000_devices[] __initdata = {
+ &ap1000_flash,
+- &ap1000_uart
++ &ap1000_uart,
++ &ap1000_eth[0],
++ &ap1000_eth[1],
+ };
+
+ static char ap1000_mem_fixup[] __initdata = "mem=64M ";
--- /dev/null
+--- a/arch/arm/mach-ixp4xx/wg302v1-setup.c
++++ b/arch/arm/mach-ixp4xx/wg302v1-setup.c
+@@ -115,6 +115,36 @@
+ &wg302v1_eth[0],
+ };
+
++static char wg302v1_mem_fixup[] __initdata = "mem=32M ";
++
++static void __init wg302v1_fixup(struct machine_desc *desc,
++ struct tag *tags, char **cmdline, struct meminfo *mi)
++
++{
++ struct tag *t = tags;
++ char *p = *cmdline;
++
++ /* Find the end of the tags table, taking note of any cmdline tag. */
++ for (; t->hdr.size; t = tag_next(t)) {
++ if (t->hdr.tag == ATAG_CMDLINE) {
++ p = t->u.cmdline.cmdline;
++ }
++ }
++
++ /* Overwrite the end of the table with a new cmdline tag. */
++ t->hdr.tag = ATAG_CMDLINE;
++ t->hdr.size = (sizeof (struct tag_header) +
++ strlen(wg302v1_mem_fixup) + strlen(p) + 1 + 4) >> 2;
++ strlcpy(t->u.cmdline.cmdline, wg302v1_mem_fixup, COMMAND_LINE_SIZE);
++ strlcpy(t->u.cmdline.cmdline + strlen(wg302v1_mem_fixup), p,
++ COMMAND_LINE_SIZE - strlen(wg302v1_mem_fixup));
++
++ /* Terminate the table. */
++ t = tag_next(t);
++ t->hdr.tag = ATAG_NONE;
++ t->hdr.size = 0;
++}
++
+ static void __init wg302v1_init(void)
+ {
+ ixp4xx_sys_init();
+@@ -133,6 +163,7 @@
+ /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
+ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
+ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
++ .fixup = wg302v1_fixup,
+ .map_io = ixp4xx_map_io,
+ .init_irq = ixp4xx_init_irq,
+ .timer = &ixp4xx_timer,
--- /dev/null
+--- a/arch/arm/mach-ixp4xx/coyote-setup.c
++++ b/arch/arm/mach-ixp4xx/coyote-setup.c
+@@ -73,9 +73,37 @@
+ .resource = &coyote_uart_resource,
+ };
+
++/* Built-in 10/100 Ethernet MAC interfaces */
++static struct eth_plat_info ixdpg425_plat_eth[] = {
++ {
++ .phy = 5,
++ .rxq = 3,
++ .txreadyq = 20,
++ }, {
++ .phy = 4,
++ .rxq = 4,
++ .txreadyq = 21,
++ }
++};
++
++static struct platform_device ixdpg425_eth[] = {
++ {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEB,
++ .dev.platform_data = ixdpg425_plat_eth,
++ }, {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEC,
++ .dev.platform_data = ixdpg425_plat_eth + 1,
++ }
++};
++
++
+ static struct platform_device *coyote_devices[] __initdata = {
+ &coyote_flash,
+- &coyote_uart
++ &coyote_uart,
++ &ixdpg425_eth[0],
++ &ixdpg425_eth[1],
+ };
+
+ static void __init coyote_init(void)
--- /dev/null
+--- a/arch/arm/mach-ixp4xx/Kconfig
++++ b/arch/arm/mach-ixp4xx/Kconfig
+@@ -158,6 +158,14 @@
+ PrPCM1100 Processor Mezanine Module. For more information on
+ this platform, see <file:Documentation/arm/IXP4xx>.
+
++config MACH_TW5334
++ bool "Titan Wireless TW-533-4"
++ select PCI
++ help
++ Say 'Y' here if you want your kernel to support the Titan
++ Wireless TW533-4. For more information on this platform,
++ see http://openwrt.org
++
+ config MACH_NAS100D
+ bool
+ prompt "NAS100D"
+--- a/arch/arm/mach-ixp4xx/Makefile
++++ b/arch/arm/mach-ixp4xx/Makefile
+@@ -22,6 +22,7 @@
+ obj-pci-$(CONFIG_MACH_COMPEX) += ixdp425-pci.o
+ obj-pci-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-pci.o
+ obj-pci-$(CONFIG_MACH_AP1000) += ixdp425-pci.o
++obj-pci-$(CONFIG_MACH_TW5334) += tw5334-pci.o
+
+ obj-y += common.o
+
+@@ -42,6 +43,7 @@
+ obj-$(CONFIG_MACH_COMPEX) += compex-setup.o
+ obj-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-setup.o
+ obj-$(CONFIG_MACH_AP1000) += ap1000-setup.o
++obj-$(CONFIG_MACH_TW5334) += tw5334-setup.o
+
+ obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
+ obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o
+--- /dev/null
++++ b/arch/arm/mach-ixp4xx/tw5334-setup.c
+@@ -0,0 +1,162 @@
++/*
++ * arch/arm/mach-ixp4xx/tw5334-setup.c
++ *
++ * Board setup for the Titan Wireless TW-533-4
++ *
++ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
++ *
++ * based on coyote-setup.c:
++ * Copyright (C) 2003-2005 MontaVista Software, Inc.
++ *
++ * Author: Imre Kaloz <Kaloz@openwrt.org>
++ */
++
++#include <linux/if_ether.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/device.h>
++#include <linux/serial.h>
++#include <linux/tty.h>
++#include <linux/serial_8250.h>
++#include <linux/slab.h>
++
++#include <asm/types.h>
++#include <asm/setup.h>
++#include <asm/memory.h>
++#include <asm/hardware.h>
++#include <asm/irq.h>
++#include <asm/mach-types.h>
++#include <asm/mach/arch.h>
++#include <asm/mach/flash.h>
++
++static struct flash_platform_data tw5334_flash_data = {
++ .map_name = "cfi_probe",
++ .width = 2,
++};
++
++static struct resource tw5334_flash_resource = {
++ .flags = IORESOURCE_MEM,
++};
++
++static struct platform_device tw5334_flash = {
++ .name = "IXP4XX-Flash",
++ .id = 0,
++ .dev = {
++ .platform_data = &tw5334_flash_data,
++ },
++ .num_resources = 1,
++ .resource = &tw5334_flash_resource,
++};
++
++static struct resource tw5334_uart_resource = {
++ .start = IXP4XX_UART2_BASE_PHYS,
++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
++ .flags = IORESOURCE_MEM,
++};
++
++static struct plat_serial8250_port tw5334_uart_data[] = {
++ {
++ .mapbase = IXP4XX_UART2_BASE_PHYS,
++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
++ .irq = IRQ_IXP4XX_UART2,
++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
++ .iotype = UPIO_MEM,
++ .regshift = 2,
++ .uartclk = IXP4XX_UART_XTAL,
++ },
++ { },
++};
++
++static struct platform_device tw5334_uart = {
++ .name = "serial8250",
++ .id = PLAT8250_DEV_PLATFORM,
++ .dev = {
++ .platform_data = tw5334_uart_data,
++ },
++ .num_resources = 1,
++ .resource = &tw5334_uart_resource,
++};
++
++/* Built-in 10/100 Ethernet MAC interfaces */
++static struct eth_plat_info tw5334_plat_eth[] = {
++ {
++ .phy = 0,
++ .rxq = 3,
++ .txreadyq = 20,
++ }, {
++ .phy = 1,
++ .rxq = 4,
++ .txreadyq = 21,
++ }
++};
++
++static struct platform_device tw5334_eth[] = {
++ {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEB,
++ .dev.platform_data = tw5334_plat_eth,
++ }, {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEC,
++ .dev.platform_data = tw5334_plat_eth + 1,
++ }
++};
++
++static struct platform_device *tw5334_devices[] __initdata = {
++ &tw5334_flash,
++ &tw5334_uart,
++ &tw5334_eth[0],
++ &tw5334_eth[1],
++};
++
++static void __init tw5334_init(void)
++{
++ DECLARE_MAC_BUF(mac_buf);
++ uint8_t __iomem *f;
++ int i;
++
++ ixp4xx_sys_init();
++
++ tw5334_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
++ tw5334_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
++
++ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
++ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
++
++ platform_add_devices(tw5334_devices, ARRAY_SIZE(tw5334_devices));
++
++ /*
++ * Map in a portion of the flash and read the MAC addresses.
++ * Since it is stored in BE in the flash itself, we need to
++ * byteswap it if we're in LE mode.
++ */
++ f = ioremap(IXP4XX_EXP_BUS_BASE(0), 0x1000000);
++ if (f) {
++ for (i = 0; i < 6; i++)
++#ifdef __ARMEB__
++ tw5334_plat_eth[0].hwaddr[i] = readb(f + 0xFC0422 + i);
++ tw5334_plat_eth[1].hwaddr[i] = readb(f + 0xFC043B + i);
++#else
++ tw5334_plat_eth[0].hwaddr[i] = readb(f + 0xFC0422 + (i^3));
++ tw5334_plat_eth[1].hwaddr[i] = readb(f + 0xFC043B + (i^3));
++#endif
++ iounmap(f);
++ }
++ printk(KERN_INFO "TW-533-4: Using MAC address %s for port 0\n",
++ print_mac(mac_buf, tw5334_plat_eth[0].hwaddr));
++ printk(KERN_INFO "TW-533-4: Using MAC address %s for port 1\n",
++ print_mac(mac_buf, tw5334_plat_eth[1].hwaddr));
++}
++
++#ifdef CONFIG_MACH_TW5334
++MACHINE_START(TW5334, "Titan Wireless TW-533-4")
++ /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
++ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
++ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
++ .map_io = ixp4xx_map_io,
++ .init_irq = ixp4xx_init_irq,
++ .timer = &ixp4xx_timer,
++ .boot_params = 0x0100,
++ .init_machine = tw5334_init,
++MACHINE_END
++#endif
+--- /dev/null
++++ b/arch/arm/mach-ixp4xx/tw5334-pci.c
+@@ -0,0 +1,69 @@
++/*
++ * arch/arch/mach-ixp4xx/tw5334-pci.c
++ *
++ * PCI setup routines for the Titan Wireless TW-533-4
++ *
++ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
++ *
++ * based on coyote-pci.c:
++ * Copyright (C) 2002 Jungo Software Technologies.
++ * Copyright (C) 2003 MontaVista Softwrae, Inc.
++ *
++ * Maintainer: Imre Kaloz <kaloz@openwrt.org>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include <linux/kernel.h>
++#include <linux/pci.h>
++#include <linux/init.h>
++#include <linux/irq.h>
++
++#include <asm/mach-types.h>
++#include <asm/hardware.h>
++
++#include <asm/mach/pci.h>
++
++void __init tw5334_pci_preinit(void)
++{
++ set_irq_type(IRQ_IXP4XX_GPIO6, IRQT_LOW);
++ set_irq_type(IRQ_IXP4XX_GPIO2, IRQT_LOW);
++ set_irq_type(IRQ_IXP4XX_GPIO1, IRQT_LOW);
++ set_irq_type(IRQ_IXP4XX_GPIO0, IRQT_LOW);
++
++ ixp4xx_pci_preinit();
++}
++
++static int __init tw5334_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
++{
++ if (slot == 12)
++ return IRQ_IXP4XX_GPIO6;
++ else if (slot == 13)
++ return IRQ_IXP4XX_GPIO2;
++ else if (slot == 14)
++ return IRQ_IXP4XX_GPIO1;
++ else if (slot == 15)
++ return IRQ_IXP4XX_GPIO0;
++ else return -1;
++}
++
++struct hw_pci tw5334_pci __initdata = {
++ .nr_controllers = 1,
++ .preinit = tw5334_pci_preinit,
++ .swizzle = pci_std_swizzle,
++ .setup = ixp4xx_setup,
++ .scan = ixp4xx_scan_bus,
++ .map_irq = tw5334_map_irq,
++};
++
++int __init tw5334_pci_init(void)
++{
++ if (machine_is_tw5334())
++ pci_common_init(&tw5334_pci);
++ return 0;
++}
++
++subsys_initcall(tw5334_pci_init);
+--- a/include/asm-arm/arch-ixp4xx/uncompress.h
++++ b/include/asm-arm/arch-ixp4xx/uncompress.h
+@@ -42,7 +42,8 @@
+ */
+ if (machine_is_adi_coyote() || machine_is_gtwx5715() ||
+ machine_is_gateway7001() || machine_is_wg302v2() ||
+- machine_is_pronghorn() || machine_is_pronghorn_metro() || machine_is_wrt300nv2())
++ machine_is_pronghorn() || machine_is_pronghorn_metro() || machine_is_wrt300nv2() ||
++ machine_is_tw5334())
+ uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS;
+ else
+ uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS;
--- /dev/null
+--- a/arch/arm/mach-ixp4xx/Kconfig
++++ b/arch/arm/mach-ixp4xx/Kconfig
+@@ -25,6 +25,14 @@
+ Avila Network Platform. For more information on this platform,
+ see <file:Documentation/arm/IXP4xx>.
+
++config MACH_CAMBRIA
++ bool "Cambria"
++ select PCI
++ help
++ Say 'Y' here if you want your kernel to support the Gateworks
++ Cambria series. For more information on this platform,
++ see <file:Documentation/arm/IXP4xx>.
++
+ config MACH_LOFT
+ bool "Loft"
+ depends on MACH_AVILA
+@@ -208,7 +216,7 @@
+
+ config CPU_IXP43X
+ bool
+- depends on MACH_KIXRP435
++ depends on MACH_KIXRP435 || MACH_CAMBRIA
+ default y
+
+ config MACH_GTWX5715
+--- a/arch/arm/mach-ixp4xx/Makefile
++++ b/arch/arm/mach-ixp4xx/Makefile
+@@ -7,6 +7,7 @@
+
+ obj-pci-$(CONFIG_ARCH_IXDP4XX) += ixdp425-pci.o
+ obj-pci-$(CONFIG_MACH_AVILA) += avila-pci.o
++obj-pci-$(CONFIG_MACH_CAMBRIA) += cambria-pci.o
+ obj-pci-$(CONFIG_MACH_IXDPG425) += ixdpg425-pci.o
+ obj-pci-$(CONFIG_ARCH_ADI_COYOTE) += coyote-pci.o
+ obj-pci-$(CONFIG_MACH_GTWX5715) += gtwx5715-pci.o
+@@ -28,6 +29,7 @@
+
+ obj-$(CONFIG_ARCH_IXDP4XX) += ixdp425-setup.o
+ obj-$(CONFIG_MACH_AVILA) += avila-setup.o
++obj-$(CONFIG_MACH_CAMBRIA) += cambria-setup.o
+ obj-$(CONFIG_MACH_IXDPG425) += coyote-setup.o
+ obj-$(CONFIG_ARCH_ADI_COYOTE) += coyote-setup.o
+ obj-$(CONFIG_MACH_GTWX5715) += gtwx5715-setup.o
+--- /dev/null
++++ b/arch/arm/mach-ixp4xx/cambria-pci.c
+@@ -0,0 +1,74 @@
++/*
++ * arch/arch/mach-ixp4xx/cambria-pci.c
++ *
++ * PCI setup routines for Gateworks Cambria series
++ *
++ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
++ *
++ * based on coyote-pci.c:
++ * Copyright (C) 2002 Jungo Software Technologies.
++ * Copyright (C) 2003 MontaVista Softwrae, Inc.
++ *
++ * Maintainer: Imre Kaloz <kaloz@openwrt.org>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include <linux/kernel.h>
++#include <linux/pci.h>
++#include <linux/init.h>
++#include <linux/irq.h>
++
++#include <asm/mach-types.h>
++#include <asm/hardware.h>
++#include <asm/irq.h>
++
++#include <asm/mach/pci.h>
++
++extern void ixp4xx_pci_preinit(void);
++extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
++extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
++
++void __init cambria_pci_preinit(void)
++{
++ set_irq_type(IRQ_IXP4XX_GPIO11, IRQT_LOW);
++ set_irq_type(IRQ_IXP4XX_GPIO10, IRQT_LOW);
++ set_irq_type(IRQ_IXP4XX_GPIO9, IRQT_LOW);
++ set_irq_type(IRQ_IXP4XX_GPIO8, IRQT_LOW);
++
++ ixp4xx_pci_preinit();
++}
++
++static int __init cambria_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
++{
++ if (slot == 1)
++ return IRQ_IXP4XX_GPIO11;
++ else if (slot == 2)
++ return IRQ_IXP4XX_GPIO10;
++ else if (slot == 3)
++ return IRQ_IXP4XX_GPIO9;
++ else if (slot == 4)
++ return IRQ_IXP4XX_GPIO8;
++ else return -1;
++}
++
++struct hw_pci cambria_pci __initdata = {
++ .nr_controllers = 1,
++ .preinit = cambria_pci_preinit,
++ .swizzle = pci_std_swizzle,
++ .setup = ixp4xx_setup,
++ .scan = ixp4xx_scan_bus,
++ .map_irq = cambria_map_irq,
++};
++
++int __init cambria_pci_init(void)
++{
++ if (machine_is_cambria())
++ pci_common_init(&cambria_pci);
++ return 0;
++}
++
++subsys_initcall(cambria_pci_init);
+--- /dev/null
++++ b/arch/arm/mach-ixp4xx/cambria-setup.c
+@@ -0,0 +1,444 @@
++/*
++ * arch/arm/mach-ixp4xx/cambria-setup.c
++ *
++ * Board setup for the Gateworks Cambria series
++ *
++ * Copyright (C) 2008 Imre Kaloz <Kaloz@openwrt.org>
++ *
++ * based on coyote-setup.c:
++ * Copyright (C) 2003-2005 MontaVista Software, Inc.
++ *
++ * Author: Imre Kaloz <Kaloz@openwrt.org>
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/device.h>
++#include <linux/if_ether.h>
++#include <linux/socket.h>
++#include <linux/netdevice.h>
++#include <linux/serial.h>
++#include <linux/tty.h>
++#include <linux/serial_8250.h>
++#include <linux/slab.h>
++#ifdef CONFIG_SENSORS_EEPROM
++# include <linux/i2c.h>
++# include <linux/eeprom.h>
++#endif
++
++#include <linux/leds.h>
++#include <linux/i2c-gpio.h>
++#include <asm/types.h>
++#include <asm/setup.h>
++#include <asm/memory.h>
++#include <asm/hardware.h>
++#include <asm/irq.h>
++#include <asm/mach-types.h>
++#include <asm/mach/arch.h>
++#include <asm/mach/flash.h>
++
++struct cambria_board_info {
++ unsigned char *model;
++ void (* setup)(void);
++};
++
++static struct cambria_board_info *cambria_info __initdata;
++
++static struct flash_platform_data cambria_flash_data = {
++ .map_name = "cfi_probe",
++ .width = 2,
++};
++
++static struct resource cambria_flash_resource = {
++ .flags = IORESOURCE_MEM,
++};
++
++static struct platform_device cambria_flash = {
++ .name = "IXP4XX-Flash",
++ .id = 0,
++ .dev = {
++ .platform_data = &cambria_flash_data,
++ },
++ .num_resources = 1,
++ .resource = &cambria_flash_resource,
++};
++
++static struct i2c_gpio_platform_data cambria_i2c_gpio_data = {
++ .sda_pin = 7,
++ .scl_pin = 6,
++};
++
++static struct platform_device cambria_i2c_gpio = {
++ .name = "i2c-gpio",
++ .id = 0,
++ .dev = {
++ .platform_data = &cambria_i2c_gpio_data,
++ },
++};
++
++static struct resource cambria_uart_resource = {
++ .start = IXP4XX_UART1_BASE_PHYS,
++ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
++ .flags = IORESOURCE_MEM,
++};
++
++static struct plat_serial8250_port cambria_uart_data[] = {
++ {
++ .mapbase = IXP4XX_UART1_BASE_PHYS,
++ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
++ .irq = IRQ_IXP4XX_UART1,
++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
++ .iotype = UPIO_MEM,
++ .regshift = 2,
++ .uartclk = IXP4XX_UART_XTAL,
++ },
++ { },
++};
++
++static struct platform_device cambria_uart = {
++ .name = "serial8250",
++ .id = PLAT8250_DEV_PLATFORM,
++ .dev = {
++ .platform_data = cambria_uart_data,
++ },
++ .num_resources = 1,
++ .resource = &cambria_uart_resource,
++};
++
++static struct resource cambria_pata_resources[] = {
++ {
++ .flags = IORESOURCE_MEM
++ },
++ {
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "intrq",
++ .start = IRQ_IXP4XX_GPIO12,
++ .end = IRQ_IXP4XX_GPIO12,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct ixp4xx_pata_data cambria_pata_data = {
++ .cs0_bits = 0xbfff3c03,
++ .cs1_bits = 0xbfff3c03,
++};
++
++static struct platform_device cambria_pata = {
++ .name = "pata_ixp4xx_cf",
++ .id = 0,
++ .dev.platform_data = &cambria_pata_data,
++ .num_resources = ARRAY_SIZE(cambria_pata_resources),
++ .resource = cambria_pata_resources,
++};
++
++static struct eth_plat_info cambria_npec_data = {
++ .phy = 1,
++ .rxq = 4,
++ .txreadyq = 21,
++};
++
++static struct eth_plat_info cambria_npea_data = {
++ .phy = 2,
++ .rxq = 2,
++ .txreadyq = 19,
++};
++
++static struct platform_device cambria_npec_device = {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEC,
++ .dev.platform_data = &cambria_npec_data,
++};
++
++static struct platform_device cambria_npea_device = {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEA,
++ .dev.platform_data = &cambria_npea_data,
++};
++
++static struct gpio_led cambria_gpio_leds[] = {
++ {
++ .name = "user", /* green led */
++ .gpio = 5,
++ .active_low = 1,
++ }
++};
++
++static struct gpio_led_platform_data cambria_gpio_leds_data = {
++ .num_leds = 1,
++ .leds = cambria_gpio_leds,
++};
++
++static struct platform_device cambria_gpio_leds_device = {
++ .name = "leds-gpio",
++ .id = -1,
++ .dev.platform_data = &cambria_gpio_leds_data,
++};
++
++
++static struct latch_led cambria_latch_leds[] = {
++ {
++ .name = "ledA", /* green led */
++ .bit = 0,
++ },
++ {
++ .name = "ledB", /* green led */
++ .bit = 1,
++ },
++ {
++ .name = "ledC", /* green led */
++ .bit = 2,
++ },
++ {
++ .name = "ledD", /* green led */
++ .bit = 3,
++ },
++ {
++ .name = "ledE", /* green led */
++ .bit = 4,
++ },
++ {
++ .name = "ledF", /* green led */
++ .bit = 5,
++ },
++ {
++ .name = "ledG", /* green led */
++ .bit = 6,
++ },
++ {
++ .name = "ledH", /* green led */
++ .bit = 7,
++ }
++};
++
++static struct latch_led_platform_data cambria_latch_leds_data = {
++ .num_leds = 8,
++ .leds = cambria_latch_leds,
++ .mem = 0x53F40000,
++};
++
++static struct platform_device cambria_latch_leds_device = {
++ .name = "leds-latch",
++ .id = -1,
++ .dev.platform_data = &cambria_latch_leds_data,
++};
++
++static struct resource cambria_usb0_resources[] = {
++ {
++ .start = 0xCD000000,
++ .end = 0xCD000300,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .start = 32,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct resource cambria_usb1_resources[] = {
++ {
++ .start = 0xCE000000,
++ .end = 0xCE000300,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .start = 33,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static u64 ehci_dma_mask = ~(u32)0;
++
++static struct platform_device cambria_usb0_device = {
++ .name = "ixp4xx-ehci",
++ .id = 0,
++ .resource = cambria_usb0_resources,
++ .num_resources = ARRAY_SIZE(cambria_usb0_resources),
++ .dev = {
++ .dma_mask = &ehci_dma_mask,
++ .coherent_dma_mask = 0xffffffff,
++ },
++};
++
++static struct platform_device cambria_usb1_device = {
++ .name = "ixp4xx-ehci",
++ .id = 1,
++ .resource = cambria_usb1_resources,
++ .num_resources = ARRAY_SIZE(cambria_usb1_resources),
++ .dev = {
++ .dma_mask = &ehci_dma_mask,
++ .coherent_dma_mask = 0xffffffff,
++ },
++};
++
++static struct platform_device *cambria_devices[] __initdata = {
++ &cambria_i2c_gpio,
++ &cambria_flash,
++ &cambria_uart,
++};
++
++static void __init cambria_gw23xx_setup(void)
++{
++ platform_device_register(&cambria_npec_device);
++ platform_device_register(&cambria_npea_device);
++}
++
++#ifdef CONFIG_SENSORS_EEPROM
++static void __init cambria_gw2350_setup(void)
++{
++ platform_device_register(&cambria_npec_device);
++ platform_device_register(&cambria_npea_device);
++
++ platform_device_register(&cambria_usb0_device);
++ platform_device_register(&cambria_usb1_device);
++
++ platform_device_register(&cambria_gpio_leds_device);
++}
++
++static void __init cambria_gw2358_setup(void)
++{
++ platform_device_register(&cambria_npec_device);
++ platform_device_register(&cambria_npea_device);
++
++ platform_device_register(&cambria_usb0_device);
++ platform_device_register(&cambria_usb1_device);
++
++ platform_device_register(&cambria_pata);
++
++ platform_device_register(&cambria_latch_leds_device);
++}
++
++static struct cambria_board_info cambria_boards[] __initdata = {
++ {
++ .model = "GW2350",
++ .setup = cambria_gw2350_setup,
++ }, {
++ .model = "GW2358",
++ .setup = cambria_gw2358_setup,
++ }
++};
++
++static struct cambria_board_info * __init cambria_find_board_info(char *model)
++{
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(cambria_boards); i++) {
++ struct cambria_board_info *info = &cambria_boards[i];
++ if (strncmp(info->model, model, strlen(info->model)) == 0)
++ return info;
++ }
++
++ return NULL;
++}
++
++struct cambria_eeprom_header {
++ unsigned char mac0[ETH_ALEN];
++ unsigned char mac1[ETH_ALEN];
++ unsigned char res0[4];
++ unsigned char magic[2];
++ unsigned char config[14];
++ unsigned char model[16];
++};
++
++static int __init cambria_eeprom_notify(struct notifier_block *self,
++ unsigned long event, void *t)
++{
++ struct eeprom_data *ee = t;
++ struct cambria_eeprom_header hdr;
++
++ if (cambria_info)
++ return NOTIFY_DONE;
++
++ /* The eeprom is at address 0x51 */
++ if (event != EEPROM_REGISTER || ee->client.addr != 0x51)
++ return NOTIFY_DONE;
++
++ ee->attr->read(&ee->client.dev.kobj, ee->attr, (char *)&hdr,
++ 0, sizeof(hdr));
++
++ if (hdr.magic[0] != 'G' || hdr.magic[1] != 'W')
++ return NOTIFY_DONE;
++
++ memcpy(&cambria_npec_data.hwaddr, hdr.mac0, ETH_ALEN);
++ memcpy(&cambria_npea_data.hwaddr, hdr.mac1, ETH_ALEN);
++
++ cambria_info = cambria_find_board_info(hdr.model);
++
++ return NOTIFY_OK;
++}
++
++static struct notifier_block cambria_eeprom_notifier __initdata = {
++ .notifier_call = cambria_eeprom_notify
++};
++
++static void __init cambria_register_eeprom_notifier(void)
++{
++ register_eeprom_notifier(&cambria_eeprom_notifier);
++}
++
++static void __init cambria_unregister_eeprom_notifier(void)
++{
++ unregister_eeprom_notifier(&cambria_eeprom_notifier);
++}
++#else /* CONFIG_SENSORS_EEPROM */
++static inline void cambria_register_eeprom_notifier(void) {};
++static inline void cambria_unregister_eeprom_notifier(void) {};
++#endif /* CONFIG_SENSORS_EEPROM */
++
++static void __init cambria_init(void)
++{
++ ixp4xx_sys_init();
++
++ cambria_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
++ cambria_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
++
++ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
++ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
++
++ platform_add_devices(cambria_devices, ARRAY_SIZE(cambria_devices));
++
++ cambria_pata_resources[0].start = 0x53e00000;
++ cambria_pata_resources[0].end = 0x53e3ffff;
++
++ cambria_pata_resources[1].start = 0x53e40000;
++ cambria_pata_resources[1].end = 0x53e7ffff;
++
++ cambria_pata_data.cs0_cfg = IXP4XX_EXP_CS3;
++ cambria_pata_data.cs1_cfg = IXP4XX_EXP_CS3;
++
++ cambria_register_eeprom_notifier();
++}
++
++static int __init cambria_model_setup(void)
++{
++ if (!machine_is_cambria())
++ return 0;
++
++ if (cambria_info) {
++ printk(KERN_DEBUG "Running on Gateworks Cambria %s\n",
++ cambria_info->model);
++ cambria_info->setup();
++ } else {
++ printk(KERN_INFO "Unknown/missing Cambria model number"
++ " -- defaults will be used\n");
++ cambria_gw23xx_setup();
++ }
++
++ cambria_unregister_eeprom_notifier();
++ return 0;
++}
++late_initcall(cambria_model_setup);
++
++#ifdef CONFIG_MACH_CAMBRIA
++MACHINE_START(CAMBRIA, "Gateworks Cambria series")
++ /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
++ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
++ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
++ .map_io = ixp4xx_map_io,
++ .init_irq = ixp4xx_init_irq,
++ .timer = &ixp4xx_timer,
++ .boot_params = 0x0100,
++ .init_machine = cambria_init,
++MACHINE_END
++#endif
+--- a/include/asm-arm/arch-ixp4xx/hardware.h
++++ b/include/asm-arm/arch-ixp4xx/hardware.h
+@@ -18,7 +18,7 @@
+ #define __ASM_ARCH_HARDWARE_H__
+
+ #define PCIBIOS_MIN_IO 0x00001000
+-#define PCIBIOS_MIN_MEM (cpu_is_ixp43x() ? 0x40000000 : 0x48000000)
++#define PCIBIOS_MIN_MEM (cpu_is_ixp43x() ? 0x48000000 : 0x48000000)
+
+ /*
+ * We override the standard dma-mask routines for bouncing.
--- /dev/null
+--- a/arch/arm/mach-ixp4xx/cambria-setup.c
++++ b/arch/arm/mach-ixp4xx/cambria-setup.c
+@@ -36,6 +36,7 @@
+ #include <asm/mach-types.h>
+ #include <asm/mach/arch.h>
+ #include <asm/mach/flash.h>
++#include <linux/irq.h>
+
+ struct cambria_board_info {
+ unsigned char *model;
+@@ -105,6 +106,43 @@
+ .resource = &cambria_uart_resource,
+ };
+
++static struct resource cambria_optional_uart_resources[] = {
++ {
++ .start = 0x52000000,
++ .end = 0x52000fff,
++ .flags = IORESOURCE_MEM
++ },
++ {
++ .start = 0x53000000,
++ .end = 0x53000fff,
++ .flags = IORESOURCE_MEM
++ }
++};
++
++static struct plat_serial8250_port cambria_optional_uart_data[] = {
++ {
++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_BUGGY_UART,
++ .iotype = UPIO_MEM,
++ .regshift = 0,
++ .uartclk = 1843200,
++ },
++ {
++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_BUGGY_UART,
++ .iotype = UPIO_MEM,
++ .regshift = 0,
++ .uartclk = 1843200,
++ },
++ { },
++};
++
++static struct platform_device cambria_optional_uart = {
++ .name = "serial8250",
++ .id = PLAT8250_DEV_PLATFORM1,
++ .dev.platform_data = cambria_optional_uart_data,
++ .num_resources = 2,
++ .resource = cambria_optional_uart_resources,
++};
++
+ static struct resource cambria_pata_resources[] = {
+ {
+ .flags = IORESOURCE_MEM
+@@ -287,6 +325,19 @@
+ #ifdef CONFIG_SENSORS_EEPROM
+ static void __init cambria_gw2350_setup(void)
+ {
++ *IXP4XX_EXP_CS2 = 0xbfff0003;
++ set_irq_type(IRQ_IXP4XX_GPIO3, IRQT_RISING);
++ cambria_optional_uart_data[0].mapbase = 0x52FF0000;
++ cambria_optional_uart_data[0].membase = (void __iomem *)ioremap(0x52FF0000, 0x0fff);
++ cambria_optional_uart_data[0].irq = IRQ_IXP4XX_GPIO3;
++
++ *IXP4XX_EXP_CS3 = 0xbfff0003;
++ set_irq_type(IRQ_IXP4XX_GPIO4, IRQT_RISING);
++ cambria_optional_uart_data[1].mapbase = 0x53FF0000;
++ cambria_optional_uart_data[1].membase = (void __iomem *)ioremap(0x53FF0000, 0x0fff);
++ cambria_optional_uart_data[1].irq = IRQ_IXP4XX_GPIO4;
++
++ platform_device_register(&cambria_optional_uart);
+ platform_device_register(&cambria_npec_device);
+ platform_device_register(&cambria_npea_device);
+
+@@ -294,10 +345,26 @@
+ platform_device_register(&cambria_usb1_device);
+
+ platform_device_register(&cambria_gpio_leds_device);
++
++ *IXP4XX_EXP_CS2 = 0xBFFF3C43;
++ *IXP4XX_EXP_CS3 = 0xBFFF3C43;
+ }
+
+ static void __init cambria_gw2358_setup(void)
+ {
++ *IXP4XX_EXP_CS3 = 0xbfff0003;
++ set_irq_type(IRQ_IXP4XX_GPIO3, IRQT_RISING);
++ cambria_optional_uart_data[0].mapbase = 0x53FC0000;
++ cambria_optional_uart_data[0].membase = (void __iomem *)ioremap(0x53FC0000, 0x0fff);
++ cambria_optional_uart_data[0].irq = IRQ_IXP4XX_GPIO3;
++
++ set_irq_type(IRQ_IXP4XX_GPIO4, IRQT_RISING);
++ cambria_optional_uart_data[1].mapbase = 0x53F80000;
++ cambria_optional_uart_data[1].membase = (void __iomem *)ioremap(0x53F80000, 0x0fff);
++ cambria_optional_uart_data[1].irq = IRQ_IXP4XX_GPIO4;
++
++ platform_device_register(&cambria_optional_uart);
++
+ platform_device_register(&cambria_npec_device);
+ platform_device_register(&cambria_npea_device);
+
--- /dev/null
+--- a/arch/arm/mach-ixp4xx/cambria-setup.c
++++ b/arch/arm/mach-ixp4xx/cambria-setup.c
+@@ -214,6 +214,21 @@
+ .dev.platform_data = &cambria_gpio_leds_data,
+ };
+
++static struct resource cambria_gpio_resources[] = {
++ {
++ .name = "gpio",
++ .flags = 0,
++ },
++};
++
++static struct platform_device cambria_gpio = {
++ .name = "GPIODEV",
++ .id = -1,
++ .num_resources = ARRAY_SIZE(cambria_gpio_resources),
++ .resource = cambria_gpio_resources,
++};
++
++
+
+ static struct latch_led cambria_latch_leds[] = {
+ {
+@@ -337,6 +352,11 @@
+ cambria_optional_uart_data[1].membase = (void __iomem *)ioremap(0x53FF0000, 0x0fff);
+ cambria_optional_uart_data[1].irq = IRQ_IXP4XX_GPIO4;
+
++ cambria_gpio_resources[0].start = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4) |\
++ (1 << 5) | (1 << 8) | (1 << 9) | (1 << 12);
++ cambria_gpio_resources[0].end = cambria_gpio_resources[0].start;
++
++ platform_device_register(&cambria_gpio);
+ platform_device_register(&cambria_optional_uart);
+ platform_device_register(&cambria_npec_device);
+ platform_device_register(&cambria_npea_device);
+@@ -363,6 +383,10 @@
+ cambria_optional_uart_data[1].membase = (void __iomem *)ioremap(0x53F80000, 0x0fff);
+ cambria_optional_uart_data[1].irq = IRQ_IXP4XX_GPIO4;
+
++ cambria_gpio_resources[0].start = (1 << 14);
++ cambria_gpio_resources[0].end = cambria_gpio_resources[0].start;
++
++ platform_device_register(&cambria_gpio);
+ platform_device_register(&cambria_optional_uart);
+
+ platform_device_register(&cambria_npec_device);
--- /dev/null
+--- a/arch/arm/mach-ixp4xx/ixp4xx_npe.c
++++ b/arch/arm/mach-ixp4xx/ixp4xx_npe.c
+@@ -592,6 +592,8 @@
+ npe_reset(npe);
+ #endif
+
++ print_npe(KERN_INFO, npe, "firmware's license can be found in /usr/share/doc/LICENSE.IPL\n");
++
+ print_npe(KERN_INFO, npe, "firmware functionality 0x%X, "
+ "revision 0x%X:%X\n", (image->id >> 16) & 0xFF,
+ (image->id >> 8) & 0xFF, image->id & 0xFF);
--- /dev/null
+--- a/drivers/net/arm/ixp4xx_eth.c
++++ b/drivers/net/arm/ixp4xx_eth.c
+@@ -165,14 +165,15 @@
+ struct net_device *netdev;
+ struct napi_struct napi;
+ struct net_device_stats stat;
+- struct mii_if_info mii;
++ struct mii_if_info mii[IXP4XX_ETH_PHY_MAX_ADDR];
+ struct delayed_work mdio_thread;
+ struct eth_plat_info *plat;
+ buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
+ struct desc *desc_tab; /* coherent */
+ u32 desc_tab_phys;
+ int id; /* logical port ID */
+- u16 mii_bmcr;
++ u16 mii_bmcr[IXP4XX_ETH_PHY_MAX_ADDR];
++ int phy_count;
+ };
+
+ /* NPE message structure */
+@@ -316,12 +317,13 @@
+ spin_unlock_irqrestore(&mdio_lock, flags);
+ }
+
+-static void phy_reset(struct net_device *dev, int phy_id)
++static void phy_reset(struct net_device *dev, int idx)
+ {
+ struct port *port = netdev_priv(dev);
++ int phy_id = port->mii[idx].phy_id;
+ int cycles = 0;
+
+- mdio_write(dev, phy_id, MII_BMCR, port->mii_bmcr | BMCR_RESET);
++ mdio_write(dev, phy_id, MII_BMCR, port->mii_bmcr[idx] | BMCR_RESET);
+
+ while (cycles < MAX_MII_RESET_RETRIES) {
+ if (!(mdio_read(dev, phy_id, MII_BMCR) & BMCR_RESET)) {
+@@ -335,12 +337,12 @@
+ cycles++;
+ }
+
+- printk(KERN_ERR "%s: MII reset failed\n", dev->name);
++ printk(KERN_ERR "%s: MII reset failed on PHY%2d\n", dev->name, phy_id);
+ }
+
+-static void eth_set_duplex(struct port *port)
++static void eth_set_duplex(struct port *port, int full_duplex)
+ {
+- if (port->mii.full_duplex)
++ if (full_duplex)
+ __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX,
+ &port->regs->tx_control[0]);
+ else
+@@ -348,7 +350,7 @@
+ &port->regs->tx_control[0]);
+ }
+
+-
++#if 0
+ static void phy_check_media(struct port *port, int init)
+ {
+ if (mii_check_media(&port->mii, 1, init))
+@@ -367,7 +369,63 @@
+ }
+ }
+ }
++#else
++static void phy_update_link(struct net_device *dev, int link)
++{
++ int prev_link = netif_carrier_ok(dev);
++
++ if (!prev_link && link) {
++ printk(KERN_INFO "%s: link up\n", dev->name);
++ netif_carrier_on(dev);
++ } else if (prev_link && !link) {
++ printk(KERN_INFO "%s: link down\n", dev->name);
++ netif_carrier_off(dev);
++ }
++}
++
++static void phy_check_media(struct port *port, int init)
++{
++ struct net_device *dev = port->netdev;
++
++ if (port->phy_count == 1) {
++ struct mii_if_info *mii = &port->mii[0];
++
++ if (mii_check_media(mii, 1, init))
++ eth_set_duplex(port, mii->full_duplex);
++
++ if (mii->force_media) /* mii_check_media() doesn't work */
++ phy_update_link(dev, mii_link_ok(mii));
++ } else {
++ int cur_link = 0;
++ int i;
++
++ if (init)
++ eth_set_duplex(port, 1);
++
++ for (i = 0; i < port->phy_count; i++)
++ cur_link |= mii_link_ok(&port->mii[i]);
++
++ phy_update_link(dev, cur_link);
++ }
++}
++#endif
++
++static void phy_power_down(struct net_device *dev, int idx)
++{
++ struct port *port = netdev_priv(dev);
++ int phy_id = port->mii[idx].phy_id;
++
++ port->mii_bmcr[idx] = mdio_read(dev, phy_id, MII_BMCR) &
++ ~(BMCR_RESET | BMCR_PDOWN);
++ mdio_write(dev, phy_id, MII_BMCR, port->mii_bmcr[idx] | BMCR_PDOWN);
++}
++
++static void phy_power_up(struct net_device *dev, int idx)
++{
++ struct port *port = netdev_priv(dev);
+
++ mdio_write(dev, port->mii[idx].phy_id, MII_BMCR, port->mii_bmcr[idx]);
++}
+
+ static void mdio_thread(struct work_struct *work)
+ {
+@@ -792,9 +850,12 @@
+
+ if (!netif_running(dev))
+ return -EINVAL;
+- err = generic_mii_ioctl(&port->mii, if_mii(req), cmd, &duplex_chg);
++ if (port->phy_count != 1)
++ return -EOPNOTSUPP;
++
++ err = generic_mii_ioctl(&port->mii[0], if_mii(req), cmd, &duplex_chg);
+ if (duplex_chg)
+- eth_set_duplex(port);
++ eth_set_duplex(port, port->mii[0].full_duplex);
+ return err;
+ }
+
+@@ -947,7 +1008,8 @@
+ }
+ }
+
+- mdio_write(dev, port->plat->phy, MII_BMCR, port->mii_bmcr);
++ for (i = 0; i < port->phy_count; i++)
++ phy_power_up(dev, i);
+
+ memset(&msg, 0, sizeof(msg));
+ msg.cmd = NPE_VLAN_SETRXQOSENTRY;
+@@ -1107,10 +1169,8 @@
+ printk(KERN_CRIT "%s: unable to disable loopback\n",
+ dev->name);
+
+- port->mii_bmcr = mdio_read(dev, port->plat->phy, MII_BMCR) &
+- ~(BMCR_RESET | BMCR_PDOWN); /* may have been altered */
+- mdio_write(dev, port->plat->phy, MII_BMCR,
+- port->mii_bmcr | BMCR_PDOWN);
++ for (i = 0; i < port->phy_count; i++)
++ phy_power_down(dev, i);
+
+ if (!ports_open)
+ qmgr_disable_irq(TXDONE_QUEUE);
+@@ -1120,6 +1180,42 @@
+ return 0;
+ }
+
++static void eth_add_phy(struct net_device *dev, int phy_id)
++{
++ struct port *port = netdev_priv(dev);
++ int i;
++
++ i = port->phy_count++;
++
++ port->mii[i].dev = dev;
++ port->mii[i].mdio_read = mdio_read;
++ port->mii[i].mdio_write = mdio_write;
++ port->mii[i].phy_id = phy_id;
++ port->mii[i].phy_id_mask = 0x1F;
++ port->mii[i].reg_num_mask = 0x1F;
++
++ printk(KERN_INFO "%s: MII PHY %i on %s\n", dev->name, phy_id,
++ npe_name(port->npe));
++
++ phy_reset(dev, i);
++ phy_power_down(dev, i);
++}
++
++static void eth_init_mii(struct net_device *dev)
++{
++ struct port *port = netdev_priv(dev);
++
++ if (port->plat->phy < IXP4XX_ETH_PHY_MAX_ADDR) {
++ eth_add_phy(dev, port->plat->phy);
++ } else {
++ int i;
++ for (i = 0; i < IXP4XX_ETH_PHY_MAX_ADDR; i++)
++ if (port->plat->phy_mask & (1U << i))
++ eth_add_phy(dev, i);
++ }
++
++}
++
+ static int __devinit eth_init_one(struct platform_device *pdev)
+ {
+ struct port *port;
+@@ -1192,20 +1288,7 @@
+ __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control);
+ udelay(50);
+
+- port->mii.dev = dev;
+- port->mii.mdio_read = mdio_read;
+- port->mii.mdio_write = mdio_write;
+- port->mii.phy_id = plat->phy;
+- port->mii.phy_id_mask = 0x1F;
+- port->mii.reg_num_mask = 0x1F;
+-
+- printk(KERN_INFO "%s: MII PHY %i on %s\n", dev->name, plat->phy,
+- npe_name(port->npe));
+-
+- phy_reset(dev, plat->phy);
+- port->mii_bmcr = mdio_read(dev, plat->phy, MII_BMCR) &
+- ~(BMCR_RESET | BMCR_PDOWN);
+- mdio_write(dev, plat->phy, MII_BMCR, port->mii_bmcr | BMCR_PDOWN);
++ eth_init_mii(dev);
+
+ INIT_DELAYED_WORK(&port->mdio_thread, mdio_thread);
+ return 0;
+--- a/include/asm-arm/arch-ixp4xx/platform.h
++++ b/include/asm-arm/arch-ixp4xx/platform.h
+@@ -95,12 +95,15 @@
+ #define IXP4XX_ETH_NPEB 0x10
+ #define IXP4XX_ETH_NPEC 0x20
+
++#define IXP4XX_ETH_PHY_MAX_ADDR 32
++
+ /* Information about built-in Ethernet MAC interfaces */
+ struct eth_plat_info {
+ u8 phy; /* MII PHY ID, 0 - 31 */
+ u8 rxq; /* configurable, currently 0 - 31 only */
+ u8 txreadyq;
+ u8 hwaddr[6];
++ u32 phy_mask;
+ };
+
+ /* Information about built-in HSS (synchronous serial) interfaces */
--- /dev/null
+--- a/drivers/net/arm/ixp4xx_eth.c
++++ b/drivers/net/arm/ixp4xx_eth.c
+@@ -322,8 +322,12 @@
+ struct port *port = netdev_priv(dev);
+ int phy_id = port->mii[idx].phy_id;
+ int cycles = 0;
++ u16 bmcr;
+
+- mdio_write(dev, phy_id, MII_BMCR, port->mii_bmcr[idx] | BMCR_RESET);
++ /* reset the PHY */
++ bmcr = mdio_read(dev, phy_id, MII_BMCR);
++ bmcr |= BMCR_ANENABLE;
++ mdio_write(dev, phy_id, MII_BMCR, bmcr | BMCR_RESET);
+
+ while (cycles < MAX_MII_RESET_RETRIES) {
+ if (!(mdio_read(dev, phy_id, MII_BMCR) & BMCR_RESET)) {
+@@ -331,13 +335,23 @@
+ printk(KERN_DEBUG "%s: phy_reset() took %i cycles\n",
+ dev->name, cycles);
+ #endif
+- return;
++ break;
+ }
+ udelay(1);
+ cycles++;
+ }
+
+- printk(KERN_ERR "%s: MII reset failed on PHY%2d\n", dev->name, phy_id);
++ if (cycles == MAX_MII_RESET_RETRIES) {
++ printk(KERN_ERR "%s: MII reset failed on PHY%2d\n", dev->name,
++ phy_id);
++ return;
++ }
++
++ /* restart auto negotiation */
++ bmcr = mdio_read(dev, phy_id, MII_BMCR);
++ bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
++ mdio_write(dev, phy_id, MII_BMCR, bmcr);
++
+ }
+
+ static void eth_set_duplex(struct port *port, int full_duplex)
--- /dev/null
+From cba5c286f3ea34ea4767fc00c705434a00fe2c37 Mon Sep 17 00:00:00 2001
+From: Imre Kaloz <kaloz@openwrt.org>
+Date: Thu, 26 Jun 2008 01:58:02 +0200
+Subject: [PATCH] Add support for the ethernet ports on IXP43x
+
+---
+ arch/arm/mach-ixp4xx/ixp4xx_npe.c | 6 +++---
+ drivers/net/arm/ixp4xx_eth.c | 13 +++++++++----
+ include/asm-arm/arch-ixp4xx/cpu.h | 2 ++
+ include/asm-arm/arch-ixp4xx/ixp4xx-regs.h | 7 ++++---
+ 4 files changed, 18 insertions(+), 10 deletions(-)
+
+--- a/arch/arm/mach-ixp4xx/ixp4xx_npe.c
++++ b/arch/arm/mach-ixp4xx/ixp4xx_npe.c
+@@ -575,8 +575,8 @@
+ for (i = 0; i < image->size; i++)
+ image->data[i] = swab32(image->data[i]);
+
+- if (!cpu_is_ixp46x() && ((image->id >> 28) & 0xF /* device ID */)) {
+- print_npe(KERN_INFO, npe, "IXP46x firmware ignored on "
++ if (cpu_is_ixp42x() && ((image->id >> 28) & 0xF /* device ID */)) {
++ print_npe(KERN_INFO, npe, "IXP46x/IXP43x firmware ignored on "
+ "IXP42x\n");
+ goto err;
+ }
+@@ -598,7 +598,7 @@
+ "revision 0x%X:%X\n", (image->id >> 16) & 0xFF,
+ (image->id >> 8) & 0xFF, image->id & 0xFF);
+
+- if (!cpu_is_ixp46x()) {
++ if (cpu_is_ixp42x()) {
+ if (!npe->id)
+ instr_size = NPE_A_42X_INSTR_SIZE;
+ else
+--- a/drivers/net/arm/ixp4xx_eth.c
++++ b/drivers/net/arm/ixp4xx_eth.c
+@@ -32,6 +32,7 @@
+ #include <linux/kernel.h>
+ #include <linux/mii.h>
+ #include <linux/platform_device.h>
++#include <asm/arch/cpu.h>
+ #include <asm/arch/npe.h>
+ #include <asm/arch/qmgr.h>
+
+@@ -1338,12 +1339,16 @@
+
+ static int __init eth_init_module(void)
+ {
+- if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEB_ETH0))
+- return -ENOSYS;
+
+- /* All MII PHY accesses use NPE-B Ethernet registers */
+ spin_lock_init(&mdio_lock);
+- mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
++ if (!cpu_is_ixp43x())
++ /* All MII PHY accesses use NPE-B Ethernet registers */
++ mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
++
++ else
++ /* IXP43x lacks NPE-B and uses NPE-C for MII PHY access */
++ mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT;
++
+ __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control);
+
+ return platform_driver_register(&drv);
+--- a/include/asm-arm/arch-ixp4xx/cpu.h
++++ b/include/asm-arm/arch-ixp4xx/cpu.h
+@@ -34,6 +34,8 @@
+ val &= ~IXP4XX_FEATURE_RESERVED;
+ if (!cpu_is_ixp46x())
+ val &= ~IXP4XX_FEATURE_IXP46X_ONLY;
++ if (cpu_is_ixp42x())
++ val &= ~IXP4XX_FEATURE_IXP43X_46X;
+
+ return val;
+ }
+--- a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
++++ b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
+@@ -628,11 +628,12 @@
+ #define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22)
+ #define IXP4XX_FEATURE_RESERVED (0xFF << 24)
+
+-#define IXP4XX_FEATURE_IXP46X_ONLY (IXP4XX_FEATURE_ECC_TIMESYNC | \
++#define IXP4XX_FEATURE_IXP43X_46X (IXP4XX_FEATURE_ECC_TIMESYNC | \
+ IXP4XX_FEATURE_USB_HOST | \
+ IXP4XX_FEATURE_NPEA_ETH | \
+- IXP4XX_FEATURE_NPEB_ETH_1_TO_3 | \
+- IXP4XX_FEATURE_RSA | \
+ IXP4XX_FEATURE_XSCALE_MAX_FREQ)
+
++#define IXP4XX_FEATURE_IXP46X_ONLY (IXP4XX_FEATURE_NPEB_ETH_1_TO_3 | \
++ IXP4XX_FEATURE_RSA)
++
+ #endif
--- /dev/null
+--- a/drivers/net/wan/Kconfig
++++ b/drivers/net/wan/Kconfig
+@@ -336,6 +336,15 @@
+
+ Say Y if your card supports this feature.
+
++config IXP4XX_HSS
++ tristate "IXP4xx HSS (synchronous serial port) support"
++ depends on HDLC && ARM && ARCH_IXP4XX
++ select IXP4XX_NPE
++ select IXP4XX_QMGR
++ help
++ Say Y here if you want to use built-in HSS ports
++ on IXP4xx processor.
++
+ config DLCI
+ tristate "Frame Relay DLCI support"
+ ---help---
+--- a/drivers/net/wan/Makefile
++++ b/drivers/net/wan/Makefile
+@@ -42,6 +42,7 @@
+ obj-$(CONFIG_WANXL) += wanxl.o
+ obj-$(CONFIG_PCI200SYN) += pci200syn.o
+ obj-$(CONFIG_PC300TOO) += pc300too.o
++obj-$(CONFIG_IXP4XX_HSS) += ixp4xx_hss.o
+
+ clean-files := wanxlfw.inc
+ $(obj)/wanxl.o: $(obj)/wanxlfw.inc
+--- /dev/null
++++ b/drivers/net/wan/ixp4xx_hss.c
+@@ -0,0 +1,2886 @@
++/*
++ * Intel IXP4xx HSS (synchronous serial port) driver for Linux
++ *
++ * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License
++ * as published by the Free Software Foundation.
++ */
++
++#include <linux/bitops.h>
++#include <linux/cdev.h>
++#include <linux/dma-mapping.h>
++#include <linux/dmapool.h>
++#include <linux/fs.h>
++#include <linux/io.h>
++#include <linux/kernel.h>
++#include <linux/hdlc.h>
++#include <linux/platform_device.h>
++#include <linux/poll.h>
++#include <asm/arch/npe.h>
++#include <asm/arch/qmgr.h>
++
++#define DEBUG_QUEUES 0
++#define DEBUG_DESC 0
++#define DEBUG_RX 0
++#define DEBUG_TX 0
++#define DEBUG_PKT_BYTES 0
++#define DEBUG_CLOSE 0
++#define DEBUG_FRAMER 0
++
++#define DRV_NAME "ixp4xx_hss"
++
++#define PKT_EXTRA_FLAGS 0 /* orig 1 */
++#define TX_FRAME_SYNC_OFFSET 0 /* channelized */
++#define PKT_NUM_PIPES 1 /* 1, 2 or 4 */
++#define PKT_PIPE_FIFO_SIZEW 4 /* total 4 dwords per HSS */
++
++#define RX_DESCS 16 /* also length of all RX queues */
++#define TX_DESCS 16 /* also length of all TX queues */
++
++#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
++#define RX_SIZE (HDLC_MAX_MRU + 4) /* NPE needs more space */
++#define MAX_CLOSE_WAIT 1000 /* microseconds */
++#define HSS_COUNT 2
++#define MIN_FRAME_SIZE 16 /* bits */
++#define MAX_FRAME_SIZE 257 /* 256 bits + framing bit */
++#define MAX_CHANNELS (MAX_FRAME_SIZE / 8)
++#define MAX_CHAN_DEVICES 32
++#define CHANNEL_HDLC 0xFE
++#define CHANNEL_UNUSED 0xFF
++
++#define NAPI_WEIGHT 16
++#define CHAN_RX_TRIGGER 16 /* 8 RX frames = 1 ms @ E1 */
++#define CHAN_RX_FRAMES 64
++#define MAX_CHAN_RX_BAD_SYNC (CHAN_RX_TRIGGER / 2 /* pairs */ - 3)
++#define CHAN_TX_LIST_FRAMES 16 /* bytes/channel per list, 16 - 48 */
++#define CHAN_TX_LISTS 8
++#define CHAN_TX_FRAMES (CHAN_TX_LIST_FRAMES * CHAN_TX_LISTS)
++#define CHAN_QUEUE_LEN 16 /* minimum possible */
++
++
++/* Queue IDs */
++#define HSS0_CHL_RXTRIG_QUEUE 12 /* orig size = 32 dwords */
++#define HSS0_PKT_RX_QUEUE 13 /* orig size = 32 dwords */
++#define HSS0_PKT_TX0_QUEUE 14 /* orig size = 16 dwords */
++#define HSS0_PKT_TX1_QUEUE 15
++#define HSS0_PKT_TX2_QUEUE 16
++#define HSS0_PKT_TX3_QUEUE 17
++#define HSS0_PKT_RXFREE0_QUEUE 18 /* orig size = 16 dwords */
++#define HSS0_PKT_RXFREE1_QUEUE 19
++#define HSS0_PKT_RXFREE2_QUEUE 20
++#define HSS0_PKT_RXFREE3_QUEUE 21
++#define HSS0_PKT_TXDONE_QUEUE 22 /* orig size = 64 dwords */
++
++#define HSS1_CHL_RXTRIG_QUEUE 10
++#define HSS1_PKT_RX_QUEUE 0
++#define HSS1_PKT_TX0_QUEUE 5
++#define HSS1_PKT_TX1_QUEUE 6
++#define HSS1_PKT_TX2_QUEUE 7
++#define HSS1_PKT_TX3_QUEUE 8
++#define HSS1_PKT_RXFREE0_QUEUE 1
++#define HSS1_PKT_RXFREE1_QUEUE 2
++#define HSS1_PKT_RXFREE2_QUEUE 3
++#define HSS1_PKT_RXFREE3_QUEUE 4
++#define HSS1_PKT_TXDONE_QUEUE 9
++
++#define NPE_PKT_MODE_HDLC 0
++#define NPE_PKT_MODE_RAW 1
++#define NPE_PKT_MODE_56KMODE 2
++#define NPE_PKT_MODE_56KENDIAN_MSB 4
++
++/* PKT_PIPE_HDLC_CFG_WRITE flags */
++#define PKT_HDLC_IDLE_ONES 0x1 /* default = flags */
++#define PKT_HDLC_CRC_32 0x2 /* default = CRC-16 */
++#define PKT_HDLC_MSB_ENDIAN 0x4 /* default = LE */
++
++
++/* hss_config, PCRs */
++/* Frame sync sampling, default = active low */
++#define PCR_FRM_SYNC_ACTIVE_HIGH 0x40000000
++#define PCR_FRM_SYNC_FALLINGEDGE 0x80000000
++#define PCR_FRM_SYNC_RISINGEDGE 0xC0000000
++
++/* Frame sync pin: input (default) or output generated off a given clk edge */
++#define PCR_FRM_SYNC_OUTPUT_FALLING 0x20000000
++#define PCR_FRM_SYNC_OUTPUT_RISING 0x30000000
++
++/* Frame and data clock sampling on edge, default = falling */
++#define PCR_FCLK_EDGE_RISING 0x08000000
++#define PCR_DCLK_EDGE_RISING 0x04000000
++
++/* Clock direction, default = input */
++#define PCR_SYNC_CLK_DIR_OUTPUT 0x02000000
++
++/* Generate/Receive frame pulses, default = enabled */
++#define PCR_FRM_PULSE_DISABLED 0x01000000
++
++ /* Data rate is full (default) or half the configured clk speed */
++#define PCR_HALF_CLK_RATE 0x00200000
++
++/* Invert data between NPE and HSS FIFOs? (default = no) */
++#define PCR_DATA_POLARITY_INVERT 0x00100000
++
++/* TX/RX endianness, default = LSB */
++#define PCR_MSB_ENDIAN 0x00080000
++
++/* Normal (default) / open drain mode (TX only) */
++#define PCR_TX_PINS_OPEN_DRAIN 0x00040000
++
++/* No framing bit transmitted and expected on RX? (default = framing bit) */
++#define PCR_SOF_NO_FBIT 0x00020000
++
++/* Drive data pins? */
++#define PCR_TX_DATA_ENABLE 0x00010000
++
++/* Voice 56k type: drive the data pins low (default), high, high Z */
++#define PCR_TX_V56K_HIGH 0x00002000
++#define PCR_TX_V56K_HIGH_IMP 0x00004000
++
++/* Unassigned type: drive the data pins low (default), high, high Z */
++#define PCR_TX_UNASS_HIGH 0x00000800
++#define PCR_TX_UNASS_HIGH_IMP 0x00001000
++
++/* T1 @ 1.544MHz only: Fbit dictated in FIFO (default) or high Z */
++#define PCR_TX_FB_HIGH_IMP 0x00000400
++
++/* 56k data endiannes - which bit unused: high (default) or low */
++#define PCR_TX_56KE_BIT_0_UNUSED 0x00000200
++
++/* 56k data transmission type: 32/8 bit data (default) or 56K data */
++#define PCR_TX_56KS_56K_DATA 0x00000100
++
++/* hss_config, cCR */
++/* Number of packetized clients, default = 1 */
++#define CCR_NPE_HFIFO_2_HDLC 0x04000000
++#define CCR_NPE_HFIFO_3_OR_4HDLC 0x08000000
++
++/* default = no loopback */
++#define CCR_LOOPBACK 0x02000000
++
++/* HSS number, default = 0 (first) */
++#define CCR_SECOND_HSS 0x01000000
++
++
++/* hss_config, clkCR: main:10, num:10, denom:12 */
++#define CLK42X_SPEED_EXP ((0x3FF << 22) | ( 2 << 12) | 15) /*65 KHz*/
++
++#define CLK42X_SPEED_512KHZ (( 130 << 22) | ( 2 << 12) | 15)
++#define CLK42X_SPEED_1536KHZ (( 43 << 22) | ( 18 << 12) | 47)
++#define CLK42X_SPEED_1544KHZ (( 43 << 22) | ( 33 << 12) | 192)
++#define CLK42X_SPEED_2048KHZ (( 32 << 22) | ( 34 << 12) | 63)
++#define CLK42X_SPEED_4096KHZ (( 16 << 22) | ( 34 << 12) | 127)
++#define CLK42X_SPEED_8192KHZ (( 8 << 22) | ( 34 << 12) | 255)
++
++#define CLK46X_SPEED_512KHZ (( 130 << 22) | ( 24 << 12) | 127)
++#define CLK46X_SPEED_1536KHZ (( 43 << 22) | (152 << 12) | 383)
++#define CLK46X_SPEED_1544KHZ (( 43 << 22) | ( 66 << 12) | 385)
++#define CLK46X_SPEED_2048KHZ (( 32 << 22) | (280 << 12) | 511)
++#define CLK46X_SPEED_4096KHZ (( 16 << 22) | (280 << 12) | 1023)
++#define CLK46X_SPEED_8192KHZ (( 8 << 22) | (280 << 12) | 2047)
++
++
++/* hss_config, LUT entries */
++#define TDMMAP_UNASSIGNED 0
++#define TDMMAP_HDLC 1 /* HDLC - packetized */
++#define TDMMAP_VOICE56K 2 /* Voice56K - 7-bit channelized */
++#define TDMMAP_VOICE64K 3 /* Voice64K - 8-bit channelized */
++
++/* offsets into HSS config */
++#define HSS_CONFIG_TX_PCR 0x00 /* port configuration registers */
++#define HSS_CONFIG_RX_PCR 0x04
++#define HSS_CONFIG_CORE_CR 0x08 /* loopback control, HSS# */
++#define HSS_CONFIG_CLOCK_CR 0x0C /* clock generator control */
++#define HSS_CONFIG_TX_FCR 0x10 /* frame configuration registers */
++#define HSS_CONFIG_RX_FCR 0x14
++#define HSS_CONFIG_TX_LUT 0x18 /* channel look-up tables */
++#define HSS_CONFIG_RX_LUT 0x38
++
++
++/* NPE command codes */
++/* writes the ConfigWord value to the location specified by offset */
++#define PORT_CONFIG_WRITE 0x40
++
++/* triggers the NPE to load the contents of the configuration table */
++#define PORT_CONFIG_LOAD 0x41
++
++/* triggers the NPE to return an HssErrorReadResponse message */
++#define PORT_ERROR_READ 0x42
++
++/* reset NPE internal status and enable the HssChannelized operation */
++#define CHAN_FLOW_ENABLE 0x43
++#define CHAN_FLOW_DISABLE 0x44
++#define CHAN_IDLE_PATTERN_WRITE 0x45
++#define CHAN_NUM_CHANS_WRITE 0x46
++#define CHAN_RX_BUF_ADDR_WRITE 0x47
++#define CHAN_RX_BUF_CFG_WRITE 0x48
++#define CHAN_TX_BLK_CFG_WRITE 0x49
++#define CHAN_TX_BUF_ADDR_WRITE 0x4A
++#define CHAN_TX_BUF_SIZE_WRITE 0x4B
++#define CHAN_TSLOTSWITCH_ENABLE 0x4C
++#define CHAN_TSLOTSWITCH_DISABLE 0x4D
++
++/* downloads the gainWord value for a timeslot switching channel associated
++ with bypassNum */
++#define CHAN_TSLOTSWITCH_GCT_DOWNLOAD 0x4E
++
++/* triggers the NPE to reset internal status and enable the HssPacketized
++ operation for the flow specified by pPipe */
++#define PKT_PIPE_FLOW_ENABLE 0x50
++#define PKT_PIPE_FLOW_DISABLE 0x51
++#define PKT_NUM_PIPES_WRITE 0x52
++#define PKT_PIPE_FIFO_SIZEW_WRITE 0x53
++#define PKT_PIPE_HDLC_CFG_WRITE 0x54
++#define PKT_PIPE_IDLE_PATTERN_WRITE 0x55
++#define PKT_PIPE_RX_SIZE_WRITE 0x56
++#define PKT_PIPE_MODE_WRITE 0x57
++
++/* HDLC packet status values - desc->status */
++#define ERR_SHUTDOWN 1 /* stop or shutdown occurrance */
++#define ERR_HDLC_ALIGN 2 /* HDLC alignment error */
++#define ERR_HDLC_FCS 3 /* HDLC Frame Check Sum error */
++#define ERR_RXFREE_Q_EMPTY 4 /* RX-free queue became empty while receiving
++ this packet (if buf_len < pkt_len) */
++#define ERR_HDLC_TOO_LONG 5 /* HDLC frame size too long */
++#define ERR_HDLC_ABORT 6 /* abort sequence received */
++#define ERR_DISCONNECTING 7 /* disconnect is in progress */
++
++
++enum mode {MODE_HDLC = 0, MODE_RAW, MODE_G704};
++enum error_bit {TX_ERROR_BIT = 0, RX_ERROR_BIT = 1};
++enum alignment { NOT_ALIGNED = 0, EVEN_FIRST, ODD_FIRST };
++
++#ifdef __ARMEB__
++typedef struct sk_buff buffer_t;
++#define free_buffer dev_kfree_skb
++#define free_buffer_irq dev_kfree_skb_irq
++#else
++typedef void buffer_t;
++#define free_buffer kfree
++#define free_buffer_irq kfree
++#endif
++
++struct chan_device {
++ struct cdev cdev;
++ struct device *dev;
++ struct port *port;
++ unsigned int open_count, excl_open;
++ unsigned int tx_first, tx_count, rx_first, rx_count; /* bytes */
++ unsigned long errors_bitmap;
++ u8 id, chan_count;
++ u8 log_channels[MAX_CHANNELS];
++};
++
++struct port {
++ struct device *dev;
++ struct npe *npe;
++ struct net_device *netdev;
++ struct napi_struct napi;
++ struct hss_plat_info *plat;
++ buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
++ struct desc *desc_tab; /* coherent */
++ u32 desc_tab_phys;
++ unsigned int id;
++ atomic_t chan_tx_irq_number, chan_rx_irq_number;
++ wait_queue_head_t chan_tx_waitq, chan_rx_waitq;
++ u8 hdlc_cfg;
++
++ /* the following fields must be protected by npe_lock */
++ enum mode mode;
++ unsigned int clock_type, clock_rate, loopback;
++ unsigned int frame_size, frame_sync_offset;
++
++ struct chan_device *chan_devices[MAX_CHAN_DEVICES];
++ u8 *chan_buf;
++ u32 chan_tx_buf_phys, chan_rx_buf_phys;
++ unsigned int chan_open_count, hdlc_open;
++ unsigned int chan_started, initialized, just_set_offset;
++ enum alignment aligned, carrier;
++ unsigned int chan_last_rx, chan_last_tx;
++ /* assigned channels, may be invalid with given frame length or mode */
++ u8 channels[MAX_CHANNELS];
++ int msg_count;
++};
++
++/* NPE message structure */
++struct msg {
++#ifdef __ARMEB__
++ u8 cmd, unused, hss_port, index;
++ union {
++ struct { u8 data8a, data8b, data8c, data8d; };
++ struct { u16 data16a, data16b; };
++ struct { u32 data32; };
++ };
++#else
++ u8 index, hss_port, unused, cmd;
++ union {
++ struct { u8 data8d, data8c, data8b, data8a; };
++ struct { u16 data16b, data16a; };
++ struct { u32 data32; };
++ };
++#endif
++};
++
++/* HDLC packet descriptor */
++struct desc {
++ u32 next; /* pointer to next buffer, unused */
++
++#ifdef __ARMEB__
++ u16 buf_len; /* buffer length */
++ u16 pkt_len; /* packet length */
++ u32 data; /* pointer to data buffer in RAM */
++ u8 status;
++ u8 error_count;
++ u16 __reserved;
++#else
++ u16 pkt_len; /* packet length */
++ u16 buf_len; /* buffer length */
++ u32 data; /* pointer to data buffer in RAM */
++ u16 __reserved;
++ u8 error_count;
++ u8 status;
++#endif
++ u32 __reserved1[4];
++};
++
++
++#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
++ (n) * sizeof(struct desc))
++#define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
++
++#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
++ ((n) + RX_DESCS) * sizeof(struct desc))
++#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
++
++#define chan_tx_buf_len(port) (port->frame_size / 8 * CHAN_TX_FRAMES)
++#define chan_tx_lists_len(port) (port->frame_size / 8 * CHAN_TX_LISTS * \
++ sizeof(u32))
++#define chan_rx_buf_len(port) (port->frame_size / 8 * CHAN_RX_FRAMES)
++
++#define chan_tx_buf(port) ((port)->chan_buf)
++#define chan_tx_lists(port) (chan_tx_buf(port) + chan_tx_buf_len(port))
++#define chan_rx_buf(port) (chan_tx_lists(port) + chan_tx_lists_len(port))
++
++#define chan_tx_lists_phys(port) ((port)->chan_tx_buf_phys + \
++ chan_tx_buf_len(port))
++
++static int hss_prepare_chan(struct port *port);
++void hss_chan_stop(struct port *port);
++
++/*****************************************************************************
++ * global variables
++ ****************************************************************************/
++
++static struct class *hss_class;
++static int chan_major;
++static int ports_open;
++static struct dma_pool *dma_pool;
++static spinlock_t npe_lock;
++
++static const struct {
++ int tx, txdone, rx, rxfree, chan;
++}queue_ids[2] = {{HSS0_PKT_TX0_QUEUE, HSS0_PKT_TXDONE_QUEUE, HSS0_PKT_RX_QUEUE,
++ HSS0_PKT_RXFREE0_QUEUE, HSS0_CHL_RXTRIG_QUEUE},
++ {HSS1_PKT_TX0_QUEUE, HSS1_PKT_TXDONE_QUEUE, HSS1_PKT_RX_QUEUE,
++ HSS1_PKT_RXFREE0_QUEUE, HSS1_CHL_RXTRIG_QUEUE},
++};
++
++/*****************************************************************************
++ * utility functions
++ ****************************************************************************/
++
++static inline struct port* dev_to_port(struct net_device *dev)
++{
++ return dev_to_hdlc(dev)->priv;
++}
++
++static inline struct chan_device* inode_to_chan_dev(struct inode *inode)
++{
++ return container_of(inode->i_cdev, struct chan_device, cdev);
++}
++
++#ifndef __ARMEB__
++static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
++{
++ int i;
++ for (i = 0; i < cnt; i++)
++ dest[i] = swab32(src[i]);
++}
++#endif
++
++static int get_number(const char **buf, size_t *len, unsigned int *ptr,
++ unsigned int min, unsigned int max)
++{
++ char *endp;
++ unsigned long val = simple_strtoul(*buf, &endp, 10);
++
++ if (endp == *buf || endp - *buf > *len || val < min || val > max)
++ return -EINVAL;
++ *len -= endp - *buf;
++ *buf = endp;
++ *ptr = val;
++ return 0;
++}
++
++static int parse_channels(const char **buf, size_t *len, u8 *channels)
++{
++ unsigned int ch, next = 0;
++
++ if (*len && (*buf)[*len - 1] == '\n')
++ (*len)--;
++
++ memset(channels, 0, MAX_CHANNELS);
++
++ if (!*len)
++ return 0;
++
++ /* Format: "A,B-C,...", A > B > C */
++ while (1) {
++ if (get_number(buf, len, &ch, next, MAX_CHANNELS - 1))
++ return -EINVAL;
++ channels[ch] = 1;
++ next = ch + 1;
++ if (!*len)
++ break;
++ if (**buf == ',') {
++ (*buf)++;
++ (*len)--;
++ continue;
++ }
++ if (**buf != '-')
++ return -EINVAL;
++ (*buf)++;
++ (*len)--;
++ if (get_number(buf, len, &ch, next, MAX_CHANNELS - 1))
++ return -EINVAL;
++ while (next <= ch)
++ channels[next++] = 1;
++ if (!*len)
++ break;
++ if (**buf != ',')
++ return -EINVAL;
++ (*buf)++;
++ (*len)--;
++ }
++ return 1;
++}
++
++static size_t print_channels(struct port *port, char *buf, u8 id)
++{
++ unsigned int ch, cnt = 0;
++ size_t len = 0;
++
++ for (ch = 0; ch < MAX_CHANNELS; ch++)
++ if (port->channels[ch] == id) {
++ if (cnt == 0) {
++ sprintf(buf + len, "%s%u", len ? "," : "", ch);
++ len += strlen(buf + len);
++ }
++ cnt++;
++ } else {
++ if (cnt > 1) {
++ sprintf(buf + len, "-%u", ch - 1);
++ len += strlen(buf + len);
++ }
++ cnt = 0;
++ }
++ if (cnt > 1) {
++ sprintf(buf + len, "-%u", ch - 1);
++ len += strlen(buf + len);
++ }
++
++ buf[len++] = '\n';
++ return len;
++}
++
++static inline unsigned int sub_offset(unsigned int a, unsigned int b,
++ unsigned int modulo)
++{
++ return (modulo /* make sure the result >= 0 */ + a - b) % modulo;
++}
++
++/*****************************************************************************
++ * HSS access
++ ****************************************************************************/
++
++static void hss_config_load(struct port *port)
++{
++ struct msg msg;
++
++ do {
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = PORT_CONFIG_LOAD;
++ msg.hss_port = port->id;
++ if (npe_send_message(port->npe, &msg, "HSS_LOAD_CONFIG"))
++ break;
++ if (npe_recv_message(port->npe, &msg, "HSS_LOAD_CONFIG"))
++ break;
++
++ /* HSS_LOAD_CONFIG for port #1 returns port_id = #4 */
++ if (msg.cmd != PORT_CONFIG_LOAD || msg.data32)
++ break;
++
++ /* HDLC may stop working without this */
++ npe_recv_message(port->npe, &msg, "FLUSH_IT");
++ return;
++ } while (0);
++
++ printk(KERN_CRIT "HSS-%i: unable to reload HSS configuration\n",
++ port->id);
++ BUG();
++}
++
++static void hss_config_set_pcr(struct port *port)
++{
++ struct msg msg;
++
++ do {
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = PORT_CONFIG_WRITE;
++ msg.hss_port = port->id;
++ msg.index = HSS_CONFIG_TX_PCR;
++ msg.data32 = PCR_FRM_SYNC_OUTPUT_RISING | PCR_MSB_ENDIAN |
++ PCR_TX_DATA_ENABLE;
++ if (port->frame_size % 8 == 0)
++ msg.data32 |= PCR_SOF_NO_FBIT;
++ if (port->clock_type == CLOCK_INT)
++ msg.data32 |= PCR_SYNC_CLK_DIR_OUTPUT;
++ if (npe_send_message(port->npe, &msg, "HSS_SET_TX_PCR"))
++ break;
++
++ msg.index = HSS_CONFIG_RX_PCR;
++ msg.data32 ^= PCR_TX_DATA_ENABLE | PCR_DCLK_EDGE_RISING;
++ if (npe_send_message(port->npe, &msg, "HSS_SET_RX_PCR"))
++ break;
++ return;
++ } while (0);
++
++ printk(KERN_CRIT "HSS-%i: unable to set HSS PCR registers\n", port->id);
++ BUG();
++}
++
++static void hss_config_set_hdlc_cfg(struct port *port)
++{
++ struct msg msg;
++
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = PKT_PIPE_HDLC_CFG_WRITE;
++ msg.hss_port = port->id;
++ msg.data8a = port->hdlc_cfg; /* rx_cfg */
++ msg.data8b = port->hdlc_cfg | (PKT_EXTRA_FLAGS << 3); /* tx_cfg */
++ if (npe_send_message(port->npe, &msg, "HSS_SET_HDLC_CFG")) {
++ printk(KERN_CRIT "HSS-%i: unable to set HSS HDLC"
++ " configuration\n", port->id);
++ BUG();
++ }
++}
++
++static void hss_config_set_core(struct port *port)
++{
++ struct msg msg;
++
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = PORT_CONFIG_WRITE;
++ msg.hss_port = port->id;
++ msg.index = HSS_CONFIG_CORE_CR;
++ msg.data32 = (port->loopback ? CCR_LOOPBACK : 0) |
++ (port->id ? CCR_SECOND_HSS : 0);
++ if (npe_send_message(port->npe, &msg, "HSS_SET_CORE_CR")) {
++ printk(KERN_CRIT "HSS-%i: unable to set HSS core control"
++ " register\n", port->id);
++ BUG();
++ }
++}
++
++static void hss_config_set_line(struct port *port)
++{
++ struct msg msg;
++
++ hss_config_set_pcr(port);
++ hss_config_set_core(port);
++
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = PORT_CONFIG_WRITE;
++ msg.hss_port = port->id;
++ msg.index = HSS_CONFIG_CLOCK_CR;
++ msg.data32 = CLK42X_SPEED_2048KHZ /* FIXME */;
++ if (npe_send_message(port->npe, &msg, "HSS_SET_CLOCK_CR")) {
++ printk(KERN_CRIT "HSS-%i: unable to set HSS clock control"
++ " register\n", port->id);
++ BUG();
++ }
++}
++
++static void hss_config_set_rx_frame(struct port *port)
++{
++ struct msg msg;
++
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = PORT_CONFIG_WRITE;
++ msg.hss_port = port->id;
++ msg.index = HSS_CONFIG_RX_FCR;
++ msg.data16a = port->frame_sync_offset;
++ msg.data16b = port->frame_size - 1;
++ if (npe_send_message(port->npe, &msg, "HSS_SET_RX_FCR")) {
++ printk(KERN_CRIT "HSS-%i: unable to set HSS RX frame size"
++ " and offset\n", port->id);
++ BUG();
++ }
++}
++
++static void hss_config_set_frame(struct port *port)
++{
++ struct msg msg;
++
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = PORT_CONFIG_WRITE;
++ msg.hss_port = port->id;
++ msg.index = HSS_CONFIG_TX_FCR;
++ msg.data16a = TX_FRAME_SYNC_OFFSET;
++ msg.data16b = port->frame_size - 1;
++ if (npe_send_message(port->npe, &msg, "HSS_SET_TX_FCR")) {
++ printk(KERN_CRIT "HSS-%i: unable to set HSS TX frame size"
++ " and offset\n", port->id);
++ BUG();
++ }
++ hss_config_set_rx_frame(port);
++}
++
++static void hss_config_set_lut(struct port *port)
++{
++ struct msg msg;
++ int chan_count = 0, log_chan = 0, i, ch;
++ u32 lut[MAX_CHANNELS / 4];
++
++ memset(lut, 0, sizeof(lut));
++ for (i = 0; i < MAX_CHAN_DEVICES; i++)
++ if (port->chan_devices[i])
++ port->chan_devices[i]->chan_count = 0;
++
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = PORT_CONFIG_WRITE;
++ msg.hss_port = port->id;
++
++ for (ch = 0; ch < MAX_CHANNELS; ch++) {
++ struct chan_device *chdev = NULL;
++ unsigned int entry;
++
++ if (port->channels[ch] < MAX_CHAN_DEVICES /* assigned */)
++ chdev = port->chan_devices[port->channels[ch]];
++
++ if (port->mode == MODE_G704 && ch == 0)
++ entry = TDMMAP_VOICE64K; /* PCM-31 pattern */
++ else if (port->mode == MODE_HDLC ||
++ port->channels[ch] == CHANNEL_HDLC)
++ entry = TDMMAP_HDLC;
++ else if (chdev && chdev->open_count) {
++ entry = TDMMAP_VOICE64K;
++ chdev->log_channels[chdev->chan_count++] = log_chan;
++ } else
++ entry = TDMMAP_UNASSIGNED;
++ if (entry == TDMMAP_VOICE64K) {
++ chan_count++;
++ log_chan++;
++ }
++
++ msg.data32 >>= 2;
++ msg.data32 |= entry << 30;
++
++ if (ch % 16 == 15) {
++ msg.index = HSS_CONFIG_TX_LUT + ((ch / 4) & ~3);
++ if (npe_send_message(port->npe, &msg, "HSS_SET_TX_LUT"))
++ break;
++
++ msg.index += HSS_CONFIG_RX_LUT - HSS_CONFIG_TX_LUT;
++ if (npe_send_message(port->npe, &msg, "HSS_SET_RX_LUT"))
++ break;
++ }
++ }
++ if (ch != MAX_CHANNELS) {
++ printk(KERN_CRIT "HSS-%i: unable to set HSS channel look-up"
++ " table\n", port->id);
++ BUG();
++ }
++
++ hss_config_set_frame(port);
++
++ if (!chan_count)
++ return;
++
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = CHAN_NUM_CHANS_WRITE;
++ msg.hss_port = port->id;
++ msg.data8a = chan_count;
++ if (npe_send_message(port->npe, &msg, "CHAN_NUM_CHANS_WRITE")) {
++ printk(KERN_CRIT "HSS-%i: unable to set HSS channel count\n",
++ port->id);
++ BUG();
++ }
++
++ /* don't leak data */
++ // FIXME memset(chan_tx_buf(port), 0, CHAN_TX_FRAMES * chan_count);
++ if (port->mode == MODE_G704) /* G.704 PCM-31 sync pattern */
++ for (i = 0; i < CHAN_TX_FRAMES; i += 4)
++ *(u32*)(chan_tx_buf(port) + i) = 0x9BDF9BDF;
++
++ for (i = 0; i < CHAN_TX_LISTS; i++) {
++ u32 phys = port->chan_tx_buf_phys + i * CHAN_TX_LIST_FRAMES;
++ u32 *list = ((u32 *)chan_tx_lists(port)) + i * chan_count;
++ for (ch = 0; ch < chan_count; ch++)
++ list[ch] = phys + ch * CHAN_TX_FRAMES;
++ }
++ dma_sync_single(port->dev, port->chan_tx_buf_phys,
++ chan_tx_buf_len(port) + chan_tx_lists_len(port),
++ DMA_TO_DEVICE);
++}
++
++static u32 hss_config_get_status(struct port *port)
++{
++ struct msg msg;
++
++ do {
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = PORT_ERROR_READ;
++ msg.hss_port = port->id;
++ if (npe_send_message(port->npe, &msg, "PORT_ERROR_READ"))
++ break;
++ if (npe_recv_message(port->npe, &msg, "PORT_ERROR_READ"))
++ break;
++
++ return msg.data32;
++ } while (0);
++
++ printk(KERN_CRIT "HSS-%i: unable to read HSS status\n", port->id);
++ BUG();
++}
++
++static void hss_config_start_chan(struct port *port)
++{
++ struct msg msg;
++
++ port->chan_last_tx = 0;
++ port->chan_last_rx = 0;
++
++ do {
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = CHAN_RX_BUF_ADDR_WRITE;
++ msg.hss_port = port->id;
++ msg.data32 = port->chan_rx_buf_phys;
++ if (npe_send_message(port->npe, &msg, "CHAN_RX_BUF_ADDR_WRITE"))
++ break;
++
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = CHAN_TX_BUF_ADDR_WRITE;
++ msg.hss_port = port->id;
++ msg.data32 = chan_tx_lists_phys(port);
++ if (npe_send_message(port->npe, &msg, "CHAN_TX_BUF_ADDR_WRITE"))
++ break;
++
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = CHAN_FLOW_ENABLE;
++ msg.hss_port = port->id;
++ if (npe_send_message(port->npe, &msg, "CHAN_FLOW_ENABLE"))
++ break;
++ port->chan_started = 1;
++ return;
++ } while (0);
++
++ printk(KERN_CRIT "HSS-%i: unable to start channelized flow\n",
++ port->id);
++ BUG();
++}
++
++static void hss_config_stop_chan(struct port *port)
++{
++ struct msg msg;
++
++ if (!port->chan_started)
++ return;
++
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = CHAN_FLOW_DISABLE;
++ msg.hss_port = port->id;
++ if (npe_send_message(port->npe, &msg, "CHAN_FLOW_DISABLE")) {
++ printk(KERN_CRIT "HSS-%i: unable to stop channelized flow\n",
++ port->id);
++ BUG();
++ }
++ hss_config_get_status(port); /* make sure it's halted */
++}
++
++static void hss_config_start_hdlc(struct port *port)
++{
++ struct msg msg;
++
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = PKT_PIPE_FLOW_ENABLE;
++ msg.hss_port = port->id;
++ msg.data32 = 0;
++ if (npe_send_message(port->npe, &msg, "HSS_ENABLE_PKT_PIPE")) {
++ printk(KERN_CRIT "HSS-%i: unable to stop packetized flow\n",
++ port->id);
++ BUG();
++ }
++}
++
++static void hss_config_stop_hdlc(struct port *port)
++{
++ struct msg msg;
++
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = PKT_PIPE_FLOW_DISABLE;
++ msg.hss_port = port->id;
++ if (npe_send_message(port->npe, &msg, "HSS_DISABLE_PKT_PIPE")) {
++ printk(KERN_CRIT "HSS-%i: unable to stop packetized flow\n",
++ port->id);
++ BUG();
++ }
++ hss_config_get_status(port); /* make sure it's halted */
++}
++
++static int hss_config_load_firmware(struct port *port)
++{
++ struct msg msg;
++
++ if (port->initialized)
++ return 0;
++
++ if (!npe_running(port->npe)) {
++ int err;
++ if ((err = npe_load_firmware(port->npe, npe_name(port->npe),
++ port->dev)))
++ return err;
++ }
++
++ do {
++ /* HSS main configuration */
++ hss_config_set_line(port);
++
++ hss_config_set_frame(port);
++
++ /* HDLC mode configuration */
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = PKT_NUM_PIPES_WRITE;
++ msg.hss_port = port->id;
++ msg.data8a = PKT_NUM_PIPES;
++ if (npe_send_message(port->npe, &msg, "HSS_SET_PKT_PIPES"))
++ break;
++
++ msg.cmd = PKT_PIPE_FIFO_SIZEW_WRITE;
++ msg.data8a = PKT_PIPE_FIFO_SIZEW;
++ if (npe_send_message(port->npe, &msg, "HSS_SET_PKT_FIFO"))
++ break;
++
++ msg.cmd = PKT_PIPE_MODE_WRITE;
++ msg.data8a = NPE_PKT_MODE_HDLC;
++ /* msg.data8b = inv_mask */
++ /* msg.data8c = or_mask */
++ if (npe_send_message(port->npe, &msg, "HSS_SET_PKT_MODE"))
++ break;
++
++ msg.cmd = PKT_PIPE_RX_SIZE_WRITE;
++ msg.data16a = HDLC_MAX_MRU; /* including CRC */
++ if (npe_send_message(port->npe, &msg, "HSS_SET_PKT_RX_SIZE"))
++ break;
++
++ msg.cmd = PKT_PIPE_IDLE_PATTERN_WRITE;
++ msg.data32 = 0x7F7F7F7F; /* ??? FIXME */
++ if (npe_send_message(port->npe, &msg, "HSS_SET_PKT_IDLE"))
++ break;
++
++ /* Channelized operation settings */
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = CHAN_TX_BLK_CFG_WRITE;
++ msg.hss_port = port->id;
++ msg.data8b = (CHAN_TX_LIST_FRAMES & ~7) / 2;
++ msg.data8a = msg.data8b / 4;
++ msg.data8d = CHAN_TX_LIST_FRAMES - msg.data8b;
++ msg.data8c = msg.data8d / 4;
++ if (npe_send_message(port->npe, &msg, "CHAN_TX_BLK_CFG_WRITE"))
++ break;
++
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = CHAN_RX_BUF_CFG_WRITE;
++ msg.hss_port = port->id;
++ msg.data8a = CHAN_RX_TRIGGER / 8;
++ msg.data8b = CHAN_RX_FRAMES;
++ if (npe_send_message(port->npe, &msg, "CHAN_RX_BUF_CFG_WRITE"))
++ break;
++
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = CHAN_TX_BUF_SIZE_WRITE;
++ msg.hss_port = port->id;
++ msg.data8a = CHAN_TX_LISTS;
++ if (npe_send_message(port->npe, &msg, "CHAN_TX_BUF_SIZE_WRITE"))
++ break;
++
++ port->initialized = 1;
++ return 0;
++ } while (0);
++
++ printk(KERN_CRIT "HSS-%i: unable to start HSS operation\n", port->id);
++ BUG();
++}
++
++/*****************************************************************************
++ * packetized (HDLC) operation
++ ****************************************************************************/
++
++static inline void debug_pkt(struct net_device *dev, const char *func,
++ u8 *data, int len)
++{
++#if DEBUG_PKT_BYTES
++ int i;
++
++ printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len);
++ for (i = 0; i < len; i++) {
++ if (i >= DEBUG_PKT_BYTES)
++ break;
++ printk(KERN_DEBUG "%s%02X", !(i % 4) ? " " : "", data[i]);
++ }
++ printk(KERN_DEBUG "\n");
++#endif
++}
++
++
++static inline void debug_desc(u32 phys, struct desc *desc)
++{
++#if DEBUG_DESC
++ printk(KERN_DEBUG "%X: %X %3X %3X %08X %X %X\n",
++ phys, desc->next, desc->buf_len, desc->pkt_len,
++ desc->data, desc->status, desc->error_count);
++#endif
++}
++
++static inline void debug_queue(unsigned int queue, int is_get, u32 phys)
++{
++#if DEBUG_QUEUES
++ static struct {
++ int queue;
++ char *name;
++ } names[] = {
++ { HSS0_PKT_TX0_QUEUE, "TX#0 " },
++ { HSS0_PKT_TXDONE_QUEUE, "TX-done#0 " },
++ { HSS0_PKT_RX_QUEUE, "RX#0 " },
++ { HSS0_PKT_RXFREE0_QUEUE, "RX-free#0 " },
++ { HSS1_PKT_TX0_QUEUE, "TX#1 " },
++ { HSS1_PKT_TXDONE_QUEUE, "TX-done#1 " },
++ { HSS1_PKT_RX_QUEUE, "RX#1 " },
++ { HSS1_PKT_RXFREE0_QUEUE, "RX-free#1 " },
++ };
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(names); i++)
++ if (names[i].queue == queue)
++ break;
++
++ printk(KERN_DEBUG "Queue %i %s%s %X\n", queue,
++ i < ARRAY_SIZE(names) ? names[i].name : "",
++ is_get ? "->" : "<-", phys);
++#endif
++}
++
++static inline u32 queue_get_entry(unsigned int queue)
++{
++ u32 phys = qmgr_get_entry(queue);
++ debug_queue(queue, 1, phys);
++ return phys;
++}
++
++static inline int queue_get_desc(unsigned int queue, struct port *port,
++ int is_tx)
++{
++ u32 phys, tab_phys, n_desc;
++ struct desc *tab;
++
++ if (!(phys = queue_get_entry(queue)))
++ return -1;
++
++ BUG_ON(phys & 0x1F);
++ tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
++ tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
++ n_desc = (phys - tab_phys) / sizeof(struct desc);
++ BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
++ debug_desc(phys, &tab[n_desc]);
++ BUG_ON(tab[n_desc].next);
++ return n_desc;
++}
++
++static inline void queue_put_desc(unsigned int queue, u32 phys,
++ struct desc *desc)
++{
++ debug_queue(queue, 0, phys);
++ debug_desc(phys, desc);
++ BUG_ON(phys & 0x1F);
++ qmgr_put_entry(queue, phys);
++ BUG_ON(qmgr_stat_overflow(queue));
++}
++
++
++static inline void dma_unmap_tx(struct port *port, struct desc *desc)
++{
++#ifdef __ARMEB__
++ dma_unmap_single(&port->netdev->dev, desc->data,
++ desc->buf_len, DMA_TO_DEVICE);
++#else
++ dma_unmap_single(&port->netdev->dev, desc->data & ~3,
++ ALIGN((desc->data & 3) + desc->buf_len, 4),
++ DMA_TO_DEVICE);
++#endif
++}
++
++
++static void hss_hdlc_set_carrier(void *pdev, int carrier)
++{
++ struct net_device *netdev = pdev;
++ struct port *port = dev_to_port(netdev);
++ unsigned long flags;
++
++ spin_lock_irqsave(&npe_lock, flags);
++ port->carrier = carrier;
++ if (!port->loopback) {
++ if (carrier)
++ netif_carrier_on(netdev);
++ else
++ netif_carrier_off(netdev);
++ }
++ spin_unlock_irqrestore(&npe_lock, flags);
++}
++
++static void hss_hdlc_rx_irq(void *pdev)
++{
++ struct net_device *dev = pdev;
++ struct port *port = dev_to_port(dev);
++
++#if DEBUG_RX
++ printk(KERN_DEBUG "%s: hss_hdlc_rx_irq\n", dev->name);
++#endif
++ qmgr_disable_irq(queue_ids[port->id].rx);
++ netif_rx_schedule(dev, &port->napi);
++}
++
++static int hss_hdlc_poll(struct napi_struct *napi, int budget)
++{
++ struct port *port = container_of(napi, struct port, napi);
++ struct net_device *dev = port->netdev;
++ unsigned int rxq = queue_ids[port->id].rx;
++ unsigned int rxfreeq = queue_ids[port->id].rxfree;
++ struct net_device_stats *stats = hdlc_stats(dev);
++ int received = 0;
++
++#if DEBUG_RX
++ printk(KERN_DEBUG "%s: hss_hdlc_poll\n", dev->name);
++#endif
++
++ while (received < budget) {
++ struct sk_buff *skb;
++ struct desc *desc;
++ int n;
++#ifdef __ARMEB__
++ struct sk_buff *temp;
++ u32 phys;
++#endif
++
++ if ((n = queue_get_desc(rxq, port, 0)) < 0) {
++ received = 0; /* No packet received */
++#if DEBUG_RX
++ printk(KERN_DEBUG "%s: hss_hdlc_poll"
++ " netif_rx_complete\n", dev->name);
++#endif
++ netif_rx_complete(dev, napi);
++ qmgr_enable_irq(rxq);
++ if (!qmgr_stat_empty(rxq) &&
++ netif_rx_reschedule(dev, napi)) {
++#if DEBUG_RX
++ printk(KERN_DEBUG "%s: hss_hdlc_poll"
++ " netif_rx_reschedule succeeded\n",
++ dev->name);
++#endif
++ qmgr_disable_irq(rxq);
++ continue;
++ }
++#if DEBUG_RX
++ printk(KERN_DEBUG "%s: hss_hdlc_poll all done\n",
++ dev->name);
++#endif
++ return 0; /* all work done */
++ }
++
++ desc = rx_desc_ptr(port, n);
++#if 0 /* FIXME - error_count counts modulo 256, perhaps we should use it */
++ if (desc->error_count)
++ printk(KERN_DEBUG "%s: hss_hdlc_poll status 0x%02X"
++ " errors %u\n", dev->name, desc->status,
++ desc->error_count);
++#endif
++ skb = NULL;
++ switch (desc->status) {
++ case 0:
++#ifdef __ARMEB__
++ if ((skb = netdev_alloc_skb(dev, RX_SIZE)) != NULL) {
++ phys = dma_map_single(&dev->dev, skb->data,
++ RX_SIZE,
++ DMA_FROM_DEVICE);
++ if (dma_mapping_error(phys)) {
++ dev_kfree_skb(skb);
++ skb = NULL;
++ }
++ }
++#else
++ skb = netdev_alloc_skb(dev, desc->pkt_len);
++#endif
++ if (!skb)
++ stats->rx_dropped++;
++ break;
++ case ERR_HDLC_ALIGN:
++ case ERR_HDLC_ABORT:
++ stats->rx_frame_errors++;
++ stats->rx_errors++;
++ break;
++ case ERR_HDLC_FCS:
++ stats->rx_crc_errors++;
++ stats->rx_errors++;
++ break;
++ case ERR_HDLC_TOO_LONG:
++ stats->rx_length_errors++;
++ stats->rx_errors++;
++ break;
++ default: /* FIXME - remove printk */
++ printk(KERN_ERR "%s: hss_hdlc_poll: status 0x%02X"
++ " errors %u\n", dev->name, desc->status,
++ desc->error_count);
++ stats->rx_errors++;
++ }
++
++ if (!skb) {
++ /* put the desc back on RX-ready queue */
++ desc->buf_len = RX_SIZE;
++ desc->pkt_len = desc->status = 0;
++ queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
++ continue;
++ }
++
++ /* process received frame */
++#ifdef __ARMEB__
++ temp = skb;
++ skb = port->rx_buff_tab[n];
++ dma_unmap_single(&dev->dev, desc->data,
++ RX_SIZE, DMA_FROM_DEVICE);
++#else
++ dma_sync_single(&dev->dev, desc->data,
++ RX_SIZE, DMA_FROM_DEVICE);
++ memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
++ ALIGN(desc->pkt_len, 4) / 4);
++#endif
++ skb_put(skb, desc->pkt_len);
++
++ debug_pkt(dev, "hss_hdlc_poll", skb->data, skb->len);
++
++ skb->protocol = hdlc_type_trans(skb, dev);
++ dev->last_rx = jiffies;
++ stats->rx_packets++;
++ stats->rx_bytes += skb->len;
++ netif_receive_skb(skb);
++
++ /* put the new buffer on RX-free queue */
++#ifdef __ARMEB__
++ port->rx_buff_tab[n] = temp;
++ desc->data = phys;
++#endif
++ desc->buf_len = RX_SIZE;
++ desc->pkt_len = 0;
++ queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
++ received++;
++ }
++#if DEBUG_RX
++ printk(KERN_DEBUG "hss_hdlc_poll: end, not all work done\n");
++#endif
++ return received; /* not all work done */
++}
++
++
++static void hss_hdlc_txdone_irq(void *pdev)
++{
++ struct net_device *dev = pdev;
++ struct port *port = dev_to_port(dev);
++ struct net_device_stats *stats = hdlc_stats(dev);
++ int n_desc;
++
++#if DEBUG_TX
++ printk(KERN_DEBUG DRV_NAME ": hss_hdlc_txdone_irq\n");
++#endif
++ while ((n_desc = queue_get_desc(queue_ids[port->id].txdone,
++ port, 1)) >= 0) {
++ struct desc *desc;
++ int start;
++
++ desc = tx_desc_ptr(port, n_desc);
++
++ stats->tx_packets++;
++ stats->tx_bytes += desc->pkt_len;
++
++ dma_unmap_tx(port, desc);
++#if DEBUG_TX
++ printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq free %p\n",
++ dev->name, port->tx_buff_tab[n_desc]);
++#endif
++ free_buffer_irq(port->tx_buff_tab[n_desc]);
++ port->tx_buff_tab[n_desc] = NULL;
++
++ start = qmgr_stat_empty(port->plat->txreadyq);
++ queue_put_desc(port->plat->txreadyq,
++ tx_desc_phys(port, n_desc), desc);
++ if (start) {
++#if DEBUG_TX
++ printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq xmit"
++ " ready\n", dev->name);
++#endif
++ netif_wake_queue(dev);
++ }
++ }
++}
++
++static int hss_hdlc_xmit(struct sk_buff *skb, struct net_device *dev)
++{
++ struct port *port = dev_to_port(dev);
++ struct net_device_stats *stats = hdlc_stats(dev);
++ unsigned int txreadyq = port->plat->txreadyq;
++ int len, offset, bytes, n;
++ void *mem;
++ u32 phys;
++ struct desc *desc;
++
++#if DEBUG_TX
++ printk(KERN_DEBUG "%s: hss_hdlc_xmit\n", dev->name);
++#endif
++
++ if (unlikely(skb->len > HDLC_MAX_MRU)) {
++ dev_kfree_skb(skb);
++ stats->tx_errors++;
++ return NETDEV_TX_OK;
++ }
++
++ debug_pkt(dev, "hss_hdlc_xmit", skb->data, skb->len);
++
++ len = skb->len;
++#ifdef __ARMEB__
++ offset = 0; /* no need to keep alignment */
++ bytes = len;
++ mem = skb->data;
++#else
++ offset = (int)skb->data & 3; /* keep 32-bit alignment */
++ bytes = ALIGN(offset + len, 4);
++ if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
++ dev_kfree_skb(skb);
++ stats->tx_dropped++;
++ return NETDEV_TX_OK;
++ }
++ memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
++ dev_kfree_skb(skb);
++#endif
++
++ phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
++ if (dma_mapping_error(phys)) {
++#ifdef __ARMEB__
++ dev_kfree_skb(skb);
++#else
++ kfree(mem);
++#endif
++ stats->tx_dropped++;
++ return NETDEV_TX_OK;
++ }
++
++ n = queue_get_desc(txreadyq, port, 1);
++ BUG_ON(n < 0);
++ desc = tx_desc_ptr(port, n);
++
++#ifdef __ARMEB__
++ port->tx_buff_tab[n] = skb;
++#else
++ port->tx_buff_tab[n] = mem;
++#endif
++ desc->data = phys + offset;
++ desc->buf_len = desc->pkt_len = len;
++
++ wmb();
++ queue_put_desc(queue_ids[port->id].tx, tx_desc_phys(port, n), desc);
++ dev->trans_start = jiffies;
++
++ if (qmgr_stat_empty(txreadyq)) {
++#if DEBUG_TX
++ printk(KERN_DEBUG "%s: hss_hdlc_xmit queue full\n", dev->name);
++#endif
++ netif_stop_queue(dev);
++ /* we could miss TX ready interrupt */
++ if (!qmgr_stat_empty(txreadyq)) {
++#if DEBUG_TX
++ printk(KERN_DEBUG "%s: hss_hdlc_xmit ready again\n",
++ dev->name);
++#endif
++ netif_wake_queue(dev);
++ }
++ }
++
++#if DEBUG_TX
++ printk(KERN_DEBUG "%s: hss_hdlc_xmit end\n", dev->name);
++#endif
++ return NETDEV_TX_OK;
++}
++
++
++static int request_hdlc_queues(struct port *port)
++{
++ int err;
++
++ err = qmgr_request_queue(queue_ids[port->id].rxfree, RX_DESCS, 0, 0);
++ if (err)
++ return err;
++
++ err = qmgr_request_queue(queue_ids[port->id].rx, RX_DESCS, 0, 0);
++ if (err)
++ goto rel_rxfree;
++
++ err = qmgr_request_queue(queue_ids[port->id].tx, TX_DESCS, 0, 0);
++ if (err)
++ goto rel_rx;
++
++ err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0);
++ if (err)
++ goto rel_tx;
++
++ err = qmgr_request_queue(queue_ids[port->id].txdone, TX_DESCS, 0, 0);
++ if (err)
++ goto rel_txready;
++ return 0;
++
++rel_txready:
++ qmgr_release_queue(port->plat->txreadyq);
++rel_tx:
++ qmgr_release_queue(queue_ids[port->id].tx);
++rel_rx:
++ qmgr_release_queue(queue_ids[port->id].rx);
++rel_rxfree:
++ qmgr_release_queue(queue_ids[port->id].rxfree);
++ printk(KERN_DEBUG "%s: unable to request hardware queues\n",
++ port->netdev->name);
++ return err;
++}
++
++static void release_hdlc_queues(struct port *port)
++{
++ qmgr_release_queue(queue_ids[port->id].rxfree);
++ qmgr_release_queue(queue_ids[port->id].rx);
++ qmgr_release_queue(queue_ids[port->id].txdone);
++ qmgr_release_queue(queue_ids[port->id].tx);
++ qmgr_release_queue(port->plat->txreadyq);
++}
++
++static int init_hdlc_queues(struct port *port)
++{
++ int i;
++
++ if (!ports_open)
++ if (!(dma_pool = dma_pool_create(DRV_NAME, NULL,
++ POOL_ALLOC_SIZE, 32, 0)))
++ return -ENOMEM;
++
++ if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
++ &port->desc_tab_phys)))
++ return -ENOMEM;
++ memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
++ memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
++ memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
++
++ /* Setup RX buffers */
++ for (i = 0; i < RX_DESCS; i++) {
++ struct desc *desc = rx_desc_ptr(port, i);
++ buffer_t *buff;
++ void *data;
++#ifdef __ARMEB__
++ if (!(buff = netdev_alloc_skb(port->netdev, RX_SIZE)))
++ return -ENOMEM;
++ data = buff->data;
++#else
++ if (!(buff = kmalloc(RX_SIZE, GFP_KERNEL)))
++ return -ENOMEM;
++ data = buff;
++#endif
++ desc->buf_len = RX_SIZE;
++ desc->data = dma_map_single(&port->netdev->dev, data,
++ RX_SIZE, DMA_FROM_DEVICE);
++ if (dma_mapping_error(desc->data)) {
++ free_buffer(buff);
++ return -EIO;
++ }
++ port->rx_buff_tab[i] = buff;
++ }
++
++ return 0;
++}
++
++static void destroy_hdlc_queues(struct port *port)
++{
++ int i;
++
++ if (port->desc_tab) {
++ for (i = 0; i < RX_DESCS; i++) {
++ struct desc *desc = rx_desc_ptr(port, i);
++ buffer_t *buff = port->rx_buff_tab[i];
++ if (buff) {
++ dma_unmap_single(&port->netdev->dev,
++ desc->data, RX_SIZE,
++ DMA_FROM_DEVICE);
++ free_buffer(buff);
++ }
++ }
++ for (i = 0; i < TX_DESCS; i++) {
++ struct desc *desc = tx_desc_ptr(port, i);
++ buffer_t *buff = port->tx_buff_tab[i];
++ if (buff) {
++ dma_unmap_tx(port, desc);
++ free_buffer(buff);
++ }
++ }
++ dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
++ port->desc_tab = NULL;
++ }
++
++ if (!ports_open && dma_pool) {
++ dma_pool_destroy(dma_pool);
++ dma_pool = NULL;
++ }
++}
++
++static int hss_hdlc_open(struct net_device *dev)
++{
++ struct port *port = dev_to_port(dev);
++ unsigned long flags;
++ int i, err = 0;
++
++ if ((err = hdlc_open(dev)))
++ return err;
++
++ if ((err = request_hdlc_queues(port)))
++ goto err_hdlc_close;
++
++ if ((err = init_hdlc_queues(port)))
++ goto err_destroy_queues;
++
++ spin_lock_irqsave(&npe_lock, flags);
++
++ if (port->mode == MODE_G704 && port->channels[0] == CHANNEL_HDLC) {
++ err = -EBUSY; /* channel #0 is used for G.704 framing */
++ goto err_unlock;
++ }
++ if (port->mode != MODE_HDLC)
++ for (i = port->frame_size / 8; i < MAX_CHANNELS; i++)
++ if (port->channels[i] == CHANNEL_HDLC) {
++ err = -ECHRNG; /* frame too short */
++ goto err_unlock;
++ }
++
++ if ((err = hss_config_load_firmware(port)))
++ goto err_unlock;
++
++ if (!port->chan_open_count && port->plat->open)
++ if ((err = port->plat->open(port->id, dev,
++ hss_hdlc_set_carrier)))
++ goto err_unlock;
++
++ if (port->mode == MODE_G704 && !port->chan_open_count)
++ if ((err = hss_prepare_chan(port)))
++ goto err_plat_close;
++
++ spin_unlock_irqrestore(&npe_lock, flags);
++
++ /* Populate queues with buffers, no failure after this point */
++ for (i = 0; i < TX_DESCS; i++)
++ queue_put_desc(port->plat->txreadyq,
++ tx_desc_phys(port, i), tx_desc_ptr(port, i));
++
++ for (i = 0; i < RX_DESCS; i++)
++ queue_put_desc(queue_ids[port->id].rxfree,
++ rx_desc_phys(port, i), rx_desc_ptr(port, i));
++
++ napi_enable(&port->napi);
++ netif_start_queue(dev);
++
++ qmgr_set_irq(queue_ids[port->id].rx, QUEUE_IRQ_SRC_NOT_EMPTY,
++ hss_hdlc_rx_irq, dev);
++
++ qmgr_set_irq(queue_ids[port->id].txdone, QUEUE_IRQ_SRC_NOT_EMPTY,
++ hss_hdlc_txdone_irq, dev);
++ qmgr_enable_irq(queue_ids[port->id].txdone);
++
++ ports_open++;
++ port->hdlc_open = 1;
++
++ hss_config_set_hdlc_cfg(port);
++ hss_config_set_lut(port);
++ hss_config_load(port);
++
++ if (port->mode == MODE_G704 && !port->chan_open_count)
++ hss_config_start_chan(port);
++
++ hss_config_start_hdlc(port);
++
++ /* we may already have RX data, enables IRQ */
++ netif_rx_schedule(dev, &port->napi);
++ return 0;
++
++err_plat_close:
++ if (!port->chan_open_count && port->plat->close)
++ port->plat->close(port->id, dev);
++err_unlock:
++ spin_unlock_irqrestore(&npe_lock, flags);
++err_destroy_queues:
++ destroy_hdlc_queues(port);
++ release_hdlc_queues(port);
++err_hdlc_close:
++ hdlc_close(dev);
++ return err;
++}
++
++static int hss_hdlc_close(struct net_device *dev)
++{
++ struct port *port = dev_to_port(dev);
++ unsigned long flags;
++ int i, buffs = RX_DESCS; /* allocated RX buffers */
++
++ spin_lock_irqsave(&npe_lock, flags);
++ ports_open--;
++ port->hdlc_open = 0;
++ qmgr_disable_irq(queue_ids[port->id].rx);
++ netif_stop_queue(dev);
++ napi_disable(&port->napi);
++
++ hss_config_stop_hdlc(port);
++
++ if (port->mode == MODE_G704 && !port->chan_open_count)
++ hss_chan_stop(port);
++
++ while (queue_get_desc(queue_ids[port->id].rxfree, port, 0) >= 0)
++ buffs--;
++ while (queue_get_desc(queue_ids[port->id].rx, port, 0) >= 0)
++ buffs--;
++
++ if (buffs)
++ printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)"
++ " left in NPE\n", dev->name, buffs);
++
++ buffs = TX_DESCS;
++ while (queue_get_desc(queue_ids[port->id].tx, port, 1) >= 0)
++ buffs--; /* cancel TX */
++
++ i = 0;
++ do {
++ while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
++ buffs--;
++ if (!buffs)
++ break;
++ } while (++i < MAX_CLOSE_WAIT);
++
++ if (buffs)
++ printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) "
++ "left in NPE\n", dev->name, buffs);
++#if DEBUG_CLOSE
++ if (!buffs)
++ printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
++#endif
++ qmgr_disable_irq(queue_ids[port->id].txdone);
++
++ if (!port->chan_open_count && port->plat->close)
++ port->plat->close(port->id, dev);
++ spin_unlock_irqrestore(&npe_lock, flags);
++
++ destroy_hdlc_queues(port);
++ release_hdlc_queues(port);
++ hdlc_close(dev);
++ return 0;
++}
++
++
++static int hss_hdlc_attach(struct net_device *dev, unsigned short encoding,
++ unsigned short parity)
++{
++ struct port *port = dev_to_port(dev);
++
++ if (encoding != ENCODING_NRZ)
++ return -EINVAL;
++
++ switch(parity) {
++ case PARITY_CRC16_PR1_CCITT:
++ port->hdlc_cfg = 0;
++ return 0;
++
++ case PARITY_CRC32_PR1_CCITT:
++ port->hdlc_cfg = PKT_HDLC_CRC_32;
++ return 0;
++
++ default:
++ return -EINVAL;
++ }
++}
++
++
++static int hss_hdlc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
++{
++ const size_t size = sizeof(sync_serial_settings);
++ sync_serial_settings new_line;
++ sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
++ struct port *port = dev_to_port(dev);
++ unsigned long flags;
++ int i, clk;
++
++ if (cmd != SIOCWANDEV)
++ return hdlc_ioctl(dev, ifr, cmd);
++
++ switch(ifr->ifr_settings.type) {
++ case IF_GET_IFACE:
++ ifr->ifr_settings.type = IF_IFACE_V35;
++ if (ifr->ifr_settings.size < size) {
++ ifr->ifr_settings.size = size; /* data size wanted */
++ return -ENOBUFS;
++ }
++ memset(&new_line, 0, sizeof(new_line));
++ new_line.clock_type = port->clock_type;
++ new_line.clock_rate = port->clock_rate;
++ new_line.loopback = port->loopback;
++ if (copy_to_user(line, &new_line, size))
++ return -EFAULT;
++
++ if (!port->chan_buf)
++ return 0;
++
++ dma_sync_single(&dev->dev, port->chan_rx_buf_phys,
++ chan_rx_buf_len(port), DMA_FROM_DEVICE);
++ printk(KERN_DEBUG "RX:\n");
++ for (i = 0; i < chan_rx_buf_len(port); i++) {
++ if (i % 32 == 0)
++ printk(KERN_DEBUG "%03X ", i);
++ printk("%02X%c", chan_rx_buf(port)[i],
++ (i + 1) % 32 ? ' ' : '\n');
++ }
++
++#if 0
++ printk(KERN_DEBUG "TX:\n");
++ for (i = 0; i < /*CHAN_TX_FRAMES * 2*/ chan_tx_buf_len(port)
++ + chan_tx_lists_len(port); i++) {
++ if (i % 32 == 0)
++ printk(KERN_DEBUG "%03X ", i);
++ printk("%02X%c", chan_tx_buf(port)[i],
++ (i + 1) % 32 ? ' ' : '\n');
++ }
++#endif
++ port->msg_count = 10;
++ return 0;
++
++ case IF_IFACE_SYNC_SERIAL:
++ case IF_IFACE_V35:
++ if(!capable(CAP_NET_ADMIN))
++ return -EPERM;
++ if (copy_from_user(&new_line, line, size))
++ return -EFAULT;
++
++ clk = new_line.clock_type;
++ if (port->plat->set_clock)
++ clk = port->plat->set_clock(port->id, clk);
++
++ if (clk != CLOCK_EXT && clk != CLOCK_INT)
++ return -EINVAL; /* No such clock setting */
++
++ if (new_line.loopback != 0 && new_line.loopback != 1)
++ return -EINVAL;
++
++ port->clock_type = clk; /* Update settings */
++ /* FIXME port->clock_rate = new_line.clock_rate */;
++ port->loopback = new_line.loopback;
++
++ spin_lock_irqsave(&npe_lock, flags);
++
++ if (port->chan_open_count || port->hdlc_open) {
++ hss_config_set_line(port);
++ hss_config_load(port);
++ }
++ if (port->loopback || port->carrier)
++ netif_carrier_on(port->netdev);
++ else
++ netif_carrier_off(port->netdev);
++ spin_unlock_irqrestore(&npe_lock, flags);
++
++ return 0;
++
++ default:
++ return hdlc_ioctl(dev, ifr, cmd);
++ }
++}
++
++/*****************************************************************************
++ * channelized (G.704) operation
++ ****************************************************************************/
++
++static void g704_rx_framer(struct port *port, unsigned int offset)
++{
++ u8 *data = chan_rx_buf(port) + sub_offset(offset, CHAN_RX_TRIGGER,
++ CHAN_RX_FRAMES);
++ unsigned int bit, frame, bad_even = 0, bad_odd = 0, cnt;
++ unsigned int is_first = port->just_set_offset;
++ u8 zeros_even, zeros_odd, ones_even, ones_odd;
++ enum alignment aligned;
++
++ port->just_set_offset = 0;
++ dma_sync_single(port->dev, port->chan_rx_buf_phys, CHAN_RX_FRAMES,
++ DMA_FROM_DEVICE);
++
++ /* check if aligned first */
++ for (frame = 0; frame < CHAN_RX_TRIGGER &&
++ (bad_even <= MAX_CHAN_RX_BAD_SYNC ||
++ bad_odd <= MAX_CHAN_RX_BAD_SYNC); frame += 2) {
++ u8 ve = data[frame];
++ u8 vo = data[frame + 1];
++
++ if ((ve & 0x7F) != 0x1B || !(vo & 0x40))
++ bad_even++;
++
++ if ((vo & 0x7F) != 0x1B || !(ve & 0x40))
++ bad_odd++;
++ }
++
++ if (bad_even <= MAX_CHAN_RX_BAD_SYNC)
++ aligned = EVEN_FIRST;
++ else if (bad_odd <= MAX_CHAN_RX_BAD_SYNC)
++ aligned = ODD_FIRST;
++ else
++ aligned = NOT_ALIGNED;
++
++ if (aligned != NOT_ALIGNED) {
++ if (aligned == port->aligned)
++ return; /* no change */
++ if (printk_ratelimit())
++ printk(KERN_INFO "HSS-%i: synchronized at %u (%s frame"
++ " first)\n", port->id, port->frame_sync_offset,
++ aligned == EVEN_FIRST ? "even" : "odd");
++ port->aligned = aligned;
++
++ atomic_inc(&port->chan_tx_irq_number);
++ wake_up_interruptible(&port->chan_tx_waitq);
++ atomic_inc(&port->chan_rx_irq_number);
++ wake_up_interruptible(&port->chan_rx_waitq);
++ return;
++ }
++
++ /* not aligned */
++ if (port->aligned != NOT_ALIGNED && printk_ratelimit()) {
++ printk(KERN_INFO "HSS-%i: lost alignment\n", port->id);
++ port->aligned = NOT_ALIGNED;
++#if DEBUG_FRAMER
++ for (cnt = 0; cnt < CHAN_RX_FRAMES; cnt++)
++ printk("%c%02X%s", cnt == offset ? '>' : ' ',
++ chan_rx_buf(port)[cnt],
++ (cnt + 1) % 32 ? "" : "\n");
++#endif
++
++ for (cnt = 0; cnt < MAX_CHAN_DEVICES; cnt++)
++ if (port->chan_devices[cnt]) {
++ set_bit(TX_ERROR_BIT, &port->chan_devices[cnt]
++ ->errors_bitmap);
++ set_bit(RX_ERROR_BIT, &port->chan_devices[cnt]
++ ->errors_bitmap);
++ }
++ atomic_inc(&port->chan_tx_irq_number);
++ wake_up_interruptible(&port->chan_tx_waitq);
++ atomic_inc(&port->chan_rx_irq_number);
++ wake_up_interruptible(&port->chan_rx_waitq);
++ }
++
++ if (is_first)
++ return;
++
++ zeros_even = zeros_odd = 0;
++ ones_even = ones_odd = 0xFF;
++ for (frame = 0; frame < CHAN_RX_TRIGGER; frame += 2) {
++ zeros_even |= data[frame];
++ zeros_odd |= data[frame + 1];
++ ones_even &= data[frame];
++ ones_odd &= data[frame + 1];
++ }
++
++ for (bit = 0; bit < 7; bit++) {
++ if ((zeros_even & ~0x9B) == 0 && (ones_even & 0x1B) == 0x1B &&
++ (ones_odd & 0x40) == 0x40) {
++ aligned = EVEN_FIRST; /* maybe */
++ break;
++ }
++ if ((zeros_odd & ~0x9B) == 0 && (ones_odd & 0x1B) == 0x1B &&
++ (ones_even & 0x40) == 0x40) {
++ aligned = ODD_FIRST; /* maybe */
++ break;
++ }
++ zeros_even <<= 1;
++ ones_even = ones_even << 1 | 1;
++ zeros_odd <<= 1;
++ ones_odd = ones_odd << 1 | 1;
++ }
++
++ port->frame_sync_offset += port->frame_size - bit;
++ port->frame_sync_offset %= port->frame_size;
++ port->just_set_offset = 1;
++
++#if DEBUG_FRAMER
++ if (bit == 7)
++ printk(KERN_DEBUG "HSS-%i: trying frame sync at %u\n",
++ port->id, port->frame_sync_offset);
++ else
++ printk(KERN_DEBUG "HSS-%i: found possible frame sync pattern at"
++ " %u (%s frame first)\n", port->id,
++ port->frame_sync_offset,
++ aligned == EVEN_FIRST ? "even" : "odd");
++#endif
++
++ hss_config_set_rx_frame(port);
++ hss_config_load(port);
++}
++
++static void chan_process_tx_irq(struct chan_device *chan_dev, int offset)
++{
++ /* in bytes */
++ unsigned int buff_len = CHAN_TX_FRAMES * chan_dev->chan_count;
++ unsigned int list_len = CHAN_TX_LIST_FRAMES * chan_dev->chan_count;
++ int eaten, last_offset = chan_dev->port->chan_last_tx * list_len;
++
++ offset *= list_len;
++ eaten = sub_offset(offset, last_offset, buff_len);
++
++ if (chan_dev->tx_count > eaten + 2 * list_len) {
++ /* two pages must be reserved for the transmitter */
++ chan_dev->tx_first += eaten;
++ chan_dev->tx_first %= buff_len;
++ chan_dev->tx_count -= eaten;
++ } else {
++ /* FIXME check
++ 0
++ 1 tx_first (may still be transmited)
++ 2 tx_offset (currently reported by the NPE)
++ 3 tx_first + 2 * list_len (free to write here)
++ 4
++ 5
++ */
++
++ /* printk(KERN_DEBUG "TX buffer underflow\n"); */
++ chan_dev->tx_first = sub_offset(offset, list_len, buff_len);
++ chan_dev->tx_count = 2 * list_len; /* reserve */
++ set_bit(TX_ERROR_BIT, &chan_dev->errors_bitmap);
++ }
++}
++
++static void chan_process_rx_irq(struct chan_device *chan_dev, int offset)
++{
++ /* in bytes */
++ unsigned int buff_len = CHAN_RX_FRAMES * chan_dev->chan_count;
++ unsigned int trig_len = CHAN_RX_TRIGGER * chan_dev->chan_count;
++ int last_offset = chan_dev->port->chan_last_rx * chan_dev->chan_count;
++
++ offset *= chan_dev->chan_count;
++ chan_dev->rx_count += sub_offset(offset, last_offset + trig_len,
++ buff_len) + trig_len;
++ if (chan_dev->rx_count > buff_len - 2 * trig_len) {
++ /* two pages - offset[0] and offset[1] are lost - FIXME check */
++ /* printk(KERN_DEBUG "RX buffer overflow\n"); */
++ chan_dev->rx_first = (offset + 2 * trig_len) % buff_len;
++ chan_dev->rx_count = buff_len - 2 * trig_len;
++ set_bit(RX_ERROR_BIT, &chan_dev->errors_bitmap);
++ }
++}
++
++static void hss_chan_irq(void *pdev)
++{
++ struct port *port = pdev;
++ u32 v;
++
++#if DEBUG_RX
++ printk(KERN_DEBUG DRV_NAME ": hss_chan_irq\n");
++#endif
++ spin_lock(&npe_lock);
++ while ((v = qmgr_get_entry(queue_ids[port->id].chan))) {
++ unsigned int first, errors, tx_list, rx_frame;
++ int i, bad;
++
++ first = v >> 24;
++ errors = (v >> 16) & 0xFF;
++ tx_list = (v >> 8) & 0xFF;
++ rx_frame = v & 0xFF;
++
++ if (port->msg_count) {
++ printk(KERN_DEBUG "chan_irq hss %i jiffies %lu first"
++ " 0x%02X errors 0x%02X tx_list 0x%02X rx_frame"
++ " 0x%02X\n", port->id, jiffies, first, errors,
++ tx_list, rx_frame);
++ port->msg_count--;
++ }
++
++ BUG_ON(rx_frame % CHAN_RX_TRIGGER);
++ BUG_ON(rx_frame >= CHAN_RX_FRAMES);
++ BUG_ON(tx_list >= CHAN_TX_LISTS);
++
++ bad = port->mode == MODE_G704 && port->aligned == NOT_ALIGNED;
++ if (!bad && tx_list != port->chan_last_tx) {
++ if (tx_list != (port->chan_last_tx + 1) % CHAN_TX_LISTS)
++ printk(KERN_DEBUG "Skipped an IRQ? Tx last %i"
++ " current %i\n", port->chan_last_tx,
++ tx_list);
++ for (i = 0; i < MAX_CHAN_DEVICES; i++) {
++ if (!port->chan_devices[i] ||
++ !port->chan_devices[i]->open_count)
++ continue;
++ chan_process_tx_irq(port->chan_devices[i],
++ tx_list);
++ }
++ atomic_inc(&port->chan_tx_irq_number);
++#if 0
++ printk(KERN_DEBUG "wakeing up TX jiff %lu\n",
++ jiffies, errors);
++#endif
++ wake_up_interruptible(&port->chan_tx_waitq);
++ }
++
++ if (rx_frame != (port->chan_last_rx + CHAN_RX_TRIGGER) %
++ CHAN_RX_FRAMES)
++ printk(KERN_DEBUG "Skipped an IRQ? Rx last %i"
++ " current %i\n", port->chan_last_rx, rx_frame);
++
++ if (port->mode == MODE_G704)
++ g704_rx_framer(port, rx_frame);
++
++ if (!bad &&
++ (port->mode != MODE_G704 || port->aligned != NOT_ALIGNED)) {
++ for (i = 0; i < MAX_CHAN_DEVICES; i++) {
++ if (!port->chan_devices[i] ||
++ !port->chan_devices[i]->open_count)
++ continue;
++ chan_process_rx_irq(port->chan_devices[i],
++ rx_frame);
++ }
++ atomic_inc(&port->chan_rx_irq_number);
++ wake_up_interruptible(&port->chan_rx_waitq);
++ }
++ port->chan_last_tx = tx_list;
++ port->chan_last_rx = rx_frame;
++ }
++ spin_unlock(&npe_lock);
++}
++
++
++static int hss_prepare_chan(struct port *port)
++{
++ int err;
++
++ if ((err = hss_config_load_firmware(port)))
++ return err;
++
++ if ((err = qmgr_request_queue(queue_ids[port->id].chan,
++ CHAN_QUEUE_LEN, 0, 0)))
++ return err;
++
++ if (!(port->chan_buf = kmalloc(chan_tx_buf_len(port) +
++ chan_tx_lists_len(port) +
++ chan_rx_buf_len(port), GFP_KERNEL))) {
++ goto release_queue;
++ err = -ENOBUFS;
++ }
++
++ port->chan_tx_buf_phys = dma_map_single(port->dev, chan_tx_buf(port),
++ chan_tx_buf_len(port) +
++ chan_tx_lists_len(port),
++ DMA_TO_DEVICE);
++ if (dma_mapping_error(port->chan_tx_buf_phys)) {
++ err = -EIO;
++ goto free;
++ }
++
++ port->chan_rx_buf_phys = dma_map_single(port->dev, chan_rx_buf(port),
++ chan_rx_buf_len(port),
++ DMA_FROM_DEVICE);
++ if (dma_mapping_error(port->chan_rx_buf_phys)) {
++ err = -EIO;
++ goto unmap_tx;
++ }
++
++ qmgr_set_irq(queue_ids[port->id].chan, QUEUE_IRQ_SRC_NOT_EMPTY,
++ hss_chan_irq, port);
++ qmgr_enable_irq(queue_ids[port->id].chan);
++ hss_chan_irq(port);
++ return 0;
++
++unmap_tx:
++ dma_unmap_single(port->dev, port->chan_tx_buf_phys,
++ chan_tx_buf_len(port) + chan_tx_lists_len(port),
++ DMA_TO_DEVICE);
++free:
++ kfree(port->chan_buf);
++ port->chan_buf = NULL;
++release_queue:
++ qmgr_release_queue(queue_ids[port->id].chan);
++ return err;
++}
++
++void hss_chan_stop(struct port *port)
++{
++ if (!port->chan_open_count && !port->hdlc_open)
++ qmgr_disable_irq(queue_ids[port->id].chan);
++
++ hss_config_stop_chan(port);
++ hss_config_set_lut(port);
++ hss_config_load(port);
++
++ if (!port->chan_open_count && !port->hdlc_open) {
++ dma_unmap_single(port->dev, port->chan_tx_buf_phys,
++ chan_tx_buf_len(port) +
++ chan_tx_lists_len(port), DMA_TO_DEVICE);
++ dma_unmap_single(port->dev, port->chan_rx_buf_phys,
++ chan_rx_buf_len(port), DMA_FROM_DEVICE);
++ kfree(port->chan_buf);
++ port->chan_buf = NULL;
++ qmgr_release_queue(queue_ids[port->id].chan);
++ }
++}
++
++static int hss_chan_open(struct inode *inode, struct file *file)
++{
++ struct chan_device *chan_dev = inode_to_chan_dev(inode);
++ struct port *port = chan_dev->port;
++ unsigned long flags;
++ int i, err = 0;
++
++ spin_lock_irqsave(&npe_lock, flags);
++
++ if (chan_dev->open_count) {
++ if (chan_dev->excl_open || (file->f_flags & O_EXCL))
++ err = -EBUSY;
++ else
++ chan_dev->open_count++;
++ goto out;
++ }
++
++ if (port->mode == MODE_HDLC) {
++ err = -ENOSYS;
++ goto out;
++ }
++
++ if (port->mode == MODE_G704 && port->channels[0] == chan_dev->id) {
++ err = -EBUSY; /* channel #0 is used for G.704 signaling */
++ goto out;
++ }
++ for (i = MAX_CHANNELS; i > port->frame_size / 8; i--)
++ if (port->channels[i - 1] == chan_dev->id) {
++ err = -ECHRNG; /* frame too short */
++ goto out;
++ }
++
++ chan_dev->rx_first = chan_dev->tx_first = 0;
++ chan_dev->rx_count = chan_dev->tx_count = 0;
++ clear_bit(TX_ERROR_BIT, &chan_dev->errors_bitmap);
++ clear_bit(RX_ERROR_BIT, &chan_dev->errors_bitmap);
++
++ if (!port->chan_open_count && !port->hdlc_open) {
++ if (port->plat->open)
++ if ((err = port->plat->open(port->id, port->netdev,
++ hss_hdlc_set_carrier)))
++ goto out;
++ if ((err = hss_prepare_chan(port))) {
++ if (port->plat->close)
++ port->plat->close(port->id, port->netdev);
++ goto out;
++ }
++ }
++
++ hss_config_stop_chan(port);
++ chan_dev->open_count++;
++ port->chan_open_count++;
++ chan_dev->excl_open = !!file->f_flags & O_EXCL;
++
++ hss_config_set_lut(port);
++ hss_config_load(port);
++ hss_config_start_chan(port);
++out:
++ spin_unlock_irqrestore(&npe_lock, flags);
++ return err;
++}
++
++static int hss_chan_release(struct inode *inode, struct file *file)
++{
++ struct chan_device *chan_dev = inode_to_chan_dev(inode);
++ struct port *port = chan_dev->port;
++ unsigned long flags;
++
++ spin_lock_irqsave(&npe_lock, flags);
++
++ if (!--chan_dev->open_count) {
++ if (!--port->chan_open_count && !port->hdlc_open) {
++ hss_chan_stop(port);
++ if (port->plat->close)
++ port->plat->close(port->id, port->netdev);
++ } else {
++ hss_config_stop_chan(port);
++ hss_config_set_lut(port);
++ hss_config_set_line(port); //
++ hss_config_start_chan(port);
++ }
++ }
++
++ spin_unlock_irqrestore(&npe_lock, flags);
++ return 0;
++}
++
++static ssize_t hss_chan_read(struct file *file, char __user *buf, size_t count,
++ loff_t *f_pos)
++{
++ struct chan_device *chan_dev = inode_to_chan_dev
++ (file->f_path.dentry->d_inode);
++ struct port *port = chan_dev->port;
++ unsigned long flags;
++ u8 *rx_buf;
++ int res = 0, loops = 0;
++
++ spin_lock_irqsave(&npe_lock, flags);
++
++ while (1) {
++ int prev_irq = atomic_read(&port->chan_rx_irq_number);
++#if 0
++ if (test_and_clear_bit(RX_ERROR_BIT, &chan_dev->errors_bitmap)
++ || (port->mode == G704 && port->aligned == NOT_ALIGNED)) {
++ res = -EIO;
++ goto out;
++ }
++#endif
++ if (count == 0)
++ goto out; /* no need to wait */
++
++ if (chan_dev->rx_count)
++ break;
++
++ spin_unlock_irqrestore(&npe_lock, flags);
++ loops++;
++ if ((res = wait_event_interruptible
++ (port->chan_rx_waitq,
++ atomic_read(&port->chan_rx_irq_number) != prev_irq)))
++ goto out;
++ spin_lock_irqsave(&npe_lock, flags);
++ continue;
++ }
++
++ dma_sync_single(port->dev, port->chan_rx_buf_phys,
++ chan_rx_buf_len(port), DMA_FROM_DEVICE);
++
++#if 0
++ if (loops > 1)
++ printk(KERN_DEBUG "ENTRY rx_first %u rx_count %u count %i"
++ " last_rx %u loops %i\n", chan_dev->rx_first,
++ chan_dev->rx_count, count, port->chan_last_rx, loops);
++#endif
++ rx_buf = chan_rx_buf(port);
++ while (chan_dev->rx_count > 0 && res < count) {
++ unsigned int chan = chan_dev->rx_first % chan_dev->chan_count;
++ unsigned int frame = chan_dev->rx_first / chan_dev->chan_count;
++
++ chan = chan_dev->log_channels[chan];
++ if (put_user(rx_buf[chan * CHAN_RX_FRAMES + frame], buf++)) {
++ res = -EFAULT;
++ goto out;
++ }
++ chan_dev->rx_first++;
++ chan_dev->rx_first %= CHAN_RX_FRAMES * chan_dev->chan_count;
++ chan_dev->rx_count--;
++ res++;
++ }
++out:
++#if 0
++ printk(KERN_DEBUG "EXIT rx_first %u rx_count %u res %i\n",
++ chan_dev->rx_first, chan_dev->rx_count, res);
++#endif
++ spin_unlock_irqrestore(&npe_lock, flags);
++ return res;
++}
++
++static ssize_t hss_chan_write(struct file *file, const char __user *buf,
++ size_t count, loff_t *f_pos)
++{
++ struct chan_device *chan_dev = inode_to_chan_dev
++ (file->f_path.dentry->d_inode);
++ struct port *port = chan_dev->port;
++ unsigned long flags;
++ u8 *tx_buf;
++ int res = 0, loops = 0;
++
++ spin_lock_irqsave(&npe_lock, flags);
++ while (1) {
++ int prev_irq = atomic_read(&port->chan_tx_irq_number);
++#if 0
++ if (test_and_clear_bit(TX_ERROR_BIT, &chan_dev->errors_bitmap)
++ || (port->mode == G704 && port->aligned == NOT_ALIGNED)) {
++ res = -EIO;
++ goto out;
++ }
++#endif
++ if (count == 0)
++ goto out; /* no need to wait */
++
++ if (chan_dev->tx_count < CHAN_TX_FRAMES * chan_dev->chan_count)
++ break;
++
++ spin_unlock_irqrestore(&npe_lock, flags);
++ loops++;
++ if ((res = wait_event_interruptible
++ (port->chan_tx_waitq,
++ atomic_read (&port->chan_tx_irq_number) != prev_irq)))
++ goto out;
++ spin_lock_irqsave(&npe_lock, flags);
++ continue;
++ }
++
++#if 0
++ if (loops > 1)
++ printk(KERN_DEBUG "ENTRY TX_first %u tx_count %u count %i"
++ " last_tx %u loops %i\n", chan_dev->tx_first,
++ chan_dev->tx_count, count, port->chan_last_tx, loops);
++#endif
++ tx_buf = chan_tx_buf(port);
++ while (chan_dev->tx_count < CHAN_TX_FRAMES * chan_dev->chan_count &&
++ res < count) {
++ unsigned int tail, chan, frame;
++
++ tail = (chan_dev->tx_first + chan_dev->tx_count) %
++ (CHAN_TX_FRAMES * chan_dev->chan_count);
++ chan = tail % chan_dev->chan_count;
++ frame = tail / chan_dev->chan_count;
++ chan = chan_dev->log_channels[chan];
++
++ if (get_user(tx_buf[chan * CHAN_TX_FRAMES + frame], buf++)) {
++ printk(KERN_DEBUG "BUG? TX %u %u %u\n",
++ tail, chan, frame);
++ res = -EFAULT;
++ goto out_sync;
++ }
++ chan_dev->tx_count++;
++ res++;
++ }
++out_sync:
++ dma_sync_single(port->dev, port->chan_tx_buf_phys,
++ chan_tx_buf_len(port), DMA_TO_DEVICE);
++out:
++#if 0
++ printk(KERN_DEBUG "EXIT TX_first %u tx_count %u res %i\n",
++ chan_dev->tx_first, chan_dev->tx_count, res);
++#endif
++ spin_unlock_irqrestore(&npe_lock, flags);
++ return res;
++}
++
++
++static unsigned int hss_chan_poll(struct file *file, poll_table *wait)
++{
++ struct chan_device *chan_dev = inode_to_chan_dev
++ (file->f_path.dentry->d_inode);
++ struct port *port = chan_dev->port;
++ unsigned long flags;
++ unsigned int mask = 0;
++
++ spin_lock_irqsave(&npe_lock, flags);
++ poll_wait(file, &port->chan_tx_waitq, wait);
++ poll_wait(file, &port->chan_rx_waitq, wait);
++
++ if (chan_dev->tx_count < CHAN_TX_FRAMES * chan_dev->chan_count)
++ mask |= POLLOUT | POLLWRNORM;
++ if (chan_dev->rx_count)
++ mask |= POLLIN | POLLRDNORM;
++ spin_unlock_irqrestore(&npe_lock, flags);
++ return mask;
++}
++
++/*****************************************************************************
++ * channelized device sysfs attributes
++ ****************************************************************************/
++
++static ssize_t chan_show_chan(struct device *dev, struct device_attribute *attr,
++ char *buf)
++{
++ struct chan_device *chan_dev = dev_get_drvdata(dev);
++
++ return print_channels(chan_dev->port, buf, chan_dev->id);
++}
++
++static ssize_t chan_set_chan(struct device *dev, struct device_attribute *attr,
++ const char *buf, size_t len)
++{
++ struct chan_device *chan_dev = dev_get_drvdata(dev);
++ struct port *port = chan_dev->port;
++ unsigned long flags;
++ unsigned int ch;
++ size_t orig_len = len;
++ int err;
++
++ if (len && buf[len - 1] == '\n')
++ len--;
++
++ if (len != 7 || memcmp(buf, "destroy", 7))
++ return -EINVAL;
++
++ spin_lock_irqsave(&npe_lock, flags);
++ cdev_del(&chan_dev->cdev);
++
++ for (ch = 0; ch < MAX_CHANNELS; ch++)
++ if (port->channels[ch] == chan_dev->id)
++ port->channels[ch] = CHANNEL_UNUSED;
++ port->chan_devices[chan_dev->id] = NULL;
++ kfree(chan_dev);
++ spin_unlock_irqrestore(&npe_lock, flags);
++
++ if ((err = device_schedule_callback(dev, device_unregister)))
++ return err;
++ return orig_len;
++}
++
++static struct device_attribute chan_attr =
++ __ATTR(channels, 0644, chan_show_chan, chan_set_chan);
++
++/*****************************************************************************
++ * main sysfs attributes
++ ****************************************************************************/
++
++static const struct file_operations chan_fops = {
++ .owner = THIS_MODULE,
++ .llseek = no_llseek,
++ .read = hss_chan_read,
++ .write = hss_chan_write,
++ .poll = hss_chan_poll,
++ .open = hss_chan_open,
++ .release = hss_chan_release,
++};
++
++static ssize_t create_chan(struct device *dev, struct device_attribute *attr,
++ const char *buf, size_t len)
++{
++ struct port *port = dev_get_drvdata(dev);
++ struct chan_device *chan_dev;
++ u8 channels[MAX_CHANNELS];
++ size_t orig_len = len;
++ unsigned long flags;
++ unsigned int ch, id;
++ int minor, err;
++
++ if ((err = parse_channels(&buf, &len, channels)) < 1)
++ return err;
++
++ if (!(chan_dev = kzalloc(sizeof(struct chan_device), GFP_KERNEL)))
++ return -ENOBUFS;
++
++ spin_lock_irqsave(&npe_lock, flags);
++
++ if (port->mode != MODE_RAW && port->mode != MODE_G704) {
++ err = -EINVAL;
++ goto free;
++ }
++
++ for (ch = 0; ch < MAX_CHANNELS; ch++)
++ if (channels[ch] && port->channels[ch] != CHANNEL_UNUSED) {
++ printk(KERN_DEBUG "Channel #%i already in use\n", ch);
++ err = -EBUSY;
++ goto free;
++ }
++
++ for (id = 0; id < MAX_CHAN_DEVICES; id++)
++ if (port->chan_devices[id] == NULL)
++ break;
++
++ if (id == MAX_CHAN_DEVICES) {
++ err = -EBUSY;
++ goto free;
++ }
++
++ for (ch = 0; ch < MAX_CHANNELS; ch++)
++ if (channels[ch])
++ break;
++
++ minor = port->id * MAX_CHAN_DEVICES + ch;
++ chan_dev->id = id;
++ chan_dev->port = port;
++ chan_dev->dev = device_create(hss_class, dev, MKDEV(chan_major, minor),
++ "hss%uch%u", port->id, ch);
++ if (IS_ERR(chan_dev->dev)) {
++ err = PTR_ERR(chan_dev->dev);
++ goto free;
++ }
++
++ cdev_init(&chan_dev->cdev, &chan_fops);
++ chan_dev->cdev.owner = THIS_MODULE;
++ if ((err = cdev_add(&chan_dev->cdev, MKDEV(chan_major, minor), 1)))
++ goto destroy_device;
++
++ for (ch = 0; ch < MAX_CHANNELS; ch++)
++ if (channels[ch])
++ port->channels[ch] = id;
++ port->chan_devices[id] = chan_dev;
++ dev_set_drvdata(chan_dev->dev, chan_dev);
++ BUG_ON(device_create_file(chan_dev->dev, &chan_attr));
++
++ spin_unlock_irqrestore(&npe_lock, flags);
++ return orig_len;
++
++destroy_device:
++ device_unregister(chan_dev->dev);
++free:
++ kfree(chan_dev);
++ spin_unlock_irqrestore(&npe_lock, flags);
++ return err;
++}
++
++static ssize_t show_hdlc_chan(struct device *dev, struct device_attribute *attr,
++ char *buf)
++{
++ return print_channels(dev_get_drvdata(dev), buf, CHANNEL_HDLC);
++}
++
++static ssize_t set_hdlc_chan(struct device *dev, struct device_attribute *attr,
++ const char *buf, size_t len)
++{
++ struct port *port = dev_get_drvdata(dev);
++ u8 channels[MAX_CHANNELS];
++ size_t orig_len = len;
++ unsigned long flags;
++ unsigned int ch;
++ int err;
++
++ if ((err = parse_channels(&buf, &len, channels)) < 0)
++ return err;
++
++ spin_lock_irqsave(&npe_lock, flags);
++
++ if (port->mode != MODE_RAW && port->mode != MODE_G704) {
++ err = -EINVAL;
++ goto err;
++ }
++
++ for (ch = 0; ch < MAX_CHANNELS; ch++)
++ if (channels[ch] &&
++ port->channels[ch] != CHANNEL_UNUSED &&
++ port->channels[ch] != CHANNEL_HDLC) {
++ printk(KERN_DEBUG "Channel #%i already in use\n", ch);
++ err = -EBUSY;
++ goto err;
++ }
++
++ for (ch = 0; ch < MAX_CHANNELS; ch++)
++ if (channels[ch])
++ port->channels[ch] = CHANNEL_HDLC;
++ else if (port->channels[ch] == CHANNEL_HDLC)
++ port->channels[ch] = CHANNEL_UNUSED;
++
++ if (port->chan_open_count || port->hdlc_open) {
++ hss_config_set_lut(port);
++ hss_config_load(port);
++ }
++
++ spin_unlock_irqrestore(&npe_lock, flags);
++ return orig_len;
++
++err:
++ spin_unlock_irqrestore(&npe_lock, flags);
++ return err;
++}
++
++static ssize_t show_clock_type(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct port *port = dev_get_drvdata(dev);
++
++ strcpy(buf, port->clock_type == CLOCK_INT ? "int\n" : "ext\n");
++ return 5;
++}
++
++static ssize_t set_clock_type(struct device *dev, struct device_attribute *attr,
++ const char *buf, size_t len)
++{
++ struct port *port = dev_get_drvdata(dev);
++ size_t orig_len = len;
++ unsigned long flags;
++ unsigned int clk, err;
++
++ if (len && buf[len - 1] == '\n')
++ len--;
++
++ if (len != 3)
++ return -EINVAL;
++ if (!memcmp(buf, "ext", 3))
++ clk = CLOCK_EXT;
++ else if (!memcmp(buf, "int", 3))
++ clk = CLOCK_INT;
++ else
++ return -EINVAL;
++
++ spin_lock_irqsave(&npe_lock, flags);
++ if (port->plat->set_clock)
++ clk = port->plat->set_clock(port->id, clk);
++ if (clk != CLOCK_EXT && clk != CLOCK_INT) {
++ err = -EINVAL; /* plat->set_clock shouldn't change the state */
++ goto err;
++ }
++ port->clock_type = clk;
++ if (port->chan_open_count || port->hdlc_open) {
++ hss_config_set_line(port);
++ hss_config_load(port);
++ }
++ spin_unlock_irqrestore(&npe_lock, flags);
++
++ return orig_len;
++err:
++ spin_unlock_irqrestore(&npe_lock, flags);
++ return err;
++}
++
++static ssize_t show_clock_rate(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct port *port = dev_get_drvdata(dev);
++
++ sprintf(buf, "%u\n", port->clock_rate);
++ return strlen(buf) + 1;
++}
++
++static ssize_t set_clock_rate(struct device *dev, struct device_attribute *attr,
++ const char *buf, size_t len)
++{
++#if 0
++ struct port *port = dev_get_drvdata(dev);
++ size_t orig_len = len;
++ unsigned long flags;
++ unsigned int rate;
++
++ if (len && buf[len - 1] == '\n')
++ len--;
++
++ if (get_number(&buf, &len, &rate, 1, 0xFFFFFFFFu))
++ return -EINVAL;
++ if (len)
++ return -EINVAL;
++
++ spin_lock_irqsave(&npe_lock, flags);
++ port->clock_rate = rate;
++ spin_unlock_irqrestore(&npe_lock, flags);
++ return orig_len;
++#endif
++ return -EINVAL; /* FIXME not yet supported */
++}
++
++static ssize_t show_frame_size(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct port *port = dev_get_drvdata(dev);
++
++ if (port->mode != MODE_RAW && port->mode != MODE_G704)
++ return -EINVAL;
++
++ sprintf(buf, "%u\n", port->frame_size);
++ return strlen(buf) + 1;
++}
++
++static ssize_t set_frame_size(struct device *dev, struct device_attribute *attr,
++ const char *buf, size_t len)
++{
++ struct port *port = dev_get_drvdata(dev);
++ size_t ret = len;
++ unsigned long flags;
++ unsigned int size;
++
++ if (len && buf[len - 1] == '\n')
++ len--;
++
++ if (get_number(&buf, &len, &size, MIN_FRAME_SIZE, MAX_FRAME_SIZE))
++ return -EINVAL;
++ if (len || size % 8 > 1)
++ return -EINVAL;
++
++ spin_lock_irqsave(&npe_lock, flags);
++ if (port->mode != MODE_RAW && port->mode != MODE_G704)
++ ret = -EINVAL;
++ else if (!port->chan_open_count && !port->hdlc_open)
++ ret = -EBUSY;
++ else {
++ port->frame_size = size;
++ port->frame_sync_offset = 0;
++ }
++ spin_unlock_irqrestore(&npe_lock, flags);
++ return ret;
++}
++
++static ssize_t show_frame_offset(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct port *port = dev_get_drvdata(dev);
++
++ sprintf(buf, "%u\n", port->frame_sync_offset);
++ return strlen(buf) + 1;
++}
++
++static ssize_t set_frame_offset(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t len)
++{
++ struct port *port = dev_get_drvdata(dev);
++ size_t orig_len = len;
++ unsigned long flags;
++ unsigned int offset;
++
++ if (len && buf[len - 1] == '\n')
++ len--;
++
++ if (get_number(&buf, &len, &offset, 0, port->frame_size - 1))
++ return -EINVAL;
++ if (len)
++ return -EINVAL;
++
++ spin_lock_irqsave(&npe_lock, flags);
++
++ port->frame_sync_offset = offset;
++ if (port->chan_open_count || port->hdlc_open) {
++ hss_config_set_rx_frame(port);
++ hss_config_load(port);
++ }
++
++ spin_unlock_irqrestore(&npe_lock, flags);
++ return orig_len;
++}
++
++static ssize_t show_loopback(struct device *dev, struct device_attribute *attr,
++ char *buf)
++{
++ struct port *port = dev_get_drvdata(dev);
++
++ sprintf(buf, "%u\n", port->loopback);
++ return strlen(buf) + 1;
++}
++
++static ssize_t set_loopback(struct device *dev, struct device_attribute *attr,
++ const char *buf, size_t len)
++{
++ struct port *port = dev_get_drvdata(dev);
++ size_t orig_len = len;
++ unsigned long flags;
++ unsigned int lb;
++
++ if (len && buf[len - 1] == '\n')
++ len--;
++
++ if (get_number(&buf, &len, &lb, 0, 1))
++ return -EINVAL;
++ if (len)
++ return -EINVAL;
++
++ spin_lock_irqsave(&npe_lock, flags);
++
++ if (port->loopback != lb) {
++ port->loopback = lb;
++ if (port->chan_open_count || port->hdlc_open) {
++ hss_config_set_core(port);
++ hss_config_load(port);
++ }
++ if (port->loopback || port->carrier)
++ netif_carrier_on(port->netdev);
++ else
++ netif_carrier_off(port->netdev);
++ }
++
++ spin_unlock_irqrestore(&npe_lock, flags);
++ return orig_len;
++}
++
++static ssize_t show_mode(struct device *dev, struct device_attribute *attr,
++ char *buf)
++{
++ struct port *port = dev_get_drvdata(dev);
++
++ switch(port->mode) {
++ case MODE_RAW:
++ strcpy(buf, "raw\n");
++ break;
++ case MODE_G704:
++ strcpy(buf, "g704\n");
++ break;
++ default:
++ strcpy(buf, "hdlc\n");
++ break;
++ }
++ return strlen(buf) + 1;
++}
++
++static ssize_t set_mode(struct device *dev, struct device_attribute *attr,
++ const char *buf, size_t len)
++{
++ struct port *port = dev_get_drvdata(dev);
++ size_t ret = len;
++ unsigned long flags;
++
++ if (len && buf[len - 1] == '\n')
++ len--;
++
++ spin_lock_irqsave(&npe_lock, flags);
++
++ if (port->chan_open_count || port->hdlc_open) {
++ ret = -EBUSY;
++ } else if (len == 4 && !memcmp(buf, "hdlc", 4))
++ port->mode = MODE_HDLC;
++ else if (len == 3 && !memcmp(buf, "raw", 3))
++ port->mode = MODE_RAW;
++ else if (len == 4 && !memcmp(buf, "g704", 4))
++ port->mode = MODE_G704;
++ else
++ ret = -EINVAL;
++
++ spin_unlock_irqrestore(&npe_lock, flags);
++ return ret;
++}
++
++static struct device_attribute hss_attrs[] = {
++ __ATTR(create_chan, 0200, NULL, create_chan),
++ __ATTR(hdlc_chan, 0644, show_hdlc_chan, set_hdlc_chan),
++ __ATTR(clock_type, 0644, show_clock_type, set_clock_type),
++ __ATTR(clock_rate, 0644, show_clock_rate, set_clock_rate),
++ __ATTR(frame_size, 0644, show_frame_size, set_frame_size),
++ __ATTR(frame_offset, 0644, show_frame_offset, set_frame_offset),
++ __ATTR(loopback, 0644, show_loopback, set_loopback),
++ __ATTR(mode, 0644, show_mode, set_mode),
++};
++
++/*****************************************************************************
++ * initialization
++ ****************************************************************************/
++
++static int __devinit hss_init_one(struct platform_device *pdev)
++{
++ struct port *port;
++ struct net_device *dev;
++ hdlc_device *hdlc;
++ int i, err;
++
++ if ((port = kzalloc(sizeof(*port), GFP_KERNEL)) == NULL)
++ return -ENOMEM;
++ platform_set_drvdata(pdev, port);
++ port->id = pdev->id;
++
++ if ((port->npe = npe_request(0)) == NULL) {
++ err = -ENOSYS;
++ goto err_free;
++ }
++
++ port->dev = &pdev->dev;
++ port->plat = pdev->dev.platform_data;
++ if ((port->netdev = dev = alloc_hdlcdev(port)) == NULL) {
++ err = -ENOMEM;
++ goto err_plat;
++ }
++
++ SET_NETDEV_DEV(dev, &pdev->dev);
++ hdlc = dev_to_hdlc(dev);
++ hdlc->attach = hss_hdlc_attach;
++ hdlc->xmit = hss_hdlc_xmit;
++ dev->open = hss_hdlc_open;
++ dev->stop = hss_hdlc_close;
++ dev->do_ioctl = hss_hdlc_ioctl;
++ dev->tx_queue_len = 100;
++ port->clock_type = CLOCK_EXT;
++ port->clock_rate = 2048000;
++ port->frame_size = 256; /* E1 */
++ memset(port->channels, CHANNEL_UNUSED, sizeof(port->channels));
++ init_waitqueue_head(&port->chan_tx_waitq);
++ init_waitqueue_head(&port->chan_rx_waitq);
++ netif_napi_add(dev, &port->napi, hss_hdlc_poll, NAPI_WEIGHT);
++
++ if ((err = register_hdlc_device(dev))) /* HDLC mode by default */
++ goto err_free_netdev;
++
++ for (i = 0; i < ARRAY_SIZE(hss_attrs); i++)
++ BUG_ON(device_create_file(port->dev, &hss_attrs[i]));
++
++ printk(KERN_INFO "%s: HSS-%i\n", dev->name, port->id);
++ return 0;
++
++err_free_netdev:
++ free_netdev(dev);
++err_plat:
++ npe_release(port->npe);
++ platform_set_drvdata(pdev, NULL);
++err_free:
++ kfree(port);
++ return err;
++}
++
++static int __devexit hss_remove_one(struct platform_device *pdev)
++{
++ struct port *port = platform_get_drvdata(pdev);
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(hss_attrs); i++)
++ device_remove_file(port->dev, &hss_attrs[i]);
++
++ unregister_hdlc_device(port->netdev);
++ free_netdev(port->netdev);
++ npe_release(port->npe);
++ platform_set_drvdata(pdev, NULL);
++ kfree(port);
++ return 0;
++}
++
++static struct platform_driver drv = {
++ .driver.name = DRV_NAME,
++ .probe = hss_init_one,
++ .remove = hss_remove_one,
++};
++
++static int __init hss_init_module(void)
++{
++ int err;
++ dev_t rdev;
++
++ if ((ixp4xx_read_feature_bits() &
++ (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) !=
++ (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS))
++ return -ENOSYS;
++
++ if ((err = alloc_chrdev_region(&rdev, 0, HSS_COUNT * MAX_CHAN_DEVICES,
++ "hss")))
++ return err;
++
++ spin_lock_init(&npe_lock);
++
++ if (IS_ERR(hss_class = class_create(THIS_MODULE, "hss"))) {
++ printk(KERN_ERR "Can't register device class 'hss'\n");
++ err = PTR_ERR(hss_class);
++ goto free_chrdev;
++ }
++ if ((err = platform_driver_register(&drv)))
++ goto destroy_class;
++
++ chan_major = MAJOR(rdev);
++ return 0;
++
++destroy_class:
++ class_destroy(hss_class);
++free_chrdev:
++ unregister_chrdev_region(MKDEV(chan_major, 0),
++ HSS_COUNT * MAX_CHAN_DEVICES);
++ return err;
++}
++
++static void __exit hss_cleanup_module(void)
++{
++ platform_driver_unregister(&drv);
++ class_destroy(hss_class);
++ unregister_chrdev_region(MKDEV(chan_major, 0),
++ HSS_COUNT * MAX_CHAN_DEVICES);
++}
++
++MODULE_AUTHOR("Krzysztof Halasa");
++MODULE_DESCRIPTION("Intel IXP4xx HSS driver");
++MODULE_LICENSE("GPL v2");
++MODULE_ALIAS("platform:ixp4xx_hss");
++module_init(hss_init_module);
++module_exit(hss_cleanup_module);
--- /dev/null
+--- a/drivers/i2c/chips/eeprom.c
++++ b/drivers/i2c/chips/eeprom.c
+@@ -33,6 +33,8 @@
+ #include <linux/jiffies.h>
+ #include <linux/i2c.h>
+ #include <linux/mutex.h>
++#include <linux/notifier.h>
++#include <linux/eeprom.h>
+
+ /* Addresses to scan */
+ static const unsigned short normal_i2c[] = { 0x50, 0x51, 0x52, 0x53, 0x54,
+@@ -41,26 +43,7 @@
+ /* Insmod parameters */
+ I2C_CLIENT_INSMOD_1(eeprom);
+
+-
+-/* Size of EEPROM in bytes */
+-#define EEPROM_SIZE 256
+-
+-/* possible types of eeprom devices */
+-enum eeprom_nature {
+- UNKNOWN,
+- VAIO,
+-};
+-
+-/* Each client has this additional data */
+-struct eeprom_data {
+- struct i2c_client client;
+- struct mutex update_lock;
+- u8 valid; /* bitfield, bit!=0 if slice is valid */
+- unsigned long last_updated[8]; /* In jiffies, 8 slices */
+- u8 data[EEPROM_SIZE]; /* Register values */
+- enum eeprom_nature nature;
+-};
+-
++ATOMIC_NOTIFIER_HEAD(eeprom_chain);
+
+ static int eeprom_attach_adapter(struct i2c_adapter *adapter);
+ static int eeprom_detect(struct i2c_adapter *adapter, int address, int kind);
+@@ -197,6 +180,7 @@
+ data->valid = 0;
+ mutex_init(&data->update_lock);
+ data->nature = UNKNOWN;
++ data->attr = &eeprom_attr;
+
+ /* Tell the I2C layer a new client has arrived */
+ if ((err = i2c_attach_client(new_client)))
+@@ -224,6 +208,9 @@
+ if (err)
+ goto exit_detach;
+
++ /* call the notifier chain */
++ atomic_notifier_call_chain(&eeprom_chain, EEPROM_REGISTER, data);
++
+ return 0;
+
+ exit_detach:
+@@ -249,6 +236,41 @@
+ return 0;
+ }
+
++/**
++ * register_eeprom_notifier - register a 'user' of EEPROM devices.
++ * @nb: pointer to notifier info structure
++ *
++ * Registers a callback function to be called upon detection
++ * of an EEPROM device. Detection invokes the 'add' callback
++ * with the kobj of the mutex and a bin_attribute which allows
++ * read from the EEPROM. The intention is that the notifier
++ * will be able to read system configuration from the notifier.
++ *
++ * Only EEPROMs detected *after* the addition of the notifier
++ * are notified. I.e. EEPROMs already known to the system
++ * will not be notified - add the notifier from board level
++ * code!
++ */
++int register_eeprom_notifier(struct notifier_block *nb)
++{
++ return atomic_notifier_chain_register(&eeprom_chain, nb);
++}
++
++/**
++ * unregister_eeprom_notifier - unregister a 'user' of EEPROM devices.
++ * @old: pointer to notifier info structure
++ *
++ * Removes a callback function from the list of 'users' to be
++ * notified upon detection of EEPROM devices.
++ */
++int unregister_eeprom_notifier(struct notifier_block *nb)
++{
++ return atomic_notifier_chain_unregister(&eeprom_chain, nb);
++}
++
++EXPORT_SYMBOL_GPL(register_eeprom_notifier);
++EXPORT_SYMBOL_GPL(unregister_eeprom_notifier);
++
+ static int __init eeprom_init(void)
+ {
+ return i2c_add_driver(&eeprom_driver);
+--- /dev/null
++++ b/include/linux/eeprom.h
+@@ -0,0 +1,71 @@
++#ifndef _LINUX_EEPROM_H
++#define _LINUX_EEPROM_H
++/*
++ * EEPROM notifier header
++ *
++ * Copyright (C) 2006 John Bowler
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#ifndef __KERNEL__
++#error This is a kernel header
++#endif
++
++#include <linux/list.h>
++#include <linux/kobject.h>
++#include <linux/sysfs.h>
++
++/* Size of EEPROM in bytes */
++#define EEPROM_SIZE 256
++
++/* possible types of eeprom devices */
++enum eeprom_nature {
++ UNKNOWN,
++ VAIO,
++};
++
++/* Each client has this additional data */
++struct eeprom_data {
++ struct i2c_client client;
++ struct mutex update_lock;
++ u8 valid; /* bitfield, bit!=0 if slice is valid */
++ unsigned long last_updated[8]; /* In jiffies, 8 slices */
++ u8 data[EEPROM_SIZE]; /* Register values */
++ enum eeprom_nature nature;
++ struct bin_attribute *attr;
++};
++
++/*
++ * This is very basic.
++ *
++ * If an EEPROM is detected on the I2C bus (this only works for
++ * I2C EEPROMs) the notifier chain is called with
++ * both the I2C information and the kobject for the sysfs
++ * device which has been registers. It is then possible to
++ * read from the device via the bin_attribute::read method
++ * to extract configuration information.
++ *
++ * Register the notifier in the board level code, there is no
++ * need to unregister it but you can if you want (it will save
++ * a little bit or kernel memory to do so).
++ */
++
++extern int register_eeprom_notifier(struct notifier_block *nb);
++extern int unregister_eeprom_notifier(struct notifier_block *nb);
++
++#endif /* _LINUX_EEPROM_H */
+--- a/include/linux/notifier.h
++++ b/include/linux/notifier.h
+@@ -253,5 +253,8 @@
+ #define VT_UPDATE 0x0004 /* A bigger update occurred */
+ #define VT_PREWRITE 0x0005 /* A char is about to be written to the console */
+
++/* eeprom notifier chain */
++#define EEPROM_REGISTER 0x0001
++
+ #endif /* __KERNEL__ */
+ #endif /* _LINUX_NOTIFIER_H */
--- /dev/null
+--- a/drivers/leds/Kconfig
++++ b/drivers/leds/Kconfig
+@@ -117,6 +117,12 @@
+ outputs. To be useful the particular board must have LEDs
+ and they must be connected to the GPIO lines.
+
++config LEDS_LATCH
++ tristate "LED Support for Memory Latched LEDs"
++ depends on LEDS_CLASS
++ help
++ -- To Do --
++
+ config LEDS_CM_X270
+ tristate "LED Support for the CM-X270 LEDs"
+ depends on LEDS_CLASS && MACH_ARMCORE
+--- /dev/null
++++ b/drivers/leds/leds-latch.c
+@@ -0,0 +1,141 @@
++/*
++ * LEDs driver for Memory Latched Devices
++ *
++ * Copyright (C) 2008 Gateworks Corp.
++ * Chris Lang <clang@gateworks.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/leds.h>
++#include <linux/workqueue.h>
++#include <asm/io.h>
++#include <linux/spinlock.h>
++
++static unsigned int mem_keep = 0xFF;
++static spinlock_t mem_lock;
++static unsigned char *iobase;
++
++struct latch_led_data {
++ struct led_classdev cdev;
++ struct work_struct work;
++ u8 new_level;
++ u8 bit;
++};
++
++static void latch_led_set(struct led_classdev *led_cdev,
++ enum led_brightness value)
++{
++ struct latch_led_data *led_dat =
++ container_of(led_cdev, struct latch_led_data, cdev);
++
++ spin_lock(mem_lock);
++
++ if (value == LED_OFF)
++ mem_keep |= (0x1 << led_dat->bit);
++ else
++ mem_keep &= ~(0x1 << led_dat->bit);
++
++ writeb(mem_keep, iobase);
++
++ spin_unlock(mem_lock);
++}
++
++static int latch_led_probe(struct platform_device *pdev)
++{
++ struct latch_led_platform_data *pdata = pdev->dev.platform_data;
++ struct latch_led *cur_led;
++ struct latch_led_data *leds_data, *led_dat;
++ int i, ret = 0;
++
++ if (!pdata)
++ return -EBUSY;
++
++ leds_data = kzalloc(sizeof(struct latch_led_data) * pdata->num_leds,
++ GFP_KERNEL);
++ if (!leds_data)
++ return -ENOMEM;
++
++ iobase = ioremap_nocache(pdata->mem, 0x1000);
++ writeb(0xFF, iobase);
++
++ for (i = 0; i < pdata->num_leds; i++) {
++ cur_led = &pdata->leds[i];
++ led_dat = &leds_data[i];
++
++ led_dat->cdev.name = cur_led->name;
++ led_dat->cdev.default_trigger = cur_led->default_trigger;
++ led_dat->cdev.brightness_set = latch_led_set;
++ led_dat->cdev.brightness = LED_OFF;
++ led_dat->bit = cur_led->bit;
++
++ ret = led_classdev_register(&pdev->dev, &led_dat->cdev);
++ if (ret < 0) {
++ goto err;
++ }
++ }
++
++ platform_set_drvdata(pdev, leds_data);
++
++ return 0;
++
++err:
++ if (i > 0) {
++ for (i = i - 1; i >= 0; i--) {
++ led_classdev_unregister(&leds_data[i].cdev);
++ }
++ }
++
++ kfree(leds_data);
++
++ return ret;
++}
++
++static int __devexit latch_led_remove(struct platform_device *pdev)
++{
++ int i;
++ struct latch_led_platform_data *pdata = pdev->dev.platform_data;
++ struct latch_led_data *leds_data;
++
++ leds_data = platform_get_drvdata(pdev);
++
++ for (i = 0; i < pdata->num_leds; i++) {
++ led_classdev_unregister(&leds_data[i].cdev);
++ cancel_work_sync(&leds_data[i].work);
++ }
++
++ kfree(leds_data);
++
++ return 0;
++}
++
++static struct platform_driver latch_led_driver = {
++ .probe = latch_led_probe,
++ .remove = __devexit_p(latch_led_remove),
++ .driver = {
++ .name = "leds-latch",
++ .owner = THIS_MODULE,
++ },
++};
++
++static int __init latch_led_init(void)
++{
++ return platform_driver_register(&latch_led_driver);
++}
++
++static void __exit latch_led_exit(void)
++{
++ platform_driver_unregister(&latch_led_driver);
++}
++
++module_init(latch_led_init);
++module_exit(latch_led_exit);
++
++MODULE_AUTHOR("Chris Lang <clang@gateworks.com>");
++MODULE_DESCRIPTION("Latch LED driver");
++MODULE_LICENSE("GPL");
+--- a/drivers/leds/Makefile
++++ b/drivers/leds/Makefile
+@@ -18,6 +18,7 @@
+ obj-$(CONFIG_LEDS_COBALT_QUBE) += leds-cobalt-qube.o
+ obj-$(CONFIG_LEDS_COBALT_RAQ) += leds-cobalt-raq.o
+ obj-$(CONFIG_LEDS_GPIO) += leds-gpio.o
++obj-$(CONFIG_LEDS_LATCH) += leds-latch.o
+ obj-$(CONFIG_LEDS_CM_X270) += leds-cm-x270.o
+ obj-$(CONFIG_LEDS_CLEVO_MAIL) += leds-clevo-mail.o
+ obj-$(CONFIG_LEDS_HP6XX) += leds-hp6xx.o
+--- a/include/linux/leds.h
++++ b/include/linux/leds.h
+@@ -134,5 +134,18 @@
+ unsigned long *delay_off);
+ };
+
++/* For the leds-latch driver */
++struct latch_led {
++ const char *name;
++ char *default_trigger;
++ unsigned bit;
++};
++
++struct latch_led_platform_data {
++ int num_leds;
++ u32 mem;
++ struct latch_led *leds;
++};
++
+
+ #endif /* __LINUX_LEDS_H_INCLUDED */
--- /dev/null
+--- a/arch/arm/mach-ixp4xx/avila-setup.c
++++ b/arch/arm/mach-ixp4xx/avila-setup.c
+@@ -132,6 +132,31 @@
+ .resource = avila_pata_resources,
+ };
+
++/* Built-in 10/100 Ethernet MAC interfaces */
++static struct eth_plat_info avila_npeb_data = {
++ .phy = 0,
++ .rxq = 3,
++ .txreadyq = 20,
++};
++
++static struct eth_plat_info avila_npec_data = {
++ .phy = 1,
++ .rxq = 4,
++ .txreadyq = 21,
++};
++
++static struct platform_device avila_npeb_device = {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEB,
++ .dev.platform_data = &avila_npeb_data,
++};
++
++static struct platform_device avila_npec_device = {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEC,
++ .dev.platform_data = &avila_npec_data,
++};
++
+ static struct platform_device *avila_devices[] __initdata = {
+ &avila_i2c_gpio,
+ &avila_flash,
+@@ -159,6 +184,8 @@
+
+ platform_device_register(&avila_pata);
+
++ platform_device_register(avila_npeb_device);
++ platform_device_register(avila_npec_device);
+ }
+
+ MACHINE_START(AVILA, "Gateworks Avila Network Platform")
--- /dev/null
+--- a/arch/arm/mach-ixp4xx/avila-setup.c
++++ b/arch/arm/mach-ixp4xx/avila-setup.c
+@@ -14,10 +14,18 @@
+ #include <linux/kernel.h>
+ #include <linux/init.h>
+ #include <linux/device.h>
++#include <linux/if_ether.h>
++#include <linux/socket.h>
++#include <linux/netdevice.h>
+ #include <linux/serial.h>
+ #include <linux/tty.h>
+ #include <linux/serial_8250.h>
+ #include <linux/slab.h>
++#ifdef CONFIG_SENSORS_EEPROM
++# include <linux/i2c.h>
++# include <linux/eeprom.h>
++#endif
++
+ #include <linux/i2c-gpio.h>
+
+ #include <asm/types.h>
+@@ -29,6 +37,13 @@
+ #include <asm/mach/arch.h>
+ #include <asm/mach/flash.h>
+
++struct avila_board_info {
++ unsigned char *model;
++ void (* setup)(void);
++};
++
++static struct avila_board_info *avila_info __initdata;
++
+ static struct flash_platform_data avila_flash_data = {
+ .map_name = "cfi_probe",
+ .width = 2,
+@@ -163,10 +178,160 @@
+ &avila_uart
+ };
+
++static void __init avila_gw23xx_setup(void)
++{
++ platform_device_register(&avila_npeb_device);
++ platform_device_register(&avila_npec_device);
++}
++
++#ifdef CONFIG_SENSORS_EEPROM
++static void __init avila_gw2342_setup(void)
++{
++ platform_device_register(&avila_npeb_device);
++ platform_device_register(&avila_npec_device);
++}
++
++static void __init avila_gw2345_setup(void)
++{
++ avila_npeb_data.phy = IXP4XX_ETH_PHY_MAX_ADDR;
++ avila_npeb_data.phy_mask = 0x1e; /* ports 1-4 of the KS8995 switch */
++ platform_device_register(&avila_npeb_device);
++
++ avila_npec_data.phy = 5; /* port 5 of the KS8995 switch */
++ platform_device_register(&avila_npec_device);
++}
++
++static void __init avila_gw2347_setup(void)
++{
++ platform_device_register(&avila_npeb_device);
++}
++
++static void __init avila_gw2348_setup(void)
++{
++ platform_device_register(&avila_npeb_device);
++ platform_device_register(&avila_npec_device);
++}
++
++static void __init avila_gw2353_setup(void)
++{
++ platform_device_register(&avila_npeb_device);
++}
++
++static void __init avila_gw2355_setup(void)
++{
++ avila_npeb_data.phy = IXP4XX_ETH_PHY_MAX_ADDR;
++ avila_npeb_data.phy_mask = 0x1e; /* ports 1-4 of the KS8995 switch */
++ platform_device_register(&avila_npeb_device);
++
++ avila_npec_data.phy = 16;
++ platform_device_register(&avila_npec_device);
++}
++
++static void __init avila_gw2357_setup(void)
++{
++ platform_device_register(&avila_npeb_device);
++}
++
++static struct avila_board_info avila_boards[] __initdata = {
++ {
++ .model = "GW2342",
++ .setup = avila_gw2342_setup,
++ }, {
++ .model = "GW2345",
++ .setup = avila_gw2345_setup,
++ }, {
++ .model = "GW2347",
++ .setup = avila_gw2347_setup,
++ }, {
++ .model = "GW2348",
++ .setup = avila_gw2348_setup,
++ }, {
++ .model = "GW2353",
++ .setup = avila_gw2353_setup,
++ }, {
++ .model = "GW2355",
++ .setup = avila_gw2355_setup,
++ }, {
++ .model = "GW2357",
++ .setup = avila_gw2357_setup,
++ }
++};
++
++static struct avila_board_info * __init avila_find_board_info(char *model)
++{
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(avila_boards); i++) {
++ struct avila_board_info *info = &avila_boards[i];
++ if (strncmp(info->model, model, strlen(info->model)) == 0)
++ return info;
++ }
++
++ return NULL;
++}
++
++struct avila_eeprom_header {
++ unsigned char mac0[ETH_ALEN];
++ unsigned char mac1[ETH_ALEN];
++ unsigned char res0[4];
++ unsigned char magic[2];
++ unsigned char config[14];
++ unsigned char model[16];
++};
++
++static int __init avila_eeprom_notify(struct notifier_block *self,
++ unsigned long event, void *t)
++{
++ struct eeprom_data *ee = t;
++ struct avila_eeprom_header hdr;
++
++ if (avila_info)
++ return NOTIFY_DONE;
++
++ /* The eeprom is at address 0x51 */
++ if (event != EEPROM_REGISTER || ee->client.addr != 0x51)
++ return NOTIFY_DONE;
++
++ ee->attr->read(&ee->client.dev.kobj, ee->attr, (char *)&hdr,
++ 0, sizeof(hdr));
++
++ if (hdr.magic[0] != 'G' || hdr.magic[1] != 'W')
++ return NOTIFY_DONE;
++
++ memcpy(&avila_npeb_data.hwaddr, hdr.mac0, ETH_ALEN);
++ memcpy(&avila_npec_data.hwaddr, hdr.mac1, ETH_ALEN);
++
++ avila_info = avila_find_board_info(hdr.model);
++
++ return NOTIFY_OK;
++}
++
++static struct notifier_block avila_eeprom_notifier __initdata = {
++ .notifier_call = avila_eeprom_notify
++};
++
++static void __init avila_register_eeprom_notifier(void)
++{
++ register_eeprom_notifier(&avila_eeprom_notifier);
++}
++
++static void __init avila_unregister_eeprom_notifier(void)
++{
++ unregister_eeprom_notifier(&avila_eeprom_notifier);
++}
++#else /* CONFIG_SENSORS_EEPROM */
++static inline void avila_register_eeprom_notifier(void) {};
++static inline void avila_unregister_eeprom_notifier(void) {};
++#endif /* CONFIG_SENSORS_EEPROM */
++
+ static void __init avila_init(void)
+ {
+ ixp4xx_sys_init();
+
++ /*
++ * These devices are present on all Avila models and don't need any
++ * model specific setup.
++ */
+ avila_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
+ avila_flash_resource.end =
+ IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
+@@ -184,9 +349,28 @@
+
+ platform_device_register(&avila_pata);
+
+- platform_device_register(avila_npeb_device);
+- platform_device_register(avila_npec_device);
++ avila_register_eeprom_notifier();
++}
++
++static int __init avila_model_setup(void)
++{
++ if (!machine_is_avila())
++ return 0;
++
++ if (avila_info) {
++ printk(KERN_DEBUG "Running on Gateworks Avila %s\n",
++ avila_info->model);
++ avila_info->setup();
++ } else {
++ printk(KERN_INFO "Unknown/missing Avila model number"
++ " -- defaults will be used\n");
++ avila_gw23xx_setup();
++ }
++
++ avila_unregister_eeprom_notifier();
++ return 0;
+ }
++late_initcall(avila_model_setup);
+
+ MACHINE_START(AVILA, "Gateworks Avila Network Platform")
+ /* Maintainer: Deepak Saxena <dsaxena@plexity.net> */
--- /dev/null
+--- a/arch/arm/mach-ixp4xx/avila-setup.c
++++ b/arch/arm/mach-ixp4xx/avila-setup.c
+@@ -26,6 +26,7 @@
+ # include <linux/eeprom.h>
+ #endif
+
++#include <linux/leds.h>
+ #include <linux/i2c-gpio.h>
+
+ #include <asm/types.h>
+@@ -172,6 +173,72 @@
+ .dev.platform_data = &avila_npec_data,
+ };
+
++static struct gpio_led avila_gpio_leds[] = {
++ {
++ .name = "user", /* green led */
++ .gpio = AVILA_GW23XX_LED_USER_GPIO,
++ .active_low = 1,
++ }
++};
++
++static struct gpio_led_platform_data avila_gpio_leds_data = {
++ .num_leds = 1,
++ .leds = avila_gpio_leds,
++};
++
++static struct platform_device avila_gpio_leds_device = {
++ .name = "leds-gpio",
++ .id = -1,
++ .dev.platform_data = &avila_gpio_leds_data,
++};
++
++static struct latch_led avila_latch_leds[] = {
++ {
++ .name = "led0", /* green led */
++ .bit = 0,
++ },
++ {
++ .name = "led1", /* green led */
++ .bit = 1,
++ },
++ {
++ .name = "led2", /* green led */
++ .bit = 2,
++ },
++ {
++ .name = "led3", /* green led */
++ .bit = 3,
++ },
++ {
++ .name = "led4", /* green led */
++ .bit = 4,
++ },
++ {
++ .name = "led5", /* green led */
++ .bit = 5,
++ },
++ {
++ .name = "led6", /* green led */
++ .bit = 6,
++ },
++ {
++ .name = "led7", /* green led */
++ .bit = 7,
++ }
++};
++
++static struct latch_led_platform_data avila_latch_leds_data = {
++ .num_leds = 8,
++ .leds = avila_latch_leds,
++ .mem = 0x51000000,
++};
++
++static struct platform_device avila_latch_leds_device = {
++ .name = "leds-latch",
++ .id = -1,
++ .dev.platform_data = &avila_latch_leds_data,
++};
++
+ static struct platform_device *avila_devices[] __initdata = {
+ &avila_i2c_gpio,
+ &avila_flash,
+@@ -182,6 +249,8 @@
+ {
+ platform_device_register(&avila_npeb_device);
+ platform_device_register(&avila_npec_device);
++
++ platform_device_register(&avila_gpio_leds_device);
+ }
+
+ #ifdef CONFIG_SENSORS_EEPROM
+@@ -189,6 +258,8 @@
+ {
+ platform_device_register(&avila_npeb_device);
+ platform_device_register(&avila_npec_device);
++
++ platform_device_register(&avila_gpio_leds_device);
+ }
+
+ static void __init avila_gw2345_setup(void)
+@@ -199,22 +270,30 @@
+
+ avila_npec_data.phy = 5; /* port 5 of the KS8995 switch */
+ platform_device_register(&avila_npec_device);
++
++ platform_device_register(&avila_gpio_leds_device);
+ }
+
+ static void __init avila_gw2347_setup(void)
+ {
+ platform_device_register(&avila_npeb_device);
++
++ avila_gpio_leds[0].gpio = AVILA_GW23X7_LED_USER_GPIO;
++ platform_device_register(&avila_gpio_leds_device);
+ }
+
+ static void __init avila_gw2348_setup(void)
+ {
+ platform_device_register(&avila_npeb_device);
+ platform_device_register(&avila_npec_device);
++
++ platform_device_register(&avila_gpio_leds_device);
+ }
+
+ static void __init avila_gw2353_setup(void)
+ {
+ platform_device_register(&avila_npeb_device);
++ platform_device_register(&avila_gpio_leds_device);
+ }
+
+ static void __init avila_gw2355_setup(void)
+@@ -225,11 +304,29 @@
+
+ avila_npec_data.phy = 16;
+ platform_device_register(&avila_npec_device);
++
++ platform_device_register(&avila_gpio_leds_device);
++
++ *IXP4XX_EXP_CS4 |= 0xbfff3c03;
++ avila_latch_leds[0].name = "RXD";
++ avila_latch_leds[1].name = "TXD";
++ avila_latch_leds[2].name = "POL";
++ avila_latch_leds[3].name = "LNK";
++ avila_latch_leds[4].name = "ERR";
++ avila_latch_leds_data.num_leds = 5;
++ avila_latch_leds_data.mem = 0x54000000;
++ platform_device_register(&avila_latch_leds_device);
+ }
+
+ static void __init avila_gw2357_setup(void)
+ {
+ platform_device_register(&avila_npeb_device);
++
++ avila_gpio_leds[0].gpio = AVILA_GW23X7_LED_USER_GPIO;
++ platform_device_register(&avila_gpio_leds_device);
++
++ *IXP4XX_EXP_CS1 |= 0xbfff3c03;
++ platform_device_register(&avila_latch_leds_device);
+ }
+
+ static struct avila_board_info avila_boards[] __initdata = {
+--- a/include/asm-arm/arch-ixp4xx/avila.h
++++ b/include/asm-arm/arch-ixp4xx/avila.h
+@@ -36,4 +36,6 @@
+ #define AVILA_PCI_INTC_PIN 9
+ #define AVILA_PCI_INTD_PIN 8
+
+-
++/* User LEDs */
++#define AVILA_GW23XX_LED_USER_GPIO 3
++#define AVILA_GW23X7_LED_USER_GPIO 4
--- /dev/null
+--- a/arch/arm/mach-ixp4xx/avila-setup.c
++++ b/arch/arm/mach-ixp4xx/avila-setup.c
+@@ -239,10 +239,28 @@
+ .dev.platform_data = &avila_latch_leds_data,
+ };
+
++static struct resource avila_gpio_resources[] = {
++ {
++ .name = "gpio",
++ /* FIXME: gpio mask should be model specific */
++ .start = AVILA_GPIO_MASK,
++ .end = AVILA_GPIO_MASK,
++ .flags = 0,
++ },
++};
++
++static struct platform_device avila_gpio = {
++ .name = "GPIODEV",
++ .id = -1,
++ .num_resources = ARRAY_SIZE(avila_gpio_resources),
++ .resource = avila_gpio_resources,
++};
++
+ static struct platform_device *avila_devices[] __initdata = {
+ &avila_i2c_gpio,
+ &avila_flash,
+- &avila_uart
++ &avila_uart,
++ &avila_gpio,
+ };
+
+ static void __init avila_gw23xx_setup(void)
+--- a/include/asm-arm/arch-ixp4xx/avila.h
++++ b/include/asm-arm/arch-ixp4xx/avila.h
+@@ -39,3 +39,6 @@
+ /* User LEDs */
+ #define AVILA_GW23XX_LED_USER_GPIO 3
+ #define AVILA_GW23X7_LED_USER_GPIO 4
++
++/* gpio mask used by platform device */
++#define AVILA_GPIO_MASK (1 << 1) | (1 << 3) | (1 << 5) | (1 << 7) | (1 << 9)
--- /dev/null
+--- a/arch/arm/mach-ixp4xx/avila-setup.c
++++ b/arch/arm/mach-ixp4xx/avila-setup.c
+@@ -294,6 +294,7 @@
+
+ static void __init avila_gw2347_setup(void)
+ {
++ avila_npeb_data.quirks |= IXP4XX_ETH_QUIRK_GW23X7;
+ platform_device_register(&avila_npeb_device);
+
+ avila_gpio_leds[0].gpio = AVILA_GW23X7_LED_USER_GPIO;
+@@ -338,6 +339,7 @@
+
+ static void __init avila_gw2357_setup(void)
+ {
++ avila_npeb_data.quirks |= IXP4XX_ETH_QUIRK_GW23X7;
+ platform_device_register(&avila_npeb_device);
+
+ avila_gpio_leds[0].gpio = AVILA_GW23X7_LED_USER_GPIO;
+--- a/drivers/net/arm/ixp4xx_eth.c
++++ b/drivers/net/arm/ixp4xx_eth.c
+@@ -348,6 +348,14 @@
+ return;
+ }
+
++ if (port->plat->quirks & IXP4XX_ETH_QUIRK_GW23X7) {
++ mdio_write(dev, 1, 0x19,
++ (mdio_read(dev, 1, 0x19) & 0xfffe) | 0x8000);
++
++ printk(KERN_DEBUG "%s: phy_id of the DP83848 changed to 0\n",
++ dev->name);
++ }
++
+ /* restart auto negotiation */
+ bmcr = mdio_read(dev, phy_id, MII_BMCR);
+ bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
+--- a/include/asm-arm/arch-ixp4xx/platform.h
++++ b/include/asm-arm/arch-ixp4xx/platform.h
+@@ -104,6 +104,8 @@
+ u8 txreadyq;
+ u8 hwaddr[6];
+ u32 phy_mask;
++ u32 quirks;
++#define IXP4XX_ETH_QUIRK_GW23X7 0x00000001
+ };
+
+ /* Information about built-in HSS (synchronous serial) interfaces */
--- /dev/null
+--- a/arch/arm/mach-ixp4xx/gtwx5715-setup.c
++++ b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
+@@ -29,6 +29,8 @@
+ #include <linux/serial_8250.h>
+ #include <linux/slab.h>
+
++#include <linux/spi/spi_gpio.h>
++
+ #include <asm/types.h>
+ #include <asm/setup.h>
+ #include <asm/memory.h>
+@@ -121,9 +123,41 @@
+ .resource = >wx5715_flash_resource,
+ };
+
++static int gtwx5715_spi_boardinfo_setup(struct spi_board_info *bi,
++ struct spi_master *master, void *data)
++{
++
++ strlcpy(bi->modalias, "spi-ks8995", sizeof(bi->modalias));
++
++ bi->max_speed_hz = 5000000 /* Hz */;
++ bi->bus_num = master->bus_num;
++ bi->mode = SPI_MODE_0;
++
++ return 0;
++}
++
++static struct spi_gpio_platform_data gtwx5715_spi_bus_data = {
++ .pin_cs = GTWX5715_KSSPI_SELECT,
++ .pin_clk = GTWX5715_KSSPI_CLOCK,
++ .pin_miso = GTWX5715_KSSPI_RXD,
++ .pin_mosi = GTWX5715_KSSPI_TXD,
++ .cs_activelow = 1,
++ .no_spi_delay = 1,
++ .boardinfo_setup = gtwx5715_spi_boardinfo_setup,
++};
++
++static struct platform_device gtwx5715_spi_bus = {
++ .name = "spi-gpio",
++ .id = 0,
++ .dev = {
++ .platform_data = >wx5715_spi_bus_data,
++ },
++};
++
+ static struct platform_device *gtwx5715_devices[] __initdata = {
+ >wx5715_uart_device,
+ >wx5715_flash,
++ >wx5715_spi_bus,
+ };
+
+ static void __init gtwx5715_init(void)
--- /dev/null
+--- a/arch/arm/mach-ixp4xx/gtwx5715-setup.c
++++ b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
+@@ -154,10 +154,37 @@
+ },
+ };
+
++static struct eth_plat_info gtwx5715_npeb_data = {
++ .phy = IXP4XX_ETH_PHY_MAX_ADDR,
++ .phy_mask = 0x1e, /* ports 1-4 of the KS8995 switch */
++ .rxq = 3,
++ .txreadyq = 20,
++};
++
++static struct eth_plat_info gtwx5715_npec_data = {
++ .phy = 5, /* port 5 of the KS8995 switch */
++ .rxq = 4,
++ .txreadyq = 21,
++};
++
++static struct platform_device gtwx5715_npeb_device = {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEB,
++ .dev.platform_data = >wx5715_npeb_data,
++};
++
++static struct platform_device gtwx5715_npec_device = {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEC,
++ .dev.platform_data = >wx5715_npec_data,
++};
++
+ static struct platform_device *gtwx5715_devices[] __initdata = {
+ >wx5715_uart_device,
+ >wx5715_flash,
+ >wx5715_spi_bus,
++ >wx5715_npeb_device,
++ >wx5715_npec_device,
+ };
+
+ static void __init gtwx5715_init(void)
--- /dev/null
+--- a/drivers/ata/pata_ixp4xx_cf.c
++++ b/drivers/ata/pata_ixp4xx_cf.c
+@@ -24,17 +24,58 @@
+ #include <scsi/scsi_host.h>
+
+ #define DRV_NAME "pata_ixp4xx_cf"
+-#define DRV_VERSION "0.2"
++#define DRV_VERSION "0.3"
+
+ static int ixp4xx_set_mode(struct ata_link *link, struct ata_device **error)
+ {
+ struct ata_device *dev;
++ struct ixp4xx_pata_data *data = link->ap->host->dev->platform_data;
++ unsigned int pio_mask;
+
+ ata_link_for_each_dev(dev, link) {
++ if (dev->id[ATA_ID_FIELD_VALID] & (1 << 1)){
++ pio_mask = dev->id[ATA_ID_PIO_MODES] & 0x03;
++ if (pio_mask & (1 << 1)){
++ pio_mask = 4;
++ }else{
++ pio_mask = 3;
++ }
++ }else{
++ pio_mask = (dev->id[ATA_ID_OLD_PIO_MODES] >> 8);
++ }
++ switch (pio_mask){
++ case 0:
++ ata_dev_printk(dev, KERN_INFO, "configured for PIO0\n");
++ dev->pio_mode = XFER_PIO_0;
++ dev->xfer_mode = XFER_PIO_0;
++ *data->cs0_cfg = 0x8a473c03;
++ break;
++ case 1:
++ ata_dev_printk(dev, KERN_INFO, "configured for PIO1\n");
++ dev->pio_mode = XFER_PIO_1;
++ dev->xfer_mode = XFER_PIO_1;
++ *data->cs0_cfg = 0x86433c03;
++ break;
++ case 2:
++ ata_dev_printk(dev, KERN_INFO, "configured for PIO2\n");
++ dev->pio_mode = XFER_PIO_2;
++ dev->xfer_mode = XFER_PIO_2;
++ *data->cs0_cfg = 0x82413c03;
++ break;
++ case 3:
++ ata_dev_printk(dev, KERN_INFO, "configured for PIO3\n");
++ dev->pio_mode = XFER_PIO_3;
++ dev->xfer_mode = XFER_PIO_3;
++ *data->cs0_cfg = 0x80823c03;
++ break;
++ case 4:
++ ata_dev_printk(dev, KERN_INFO, "configured for PIO4\n");
++ dev->pio_mode = XFER_PIO_4;
++ dev->xfer_mode = XFER_PIO_4;
++ *data->cs0_cfg = 0x80403c03;
++ break;
++ }
+ if (ata_dev_enabled(dev)) {
+- ata_dev_printk(dev, KERN_INFO, "configured for PIO0\n");
+- dev->pio_mode = XFER_PIO_0;
+- dev->xfer_mode = XFER_PIO_0;
+ dev->xfer_shift = ATA_SHIFT_PIO;
+ dev->flags |= ATA_DFLAG_PIO;
+ }
+@@ -48,6 +89,7 @@
+ unsigned int i;
+ unsigned int words = buflen >> 1;
+ u16 *buf16 = (u16 *) buf;
++ unsigned int pio_mask;
+ struct ata_port *ap = dev->link->ap;
+ void __iomem *mmio = ap->ioaddr.data_addr;
+ struct ixp4xx_pata_data *data = ap->host->dev->platform_data;
+@@ -55,8 +97,34 @@
+ /* set the expansion bus in 16bit mode and restore
+ * 8 bit mode after the transaction.
+ */
+- *data->cs0_cfg &= ~(0x01);
+- udelay(100);
++ if (dev->id[ATA_ID_FIELD_VALID] & (1 << 1)){
++ pio_mask = dev->id[ATA_ID_PIO_MODES] & 0x03;
++ if (pio_mask & (1 << 1)){
++ pio_mask = 4;
++ }else{
++ pio_mask = 3;
++ }
++ }else{
++ pio_mask = (dev->id[ATA_ID_OLD_PIO_MODES] >> 8);
++ }
++ switch (pio_mask){
++ case 0:
++ *data->cs0_cfg = 0xa9643c42;
++ break;
++ case 1:
++ *data->cs0_cfg = 0x85033c42;
++ break;
++ case 2:
++ *data->cs0_cfg = 0x80b23c42;
++ break;
++ case 3:
++ *data->cs0_cfg = 0x80823c42;
++ break;
++ case 4:
++ *data->cs0_cfg = 0x80403c42;
++ break;
++ }
++ udelay(5);
+
+ /* Transfer multiple of 2 bytes */
+ if (rw == READ)
+@@ -81,8 +149,24 @@
+ words++;
+ }
+
+- udelay(100);
+- *data->cs0_cfg |= 0x01;
++ udelay(5);
++ switch (pio_mask){
++ case 0:
++ *data->cs0_cfg = 0x8a473c03;
++ break;
++ case 1:
++ *data->cs0_cfg = 0x86433c03;
++ break;
++ case 2:
++ *data->cs0_cfg = 0x82413c03;
++ break;
++ case 3:
++ *data->cs0_cfg = 0x80823c03;
++ break;
++ case 4:
++ *data->cs0_cfg = 0x80403c03;
++ break;
++ }
+
+ return words << 1;
+ }
--- /dev/null
+--- a/arch/arm/common/dmabounce.c
++++ b/arch/arm/common/dmabounce.c
+@@ -117,6 +117,10 @@
+ } else if (size <= device_info->large.size) {
+ pool = &device_info->large;
+ } else {
++#ifdef CONFIG_DMABOUNCE_DEBUG
++ printk(KERN_INFO "A dma bounce buffer outside the pool size was requested. Requested size was 0x%08X\nThe calling code was :\n", size);
++ dump_stack();
++#endif
+ pool = NULL;
+ }
+
+--- a/arch/arm/mach-ixp4xx/Kconfig
++++ b/arch/arm/mach-ixp4xx/Kconfig
+@@ -244,6 +244,11 @@
+ default y
+ depends on PCI
+
++config DMABOUNCE_DEBUG
++ bool "Enable DMABounce debuging"
++ default n
++ depends on DMABOUNCE
++
+ config IXP4XX_INDIRECT_PCI
+ bool "Use indirect PCI memory access"
+ depends on PCI
--- /dev/null
+--- a/include/asm-arm/arch-ixp4xx/avila.h
++++ b/include/asm-arm/arch-ixp4xx/avila.h
+@@ -25,7 +25,7 @@
+ /*
+ * AVILA PCI IRQs
+ */
+-#define AVILA_PCI_MAX_DEV 4
++#define AVILA_PCI_MAX_DEV 6
+ #define LOFT_PCI_MAX_DEV 6
+ #define AVILA_PCI_IRQ_LINES 4
+
+++ /dev/null
-CONFIG_32BIT=y
-# CONFIG_64BIT is not set
-# CONFIG_8139TOO is not set
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_ARCH_POPULATES_NODE_MAP=y
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-CONFIG_ARCH_SUPPORTS_OPROFILE=y
-# CONFIG_ATM is not set
-# CONFIG_AX25 is not set
-CONFIG_BASE_SMALL=0
-# CONFIG_BCM47XX is not set
-CONFIG_BITREVERSE=y
-CONFIG_BLK_DEV_CF_MIPS=y
-# CONFIG_BOOT_PRINTK_DELAY is not set
-# CONFIG_BT is not set
-CONFIG_CEVT_R4K=y
-# CONFIG_CPU_BIG_ENDIAN is not set
-CONFIG_CPU_HAS_LLSC=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-# CONFIG_CPU_LOONGSON2 is not set
-CONFIG_CPU_MIPS32=y
-CONFIG_CPU_MIPS32_R1=y
-# CONFIG_CPU_MIPS32_R2 is not set
-# CONFIG_CPU_MIPS64_R1 is not set
-# CONFIG_CPU_MIPS64_R2 is not set
-CONFIG_CPU_MIPSR1=y
-# CONFIG_CPU_NEVADA is not set
-# CONFIG_CPU_R10000 is not set
-# CONFIG_CPU_R3000 is not set
-# CONFIG_CPU_R4300 is not set
-# CONFIG_CPU_R4X00 is not set
-# CONFIG_CPU_R5000 is not set
-# CONFIG_CPU_R5432 is not set
-# CONFIG_CPU_R6000 is not set
-# CONFIG_CPU_R8000 is not set
-# CONFIG_CPU_RM7000 is not set
-# CONFIG_CPU_RM9000 is not set
-# CONFIG_CPU_SB1 is not set
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-# CONFIG_CPU_TX39XX is not set
-# CONFIG_CPU_TX49XX is not set
-# CONFIG_CPU_VR41XX is not set
-CONFIG_CSRC_R4K=y
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_INFO is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_KOBJECT is not set
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_LOCK_ALLOC is not set
-# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_DEBUG_SG is not set
-# CONFIG_DEBUG_SHIRQ is not set
-# CONFIG_DEBUG_SLAB is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DETECT_SOFTLOCKUP is not set
-CONFIG_DEVPORT=y
-# CONFIG_DM9000 is not set
-CONFIG_DMA_NEED_PCI_MAP_STATE=y
-CONFIG_DMA_NONCOHERENT=y
-CONFIG_EXT2_FS=y
-# CONFIG_FAULT_INJECTION is not set
-CONFIG_FORCED_INLINING=y
-CONFIG_FS_POSIX_ACL=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_FIND_NEXT_BIT=y
-CONFIG_GENERIC_GPIO=y
-# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HID=m
-CONFIG_HID_SUPPORT=y
-# CONFIG_HIGH_RES_TIMERS is not set
-CONFIG_HW_HAS_PCI=y
-CONFIG_HW_RANDOM=y
-# CONFIG_I2C is not set
-# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_IBM_NEW_EMAC_RGMII is not set
-# CONFIG_IBM_NEW_EMAC_TAH is not set
-# CONFIG_IBM_NEW_EMAC_ZMII is not set
-# CONFIG_IDE is not set
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_IRQ_CPU=y
-CONFIG_KALLSYMS=y
-CONFIG_KALLSYMS_ALL=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
-CONFIG_KEXEC=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_GPIO=y
-# CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_KEYBOARD_STOWAWAY is not set
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-CONFIG_KORINA=y
-CONFIG_LEDS_RB500=y
-# CONFIG_LEMOTE_FULONG is not set
-# CONFIG_LOCK_STAT is not set
-# CONFIG_MACH_ALCHEMY is not set
-# CONFIG_MACH_DECSTATION is not set
-# CONFIG_MACH_JAZZ is not set
-# CONFIG_MACH_VR41XX is not set
-CONFIG_MIKROTIK_RB500=y
-CONFIG_MINI_FO=m
-CONFIG_MIPS=y
-# CONFIG_MIPS_ATLAS is not set
-# CONFIG_MIPS_COBALT is not set
-CONFIG_MIPS_L1_CACHE_SHIFT=4
-# CONFIG_MIPS_MALTA is not set
-CONFIG_MIPS_MT_DISABLED=y
-# CONFIG_MIPS_MT_SMP is not set
-# CONFIG_MIPS_MT_SMTC is not set
-# CONFIG_MIPS_SEAD is not set
-# CONFIG_MIPS_SIM is not set
-# CONFIG_MIPS_UNCACHED is not set
-CONFIG_MTD=y
-# CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_ALAUDA is not set
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_BLOCK2MTD=y
-# CONFIG_MTD_CFI is not set
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-CONFIG_MTD_CHAR=y
-# CONFIG_MTD_CMDLINE_PARTS is not set
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_CONCAT is not set
-# CONFIG_MTD_DEBUG is not set
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-# CONFIG_MTD_JEDECPROBE is not set
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MTDRAM is not set
-CONFIG_MTD_NAND=y
-# CONFIG_MTD_NAND_CAFE is not set
-# CONFIG_MTD_NAND_DISKONCHIP is not set
-# CONFIG_MTD_NAND_ECC_SMC is not set
-CONFIG_MTD_NAND_IDS=y
-# CONFIG_MTD_NAND_MUSEUM_IDS is not set
-# CONFIG_MTD_NAND_NANDSIM is not set
-CONFIG_MTD_NAND_PLATFORM=y
-CONFIG_MTD_NAND_VERIFY_WRITE=y
-# CONFIG_MTD_ONENAND is not set
-CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_PLATRAM is not set
-# CONFIG_MTD_PMC551 is not set
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_NATSEMI is not set
-# CONFIG_NE2K_PCI is not set
-# CONFIG_NET_SCH_ESFQ_NFCT is not set
-# CONFIG_NET_VENDOR_3COM is not set
-CONFIG_NF_CONNTRACK=y
-# CONFIG_NO_IOPORT is not set
-# CONFIG_PAGE_SIZE_16KB is not set
-CONFIG_PAGE_SIZE_4KB=y
-# CONFIG_PAGE_SIZE_64KB is not set
-# CONFIG_PAGE_SIZE_8KB is not set
-CONFIG_PCI=y
-# CONFIG_PCIPCWATCHDOG is not set
-# CONFIG_PCI_DEBUG is not set
-CONFIG_PCI_DOMAINS=y
-# CONFIG_PMC_MSP is not set
-# CONFIG_PMC_YOSEMITE is not set
-# CONFIG_PNX8550_JBS is not set
-# CONFIG_PNX8550_STB810 is not set
-# CONFIG_PROVE_LOCKING is not set
-CONFIG_RC32434_WDT=y
-# CONFIG_RCU_TORTURE_TEST is not set
-# CONFIG_RTC is not set
-CONFIG_RTC_LIB=y
-# CONFIG_RT_MUTEX_TESTER is not set
-# CONFIG_RUNTIME_DEBUG is not set
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_SCHED_DEBUG is not set
-CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
-CONFIG_SCSI_WAIT_SCAN=m
-# CONFIG_SERIAL_8250_EXTENDED is not set
-# CONFIG_SGI_IP22 is not set
-# CONFIG_SGI_IP27 is not set
-# CONFIG_SGI_IP32 is not set
-# CONFIG_SIBYTE_BIGSUR is not set
-# CONFIG_SIBYTE_CARMEL is not set
-# CONFIG_SIBYTE_CRHINE is not set
-# CONFIG_SIBYTE_CRHONE is not set
-# CONFIG_SIBYTE_LITTLESUR is not set
-# CONFIG_SIBYTE_PTSWARM is not set
-# CONFIG_SIBYTE_RHONE is not set
-# CONFIG_SIBYTE_SENTOSA is not set
-# CONFIG_SIBYTE_SWARM is not set
-CONFIG_SLABINFO=y
-# CONFIG_SOFT_WATCHDOG is not set
-# CONFIG_SOUND is not set
-# CONFIG_SPARSEMEM_STATIC is not set
-# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
-CONFIG_SSB_POSSIBLE=y
-CONFIG_SWAP_IO_SPACE=y
-CONFIG_SYSVIPC_SYSCTL=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-# CONFIG_TC35815 is not set
-# CONFIG_TICK_ONESHOT is not set
-# CONFIG_TIMER_STATS is not set
-# CONFIG_TOSHIBA_JMR3927 is not set
-# CONFIG_TOSHIBA_RBTX4927 is not set
-# CONFIG_TOSHIBA_RBTX4938 is not set
-CONFIG_TRAD_SIGNALS=y
-CONFIG_USB=m
-# CONFIG_USBPCWATCHDOG is not set
-# CONFIG_USB_EHCI_HCD is not set
-# CONFIG_USB_UHCI_HCD is not set
-# CONFIG_USER_NS is not set
-# CONFIG_VGASTATE is not set
-CONFIG_VIA_RHINE=y
-# CONFIG_VIA_RHINE_MMIO is not set
-CONFIG_VIA_RHINE_NAPI=y
-# CONFIG_YAFFS_9BYTE_TAGS is not set
-CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED=y
-CONFIG_YAFFS_AUTO_YAFFS2=y
-CONFIG_YAFFS_CHECKPOINT_RESERVED_BLOCKS=0
-# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
-# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
-CONFIG_YAFFS_DOES_ECC=y
-CONFIG_YAFFS_ECC_WRONG_ORDER=y
-CONFIG_YAFFS_FS=y
-CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
-CONFIG_YAFFS_YAFFS1=y
-CONFIG_YAFFS_YAFFS2=y
-CONFIG_ZONE_DMA_FLAG=0
--- /dev/null
+CONFIG_32BIT=y
+# CONFIG_64BIT is not set
+# CONFIG_8139TOO is not set
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+# CONFIG_ATM is not set
+# CONFIG_AX25 is not set
+CONFIG_BASE_SMALL=0
+# CONFIG_BCM47XX is not set
+CONFIG_BITREVERSE=y
+CONFIG_BLK_DEV_CF_MIPS=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_BT is not set
+CONFIG_CEVT_R4K=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_HAS_LLSC=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+# CONFIG_CPU_LOONGSON2 is not set
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPS32_R1=y
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+CONFIG_CPU_MIPSR1=y
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_VR41XX is not set
+CONFIG_CSRC_R4K=y
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_INFO is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DETECT_SOFTLOCKUP is not set
+CONFIG_DEVPORT=y
+# CONFIG_DM9000 is not set
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_EXT2_FS=y
+# CONFIG_FAULT_INJECTION is not set
+CONFIG_FORCED_INLINING=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HID=m
+CONFIG_HID_SUPPORT=y
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_HW_HAS_PCI=y
+CONFIG_HW_RANDOM=y
+# CONFIG_I2C is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IDE is not set
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=y
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_IRQ_CPU=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_KEXEC=y
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_KORINA=y
+CONFIG_LEDS_RB500=y
+# CONFIG_LEMOTE_FULONG is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_MACH_ALCHEMY is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_MACH_VR41XX is not set
+CONFIG_MIKROTIK_RB500=y
+CONFIG_MINI_FO=m
+CONFIG_MIPS=y
+# CONFIG_MIPS_ATLAS is not set
+# CONFIG_MIPS_COBALT is not set
+CONFIG_MIPS_L1_CACHE_SHIFT=4
+# CONFIG_MIPS_MALTA is not set
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+# CONFIG_MIPS_SEAD is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_MIPS_UNCACHED is not set
+CONFIG_MTD=y
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_ALAUDA is not set
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_BLOCK2MTD=y
+# CONFIG_MTD_CFI is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CHAR=y
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_CONCAT is not set
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MTDRAM is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_CAFE is not set
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+CONFIG_MTD_NAND_PLATFORM=y
+CONFIG_MTD_NAND_VERIFY_WRITE=y
+# CONFIG_MTD_ONENAND is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_PLATRAM is not set
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_NET_SCH_ESFQ_NFCT is not set
+# CONFIG_NET_VENDOR_3COM is not set
+CONFIG_NF_CONNTRACK=y
+# CONFIG_NO_IOPORT is not set
+# CONFIG_PAGE_SIZE_16KB is not set
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_64KB is not set
+# CONFIG_PAGE_SIZE_8KB is not set
+CONFIG_PCI=y
+# CONFIG_PCIPCWATCHDOG is not set
+# CONFIG_PCI_DEBUG is not set
+CONFIG_PCI_DOMAINS=y
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_PROVE_LOCKING is not set
+CONFIG_RC32434_WDT=y
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RTC is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_RUNTIME_DEBUG is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_SCSI_WAIT_SCAN=m
+# CONFIG_SERIAL_8250_EXTENDED is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_PTSWARM is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_SWARM is not set
+CONFIG_SLABINFO=y
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_SOUND is not set
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SSB_POSSIBLE=y
+CONFIG_SWAP_IO_SPACE=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+# CONFIG_TC35815 is not set
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_TOSHIBA_RBTX4927 is not set
+# CONFIG_TOSHIBA_RBTX4938 is not set
+CONFIG_TRAD_SIGNALS=y
+CONFIG_USB=m
+# CONFIG_USBPCWATCHDOG is not set
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USER_NS is not set
+# CONFIG_VGASTATE is not set
+CONFIG_VIA_RHINE=y
+# CONFIG_VIA_RHINE_MMIO is not set
+CONFIG_VIA_RHINE_NAPI=y
+# CONFIG_YAFFS_9BYTE_TAGS is not set
+CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED=y
+CONFIG_YAFFS_AUTO_YAFFS2=y
+CONFIG_YAFFS_CHECKPOINT_RESERVED_BLOCKS=0
+# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
+# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
+CONFIG_YAFFS_DOES_ECC=y
+CONFIG_YAFFS_ECC_WRONG_ORDER=y
+CONFIG_YAFFS_FS=y
+CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
+CONFIG_YAFFS_YAFFS1=y
+CONFIG_YAFFS_YAFFS2=y
+CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-/*
- * Copyright 2001 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- * stevel@mvista.com or source@mvista.com
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-
-#include <asm/pci.h>
-#include <asm/io.h>
-
-#include <asm/rc32434/rc32434.h>
-
-static int __devinitdata irq_map[2][12] = {
- { 0, 0, 2, 3, 2, 3, 0, 0, 0, 0, 0, 1 },
- { 0, 0, 1, 3, 0, 2, 1, 3, 0, 2, 1, 3 }
-};
-
-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- int irq = 0;
-
- if (dev->bus->number < 2 && PCI_SLOT(dev->devfn) < 12) {
- irq = irq_map[dev->bus->number][PCI_SLOT(dev->devfn)];
- }
- return irq + GROUP4_IRQ_BASE + 4;
-}
-
+++ /dev/null
-/**************************************************************************
- *
- * BRIEF MODULE DESCRIPTION
- * pci_ops for IDT EB434 board
- *
- * Copyright 2004 IDT Inc. (rischelp@idt.com)
- * Copyright 2006 Felix Fietkau <nbd@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- *
- **************************************************************************
- * May 2004 rkt, neb
- *
- * Initial Release
- *
- *
- *
- **************************************************************************
- */
-
-#include <linux/autoconf.h>
-#include <linux/init.h>
-#include <linux/pci.h>
-#include <linux/types.h>
-#include <linux/delay.h>
-
-#include <asm/cpu.h>
-#include <asm/io.h>
-
-#include <asm/rc32434/rc32434.h>
-#include <asm/rc32434/pci.h>
-
-#define PCI_ACCESS_READ 0
-#define PCI_ACCESS_WRITE 1
-
-
-#define PCI_CFG_SET(bus,slot,func,off) \
- (rc32434_pci->pcicfga = (0x80000000 | \
- ((bus) << 16) | ((slot)<<11) | \
- ((func)<<8) | (off)))
-
-static inline int config_access(unsigned char access_type, struct pci_bus *bus,
- unsigned int devfn, unsigned char where,
- u32 * data)
-{
- unsigned int slot = PCI_SLOT(devfn);
- u8 func = PCI_FUNC(devfn);
-
- /* Setup address */
- PCI_CFG_SET(bus->number, slot, func, where);
- rc32434_sync();
-
- if (access_type == PCI_ACCESS_WRITE)
- rc32434_pci->pcicfgd = *data;
- else
- *data = rc32434_pci->pcicfgd;
-
- rc32434_sync();
-
- return 0;
-}
-
-
-/*
- * We can't address 8 and 16 bit words directly. Instead we have to
- * read/write a 32bit word and mask/modify the data we actually want.
- */
-static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
- int where, u8 * val)
-{
- u32 data;
- int ret;
-
- ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
- *val = (data >> ((where & 3) << 3)) & 0xff;
- return ret;
-}
-
-static int read_config_word(struct pci_bus *bus, unsigned int devfn,
- int where, u16 * val)
-{
- u32 data;
- int ret;
-
- ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
- *val = (data >> ((where & 3) << 3)) & 0xffff;
- return ret;
-}
-
-static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
- int where, u32 * val)
-{
- int ret;
- int delay = 1;
-
- if (bus->number == 0 && PCI_SLOT(devfn) > 21)
- return 0;
-
-retry:
- ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val);
-
- /* PCI scan: check for invalid values, device may not have
- * finished initializing */
-
- if (where == PCI_VENDOR_ID) {
- if (ret == 0xffffffff || ret == 0x00000000 ||
- ret == 0x0000ffff || ret == 0xffff0000) {
-
- if (delay > 4)
- return 0;
-
- delay *= 2;
- msleep(delay);
- goto retry;
- }
- }
-
- return ret;
-}
-
-static int
-write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
- u8 val)
-{
- u32 data = 0;
-
- if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
- return -1;
-
- data = (data & ~(0xff << ((where & 3) << 3))) |
- (val << ((where & 3) << 3));
-
- if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
- return -1;
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-
-static int
-write_config_word(struct pci_bus *bus, unsigned int devfn, int where,
- u16 val)
-{
- u32 data = 0;
-
- if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
- return -1;
-
- data = (data & ~(0xffff << ((where & 3) << 3))) |
- (val << ((where & 3) << 3));
-
- if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
- return -1;
-
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-
-static int
-write_config_dword(struct pci_bus *bus, unsigned int devfn, int where,
- u32 val)
-{
- if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
- return -1;
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int pci_config_read(struct pci_bus *bus, unsigned int devfn,
- int where, int size, u32 * val)
-{
- switch (size) {
- case 1:
- return read_config_byte(bus, devfn, where, (u8 *) val);
- case 2:
- return read_config_word(bus, devfn, where, (u16 *) val);
- default:
- return read_config_dword(bus, devfn, where, val);
- }
-}
-
-static int pci_config_write(struct pci_bus *bus, unsigned int devfn,
- int where, int size, u32 val)
-{
- switch (size) {
- case 1:
- return write_config_byte(bus, devfn, where, (u8) val);
- case 2:
- return write_config_word(bus, devfn, where, (u16) val);
- default:
- return write_config_dword(bus, devfn, where, val);
- }
-}
-
-struct pci_ops rc32434_pci_ops = {
- .read = pci_config_read,
- .write = pci_config_write,
-};
+++ /dev/null
-/**************************************************************************
- *
- * BRIEF MODULE DESCRIPTION
- * PCI initialization for IDT EB434 board
- *
- * Copyright 2004 IDT Inc. (rischelp@idt.com)
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- *
- **************************************************************************
- * May 2004 rkt, neb
- *
- * Initial Release
- *
- *
- *
- **************************************************************************
- */
-
-#include <linux/autoconf.h>
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-
-#include <asm/rc32434/rc32434.h>
-#include <asm/rc32434/pci.h>
-
-#define PCI_ACCESS_READ 0
-#define PCI_ACCESS_WRITE 1
-
-/* define an unsigned array for the PCI registers */
-unsigned int korinaCnfgRegs[25] = {
- KORINA_CNFG1, KORINA_CNFG2, KORINA_CNFG3, KORINA_CNFG4,
- KORINA_CNFG5, KORINA_CNFG6, KORINA_CNFG7, KORINA_CNFG8,
- KORINA_CNFG9, KORINA_CNFG10, KORINA_CNFG11, KORINA_CNFG12,
- KORINA_CNFG13, KORINA_CNFG14, KORINA_CNFG15, KORINA_CNFG16,
- KORINA_CNFG17, KORINA_CNFG18, KORINA_CNFG19, KORINA_CNFG20,
- KORINA_CNFG21, KORINA_CNFG22, KORINA_CNFG23, KORINA_CNFG24
-};
-static struct resource rc32434_res_pci_mem1;
-static struct resource rc32434_res_pci_mem2;
-
-static struct resource rc32434_res_pci_mem1 = {
- .name = "PCI MEM1",
- .start = 0x50000000,
- .end = 0x5FFFFFFF,
- .flags = IORESOURCE_MEM,
- .parent = &rc32434_res_pci_mem1,
- .sibling = NULL,
- .child = &rc32434_res_pci_mem2
-};
-
-static struct resource rc32434_res_pci_mem2 = {
- .name = "PCI Mem2",
- .start = 0x60000000,
- .end = 0x6FFFFFFF,
- .flags = IORESOURCE_MEM,
- .parent = &rc32434_res_pci_mem1,
- .sibling = NULL,
- .child = NULL
-};
-
-static struct resource rc32434_res_pci_io1 = {
- .name = "PCI I/O1",
- .start = 0x18800000,
- .end = 0x188FFFFF,
- .flags = IORESOURCE_IO,
-};
-
-extern struct pci_ops rc32434_pci_ops;
-
-#define PCI_MEM1_START PCI_ADDR_START
-#define PCI_MEM1_END PCI_ADDR_START + CPUTOPCI_MEM_WIN - 1
-#define PCI_MEM2_START PCI_ADDR_START + CPUTOPCI_MEM_WIN
-#define PCI_MEM2_END PCI_ADDR_START + ( 2* CPUTOPCI_MEM_WIN) - 1
-#define PCI_IO1_START PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN)
-#define PCI_IO1_END PCI_ADDR_START + (2* CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN -1
-#define PCI_IO2_START PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN
-#define PCI_IO2_END PCI_ADDR_START + (2* CPUTOPCI_MEM_WIN) + (2 * CPUTOPCI_IO_WIN) -1
-
-
-struct pci_controller rc32434_controller2;
-
-struct pci_controller rc32434_controller = {
- .pci_ops = &rc32434_pci_ops,
- .mem_resource = &rc32434_res_pci_mem1,
- .io_resource = &rc32434_res_pci_io1,
- .mem_offset = 0,
- .io_offset = 0,
-
-};
-
-#ifdef __MIPSEB__
-#define PCI_ENDIAN_FLAG PCILBAC_sb_m
-#else
-#define PCI_ENDIAN_FLAG 0
-#endif
-
-static int __init rc32434_pcibridge_init(void)
-{
- unsigned int pcicValue, pcicData = 0;
- unsigned int dummyRead, pciCntlVal;
- int loopCount;
- unsigned int pciConfigAddr;
-
- pcicValue = rc32434_pci->pcic;
- pcicValue = (pcicValue >> PCIM_SHFT) & PCIM_BIT_LEN;
- if (!((pcicValue == PCIM_H_EA) ||
- (pcicValue == PCIM_H_IA_FIX) ||
- (pcicValue == PCIM_H_IA_RR))) {
- printk("PCI init error!!!\n");
- /* Not in Host Mode, return ERROR */
- return -1;
- }
- /* Enables the Idle Grant mode, Arbiter Parking */
- pcicData |=(PCIC_igm_m|PCIC_eap_m|PCIC_en_m);
- rc32434_pci->pcic = pcicData; /* Enable the PCI bus Interface */
- /* Zero out the PCI status & PCI Status Mask */
- for(;;)
- {
- pcicData = rc32434_pci->pcis;
- if (!(pcicData & PCIS_rip_m))
- break;
- }
-
- rc32434_pci->pcis = 0;
- rc32434_pci->pcism = 0xFFFFFFFF;
- /* Zero out the PCI decoupled registers */
- rc32434_pci->pcidac=0; /* disable PCI decoupled accesses at initialization */
- rc32434_pci->pcidas=0; /* clear the status */
- rc32434_pci->pcidasm=0x0000007F; /* Mask all the interrupts */
- /* Mask PCI Messaging Interrupts */
- rc32434_pci_msg->pciiic = 0;
- rc32434_pci_msg->pciiim = 0xFFFFFFFF;
- rc32434_pci_msg->pciioic = 0;
- rc32434_pci_msg->pciioim = 0;
-
-
- /* Setup PCILB0 as Memory Window */
- rc32434_pci->pcilba[0].a = (unsigned int) (PCI_ADDR_START);
-
- /* setup the PCI map address as same as the local address */
-
- rc32434_pci->pcilba[0].m = (unsigned int) (PCI_ADDR_START);
-
-
- /* Setup PCILBA1 as MEM */
- rc32434_pci->pcilba[0].c = ( ((SIZE_256MB & 0x1f) << PCILBAC_size_b) | PCI_ENDIAN_FLAG);
- dummyRead = rc32434_pci->pcilba[0].c; /* flush the CPU write Buffers */
- rc32434_pci->pcilba[1].a = 0x60000000;
- rc32434_pci->pcilba[1].m = 0x60000000;
-
- /* setup PCILBA2 as IO Window*/
- rc32434_pci->pcilba[1].c = (((SIZE_256MB & 0x1f) << PCILBAC_size_b )| PCI_ENDIAN_FLAG);
- dummyRead = rc32434_pci->pcilba[1].c; /* flush the CPU write Buffers */
- rc32434_pci->pcilba[2].a = 0x18C00000;
- rc32434_pci->pcilba[2].m = 0x18FFFFFF;
-
- /* setup PCILBA2 as IO Window*/
- rc32434_pci->pcilba[2].c = (((SIZE_4MB & 0x1f) << PCILBAC_size_b) | PCI_ENDIAN_FLAG );
- dummyRead = rc32434_pci->pcilba[2].c; /* flush the CPU write Buffers */
-
- /* Setup PCILBA3 as IO Window */
- rc32434_pci->pcilba[3].a = 0x18800000;
- rc32434_pci->pcilba[3].m = 0x18800000;
- rc32434_pci->pcilba[3].c = ( (((SIZE_1MB & 0x1ff) << PCILBAC_size_b) | PCILBAC_msi_m) | PCI_ENDIAN_FLAG);
- dummyRead = rc32434_pci->pcilba[3].c; /* flush the CPU write Buffers */
-
- pciConfigAddr=(unsigned int)(0x80000004);
- for(loopCount=0;loopCount<24;loopCount++){
- rc32434_pci->pcicfga=pciConfigAddr;
- dummyRead=rc32434_pci->pcicfga;
- rc32434_pci->pcicfgd = korinaCnfgRegs[loopCount];
- dummyRead=rc32434_pci->pcicfgd;
- pciConfigAddr += 4;
- }
- rc32434_pci->pcitc = (unsigned int)((PCITC_RTIMER_VAL&0xff) << PCITC_rtimer_b)
- | ((PCITC_DTIMER_VAL&0xff) << PCITC_dtimer_b);
-
- pciCntlVal=rc32434_pci->pcic;
- pciCntlVal &=~(PCIC_tnr_m);
- rc32434_pci->pcic = pciCntlVal;
- pciCntlVal=rc32434_pci->pcic;
- return 0;
-}
-
-/* Do platform specific device initialization at pci_enable_device() time */
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
- if (PCI_SLOT(dev->devfn) == 6 && dev->bus->number == 0) {
- /* disable prefetched memory range */
- pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0);
- pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0x10);
-
- pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 4);
- }
- return 0;
-}
-
-static int __init rc32434_pci_init(void)
-{
- printk("PCI: Initializing PCI\n");
-
- ioport_resource.start = rc32434_res_pci_io1.start;
- ioport_resource.end = rc32434_res_pci_io1.end;
-
- rc32434_pcibridge_init();
-
- register_pci_controller(&rc32434_controller);
- rc32434_sync();
-
- return 0;
-}
-
-arch_initcall(rc32434_pci_init);
-
+++ /dev/null
-#
-# Makefile for the RB500 board specific parts of the kernel
-#
-
-obj-y += irq.o time.o setup.o serial.o prom.o gpio.o devices.o
+++ /dev/null
-/*
- * RouterBoard 500 Platform devices
- *
- * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
- * Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/ctype.h>
-#include <linux/string.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/nand.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-
-#include <asm/bootinfo.h>
-
-#include <asm/rc32434/rc32434.h>
-#include <asm/rc32434/dma.h>
-#include <asm/rc32434/dma_v.h>
-#include <asm/rc32434/eth.h>
-#include <asm/rc32434/rb.h>
-
-#define ETH0_DMA_RX_IRQ GROUP1_IRQ_BASE + 0
-#define ETH0_DMA_TX_IRQ GROUP1_IRQ_BASE + 1
-#define ETH0_RX_OVR_IRQ GROUP3_IRQ_BASE + 9
-#define ETH0_TX_UND_IRQ GROUP3_IRQ_BASE + 10
-
-#define ETH0_RX_DMA_ADDR (DMA0_PhysicalAddress + 0*DMA_CHAN_OFFSET)
-#define ETH0_TX_DMA_ADDR (DMA0_PhysicalAddress + 1*DMA_CHAN_OFFSET)
-
-/* NAND definitions */
-#define MEM32(x) *((volatile unsigned *) (x))
-
-#define GPIO_RDY (1 << 0x08)
-#define GPIO_WPX (1 << 0x09)
-#define GPIO_ALE (1 << 0x0a)
-#define GPIO_CLE (1 << 0x0b)
-
-extern char* board_type;
-
-static struct resource korina_dev0_res[] = {
- {
- .name = "korina_regs",
- .start = ETH0_PhysicalAddress,
- .end = ETH0_PhysicalAddress + sizeof(ETH_t),
- .flags = IORESOURCE_MEM,
- }, {
- .name = "korina_rx",
- .start = ETH0_DMA_RX_IRQ,
- .end = ETH0_DMA_RX_IRQ,
- .flags = IORESOURCE_IRQ
- }, {
- .name = "korina_tx",
- .start = ETH0_DMA_TX_IRQ,
- .end = ETH0_DMA_TX_IRQ,
- .flags = IORESOURCE_IRQ
- }, {
- .name = "korina_ovr",
- .start = ETH0_RX_OVR_IRQ,
- .end = ETH0_RX_OVR_IRQ,
- .flags = IORESOURCE_IRQ
- }, {
- .name = "korina_und",
- .start = ETH0_TX_UND_IRQ,
- .end = ETH0_TX_UND_IRQ,
- .flags = IORESOURCE_IRQ
- }, {
- .name = "korina_dma_rx",
- .start = ETH0_RX_DMA_ADDR,
- .end = ETH0_RX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .name = "korina_dma_tx",
- .start = ETH0_TX_DMA_ADDR,
- .end = ETH0_TX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
- .flags = IORESOURCE_MEM,
- }
-};
-
-static struct korina_device korina_dev0_data = {
- .name = "korina0",
- .mac = {0xde, 0xca, 0xff, 0xc0, 0xff, 0xee}
-};
-
-static struct platform_device korina_dev0 = {
- .id = 0,
- .name = "korina",
- .dev.platform_data = &korina_dev0_data,
- .resource = korina_dev0_res,
- .num_resources = ARRAY_SIZE(korina_dev0_res),
-};
-
-#define CF_GPIO_NUM 13
-
-static struct resource cf_slot0_res[] = {
- {
- .name = "cf_membase",
- .flags = IORESOURCE_MEM
- }, {
- .name = "cf_irq",
- .start = (8 + 4 * 32 + CF_GPIO_NUM), /* 149 */
- .end = (8 + 4 * 32 + CF_GPIO_NUM),
- .flags = IORESOURCE_IRQ
- }
-};
-
-static struct cf_device cf_slot0_data = {
- .gpio_pin = 13
-};
-
-static struct platform_device cf_slot0 = {
- .id = 0,
- .name = "rb500-cf",
- .dev.platform_data = &cf_slot0_data,
- .resource = cf_slot0_res,
- .num_resources = ARRAY_SIZE(cf_slot0_res),
-};
-
-/* Resources and device for NAND. There is no data needed and no irqs, so just define the memory used. */
-
-/*
- * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader
- * will not be able to find the kernel that we load. So set the oobinfo
- * when creating the partitions
- */
-static struct nand_ecclayout rb500_nand_ecclayout = {
- .eccbytes = 6,
- .eccpos = { 8, 9, 10, 13, 14, 15 },
- .oobavail = 9,
- .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
-};
-
-int rb500_dev_ready(struct mtd_info *mtd)
-{
- return MEM32(IDT434_REG_BASE + GPIOD) & GPIO_RDY;
-}
-
-void rb500_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
- struct nand_chip *chip = mtd->priv;
- unsigned char orbits, nandbits;
-
- if (ctrl & NAND_CTRL_CHANGE) {
-
- orbits = (ctrl & NAND_CLE) << 1;
- orbits |= (ctrl & NAND_ALE) >> 1;
-
- nandbits = (~ctrl & NAND_CLE) << 1;
- nandbits |= (~ctrl & NAND_ALE) >> 1;
-
- changeLatchU5(orbits, nandbits);
- }
- if (cmd != NAND_CMD_NONE)
- writeb(cmd, chip->IO_ADDR_W);
-}
-
-static struct resource nand_slot0_res[] = {
- [0] = {
- .name = "nand_membase",
- .flags = IORESOURCE_MEM
- }
-};
-
-struct platform_nand_data rb500_nand_data = {
- .ctrl.dev_ready = rb500_dev_ready,
- .ctrl.cmd_ctrl = rb500_cmd_ctrl,
-};
-
-static struct platform_device nand_slot0 = {
- .name = "gen_nand",
- .id = -1,
- .resource = nand_slot0_res,
- .num_resources = ARRAY_SIZE(nand_slot0_res),
- .dev.platform_data = &rb500_nand_data,
-};
-
-static struct mtd_partition rb500_partition_info[] = {
- {
- .name = "Routerboard NAND boot",
- .offset = 0,
- .size = 4 * 1024 * 1024,
- }, {
- .name = "rootfs",
- .offset = MTDPART_OFS_NXTBLK,
- .size = MTDPART_SIZ_FULL,
- }
-};
-
-static struct platform_device rb500_led = {
- .name = "rb500-led",
- .id = 0,
-};
-
-static struct gpio_keys_button rb500_gpio_btn[] = {
- {
- .gpio = 1,
- .code = BTN_0,
- .desc = "S1",
- .active_low = 1,
- }
-};
-
-static struct gpio_keys_platform_data rb500_gpio_btn_data = {
- .buttons = rb500_gpio_btn,
- .nbuttons = ARRAY_SIZE(rb500_gpio_btn),
-};
-
-static struct platform_device rb500_button = {
- .name = "gpio-keys",
- .id = -1,
- .dev = {
- .platform_data = &rb500_gpio_btn_data,
- }
-};
-
-static struct platform_device *rb500_devs[] = {
- &korina_dev0,
- &nand_slot0,
- &cf_slot0,
- &rb500_led,
- &rb500_button
-};
-
-static void __init parse_mac_addr(char *macstr)
-{
- int i, j;
- unsigned char result, value;
-
- for (i = 0; i < 6; i++) {
- result = 0;
-
- if (i != 5 && *(macstr + 2) != ':')
- return;
-
- for (j = 0; j < 2; j++) {
- if (isxdigit(*macstr)
- && (value =
- isdigit(*macstr) ? *macstr -
- '0' : toupper(*macstr) - 'A' + 10) < 16) {
- result = result * 16 + value;
- macstr++;
- } else
- return;
- }
-
- macstr++;
- korina_dev0_data.mac[i] = result;
- }
-}
-
-
-/* DEVICE CONTROLLER 1 */
-#define CFG_DC_DEV1 (void*)0xb8010010
-#define CFG_DC_DEV2 (void*)0xb8010020
-#define CFG_DC_DEVBASE 0x0
-#define CFG_DC_DEVMASK 0x4
-#define CFG_DC_DEVC 0x8
-#define CFG_DC_DEVTC 0xC
-
-/* NAND definitions */
-#define NAND_CHIP_DELAY 25
-
-static int rb500_nand_fixup(struct mtd_info *mtd)
-{
- struct nand_chip *chip = mtd->priv;
-
- if (mtd->writesize == 512)
- chip->ecc.layout = &rb500_nand_ecclayout;
-
- return 0;
-}
-
-static void __init rb500_nand_setup(void)
-{
- switch (mips_machtype) {
- case MACH_MIKROTIK_RB532A:
- changeLatchU5(LO_FOFF | LO_CEX, LO_ULED | LO_ALE | LO_CLE | LO_WPX);
- break;
- default:
- changeLatchU5(LO_WPX | LO_FOFF | LO_CEX, LO_ULED | LO_ALE | LO_CLE);
- break;
- }
-
- /* Setup NAND specific settings */
- rb500_nand_data.chip.nr_chips = 1;
- rb500_nand_data.chip.nr_partitions = ARRAY_SIZE(rb500_partition_info);
- rb500_nand_data.chip.partitions = rb500_partition_info;
- rb500_nand_data.chip.chip_delay = NAND_CHIP_DELAY;
- rb500_nand_data.chip.options = NAND_NO_AUTOINCR;
-
- rb500_nand_data.chip.chip_fixup = &rb500_nand_fixup;
-}
-
-
-static int __init plat_setup_devices(void)
-{
- /* Look for the CF card reader */
- if (!readl(CFG_DC_DEV1 + CFG_DC_DEVMASK))
- rb500_devs[1] = NULL;
- else {
- cf_slot0_res[0].start =
- readl(CFG_DC_DEV1 + CFG_DC_DEVBASE);
- cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000;
- }
-
- /* Read the NAND resources from the device controller */
- nand_slot0_res[0].start = readl(CFG_DC_DEV2 + CFG_DC_DEVBASE);
- nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000;
-
- /* Initialise the NAND device */
- rb500_nand_setup();
-
- return platform_add_devices(rb500_devs, ARRAY_SIZE(rb500_devs));
-}
-
-static int __init setup_kmac(char *s)
-{
- printk("korina mac = %s\n", s);
- parse_mac_addr(s);
- return 0;
-}
-
-__setup("kmac=", setup_kmac);
-
-arch_initcall(plat_setup_devices);
+++ /dev/null
-/*
- * Miscellaneous functions for IDT EB434 board
- *
- * Copyright 2004 IDT Inc. (rischelp@idt.com)
- * Copyright 2006 Phil Sutter <n0-1@freewrt.org>
- * Copyright 2007 Florian Fainelli <florian@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/spinlock.h>
-#include <linux/io.h>
-#include <linux/platform_device.h>
-
-#include <asm/addrspace.h>
-#include <asm/gpio.h>
-
-#include <asm/rc32434/rb.h>
-
-#define GPIO_BADDR 0x18050000
-
-static volatile unsigned char *devCtl3Base;
-static unsigned char latchU5State;
-static spinlock_t clu5Lock = SPIN_LOCK_UNLOCKED;
-
-struct rb500_gpio_reg __iomem *rb500_gpio_reg0;
-EXPORT_SYMBOL(rb500_gpio_reg0);
-
-static struct resource rb500_gpio_reg0_res[] = {
- {
- .name = "gpio_reg0",
- .start = GPIO_BADDR,
- .end = GPIO_BADDR + sizeof(struct rb500_gpio_reg),
- .flags = IORESOURCE_MEM,
- }
-};
-
-void set434Reg(unsigned regOffs, unsigned bit, unsigned len, unsigned val)
-{
- unsigned flags, data;
- unsigned i = 0;
-
- spin_lock_irqsave(&clu5Lock, flags);
- data = *(volatile unsigned *) (IDT434_REG_BASE + regOffs);
- for (i = 0; i != len; ++i) {
- if (val & (1 << i))
- data |= (1 << (i + bit));
- else
- data &= ~(1 << (i + bit));
- }
- *(volatile unsigned *) (IDT434_REG_BASE + regOffs) = data;
- spin_unlock_irqrestore(&clu5Lock, flags);
-}
-EXPORT_SYMBOL(set434Reg);
-
-void changeLatchU5(unsigned char orMask, unsigned char nandMask)
-{
- unsigned flags;
-
- spin_lock_irqsave(&clu5Lock, flags);
- latchU5State = (latchU5State | orMask) & ~nandMask;
- if (!devCtl3Base)
- devCtl3Base = (volatile unsigned char *)
- KSEG1ADDR(*(volatile unsigned *)
- KSEG1ADDR(0x18010030));
- *devCtl3Base = latchU5State;
- spin_unlock_irqrestore(&clu5Lock, flags);
-}
-EXPORT_SYMBOL(changeLatchU5);
-
-unsigned char getLatchU5State(void)
-{
- return latchU5State;
-}
-EXPORT_SYMBOL(getLatchU5State);
-
-int rb500_gpio_get_value(unsigned gpio)
-{
- return readl(&rb500_gpio_reg0->gpiod) & (1 << gpio);
-}
-EXPORT_SYMBOL(rb500_gpio_get_value);
-
-void rb500_gpio_set_value(unsigned gpio, int value)
-{
- unsigned tmp;
-
- tmp = readl(&rb500_gpio_reg0->gpiod) & ~(1 << gpio);
- if (value)
- tmp |= 1 << gpio;
-
- writel(tmp, (void *)&rb500_gpio_reg0->gpiod);
-}
-EXPORT_SYMBOL(rb500_gpio_set_value);
-
-int rb500_gpio_direction_input(unsigned gpio)
-{
- writel(readl(&rb500_gpio_reg0->gpiocfg) & ~(1 << gpio), (void *)&rb500_gpio_reg0->gpiocfg);
-
- return 0;
-}
-EXPORT_SYMBOL(rb500_gpio_direction_input);
-
-int rb500_gpio_direction_output(unsigned gpio, int value)
-{
- gpio_set_value(gpio, value);
- writel(readl(&rb500_gpio_reg0->gpiocfg) | (1 << gpio), (void *)&rb500_gpio_reg0->gpiocfg);
-
- return 0;
-}
-EXPORT_SYMBOL(rb500_gpio_direction_output);
-
-void rb500_gpio_set_int_level(unsigned gpio, int value)
-{
- unsigned tmp;
-
- tmp = readl(&rb500_gpio_reg0->gpioilevel) & ~(1 << gpio);
- if (value)
- tmp |= 1 << gpio;
- writel(tmp, (void *)&rb500_gpio_reg0->gpioilevel);
-}
-EXPORT_SYMBOL(rb500_gpio_set_int_level);
-
-int rb500_gpio_get_int_level(unsigned gpio)
-{
- return readl(&rb500_gpio_reg0->gpioilevel) & (1 << gpio);
-}
-EXPORT_SYMBOL(rb500_gpio_get_int_level);
-
-void rb500_gpio_set_int_status(unsigned gpio, int value)
-{
- unsigned tmp;
-
- tmp = readl(&rb500_gpio_reg0->gpioistat);
- if (value)
- tmp |= 1 << gpio;
- writel(tmp, (void *)&rb500_gpio_reg0->gpioistat);
-}
-EXPORT_SYMBOL(rb500_gpio_set_int_status);
-
-int rb500_gpio_get_int_status(unsigned gpio)
-{
- return readl(&rb500_gpio_reg0->gpioistat) & (1 << gpio);
-}
-EXPORT_SYMBOL(rb500_gpio_get_int_status);
-
-void rb500_gpio_set_func(unsigned gpio, int value)
-{
- unsigned tmp;
-
- tmp = readl(&rb500_gpio_reg0->gpiofunc);
- if (value)
- tmp |= 1 << gpio;
- writel(tmp, (void *)&rb500_gpio_reg0->gpiofunc);
-}
-EXPORT_SYMBOL(rb500_gpio_set_func);
-
-int rb500_gpio_get_func(unsigned gpio)
-{
- return readl(&rb500_gpio_reg0->gpiofunc) & (1 << gpio);
-}
-EXPORT_SYMBOL(rb500_gpio_get_func);
-
-int __init rb500_gpio_init(void)
-{
- rb500_gpio_reg0 = ioremap_nocache(rb500_gpio_reg0_res[0].start,
- rb500_gpio_reg0_res[0].end -
- rb500_gpio_reg0_res[0].start);
-
- if (!rb500_gpio_reg0) {
- printk(KERN_ERR "rb500: cannot remap GPIO register 0\n");
- return -ENXIO;
- }
-
- return 0;
-}
-arch_initcall(rb500_gpio_init);
+++ /dev/null
-/*
- * BRIEF MODULE DESCRIPTION
- * RC32434 interrupt routines.
- *
- * Copyright 2002 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- * stevel@mvista.com or source@mvista.com
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/kernel_stat.h>
-#include <linux/module.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/timex.h>
-#include <linux/slab.h>
-#include <linux/random.h>
-#include <linux/delay.h>
-
-#include <asm/bitops.h>
-#include <asm/bootinfo.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/time.h>
-#include <asm/mipsregs.h>
-#include <asm/system.h>
-#include <asm/rc32434/rc32434.h>
-#include <asm/rc32434/gpio.h>
-
-extern void set_debug_traps(void);
-extern irq_cpustat_t irq_stat [NR_CPUS];
-unsigned int local_bh_count[NR_CPUS];
-unsigned int local_irq_count[NR_CPUS];
-
-static unsigned int startup_irq(unsigned int irq);
-static void rb500_end_irq(unsigned int irq_nr);
-static void mask_and_ack_irq(unsigned int irq_nr);
-static void rb500_enable_irq(unsigned int irq_nr);
-static void rb500_disable_irq(unsigned int irq_nr);
-
-extern void __init init_generic_irq(void);
-extern struct rb500_gpio_reg __iomem *rb500_gpio_reg0;
-
-typedef struct {
- u32 mask; /* mask of valid bits in pending/mask registers */
- volatile u32 *base_addr;
-} intr_group_t;
-
-#define RC32434_NR_IRQS (GROUP4_IRQ_BASE + 32)
-
-#if (NR_IRQS < RC32434_NR_IRQS)
-#error Too little irqs defined. Did you override <asm/irq.h> ?
-#endif
-
-static const intr_group_t intr_group[NUM_INTR_GROUPS] = {
- { 0x0000efff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET) },
- { 0x00001fff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET) },
- { 0x00000007, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET) },
- { 0x0003ffff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET) },
- { 0xffffffff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET) }
-};
-
-#define READ_PEND(base) (*(base))
-#define READ_MASK(base) (*(base + 2))
-#define WRITE_MASK(base, val) (*(base + 2) = (val))
-
-static inline int irq_to_group(unsigned int irq_nr)
-{
- return ((irq_nr - GROUP0_IRQ_BASE) >> 5);
-}
-
-static inline int group_to_ip(unsigned int group)
-{
- return group + 2;
-}
-
-static inline void enable_local_irq(unsigned int ip)
-{
- int ipnum = 0x100 << ip;
- clear_c0_cause(ipnum);
- set_c0_status(ipnum);
-}
-
-static inline void disable_local_irq(unsigned int ip)
-{
- int ipnum = 0x100 << ip;
- clear_c0_status(ipnum);
-}
-
-static inline void ack_local_irq(unsigned int ip)
-{
- int ipnum = 0x100 << ip;
- clear_c0_cause(ipnum);
-}
-
-static void rb500_enable_irq(unsigned int irq_nr)
-{
- int ip = irq_nr - GROUP0_IRQ_BASE;
- unsigned int group, intr_bit;
- volatile unsigned int *addr;
-
-
- if (ip < 0)
- enable_local_irq(irq_nr);
- else {
- group = ip >> 5;
-
- ip &= (1<<5)-1;
- intr_bit = 1 << ip;
-
- enable_local_irq(group_to_ip(group));
-
- addr = intr_group[group].base_addr;
- WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
- }
-}
-
-static void rb500_disable_irq(unsigned int irq_nr)
-{
- int ip = irq_nr - GROUP0_IRQ_BASE;
- unsigned int group, intr_bit, mask;
- volatile unsigned int *addr;
-
- if (ip < 0) {
- disable_local_irq(irq_nr);
- }else{
- group = ip >> 5;
-
- ip &= (1<<5) -1;
- intr_bit = 1 << ip;
- addr = intr_group[group].base_addr;
- mask = READ_MASK(addr);
- mask |= intr_bit;
- WRITE_MASK(addr,mask);
-
- /*
- * if there are no more interrupts enabled in this
- * group, disable corresponding IP
- */
- if (mask == intr_group[group].mask)
- disable_local_irq(group_to_ip(group));
- }
-}
-
-static unsigned int startup_irq(unsigned int irq_nr)
-{
- rb500_enable_irq(irq_nr);
- return 0;
-}
-
-static void shutdown_irq(unsigned int irq_nr)
-{
- rb500_disable_irq(irq_nr);
- return;
-}
-
-static void mask_and_ack_irq(unsigned int irq_nr)
-{
- rb500_disable_irq(irq_nr);
- ack_local_irq(group_to_ip(irq_to_group(irq_nr)));
-}
-
-static void rb500_end_irq(unsigned int irq_nr)
-{
-
- int ip = irq_nr - GROUP0_IRQ_BASE;
- unsigned int intr_bit, group;
- volatile unsigned int *addr;
-
- if ((irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
- printk("warning: end_irq %d did not enable (%x)\n",
- irq_nr, irq_desc[irq_nr].status);
- return;
- }
-
- if (ip < 0) {
- enable_local_irq(irq_nr);
- } else {
- group = ip >> 5;
-
- ip &= (1 << 5) - 1;
- intr_bit = 1 << ip;
-
- if (irq_nr >= GROUP4_IRQ_BASE && irq_nr <= (GROUP4_IRQ_BASE + 13)) {
- rb500_gpio_reg0->gpioistat = rb500_gpio_reg0->gpioistat & ~intr_bit;
- }
-
- enable_local_irq(group_to_ip(group));
-
- addr = intr_group[group].base_addr;
- WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
- }
-}
-
-static struct hw_interrupt_type rc32434_irq_type = {
- .typename = "RB500",
- .startup = startup_irq,
- .shutdown = shutdown_irq,
- .enable = rb500_enable_irq,
- .disable = rb500_disable_irq,
- .ack = mask_and_ack_irq,
- .end = rb500_end_irq,
-};
-
-
-void __init arch_init_irq(void)
-{
- int i;
-
- printk("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS);
- memset(irq_desc, 0, sizeof(irq_desc));
-
- for (i = 0; i < RC32434_NR_IRQS; i++) {
- irq_desc[i].status = IRQ_DISABLED;
- irq_desc[i].action = NULL;
- irq_desc[i].depth = 1;
- irq_desc[i].chip = &rc32434_irq_type;
- spin_lock_init(&irq_desc[i].lock);
- }
-}
-
-/* Main Interrupt dispatcher */
-asmlinkage void plat_irq_dispatch(void)
-{
- unsigned int ip, pend, group;
- volatile unsigned int *addr;
- unsigned int cp0_cause = read_c0_cause() & read_c0_status();
-
- if (cp0_cause & CAUSEF_IP7) {
- do_IRQ(7);
- } else if ((ip = (cp0_cause & 0x7c00))) {
- group = 21 - rc32434_clz(ip);
-
- addr = intr_group[group].base_addr;
-
- pend = READ_PEND(addr);
- pend &= ~READ_MASK(addr); // only unmasked interrupts
- pend = 39 - rc32434_clz(pend);
- do_IRQ((group << 5) + pend);
- }
-}
+++ /dev/null
-/*
-* prom.c
-**********************************************************************
-* P . Sadik Oct 10, 2003
-*
-* Started change log
-* idt_cpu_freq is make a kernel configuration parameter
-* idt_cpu_freq is exported so that other modules can use it.
-* Code cleanup
-**********************************************************************
-* P. Sadik Oct 20, 2003
-*
-* Removed NVRAM code from here, since they are already available under
-* nvram directory.
-* Added serial port initialisation.
-**********************************************************************
-**********************************************************************
-* P. Sadik Oct 30, 2003
-*
-* Added reset_cons_port
-**********************************************************************
-
- P.Christeas, 2005-2006
- Port to 2.6, add 2.6 cmdline parsing
-
-*/
-
-#include <linux/autoconf.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/string.h>
-#include <linux/console.h>
-#include <asm/bootinfo.h>
-#include <linux/bootmem.h>
-#include <linux/ioport.h>
-#include <linux/blkdev.h>
-#include <asm/rc32434/ddr.h>
-
-#define PROM_ENTRY(x) (0xbfc00000+((x)*8))
-extern void __init setup_serial_port(void);
-
-unsigned int idt_cpu_freq = 132000000;
-EXPORT_SYMBOL(idt_cpu_freq);
-unsigned int gpio_bootup_state = 0;
-EXPORT_SYMBOL(gpio_bootup_state);
-
-char mips_mac_address[18] = "08:00:06:05:40:01";
-EXPORT_SYMBOL(mips_mac_address);
-
-/* what to append to cmdline when button is [not] pressed */
-#define GPIO_INIT_NOBUTTON ""
-#define GPIO_INIT_BUTTON " 2"
-
-#ifdef CONFIG_MIKROTIK_RB500
-unsigned soft_reboot = 0;
-EXPORT_SYMBOL(soft_reboot);
-#endif
-
-#define SR_NMI 0x00180000 /* NMI */
-#define SERIAL_SPEED_ENTRY 0x00000001
-
-#ifdef CONFIG_REMOTE_DEBUG
-extern int remote_debug;
-#endif
-
-#define FREQ_TAG "HZ="
-#define GPIO_TAG "gpio="
-#define KMAC_TAG "kmac="
-#define MEM_TAG "mem="
-#define BOARD_TAG "board="
-#define IGNORE_CMDLINE_MEM 1
-#define DEBUG_DDR
-
-#define BOARD_RB532 "500"
-#define BOARD_RB532A "500r5"
-
-void parse_soft_settings(unsigned *ptr, unsigned size);
-void parse_hard_settings(unsigned *ptr, unsigned size);
-
-void __init prom_setup_cmdline(void);
-
-void __init prom_init(void)
-{
- DDR_t ddr = (DDR_t) DDR_VirtualAddress; /* define the pointer to the DDR registers */
- phys_t memsize = 0-ddr->ddrmask;
-
- /* this should be the very first message, even before serial is properly initialized */
- prom_setup_cmdline();
- setup_serial_port();
-
- soft_reboot = read_c0_status() & SR_NMI;
- pm_power_off = NULL;
-
- /*
- * give all RAM to boot allocator,
- * except for the first 0x400 and the last 0x200 bytes
- */
- add_memory_region(ddr->ddrbase + 0x400, memsize - 0x600, BOOT_MEM_RAM);
-}
-
-void __init prom_free_prom_memory(void)
-{
- /* No prom memory to free */
-}
-
-static inline int match_tag(char *arg, const char *tag)
-{
- return (strncmp(arg, tag, strlen(tag)) == 0);
-}
-
-static inline unsigned long tag2ul(char *arg, const char *tag)
-{
- char *num = arg+strlen(tag);
- return simple_strtoul(num, 0, 10);
-}
-
-extern char _image_cmdline;
-void __init prom_setup_cmdline(void){
- char cmd_line[CL_SIZE];
- char *cp;
- int prom_argc;
- char **prom_argv, **prom_envp;
- int i;
-
- prom_argc = fw_arg0;
- prom_argv = (char **) fw_arg1;
- prom_envp = (char **) fw_arg2;
-
- cp=cmd_line;
- /* Note: it is common that parameters start at argv[1] and not argv[0],
- however, our elf loader starts at [0] */
- for(i=0;i<prom_argc;i++){
- if (match_tag(prom_argv[i], FREQ_TAG)) {
- idt_cpu_freq = tag2ul(prom_argv[i], FREQ_TAG);
- continue;
- }
-#ifdef IGNORE_CMDLINE_MEM
- /* parses out the "mem=xx" arg */
- if (match_tag(prom_argv[i], MEM_TAG)) {
- continue;
- }
-#endif
- if (i>0) *(cp++) = ' ';
- if (match_tag(prom_argv[i], BOARD_TAG)) {
- char *board = prom_argv[i] + strlen(BOARD_TAG);
- if (match_tag(board, BOARD_RB532A))
- mips_machtype = MACH_MIKROTIK_RB532A;
- else
- mips_machtype = MACH_MIKROTIK_RB532;
- }
-
- if (match_tag(prom_argv[i], GPIO_TAG)) {
- gpio_bootup_state = tag2ul(prom_argv[i], GPIO_TAG);
- }
- strcpy(cp,prom_argv[i]);
- cp+=strlen(prom_argv[i]);
- }
- *(cp++) = ' ';
- strcpy(cp,(&_image_cmdline + 8));
- cp += strlen(&_image_cmdline);
-
- i=strlen(arcs_cmdline);
- if (i>0){
- *(cp++) = ' ';
- strcpy(cp,arcs_cmdline);
- cp+=strlen(arcs_cmdline);
- }
- if (gpio_bootup_state&0x02)
- strcpy(cp,GPIO_INIT_NOBUTTON);
- else
- strcpy(cp,GPIO_INIT_BUTTON);
- cmd_line[CL_SIZE-1] = '\0';
-
- strcpy(arcs_cmdline,cmd_line);
-}
-
+++ /dev/null
-/**************************************************************************
- *
- * BRIEF MODULE DESCRIPTION
- * Serial port initialisation.
- *
- * Copyright 2004 IDT Inc. (rischelp@idt.com)
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- *
- **************************************************************************
- * May 2004 rkt, neb
- *
- * Initial Release
- *
- *
- *
- **************************************************************************
- */
-
-
-#include <linux/autoconf.h>
-#include <linux/init.h>
-#include <linux/sched.h>
-#include <linux/pci.h>
-#include <linux/interrupt.h>
-#include <linux/tty.h>
-#include <linux/serial.h>
-#include <linux/serial_core.h>
-#include <linux/serial_8250.h>
-
-#include <asm/time.h>
-#include <asm/cpu.h>
-#include <asm/bootinfo.h>
-#include <asm/irq.h>
-#include <asm/serial.h>
-#include <asm/rc32434/rc32434.h>
-
-extern unsigned int idt_cpu_freq;
-
-static struct uart_port serial_req = {
- .type = PORT_16550A,
- .line = 0,
- .irq = RC32434_UART0_IRQ,
- //.flags = STD_COM_FLAGS,
- .iotype = UPIO_MEM,
- .membase = (char *) KSEG1ADDR(RC32434_UART0_BASE),
-// .fifosize = 14
- .regshift = 2
-};
-
-int __init setup_serial_port(void)
-{
- serial_req.uartclk = idt_cpu_freq;
-
- if (early_serial_setup(&serial_req))
- return -ENODEV;
-
- return(0);
-}
+++ /dev/null
-/*
- * setup.c - boot time setup code
- */
-
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/irq.h>
-#include <linux/ioport.h>
-#include <linux/pm.h>
-#include <asm/bootinfo.h>
-#include <asm/mipsregs.h>
-#include <asm/pgtable.h>
-#include <asm/reboot.h>
-#include <asm/addrspace.h> /* for KSEG1ADDR() */
-#include <asm/time.h>
-#include <asm/io.h>
-#include <asm/rc32434/rc32434.h>
-#include <asm/rc32434/pci.h>
-
-#ifdef CONFIG_PCI
-extern void rc32434_time_init(void);
-extern int __init rc32434_pcibridge_init(void);
-#endif
-
-#define epldMask ((volatile unsigned char *)0xB900000d)
-
-static void rb_machine_restart(char *command)
-{
- /* just jump to the reset vector */
- * (volatile unsigned *) KSEG1ADDR(0x18008000) = 0x80000001;
- ((void (*)(void))KSEG1ADDR(0x1FC00000u))();
-}
-
-static void rb_machine_halt(void)
-{
- for(;;) continue;
-}
-
-#ifdef CONFIG_CPU_HAS_WB
-void (*__wbflush) (void);
-
-static void rb_write_buffer_flush(void)
-{
- __asm__ __volatile__
- ("sync\n\t" "nop\n\t" "loop: bc0f loop\n\t" "nop\n\t");
-}
-#endif
-
-void __init plat_mem_setup(void)
-{
- unsigned int pciCntlVal;
-
- //board_time_init = rc32434_time_init;
-
-#ifdef CONFIG_CPU_HAS_WB
- __wbflush = rb_write_buffer_flush;
-#endif
- _machine_restart = rb_machine_restart;
- _machine_halt = rb_machine_halt;
- /*_machine_power_off = rb_machine_power_halt;*/
- pm_power_off = rb_machine_halt;
-
- set_io_port_base(KSEG1);
-
- pciCntlVal=rc32434_pci->pcic;
- pciCntlVal &= 0xFFFFFF7;
- rc32434_pci->pcic = pciCntlVal;
-
-#ifdef CONFIG_PCI
- /* Enable PCI interrupts in EPLD Mask register */
- *epldMask = 0x0;
- *(epldMask + 1) = 0x0;
-#endif
- write_c0_wired(0);
-}
-
-const char *get_system_type(void)
-{
- return "MIPS RB500";
-}
+++ /dev/null
-/*
-****************************************************************************
-* Carsten Langgaard, carstenl@mips.com
-* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
-*
-***************************************************************************
-*
-* This program is free software; you can distribute it and/or modify it
-* under the terms of the GNU General Public License (Version 2) as
-* published by the Free Software Foundation.
-*
-* This program is distributed in the hope it will be useful, but WITHOUT
-* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-* for more details.
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, write to the Free Software Foundation, Inc.,
-* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
-*
-****************************************************************************
-*
-* Setting up the clock on the MIPS boards.
-*
-****************************************************************************
-* P. Sadik Oct 10, 2003
-*
-* Started change log.
-* mips_counter_frequency is now calculated at run time, based on idt_cpu_freq.
-* Code cleanup
-****************************************************************************
-*/
-
-#include <linux/autoconf.h>
-#include <linux/init.h>
-#include <linux/kernel_stat.h>
-#include <linux/sched.h>
-#include <linux/spinlock.h>
-#include <linux/mc146818rtc.h>
-#include <linux/irq.h>
-#include <linux/timex.h>
-
-#include <asm/irq_cpu.h>
-#include <asm/mipsregs.h>
-#include <asm/ptrace.h>
-#include <asm/debug.h>
-#include <asm/rc32434/rc32434.h>
-
-static unsigned long r4k_offset; /* Amount to incr compare reg each time */
-extern unsigned int mips_hpt_frequency;
-extern unsigned int idt_cpu_freq;
-
-/*
- * Figure out the r4k offset, the amount to increment the compare
- * register for each time tick. There is no RTC available.
- *
- * The RC32434 counts at half the CPU *core* speed.
- */
-static unsigned long __init cal_r4koff(void)
-{
- mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
- return (mips_hpt_frequency / HZ);
-}
-
-
-void __init plat_time_init(void)
-{
- unsigned int est_freq, flags;
-
- local_irq_save(flags);
-
- printk("calculating r4koff... ");
- r4k_offset = cal_r4koff();
- printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
-
- est_freq = 2*r4k_offset*HZ;
- est_freq += 5000; /* round */
- est_freq -= est_freq%10000;
- printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
- (est_freq%1000000)*100/1000000);
- local_irq_restore(flags);
-}
+++ /dev/null
-## Makefile for the RB532 CF port
-
-obj-y += bdev.o ata.o
+++ /dev/null
-/* CF-mips driver
- This is a block driver for the direct (mmaped) interface to the CF-slot,
- found in Routerboard.com's RB532 board
- See SDK provided from routerboard.com.
-
- Module adapted By P.Christeas <p_christeas@yahoo.com>, 2005-6.
- Cleaned up and adapted to platform_device by Felix Fietkau <nbd@openwrt.org>
-
- This work is redistributed under the terms of the GNU General Public License.
-*/
-
-#include <linux/kernel.h> /* printk() */
-#include <linux/module.h> /* module to be loadable */
-#include <linux/delay.h>
-#include <linux/sched.h>
-#include <linux/pci.h>
-#include <linux/ioport.h> /* request_mem_region() */
-
-#include <asm/gpio.h>
-#include <asm/unaligned.h> /* ioremap() */
-#include <asm/io.h> /* ioremap() */
-#include <asm/rc32434/rb.h>
-
-#include "ata.h"
-
-#define REQUEST_MEM_REGION 0
-#define DEBUG 1
-
-#if DEBUG
-#define DEBUGP printk
-#else
-#define DEBUGP(format, args...)
-#endif
-
-#define SECS 1000000 /* unit for wait_not_busy() is 1us */
-
-unsigned cf_head = 0;
-unsigned cf_cyl = 0;
-unsigned cf_spt = 0;
-unsigned cf_sectors = 0;
-static unsigned cf_block_size = 1;
-static void *baddr = 0;
-
-#define DBUF32 ((volatile u32 *)((unsigned long)dev->baddr | ATA_DBUF_OFFSET))
-
-
-static void cf_do_tasklet(unsigned long dev_l);
-
-
-static inline void wareg(u8 val, unsigned reg, struct cf_mips_dev* dev)
-{
- writeb(val, dev->baddr + ATA_REG_OFFSET + reg);
-}
-
-static inline u8 rareg(unsigned reg, struct cf_mips_dev* dev)
-{
- return readb(dev->baddr + ATA_REG_OFFSET + reg);
-}
-
-static inline int cfrdy(struct cf_mips_dev *dev)
-{
- return gpio_get_value(dev->pin);
-}
-
-static inline void prepare_cf_irq(struct cf_mips_dev *dev)
-{
- rb500_gpio_set_int_level(1, dev->pin); /* interrupt on cf ready (not busy) */
- rb500_gpio_set_int_status(0, dev->pin); /* clear interrupt status */
-}
-
-static inline int cf_present(struct cf_mips_dev* dev)
-{
- /* TODO: read and configure CIS into memory mapped mode
- * TODO: parse CISTPL_CONFIG on CF+ cards to get base address (0x200)
- * TODO: maybe adjust power saving setting for Hitachi Microdrive
- */
- int i;
-
- /* setup CFRDY GPIO as input */
- rb500_gpio_set_func(dev->pin, 0);
- gpio_direction_input(dev->pin);
-
- for (i = 0; i < 0x10; ++i) {
- if (rareg(i,dev) != 0xff)
- return 1;
- }
- return 0;
-}
-
-static inline int is_busy(struct cf_mips_dev *dev)
-{
- return !cfrdy(dev);
-}
-
-static int wait_not_busy(int to_us, int wait_for_busy,struct cf_mips_dev *dev)
-{
- int us_passed = 0;
- if (wait_for_busy && !is_busy(dev)) {
- /* busy must appear within 400ns,
- * but it may dissapear before we see it
- * => must not wait for busy in a loop
- */
- ndelay(400);
- }
-
- do {
- if (us_passed)
- udelay(1); /* never reached in async mode */
- if (!is_busy(dev)) {
- if (us_passed > 1 * SECS) {
- printk(KERN_WARNING "cf-mips: not busy ok (after %dus)"
- ", status 0x%02x\n", us_passed, (unsigned) rareg(ATA_REG_ST,dev));
- }
- return CF_TRANS_OK;
- }
- if (us_passed == 1 * SECS) {
- printk(KERN_WARNING "cf-mips: wait not busy %dus..\n", to_us);
- }
- if (dev->async_mode) {
- dev->to_timer.expires = jiffies + (to_us * HZ / SECS);
- dev->irq_enable_time = jiffies;
- prepare_cf_irq(dev);
- if (is_busy(dev)) {
- add_timer(&dev->to_timer);
- enable_irq(dev->irq);
- return CF_TRANS_IN_PROGRESS;
- }
- continue;
- }
- ++us_passed;
- } while (us_passed < to_us);
-
- printk(KERN_ERR "cf-mips: wait not busy timeout (%dus)"
- ", status 0x%02x, state %d\n",
- to_us, (unsigned) rareg(ATA_REG_ST,dev), dev->tstate);
- return CF_TRANS_FAILED;
-}
-
-static irqreturn_t cf_irq_handler(int irq, void *dev_id)
-{
- /* While tasklet has not disabled irq, irq will be retried all the time
- * because of ILEVEL matching GPIO pin status => deadlock.
- * To avoid this, we change ILEVEL to 0.
- */
- struct cf_mips_dev *dev=dev_id;
-
- rb500_gpio_set_int_level(0, dev->pin);
- rb500_gpio_set_int_status(0, dev->pin);
-
- del_timer(&dev->to_timer);
- tasklet_schedule(&dev->tasklet);
- return IRQ_HANDLED;
-}
-
-static int do_reset(struct cf_mips_dev *dev)
-{
- printk(KERN_INFO "cf-mips: resetting..\n");
-
- wareg(ATA_REG_DC_SRST, ATA_REG_DC,dev);
- udelay(1); /* FIXME: how long should we wait here? */
- wareg(0, ATA_REG_DC,dev);
-
- return wait_not_busy(30 * SECS, 1,dev);
-}
-
-static int set_multiple(struct cf_mips_dev *dev)
-{
- if (dev->block_size <= 1)
- return CF_TRANS_OK;
-
- wareg(dev->block_size, ATA_REG_SC,dev);
- wareg(ATA_REG_DH_BASE | ATA_REG_DH_LBA, ATA_REG_DH,dev);
- wareg(ATA_CMD_SET_MULTIPLE, ATA_REG_CMD,dev);
-
- return wait_not_busy(10 * SECS, 1,dev);
-}
-
-static int set_cmd(struct cf_mips_dev *dev)
-{
- //DEBUGP(KERN_INFO "cf-mips: ata cmd 0x%02x\n", dev->tcmd);
- // sector_count should be <=24 bits..
- BUG_ON(dev->tsect_start>=0x10000000);
- // This way, it addresses 2^24 * 512 = 128G
-
- if (dev->tsector_count) {
- wareg(dev->tsector_count & 0xff, ATA_REG_SC,dev);
- wareg(dev->tsect_start & 0xff, ATA_REG_SN,dev);
- wareg((dev->tsect_start >> 8) & 0xff, ATA_REG_CL,dev);
- wareg((dev->tsect_start >> 16) & 0xff, ATA_REG_CH,dev);
- }
- wareg(((dev->tsect_start >> 24) & 0x0f) | ATA_REG_DH_BASE | ATA_REG_DH_LBA,
- ATA_REG_DH,dev); /* select drive on all commands */
- wareg(dev->tcmd, ATA_REG_CMD,dev);
- return wait_not_busy(10 * SECS, 1,dev);
-}
-
-static int do_trans(struct cf_mips_dev *dev)
-{
- int res;
- unsigned st;
- int transfered;
-
- //printk("do_trans: %d sectors left\n",dev->tsectors_left);
- while (dev->tsectors_left) {
- transfered = 0;
-
- st = rareg(ATA_REG_ST,dev);
- if (!(st & ATA_REG_ST_DRQ)) {
- printk(KERN_ERR "cf-mips: do_trans without DRQ (status 0x%x)!\n", st);
- if (st & ATA_REG_ST_ERR) {
- int errId = rareg(ATA_REG_ERR,dev);
- printk(KERN_ERR "cf-mips: %s error, status 0x%x, errid 0x%x\n",
- (dev->tread ? "read" : "write"), st, errId);
- }
- return CF_TRANS_FAILED;
- }
- do { /* Fill/read the buffer one block */
- u32 *qbuf, *qend;
- qbuf = (u32 *)dev->tbuf;
- qend = qbuf + CF_SECT_SIZE / sizeof(u32);
- if (dev->tread) {
- while (qbuf!=qend)
- put_unaligned(*DBUF32,qbuf++);
- //*(qbuf++) = *DBUF32;
- }
- else {
- while(qbuf!=qend)
- *DBUF32 = get_unaligned(qbuf++);
- }
-
- dev->tsectors_left--;
- dev->tbuf += CF_SECT_SIZE;
- dev->tbuf_size -= CF_SECT_SIZE;
- transfered++;
- } while (transfered != dev->block_size && dev->tsectors_left > 0);
-
- res = wait_not_busy(10 * SECS, 1,dev);
- if (res != CF_TRANS_OK)
- return res;
- };
-
- st = rareg(ATA_REG_ST,dev);
- if (st & (ATA_REG_ST_DRQ | ATA_REG_ST_DWF | ATA_REG_ST_ERR)) {
- if (st & ATA_REG_ST_DRQ) {
- printk(KERN_ERR "cf-mips: DRQ after all %d sectors are %s"
- ", status 0x%x\n", dev->tsector_count, (dev->tread ? "read" : "written"), st);
- } else if (st & ATA_REG_ST_DWF) {
- printk(KERN_ERR "cf-mips: write fault, status 0x%x\n", st);
- } else {
- int errId = rareg(ATA_REG_ERR,dev);
- printk(KERN_ERR "cf-mips: %s error, status 0x%x, errid 0x%x\n",
- (dev->tread ? "read" : "write"), st, errId);
- }
- return CF_TRANS_FAILED;
- }
- return CF_TRANS_OK;
-}
-
-static int cf_do_state(struct cf_mips_dev *dev)
-{
- int res;
- switch (dev->tstate) { /* fall through everywhere */
- case TS_IDLE:
- dev->tstate = TS_READY;
- if (is_busy(dev)) {
- dev->tstate = TS_AFTER_RESET;
- res = do_reset(dev);
- if (res != CF_TRANS_OK)
- break;
- }
- case TS_AFTER_RESET:
- if (dev->tstate == TS_AFTER_RESET) {
- dev->tstate = TS_READY;
- res = set_multiple(dev);
- if (res != CF_TRANS_OK)
- break;
- }
- case TS_READY:
- dev->tstate = TS_CMD;
- res = set_cmd(dev);
- if (res != CF_TRANS_OK)
- break;;
- case TS_CMD:
- dev->tstate = TS_TRANS;
- case TS_TRANS:
- res = do_trans(dev);
- break;
- default:
- printk(KERN_ERR "cf-mips: BUG: unknown tstate %d\n", dev->tstate);
- return CF_TRANS_FAILED;
- }
- if (res != CF_TRANS_IN_PROGRESS)
- dev->tstate = TS_IDLE;
- return res;
-}
-
-static void cf_do_tasklet(unsigned long dev_l)
-{
- struct cf_mips_dev* dev=(struct cf_mips_dev*) dev_l;
- int res;
-
- disable_irq(dev->irq);
-
- if (dev->tstate == TS_IDLE)
- return; /* can happen when irq is first registered */
-
-#if 0
- DEBUGP(KERN_WARNING "cf-mips: not busy ok (tasklet) status 0x%02x\n",
- (unsigned) rareg(ATA_REG_ST,dev));
-#endif
-
- res = cf_do_state(dev);
- if (res == CF_TRANS_IN_PROGRESS)
- return;
- cf_async_trans_done(dev,res);
-}
-
-static void cf_async_timeout(unsigned long dev_l)
-{
- struct cf_mips_dev* dev=(struct cf_mips_dev*) dev_l;
- disable_irq(dev->irq);
- /* Perhaps send abort to the device? */
- printk(KERN_ERR "cf-mips: wait not busy timeout (%lus)"
- ", status 0x%02x, state %d\n",
- jiffies - dev->irq_enable_time, (unsigned) rareg(ATA_REG_ST,dev), dev->tstate);
- dev->tstate = TS_IDLE;
- cf_async_trans_done(dev,CF_TRANS_FAILED);
-}
-
-int cf_do_transfer(struct cf_mips_dev* dev,sector_t sector, unsigned long nsect,
- char* buffer, int is_write)
-{
- BUG_ON(dev->tstate!=TS_IDLE);
- if (nsect > ATA_MAX_SECT_PER_CMD) {
- printk(KERN_WARNING "cf-mips: sector count %lu out of range\n",nsect);
- return CF_TRANS_FAILED;
- }
- if (sector + nsect > dev->sectors) {
- printk(KERN_WARNING "cf-mips: sector %lu out of range\n",sector);
- return CF_TRANS_FAILED;
- }
- dev->tbuf = buffer;
- dev->tbuf_size = nsect*512;
- dev->tsect_start = sector;
- dev->tsector_count = nsect;
- dev->tsectors_left = dev->tsector_count;
- dev->tread = (is_write)?0:1;
-
- dev->tcmd = (dev->block_size == 1 ?
- (is_write ? ATA_CMD_WRITE_SECTORS : ATA_CMD_READ_SECTORS) :
- (is_write ? ATA_CMD_WRITE_MULTIPLE : ATA_CMD_READ_MULTIPLE));
-
- return cf_do_state(dev);
-}
-
-static int do_identify(struct cf_mips_dev *dev)
-{
- u16 sbuf[CF_SECT_SIZE >> 1];
- int res;
- char tstr[17]; //serial
- char tmp;
- int i;
- BUG_ON(dev->tstate!=TS_IDLE);
- dev->tbuf = (char *) sbuf;
- dev->tbuf_size = CF_SECT_SIZE;
- dev->tsect_start = 0;
- dev->tsector_count = 0;
- dev->tsectors_left = 1;
- dev->tread = 1;
- dev->tcmd = ATA_CMD_IDENTIFY_DRIVE;
-
- DEBUGP(KERN_INFO "cf-mips: identify drive..\n");
- res = cf_do_state(dev);
- if (res == CF_TRANS_IN_PROGRESS) {
- printk(KERN_ERR "cf-mips: BUG: async identify cmd\n");
- return CF_TRANS_FAILED;
- }
- if (res != CF_TRANS_OK)
- return 0;
-
- dev->head = sbuf[3];
- dev->cyl = sbuf[1];
- dev->spt = sbuf[6];
- dev->sectors = ((unsigned long) sbuf[7] << 16) | sbuf[8];
- dev->dtype=sbuf[0];
- memcpy(tstr, &sbuf[12], 16);
- tstr[16] = '\0';
-
- /* Byte-swap the serial number */
- for (i = 0; i<8; i++) {
- tmp = tstr[i * 2];
- tstr[i * 2] = tstr[i * 2 +1];
- tstr[i * 2 + 1] = tmp;
- }
-
- printk(KERN_INFO "cf-mips: %s detected, C/H/S=%d/%d/%d sectors=%u (%uMB) Serial=%s\n",
- (sbuf[0] == 0x848A ? "CF card" : "ATA drive"), dev->cyl, dev->head,
- dev->spt, dev->sectors, dev->sectors >> 11, tstr);
- return 1;
-}
-
-static void init_multiple(struct cf_mips_dev * dev)
-{
- int res;
- DEBUGP(KERN_INFO "cf-mips: detecting block size\n");
-
- dev->block_size = 128; /* max block size = 128 sectors (64KB) */
- do {
- wareg(dev->block_size, ATA_REG_SC,dev);
- wareg(ATA_REG_DH_BASE | ATA_REG_DH_LBA, ATA_REG_DH,dev);
- wareg(ATA_CMD_SET_MULTIPLE, ATA_REG_CMD,dev);
-
- res = wait_not_busy(10 * SECS, 1,dev);
- if (res != CF_TRANS_OK) {
- printk(KERN_ERR "cf-mips: failed to detect block size: busy!\n");
- dev->block_size = 1;
- return;
- }
- if ((rareg(ATA_REG_ST,dev) & ATA_REG_ST_ERR) == 0)
- break;
- dev->block_size /= 2;
- } while (dev->block_size > 1);
-
- printk(KERN_INFO "cf-mips: multiple sectors = %d\n", dev->block_size);
-}
-
-int cf_init(struct cf_mips_dev *dev)
-{
- tasklet_init(&dev->tasklet,cf_do_tasklet,(unsigned long)dev);
- dev->baddr = ioremap_nocache((unsigned long)dev->base, CFDEV_BUF_SIZE);
- if (!dev->baddr) {
- printk(KERN_ERR "cf-mips: cf_init: ioremap for (%lx,%x) failed\n",
- (unsigned long) dev->base, CFDEV_BUF_SIZE);
- return -EBUSY;
- }
-
- if (!cf_present(dev)) {
- printk(KERN_WARNING "cf-mips: cf card not present\n");
- iounmap(dev->baddr);
- return -ENODEV;
- }
-
- if (do_reset(dev) != CF_TRANS_OK) {
- printk(KERN_ERR "cf-mips: cf reset failed\n");
- iounmap(dev->baddr);
- return -EBUSY;
- }
-
- if (!do_identify(dev)) {
- printk(KERN_ERR "cf-mips: cf identify failed\n");
- iounmap(dev->baddr);
- return -EBUSY;
- }
-
-/* set_apm_level(ATA_APM_WITH_STANDBY); */
- init_multiple(dev);
-
- init_timer(&dev->to_timer);
- dev->to_timer.function = cf_async_timeout;
- dev->to_timer.data = (unsigned long)dev;
-
- prepare_cf_irq(dev);
- if (request_irq(dev->irq, cf_irq_handler, 0, "CF Mips", dev)) {
- printk(KERN_ERR "cf-mips: failed to get irq\n");
- iounmap(dev->baddr);
- return -EBUSY;
- }
- /* Disable below would be odd, because request will enable, and the tasklet
- will disable it itself */
- //disable_irq(dev->irq);
-
- dev->async_mode = 1;
-
- return 0;
-}
-
-void cf_cleanup(struct cf_mips_dev *dev)
-{
- iounmap(dev->baddr);
- free_irq(dev->irq, NULL);
-#if REQUEST_MEM_REGION
- release_mem_region((unsigned long)dev->base, CFDEV_BUF_SIZE);
-#endif
-}
-
-
-/*eof*/
+++ /dev/null
-/* CF-mips driver
- This is a block driver for the direct (mmaped) interface to the CF-slot,
- found in Routerboard.com's RB532 board
- See SDK provided from routerboard.com.
-
- Module adapted By P.Christeas <p_christeas@yahoo.com>, 2005-6.
- Cleaned up and adapted to platform_device by Felix Fietkau <nbd@openwrt.org>
-
- This work is redistributed under the terms of the GNU General Public License.
-*/
-
-#ifndef __CFMIPS_ATA_H__
-#define __CFMIPS_ATA_H__
-
-#include <linux/interrupt.h>
-
-#define CFG_DC_DEV1 (void*)0xb8010010
-#define CFG_DC_DEVBASE 0x0
-#define CFG_DC_DEVMASK 0x4
-#define CFG_DC_DEVC 0x8
-#define CFG_DC_DEVTC 0xC
-
-#define CFDEV_BUF_SIZE 0x1000
-#define ATA_CIS_OFFSET 0x200
-#define ATA_REG_OFFSET 0x800
-#define ATA_DBUF_OFFSET 0xC00
-
-#define ATA_REG_FEAT 0x1
-#define ATA_REG_SC 0x2
-#define ATA_REG_SN 0x3
-#define ATA_REG_CL 0x4
-#define ATA_REG_CH 0x5
-#define ATA_REG_DH 0x6
-#define ATA_REG_DH_BASE 0xa0
-#define ATA_REG_DH_LBA 0x40
-#define ATA_REG_DH_DRV 0x10
-#define ATA_REG_CMD 0x7
-#define ATA_REG_ST 0x7
-#define ATA_REG_ST_BUSY 0x80
-#define ATA_REG_ST_RDY 0x40
-#define ATA_REG_ST_DWF 0x20
-#define ATA_REG_ST_DSC 0x10
-#define ATA_REG_ST_DRQ 0x08
-#define ATA_REG_ST_CORR 0x04
-#define ATA_REG_ST_ERR 0x01
-#define ATA_REG_ERR 0xd
-#define ATA_REG_DC 0xe
-#define ATA_REG_DC_IEN 0x02
-#define ATA_REG_DC_SRST 0x04
-
-#define ATA_CMD_READ_SECTORS 0x20
-#define ATA_CMD_WRITE_SECTORS 0x30
-#define ATA_CMD_EXEC_DRIVE_DIAG 0x90
-#define ATA_CMD_READ_MULTIPLE 0xC4
-#define ATA_CMD_WRITE_MULTIPLE 0xC5
-#define ATA_CMD_SET_MULTIPLE 0xC6
-#define ATA_CMD_IDENTIFY_DRIVE 0xEC
-#define ATA_CMD_SET_FEATURES 0xEF
-
-#define ATA_FEATURE_ENABLE_APM 0x05
-#define ATA_FEATURE_DISABLE_APM 0x85
-#define ATA_APM_DISABLED 0x00
-#define ATA_APM_MIN_POWER 0x01
-#define ATA_APM_WITH_STANDBY 0x7f
-#define ATA_APM_WITHOUT_STANDBY 0x80
-#define ATA_APM_MAX_PERFORMANCE 0xfe
-
-#define CF_SECT_SIZE 0x200
-/* That is the ratio CF_SECT_SIZE/512 (the kernel sector size) */
-#define CF_KERNEL_MUL 1
-#define ATA_MAX_SECT_PER_CMD 0x100
-
-#define CF_TRANS_FAILED 0
-#define CF_TRANS_OK 1
-#define CF_TRANS_IN_PROGRESS 2
-
-
-enum trans_state {
- TS_IDLE = 0,
- TS_AFTER_RESET,
- TS_READY,
- TS_CMD,
- TS_TRANS
-};
-
-//
-// #if DEBUG
-// static unsigned long busy_time;
-// #endif
-
-/** Struct to hold the cfdev
-Actually, all the data here only has one instance. However, for
-reasons of programming conformity, it is passed around as a pointer
-*/
-struct cf_mips_dev {
- void *base; /* base address for I/O */
- void *baddr; /* remapped address */
-
- int pin; /* gpio pin */
- int irq; /* gpio irq */
-
- unsigned head;
- unsigned cyl;
- unsigned spt;
- unsigned sectors;
-
- unsigned short block_size;
- unsigned dtype ; // ATA or CF
- struct request_queue *queue;
- struct gendisk *gd;
-
- /* Transaction state */
- enum trans_state tstate;
- char *tbuf;
- unsigned long tbuf_size;
- sector_t tsect_start;
- unsigned tsector_count;
- unsigned tsectors_left;
- int tread;
- unsigned tcmd;
- int async_mode;
- unsigned long irq_enable_time;
-
- struct request *active_req; /* A request is being carried out. Is that different from tstate? */
- int users;
- struct timer_list to_timer;
- struct tasklet_struct tasklet;
-
- /** This lock ensures that the requests to this device are all done
- atomically. Transfers can run in parallel, requests are all queued
- one-by-one */
- spinlock_t lock;
-};
-
-int cf_do_transfer(struct cf_mips_dev* dev,sector_t sector, unsigned long nsect,
- char* buffer, int is_write);
-int cf_init(struct cf_mips_dev* dev);
-void cf_cleanup(struct cf_mips_dev* dev);
-
-void cf_async_trans_done(struct cf_mips_dev* dev, int result);
-// void *cf_get_next_buf(unsigned long *buf_size);
-
-#endif
+++ /dev/null
-/* CF-mips driver
- This is a block driver for the direct (mmaped) interface to the CF-slot,
- found in Routerboard.com's RB532 board
- See SDK provided from routerboard.com.
-
- Module adapted By P.Christeas <p_christeas@yahoo.com>, 2005-6.
- Cleaned up and adapted to platform_device by Felix Fietkau <nbd@openwrt.org>
-
- This work is redistributed under the terms of the GNU General Public License.
-*/
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/time.h>
-#include <linux/wait.h>
-#include <linux/fs.h>
-#include <linux/genhd.h>
-#include <linux/blkdev.h>
-#include <linux/blkpg.h>
-#include <linux/hdreg.h>
-#include <linux/platform_device.h>
-
-#include <asm/uaccess.h>
-#include <asm/io.h>
-#include <asm/gpio.h>
-
-#include <asm/rc32434/rb.h>
-
-#ifdef DEBUG
-#define DEBUGP printk
-#define DLEVEL 1
-#else
-#define DEBUGP(format, args...)
-#define DLEVEL 0
-#endif
-
-#define CF_MIPS_MAJOR 13
-#define MAJOR_NR CF_MIPS_MAJOR
-#define CF_MAX_PART 16 /* max 15 partitions */
-
-#include "ata.h"
-
-//extern struct block_device_operations cf_bdops;
-
-// static struct hd_struct cf_parts[CF_MAX_PART];
-// static int cf_part_sizes[CF_MAX_PART];
-// static int cf_hsect_sizes[CF_MAX_PART];
-// static int cf_max_sectors[CF_MAX_PART];
-// static int cf_blksize_sizes[CF_MAX_PART];
-
-// static spinlock_t lock = SPIN_LOCK_UNLOCKED;
-
-// volatile int cf_busy = 0;
-
-static struct request *active_req = NULL;
-
-static int cf_open (struct inode *, struct file *);
-static int cf_release (struct inode *, struct file *);
-static int cf_ioctl (struct inode *, struct file *, unsigned, unsigned long);
-
-static void cf_request(request_queue_t * q);
-static int cf_transfer(const struct request *req);
-
-/*long (*unlocked_ioctl) (struct file *, unsigned, unsigned long);
-long (*compat_ioctl) (struct file *, unsigned, unsigned long);*/
-// int (*direct_access) (struct block_device *, sector_t, unsigned long *);
-// int (*media_changed) (struct gendisk *);
-// int (*revalidate_disk) (struct gendisk *);
-
-static struct block_device_operations cf_bdops = {
- .owner = THIS_MODULE,
- .open = cf_open,
- .release = cf_release,
- .ioctl = cf_ioctl,
- .media_changed = NULL,
- .unlocked_ioctl = NULL,
- .revalidate_disk = NULL,
- .compat_ioctl = NULL,
- .direct_access = NULL
-};
-
-
-int cf_mips_probe(struct platform_device *pdev)
-{
- struct gendisk* cf_gendisk=NULL;
- struct cf_device *cdev = (struct cf_device *) pdev->dev.platform_data;
- struct cf_mips_dev *dev;
- struct resource *r;
- int reg_result;
-
- reg_result = register_blkdev(MAJOR_NR, "cf-mips");
- if (reg_result < 0) {
- printk(KERN_WARNING "cf-mips: can't get major %d\n", MAJOR_NR);
- return reg_result;
- }
-
- dev = (struct cf_mips_dev *)kmalloc(sizeof(struct cf_mips_dev),GFP_KERNEL);
- if (!dev)
- goto out_err;
- memset(dev, 0, sizeof(struct cf_mips_dev));
- cdev->dev = dev;
-
- dev->pin = cdev->gpio_pin;
- dev->irq = platform_get_irq_byname(pdev, "cf_irq");
- r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cf_membase");
- dev->base = (void *) r->start;
-
- if (cf_init(dev)) goto out_err;
- printk("init done");
-
- spin_lock_init(&dev->lock);
- dev->queue = blk_init_queue(cf_request,&dev->lock);
- if (!dev->queue){
- printk(KERN_ERR "cf-mips: no mem for queue\n");
- goto out_err;
- }
- blk_queue_max_sectors(dev->queue,ATA_MAX_SECT_PER_CMD);
-
- /* For memory devices, it is always better to avoid crossing segments
- inside the same request. */
-/* if (dev->dtype==0x848A){
- printk(KERN_INFO "Setting boundary for cf to 0x%x",(dev->block_size*512)-1);
- blk_queue_segment_boundary(dev->queue, (dev->block_size*512)-1);
- }*/
-
- dev->gd = alloc_disk(CF_MAX_PART);
- cf_gendisk = dev->gd;
- cdev->gd = dev->gd;
- if (!cf_gendisk) goto out_err; /* Last of these goto's */
-
- cf_gendisk->major = MAJOR_NR;
- cf_gendisk->first_minor = 0;
- cf_gendisk->queue=dev->queue;
- BUG_ON(cf_gendisk->minors != CF_MAX_PART);
- strcpy(cf_gendisk->disk_name,"cfa");
- cf_gendisk->fops = &cf_bdops;
- cf_gendisk->flags = 0 ; /* is not yet GENHD_FL_REMOVABLE */
- cf_gendisk->private_data=dev;
-
- set_capacity(cf_gendisk,dev->sectors * CF_KERNEL_MUL);
-
- /* Let the disk go live */
- add_disk(cf_gendisk);
-#if 0
- result = cf_init();
-
- /* default cfg for all partitions */
- memset(cf_parts, 0, sizeof (cf_parts[0]) * CF_MAX_PART);
- memset(cf_part_sizes, 0, sizeof (cf_part_sizes[0]) * CF_MAX_PART);
- for (i = 0; i < CF_MAX_PART; ++i) {
- cf_hsect_sizes[i] = CF_SECT_SIZE;
- cf_max_sectors[i] = ATA_MAX_SECT_PER_CMD;
- cf_blksize_sizes[i] = BLOCK_SIZE;
- }
-
- /* setup info for whole disk (partition 0) */
- cf_part_sizes[0] = cf_sectors / 2;
- cf_parts[0].nr_sects = cf_sectors;
-
- blk_size[MAJOR_NR] = cf_part_sizes;
- blksize_size[MAJOR_NR] = cf_blksize_sizes;
- max_sectors[MAJOR_NR] = cf_max_sectors;
- hardsect_size[MAJOR_NR] = cf_hsect_sizes;
- read_ahead[MAJOR_NR] = 8; /* (4kB) */
-
- blk_init_queue(BLK_DEFAULT_QUEUE(MAJOR_NR), DEVICE_REQUEST);
-
- add_gendisk(&cf_gendisk);
-#endif
-// printk(KERN_INFO "cf-mips partition check: \n");
-// register_disk(cf_gendisk, MKDEV(MAJOR_NR, 0), CF_MAX_PART,
-// &cf_bdops, dev->sectors);
- return 0;
-
-out_err:
- if (dev->queue){
- blk_cleanup_queue(dev->queue);
- }
- if (reg_result) {
- unregister_blkdev(MAJOR_NR, "cf-mips");
- return reg_result;
- }
- if (dev){
- cf_cleanup(dev);
- kfree(dev);
- }
- return 1;
-}
-
-static int
-cf_mips_remove(struct platform_device *pdev)
-{
- struct cf_device *cdev = (struct cf_device *) pdev->dev.platform_data;
- struct cf_mips_dev *dev = (struct cf_mips_dev *) cdev->dev;
-
- unregister_blkdev(MAJOR_NR, "cf-mips");
- blk_cleanup_queue(dev->queue);
-
- del_gendisk(dev->gd);
- cf_cleanup(dev);
- return 0;
-}
-
-
-static struct platform_driver cf_driver = {
- .driver.name = "rb500-cf",
- .probe = cf_mips_probe,
- .remove = cf_mips_remove,
-};
-
-static int __init cf_mips_init(void)
-{
- printk(KERN_INFO "cf-mips module loaded\n");
- return platform_driver_register(&cf_driver);
-}
-
-static void cf_mips_cleanup(void)
-{
- platform_driver_unregister(&cf_driver);
- printk(KERN_INFO "cf-mips module removed\n");
-}
-
-module_init(cf_mips_init);
-module_exit(cf_mips_cleanup);
-
-MODULE_LICENSE("GPL");
-MODULE_ALIAS_BLOCKDEV_MAJOR(CF_MIPS_MAJOR);
-
-
-static int cf_open(struct inode *inode, struct file *filp)
-{
- struct cf_mips_dev *dev=inode->i_bdev->bd_disk->private_data;
- int minor = MINOR(inode->i_rdev);
-
- if (minor >= CF_MAX_PART)
- return -ENODEV;
- //DEBUGP(KERN_INFO "cf-mips module opened, minor %d\n", minor);
- spin_lock(&dev->lock);
- dev->users++;
- spin_unlock(&dev->lock);
- filp->private_data=dev;
-
- /* dirty workaround to set CFRDY GPIO as an input when some other
- program sets it as an output */
- gpio_set_value(dev->pin, 0);
- return 0; /* success */
-}
-
-static int cf_release(struct inode *inode, struct file *filp)
-{
- int minor = MINOR(inode->i_rdev);
- struct cf_mips_dev *dev=inode->i_bdev->bd_disk->private_data;
- spin_lock(&dev->lock);
- dev->users--;
- spin_unlock(&dev->lock);
- return 0;
-}
-
-static int cf_ioctl(struct inode *inode, struct file *filp,
- unsigned int cmd, unsigned long arg)
-{
- unsigned minor = MINOR(inode->i_rdev);
- struct cf_mips_dev *dev=inode->i_bdev->bd_disk->private_data;
-
- DEBUGP(KERN_INFO "cf_ioctl cmd %u\n", cmd);
- switch (cmd) {
- case BLKRRPART: /* re-read partition table */
- if (!capable(CAP_SYS_ADMIN))
- return -EACCES;
- printk(KERN_INFO "cf-mips partition check: \n");
- register_disk(dev->gd);
- return 0;
-
- case HDIO_GETGEO:
- {
- struct hd_geometry geo;
- geo.cylinders = dev->cyl;
- geo.heads = dev->head;
- geo.sectors = dev->spt;
- geo.start = (*dev->gd->part)[minor].start_sect;
- if (copy_to_user((void *) arg, &geo, sizeof (geo)))
- return -EFAULT;
- }
- return 0;
- }
-
- return -EINVAL; /* unknown command */
-}
-
-static void cf_request(request_queue_t * q)
-{
- struct cf_mips_dev* dev;
-
- struct request * req;
- int status;
-
- /* We could have q->queuedata = dev , but haven't yet. */
- if (active_req)
- return;
-
- while ((req=elv_next_request(q))!=NULL){
- dev=req->rq_disk->private_data;
- status=cf_transfer(req);
- if (status==CF_TRANS_IN_PROGRESS){
- active_req=req;
- return;
- }
- end_request(req,status);
- }
-}
-
-static int cf_transfer(const struct request *req)
-{
- struct cf_mips_dev* dev=req->rq_disk->private_data;
-
- if (!blk_fs_request(req)){
- if (printk_ratelimit())
- printk(KERN_WARNING "cf-mips: skipping non-fs request 0x%x\n",req->cmd[0]);
- return CF_TRANS_FAILED;
- }
-
- return cf_do_transfer(dev,req->sector,req->current_nr_sectors,req->buffer,rq_data_dir(req));
-}
-
-void cf_async_trans_done(struct cf_mips_dev * dev,int result)
-{
- struct request *req;
-
- spin_lock(&dev->lock);
- req=active_req;
- active_req=NULL;
- end_request(req,result);
- spin_unlock(&dev->lock);
-
- spin_lock(&dev->lock);
- cf_request(dev->queue);
- spin_unlock(&dev->lock);
-}
-
+++ /dev/null
-/*
- * linux/drivers/leds/leds-rb500.c
- *
- * Copyright (C) 2006
- * Twente Institute for Wireless and Mobile Communications BV
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details (see file GPLv2).
- *
- * Author: Tjalling Hattink <tjalling.hattink@ti-wmc.nl>
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/leds.h>
-#include <asm/rc32434/rb.h>
-
-static void rb500led_amber_set(struct led_classdev *led_cdev, enum led_brightness value)
-{
- if (value)
- changeLatchU5(LO_ULED, 0);
- else
- changeLatchU5(0, LO_ULED);
-}
-
-static struct led_classdev rb500_amber_led = {
- .name = "rb500led:amber",
- .default_trigger = "ide-disk",
- .brightness_set = rb500led_amber_set,
-};
-
-static int rb500led_probe(struct platform_device *pdev)
-{
- int ret;
-
- changeLatchU5(0, LO_ULED);
-
- ret = led_classdev_register(&pdev->dev, &rb500_amber_led);
-
- return ret;
-}
-
-static int rb500led_remove(struct platform_device *pdev)
-{
- led_classdev_unregister(&rb500_amber_led);
-
- return 0;
-}
-
-static struct platform_driver rb500led_driver = {
- .probe = rb500led_probe,
- .remove = rb500led_remove,
- .driver = {
- .name = "rb500-led",
- },
-};
-
-static int __init rb500led_init(void)
-{
- return platform_driver_register(&rb500led_driver);
-}
-
-static void __exit rb500led_exit(void)
-{
- platform_driver_unregister(&rb500led_driver);
-}
-
-module_init(rb500led_init);
-module_exit(rb500led_exit);
-
-MODULE_AUTHOR("tjalling.hattink@ti-wmc.nl");
-MODULE_DESCRIPTION("Mikrotik RB500 LED driver");
-MODULE_LICENSE("GPL");
+++ /dev/null
-/**************************************************************************
- *
- * BRIEF MODULE DESCRIPTION
- * Driver for the IDT RC32434 on-chip ethernet controller.
- *
- * Copyright 2004 IDT Inc. (rischelp@idt.com)
- * Copyright 2006 Felix Fietkau <nbd@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- *
- **************************************************************************
- * May 2004 rkt, neb
- *
- * Based on the driver developed by B. Maruthanayakam, H. Kou and others.
- *
- * Aug 2004 Sadik
- *
- * Added NAPI
- *
- **************************************************************************
- */
-
-#include <linux/autoconf.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/moduleparam.h>
-#include <linux/sched.h>
-#include <linux/ctype.h>
-#include <linux/types.h>
-#include <linux/fcntl.h>
-#include <linux/interrupt.h>
-#include <linux/ptrace.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/proc_fs.h>
-#include <linux/in.h>
-#include <linux/slab.h>
-#include <linux/string.h>
-#include <linux/delay.h>
-#include <linux/netdevice.h>
-#include <linux/etherdevice.h>
-#include <linux/skbuff.h>
-#include <linux/errno.h>
-#include <linux/platform_device.h>
-#include <asm/bootinfo.h>
-#include <asm/system.h>
-#include <asm/bitops.h>
-#include <asm/pgtable.h>
-#include <asm/segment.h>
-#include <asm/io.h>
-#include <asm/dma.h>
-
-#include <asm/rc32434/rb.h>
-#include "rc32434_eth.h"
-
-#define DRIVER_VERSION "(mar2904)"
-
-#define DRIVER_NAME "rc32434 Ethernet driver. " DRIVER_VERSION
-
-#define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \
- ((dev)->dev_addr[1]))
-#define STATION_ADDRESS_LOW(dev) (((dev)->dev_addr[2] << 24) | \
- ((dev)->dev_addr[3] << 16) | \
- ((dev)->dev_addr[4] << 8) | \
- ((dev)->dev_addr[5]))
-
-#define MII_CLOCK 1250000 /* no more than 2.5MHz */
-#define CONFIG_IDT_USE_NAPI 1
-
-
-static inline void rc32434_abort_tx(struct net_device *dev)
-{
- struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
- rc32434_abort_dma(dev, lp->tx_dma_regs);
-
-}
-
-static inline void rc32434_abort_rx(struct net_device *dev)
-{
- struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
- rc32434_abort_dma(dev, lp->rx_dma_regs);
-
-}
-
-static inline void rc32434_start_tx(struct rc32434_local *lp, volatile DMAD_t td)
-{
- rc32434_start_dma(lp->tx_dma_regs, CPHYSADDR(td));
-}
-
-static inline void rc32434_start_rx(struct rc32434_local *lp, volatile DMAD_t rd)
-{
- rc32434_start_dma(lp->rx_dma_regs, CPHYSADDR(rd));
-}
-
-static inline void rc32434_chain_tx(struct rc32434_local *lp, volatile DMAD_t td)
-{
- rc32434_chain_dma(lp->tx_dma_regs, CPHYSADDR(td));
-}
-
-static inline void rc32434_chain_rx(struct rc32434_local *lp, volatile DMAD_t rd)
-{
- rc32434_chain_dma(lp->rx_dma_regs, CPHYSADDR(rd));
-}
-
-#ifdef RC32434_PROC_DEBUG
-static int rc32434_read_proc(char *buf, char **start, off_t fpos,
- int length, int *eof, void *data)
-{
- struct net_device *dev = (struct net_device *)data;
- struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
- int len = 0;
-
- /* print out header */
- len += sprintf(buf + len, "\n\tKorina Ethernet Debug\n\n");
- len += sprintf (buf + len,
- "DMA halt count = %10d, DMA run count = %10d\n",
- lp->dma_halt_cnt, lp->dma_run_cnt);
-
- if (fpos >= len) {
- *start = buf;
- *eof = 1;
- return 0;
- }
- *start = buf + fpos;
-
- if ((len -= fpos) > length)
- return length;
- *eof = 1;
-
- return len;
-
-}
-#endif
-
-
-/*
- * Restart the RC32434 ethernet controller.
- */
-static int rc32434_restart(struct net_device *dev)
-{
- struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
-
- /*
- * Disable interrupts
- */
- disable_irq(lp->rx_irq);
- disable_irq(lp->tx_irq);
-#ifdef RC32434_REVISION
- disable_irq(lp->ovr_irq);
-#endif
- disable_irq(lp->und_irq);
-
- /* Mask F E bit in Tx DMA */
- __raw_writel(__raw_readl(&lp->tx_dma_regs->dmasm) | DMASM_f_m | DMASM_e_m, &lp->tx_dma_regs->dmasm);
- /* Mask D H E bit in Rx DMA */
- __raw_writel(__raw_readl(&lp->rx_dma_regs->dmasm) | DMASM_d_m | DMASM_h_m | DMASM_e_m, &lp->rx_dma_regs->dmasm);
-
- rc32434_init(dev);
- rc32434_multicast_list(dev);
-
- enable_irq(lp->und_irq);
-#ifdef RC32434_REVISION
- enable_irq(lp->ovr_irq);
-#endif
- enable_irq(lp->tx_irq);
- enable_irq(lp->rx_irq);
-
- return 0;
-}
-
-static int rc32434_probe(struct platform_device *pdev)
-{
- struct korina_device *bif = (struct korina_device *) pdev->dev.platform_data;
- struct rc32434_local *lp = NULL;
- struct net_device *dev = NULL;
- struct resource *r;
- int i, retval,err;
-
- dev = alloc_etherdev(sizeof(struct rc32434_local));
- if(!dev) {
- ERR("Korina_eth: alloc_etherdev failed\n");
- return -1;
- }
-
- platform_set_drvdata(pdev, dev);
- SET_NETDEV_DEV(dev, &pdev->dev);
- bif->dev = dev;
-
- memcpy(dev->dev_addr, bif->mac, 6);
-
- /* Initialize the device structure. */
- if (dev->priv == NULL) {
- lp = (struct rc32434_local *)kmalloc(sizeof(*lp), GFP_KERNEL);
- memset(lp, 0, sizeof(struct rc32434_local));
- }
- else {
- lp = (struct rc32434_local *)dev->priv;
- }
-
- lp->rx_irq = platform_get_irq_byname(pdev, "korina_rx");
- lp->tx_irq = platform_get_irq_byname(pdev, "korina_tx");
- lp->ovr_irq = platform_get_irq_byname(pdev, "korina_ovr");
- lp->und_irq = platform_get_irq_byname(pdev, "korina_und");
-
- r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_regs");
- dev->base_addr = r->start;
- lp->eth_regs = ioremap_nocache(r->start, r->end - r->start);
- if (!lp->eth_regs) {
- ERR("Can't remap eth registers\n");
- retval = -ENXIO;
- goto probe_err_out;
- }
-
- r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_dma_rx");
- lp->rx_dma_regs = ioremap_nocache(r->start, r->end - r->start);
- if (!lp->rx_dma_regs) {
- ERR("Can't remap Rx DMA registers\n");
- retval = -ENXIO;
- goto probe_err_out;
- }
-
- r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_dma_tx");
- lp->tx_dma_regs = ioremap_nocache(r->start, r->end - r->start);
- if (!lp->tx_dma_regs) {
- ERR("Can't remap Tx DMA registers\n");
- retval = -ENXIO;
- goto probe_err_out;
- }
-
-#ifdef RC32434_PROC_DEBUG
- lp->ps = create_proc_read_entry (bif->name, 0, proc_net,
- rc32434_read_proc, dev);
-#endif
-
- lp->td_ring = (DMAD_t)kmalloc(TD_RING_SIZE + RD_RING_SIZE, GFP_KERNEL);
- if (!lp->td_ring) {
- ERR("Can't allocate descriptors\n");
- retval = -ENOMEM;
- goto probe_err_out;
- }
-
- dma_cache_inv((unsigned long)(lp->td_ring), TD_RING_SIZE + RD_RING_SIZE);
-
- /* now convert TD_RING pointer to KSEG1 */
- lp->td_ring = (DMAD_t )KSEG1ADDR(lp->td_ring);
- lp->rd_ring = &lp->td_ring[RC32434_NUM_TDS];
-
-
- spin_lock_init(&lp->lock);
-
- /* just use the rx dma irq */
- dev->irq = lp->rx_irq;
-
- dev->priv = lp;
- lp->dev = dev;
-
- dev->open = rc32434_open;
- dev->stop = rc32434_close;
- dev->hard_start_xmit = rc32434_send_packet;
- dev->get_stats = rc32434_get_stats;
- dev->set_multicast_list = &rc32434_multicast_list;
- dev->tx_timeout = rc32434_tx_timeout;
- dev->watchdog_timeo = RC32434_TX_TIMEOUT;
-
- netif_napi_add(dev, &lp->napi, rc32434_poll, 64);
- lp->tx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
- tasklet_init(lp->tx_tasklet, rc32434_tx_tasklet, (unsigned long)dev);
-
- if ((err = register_netdev(dev))) {
- printk(KERN_ERR "rc32434 ethernet. Cannot register net device %d\n", err);
- free_netdev(dev);
- retval = -EINVAL;
- goto probe_err_out;
- }
-
- INFO("Rx IRQ %d, Tx IRQ %d, ", lp->rx_irq, lp->tx_irq);
- for (i = 0; i < 6; i++) {
- printk("%2.2x", dev->dev_addr[i]);
- if (i<5)
- printk(":");
- }
- printk("\n");
-
- return 0;
-
- probe_err_out:
- rc32434_cleanup_module();
- ERR(" failed. Returns %d\n", retval);
- return retval;
-
-}
-
-static int rc32434_remove(struct platform_device *pdev)
-{
- struct korina_device *bif = (struct korina_device *) pdev->dev.platform_data;
-
- if (bif->dev != NULL) {
- struct rc32434_local *lp = (struct rc32434_local *)bif->dev->priv;
- if (lp != NULL) {
- if (lp->eth_regs)
- iounmap((void*)lp->eth_regs);
- if (lp->rx_dma_regs)
- iounmap((void*)lp->rx_dma_regs);
- if (lp->tx_dma_regs)
- iounmap((void*)lp->tx_dma_regs);
- if (lp->td_ring)
- kfree((void*)KSEG0ADDR(lp->td_ring));
-
-#ifdef RC32434_PROC_DEBUG
- if (lp->ps) {
- remove_proc_entry(bif->name, proc_net);
- }
-#endif
- kfree(lp);
- }
-
- platform_set_drvdata(pdev, NULL);
- unregister_netdev(bif->dev);
- free_netdev(bif->dev);
- kfree(bif->dev);
- }
- return 0;
-}
-
-
-static int rc32434_open(struct net_device *dev)
-{
- struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
-
- /* Initialize */
- if (rc32434_init(dev)) {
- ERR("Error: cannot open the Ethernet device\n");
- return -EAGAIN;
- }
-
- /* Install the interrupt handler that handles the Done Finished Ovr and Und Events */
- if (request_irq(lp->rx_irq, &rc32434_rx_dma_interrupt,
- IRQF_SHARED | IRQF_DISABLED,
- "Korina ethernet Rx", dev)) {
- ERR(": unable to get Rx DMA IRQ %d\n",
- lp->rx_irq);
- return -EAGAIN;
- }
- if (request_irq(lp->tx_irq, &rc32434_tx_dma_interrupt,
- IRQF_SHARED | IRQF_DISABLED,
- "Korina ethernet Tx", dev)) {
- ERR(": unable to get Tx DMA IRQ %d\n",
- lp->tx_irq);
- free_irq(lp->rx_irq, dev);
- return -EAGAIN;
- }
-
-#ifdef RC32434_REVISION
- /* Install handler for overrun error. */
- if (request_irq(lp->ovr_irq, &rc32434_ovr_interrupt,
- IRQF_SHARED | IRQF_DISABLED,
- "Ethernet Overflow", dev)) {
- ERR(": unable to get OVR IRQ %d\n",
- lp->ovr_irq);
- free_irq(lp->rx_irq, dev);
- free_irq(lp->tx_irq, dev);
- return -EAGAIN;
- }
-#endif
-
- /* Install handler for underflow error. */
- if (request_irq(lp->und_irq, &rc32434_und_interrupt,
- IRQF_SHARED | IRQF_DISABLED,
- "Ethernet Underflow", dev)) {
- ERR(": unable to get UND IRQ %d\n",
- lp->und_irq);
- free_irq(lp->rx_irq, dev);
- free_irq(lp->tx_irq, dev);
-#ifdef RC32434_REVISION
- free_irq(lp->ovr_irq, dev);
-#endif
- return -EAGAIN;
- }
-
-
- return 0;
-}
-
-
-
-
-static int rc32434_close(struct net_device *dev)
-{
- struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
- u32 tmp;
-
- /* Disable interrupts */
- disable_irq(lp->rx_irq);
- disable_irq(lp->tx_irq);
-#ifdef RC32434_REVISION
- disable_irq(lp->ovr_irq);
-#endif
- disable_irq(lp->und_irq);
-
- tmp = __raw_readl(&lp->tx_dma_regs->dmasm);
- tmp = tmp | DMASM_f_m | DMASM_e_m;
- __raw_writel(tmp, &lp->tx_dma_regs->dmasm);
-
- tmp = __raw_readl(&lp->rx_dma_regs->dmasm);
- tmp = tmp | DMASM_d_m | DMASM_h_m | DMASM_e_m;
- __raw_writel(tmp, &lp->rx_dma_regs->dmasm);
-
- free_irq(lp->rx_irq, dev);
- free_irq(lp->tx_irq, dev);
-#ifdef RC32434_REVISION
- free_irq(lp->ovr_irq, dev);
-#endif
- free_irq(lp->und_irq, dev);
- return 0;
-}
-
-
-/* transmit packet */
-static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev)
-{
- struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
- unsigned long flags;
- u32 length;
- DMAD_t td;
-
-
- spin_lock_irqsave(&lp->lock, flags);
-
- td = &lp->td_ring[lp->tx_chain_tail];
-
- /* stop queue when full, drop pkts if queue already full */
- if(lp->tx_count >= (RC32434_NUM_TDS - 2)) {
- lp->tx_full = 1;
-
- if(lp->tx_count == (RC32434_NUM_TDS - 2)) {
- netif_stop_queue(dev);
- }
- else {
- lp->stats.tx_dropped++;
- dev_kfree_skb_any(skb);
- spin_unlock_irqrestore(&lp->lock, flags);
- return 1;
- }
- }
-
- lp->tx_count ++;
-
- lp->tx_skb[lp->tx_chain_tail] = skb;
-
- length = skb->len;
- dma_cache_wback((u32)skb->data, skb->len);
-
- /* Setup the transmit descriptor. */
- dma_cache_inv((u32) td, sizeof(*td));
- td->ca = CPHYSADDR(skb->data);
-
- if(__raw_readl(&(lp->tx_dma_regs->dmandptr)) == 0) {
- if( lp->tx_chain_status == empty ) {
- td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
- lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
- __raw_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
- lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */
- }
- else {
- td->control = DMA_COUNT(length) |DMAD_cof_m|DMAD_iof_m; /* Update tail */
- lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */
- lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */
- lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
- __raw_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
- lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */
- lp->tx_chain_status = empty;
- }
- }
- else {
- if( lp->tx_chain_status == empty ) {
- td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
- lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
- lp->tx_chain_status = filled;
- }
- else {
- td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
- lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */
- lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */
- lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
- }
- }
- dma_cache_wback((u32) td, sizeof(*td));
-
- dev->trans_start = jiffies;
-
- spin_unlock_irqrestore(&lp->lock, flags);
-
- return 0;
-}
-
-
-/* Ethernet MII-PHY Handler */
-static void rc32434_mii_handler(unsigned long data)
-{
- struct net_device *dev = (struct net_device *)data;
- struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
- unsigned long flags;
- unsigned long duplex_status;
- int port_addr = (lp->rx_irq == 0x2c? 1:0) << 8;
-
- spin_lock_irqsave(&lp->lock, flags);
-
- /* Two ports are using the same MII, the difference is the PHY address */
- __raw_writel(0, &rc32434_eth0_regs->miimcfg);
- __raw_writel(0, &rc32434_eth0_regs->miimcmd);
- __raw_writel(port_addr |0x05, &rc32434_eth0_regs->miimaddr);
- __raw_writel(MIIMCMD_scn_m, &rc32434_eth0_regs->miimcmd);
- while(__raw_readl(&rc32434_eth0_regs->miimind) & MIIMIND_nv_m);
-
- ERR("irq:%x port_addr:%x RDD:%x\n",
- lp->rx_irq, port_addr, __raw_readl(&rc32434_eth0_regs->miimrdd));
- duplex_status = (__raw_readl(&rc32434_eth0_regs->miimrdd) & 0x140)? ETHMAC2_fd_m: 0;
- if(duplex_status != lp->duplex_mode) {
- ERR("The MII-PHY is Auto-negotiated to %s-Duplex mode for Eth-%x\n", duplex_status? "Full":"Half", lp->rx_irq == 0x2c? 1:0);
- lp->duplex_mode = duplex_status;
- rc32434_restart(dev);
- }
-
- lp->mii_phy_timer.expires = jiffies + 10 * HZ;
- add_timer(&lp->mii_phy_timer);
-
- spin_unlock_irqrestore(&lp->lock, flags);
-
-}
-
-#ifdef RC32434_REVISION
-/* Ethernet Rx Overflow interrupt */
-static irqreturn_t
-rc32434_ovr_interrupt(int irq, void *dev_id)
-{
- struct net_device *dev = (struct net_device *)dev_id;
- struct rc32434_local *lp;
- unsigned int ovr;
- irqreturn_t retval = IRQ_NONE;
-
- ASSERT(dev != NULL);
-
- lp = (struct rc32434_local *)dev->priv;
- spin_lock(&lp->lock);
- ovr = __raw_readl(&lp->eth_regs->ethintfc);
-
- if(ovr & ETHINTFC_ovr_m) {
- netif_stop_queue(dev);
-
- /* clear OVR bit */
- __raw_writel((ovr & ~ETHINTFC_ovr_m), &lp->eth_regs->ethintfc);
-
- /* Restart interface */
- rc32434_restart(dev);
- retval = IRQ_HANDLED;
- }
- spin_unlock(&lp->lock);
-
- return retval;
-}
-
-#endif
-
-
-/* Ethernet Tx Underflow interrupt */
-static irqreturn_t
-rc32434_und_interrupt(int irq, void *dev_id)
-{
- struct net_device *dev = (struct net_device *)dev_id;
- struct rc32434_local *lp;
- unsigned int und;
- irqreturn_t retval = IRQ_NONE;
-
- ASSERT(dev != NULL);
-
- lp = (struct rc32434_local *)dev->priv;
-
- spin_lock(&lp->lock);
-
- und = __raw_readl(&lp->eth_regs->ethintfc);
-
- if(und & ETHINTFC_und_m) {
- netif_stop_queue(dev);
-
- __raw_writel((und & ~ETHINTFC_und_m), &lp->eth_regs->ethintfc);
-
- /* Restart interface */
- rc32434_restart(dev);
- retval = IRQ_HANDLED;
- }
-
- spin_unlock(&lp->lock);
-
- return retval;
-}
-
-
-/* Ethernet Rx DMA interrupt */
-static irqreturn_t
-rc32434_rx_dma_interrupt(int irq, void *dev_id)
-{
- struct net_device *dev = (struct net_device *)dev_id;
- struct rc32434_local* lp;
- volatile u32 dmas,dmasm;
- irqreturn_t retval;
-
- ASSERT(dev != NULL);
-
- lp = (struct rc32434_local *)dev->priv;
-
- dmas = __raw_readl(&lp->rx_dma_regs->dmas);
- if(dmas & (DMAS_d_m|DMAS_h_m|DMAS_e_m)) {
- /* Mask D H E bit in Rx DMA */
- dmasm = __raw_readl(&lp->rx_dma_regs->dmasm);
- __raw_writel(dmasm | (DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
- netif_rx_schedule(dev, &lp->napi);
-
- if (dmas & DMAS_e_m)
- ERR(": DMA error\n");
-
- retval = IRQ_HANDLED;
- }
- else
- retval = IRQ_NONE;
-
- return retval;
-}
-
-
-static int rc32434_rx(struct net_device *dev, int limit)
-{
- struct rc32434_local *lp = netdev_priv(dev);
- volatile DMAD_t rd = &lp->rd_ring[lp->rx_next_done];
- struct sk_buff *skb, *skb_new;
- u8 *pkt_buf;
- u32 devcs, pkt_len, dmas, rx_free_desc;
- u32 pktuncrc_len;
- int count;
-
- dma_cache_inv((u32)rd, sizeof(*rd));
- for (count = 0; count < limit; count++) {
- /* init the var. used for the later operations within the while loop */
- skb_new = NULL;
- devcs = rd->devcs;
- pkt_len = RCVPKT_LENGTH(devcs);
- skb = lp->rx_skb[lp->rx_next_done];
-
- if ((devcs & ( ETHRX_ld_m)) != ETHRX_ld_m) {
- /* check that this is a whole packet */
- /* WARNING: DMA_FD bit incorrectly set in Rc32434 (errata ref #077) */
- lp->stats.rx_errors++;
- lp->stats.rx_dropped++;
- }
- else if ( (devcs & ETHRX_rok_m) ) {
-
- /* must be the (first and) last descriptor then */
- pkt_buf = (u8*)lp->rx_skb[lp->rx_next_done]->data;
-
- pktuncrc_len = pkt_len - 4;
- /* invalidate the cache */
- dma_cache_inv((unsigned long)pkt_buf, pktuncrc_len);
-
- /* Malloc up new buffer. */
- skb_new = netdev_alloc_skb(dev, RC32434_RBSIZE + 2);
-
- if (skb_new != NULL){
- /* Make room */
- skb_put(skb, pktuncrc_len);
-
- skb->protocol = eth_type_trans(skb, dev);
-
- /* pass the packet to upper layers */
- netif_receive_skb(skb);
-
- dev->last_rx = jiffies;
- lp->stats.rx_packets++;
- lp->stats.rx_bytes += pktuncrc_len;
-
- if (IS_RCV_MP(devcs))
- lp->stats.multicast++;
-
- /* 16 bit align */
- skb_reserve(skb_new, 2);
-
- skb_new->dev = dev;
- lp->rx_skb[lp->rx_next_done] = skb_new;
- }
- else {
- ERR("no memory, dropping rx packet.\n");
- lp->stats.rx_errors++;
- lp->stats.rx_dropped++;
- }
- }
- else {
- /* This should only happen if we enable accepting broken packets */
- lp->stats.rx_errors++;
- lp->stats.rx_dropped++;
-
- /* add statistics counters */
- if (IS_RCV_CRC_ERR(devcs)) {
- DBG(2, "RX CRC error\n");
- lp->stats.rx_crc_errors++;
- }
- else if (IS_RCV_LOR_ERR(devcs)) {
- DBG(2, "RX LOR error\n");
- lp->stats.rx_length_errors++;
- }
- else if (IS_RCV_LE_ERR(devcs)) {
- DBG(2, "RX LE error\n");
- lp->stats.rx_length_errors++;
- }
- else if (IS_RCV_OVR_ERR(devcs)) {
- lp->stats.rx_over_errors++;
- }
- else if (IS_RCV_CV_ERR(devcs)) {
- /* code violation */
- DBG(2, "RX CV error\n");
- lp->stats.rx_frame_errors++;
- }
- else if (IS_RCV_CES_ERR(devcs)) {
- DBG(2, "RX Preamble error\n");
- }
- }
- rd->devcs = 0;
-
- /* restore descriptor's curr_addr */
- if(skb_new) {
- rd->ca = CPHYSADDR(skb_new->data);
- }
- else
- rd->ca = CPHYSADDR(skb->data);
-
- rd->control = DMA_COUNT(RC32434_RBSIZE) |DMAD_cod_m |DMAD_iod_m;
- lp->rd_ring[(lp->rx_next_done-1)& RC32434_RDS_MASK].control &= ~(DMAD_cod_m);
-
- lp->rx_next_done = (lp->rx_next_done + 1) & RC32434_RDS_MASK;
- dma_cache_wback((u32)rd, sizeof(*rd));
- rd = &lp->rd_ring[lp->rx_next_done];
- __raw_writel( ~DMAS_d_m, &lp->rx_dma_regs->dmas);
- }
-
- dmas = __raw_readl(&lp->rx_dma_regs->dmas);
-
- if(dmas & DMAS_h_m) {
- /* Mask off halt and error bits */
- __raw_writel( ~(DMAS_h_m | DMAS_e_m), &lp->rx_dma_regs->dmas);
-#ifdef RC32434_PROC_DEBUG
- lp->dma_halt_cnt++;
-#endif
- rd->devcs = 0;
- skb = lp->rx_skb[lp->rx_next_done];
- rd->ca = CPHYSADDR(skb->data);
- dma_cache_wback((u32)rd, sizeof(*rd));
- rc32434_chain_rx(lp,rd);
- }
-
- return count;
-}
-
-static int rc32434_poll(struct napi_struct *napi, int budget)
-{
- struct rc32434_local *lp =
- container_of(napi, struct rc32434_local, napi);
- struct net_device *dev = lp->dev;
- int work_done;
-
- work_done = rc32434_rx(dev, budget);
- if (work_done < budget) {
- netif_rx_complete(dev, napi);
-
- /* Mask off interrupts */
- writel(readl(&lp->rx_dma_regs->dmasm) &
- (DMASM_d_m | DMASM_h_m |DMASM_e_m),
- &lp->rx_dma_regs->dmasm);
- }
- return work_done;
-}
-
-
-
-/* Ethernet Tx DMA interrupt */
-static irqreturn_t
-rc32434_tx_dma_interrupt(int irq, void *dev_id)
-{
- struct net_device *dev = (struct net_device *)dev_id;
- struct rc32434_local *lp;
- volatile u32 dmas,dmasm;
- irqreturn_t retval;
-
- ASSERT(dev != NULL);
-
- lp = (struct rc32434_local *)dev->priv;
-
- dmas = __raw_readl(&lp->tx_dma_regs->dmas);
-
- if (dmas & (DMAS_f_m | DMAS_e_m)) {
- dmasm = __raw_readl(&lp->tx_dma_regs->dmasm);
- /* Mask F E bit in Tx DMA */
- __raw_writel(dmasm | (DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
-
- tasklet_hi_schedule(lp->tx_tasklet);
-
- if(lp->tx_chain_status == filled && (__raw_readl(&(lp->tx_dma_regs->dmandptr)) == 0)) {
- __raw_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr));
- lp->tx_chain_status = empty;
- lp->tx_chain_head = lp->tx_chain_tail;
- dev->trans_start = jiffies;
- }
-
- if (dmas & DMAS_e_m)
- ERR(": DMA error\n");
-
- retval = IRQ_HANDLED;
- }
- else
- retval = IRQ_NONE;
-
- return retval;
-}
-
-
-static void rc32434_tx_tasklet(unsigned long tx_data_dev)
-{
- struct net_device *dev = (struct net_device *)tx_data_dev;
- struct rc32434_local* lp = (struct rc32434_local *)dev->priv;
- volatile DMAD_t td = &lp->td_ring[lp->tx_next_done];
- u32 devcs;
- unsigned long flags;
- volatile u32 dmas;
-
- spin_lock_irqsave(&lp->lock, flags);
-
- /* process all desc that are done */
- while(IS_DMA_FINISHED(td->control)) {
- if(lp->tx_full == 1) {
- netif_wake_queue(dev);
- lp->tx_full = 0;
- }
-
- devcs = lp->td_ring[lp->tx_next_done].devcs;
- if ((devcs & (ETHTX_fd_m | ETHTX_ld_m)) != (ETHTX_fd_m | ETHTX_ld_m)) {
- lp->stats.tx_errors++;
- lp->stats.tx_dropped++;
-
- /* should never happen */
- DBG(1, __FUNCTION__ ": split tx ignored\n");
- }
- else if (IS_TX_TOK(devcs)) {
- lp->stats.tx_packets++;
- lp->stats.tx_bytes+=lp->tx_skb[lp->tx_next_done]->len;
- }
- else {
- lp->stats.tx_errors++;
- lp->stats.tx_dropped++;
-
- /* underflow */
- if (IS_TX_UND_ERR(devcs))
- lp->stats.tx_fifo_errors++;
-
- /* oversized frame */
- if (IS_TX_OF_ERR(devcs))
- lp->stats.tx_aborted_errors++;
-
- /* excessive deferrals */
- if (IS_TX_ED_ERR(devcs))
- lp->stats.tx_carrier_errors++;
-
- /* collisions: medium busy */
- if (IS_TX_EC_ERR(devcs))
- lp->stats.collisions++;
-
- /* late collision */
- if (IS_TX_LC_ERR(devcs))
- lp->stats.tx_window_errors++;
-
- }
-
- /* We must always free the original skb */
- if (lp->tx_skb[lp->tx_next_done] != NULL) {
- dev_kfree_skb_any(lp->tx_skb[lp->tx_next_done]);
- lp->tx_skb[lp->tx_next_done] = NULL;
- }
-
- lp->td_ring[lp->tx_next_done].control = DMAD_iof_m;
- lp->td_ring[lp->tx_next_done].devcs = ETHTX_fd_m | ETHTX_ld_m;
- lp->td_ring[lp->tx_next_done].link = 0;
- lp->td_ring[lp->tx_next_done].ca = 0;
- lp->tx_count --;
-
- /* go on to next transmission */
- lp->tx_next_done = (lp->tx_next_done + 1) & RC32434_TDS_MASK;
- td = &lp->td_ring[lp->tx_next_done];
-
- }
-
- dmas = __raw_readl(&lp->tx_dma_regs->dmas);
- __raw_writel( ~dmas, &lp->tx_dma_regs->dmas);
-
- /* Enable F E bit in Tx DMA */
- __raw_writel(__raw_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
- spin_unlock_irqrestore(&lp->lock, flags);
-
-}
-
-
-static struct net_device_stats * rc32434_get_stats(struct net_device *dev)
-{
- struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
- return &lp->stats;
-}
-
-
-/*
- * Set or clear the multicast filter for this adaptor.
- */
-static void rc32434_multicast_list(struct net_device *dev)
-{
- /* listen to broadcasts always and to treat */
- /* IFF bits independantly */
- struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
- unsigned long flags;
- u32 recognise = ETHARC_ab_m; /* always accept broadcasts */
-
- if (dev->flags & IFF_PROMISC) /* set promiscuous mode */
- recognise |= ETHARC_pro_m;
-
- if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 15))
- recognise |= ETHARC_am_m; /* all multicast & bcast */
- else if (dev->mc_count > 0) {
- DBG(2, __FUNCTION__ ": mc_count %d\n", dev->mc_count);
- recognise |= ETHARC_am_m; /* for the time being */
- }
-
- spin_lock_irqsave(&lp->lock, flags);
- __raw_writel(recognise, &lp->eth_regs->etharc);
- spin_unlock_irqrestore(&lp->lock, flags);
-}
-
-
-static void rc32434_tx_timeout(struct net_device *dev)
-{
- struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
- unsigned long flags;
-
- spin_lock_irqsave(&lp->lock, flags);
- rc32434_restart(dev);
- spin_unlock_irqrestore(&lp->lock, flags);
-
-}
-
-
-/*
- * Initialize the RC32434 ethernet controller.
- */
-static int rc32434_init(struct net_device *dev)
-{
- struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
- int i, j;
-
- /* Disable DMA */
- rc32434_abort_tx(dev);
- rc32434_abort_rx(dev);
-
- /* reset ethernet logic */
- __raw_writel(0, &lp->eth_regs->ethintfc);
- while((__raw_readl(&lp->eth_regs->ethintfc) & ETHINTFC_rip_m))
- dev->trans_start = jiffies;
-
- /* Enable Ethernet Interface */
- __raw_writel(ETHINTFC_en_m, &lp->eth_regs->ethintfc);
-
- tasklet_disable(lp->tx_tasklet);
-
- /* Initialize the transmit Descriptors */
- for (i = 0; i < RC32434_NUM_TDS; i++) {
- lp->td_ring[i].control = DMAD_iof_m;
- lp->td_ring[i].devcs = ETHTX_fd_m | ETHTX_ld_m;
- lp->td_ring[i].ca = 0;
- lp->td_ring[i].link = 0;
- if (lp->tx_skb[i] != NULL) {
- dev_kfree_skb_any(lp->tx_skb[i]);
- lp->tx_skb[i] = NULL;
- }
- }
- lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail = lp->tx_full = lp->tx_count = 0;
- lp-> tx_chain_status = empty;
-
- /*
- * Initialize the receive descriptors so that they
- * become a circular linked list, ie. let the last
- * descriptor point to the first again.
- */
- for (i=0; i<RC32434_NUM_RDS; i++) {
- struct sk_buff *skb = lp->rx_skb[i];
-
- if (lp->rx_skb[i] == NULL) {
- skb = dev_alloc_skb(RC32434_RBSIZE + 2);
- if (skb == NULL) {
- ERR("No memory in the system\n");
- for (j = 0; j < RC32434_NUM_RDS; j ++)
- if (lp->rx_skb[j] != NULL)
- dev_kfree_skb_any(lp->rx_skb[j]);
-
- return 1;
- }
- else {
- skb->dev = dev;
- skb_reserve(skb, 2);
- lp->rx_skb[i] = skb;
- lp->rd_ring[i].ca = CPHYSADDR(skb->data);
-
- }
- }
- lp->rd_ring[i].control = DMAD_iod_m | DMA_COUNT(RC32434_RBSIZE);
- lp->rd_ring[i].devcs = 0;
- lp->rd_ring[i].ca = CPHYSADDR(skb->data);
- lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[i+1]);
-
- }
- /* loop back */
- lp->rd_ring[RC32434_NUM_RDS-1].link = CPHYSADDR(&lp->rd_ring[0]);
- lp->rx_next_done = 0;
-
- lp->rd_ring[RC32434_NUM_RDS-1].control |= DMAD_cod_m;
- lp->rx_chain_head = 0;
- lp->rx_chain_tail = 0;
- lp->rx_chain_status = empty;
-
- __raw_writel(0, &lp->rx_dma_regs->dmas);
- /* Start Rx DMA */
- rc32434_start_rx(lp, &lp->rd_ring[0]);
-
- /* Enable F E bit in Tx DMA */
- __raw_writel(__raw_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
- /* Enable D H E bit in Rx DMA */
- __raw_writel(__raw_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
-
- /* Accept only packets destined for this Ethernet device address */
- __raw_writel(ETHARC_ab_m, &lp->eth_regs->etharc);
-
- /* Set all Ether station address registers to their initial values */
- __raw_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0);
- __raw_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0);
-
- __raw_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1);
- __raw_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1);
-
- __raw_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2);
- __raw_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2);
-
- __raw_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3);
- __raw_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3);
-
-
- /* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */
- __raw_writel(ETHMAC2_pe_m | ETHMAC2_cen_m | ETHMAC2_fd_m, &lp->eth_regs->ethmac2);
- //ETHMAC2_flc_m ETHMAC2_fd_m lp->duplex_mode
-
- /* Back to back inter-packet-gap */
- __raw_writel(0x15, &lp->eth_regs->ethipgt);
- /* Non - Back to back inter-packet-gap */
- __raw_writel(0x12, &lp->eth_regs->ethipgr);
-
- /* Management Clock Prescaler Divisor */
- /* Clock independent setting */
- __raw_writel(((idt_cpu_freq)/MII_CLOCK+1) & ~1,
- &lp->eth_regs->ethmcp);
-
- /* don't transmit until fifo contains 48b */
- __raw_writel(48, &lp->eth_regs->ethfifott);
-
- __raw_writel(ETHMAC1_re_m, &lp->eth_regs->ethmac1);
-
- napi_enable(&lp->napi);
- tasklet_enable(lp->tx_tasklet);
-
- netif_start_queue(dev);
-
- return 0;
-}
-
-static struct platform_driver korina_driver = {
- .driver.name = "korina",
- .probe = rc32434_probe,
- .remove = rc32434_remove,
-};
-
-static int __init rc32434_init_module(void)
-{
- return platform_driver_register(&korina_driver);
-}
-
-static void rc32434_cleanup_module(void)
-{
- return platform_driver_unregister(&korina_driver);
-}
-
-module_init(rc32434_init_module);
-module_exit(rc32434_cleanup_module);
+++ /dev/null
-/**************************************************************************
- *
- * BRIEF MODULE DESCRIPTION
- * Definitions for IDT RC32434 on-chip ethernet controller.
- *
- * Copyright 2004 IDT Inc. (rischelp@idt.com)
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- *
- **************************************************************************
- * May 2004 rkt, neb
- *
- * Initial Release
- *
- * Aug 2004
- *
- * Added NAPI
- *
- **************************************************************************
- */
-
-
-#include <asm/rc32434/rc32434.h>
-#include <asm/rc32434/dma_v.h>
-#include <asm/rc32434/eth_v.h>
-
-#define CONFIG_IDT_USE_NAPI 1
-#define RC32434_DEBUG 2
-//#define RC32434_PROC_DEBUG
-#undef RC32434_DEBUG
-
-#ifdef RC32434_DEBUG
-
-/* use 0 for production, 1 for verification, >2 for debug */
-static int rc32434_debug = RC32434_DEBUG;
-#define ASSERT(expr) \
- if(!(expr)) { \
- printk( "Assertion failed! %s,%s,%s,line=%d\n", \
- #expr,__FILE__,__FUNCTION__,__LINE__); }
-#define DBG(lvl, format, arg...) if (rc32434_debug > lvl) printk(KERN_INFO "%s: " format, dev->name , ## arg)
-#else
-#define ASSERT(expr) do {} while (0)
-#define DBG(lvl, format, arg...) do {} while (0)
-#endif
-
-#define INFO(format, arg...) printk(KERN_INFO "%s: " format, dev->name , ## arg)
-#define ERR(format, arg...) printk(KERN_ERR "%s: " format, dev->name , ## arg)
-#define WARN(format, arg...) printk(KERN_WARNING "%s: " format, dev->name , ## arg)
-
-/* the following must be powers of two */
-#ifdef CONFIG_IDT_USE_NAPI
-#define RC32434_NUM_RDS 64 /* number of receive descriptors */
-#define RC32434_NUM_TDS 64 /* number of transmit descriptors */
-#else
-#define RC32434_NUM_RDS 128 /* number of receive descriptors */
-#define RC32434_NUM_TDS 128 /* number of transmit descriptors */
-#endif
-
-#define RC32434_RBSIZE 1536 /* size of one resource buffer = Ether MTU */
-#define RC32434_RDS_MASK (RC32434_NUM_RDS-1)
-#define RC32434_TDS_MASK (RC32434_NUM_TDS-1)
-#define RD_RING_SIZE (RC32434_NUM_RDS * sizeof(struct DMAD_s))
-#define TD_RING_SIZE (RC32434_NUM_TDS * sizeof(struct DMAD_s))
-
-#define RC32434_TX_TIMEOUT HZ * 100
-
-#define rc32434_eth0_regs ((ETH_t)(ETH0_VirtualAddress))
-#define rc32434_eth1_regs ((ETH_t)(ETH1_VirtualAddress))
-
-enum status { filled, empty};
-#define IS_DMA_FINISHED(X) (((X) & (DMAD_f_m)) != 0)
-#define IS_DMA_DONE(X) (((X) & (DMAD_d_m)) != 0)
-
-
-/* Information that need to be kept for each board. */
-struct rc32434_local {
- ETH_t eth_regs;
- DMA_Chan_t rx_dma_regs;
- DMA_Chan_t tx_dma_regs;
- volatile DMAD_t td_ring; /* transmit descriptor ring */
- volatile DMAD_t rd_ring; /* receive descriptor ring */
-
- struct sk_buff* tx_skb[RC32434_NUM_TDS]; /* skbuffs for pkt to trans */
- struct sk_buff* rx_skb[RC32434_NUM_RDS]; /* skbuffs for pkt to trans */
-
- struct tasklet_struct * tx_tasklet;
-
- int rx_next_done;
- int rx_chain_head;
- int rx_chain_tail;
- enum status rx_chain_status;
-
- int tx_next_done;
- int tx_chain_head;
- int tx_chain_tail;
- enum status tx_chain_status;
- int tx_count;
- int tx_full;
-
- struct timer_list mii_phy_timer;
- unsigned long duplex_mode;
-
- int rx_irq;
- int tx_irq;
- int ovr_irq;
- int und_irq;
-
- struct net_device_stats stats;
- spinlock_t lock;
-
- /* debug /proc entry */
- struct proc_dir_entry *ps;
- int dma_halt_cnt; int dma_run_cnt;
- struct napi_struct napi;
- struct net_device *dev;
-};
-
-extern unsigned int idt_cpu_freq;
-
-/* Index to functions, as function prototypes. */
-static int rc32434_open(struct net_device *dev);
-static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev);
-static void rc32434_mii_handler(unsigned long data);
-static irqreturn_t rc32434_und_interrupt(int irq, void *dev_id);
-static irqreturn_t rc32434_rx_dma_interrupt(int irq, void *dev_id);
-static irqreturn_t rc32434_tx_dma_interrupt(int irq, void *dev_id);
-#ifdef RC32434_REVISION
-static irqreturn_t rc32434_ovr_interrupt(int irq, void *dev_id);
-#endif
-static int rc32434_close(struct net_device *dev);
-static struct net_device_stats *rc32434_get_stats(struct net_device *dev);
-static void rc32434_multicast_list(struct net_device *dev);
-static int rc32434_init(struct net_device *dev);
-static void rc32434_tx_timeout(struct net_device *dev);
-
-static void rc32434_tx_tasklet(unsigned long tx_data_dev);
-static int rc32434_poll(struct napi_struct *napi, int budget);
-static void rc32434_cleanup_module(void);
-
-
-static inline void rc32434_abort_dma(struct net_device *dev, DMA_Chan_t ch)
-{
- if (__raw_readl(&ch->dmac) & DMAC_run_m) {
- __raw_writel(0x10, &ch->dmac);
-
- while (!(__raw_readl(&ch->dmas) & DMAS_h_m))
- dev->trans_start = jiffies;
-
- __raw_writel(0, &ch->dmas);
- }
-
- __raw_writel(0, &ch->dmadptr);
- __raw_writel(0, &ch->dmandptr);
-}
+++ /dev/null
-/*
- * RC32434_WDT 0.01: IDT Interprise 79RC32434 watchdog driver
- * Copyright (c) Ondrej Zajicek <santiago@crfreenet.org>, 2006
- *
- * based on
- *
- * SoftDog 0.05: A Software Watchdog Device
- *
- * (c) Copyright 1996 Alan Cox <alan@redhat.com>, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- */
-
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/fs.h>
-#include <linux/mm.h>
-#include <linux/miscdevice.h>
-#include <linux/watchdog.h>
-#include <linux/reboot.h>
-#include <linux/smp_lock.h>
-#include <linux/init.h>
-#include <asm/bootinfo.h>
-#include <asm/time.h>
-#include <asm/uaccess.h>
-#include <asm/rc32434/integ.h>
-
-#define DEFAULT_TIMEOUT 15 /* (secs) Default is 15 seconds */
-#define MAX_TIMEOUT 20
-/*
- * (secs) Max is 20 seconds
- * (max frequency of counter is ~200 MHz, counter is 32-bit unsigned int)
- */
-
-#define NAME "rc32434_wdt"
-#define VERSION "0.1"
-
-static INTEG_t rc_wdt = (INTEG_t) INTEG_VirtualAddress;
-
-static int expect_close = 0;
-static int access = 0;
-static int timeout = 0;
-
-static int nowayout = WATCHDOG_NOWAYOUT;
-module_param(nowayout, int, 0);
-MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
-MODULE_LICENSE("GPL");
-
-
-static inline void start_wdt(void)
-{
- rc_wdt -> wtcount = 0;
- rc_wdt -> errcs |= ERRCS_wre_m;
- rc_wdt -> wtc |= WTC_en_m;
-}
-
-static inline void stop_wdt(void)
-{
- rc_wdt -> wtc &= ~WTC_en_m;
- rc_wdt -> errcs &= ~ERRCS_wre_m;
-}
-
-static inline void set_wdt(int new_timeout)
-{
- u32 cmp = new_timeout * mips_hpt_frequency;
- u32 state;
-
- timeout = new_timeout;
- /*
- * store and disable WTC
- */
- state = rc_wdt -> wtc & WTC_en_m;
- rc_wdt -> wtc &= ~WTC_en_m;
-
- rc_wdt -> wtcount = 0;
- rc_wdt -> wtcompare = cmp;
-
- /*
- * restore WTC
- */
- rc_wdt -> wtc |= state;
-}
-
-static inline void update_wdt(void)
-{
- rc_wdt -> wtcount = 0;
-}
-
-/*
- * Allow only one person to hold it open
- */
-
-static int wdt_open(struct inode *inode, struct file *file)
-{
- if (access)
- return -EBUSY;
- if (nowayout) {
- __module_get(THIS_MODULE);
- }
- /*
- * Activate timer
- */
- start_wdt();
- printk(KERN_INFO NAME ": enabling watchdog timer\n");
- access = 1;
- return 0;
-}
-
-static int wdt_release(struct inode *inode, struct file *file)
-{
- /*
- * Shut off the timer.
- * Lock it in if it's a module and we set nowayout
- */
- if (expect_close && nowayout == 0) {
- stop_wdt ();
- printk(KERN_INFO NAME ": disabling watchdog timer\n");
- module_put(THIS_MODULE);
- } else {
- printk (KERN_CRIT NAME ": device closed unexpectedly. WDT will not stop!\n");
- }
- access = 0;
- return 0;
-}
-
-static ssize_t wdt_write(struct file *file, const char *data, size_t len, loff_t *ppos)
-{
- /*
- * Refresh the timer.
- */
- if (len) {
- if (!nowayout) {
- size_t i;
-
- /* In case it was set long ago */
- expect_close = 0;
-
- for (i = 0; i != len; i++) {
- char c;
- if (get_user(c, data + i))
- return -EFAULT;
- if (c == 'V')
- expect_close = 1;
- }
- }
- update_wdt ();
- return len;
- }
- return 0;
-}
-
-static int wdt_ioctl(struct inode *inode, struct file *file,
- unsigned int cmd, unsigned long arg)
-{
- int new_timeout;
- static struct watchdog_info ident = {
- .options = WDIOF_SETTIMEOUT |
- WDIOF_KEEPALIVEPING |
- WDIOF_MAGICCLOSE,
- .firmware_version = 0,
- .identity = "RC32434_WDT Watchdog",
- };
- switch (cmd) {
- default:
- return -ENOTTY;
- case WDIOC_GETSUPPORT:
- if(copy_to_user((struct watchdog_info *)arg, &ident, sizeof(ident)))
- return -EFAULT;
- return 0;
- case WDIOC_GETSTATUS:
- case WDIOC_GETBOOTSTATUS:
- return put_user(0,(int *)arg);
- case WDIOC_KEEPALIVE:
- update_wdt();
- return 0;
- case WDIOC_SETTIMEOUT:
- if (get_user(new_timeout, (int *)arg))
- return -EFAULT;
- if (new_timeout < 1)
- return -EINVAL;
- if (new_timeout > MAX_TIMEOUT)
- return -EINVAL;
- set_wdt(new_timeout);
- /* Fall */
- case WDIOC_GETTIMEOUT:
- return put_user(timeout, (int *)arg);
- }
-}
-
-static struct file_operations wdt_fops = {
- owner: THIS_MODULE,
- llseek: no_llseek,
- write: wdt_write,
- ioctl: wdt_ioctl,
- open: wdt_open,
- release: wdt_release,
-};
-
-static struct miscdevice wdt_miscdev = {
- minor: WATCHDOG_MINOR,
- name: "watchdog",
- fops: &wdt_fops,
-};
-
-static char banner[] __initdata = KERN_INFO NAME ": Watchdog Timer version " VERSION ", timer margin: %d sec\n";
-
-static int __init watchdog_init(void)
-{
- int ret;
-
- /*
- * There should be check for RC32434 SoC
- */
- if (mips_machgroup != MACH_GROUP_MIKROTIK) return -1;
-
- ret = misc_register(&wdt_miscdev);
-
- if (ret)
- return ret;
-
- stop_wdt();
- set_wdt(DEFAULT_TIMEOUT);
-
- printk(banner, timeout);
-
- return 0;
-}
-
-static void __exit watchdog_exit(void)
-{
- misc_deregister(&wdt_miscdev);
-}
-
-module_init(watchdog_init);
-module_exit(watchdog_exit);
+++ /dev/null
-#ifndef __IDT_DDR_H__
-#define __IDT_DDR_H__
-
-/*******************************************************************************
- *
- * Copyright 2002 Integrated Device Technology, Inc.
- * All rights reserved.
- *
- * DDR register definition.
- *
- * File : $Id: ddr.h,v 1.2 2002/06/06 18:34:03 astichte Exp $
- *
- * Author : ryan.holmQVist@idt.com
- * Date : 20011005
- * Update :
- * $Log: ddr.h,v $
- * Revision 1.2 2002/06/06 18:34:03 astichte
- * Added XXX_PhysicalAddress and XXX_VirtualAddress
- *
- * Revision 1.1 2002/05/29 17:33:21 sysarch
- * jba File moved from vcode/include/idt/acacia
- *
- *
- ******************************************************************************/
-
-enum
-{
- DDR0_PhysicalAddress = 0x18018000,
- DDR_PhysicalAddress = DDR0_PhysicalAddress, // Default
-
- DDR0_VirtualAddress = 0xb8018000,
- DDR_VirtualAddress = DDR0_VirtualAddress, // Default
-} ;
-
-typedef struct DDR_s
-{
- u32 ddrbase ;
- u32 ddrmask ;
- u32 res1;
- u32 res2;
- u32 ddrc ;
- u32 ddrabase ;
- u32 ddramask ;
- u32 ddramap ;
- u32 ddrcust;
- u32 ddrrdc;
- u32 ddrspare;
-} volatile *DDR_t ;
-
-enum
-{
- DDR0BASE_baseaddr_b = 16,
- DDR0BASE_baseaddr_m = 0xffff0000,
-
- DDR0MASK_mask_b = 16,
- DDR0MASK_mask_m = 0xffff0000,
-
- DDR1BASE_baseaddr_b = 16,
- DDR1BASE_baseaddr_m = 0xffff0000,
-
- DDR1MASK_mask_b = 16,
- DDR1MASK_mask_m = 0xffff0000,
-
- DDRC_ata_b = 5,
- DDRC_ata_m = 0x000000E0,
- DDRC_dbw_b = 8,
- DDRC_dbw_m = 0x00000100,
- DDRC_wr_b = 9,
- DDRC_wr_m = 0x00000600,
- DDRC_ps_b = 11,
- DDRC_ps_m = 0x00001800,
- DDRC_dtype_b = 13,
- DDRC_dtype_m = 0x0000e000,
- DDRC_rfc_b = 16,
- DDRC_rfc_m = 0x000f0000,
- DDRC_rp_b = 20,
- DDRC_rp_m = 0x00300000,
- DDRC_ap_b = 22,
- DDRC_ap_m = 0x00400000,
- DDRC_rcd_b = 23,
- DDRC_rcd_m = 0x01800000,
- DDRC_cl_b = 25,
- DDRC_cl_m = 0x06000000,
- DDRC_dbm_b = 27,
- DDRC_dbm_m = 0x08000000,
- DDRC_sds_b = 28,
- DDRC_sds_m = 0x10000000,
- DDRC_atp_b = 29,
- DDRC_atp_m = 0x60000000,
- DDRC_re_b = 31,
- DDRC_re_m = 0x80000000,
-
- DDRRDC_ces_b = 0,
- DDRRDC_ces_m = 0x00000001,
- DDRRDC_ace_b = 1,
- DDRRDC_ace_m = 0x00000002,
-
- DDRABASE_baseaddr_b = 16,
- DDRABASE_baseaddr_m = 0xffff0000,
-
- DDRAMASK_mask_b = 16,
- DDRAMASK_mask_m = 0xffff0000,
-
- DDRAMAP_map_b = 16,
- DDRAMAP_map_m = 0xffff0000,
-
- DDRCUST_cs_b = 0,
- DDRCUST_cs_m = 0x00000003,
- DDRCUST_we_b = 2,
- DDRCUST_we_m = 0x00000004,
- DDRCUST_ras_b = 3,
- DDRCUST_ras_m = 0x00000008,
- DDRCUST_cas_b = 4,
- DDRCUST_cas_m = 0x00000010,
- DDRCUST_cke_b = 5,
- DDRCUST_cke_m = 0x00000020,
- DDRCUST_ba_b = 6,
- DDRCUST_ba_m = 0x000000c0,
-
- RCOUNT_rcount_b = 0,
- RCOUNT_rcount_m = 0x0000ffff,
-
- RCOMPARE_rcompare_b = 0,
- RCOMPARE_rcompare_m = 0x0000ffff,
-
- RTC_ce_b = 0,
- RTC_ce_m = 0x00000001,
- RTC_to_b = 1,
- RTC_to_m = 0x00000002,
- RTC_rqe_b = 2,
- RTC_rqe_m = 0x00000004,
-
- DDRDQSC_dm_b = 0,
- DDRDQSC_dm_m = 0x00000003,
- DDRDQSC_dqsbs_b = 2,
- DDRDQSC_dqsbs_m = 0x000000fc,
- DDRDQSC_db_b = 8,
- DDRDQSC_db_m = 0x00000100,
- DDRDQSC_dbsp_b = 9,
- DDRDQSC_dbsp_m = 0x01fffe00,
- DDRDQSC_bdp_b = 25,
- DDRDQSC_bdp_m = 0x7e000000,
-
- DDRDLLC_eao_b = 0,
- DDRDLLC_eao_m = 0x00000001,
- DDRDLLC_eo_b = 1,
- DDRDLLC_eo_m = 0x0000003e,
- DDRDLLC_fs_b = 6,
- DDRDLLC_fs_m = 0x000000c0,
- DDRDLLC_as_b = 8,
- DDRDLLC_as_m = 0x00000700,
- DDRDLLC_sp_b = 11,
- DDRDLLC_sp_m = 0x001ff800,
-
- DDRDLLFC_men_b = 0,
- DDRDLLFC_men_m = 0x00000001,
- DDRDLLFC_aen_b = 1,
- DDRDLLFC_aen_m = 0x00000002,
- DDRDLLFC_ff_b = 2,
- DDRDLLFC_ff_m = 0x00000004,
-
- DDRDLLTA_addr_b = 2,
- DDRDLLTA_addr_m = 0xfffffffc,
-
- DDRDLLED_dbe_b = 0,
- DDRDLLED_dbe_m = 0x00000001,
- DDRDLLED_dte_b = 1,
- DDRDLLED_dte_m = 0x00000002,
-
-
-} ;
-
-#endif // __IDT_DDR_H__
+++ /dev/null
-#ifndef __IDT_DMA_H__
-#define __IDT_DMA_H__
-
-/*******************************************************************************
- *
- * Copyright 2002 Integrated Device Technology, Inc.
- * All rights reserved.
- *
- * DMA register definition.
- *
- * File : $Id: dma.h,v 1.3 2002/06/06 18:34:03 astichte Exp $
- *
- * Author : ryan.holmQVist@idt.com
- * Date : 20011005
- * Update :
- * $Log: dma.h,v $
- * Revision 1.3 2002/06/06 18:34:03 astichte
- * Added XXX_PhysicalAddress and XXX_VirtualAddress
- *
- * Revision 1.2 2002/06/05 18:30:46 astichte
- * Removed IDTField
- *
- * Revision 1.1 2002/05/29 17:33:21 sysarch
- * jba File moved from vcode/include/idt/acacia
- *
- *
- ******************************************************************************/
-
-enum
-{
- DMA0_PhysicalAddress = 0x18040000,
- DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
-
- DMA0_VirtualAddress = 0xb8040000,
- DMA_VirtualAddress = DMA0_VirtualAddress, // Default
-} ;
-
-/*
- * DMA descriptor (in physical memory).
- */
-
-typedef struct DMAD_s
-{
- u32 control ; // Control. use DMAD_*
- u32 ca ; // Current Address.
- u32 devcs ; // Device control and status.
- u32 link ; // Next descriptor in chain.
-} volatile *DMAD_t ;
-
-enum
-{
- DMAD_size = sizeof (struct DMAD_s),
- DMAD_count_b = 0, // in DMAD_t -> control
- DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
- DMAD_ds_b = 20, // in DMAD_t -> control
- DMAD_ds_m = 0x00300000, // in DMAD_t -> control
- DMAD_ds_ethRcv_v = 0,
- DMAD_ds_ethXmt_v = 0,
- DMAD_ds_memToFifo_v = 0,
- DMAD_ds_fifoToMem_v = 0,
- DMAD_ds_pciToMem_v = 0,
- DMAD_ds_memToPci_v = 0,
-
- DMAD_devcmd_b = 22, // in DMAD_t -> control
- DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
- DMAD_devcmd_byte_v = 0, //memory-to-memory
- DMAD_devcmd_halfword_v = 1, //memory-to-memory
- DMAD_devcmd_word_v = 2, //memory-to-memory
- DMAD_devcmd_2words_v = 3, //memory-to-memory
- DMAD_devcmd_4words_v = 4, //memory-to-memory
- DMAD_devcmd_6words_v = 5, //memory-to-memory
- DMAD_devcmd_8words_v = 6, //memory-to-memory
- DMAD_devcmd_16words_v = 7, //memory-to-memory
- DMAD_cof_b = 25, // chain on finished
- DMAD_cof_m = 0x02000000, //
- DMAD_cod_b = 26, // chain on done
- DMAD_cod_m = 0x04000000, //
- DMAD_iof_b = 27, // interrupt on finished
- DMAD_iof_m = 0x08000000, //
- DMAD_iod_b = 28, // interrupt on done
- DMAD_iod_m = 0x10000000, //
- DMAD_t_b = 29, // terminated
- DMAD_t_m = 0x20000000, //
- DMAD_d_b = 30, // done
- DMAD_d_m = 0x40000000, //
- DMAD_f_b = 31, // finished
- DMAD_f_m = 0x80000000, //
-} ;
-
-/*
- * DMA register (within Internal Register Map).
- */
-
-struct DMA_Chan_s
-{
- u32 dmac ; // Control.
- u32 dmas ; // Status.
- u32 dmasm ; // Mask.
- u32 dmadptr ; // Descriptor pointer.
- u32 dmandptr ; // Next descriptor pointer.
-};
-
-typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
-
-//DMA_Channels use DMACH_count instead
-
-enum
-{
- DMAC_run_b = 0, //
- DMAC_run_m = 0x00000001, //
- DMAC_dm_b = 1, // done mask
- DMAC_dm_m = 0x00000002, //
- DMAC_mode_b = 2, //
- DMAC_mode_m = 0x0000000c, //
- DMAC_mode_auto_v = 0,
- DMAC_mode_burst_v = 1,
- DMAC_mode_transfer_v = 2, //usually used
- DMAC_mode_reserved_v = 3,
- DMAC_a_b = 4, //
- DMAC_a_m = 0x00000010, //
-
- DMAS_f_b = 0, // finished (sticky)
- DMAS_f_m = 0x00000001, //
- DMAS_d_b = 1, // done (sticky)
- DMAS_d_m = 0x00000002, //
- DMAS_c_b = 2, // chain (sticky)
- DMAS_c_m = 0x00000004, //
- DMAS_e_b = 3, // error (sticky)
- DMAS_e_m = 0x00000008, //
- DMAS_h_b = 4, // halt (sticky)
- DMAS_h_m = 0x00000010, //
-
- DMASM_f_b = 0, // finished (1=mask)
- DMASM_f_m = 0x00000001, //
- DMASM_d_b = 1, // done (1=mask)
- DMASM_d_m = 0x00000002, //
- DMASM_c_b = 2, // chain (1=mask)
- DMASM_c_m = 0x00000004, //
- DMASM_e_b = 3, // error (1=mask)
- DMASM_e_m = 0x00000008, //
- DMASM_h_b = 4, // halt (1=mask)
- DMASM_h_m = 0x00000010, //
-} ;
-
-/*
- * DMA channel definitions
- */
-
-enum
-{
- DMACH_ethRcv = 0,
- DMACH_ethXmt = 1,
- DMACH_memToFifo = 2,
- DMACH_fifoToMem = 3,
- DMACH_pciToMem = 4,
- DMACH_memToPci = 5,
-
- DMACH_count //must be last
-};
-
-
-typedef struct DMAC_s
-{
- struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
-} volatile *DMA_t ;
-
-#endif // __IDT_DMA_H__
-
+++ /dev/null
-#ifndef __IDT_DMA_V_H__
-#define __IDT_DMA_V_H__
-
-/*******************************************************************************
- *
- * Copyright 2002 Integrated Device Technology, Inc.
- * All rights reserved.
- *
- * DMA register definition.
- *
- * File : $Id: dma.h,v 1.3 2002/06/06 18:34:03 astichte Exp $
- *
- * Author : ryan.holmQVist@idt.com
- * Date : 20011005
- * Update :
- * $Log: dma.h,v $
- * Revision 1.3 2002/06/06 18:34:03 astichte
- * Added XXX_PhysicalAddress and XXX_VirtualAddress
- *
- * Revision 1.2 2002/06/05 18:30:46 astichte
- * Removed IDTField
- *
- * Revision 1.1 2002/05/29 17:33:21 sysarch
- * jba File moved from vcode/include/idt/acacia
- *
- *
- ******************************************************************************/
-#include <asm/rc32434/dma.h>
-#include <asm/rc32434/rc32434.h>
-#define DMA_CHAN_OFFSET 0x14
-#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
-#define DMA_COUNT(count) \
- ((count) & DMAD_count_m)
-
-#define DMA_HALT_TIMEOUT 500
-
-
-static inline int rc32434_halt_dma(DMA_Chan_t ch)
-{
- int timeout=1;
- if (local_readl(&ch->dmac) & DMAC_run_m) {
- local_writel(0, &ch->dmac);
- for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
- if (local_readl(&ch->dmas) & DMAS_h_m) {
- local_writel(0, &ch->dmas);
- break;
- }
- }
- }
-
- return timeout ? 0 : 1;
-}
-
-static inline void rc32434_start_dma(DMA_Chan_t ch, u32 dma_addr)
-{
- local_writel(0, &ch->dmandptr);
- local_writel(dma_addr, &ch->dmadptr);
-}
-
-static inline void rc32434_chain_dma(DMA_Chan_t ch, u32 dma_addr)
-{
- local_writel(dma_addr, &ch->dmandptr);
-}
-
-#endif // __IDT_DMA_V_H__
-
-
-
-
-
-
-
+++ /dev/null
-#ifndef __IDT_ETH_H__
-#define __IDT_ETH_H__
-
-/*******************************************************************************
- *
- * Copyright 2002 Integrated Device Technology, Inc.
- * All rights reserved.
- *
- * Ethernet register definition.
- *
- * File : $Id: eth.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
- *
- * Author : Allen.Stichter@idt.com
- * Date : 20020605
- * Update :
- * $Log: eth.h,v $
- * Revision 1.3 2002/06/06 18:34:04 astichte
- * Added XXX_PhysicalAddress and XXX_VirtualAddress
- *
- * Revision 1.2 2002/06/05 18:19:46 astichte
- * Added
- *
- * Revision 1.1 2002/05/29 17:33:22 sysarch
- * jba File moved from vcode/include/idt/acacia
- *
- ******************************************************************************/
-
-enum
-{
- ETH0_PhysicalAddress = 0x18060000,
- ETH_PhysicalAddress = ETH0_PhysicalAddress, // Default
-
- ETH0_VirtualAddress = 0xb8060000,
- ETH_VirtualAddress = ETH0_VirtualAddress, // Default
-} ;
-
-typedef struct
-{
- u32 ethintfc ;
- u32 ethfifott ;
- u32 etharc ;
- u32 ethhash0 ;
- u32 ethhash1 ;
- u32 ethu0 [4] ; // Reserved.
- u32 ethpfs ;
- u32 ethmcp ;
- u32 eth_u1 [10] ; // Reserved.
- u32 ethspare ;
- u32 eth_u2 [42] ; // Reserved.
- u32 ethsal0 ;
- u32 ethsah0 ;
- u32 ethsal1 ;
- u32 ethsah1 ;
- u32 ethsal2 ;
- u32 ethsah2 ;
- u32 ethsal3 ;
- u32 ethsah3 ;
- u32 ethrbc ;
- u32 ethrpc ;
- u32 ethrupc ;
- u32 ethrfc ;
- u32 ethtbc ;
- u32 ethgpf ;
- u32 eth_u9 [50] ; // Reserved.
- u32 ethmac1 ;
- u32 ethmac2 ;
- u32 ethipgt ;
- u32 ethipgr ;
- u32 ethclrt ;
- u32 ethmaxf ;
- u32 eth_u10 ; // Reserved.
- u32 ethmtest ;
- u32 miimcfg ;
- u32 miimcmd ;
- u32 miimaddr ;
- u32 miimwtd ;
- u32 miimrdd ;
- u32 miimind ;
- u32 eth_u11 ; // Reserved.
- u32 eth_u12 ; // Reserved.
- u32 ethcfsa0 ;
- u32 ethcfsa1 ;
- u32 ethcfsa2 ;
-} volatile *ETH_t;
-
-enum
-{
- ETHINTFC_en_b = 0,
- ETHINTFC_en_m = 0x00000001,
- ETHINTFC_its_b = 1,
- ETHINTFC_its_m = 0x00000002,
- ETHINTFC_rip_b = 2,
- ETHINTFC_rip_m = 0x00000004,
- ETHINTFC_jam_b = 3,
- ETHINTFC_jam_m = 0x00000008,
- ETHINTFC_ovr_b = 4,
- ETHINTFC_ovr_m = 0x00000010,
- ETHINTFC_und_b = 5,
- ETHINTFC_und_m = 0x00000020,
- ETHINTFC_iom_b = 6,
- ETHINTFC_iom_m = 0x000000c0,
-
- ETHFIFOTT_tth_b = 0,
- ETHFIFOTT_tth_m = 0x0000007f,
-
- ETHARC_pro_b = 0,
- ETHARC_pro_m = 0x00000001,
- ETHARC_am_b = 1,
- ETHARC_am_m = 0x00000002,
- ETHARC_afm_b = 2,
- ETHARC_afm_m = 0x00000004,
- ETHARC_ab_b = 3,
- ETHARC_ab_m = 0x00000008,
-
- ETHSAL_byte5_b = 0,
- ETHSAL_byte5_m = 0x000000ff,
- ETHSAL_byte4_b = 8,
- ETHSAL_byte4_m = 0x0000ff00,
- ETHSAL_byte3_b = 16,
- ETHSAL_byte3_m = 0x00ff0000,
- ETHSAL_byte2_b = 24,
- ETHSAL_byte2_m = 0xff000000,
-
- ETHSAH_byte1_b = 0,
- ETHSAH_byte1_m = 0x000000ff,
- ETHSAH_byte0_b = 8,
- ETHSAH_byte0_m = 0x0000ff00,
-
- ETHGPF_ptv_b = 0,
- ETHGPF_ptv_m = 0x0000ffff,
-
- ETHPFS_pfd_b = 0,
- ETHPFS_pfd_m = 0x00000001,
-
- ETHCFSA0_cfsa4_b = 0,
- ETHCFSA0_cfsa4_m = 0x000000ff,
- ETHCFSA0_cfsa5_b = 8,
- ETHCFSA0_cfsa5_m = 0x0000ff00,
-
- ETHCFSA1_cfsa2_b = 0,
- ETHCFSA1_cfsa2_m = 0x000000ff,
- ETHCFSA1_cfsa3_b = 8,
- ETHCFSA1_cfsa3_m = 0x0000ff00,
-
- ETHCFSA2_cfsa0_b = 0,
- ETHCFSA2_cfsa0_m = 0x000000ff,
- ETHCFSA2_cfsa1_b = 8,
- ETHCFSA2_cfsa1_m = 0x0000ff00,
-
- ETHMAC1_re_b = 0,
- ETHMAC1_re_m = 0x00000001,
- ETHMAC1_paf_b = 1,
- ETHMAC1_paf_m = 0x00000002,
- ETHMAC1_rfc_b = 2,
- ETHMAC1_rfc_m = 0x00000004,
- ETHMAC1_tfc_b = 3,
- ETHMAC1_tfc_m = 0x00000008,
- ETHMAC1_lb_b = 4,
- ETHMAC1_lb_m = 0x00000010,
- ETHMAC1_mr_b = 31,
- ETHMAC1_mr_m = 0x80000000,
-
- ETHMAC2_fd_b = 0,
- ETHMAC2_fd_m = 0x00000001,
- ETHMAC2_flc_b = 1,
- ETHMAC2_flc_m = 0x00000002,
- ETHMAC2_hfe_b = 2,
- ETHMAC2_hfe_m = 0x00000004,
- ETHMAC2_dc_b = 3,
- ETHMAC2_dc_m = 0x00000008,
- ETHMAC2_cen_b = 4,
- ETHMAC2_cen_m = 0x00000010,
- ETHMAC2_pe_b = 5,
- ETHMAC2_pe_m = 0x00000020,
- ETHMAC2_vpe_b = 6,
- ETHMAC2_vpe_m = 0x00000040,
- ETHMAC2_ape_b = 7,
- ETHMAC2_ape_m = 0x00000080,
- ETHMAC2_ppe_b = 8,
- ETHMAC2_ppe_m = 0x00000100,
- ETHMAC2_lpe_b = 9,
- ETHMAC2_lpe_m = 0x00000200,
- ETHMAC2_nb_b = 12,
- ETHMAC2_nb_m = 0x00001000,
- ETHMAC2_bp_b = 13,
- ETHMAC2_bp_m = 0x00002000,
- ETHMAC2_ed_b = 14,
- ETHMAC2_ed_m = 0x00004000,
-
- ETHIPGT_ipgt_b = 0,
- ETHIPGT_ipgt_m = 0x0000007f,
-
- ETHIPGR_ipgr2_b = 0,
- ETHIPGR_ipgr2_m = 0x0000007f,
- ETHIPGR_ipgr1_b = 8,
- ETHIPGR_ipgr1_m = 0x00007f00,
-
- ETHCLRT_maxret_b = 0,
- ETHCLRT_maxret_m = 0x0000000f,
- ETHCLRT_colwin_b = 8,
- ETHCLRT_colwin_m = 0x00003f00,
-
- ETHMAXF_maxf_b = 0,
- ETHMAXF_maxf_m = 0x0000ffff,
-
- ETHMTEST_tb_b = 2,
- ETHMTEST_tb_m = 0x00000004,
-
- ETHMCP_div_b = 0,
- ETHMCP_div_m = 0x000000ff,
-
- MIIMCFG_rsv_b = 0,
- MIIMCFG_rsv_m = 0x0000000c,
-
- MIIMCMD_rd_b = 0,
- MIIMCMD_rd_m = 0x00000001,
- MIIMCMD_scn_b = 1,
- MIIMCMD_scn_m = 0x00000002,
-
- MIIMADDR_regaddr_b = 0,
- MIIMADDR_regaddr_m = 0x0000001f,
- MIIMADDR_phyaddr_b = 8,
- MIIMADDR_phyaddr_m = 0x00001f00,
-
- MIIMWTD_wdata_b = 0,
- MIIMWTD_wdata_m = 0x0000ffff,
-
- MIIMRDD_rdata_b = 0,
- MIIMRDD_rdata_m = 0x0000ffff,
-
- MIIMIND_bsy_b = 0,
- MIIMIND_bsy_m = 0x00000001,
- MIIMIND_scn_b = 1,
- MIIMIND_scn_m = 0x00000002,
- MIIMIND_nv_b = 2,
- MIIMIND_nv_m = 0x00000004,
-
-} ;
-
-/*
- * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
- */
-enum
-{
- ETHRX_fd_b = 0,
- ETHRX_fd_m = 0x00000001,
- ETHRX_ld_b = 1,
- ETHRX_ld_m = 0x00000002,
- ETHRX_rok_b = 2,
- ETHRX_rok_m = 0x00000004,
- ETHRX_fm_b = 3,
- ETHRX_fm_m = 0x00000008,
- ETHRX_mp_b = 4,
- ETHRX_mp_m = 0x00000010,
- ETHRX_bp_b = 5,
- ETHRX_bp_m = 0x00000020,
- ETHRX_vlt_b = 6,
- ETHRX_vlt_m = 0x00000040,
- ETHRX_cf_b = 7,
- ETHRX_cf_m = 0x00000080,
- ETHRX_ovr_b = 8,
- ETHRX_ovr_m = 0x00000100,
- ETHRX_crc_b = 9,
- ETHRX_crc_m = 0x00000200,
- ETHRX_cv_b = 10,
- ETHRX_cv_m = 0x00000400,
- ETHRX_db_b = 11,
- ETHRX_db_m = 0x00000800,
- ETHRX_le_b = 12,
- ETHRX_le_m = 0x00001000,
- ETHRX_lor_b = 13,
- ETHRX_lor_m = 0x00002000,
- ETHRX_ces_b = 14,
- ETHRX_ces_m = 0x00004000,
- ETHRX_length_b = 16,
- ETHRX_length_m = 0xffff0000,
-
- ETHTX_fd_b = 0,
- ETHTX_fd_m = 0x00000001,
- ETHTX_ld_b = 1,
- ETHTX_ld_m = 0x00000002,
- ETHTX_oen_b = 2,
- ETHTX_oen_m = 0x00000004,
- ETHTX_pen_b = 3,
- ETHTX_pen_m = 0x00000008,
- ETHTX_cen_b = 4,
- ETHTX_cen_m = 0x00000010,
- ETHTX_hen_b = 5,
- ETHTX_hen_m = 0x00000020,
- ETHTX_tok_b = 6,
- ETHTX_tok_m = 0x00000040,
- ETHTX_mp_b = 7,
- ETHTX_mp_m = 0x00000080,
- ETHTX_bp_b = 8,
- ETHTX_bp_m = 0x00000100,
- ETHTX_und_b = 9,
- ETHTX_und_m = 0x00000200,
- ETHTX_of_b = 10,
- ETHTX_of_m = 0x00000400,
- ETHTX_ed_b = 11,
- ETHTX_ed_m = 0x00000800,
- ETHTX_ec_b = 12,
- ETHTX_ec_m = 0x00001000,
- ETHTX_lc_b = 13,
- ETHTX_lc_m = 0x00002000,
- ETHTX_td_b = 14,
- ETHTX_td_m = 0x00004000,
- ETHTX_crc_b = 15,
- ETHTX_crc_m = 0x00008000,
- ETHTX_le_b = 16,
- ETHTX_le_m = 0x00010000,
- ETHTX_cc_b = 17,
- ETHTX_cc_m = 0x001E0000,
-} ;
-
-#endif // __IDT_ETH_H__
-
-
-
-
+++ /dev/null
-#ifndef __IDT_ETH_V_H__
-#define __IDT_ETH_V_H__
-
-/*******************************************************************************
- *
- * Copyright 2002 Integrated Device Technology, Inc.
- * All rights reserved.
- *
- * Ethernet register definition.
- *
- * File : $Id: eth.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
- *
- * Author : Allen.Stichter@idt.com
- * Date : 20020605
- * Update :
- * $Log: eth.h,v $
- * Revision 1.3 2002/06/06 18:34:04 astichte
- * Added XXX_PhysicalAddress and XXX_VirtualAddress
- *
- * Revision 1.2 2002/06/05 18:19:46 astichte
- * Added
- *
- * Revision 1.1 2002/05/29 17:33:22 sysarch
- * jba File moved from vcode/include/idt/acacia
- *
- ******************************************************************************/
-
-#include <asm/rc32434/eth.h>
-
-#define IS_TX_TOK(X) (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b ) /* Transmit Okay */
-#define IS_TX_MP(X) (((X) & (1<<ETHTX_mp_b)) >> ETHTX_mp_b ) /* Multicast */
-#define IS_TX_BP(X) (((X) & (1<<ETHTX_bp_b)) >> ETHTX_bp_b ) /* Broadcast */
-#define IS_TX_UND_ERR(X) (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b ) /* Transmit FIFO Underflow */
-#define IS_TX_OF_ERR(X) (((X) & (1<<ETHTX_of_b)) >> ETHTX_of_b ) /* Oversized frame */
-#define IS_TX_ED_ERR(X) (((X) & (1<<ETHTX_ed_b)) >> ETHTX_ed_b ) /* Excessive deferral */
-#define IS_TX_EC_ERR(X) (((X) & (1<<ETHTX_ec_b)) >> ETHTX_ec_b) /* Excessive collisions */
-#define IS_TX_LC_ERR(X) (((X) & (1<<ETHTX_lc_b)) >> ETHTX_lc_b ) /* Late Collision */
-#define IS_TX_TD_ERR(X) (((X) & (1<<ETHTX_td_b)) >> ETHTX_td_b ) /* Transmit deferred*/
-#define IS_TX_CRC_ERR(X) (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b ) /* CRC Error */
-#define IS_TX_LE_ERR(X) (((X) & (1<<ETHTX_le_b)) >> ETHTX_le_b ) /* Length Error */
-
-#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b) /* Collision Count */
-
-#define IS_RCV_ROK(X) (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b) /* Receive Okay */
-#define IS_RCV_FM(X) (((X) & (1<<ETHRX_fm_b)) >> ETHRX_fm_b) /* Is Filter Match */
-#define IS_RCV_MP(X) (((X) & (1<<ETHRX_mp_b)) >> ETHRX_mp_b) /* Is it MP */
-#define IS_RCV_BP(X) (((X) & (1<<ETHRX_bp_b)) >> ETHRX_bp_b) /* Is it BP */
-#define IS_RCV_VLT(X) (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b) /* VLAN Tag Detect */
-#define IS_RCV_CF(X) (((X) & (1<<ETHRX_cf_b)) >> ETHRX_cf_b) /* Control Frame */
-#define IS_RCV_OVR_ERR(X) (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b) /* Receive Overflow */
-#define IS_RCV_CRC_ERR(X) (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b) /* CRC Error */
-#define IS_RCV_CV_ERR(X) (((X) & (1<<ETHRX_cv_b)) >> ETHRX_cv_b) /* Code Violation */
-#define IS_RCV_DB_ERR(X) (((X) & (1<<ETHRX_db_b)) >> ETHRX_db_b) /* Dribble Bits */
-#define IS_RCV_LE_ERR(X) (((X) & (1<<ETHRX_le_b)) >> ETHRX_le_b) /* Length error */
-#define IS_RCV_LOR_ERR(X) (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b) /* Length Out of Range */
-#define IS_RCV_CES_ERR(X) (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b) /* Preamble error */
-#define RCVPKT_LENGTH(X) (((X) & ETHRX_length_m) >> ETHRX_length_b) /* Length of the received packet */
-#endif // __IDT_ETH_V_H__
-
-
-
-
-
+++ /dev/null
-/*
- * Copyright 2002 Integrated Device Technology, Inc.
- * All rights reserved.
- *
- * GPIO register definition.
- *
- * Author : ryan.holmQVist@idt.com
- * Date : 20011005
- * Copyright (C) 2001, 2002 Ryan Holm <ryan.holmQVist@idt.com>
- * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
- */
-
-#ifndef _RC32434_GPIO_H_
-#define _RC32434_GPIO_H_
-
-#include <linux/types.h>
-
-struct rb500_gpio_reg {
- u32 gpiofunc; /* GPIO Function Register
- * gpiofunc[x]==0 bit = gpio
- * func[x]==1 bit = altfunc
- */
- u32 gpiocfg; /* GPIO Configuration Register
- * gpiocfg[x]==0 bit = input
- * gpiocfg[x]==1 bit = output
- */
- u32 gpiod; /* GPIO Data Register
- * gpiod[x] read/write gpio pinX status
- */
- u32 gpioilevel; /* GPIO Interrupt Status Register
- * interrupt level (see gpioistat)
- */
- u32 gpioistat; /* Gpio Interrupt Status Register
- * istat[x] = (gpiod[x] == level[x])
- * cleared in ISR (STICKY bits)
- */
- u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
-};
-
-/* UART GPIO signals */
-#define RC32434_UART0_SOUT (1 << 0)
-#define RC32434_UART0_SIN (1 << 1)
-#define RC32434_UART0_RTS (1 << 2)
-#define RC32434_UART0_CTS (1 << 3)
-
-/* M & P bus GPIO signals */
-#define RC32434_MP_BIT_22 (1 << 4)
-#define RC32434_MP_BIT_23 (1 << 5)
-#define RC32434_MP_BIT_24 (1 << 6)
-#define RC32434_MP_BIT_25 (1 << 7)
-
-/* CPU GPIO signals */
-#define RC32434_CPU_GPIO (1 << 8)
-
-/* Reserved GPIO signals */
-#define RC32434_AF_SPARE_6 (1 << 9)
-#define RC32434_AF_SPARE_4 (1 << 10)
-#define RC32434_AF_SPARE_3 (1 << 11)
-#define RC32434_AF_SPARE_2 (1 << 12)
-
-/* PCI messaging unit */
-#define RC32434_PCI_MSU_GPIO (1 << 13)
-
-extern int rb500_gpio_get_value(unsigned gpio);
-extern void rb500_gpio_set_value(unsigned gpio, int value);
-extern int rb500_gpio_direction_input(unsigned gpio);
-extern int rb500_gpio_direction_output(unsigned gpio, int value);
-extern void rb500_gpio_set_int_level(unsigned gpio, int value);
-extern int rb500_gpio_get_int_level(unsigned gpio);
-extern void rb500_gpio_set_int_status(unsigned gpio, int value);
-extern int rb500_gpio_get_int_status(unsigned gpio);
-extern void rb500_gpio_set_func(unsigned gpio, int value);
-extern int rb500_gpio_get_func(unsigned gpio);
-
-
-/* Wrappers for the arch-neutral GPIO API */
-
-static inline int gpio_request(unsigned gpio, const char *label)
-{
- /* Not yet implemented */
- return 0;
-}
-
-static inline void gpio_free(unsigned gpio)
-{
- /* Not yet implemented */
-}
-
-static inline int gpio_direction_input(unsigned gpio)
-{
- return rb500_gpio_direction_input(gpio);
-}
-
-static inline int gpio_direction_output(unsigned gpio, int value)
-{
- return rb500_gpio_direction_output(gpio, value);
-}
-
-static inline int gpio_get_value(unsigned gpio)
-{
- return rb500_gpio_get_value(gpio);
-}
-
-static inline void gpio_set_value(unsigned gpio, int value)
-{
- rb500_gpio_set_value(gpio, value);
-}
-
-static inline int gpio_to_irq(unsigned gpio)
-{
- return gpio;
-}
-
-static inline int irq_to_gpio(unsigned irq)
-{
- return irq;
-}
-
-/* For cansleep */
-#include <asm-generic/gpio.h>
-
-#endif /* _RC32434_GPIO_H_ */
+++ /dev/null
-#ifndef __IDT_INTEG_H__
-#define __IDT_INTEG_H__
-
-/*******************************************************************************
- *
- * Copyright 2002 Integrated Device Technology, Inc.
- * All rights reserved.
- *
- * System Integrity register definition.
- *
- * File : $Id: integ.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
- *
- * Author : ryan.holmQVist@idt.com
- * Date : 20011005
- * Update :
- * $Log: integ.h,v $
- * Revision 1.3 2002/06/06 18:34:04 astichte
- * Added XXX_PhysicalAddress and XXX_VirtualAddress
- *
- * Revision 1.2 2002/06/05 18:32:33 astichte
- * Removed IDTField
- *
- * Revision 1.1 2002/05/29 17:33:22 sysarch
- * jba File moved from vcode/include/idt/acacia
- *
- ******************************************************************************/
-
-enum
-{
- INTEG0_PhysicalAddress = 0x18030000,
- INTEG_PhysicalAddress = INTEG0_PhysicalAddress, // Default
-
- INTEG0_VirtualAddress = 0xb8030000,
- INTEG_VirtualAddress = INTEG0_VirtualAddress, // Default
-} ;
-
-// if you are looing for CEA, try rst.h
-typedef struct
-{
- u32 filler [0xc] ; // 0x30 bytes unused.
- u32 errcs ; // sticky use ERRCS_
- u32 wtcount ; // Watchdog timer count reg.
- u32 wtcompare ; // Watchdog timer timeout value.
- u32 wtc ; // Watchdog timer control. use WTC_
-} volatile *INTEG_t ;
-
-enum
-{
- ERRCS_wto_b = 0, // In INTEG_t -> errcs
- ERRCS_wto_m = 0x00000001,
- ERRCS_wne_b = 1, // In INTEG_t -> errcs
- ERRCS_wne_m = 0x00000002,
- ERRCS_ucw_b = 2, // In INTEG_t -> errcs
- ERRCS_ucw_m = 0x00000004,
- ERRCS_ucr_b = 3, // In INTEG_t -> errcs
- ERRCS_ucr_m = 0x00000008,
- ERRCS_upw_b = 4, // In INTEG_t -> errcs
- ERRCS_upw_m = 0x00000010,
- ERRCS_upr_b = 5, // In INTEG_t -> errcs
- ERRCS_upr_m = 0x00000020,
- ERRCS_udw_b = 6, // In INTEG_t -> errcs
- ERRCS_udw_m = 0x00000040,
- ERRCS_udr_b = 7, // In INTEG_t -> errcs
- ERRCS_udr_m = 0x00000080,
- ERRCS_sae_b = 8, // In INTEG_t -> errcs
- ERRCS_sae_m = 0x00000100,
- ERRCS_wre_b = 9, // In INTEG_t -> errcs
- ERRCS_wre_m = 0x00000200,
-
- WTC_en_b = 0, // In INTEG_t -> wtc
- WTC_en_m = 0x00000001,
- WTC_to_b = 1, // In INTEG_t -> wtc
- WTC_to_m = 0x00000002,
-} ;
-
-#endif // __IDT_INTEG_H__
+++ /dev/null
-#ifndef __ASM_MACH_MIPS_IRQ_H
-#define __ASM_MACH_MIPS_IRQ_H
-
-#define NR_IRQS 256
-#include_next <irq.h>
-
-#endif /* __ASM_MACH_MIPS_IRQ_H */
+++ /dev/null
-/**************************************************************************
- *
- * BRIEF MODULE DESCRIPTION
- * PCI register definitio
- *
- * Copyright 2004 IDT Inc. (rischelp@idt.com)
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- *
- **************************************************************************
- * May 2004 rkt, neb.
- *
- * Initial Release
- *
- *
- *
- **************************************************************************
- */
-
-#ifndef __IDT_PCI_H__
-#define __IDT_PCI_H__
-
-enum
-{
- PCI0_PhysicalAddress = 0x18080000,
- PCI_PhysicalAddress = PCI0_PhysicalAddress,
-
- PCI0_VirtualAddress = 0xB8080000,
- PCI_VirtualAddress = PCI0_VirtualAddress,
-} ;
-
-enum
-{
- PCI_LbaCount = 4, // Local base addresses.
-} ;
-
-typedef struct
-{
- u32 a ; // Address.
- u32 c ; // Control.
- u32 m ; // mapping.
-} PCI_Map_s ;
-
-typedef struct
-{
- u32 pcic ;
- u32 pcis ;
- u32 pcism ;
- u32 pcicfga ;
- u32 pcicfgd ;
- PCI_Map_s pcilba [PCI_LbaCount] ;
- u32 pcidac ;
- u32 pcidas ;
- u32 pcidasm ;
- u32 pcidad ;
- u32 pcidma8c ;
- u32 pcidma9c ;
- u32 pcitc ;
-} volatile *PCI_t ;
-
-// PCI messaging unit.
-enum
-{
- PCIM_Count = 2,
-} ;
-typedef struct
-{
- u32 pciim [PCIM_Count] ;
- u32 pciom [PCIM_Count] ;
- u32 pciid ;
- u32 pciiic ;
- u32 pciiim ;
- u32 pciiod ;
- u32 pciioic ;
- u32 pciioim ;
-} volatile *PCIM_t ;
-
-/*******************************************************************************
- *
- * PCI Control Register
- *
- ******************************************************************************/
-enum
-{
- PCIC_en_b = 0,
- PCIC_en_m = 0x00000001,
- PCIC_tnr_b = 1,
- PCIC_tnr_m = 0x00000002,
- PCIC_sce_b = 2,
- PCIC_sce_m = 0x00000004,
- PCIC_ien_b = 3,
- PCIC_ien_m = 0x00000008,
- PCIC_aaa_b = 4,
- PCIC_aaa_m = 0x00000010,
- PCIC_eap_b = 5,
- PCIC_eap_m = 0x00000020,
- PCIC_pcim_b = 6,
- PCIC_pcim_m = 0x000001c0,
- PCIC_pcim_disabled_v = 0,
- PCIC_pcim_tnr_v = 1, // Satellite - target not ready
- PCIC_pcim_suspend_v = 2, // Satellite - suspended CPU.
- PCIC_pcim_extern_v = 3, // Host - external arbiter.
- PCIC_pcim_fixed_v = 4, // Host - fixed priority arb.
- PCIC_pcim_roundrobin_v = 5, // Host - round robin priority.
- PCIC_pcim_reserved6_v = 6,
- PCIC_pcim_reserved7_v = 7,
- PCIC_igm_b = 9,
- PCIC_igm_m = 0x00000200,
-} ;
-
-/*******************************************************************************
- *
- * PCI Status Register
- *
- ******************************************************************************/
-enum {
- PCIS_eed_b = 0,
- PCIS_eed_m = 0x00000001,
- PCIS_wr_b = 1,
- PCIS_wr_m = 0x00000002,
- PCIS_nmi_b = 2,
- PCIS_nmi_m = 0x00000004,
- PCIS_ii_b = 3,
- PCIS_ii_m = 0x00000008,
- PCIS_cwe_b = 4,
- PCIS_cwe_m = 0x00000010,
- PCIS_cre_b = 5,
- PCIS_cre_m = 0x00000020,
- PCIS_mdpe_b = 6,
- PCIS_mdpe_m = 0x00000040,
- PCIS_sta_b = 7,
- PCIS_sta_m = 0x00000080,
- PCIS_rta_b = 8,
- PCIS_rta_m = 0x00000100,
- PCIS_rma_b = 9,
- PCIS_rma_m = 0x00000200,
- PCIS_sse_b = 10,
- PCIS_sse_m = 0x00000400,
- PCIS_ose_b = 11,
- PCIS_ose_m = 0x00000800,
- PCIS_pe_b = 12,
- PCIS_pe_m = 0x00001000,
- PCIS_tae_b = 13,
- PCIS_tae_m = 0x00002000,
- PCIS_rle_b = 14,
- PCIS_rle_m = 0x00004000,
- PCIS_bme_b = 15,
- PCIS_bme_m = 0x00008000,
- PCIS_prd_b = 16,
- PCIS_prd_m = 0x00010000,
- PCIS_rip_b = 17,
- PCIS_rip_m = 0x00020000,
-} ;
-
-/*******************************************************************************
- *
- * PCI Status Mask Register
- *
- ******************************************************************************/
-enum {
- PCISM_eed_b = 0,
- PCISM_eed_m = 0x00000001,
- PCISM_wr_b = 1,
- PCISM_wr_m = 0x00000002,
- PCISM_nmi_b = 2,
- PCISM_nmi_m = 0x00000004,
- PCISM_ii_b = 3,
- PCISM_ii_m = 0x00000008,
- PCISM_cwe_b = 4,
- PCISM_cwe_m = 0x00000010,
- PCISM_cre_b = 5,
- PCISM_cre_m = 0x00000020,
- PCISM_mdpe_b = 6,
- PCISM_mdpe_m = 0x00000040,
- PCISM_sta_b = 7,
- PCISM_sta_m = 0x00000080,
- PCISM_rta_b = 8,
- PCISM_rta_m = 0x00000100,
- PCISM_rma_b = 9,
- PCISM_rma_m = 0x00000200,
- PCISM_sse_b = 10,
- PCISM_sse_m = 0x00000400,
- PCISM_ose_b = 11,
- PCISM_ose_m = 0x00000800,
- PCISM_pe_b = 12,
- PCISM_pe_m = 0x00001000,
- PCISM_tae_b = 13,
- PCISM_tae_m = 0x00002000,
- PCISM_rle_b = 14,
- PCISM_rle_m = 0x00004000,
- PCISM_bme_b = 15,
- PCISM_bme_m = 0x00008000,
- PCISM_prd_b = 16,
- PCISM_prd_m = 0x00010000,
- PCISM_rip_b = 17,
- PCISM_rip_m = 0x00020000,
-} ;
-
-/*******************************************************************************
- *
- * PCI Configuration Address Register
- *
- ******************************************************************************/
-enum {
- PCICFGA_reg_b = 2,
- PCICFGA_reg_m = 0x000000fc,
- PCICFGA_reg_id_v = 0x00>>2, //use PCFGID_
- PCICFGA_reg_04_v = 0x04>>2, //use PCFG04_
- PCICFGA_reg_08_v = 0x08>>2, //use PCFG08_
- PCICFGA_reg_0C_v = 0x0C>>2, //use PCFG0C_
- PCICFGA_reg_pba0_v = 0x10>>2, //use PCIPBA_
- PCICFGA_reg_pba1_v = 0x14>>2, //use PCIPBA_
- PCICFGA_reg_pba2_v = 0x18>>2, //use PCIPBA_
- PCICFGA_reg_pba3_v = 0x1c>>2, //use PCIPBA_
- PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
- PCICFGA_reg_3C_v = 0x3C>>2, //use PCFG3C_
- PCICFGA_reg_pba0c_v = 0x44>>2, //use PCIPBAC_
- PCICFGA_reg_pba0m_v = 0x48>>2,
- PCICFGA_reg_pba1c_v = 0x4c>>2, //use PCIPBAC_
- PCICFGA_reg_pba1m_v = 0x50>>2,
- PCICFGA_reg_pba2c_v = 0x54>>2, //use PCIPBAC_
- PCICFGA_reg_pba2m_v = 0x58>>2,
- PCICFGA_reg_pba3c_v = 0x5c>>2, //use PCIPBAC_
- PCICFGA_reg_pba3m_v = 0x60>>2,
- PCICFGA_reg_pmgt_v = 0x64>>2,
- PCICFGA_func_b = 8,
- PCICFGA_func_m = 0x00000700,
- PCICFGA_dev_b = 11,
- PCICFGA_dev_m = 0x0000f800,
- PCICFGA_dev_internal_v = 0,
- PCICFGA_bus_b = 16,
- PCICFGA_bus_m = 0x00ff0000,
- PCICFGA_bus_type0_v = 0, //local bus
- PCICFGA_en_b = 31, // read only
- PCICFGA_en_m = 0x80000000,
-} ;
-
-enum {
- PCFGID_vendor_b = 0,
- PCFGID_vendor_m = 0x0000ffff,
- PCFGID_vendor_IDT_v = 0x111d,
- PCFGID_device_b = 16,
- PCFGID_device_m = 0xffff0000,
- PCFGID_device_Korinade_v = 0x0214,
-
- PCFG04_command_ioena_b = 1,
- PCFG04_command_ioena_m = 0x00000001,
- PCFG04_command_memena_b = 2,
- PCFG04_command_memena_m = 0x00000002,
- PCFG04_command_bmena_b = 3,
- PCFG04_command_bmena_m = 0x00000004,
- PCFG04_command_mwinv_b = 5,
- PCFG04_command_mwinv_m = 0x00000010,
- PCFG04_command_parena_b = 7,
- PCFG04_command_parena_m = 0x00000040,
- PCFG04_command_serrena_b = 9,
- PCFG04_command_serrena_m = 0x00000100,
- PCFG04_command_fastbbena_b = 10,
- PCFG04_command_fastbbena_m = 0x00000200,
- PCFG04_status_b = 16,
- PCFG04_status_m = 0xffff0000,
- PCFG04_status_66MHz_b = 21, // 66 MHz enable
- PCFG04_status_66MHz_m = 0x00200000,
- PCFG04_status_fbb_b = 23,
- PCFG04_status_fbb_m = 0x00800000,
- PCFG04_status_mdpe_b = 24,
- PCFG04_status_mdpe_m = 0x01000000,
- PCFG04_status_dst_b = 25,
- PCFG04_status_dst_m = 0x06000000,
- PCFG04_status_sta_b = 27,
- PCFG04_status_sta_m = 0x08000000,
- PCFG04_status_rta_b = 28,
- PCFG04_status_rta_m = 0x10000000,
- PCFG04_status_rma_b = 29,
- PCFG04_status_rma_m = 0x20000000,
- PCFG04_status_sse_b = 30,
- PCFG04_status_sse_m = 0x40000000,
- PCFG04_status_pe_b = 31,
- PCFG04_status_pe_m = 0x40000000,
-
- PCFG08_revId_b = 0,
- PCFG08_revId_m = 0x000000ff,
- PCFG08_classCode_b = 0,
- PCFG08_classCode_m = 0xffffff00,
- PCFG08_classCode_bridge_v = 06,
- PCFG08_classCode_proc_v = 0x0b3000, // processor-MIPS
- PCFG0C_cacheline_b = 0,
- PCFG0C_cacheline_m = 0x000000ff,
- PCFG0C_masterLatency_b = 8,
- PCFG0C_masterLatency_m = 0x0000ff00,
- PCFG0C_headerType_b = 16,
- PCFG0C_headerType_m = 0x00ff0000,
- PCFG0C_bist_b = 24,
- PCFG0C_bist_m = 0xff000000,
-
- PCIPBA_msi_b = 0,
- PCIPBA_msi_m = 0x00000001,
- PCIPBA_p_b = 3,
- PCIPBA_p_m = 0x00000004,
- PCIPBA_baddr_b = 8,
- PCIPBA_baddr_m = 0xffffff00,
-
- PCFGSS_vendorId_b = 0,
- PCFGSS_vendorId_m = 0x0000ffff,
- PCFGSS_id_b = 16,
- PCFGSS_id_m = 0xffff0000,
-
- PCFG3C_interruptLine_b = 0,
- PCFG3C_interruptLine_m = 0x000000ff,
- PCFG3C_interruptPin_b = 8,
- PCFG3C_interruptPin_m = 0x0000ff00,
- PCFG3C_minGrant_b = 16,
- PCFG3C_minGrant_m = 0x00ff0000,
- PCFG3C_maxLat_b = 24,
- PCFG3C_maxLat_m = 0xff000000,
-
- PCIPBAC_msi_b = 0,
- PCIPBAC_msi_m = 0x00000001,
- PCIPBAC_p_b = 1,
- PCIPBAC_p_m = 0x00000002,
- PCIPBAC_size_b = 2,
- PCIPBAC_size_m = 0x0000007c,
- PCIPBAC_sb_b = 7,
- PCIPBAC_sb_m = 0x00000080,
- PCIPBAC_pp_b = 8,
- PCIPBAC_pp_m = 0x00000100,
- PCIPBAC_mr_b = 9,
- PCIPBAC_mr_m = 0x00000600,
- PCIPBAC_mr_read_v =0, //no prefetching
- PCIPBAC_mr_readLine_v =1,
- PCIPBAC_mr_readMult_v =2,
- PCIPBAC_mrl_b = 11,
- PCIPBAC_mrl_m = 0x00000800,
- PCIPBAC_mrm_b = 12,
- PCIPBAC_mrm_m = 0x00001000,
- PCIPBAC_trp_b = 13,
- PCIPBAC_trp_m = 0x00002000,
-
- PCFG40_trdyTimeout_b = 0,
- PCFG40_trdyTimeout_m = 0x000000ff,
- PCFG40_retryLim_b = 8,
- PCFG40_retryLim_m = 0x0000ff00,
-};
-
-/*******************************************************************************
- *
- * PCI Local Base Address [0|1|2|3] Register
- *
- ******************************************************************************/
-enum {
- PCILBA_baddr_b = 0, // In PCI_t -> pcilba [] .a
- PCILBA_baddr_m = 0xffffff00,
-} ;
-/*******************************************************************************
- *
- * PCI Local Base Address Control Register
- *
- ******************************************************************************/
-enum {
- PCILBAC_msi_b = 0, // In pPci->pcilba[i].c
- PCILBAC_msi_m = 0x00000001,
- PCILBAC_msi_mem_v = 0,
- PCILBAC_msi_io_v = 1,
- PCILBAC_size_b = 2, // In pPci->pcilba[i].c
- PCILBAC_size_m = 0x0000007c,
- PCILBAC_sb_b = 7, // In pPci->pcilba[i].c
- PCILBAC_sb_m = 0x00000080,
- PCILBAC_rt_b = 8, // In pPci->pcilba[i].c
- PCILBAC_rt_m = 0x00000100,
- PCILBAC_rt_noprefetch_v = 0, // mem read
- PCILBAC_rt_prefetch_v = 1, // mem readline
-} ;
-
-/*******************************************************************************
- *
- * PCI Local Base Address [0|1|2|3] Mapping Register
- *
- ******************************************************************************/
-enum {
- PCILBAM_maddr_b = 8,
- PCILBAM_maddr_m = 0xffffff00,
-} ;
-
-/*******************************************************************************
- *
- * PCI Decoupled Access Control Register
- *
- ******************************************************************************/
-enum {
- PCIDAC_den_b = 0,
- PCIDAC_den_m = 0x00000001,
-} ;
-
-/*******************************************************************************
- *
- * PCI Decoupled Access Status Register
- *
- ******************************************************************************/
-enum {
- PCIDAS_d_b = 0,
- PCIDAS_d_m = 0x00000001,
- PCIDAS_b_b = 1,
- PCIDAS_b_m = 0x00000002,
- PCIDAS_e_b = 2,
- PCIDAS_e_m = 0x00000004,
- PCIDAS_ofe_b = 3,
- PCIDAS_ofe_m = 0x00000008,
- PCIDAS_off_b = 4,
- PCIDAS_off_m = 0x00000010,
- PCIDAS_ife_b = 5,
- PCIDAS_ife_m = 0x00000020,
- PCIDAS_iff_b = 6,
- PCIDAS_iff_m = 0x00000040,
-} ;
-
-/*******************************************************************************
- *
- * PCI DMA Channel 8 Configuration Register
- *
- ******************************************************************************/
-enum
-{
- PCIDMA8C_mbs_b = 0, // Maximum Burst Size.
- PCIDMA8C_mbs_m = 0x00000fff, // { pcidma8c }
- PCIDMA8C_our_b = 12, // Optimize Unaligned Burst Reads.
- PCIDMA8C_our_m = 0x00001000, // { pcidma8c }
-} ;
-
-/*******************************************************************************
- *
- * PCI DMA Channel 9 Configuration Register
- *
- ******************************************************************************/
-enum
-{
- PCIDMA9C_mbs_b = 0, // Maximum Burst Size.
- PCIDMA9C_mbs_m = 0x00000fff, // { pcidma9c }
-} ;
-
-/*******************************************************************************
- *
- * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
- *
- ******************************************************************************/
-enum {
- PCIDMAD_pt_b = 22, // in DEVCMD field (descriptor)
- PCIDMAD_pt_m = 0x00c00000, // preferred transaction field
- // These are for reads (DMA channel 8)
- PCIDMAD_devcmd_mr_v = 0, //memory read
- PCIDMAD_devcmd_mrl_v = 1, //memory read line
- PCIDMAD_devcmd_mrm_v = 2, //memory read multiple
- PCIDMAD_devcmd_ior_v = 3, //I/O read
- // These are for writes (DMA channel 9)
- PCIDMAD_devcmd_mw_v = 0, //memory write
- PCIDMAD_devcmd_mwi_v = 1, //memory write invalidate
- PCIDMAD_devcmd_iow_v = 3, //I/O write
-
- // Swap byte field applies to both DMA channel 8 and 9
- PCIDMAD_sb_b = 24, // in DEVCMD field (descriptor)
- PCIDMAD_sb_m = 0x01000000, // swap byte field
-} ;
-
-
-/*******************************************************************************
- *
- * PCI Target Control Register
- *
- ******************************************************************************/
-enum
-{
- PCITC_rtimer_b = 0, // In PCITC_t -> pcitc
- PCITC_rtimer_m = 0x000000ff,
- PCITC_dtimer_b = 8, // In PCITC_t -> pcitc
- PCITC_dtimer_m = 0x0000ff00,
- PCITC_rdr_b = 18, // In PCITC_t -> pcitc
- PCITC_rdr_m = 0x00040000,
- PCITC_ddt_b = 19, // In PCITC_t -> pcitc
- PCITC_ddt_m = 0x00080000,
-} ;
-/*******************************************************************************
- *
- * PCI messaging unit [applies to both inbound and outbound registers ]
- *
- ******************************************************************************/
-enum
-{
- PCIM_m0_b = 0, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
- PCIM_m0_m = 0x00000001, // inbound or outbound message 0
- PCIM_m1_b = 1, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
- PCIM_m1_m = 0x00000002, // inbound or outbound message 1
- PCIM_db_b = 2, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
- PCIM_db_m = 0x00000004, // inbound or outbound doorbell
-};
-
-
-
-
-
-
-#define PCI_MSG_VirtualAddress 0xB8088010
-#define rc32434_pci ((volatile PCI_t) PCI0_VirtualAddress)
-#define rc32434_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
-
-#define PCIM_SHFT 0x6
-#define PCIM_BIT_LEN 0x7
-#define PCIM_H_EA 0x3
-#define PCIM_H_IA_FIX 0x4
-#define PCIM_H_IA_RR 0x5
-
-#define PCI_ADDR_START 0x50000000
-
-#define CPUTOPCI_MEM_WIN 0x02000000
-#define CPUTOPCI_IO_WIN 0x00100000
-#define PCILBA_SIZE_SHFT 2
-#define PCILBA_SIZE_MASK 0x1F
-#define SIZE_256MB 0x1C
-#define SIZE_128MB 0x1B
-#define SIZE_64MB 0x1A
-#define SIZE_32MB 0x19
-#define SIZE_16MB 0x18
-#define SIZE_4MB 0x16
-#define SIZE_2MB 0x15
-#define SIZE_1MB 0x14
-#define KORINA_CONFIG0_ADDR 0x80000000
-#define KORINA_CONFIG1_ADDR 0x80000004
-#define KORINA_CONFIG2_ADDR 0x80000008
-#define KORINA_CONFIG3_ADDR 0x8000000C
-#define KORINA_CONFIG4_ADDR 0x80000010
-#define KORINA_CONFIG5_ADDR 0x80000014
-#define KORINA_CONFIG6_ADDR 0x80000018
-#define KORINA_CONFIG7_ADDR 0x8000001C
-#define KORINA_CONFIG8_ADDR 0x80000020
-#define KORINA_CONFIG9_ADDR 0x80000024
-#define KORINA_CONFIG10_ADDR 0x80000028
-#define KORINA_CONFIG11_ADDR 0x8000002C
-#define KORINA_CONFIG12_ADDR 0x80000030
-#define KORINA_CONFIG13_ADDR 0x80000034
-#define KORINA_CONFIG14_ADDR 0x80000038
-#define KORINA_CONFIG15_ADDR 0x8000003C
-#define KORINA_CONFIG16_ADDR 0x80000040
-#define KORINA_CONFIG17_ADDR 0x80000044
-#define KORINA_CONFIG18_ADDR 0x80000048
-#define KORINA_CONFIG19_ADDR 0x8000004C
-#define KORINA_CONFIG20_ADDR 0x80000050
-#define KORINA_CONFIG21_ADDR 0x80000054
-#define KORINA_CONFIG22_ADDR 0x80000058
-#define KORINA_CONFIG23_ADDR 0x8000005C
-#define KORINA_CONFIG24_ADDR 0x80000060
-#define KORINA_CONFIG25_ADDR 0x80000064
-#define KORINA_CMD (PCFG04_command_ioena_m | \
- PCFG04_command_memena_m | \
- PCFG04_command_bmena_m | \
- PCFG04_command_mwinv_m | \
- PCFG04_command_parena_m | \
- PCFG04_command_serrena_m )
-
-#define KORINA_STAT (PCFG04_status_mdpe_m | \
- PCFG04_status_sta_m | \
- PCFG04_status_rta_m | \
- PCFG04_status_rma_m | \
- PCFG04_status_sse_m | \
- PCFG04_status_pe_m)
-
-#define KORINA_CNFG1 ((KORINA_STAT<<16)|KORINA_CMD)
-
-#define KORINA_REVID 0
-#define KORINA_CLASS_CODE 0
-#define KORINA_CNFG2 ((KORINA_CLASS_CODE<<8) | \
- KORINA_REVID)
-
-#define KORINA_CACHE_LINE_SIZE 4
-#define KORINA_MASTER_LAT 0x3c
-#define KORINA_HEADER_TYPE 0
-#define KORINA_BIST 0
-
-#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
- (KORINA_HEADER_TYPE<<16) | \
- (KORINA_MASTER_LAT<<8) | \
- KORINA_CACHE_LINE_SIZE )
-
-#define KORINA_BAR0 0x00000008 /* 128 MB Memory */
-#define KORINA_BAR1 0x18800001 /* 1 MB IO */
-#define KORINA_BAR2 0x18000001 /* 2 MB IO window for Korina
- internal Registers */
-#define KORINA_BAR3 0x48000008 /* Spare 128 MB Memory */
-
-#define KORINA_CNFG4 KORINA_BAR0
-#define KORINA_CNFG5 KORINA_BAR1
-#define KORINA_CNFG6 KORINA_BAR2
-#define KORINA_CNFG7 KORINA_BAR3
-
-#define KORINA_SUBSYS_VENDOR_ID 0x011d
-#define KORINA_SUBSYSTEM_ID 0x0214
-#define KORINA_CNFG8 0
-#define KORINA_CNFG9 0
-#define KORINA_CNFG10 0
-#define KORINA_CNFG11 ((KORINA_SUBSYS_VENDOR_ID<<16) | \
- KORINA_SUBSYSTEM_ID)
-#define KORINA_INT_LINE 1
-#define KORINA_INT_PIN 1
-#define KORINA_MIN_GNT 8
-#define KORINA_MAX_LAT 0x38
-#define KORINA_CNFG12 0
-#define KORINA_CNFG13 0
-#define KORINA_CNFG14 0
-#define KORINA_CNFG15 ((KORINA_MAX_LAT<<24) | \
- (KORINA_MIN_GNT<<16) | \
- (KORINA_INT_PIN<<8) | \
- KORINA_INT_LINE)
-#define KORINA_RETRY_LIMIT 0x80
-#define KORINA_TRDY_LIMIT 0x80
-#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
- KORINA_TRDY_LIMIT)
-#define PCI_PBAxC_R 0x0
-#define PCI_PBAxC_RL 0x1
-#define PCI_PBAxC_RM 0x2
-#define SIZE_SHFT 2
-
-#if defined(__MIPSEB__)
-#define KORINA_PBA0C ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
- ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
- PCIPBAC_pp_m | \
- (SIZE_128MB<<SIZE_SHFT) | \
- PCIPBAC_p_m)
-#else
-#define KORINA_PBA0C ( PCIPBAC_mrl_m | \
- ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
- PCIPBAC_pp_m | \
- (SIZE_128MB<<SIZE_SHFT) | \
- PCIPBAC_p_m)
-#endif
-#define KORINA_CNFG17 KORINA_PBA0C
-#define KORINA_PBA0M 0x0
-#define KORINA_CNFG18 KORINA_PBA0M
-
-#if defined(__MIPSEB__)
-#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
- PCIPBAC_msi_m)
-#else
-#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | \
- PCIPBAC_msi_m)
-#endif
-#define KORINA_CNFG19 KORINA_PBA1C
-#define KORINA_PBA1M 0x0
-#define KORINA_CNFG20 KORINA_PBA1M
-
-#if defined(__MIPSEB__)
-#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
- PCIPBAC_msi_m)
-#else
-#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | \
- PCIPBAC_msi_m)
-#endif
-#define KORINA_CNFG21 KORINA_PBA2C
-#define KORINA_PBA2M 0x18000000
-#define KORINA_CNFG22 KORINA_PBA2M
-#define KORINA_PBA3C 0
-#define KORINA_CNFG23 KORINA_PBA3C
-#define KORINA_PBA3M 0
-#define KORINA_CNFG24 KORINA_PBA3M
-
-
-
-#define PCITC_DTIMER_VAL 8
-#define PCITC_RTIMER_VAL 0x10
-
-
-
-
-#endif // __IDT_PCI_H__
-
-
-
+++ /dev/null
-/*
- * Copyright (C) 2004 IDT Inc.
- * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-#ifndef __MIPS_RB_H__
-#define __MIPS_RB_H__
-#include <linux/genhd.h>
-
-#define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(0x18000000))
-#define DEV0BASE 0x010000
-#define DEV0MASK 0x010004
-#define DEV0C 0x010008
-#define DEV0TC 0x01000C
-#define DEV1BASE 0x010010
-#define DEV1MASK 0x010014
-#define DEV1C 0x010018
-#define DEV1TC 0x01001C
-#define DEV2BASE 0x010020
-#define DEV2MASK 0x010024
-#define DEV2C 0x010028
-#define DEV2TC 0x01002C
-#define DEV3BASE 0x010030
-#define DEV3MASK 0x010034
-#define DEV3C 0x010038
-#define DEV3TC 0x01003C
-#define BTCS 0x010040
-#define BTCOMPARE 0x010044
-#define GPIOFUNC 0x050000
-#define GPIOCFG 0x050004
-#define GPIOD 0x050008
-#define GPIOILEVEL 0x05000C
-#define GPIOISTAT 0x050010
-#define GPIONMIEN 0x050014
-#define IMASK6 0x038038
-
-#define LO_WPX (1 << 0)
-#define LO_ALE (1 << 1)
-#define LO_CLE (1 << 2)
-#define LO_CEX (1 << 3)
-#define LO_FOFF (1 << 5)
-#define LO_SPICS (1 << 6)
-#define LO_ULED (1 << 7)
-
-typedef enum {
- FUNC = 0x00,
- CFG = 0x04,
- DATA = 0x08,
- ILEVEL = 0x0c,
- ISTAT = 0x10,
- NMIEN = 0x14
-} gpio_func;
-
-extern void changeLatchU5(unsigned char orMask, unsigned char nandMask);
-extern unsigned get434Reg(unsigned regOffs);
-extern void set434Reg(unsigned regOffs, unsigned bit, unsigned len, unsigned val);
-extern void gpio_set(gpio_func func, u32 mask, u32 value);
-extern u32 gpio_get(gpio_func func);
-
-#define get434Reg(x) (*(volatile unsigned *) (IDT434_REG_BASE + (x)))
-
-struct korina_device {
- char *name;
- unsigned char mac[6];
- struct net_device *dev;
-};
-
-struct cf_device {
- int gpio_pin;
- void *dev;
- struct gendisk *gd;
-};
-
-#endif
+++ /dev/null
-/*
- ***************************************************************************
- * Definitions for IDT RC323434 CPU.
- *
- ****************************************************************************
- * Kiran Rao
- *
- * Original form
- ****************************************************************************
- * P. Sadik Oct 08, 2003
- *
- * Started revision history
- * Made IDT_BUS_FREQ a kernel configuration parameter
- ****************************************************************************
- * P. Sadik Oct 10, 2003
- *
- * Removed IDT_BUS_FREQ, since this parameter is no longer required. Instead
- * idt_cpu_freq is used everywhere
- ****************************************************************************
- * P. Sadik Oct 20, 2003
- *
- * Removed RC32434_BASE_BAUD
- ****************************************************************************
-*/
-#ifndef _RC32434_H_
-#define _RC32434_H_
-
-#include <linux/autoconf.h>
-#include <linux/delay.h>
-#include <asm/io.h>
-
-#define RC32434_REG_BASE 0x18000000
-
-#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
-
-
-#define IDT_CLOCK_MULT 2
-#define MIPS_CPU_TIMER_IRQ 7
-/* Interrupt Controller */
-#define IC_GROUP0_PEND (RC32434_REG_BASE + 0x38000)
-#define IC_GROUP0_MASK (RC32434_REG_BASE + 0x38008)
-#define IC_GROUP_OFFSET 0x0C
-
-#define NUM_INTR_GROUPS 5
-/* 16550 UARTs */
-
-#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
-#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
-#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
-#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */
-#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
-
-
-#ifdef __MIPSEB__
-#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003)
-#else
-#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000)
-#endif
-
-#define RC32434_UART0_IRQ GROUP3_IRQ_BASE + 0
-// #define EB434_UART1_IRQ GROUP4_IRQ_BASE + 11
-
-#define local_readl(addr) __raw_readl(addr)
-#define local_writel(l,addr) __raw_writel(l,addr)
-
-/* cpu pipeline flush */
-static inline void rc32434_sync(void)
-{
- __asm__ volatile ("sync");
-}
-
-static inline void rc32434_sync_udelay(int us)
-{
- __asm__ volatile ("sync");
- udelay(us);
-}
-
-static inline void rc32434_sync_delay(int ms)
-{
- __asm__ volatile ("sync");
- mdelay(ms);
-}
-
-/*
- * C access to CLZ and CLO instructions
- * (count leading zeroes/ones).
- */
-static inline int rc32434_clz(unsigned long val)
-{
- int ret;
- __asm__ volatile (
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips32\n\t"
- "clz\t%0,%1\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- : "=r" (ret)
- : "r" (val));
-
- return ret;
-}
-static inline int rc32434_clo(unsigned long val)
-{
- int ret;
- __asm__ volatile (
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips32\n\t"
- "clo\t%0,%1\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- : "=r" (ret)
- : "r" (val));
-
- return ret;
-}
-
-#endif /* _RC32434_H_ */
+++ /dev/null
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
-#define __ASM_MIPS_MACH_MIPS_WAR_H
-
-#define R4600_V1_INDEX_ICACHEOP_WAR 0
-#define R4600_V1_HIT_CACHEOP_WAR 0
-#define R4600_V2_HIT_CACHEOP_WAR 0
-#define R5432_CP0_INTERRUPT_WAR 0
-#define BCM1250_M3_WAR 0
-#define SIBYTE_1956_WAR 0
-#define MIPS4K_ICACHE_REFILL_WAR 1
-#define MIPS_CACHE_SYNC_WAR 0
-#define TX49XX_ICACHE_INDEX_INV_WAR 0
-#define RM9000_CDEX_SMP_WAR 0
-#define ICACHE_REFILLS_WORKAROUND_WAR 0
-#define R10000_LLSC_WAR 0
-#define MIPS34K_MISSED_ITLB_WAR 0
-
-#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
--- /dev/null
+/*
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ * stevel@mvista.com or source@mvista.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/pci.h>
+#include <asm/io.h>
+
+#include <asm/rc32434/rc32434.h>
+
+static int __devinitdata irq_map[2][12] = {
+ { 0, 0, 2, 3, 2, 3, 0, 0, 0, 0, 0, 1 },
+ { 0, 0, 1, 3, 0, 2, 1, 3, 0, 2, 1, 3 }
+};
+
+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+ int irq = 0;
+
+ if (dev->bus->number < 2 && PCI_SLOT(dev->devfn) < 12) {
+ irq = irq_map[dev->bus->number][PCI_SLOT(dev->devfn)];
+ }
+ return irq + GROUP4_IRQ_BASE + 4;
+}
+
--- /dev/null
+/**************************************************************************
+ *
+ * BRIEF MODULE DESCRIPTION
+ * pci_ops for IDT EB434 board
+ *
+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
+ * Copyright 2006 Felix Fietkau <nbd@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ * May 2004 rkt, neb
+ *
+ * Initial Release
+ *
+ *
+ *
+ **************************************************************************
+ */
+
+#include <linux/autoconf.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+
+#include <asm/cpu.h>
+#include <asm/io.h>
+
+#include <asm/rc32434/rc32434.h>
+#include <asm/rc32434/pci.h>
+
+#define PCI_ACCESS_READ 0
+#define PCI_ACCESS_WRITE 1
+
+
+#define PCI_CFG_SET(bus,slot,func,off) \
+ (rc32434_pci->pcicfga = (0x80000000 | \
+ ((bus) << 16) | ((slot)<<11) | \
+ ((func)<<8) | (off)))
+
+static inline int config_access(unsigned char access_type, struct pci_bus *bus,
+ unsigned int devfn, unsigned char where,
+ u32 * data)
+{
+ unsigned int slot = PCI_SLOT(devfn);
+ u8 func = PCI_FUNC(devfn);
+
+ /* Setup address */
+ PCI_CFG_SET(bus->number, slot, func, where);
+ rc32434_sync();
+
+ if (access_type == PCI_ACCESS_WRITE)
+ rc32434_pci->pcicfgd = *data;
+ else
+ *data = rc32434_pci->pcicfgd;
+
+ rc32434_sync();
+
+ return 0;
+}
+
+
+/*
+ * We can't address 8 and 16 bit words directly. Instead we have to
+ * read/write a 32bit word and mask/modify the data we actually want.
+ */
+static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
+ int where, u8 * val)
+{
+ u32 data;
+ int ret;
+
+ ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
+ *val = (data >> ((where & 3) << 3)) & 0xff;
+ return ret;
+}
+
+static int read_config_word(struct pci_bus *bus, unsigned int devfn,
+ int where, u16 * val)
+{
+ u32 data;
+ int ret;
+
+ ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
+ *val = (data >> ((where & 3) << 3)) & 0xffff;
+ return ret;
+}
+
+static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
+ int where, u32 * val)
+{
+ int ret;
+ int delay = 1;
+
+ if (bus->number == 0 && PCI_SLOT(devfn) > 21)
+ return 0;
+
+retry:
+ ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val);
+
+ /* PCI scan: check for invalid values, device may not have
+ * finished initializing */
+
+ if (where == PCI_VENDOR_ID) {
+ if (ret == 0xffffffff || ret == 0x00000000 ||
+ ret == 0x0000ffff || ret == 0xffff0000) {
+
+ if (delay > 4)
+ return 0;
+
+ delay *= 2;
+ msleep(delay);
+ goto retry;
+ }
+ }
+
+ return ret;
+}
+
+static int
+write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
+ u8 val)
+{
+ u32 data = 0;
+
+ if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
+ return -1;
+
+ data = (data & ~(0xff << ((where & 3) << 3))) |
+ (val << ((where & 3) << 3));
+
+ if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
+ return -1;
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+
+static int
+write_config_word(struct pci_bus *bus, unsigned int devfn, int where,
+ u16 val)
+{
+ u32 data = 0;
+
+ if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
+ return -1;
+
+ data = (data & ~(0xffff << ((where & 3) << 3))) |
+ (val << ((where & 3) << 3));
+
+ if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
+ return -1;
+
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+
+static int
+write_config_dword(struct pci_bus *bus, unsigned int devfn, int where,
+ u32 val)
+{
+ if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
+ return -1;
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int pci_config_read(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 * val)
+{
+ switch (size) {
+ case 1:
+ return read_config_byte(bus, devfn, where, (u8 *) val);
+ case 2:
+ return read_config_word(bus, devfn, where, (u16 *) val);
+ default:
+ return read_config_dword(bus, devfn, where, val);
+ }
+}
+
+static int pci_config_write(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 val)
+{
+ switch (size) {
+ case 1:
+ return write_config_byte(bus, devfn, where, (u8) val);
+ case 2:
+ return write_config_word(bus, devfn, where, (u16) val);
+ default:
+ return write_config_dword(bus, devfn, where, val);
+ }
+}
+
+struct pci_ops rc32434_pci_ops = {
+ .read = pci_config_read,
+ .write = pci_config_write,
+};
--- /dev/null
+/**************************************************************************
+ *
+ * BRIEF MODULE DESCRIPTION
+ * PCI initialization for IDT EB434 board
+ *
+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ * May 2004 rkt, neb
+ *
+ * Initial Release
+ *
+ *
+ *
+ **************************************************************************
+ */
+
+#include <linux/autoconf.h>
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/rc32434/rc32434.h>
+#include <asm/rc32434/pci.h>
+
+#define PCI_ACCESS_READ 0
+#define PCI_ACCESS_WRITE 1
+
+/* define an unsigned array for the PCI registers */
+unsigned int korinaCnfgRegs[25] = {
+ KORINA_CNFG1, KORINA_CNFG2, KORINA_CNFG3, KORINA_CNFG4,
+ KORINA_CNFG5, KORINA_CNFG6, KORINA_CNFG7, KORINA_CNFG8,
+ KORINA_CNFG9, KORINA_CNFG10, KORINA_CNFG11, KORINA_CNFG12,
+ KORINA_CNFG13, KORINA_CNFG14, KORINA_CNFG15, KORINA_CNFG16,
+ KORINA_CNFG17, KORINA_CNFG18, KORINA_CNFG19, KORINA_CNFG20,
+ KORINA_CNFG21, KORINA_CNFG22, KORINA_CNFG23, KORINA_CNFG24
+};
+static struct resource rc32434_res_pci_mem1;
+static struct resource rc32434_res_pci_mem2;
+
+static struct resource rc32434_res_pci_mem1 = {
+ .name = "PCI MEM1",
+ .start = 0x50000000,
+ .end = 0x5FFFFFFF,
+ .flags = IORESOURCE_MEM,
+ .parent = &rc32434_res_pci_mem1,
+ .sibling = NULL,
+ .child = &rc32434_res_pci_mem2
+};
+
+static struct resource rc32434_res_pci_mem2 = {
+ .name = "PCI Mem2",
+ .start = 0x60000000,
+ .end = 0x6FFFFFFF,
+ .flags = IORESOURCE_MEM,
+ .parent = &rc32434_res_pci_mem1,
+ .sibling = NULL,
+ .child = NULL
+};
+
+static struct resource rc32434_res_pci_io1 = {
+ .name = "PCI I/O1",
+ .start = 0x18800000,
+ .end = 0x188FFFFF,
+ .flags = IORESOURCE_IO,
+};
+
+extern struct pci_ops rc32434_pci_ops;
+
+#define PCI_MEM1_START PCI_ADDR_START
+#define PCI_MEM1_END PCI_ADDR_START + CPUTOPCI_MEM_WIN - 1
+#define PCI_MEM2_START PCI_ADDR_START + CPUTOPCI_MEM_WIN
+#define PCI_MEM2_END PCI_ADDR_START + ( 2* CPUTOPCI_MEM_WIN) - 1
+#define PCI_IO1_START PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN)
+#define PCI_IO1_END PCI_ADDR_START + (2* CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN -1
+#define PCI_IO2_START PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN
+#define PCI_IO2_END PCI_ADDR_START + (2* CPUTOPCI_MEM_WIN) + (2 * CPUTOPCI_IO_WIN) -1
+
+
+struct pci_controller rc32434_controller2;
+
+struct pci_controller rc32434_controller = {
+ .pci_ops = &rc32434_pci_ops,
+ .mem_resource = &rc32434_res_pci_mem1,
+ .io_resource = &rc32434_res_pci_io1,
+ .mem_offset = 0,
+ .io_offset = 0,
+
+};
+
+#ifdef __MIPSEB__
+#define PCI_ENDIAN_FLAG PCILBAC_sb_m
+#else
+#define PCI_ENDIAN_FLAG 0
+#endif
+
+static int __init rc32434_pcibridge_init(void)
+{
+ unsigned int pcicValue, pcicData = 0;
+ unsigned int dummyRead, pciCntlVal;
+ int loopCount;
+ unsigned int pciConfigAddr;
+
+ pcicValue = rc32434_pci->pcic;
+ pcicValue = (pcicValue >> PCIM_SHFT) & PCIM_BIT_LEN;
+ if (!((pcicValue == PCIM_H_EA) ||
+ (pcicValue == PCIM_H_IA_FIX) ||
+ (pcicValue == PCIM_H_IA_RR))) {
+ printk("PCI init error!!!\n");
+ /* Not in Host Mode, return ERROR */
+ return -1;
+ }
+ /* Enables the Idle Grant mode, Arbiter Parking */
+ pcicData |=(PCIC_igm_m|PCIC_eap_m|PCIC_en_m);
+ rc32434_pci->pcic = pcicData; /* Enable the PCI bus Interface */
+ /* Zero out the PCI status & PCI Status Mask */
+ for(;;)
+ {
+ pcicData = rc32434_pci->pcis;
+ if (!(pcicData & PCIS_rip_m))
+ break;
+ }
+
+ rc32434_pci->pcis = 0;
+ rc32434_pci->pcism = 0xFFFFFFFF;
+ /* Zero out the PCI decoupled registers */
+ rc32434_pci->pcidac=0; /* disable PCI decoupled accesses at initialization */
+ rc32434_pci->pcidas=0; /* clear the status */
+ rc32434_pci->pcidasm=0x0000007F; /* Mask all the interrupts */
+ /* Mask PCI Messaging Interrupts */
+ rc32434_pci_msg->pciiic = 0;
+ rc32434_pci_msg->pciiim = 0xFFFFFFFF;
+ rc32434_pci_msg->pciioic = 0;
+ rc32434_pci_msg->pciioim = 0;
+
+
+ /* Setup PCILB0 as Memory Window */
+ rc32434_pci->pcilba[0].a = (unsigned int) (PCI_ADDR_START);
+
+ /* setup the PCI map address as same as the local address */
+
+ rc32434_pci->pcilba[0].m = (unsigned int) (PCI_ADDR_START);
+
+
+ /* Setup PCILBA1 as MEM */
+ rc32434_pci->pcilba[0].c = ( ((SIZE_256MB & 0x1f) << PCILBAC_size_b) | PCI_ENDIAN_FLAG);
+ dummyRead = rc32434_pci->pcilba[0].c; /* flush the CPU write Buffers */
+ rc32434_pci->pcilba[1].a = 0x60000000;
+ rc32434_pci->pcilba[1].m = 0x60000000;
+
+ /* setup PCILBA2 as IO Window*/
+ rc32434_pci->pcilba[1].c = (((SIZE_256MB & 0x1f) << PCILBAC_size_b )| PCI_ENDIAN_FLAG);
+ dummyRead = rc32434_pci->pcilba[1].c; /* flush the CPU write Buffers */
+ rc32434_pci->pcilba[2].a = 0x18C00000;
+ rc32434_pci->pcilba[2].m = 0x18FFFFFF;
+
+ /* setup PCILBA2 as IO Window*/
+ rc32434_pci->pcilba[2].c = (((SIZE_4MB & 0x1f) << PCILBAC_size_b) | PCI_ENDIAN_FLAG );
+ dummyRead = rc32434_pci->pcilba[2].c; /* flush the CPU write Buffers */
+
+ /* Setup PCILBA3 as IO Window */
+ rc32434_pci->pcilba[3].a = 0x18800000;
+ rc32434_pci->pcilba[3].m = 0x18800000;
+ rc32434_pci->pcilba[3].c = ( (((SIZE_1MB & 0x1ff) << PCILBAC_size_b) | PCILBAC_msi_m) | PCI_ENDIAN_FLAG);
+ dummyRead = rc32434_pci->pcilba[3].c; /* flush the CPU write Buffers */
+
+ pciConfigAddr=(unsigned int)(0x80000004);
+ for(loopCount=0;loopCount<24;loopCount++){
+ rc32434_pci->pcicfga=pciConfigAddr;
+ dummyRead=rc32434_pci->pcicfga;
+ rc32434_pci->pcicfgd = korinaCnfgRegs[loopCount];
+ dummyRead=rc32434_pci->pcicfgd;
+ pciConfigAddr += 4;
+ }
+ rc32434_pci->pcitc = (unsigned int)((PCITC_RTIMER_VAL&0xff) << PCITC_rtimer_b)
+ | ((PCITC_DTIMER_VAL&0xff) << PCITC_dtimer_b);
+
+ pciCntlVal=rc32434_pci->pcic;
+ pciCntlVal &=~(PCIC_tnr_m);
+ rc32434_pci->pcic = pciCntlVal;
+ pciCntlVal=rc32434_pci->pcic;
+ return 0;
+}
+
+/* Do platform specific device initialization at pci_enable_device() time */
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+ if (PCI_SLOT(dev->devfn) == 6 && dev->bus->number == 0) {
+ /* disable prefetched memory range */
+ pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0);
+ pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0x10);
+
+ pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 4);
+ }
+ return 0;
+}
+
+static int __init rc32434_pci_init(void)
+{
+ printk("PCI: Initializing PCI\n");
+
+ ioport_resource.start = rc32434_res_pci_io1.start;
+ ioport_resource.end = rc32434_res_pci_io1.end;
+
+ rc32434_pcibridge_init();
+
+ register_pci_controller(&rc32434_controller);
+ rc32434_sync();
+
+ return 0;
+}
+
+arch_initcall(rc32434_pci_init);
+
--- /dev/null
+#
+# Makefile for the RB500 board specific parts of the kernel
+#
+
+obj-y += irq.o time.o setup.o serial.o prom.o gpio.o devices.o
--- /dev/null
+/*
+ * RouterBoard 500 Platform devices
+ *
+ * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
+ * Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/ctype.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+
+#include <asm/bootinfo.h>
+
+#include <asm/rc32434/rc32434.h>
+#include <asm/rc32434/dma.h>
+#include <asm/rc32434/dma_v.h>
+#include <asm/rc32434/eth.h>
+#include <asm/rc32434/rb.h>
+
+#define ETH0_DMA_RX_IRQ GROUP1_IRQ_BASE + 0
+#define ETH0_DMA_TX_IRQ GROUP1_IRQ_BASE + 1
+#define ETH0_RX_OVR_IRQ GROUP3_IRQ_BASE + 9
+#define ETH0_TX_UND_IRQ GROUP3_IRQ_BASE + 10
+
+#define ETH0_RX_DMA_ADDR (DMA0_PhysicalAddress + 0*DMA_CHAN_OFFSET)
+#define ETH0_TX_DMA_ADDR (DMA0_PhysicalAddress + 1*DMA_CHAN_OFFSET)
+
+/* NAND definitions */
+#define MEM32(x) *((volatile unsigned *) (x))
+
+#define GPIO_RDY (1 << 0x08)
+#define GPIO_WPX (1 << 0x09)
+#define GPIO_ALE (1 << 0x0a)
+#define GPIO_CLE (1 << 0x0b)
+
+extern char* board_type;
+
+static struct resource korina_dev0_res[] = {
+ {
+ .name = "korina_regs",
+ .start = ETH0_PhysicalAddress,
+ .end = ETH0_PhysicalAddress + sizeof(ETH_t),
+ .flags = IORESOURCE_MEM,
+ }, {
+ .name = "korina_rx",
+ .start = ETH0_DMA_RX_IRQ,
+ .end = ETH0_DMA_RX_IRQ,
+ .flags = IORESOURCE_IRQ
+ }, {
+ .name = "korina_tx",
+ .start = ETH0_DMA_TX_IRQ,
+ .end = ETH0_DMA_TX_IRQ,
+ .flags = IORESOURCE_IRQ
+ }, {
+ .name = "korina_ovr",
+ .start = ETH0_RX_OVR_IRQ,
+ .end = ETH0_RX_OVR_IRQ,
+ .flags = IORESOURCE_IRQ
+ }, {
+ .name = "korina_und",
+ .start = ETH0_TX_UND_IRQ,
+ .end = ETH0_TX_UND_IRQ,
+ .flags = IORESOURCE_IRQ
+ }, {
+ .name = "korina_dma_rx",
+ .start = ETH0_RX_DMA_ADDR,
+ .end = ETH0_RX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .name = "korina_dma_tx",
+ .start = ETH0_TX_DMA_ADDR,
+ .end = ETH0_TX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
+ .flags = IORESOURCE_MEM,
+ }
+};
+
+static struct korina_device korina_dev0_data = {
+ .name = "korina0",
+ .mac = {0xde, 0xca, 0xff, 0xc0, 0xff, 0xee}
+};
+
+static struct platform_device korina_dev0 = {
+ .id = 0,
+ .name = "korina",
+ .dev.platform_data = &korina_dev0_data,
+ .resource = korina_dev0_res,
+ .num_resources = ARRAY_SIZE(korina_dev0_res),
+};
+
+#define CF_GPIO_NUM 13
+
+static struct resource cf_slot0_res[] = {
+ {
+ .name = "cf_membase",
+ .flags = IORESOURCE_MEM
+ }, {
+ .name = "cf_irq",
+ .start = (8 + 4 * 32 + CF_GPIO_NUM), /* 149 */
+ .end = (8 + 4 * 32 + CF_GPIO_NUM),
+ .flags = IORESOURCE_IRQ
+ }
+};
+
+static struct cf_device cf_slot0_data = {
+ .gpio_pin = 13
+};
+
+static struct platform_device cf_slot0 = {
+ .id = 0,
+ .name = "rb500-cf",
+ .dev.platform_data = &cf_slot0_data,
+ .resource = cf_slot0_res,
+ .num_resources = ARRAY_SIZE(cf_slot0_res),
+};
+
+/* Resources and device for NAND. There is no data needed and no irqs, so just define the memory used. */
+
+/*
+ * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader
+ * will not be able to find the kernel that we load. So set the oobinfo
+ * when creating the partitions
+ */
+static struct nand_ecclayout rb500_nand_ecclayout = {
+ .eccbytes = 6,
+ .eccpos = { 8, 9, 10, 13, 14, 15 },
+ .oobavail = 9,
+ .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
+};
+
+int rb500_dev_ready(struct mtd_info *mtd)
+{
+ return MEM32(IDT434_REG_BASE + GPIOD) & GPIO_RDY;
+}
+
+void rb500_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+ struct nand_chip *chip = mtd->priv;
+ unsigned char orbits, nandbits;
+
+ if (ctrl & NAND_CTRL_CHANGE) {
+
+ orbits = (ctrl & NAND_CLE) << 1;
+ orbits |= (ctrl & NAND_ALE) >> 1;
+
+ nandbits = (~ctrl & NAND_CLE) << 1;
+ nandbits |= (~ctrl & NAND_ALE) >> 1;
+
+ changeLatchU5(orbits, nandbits);
+ }
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, chip->IO_ADDR_W);
+}
+
+static struct resource nand_slot0_res[] = {
+ [0] = {
+ .name = "nand_membase",
+ .flags = IORESOURCE_MEM
+ }
+};
+
+struct platform_nand_data rb500_nand_data = {
+ .ctrl.dev_ready = rb500_dev_ready,
+ .ctrl.cmd_ctrl = rb500_cmd_ctrl,
+};
+
+static struct platform_device nand_slot0 = {
+ .name = "gen_nand",
+ .id = -1,
+ .resource = nand_slot0_res,
+ .num_resources = ARRAY_SIZE(nand_slot0_res),
+ .dev.platform_data = &rb500_nand_data,
+};
+
+static struct mtd_partition rb500_partition_info[] = {
+ {
+ .name = "Routerboard NAND boot",
+ .offset = 0,
+ .size = 4 * 1024 * 1024,
+ }, {
+ .name = "rootfs",
+ .offset = MTDPART_OFS_NXTBLK,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+
+static struct platform_device rb500_led = {
+ .name = "rb500-led",
+ .id = 0,
+};
+
+static struct gpio_keys_button rb500_gpio_btn[] = {
+ {
+ .gpio = 1,
+ .code = BTN_0,
+ .desc = "S1",
+ .active_low = 1,
+ }
+};
+
+static struct gpio_keys_platform_data rb500_gpio_btn_data = {
+ .buttons = rb500_gpio_btn,
+ .nbuttons = ARRAY_SIZE(rb500_gpio_btn),
+};
+
+static struct platform_device rb500_button = {
+ .name = "gpio-keys",
+ .id = -1,
+ .dev = {
+ .platform_data = &rb500_gpio_btn_data,
+ }
+};
+
+static struct platform_device *rb500_devs[] = {
+ &korina_dev0,
+ &nand_slot0,
+ &cf_slot0,
+ &rb500_led,
+ &rb500_button
+};
+
+static void __init parse_mac_addr(char *macstr)
+{
+ int i, j;
+ unsigned char result, value;
+
+ for (i = 0; i < 6; i++) {
+ result = 0;
+
+ if (i != 5 && *(macstr + 2) != ':')
+ return;
+
+ for (j = 0; j < 2; j++) {
+ if (isxdigit(*macstr)
+ && (value =
+ isdigit(*macstr) ? *macstr -
+ '0' : toupper(*macstr) - 'A' + 10) < 16) {
+ result = result * 16 + value;
+ macstr++;
+ } else
+ return;
+ }
+
+ macstr++;
+ korina_dev0_data.mac[i] = result;
+ }
+}
+
+
+/* DEVICE CONTROLLER 1 */
+#define CFG_DC_DEV1 (void*)0xb8010010
+#define CFG_DC_DEV2 (void*)0xb8010020
+#define CFG_DC_DEVBASE 0x0
+#define CFG_DC_DEVMASK 0x4
+#define CFG_DC_DEVC 0x8
+#define CFG_DC_DEVTC 0xC
+
+/* NAND definitions */
+#define NAND_CHIP_DELAY 25
+
+static int rb500_nand_fixup(struct mtd_info *mtd)
+{
+ struct nand_chip *chip = mtd->priv;
+
+ if (mtd->writesize == 512)
+ chip->ecc.layout = &rb500_nand_ecclayout;
+
+ return 0;
+}
+
+static void __init rb500_nand_setup(void)
+{
+ switch (mips_machtype) {
+ case MACH_MIKROTIK_RB532A:
+ changeLatchU5(LO_FOFF | LO_CEX, LO_ULED | LO_ALE | LO_CLE | LO_WPX);
+ break;
+ default:
+ changeLatchU5(LO_WPX | LO_FOFF | LO_CEX, LO_ULED | LO_ALE | LO_CLE);
+ break;
+ }
+
+ /* Setup NAND specific settings */
+ rb500_nand_data.chip.nr_chips = 1;
+ rb500_nand_data.chip.nr_partitions = ARRAY_SIZE(rb500_partition_info);
+ rb500_nand_data.chip.partitions = rb500_partition_info;
+ rb500_nand_data.chip.chip_delay = NAND_CHIP_DELAY;
+ rb500_nand_data.chip.options = NAND_NO_AUTOINCR;
+
+ rb500_nand_data.chip.chip_fixup = &rb500_nand_fixup;
+}
+
+
+static int __init plat_setup_devices(void)
+{
+ /* Look for the CF card reader */
+ if (!readl(CFG_DC_DEV1 + CFG_DC_DEVMASK))
+ rb500_devs[1] = NULL;
+ else {
+ cf_slot0_res[0].start =
+ readl(CFG_DC_DEV1 + CFG_DC_DEVBASE);
+ cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000;
+ }
+
+ /* Read the NAND resources from the device controller */
+ nand_slot0_res[0].start = readl(CFG_DC_DEV2 + CFG_DC_DEVBASE);
+ nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000;
+
+ /* Initialise the NAND device */
+ rb500_nand_setup();
+
+ return platform_add_devices(rb500_devs, ARRAY_SIZE(rb500_devs));
+}
+
+static int __init setup_kmac(char *s)
+{
+ printk("korina mac = %s\n", s);
+ parse_mac_addr(s);
+ return 0;
+}
+
+__setup("kmac=", setup_kmac);
+
+arch_initcall(plat_setup_devices);
--- /dev/null
+/*
+ * Miscellaneous functions for IDT EB434 board
+ *
+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
+ * Copyright 2006 Phil Sutter <n0-1@freewrt.org>
+ * Copyright 2007 Florian Fainelli <florian@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+
+#include <asm/addrspace.h>
+#include <asm/gpio.h>
+
+#include <asm/rc32434/rb.h>
+
+#define GPIO_BADDR 0x18050000
+
+static volatile unsigned char *devCtl3Base;
+static unsigned char latchU5State;
+static spinlock_t clu5Lock = SPIN_LOCK_UNLOCKED;
+
+struct rb500_gpio_reg __iomem *rb500_gpio_reg0;
+EXPORT_SYMBOL(rb500_gpio_reg0);
+
+static struct resource rb500_gpio_reg0_res[] = {
+ {
+ .name = "gpio_reg0",
+ .start = GPIO_BADDR,
+ .end = GPIO_BADDR + sizeof(struct rb500_gpio_reg),
+ .flags = IORESOURCE_MEM,
+ }
+};
+
+void set434Reg(unsigned regOffs, unsigned bit, unsigned len, unsigned val)
+{
+ unsigned flags, data;
+ unsigned i = 0;
+
+ spin_lock_irqsave(&clu5Lock, flags);
+ data = *(volatile unsigned *) (IDT434_REG_BASE + regOffs);
+ for (i = 0; i != len; ++i) {
+ if (val & (1 << i))
+ data |= (1 << (i + bit));
+ else
+ data &= ~(1 << (i + bit));
+ }
+ *(volatile unsigned *) (IDT434_REG_BASE + regOffs) = data;
+ spin_unlock_irqrestore(&clu5Lock, flags);
+}
+EXPORT_SYMBOL(set434Reg);
+
+void changeLatchU5(unsigned char orMask, unsigned char nandMask)
+{
+ unsigned flags;
+
+ spin_lock_irqsave(&clu5Lock, flags);
+ latchU5State = (latchU5State | orMask) & ~nandMask;
+ if (!devCtl3Base)
+ devCtl3Base = (volatile unsigned char *)
+ KSEG1ADDR(*(volatile unsigned *)
+ KSEG1ADDR(0x18010030));
+ *devCtl3Base = latchU5State;
+ spin_unlock_irqrestore(&clu5Lock, flags);
+}
+EXPORT_SYMBOL(changeLatchU5);
+
+unsigned char getLatchU5State(void)
+{
+ return latchU5State;
+}
+EXPORT_SYMBOL(getLatchU5State);
+
+int rb500_gpio_get_value(unsigned gpio)
+{
+ return readl(&rb500_gpio_reg0->gpiod) & (1 << gpio);
+}
+EXPORT_SYMBOL(rb500_gpio_get_value);
+
+void rb500_gpio_set_value(unsigned gpio, int value)
+{
+ unsigned tmp;
+
+ tmp = readl(&rb500_gpio_reg0->gpiod) & ~(1 << gpio);
+ if (value)
+ tmp |= 1 << gpio;
+
+ writel(tmp, (void *)&rb500_gpio_reg0->gpiod);
+}
+EXPORT_SYMBOL(rb500_gpio_set_value);
+
+int rb500_gpio_direction_input(unsigned gpio)
+{
+ writel(readl(&rb500_gpio_reg0->gpiocfg) & ~(1 << gpio), (void *)&rb500_gpio_reg0->gpiocfg);
+
+ return 0;
+}
+EXPORT_SYMBOL(rb500_gpio_direction_input);
+
+int rb500_gpio_direction_output(unsigned gpio, int value)
+{
+ gpio_set_value(gpio, value);
+ writel(readl(&rb500_gpio_reg0->gpiocfg) | (1 << gpio), (void *)&rb500_gpio_reg0->gpiocfg);
+
+ return 0;
+}
+EXPORT_SYMBOL(rb500_gpio_direction_output);
+
+void rb500_gpio_set_int_level(unsigned gpio, int value)
+{
+ unsigned tmp;
+
+ tmp = readl(&rb500_gpio_reg0->gpioilevel) & ~(1 << gpio);
+ if (value)
+ tmp |= 1 << gpio;
+ writel(tmp, (void *)&rb500_gpio_reg0->gpioilevel);
+}
+EXPORT_SYMBOL(rb500_gpio_set_int_level);
+
+int rb500_gpio_get_int_level(unsigned gpio)
+{
+ return readl(&rb500_gpio_reg0->gpioilevel) & (1 << gpio);
+}
+EXPORT_SYMBOL(rb500_gpio_get_int_level);
+
+void rb500_gpio_set_int_status(unsigned gpio, int value)
+{
+ unsigned tmp;
+
+ tmp = readl(&rb500_gpio_reg0->gpioistat);
+ if (value)
+ tmp |= 1 << gpio;
+ writel(tmp, (void *)&rb500_gpio_reg0->gpioistat);
+}
+EXPORT_SYMBOL(rb500_gpio_set_int_status);
+
+int rb500_gpio_get_int_status(unsigned gpio)
+{
+ return readl(&rb500_gpio_reg0->gpioistat) & (1 << gpio);
+}
+EXPORT_SYMBOL(rb500_gpio_get_int_status);
+
+void rb500_gpio_set_func(unsigned gpio, int value)
+{
+ unsigned tmp;
+
+ tmp = readl(&rb500_gpio_reg0->gpiofunc);
+ if (value)
+ tmp |= 1 << gpio;
+ writel(tmp, (void *)&rb500_gpio_reg0->gpiofunc);
+}
+EXPORT_SYMBOL(rb500_gpio_set_func);
+
+int rb500_gpio_get_func(unsigned gpio)
+{
+ return readl(&rb500_gpio_reg0->gpiofunc) & (1 << gpio);
+}
+EXPORT_SYMBOL(rb500_gpio_get_func);
+
+int __init rb500_gpio_init(void)
+{
+ rb500_gpio_reg0 = ioremap_nocache(rb500_gpio_reg0_res[0].start,
+ rb500_gpio_reg0_res[0].end -
+ rb500_gpio_reg0_res[0].start);
+
+ if (!rb500_gpio_reg0) {
+ printk(KERN_ERR "rb500: cannot remap GPIO register 0\n");
+ return -ENXIO;
+ }
+
+ return 0;
+}
+arch_initcall(rb500_gpio_init);
--- /dev/null
+/*
+ * BRIEF MODULE DESCRIPTION
+ * RC32434 interrupt routines.
+ *
+ * Copyright 2002 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ * stevel@mvista.com or source@mvista.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/kernel_stat.h>
+#include <linux/module.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/timex.h>
+#include <linux/slab.h>
+#include <linux/random.h>
+#include <linux/delay.h>
+
+#include <asm/bitops.h>
+#include <asm/bootinfo.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/time.h>
+#include <asm/mipsregs.h>
+#include <asm/system.h>
+#include <asm/rc32434/rc32434.h>
+#include <asm/rc32434/gpio.h>
+
+extern void set_debug_traps(void);
+extern irq_cpustat_t irq_stat [NR_CPUS];
+unsigned int local_bh_count[NR_CPUS];
+unsigned int local_irq_count[NR_CPUS];
+
+static unsigned int startup_irq(unsigned int irq);
+static void rb500_end_irq(unsigned int irq_nr);
+static void mask_and_ack_irq(unsigned int irq_nr);
+static void rb500_enable_irq(unsigned int irq_nr);
+static void rb500_disable_irq(unsigned int irq_nr);
+
+extern void __init init_generic_irq(void);
+extern struct rb500_gpio_reg __iomem *rb500_gpio_reg0;
+
+typedef struct {
+ u32 mask; /* mask of valid bits in pending/mask registers */
+ volatile u32 *base_addr;
+} intr_group_t;
+
+#define RC32434_NR_IRQS (GROUP4_IRQ_BASE + 32)
+
+#if (NR_IRQS < RC32434_NR_IRQS)
+#error Too little irqs defined. Did you override <asm/irq.h> ?
+#endif
+
+static const intr_group_t intr_group[NUM_INTR_GROUPS] = {
+ { 0x0000efff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET) },
+ { 0x00001fff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET) },
+ { 0x00000007, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET) },
+ { 0x0003ffff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET) },
+ { 0xffffffff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET) }
+};
+
+#define READ_PEND(base) (*(base))
+#define READ_MASK(base) (*(base + 2))
+#define WRITE_MASK(base, val) (*(base + 2) = (val))
+
+static inline int irq_to_group(unsigned int irq_nr)
+{
+ return ((irq_nr - GROUP0_IRQ_BASE) >> 5);
+}
+
+static inline int group_to_ip(unsigned int group)
+{
+ return group + 2;
+}
+
+static inline void enable_local_irq(unsigned int ip)
+{
+ int ipnum = 0x100 << ip;
+ clear_c0_cause(ipnum);
+ set_c0_status(ipnum);
+}
+
+static inline void disable_local_irq(unsigned int ip)
+{
+ int ipnum = 0x100 << ip;
+ clear_c0_status(ipnum);
+}
+
+static inline void ack_local_irq(unsigned int ip)
+{
+ int ipnum = 0x100 << ip;
+ clear_c0_cause(ipnum);
+}
+
+static void rb500_enable_irq(unsigned int irq_nr)
+{
+ int ip = irq_nr - GROUP0_IRQ_BASE;
+ unsigned int group, intr_bit;
+ volatile unsigned int *addr;
+
+
+ if (ip < 0)
+ enable_local_irq(irq_nr);
+ else {
+ group = ip >> 5;
+
+ ip &= (1<<5)-1;
+ intr_bit = 1 << ip;
+
+ enable_local_irq(group_to_ip(group));
+
+ addr = intr_group[group].base_addr;
+ WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
+ }
+}
+
+static void rb500_disable_irq(unsigned int irq_nr)
+{
+ int ip = irq_nr - GROUP0_IRQ_BASE;
+ unsigned int group, intr_bit, mask;
+ volatile unsigned int *addr;
+
+ if (ip < 0) {
+ disable_local_irq(irq_nr);
+ }else{
+ group = ip >> 5;
+
+ ip &= (1<<5) -1;
+ intr_bit = 1 << ip;
+ addr = intr_group[group].base_addr;
+ mask = READ_MASK(addr);
+ mask |= intr_bit;
+ WRITE_MASK(addr,mask);
+
+ /*
+ * if there are no more interrupts enabled in this
+ * group, disable corresponding IP
+ */
+ if (mask == intr_group[group].mask)
+ disable_local_irq(group_to_ip(group));
+ }
+}
+
+static unsigned int startup_irq(unsigned int irq_nr)
+{
+ rb500_enable_irq(irq_nr);
+ return 0;
+}
+
+static void shutdown_irq(unsigned int irq_nr)
+{
+ rb500_disable_irq(irq_nr);
+ return;
+}
+
+static void mask_and_ack_irq(unsigned int irq_nr)
+{
+ rb500_disable_irq(irq_nr);
+ ack_local_irq(group_to_ip(irq_to_group(irq_nr)));
+}
+
+static void rb500_end_irq(unsigned int irq_nr)
+{
+
+ int ip = irq_nr - GROUP0_IRQ_BASE;
+ unsigned int intr_bit, group;
+ volatile unsigned int *addr;
+
+ if ((irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
+ printk("warning: end_irq %d did not enable (%x)\n",
+ irq_nr, irq_desc[irq_nr].status);
+ return;
+ }
+
+ if (ip < 0) {
+ enable_local_irq(irq_nr);
+ } else {
+ group = ip >> 5;
+
+ ip &= (1 << 5) - 1;
+ intr_bit = 1 << ip;
+
+ if (irq_nr >= GROUP4_IRQ_BASE && irq_nr <= (GROUP4_IRQ_BASE + 13)) {
+ rb500_gpio_reg0->gpioistat = rb500_gpio_reg0->gpioistat & ~intr_bit;
+ }
+
+ enable_local_irq(group_to_ip(group));
+
+ addr = intr_group[group].base_addr;
+ WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
+ }
+}
+
+static struct hw_interrupt_type rc32434_irq_type = {
+ .typename = "RB500",
+ .startup = startup_irq,
+ .shutdown = shutdown_irq,
+ .enable = rb500_enable_irq,
+ .disable = rb500_disable_irq,
+ .ack = mask_and_ack_irq,
+ .end = rb500_end_irq,
+};
+
+
+void __init arch_init_irq(void)
+{
+ int i;
+
+ printk("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS);
+ memset(irq_desc, 0, sizeof(irq_desc));
+
+ for (i = 0; i < RC32434_NR_IRQS; i++) {
+ irq_desc[i].status = IRQ_DISABLED;
+ irq_desc[i].action = NULL;
+ irq_desc[i].depth = 1;
+ irq_desc[i].chip = &rc32434_irq_type;
+ spin_lock_init(&irq_desc[i].lock);
+ }
+}
+
+/* Main Interrupt dispatcher */
+asmlinkage void plat_irq_dispatch(void)
+{
+ unsigned int ip, pend, group;
+ volatile unsigned int *addr;
+ unsigned int cp0_cause = read_c0_cause() & read_c0_status();
+
+ if (cp0_cause & CAUSEF_IP7) {
+ do_IRQ(7);
+ } else if ((ip = (cp0_cause & 0x7c00))) {
+ group = 21 - rc32434_clz(ip);
+
+ addr = intr_group[group].base_addr;
+
+ pend = READ_PEND(addr);
+ pend &= ~READ_MASK(addr); // only unmasked interrupts
+ pend = 39 - rc32434_clz(pend);
+ do_IRQ((group << 5) + pend);
+ }
+}
--- /dev/null
+/*
+* prom.c
+**********************************************************************
+* P . Sadik Oct 10, 2003
+*
+* Started change log
+* idt_cpu_freq is make a kernel configuration parameter
+* idt_cpu_freq is exported so that other modules can use it.
+* Code cleanup
+**********************************************************************
+* P. Sadik Oct 20, 2003
+*
+* Removed NVRAM code from here, since they are already available under
+* nvram directory.
+* Added serial port initialisation.
+**********************************************************************
+**********************************************************************
+* P. Sadik Oct 30, 2003
+*
+* Added reset_cons_port
+**********************************************************************
+
+ P.Christeas, 2005-2006
+ Port to 2.6, add 2.6 cmdline parsing
+
+*/
+
+#include <linux/autoconf.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/string.h>
+#include <linux/console.h>
+#include <asm/bootinfo.h>
+#include <linux/bootmem.h>
+#include <linux/ioport.h>
+#include <linux/blkdev.h>
+#include <asm/rc32434/ddr.h>
+
+#define PROM_ENTRY(x) (0xbfc00000+((x)*8))
+extern void __init setup_serial_port(void);
+
+unsigned int idt_cpu_freq = 132000000;
+EXPORT_SYMBOL(idt_cpu_freq);
+unsigned int gpio_bootup_state = 0;
+EXPORT_SYMBOL(gpio_bootup_state);
+
+char mips_mac_address[18] = "08:00:06:05:40:01";
+EXPORT_SYMBOL(mips_mac_address);
+
+/* what to append to cmdline when button is [not] pressed */
+#define GPIO_INIT_NOBUTTON ""
+#define GPIO_INIT_BUTTON " 2"
+
+#ifdef CONFIG_MIKROTIK_RB500
+unsigned soft_reboot = 0;
+EXPORT_SYMBOL(soft_reboot);
+#endif
+
+#define SR_NMI 0x00180000 /* NMI */
+#define SERIAL_SPEED_ENTRY 0x00000001
+
+#ifdef CONFIG_REMOTE_DEBUG
+extern int remote_debug;
+#endif
+
+#define FREQ_TAG "HZ="
+#define GPIO_TAG "gpio="
+#define KMAC_TAG "kmac="
+#define MEM_TAG "mem="
+#define BOARD_TAG "board="
+#define IGNORE_CMDLINE_MEM 1
+#define DEBUG_DDR
+
+#define BOARD_RB532 "500"
+#define BOARD_RB532A "500r5"
+
+void parse_soft_settings(unsigned *ptr, unsigned size);
+void parse_hard_settings(unsigned *ptr, unsigned size);
+
+void __init prom_setup_cmdline(void);
+
+void __init prom_init(void)
+{
+ DDR_t ddr = (DDR_t) DDR_VirtualAddress; /* define the pointer to the DDR registers */
+ phys_t memsize = 0-ddr->ddrmask;
+
+ /* this should be the very first message, even before serial is properly initialized */
+ prom_setup_cmdline();
+ setup_serial_port();
+
+ soft_reboot = read_c0_status() & SR_NMI;
+ pm_power_off = NULL;
+
+ /*
+ * give all RAM to boot allocator,
+ * except for the first 0x400 and the last 0x200 bytes
+ */
+ add_memory_region(ddr->ddrbase + 0x400, memsize - 0x600, BOOT_MEM_RAM);
+}
+
+void __init prom_free_prom_memory(void)
+{
+ /* No prom memory to free */
+}
+
+static inline int match_tag(char *arg, const char *tag)
+{
+ return (strncmp(arg, tag, strlen(tag)) == 0);
+}
+
+static inline unsigned long tag2ul(char *arg, const char *tag)
+{
+ char *num = arg+strlen(tag);
+ return simple_strtoul(num, 0, 10);
+}
+
+extern char _image_cmdline;
+void __init prom_setup_cmdline(void){
+ char cmd_line[CL_SIZE];
+ char *cp;
+ int prom_argc;
+ char **prom_argv, **prom_envp;
+ int i;
+
+ prom_argc = fw_arg0;
+ prom_argv = (char **) fw_arg1;
+ prom_envp = (char **) fw_arg2;
+
+ cp=cmd_line;
+ /* Note: it is common that parameters start at argv[1] and not argv[0],
+ however, our elf loader starts at [0] */
+ for(i=0;i<prom_argc;i++){
+ if (match_tag(prom_argv[i], FREQ_TAG)) {
+ idt_cpu_freq = tag2ul(prom_argv[i], FREQ_TAG);
+ continue;
+ }
+#ifdef IGNORE_CMDLINE_MEM
+ /* parses out the "mem=xx" arg */
+ if (match_tag(prom_argv[i], MEM_TAG)) {
+ continue;
+ }
+#endif
+ if (i>0) *(cp++) = ' ';
+ if (match_tag(prom_argv[i], BOARD_TAG)) {
+ char *board = prom_argv[i] + strlen(BOARD_TAG);
+ if (match_tag(board, BOARD_RB532A))
+ mips_machtype = MACH_MIKROTIK_RB532A;
+ else
+ mips_machtype = MACH_MIKROTIK_RB532;
+ }
+
+ if (match_tag(prom_argv[i], GPIO_TAG)) {
+ gpio_bootup_state = tag2ul(prom_argv[i], GPIO_TAG);
+ }
+ strcpy(cp,prom_argv[i]);
+ cp+=strlen(prom_argv[i]);
+ }
+ *(cp++) = ' ';
+ strcpy(cp,(&_image_cmdline + 8));
+ cp += strlen(&_image_cmdline);
+
+ i=strlen(arcs_cmdline);
+ if (i>0){
+ *(cp++) = ' ';
+ strcpy(cp,arcs_cmdline);
+ cp+=strlen(arcs_cmdline);
+ }
+ if (gpio_bootup_state&0x02)
+ strcpy(cp,GPIO_INIT_NOBUTTON);
+ else
+ strcpy(cp,GPIO_INIT_BUTTON);
+ cmd_line[CL_SIZE-1] = '\0';
+
+ strcpy(arcs_cmdline,cmd_line);
+}
+
--- /dev/null
+/**************************************************************************
+ *
+ * BRIEF MODULE DESCRIPTION
+ * Serial port initialisation.
+ *
+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ * May 2004 rkt, neb
+ *
+ * Initial Release
+ *
+ *
+ *
+ **************************************************************************
+ */
+
+
+#include <linux/autoconf.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/pci.h>
+#include <linux/interrupt.h>
+#include <linux/tty.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+#include <linux/serial_8250.h>
+
+#include <asm/time.h>
+#include <asm/cpu.h>
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+#include <asm/serial.h>
+#include <asm/rc32434/rc32434.h>
+
+extern unsigned int idt_cpu_freq;
+
+static struct uart_port serial_req = {
+ .type = PORT_16550A,
+ .line = 0,
+ .irq = RC32434_UART0_IRQ,
+ //.flags = STD_COM_FLAGS,
+ .iotype = UPIO_MEM,
+ .membase = (char *) KSEG1ADDR(RC32434_UART0_BASE),
+// .fifosize = 14
+ .regshift = 2
+};
+
+int __init setup_serial_port(void)
+{
+ serial_req.uartclk = idt_cpu_freq;
+
+ if (early_serial_setup(&serial_req))
+ return -ENODEV;
+
+ return(0);
+}
--- /dev/null
+/*
+ * setup.c - boot time setup code
+ */
+
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/irq.h>
+#include <linux/ioport.h>
+#include <linux/pm.h>
+#include <asm/bootinfo.h>
+#include <asm/mipsregs.h>
+#include <asm/pgtable.h>
+#include <asm/reboot.h>
+#include <asm/addrspace.h> /* for KSEG1ADDR() */
+#include <asm/time.h>
+#include <asm/io.h>
+#include <asm/rc32434/rc32434.h>
+#include <asm/rc32434/pci.h>
+
+#ifdef CONFIG_PCI
+extern void rc32434_time_init(void);
+extern int __init rc32434_pcibridge_init(void);
+#endif
+
+#define epldMask ((volatile unsigned char *)0xB900000d)
+
+static void rb_machine_restart(char *command)
+{
+ /* just jump to the reset vector */
+ * (volatile unsigned *) KSEG1ADDR(0x18008000) = 0x80000001;
+ ((void (*)(void))KSEG1ADDR(0x1FC00000u))();
+}
+
+static void rb_machine_halt(void)
+{
+ for(;;) continue;
+}
+
+#ifdef CONFIG_CPU_HAS_WB
+void (*__wbflush) (void);
+
+static void rb_write_buffer_flush(void)
+{
+ __asm__ __volatile__
+ ("sync\n\t" "nop\n\t" "loop: bc0f loop\n\t" "nop\n\t");
+}
+#endif
+
+void __init plat_mem_setup(void)
+{
+ unsigned int pciCntlVal;
+
+ //board_time_init = rc32434_time_init;
+
+#ifdef CONFIG_CPU_HAS_WB
+ __wbflush = rb_write_buffer_flush;
+#endif
+ _machine_restart = rb_machine_restart;
+ _machine_halt = rb_machine_halt;
+ /*_machine_power_off = rb_machine_power_halt;*/
+ pm_power_off = rb_machine_halt;
+
+ set_io_port_base(KSEG1);
+
+ pciCntlVal=rc32434_pci->pcic;
+ pciCntlVal &= 0xFFFFFF7;
+ rc32434_pci->pcic = pciCntlVal;
+
+#ifdef CONFIG_PCI
+ /* Enable PCI interrupts in EPLD Mask register */
+ *epldMask = 0x0;
+ *(epldMask + 1) = 0x0;
+#endif
+ write_c0_wired(0);
+}
+
+const char *get_system_type(void)
+{
+ return "MIPS RB500";
+}
--- /dev/null
+/*
+****************************************************************************
+* Carsten Langgaard, carstenl@mips.com
+* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
+*
+***************************************************************************
+*
+* This program is free software; you can distribute it and/or modify it
+* under the terms of the GNU General Public License (Version 2) as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope it will be useful, but WITHOUT
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+* for more details.
+*
+* You should have received a copy of the GNU General Public License along
+* with this program; if not, write to the Free Software Foundation, Inc.,
+* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+*
+****************************************************************************
+*
+* Setting up the clock on the MIPS boards.
+*
+****************************************************************************
+* P. Sadik Oct 10, 2003
+*
+* Started change log.
+* mips_counter_frequency is now calculated at run time, based on idt_cpu_freq.
+* Code cleanup
+****************************************************************************
+*/
+
+#include <linux/autoconf.h>
+#include <linux/init.h>
+#include <linux/kernel_stat.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/mc146818rtc.h>
+#include <linux/irq.h>
+#include <linux/timex.h>
+
+#include <asm/irq_cpu.h>
+#include <asm/mipsregs.h>
+#include <asm/ptrace.h>
+#include <asm/debug.h>
+#include <asm/rc32434/rc32434.h>
+
+static unsigned long r4k_offset; /* Amount to incr compare reg each time */
+extern unsigned int mips_hpt_frequency;
+extern unsigned int idt_cpu_freq;
+
+/*
+ * Figure out the r4k offset, the amount to increment the compare
+ * register for each time tick. There is no RTC available.
+ *
+ * The RC32434 counts at half the CPU *core* speed.
+ */
+static unsigned long __init cal_r4koff(void)
+{
+ mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
+ return (mips_hpt_frequency / HZ);
+}
+
+
+void __init plat_time_init(void)
+{
+ unsigned int est_freq, flags;
+
+ local_irq_save(flags);
+
+ printk("calculating r4koff... ");
+ r4k_offset = cal_r4koff();
+ printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
+
+ est_freq = 2*r4k_offset*HZ;
+ est_freq += 5000; /* round */
+ est_freq -= est_freq%10000;
+ printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
+ (est_freq%1000000)*100/1000000);
+ local_irq_restore(flags);
+}
--- /dev/null
+## Makefile for the RB532 CF port
+
+obj-y += bdev.o ata.o
--- /dev/null
+/* CF-mips driver
+ This is a block driver for the direct (mmaped) interface to the CF-slot,
+ found in Routerboard.com's RB532 board
+ See SDK provided from routerboard.com.
+
+ Module adapted By P.Christeas <p_christeas@yahoo.com>, 2005-6.
+ Cleaned up and adapted to platform_device by Felix Fietkau <nbd@openwrt.org>
+
+ This work is redistributed under the terms of the GNU General Public License.
+*/
+
+#include <linux/kernel.h> /* printk() */
+#include <linux/module.h> /* module to be loadable */
+#include <linux/delay.h>
+#include <linux/sched.h>
+#include <linux/pci.h>
+#include <linux/ioport.h> /* request_mem_region() */
+
+#include <asm/gpio.h>
+#include <asm/unaligned.h> /* ioremap() */
+#include <asm/io.h> /* ioremap() */
+#include <asm/rc32434/rb.h>
+
+#include "ata.h"
+
+#define REQUEST_MEM_REGION 0
+#define DEBUG 1
+
+#if DEBUG
+#define DEBUGP printk
+#else
+#define DEBUGP(format, args...)
+#endif
+
+#define SECS 1000000 /* unit for wait_not_busy() is 1us */
+
+unsigned cf_head = 0;
+unsigned cf_cyl = 0;
+unsigned cf_spt = 0;
+unsigned cf_sectors = 0;
+static unsigned cf_block_size = 1;
+static void *baddr = 0;
+
+#define DBUF32 ((volatile u32 *)((unsigned long)dev->baddr | ATA_DBUF_OFFSET))
+
+
+static void cf_do_tasklet(unsigned long dev_l);
+
+
+static inline void wareg(u8 val, unsigned reg, struct cf_mips_dev* dev)
+{
+ writeb(val, dev->baddr + ATA_REG_OFFSET + reg);
+}
+
+static inline u8 rareg(unsigned reg, struct cf_mips_dev* dev)
+{
+ return readb(dev->baddr + ATA_REG_OFFSET + reg);
+}
+
+static inline int cfrdy(struct cf_mips_dev *dev)
+{
+ return gpio_get_value(dev->pin);
+}
+
+static inline void prepare_cf_irq(struct cf_mips_dev *dev)
+{
+ rb500_gpio_set_int_level(1, dev->pin); /* interrupt on cf ready (not busy) */
+ rb500_gpio_set_int_status(0, dev->pin); /* clear interrupt status */
+}
+
+static inline int cf_present(struct cf_mips_dev* dev)
+{
+ /* TODO: read and configure CIS into memory mapped mode
+ * TODO: parse CISTPL_CONFIG on CF+ cards to get base address (0x200)
+ * TODO: maybe adjust power saving setting for Hitachi Microdrive
+ */
+ int i;
+
+ /* setup CFRDY GPIO as input */
+ rb500_gpio_set_func(dev->pin, 0);
+ gpio_direction_input(dev->pin);
+
+ for (i = 0; i < 0x10; ++i) {
+ if (rareg(i,dev) != 0xff)
+ return 1;
+ }
+ return 0;
+}
+
+static inline int is_busy(struct cf_mips_dev *dev)
+{
+ return !cfrdy(dev);
+}
+
+static int wait_not_busy(int to_us, int wait_for_busy,struct cf_mips_dev *dev)
+{
+ int us_passed = 0;
+ if (wait_for_busy && !is_busy(dev)) {
+ /* busy must appear within 400ns,
+ * but it may dissapear before we see it
+ * => must not wait for busy in a loop
+ */
+ ndelay(400);
+ }
+
+ do {
+ if (us_passed)
+ udelay(1); /* never reached in async mode */
+ if (!is_busy(dev)) {
+ if (us_passed > 1 * SECS) {
+ printk(KERN_WARNING "cf-mips: not busy ok (after %dus)"
+ ", status 0x%02x\n", us_passed, (unsigned) rareg(ATA_REG_ST,dev));
+ }
+ return CF_TRANS_OK;
+ }
+ if (us_passed == 1 * SECS) {
+ printk(KERN_WARNING "cf-mips: wait not busy %dus..\n", to_us);
+ }
+ if (dev->async_mode) {
+ dev->to_timer.expires = jiffies + (to_us * HZ / SECS);
+ dev->irq_enable_time = jiffies;
+ prepare_cf_irq(dev);
+ if (is_busy(dev)) {
+ add_timer(&dev->to_timer);
+ enable_irq(dev->irq);
+ return CF_TRANS_IN_PROGRESS;
+ }
+ continue;
+ }
+ ++us_passed;
+ } while (us_passed < to_us);
+
+ printk(KERN_ERR "cf-mips: wait not busy timeout (%dus)"
+ ", status 0x%02x, state %d\n",
+ to_us, (unsigned) rareg(ATA_REG_ST,dev), dev->tstate);
+ return CF_TRANS_FAILED;
+}
+
+static irqreturn_t cf_irq_handler(int irq, void *dev_id)
+{
+ /* While tasklet has not disabled irq, irq will be retried all the time
+ * because of ILEVEL matching GPIO pin status => deadlock.
+ * To avoid this, we change ILEVEL to 0.
+ */
+ struct cf_mips_dev *dev=dev_id;
+
+ rb500_gpio_set_int_level(0, dev->pin);
+ rb500_gpio_set_int_status(0, dev->pin);
+
+ del_timer(&dev->to_timer);
+ tasklet_schedule(&dev->tasklet);
+ return IRQ_HANDLED;
+}
+
+static int do_reset(struct cf_mips_dev *dev)
+{
+ printk(KERN_INFO "cf-mips: resetting..\n");
+
+ wareg(ATA_REG_DC_SRST, ATA_REG_DC,dev);
+ udelay(1); /* FIXME: how long should we wait here? */
+ wareg(0, ATA_REG_DC,dev);
+
+ return wait_not_busy(30 * SECS, 1,dev);
+}
+
+static int set_multiple(struct cf_mips_dev *dev)
+{
+ if (dev->block_size <= 1)
+ return CF_TRANS_OK;
+
+ wareg(dev->block_size, ATA_REG_SC,dev);
+ wareg(ATA_REG_DH_BASE | ATA_REG_DH_LBA, ATA_REG_DH,dev);
+ wareg(ATA_CMD_SET_MULTIPLE, ATA_REG_CMD,dev);
+
+ return wait_not_busy(10 * SECS, 1,dev);
+}
+
+static int set_cmd(struct cf_mips_dev *dev)
+{
+ //DEBUGP(KERN_INFO "cf-mips: ata cmd 0x%02x\n", dev->tcmd);
+ // sector_count should be <=24 bits..
+ BUG_ON(dev->tsect_start>=0x10000000);
+ // This way, it addresses 2^24 * 512 = 128G
+
+ if (dev->tsector_count) {
+ wareg(dev->tsector_count & 0xff, ATA_REG_SC,dev);
+ wareg(dev->tsect_start & 0xff, ATA_REG_SN,dev);
+ wareg((dev->tsect_start >> 8) & 0xff, ATA_REG_CL,dev);
+ wareg((dev->tsect_start >> 16) & 0xff, ATA_REG_CH,dev);
+ }
+ wareg(((dev->tsect_start >> 24) & 0x0f) | ATA_REG_DH_BASE | ATA_REG_DH_LBA,
+ ATA_REG_DH,dev); /* select drive on all commands */
+ wareg(dev->tcmd, ATA_REG_CMD,dev);
+ return wait_not_busy(10 * SECS, 1,dev);
+}
+
+static int do_trans(struct cf_mips_dev *dev)
+{
+ int res;
+ unsigned st;
+ int transfered;
+
+ //printk("do_trans: %d sectors left\n",dev->tsectors_left);
+ while (dev->tsectors_left) {
+ transfered = 0;
+
+ st = rareg(ATA_REG_ST,dev);
+ if (!(st & ATA_REG_ST_DRQ)) {
+ printk(KERN_ERR "cf-mips: do_trans without DRQ (status 0x%x)!\n", st);
+ if (st & ATA_REG_ST_ERR) {
+ int errId = rareg(ATA_REG_ERR,dev);
+ printk(KERN_ERR "cf-mips: %s error, status 0x%x, errid 0x%x\n",
+ (dev->tread ? "read" : "write"), st, errId);
+ }
+ return CF_TRANS_FAILED;
+ }
+ do { /* Fill/read the buffer one block */
+ u32 *qbuf, *qend;
+ qbuf = (u32 *)dev->tbuf;
+ qend = qbuf + CF_SECT_SIZE / sizeof(u32);
+ if (dev->tread) {
+ while (qbuf!=qend)
+ put_unaligned(*DBUF32,qbuf++);
+ //*(qbuf++) = *DBUF32;
+ }
+ else {
+ while(qbuf!=qend)
+ *DBUF32 = get_unaligned(qbuf++);
+ }
+
+ dev->tsectors_left--;
+ dev->tbuf += CF_SECT_SIZE;
+ dev->tbuf_size -= CF_SECT_SIZE;
+ transfered++;
+ } while (transfered != dev->block_size && dev->tsectors_left > 0);
+
+ res = wait_not_busy(10 * SECS, 1,dev);
+ if (res != CF_TRANS_OK)
+ return res;
+ };
+
+ st = rareg(ATA_REG_ST,dev);
+ if (st & (ATA_REG_ST_DRQ | ATA_REG_ST_DWF | ATA_REG_ST_ERR)) {
+ if (st & ATA_REG_ST_DRQ) {
+ printk(KERN_ERR "cf-mips: DRQ after all %d sectors are %s"
+ ", status 0x%x\n", dev->tsector_count, (dev->tread ? "read" : "written"), st);
+ } else if (st & ATA_REG_ST_DWF) {
+ printk(KERN_ERR "cf-mips: write fault, status 0x%x\n", st);
+ } else {
+ int errId = rareg(ATA_REG_ERR,dev);
+ printk(KERN_ERR "cf-mips: %s error, status 0x%x, errid 0x%x\n",
+ (dev->tread ? "read" : "write"), st, errId);
+ }
+ return CF_TRANS_FAILED;
+ }
+ return CF_TRANS_OK;
+}
+
+static int cf_do_state(struct cf_mips_dev *dev)
+{
+ int res;
+ switch (dev->tstate) { /* fall through everywhere */
+ case TS_IDLE:
+ dev->tstate = TS_READY;
+ if (is_busy(dev)) {
+ dev->tstate = TS_AFTER_RESET;
+ res = do_reset(dev);
+ if (res != CF_TRANS_OK)
+ break;
+ }
+ case TS_AFTER_RESET:
+ if (dev->tstate == TS_AFTER_RESET) {
+ dev->tstate = TS_READY;
+ res = set_multiple(dev);
+ if (res != CF_TRANS_OK)
+ break;
+ }
+ case TS_READY:
+ dev->tstate = TS_CMD;
+ res = set_cmd(dev);
+ if (res != CF_TRANS_OK)
+ break;;
+ case TS_CMD:
+ dev->tstate = TS_TRANS;
+ case TS_TRANS:
+ res = do_trans(dev);
+ break;
+ default:
+ printk(KERN_ERR "cf-mips: BUG: unknown tstate %d\n", dev->tstate);
+ return CF_TRANS_FAILED;
+ }
+ if (res != CF_TRANS_IN_PROGRESS)
+ dev->tstate = TS_IDLE;
+ return res;
+}
+
+static void cf_do_tasklet(unsigned long dev_l)
+{
+ struct cf_mips_dev* dev=(struct cf_mips_dev*) dev_l;
+ int res;
+
+ disable_irq(dev->irq);
+
+ if (dev->tstate == TS_IDLE)
+ return; /* can happen when irq is first registered */
+
+#if 0
+ DEBUGP(KERN_WARNING "cf-mips: not busy ok (tasklet) status 0x%02x\n",
+ (unsigned) rareg(ATA_REG_ST,dev));
+#endif
+
+ res = cf_do_state(dev);
+ if (res == CF_TRANS_IN_PROGRESS)
+ return;
+ cf_async_trans_done(dev,res);
+}
+
+static void cf_async_timeout(unsigned long dev_l)
+{
+ struct cf_mips_dev* dev=(struct cf_mips_dev*) dev_l;
+ disable_irq(dev->irq);
+ /* Perhaps send abort to the device? */
+ printk(KERN_ERR "cf-mips: wait not busy timeout (%lus)"
+ ", status 0x%02x, state %d\n",
+ jiffies - dev->irq_enable_time, (unsigned) rareg(ATA_REG_ST,dev), dev->tstate);
+ dev->tstate = TS_IDLE;
+ cf_async_trans_done(dev,CF_TRANS_FAILED);
+}
+
+int cf_do_transfer(struct cf_mips_dev* dev,sector_t sector, unsigned long nsect,
+ char* buffer, int is_write)
+{
+ BUG_ON(dev->tstate!=TS_IDLE);
+ if (nsect > ATA_MAX_SECT_PER_CMD) {
+ printk(KERN_WARNING "cf-mips: sector count %lu out of range\n",nsect);
+ return CF_TRANS_FAILED;
+ }
+ if (sector + nsect > dev->sectors) {
+ printk(KERN_WARNING "cf-mips: sector %lu out of range\n",sector);
+ return CF_TRANS_FAILED;
+ }
+ dev->tbuf = buffer;
+ dev->tbuf_size = nsect*512;
+ dev->tsect_start = sector;
+ dev->tsector_count = nsect;
+ dev->tsectors_left = dev->tsector_count;
+ dev->tread = (is_write)?0:1;
+
+ dev->tcmd = (dev->block_size == 1 ?
+ (is_write ? ATA_CMD_WRITE_SECTORS : ATA_CMD_READ_SECTORS) :
+ (is_write ? ATA_CMD_WRITE_MULTIPLE : ATA_CMD_READ_MULTIPLE));
+
+ return cf_do_state(dev);
+}
+
+static int do_identify(struct cf_mips_dev *dev)
+{
+ u16 sbuf[CF_SECT_SIZE >> 1];
+ int res;
+ char tstr[17]; //serial
+ char tmp;
+ int i;
+ BUG_ON(dev->tstate!=TS_IDLE);
+ dev->tbuf = (char *) sbuf;
+ dev->tbuf_size = CF_SECT_SIZE;
+ dev->tsect_start = 0;
+ dev->tsector_count = 0;
+ dev->tsectors_left = 1;
+ dev->tread = 1;
+ dev->tcmd = ATA_CMD_IDENTIFY_DRIVE;
+
+ DEBUGP(KERN_INFO "cf-mips: identify drive..\n");
+ res = cf_do_state(dev);
+ if (res == CF_TRANS_IN_PROGRESS) {
+ printk(KERN_ERR "cf-mips: BUG: async identify cmd\n");
+ return CF_TRANS_FAILED;
+ }
+ if (res != CF_TRANS_OK)
+ return 0;
+
+ dev->head = sbuf[3];
+ dev->cyl = sbuf[1];
+ dev->spt = sbuf[6];
+ dev->sectors = ((unsigned long) sbuf[7] << 16) | sbuf[8];
+ dev->dtype=sbuf[0];
+ memcpy(tstr, &sbuf[12], 16);
+ tstr[16] = '\0';
+
+ /* Byte-swap the serial number */
+ for (i = 0; i<8; i++) {
+ tmp = tstr[i * 2];
+ tstr[i * 2] = tstr[i * 2 +1];
+ tstr[i * 2 + 1] = tmp;
+ }
+
+ printk(KERN_INFO "cf-mips: %s detected, C/H/S=%d/%d/%d sectors=%u (%uMB) Serial=%s\n",
+ (sbuf[0] == 0x848A ? "CF card" : "ATA drive"), dev->cyl, dev->head,
+ dev->spt, dev->sectors, dev->sectors >> 11, tstr);
+ return 1;
+}
+
+static void init_multiple(struct cf_mips_dev * dev)
+{
+ int res;
+ DEBUGP(KERN_INFO "cf-mips: detecting block size\n");
+
+ dev->block_size = 128; /* max block size = 128 sectors (64KB) */
+ do {
+ wareg(dev->block_size, ATA_REG_SC,dev);
+ wareg(ATA_REG_DH_BASE | ATA_REG_DH_LBA, ATA_REG_DH,dev);
+ wareg(ATA_CMD_SET_MULTIPLE, ATA_REG_CMD,dev);
+
+ res = wait_not_busy(10 * SECS, 1,dev);
+ if (res != CF_TRANS_OK) {
+ printk(KERN_ERR "cf-mips: failed to detect block size: busy!\n");
+ dev->block_size = 1;
+ return;
+ }
+ if ((rareg(ATA_REG_ST,dev) & ATA_REG_ST_ERR) == 0)
+ break;
+ dev->block_size /= 2;
+ } while (dev->block_size > 1);
+
+ printk(KERN_INFO "cf-mips: multiple sectors = %d\n", dev->block_size);
+}
+
+int cf_init(struct cf_mips_dev *dev)
+{
+ tasklet_init(&dev->tasklet,cf_do_tasklet,(unsigned long)dev);
+ dev->baddr = ioremap_nocache((unsigned long)dev->base, CFDEV_BUF_SIZE);
+ if (!dev->baddr) {
+ printk(KERN_ERR "cf-mips: cf_init: ioremap for (%lx,%x) failed\n",
+ (unsigned long) dev->base, CFDEV_BUF_SIZE);
+ return -EBUSY;
+ }
+
+ if (!cf_present(dev)) {
+ printk(KERN_WARNING "cf-mips: cf card not present\n");
+ iounmap(dev->baddr);
+ return -ENODEV;
+ }
+
+ if (do_reset(dev) != CF_TRANS_OK) {
+ printk(KERN_ERR "cf-mips: cf reset failed\n");
+ iounmap(dev->baddr);
+ return -EBUSY;
+ }
+
+ if (!do_identify(dev)) {
+ printk(KERN_ERR "cf-mips: cf identify failed\n");
+ iounmap(dev->baddr);
+ return -EBUSY;
+ }
+
+/* set_apm_level(ATA_APM_WITH_STANDBY); */
+ init_multiple(dev);
+
+ init_timer(&dev->to_timer);
+ dev->to_timer.function = cf_async_timeout;
+ dev->to_timer.data = (unsigned long)dev;
+
+ prepare_cf_irq(dev);
+ if (request_irq(dev->irq, cf_irq_handler, 0, "CF Mips", dev)) {
+ printk(KERN_ERR "cf-mips: failed to get irq\n");
+ iounmap(dev->baddr);
+ return -EBUSY;
+ }
+ /* Disable below would be odd, because request will enable, and the tasklet
+ will disable it itself */
+ //disable_irq(dev->irq);
+
+ dev->async_mode = 1;
+
+ return 0;
+}
+
+void cf_cleanup(struct cf_mips_dev *dev)
+{
+ iounmap(dev->baddr);
+ free_irq(dev->irq, NULL);
+#if REQUEST_MEM_REGION
+ release_mem_region((unsigned long)dev->base, CFDEV_BUF_SIZE);
+#endif
+}
+
+
+/*eof*/
--- /dev/null
+/* CF-mips driver
+ This is a block driver for the direct (mmaped) interface to the CF-slot,
+ found in Routerboard.com's RB532 board
+ See SDK provided from routerboard.com.
+
+ Module adapted By P.Christeas <p_christeas@yahoo.com>, 2005-6.
+ Cleaned up and adapted to platform_device by Felix Fietkau <nbd@openwrt.org>
+
+ This work is redistributed under the terms of the GNU General Public License.
+*/
+
+#ifndef __CFMIPS_ATA_H__
+#define __CFMIPS_ATA_H__
+
+#include <linux/interrupt.h>
+
+#define CFG_DC_DEV1 (void*)0xb8010010
+#define CFG_DC_DEVBASE 0x0
+#define CFG_DC_DEVMASK 0x4
+#define CFG_DC_DEVC 0x8
+#define CFG_DC_DEVTC 0xC
+
+#define CFDEV_BUF_SIZE 0x1000
+#define ATA_CIS_OFFSET 0x200
+#define ATA_REG_OFFSET 0x800
+#define ATA_DBUF_OFFSET 0xC00
+
+#define ATA_REG_FEAT 0x1
+#define ATA_REG_SC 0x2
+#define ATA_REG_SN 0x3
+#define ATA_REG_CL 0x4
+#define ATA_REG_CH 0x5
+#define ATA_REG_DH 0x6
+#define ATA_REG_DH_BASE 0xa0
+#define ATA_REG_DH_LBA 0x40
+#define ATA_REG_DH_DRV 0x10
+#define ATA_REG_CMD 0x7
+#define ATA_REG_ST 0x7
+#define ATA_REG_ST_BUSY 0x80
+#define ATA_REG_ST_RDY 0x40
+#define ATA_REG_ST_DWF 0x20
+#define ATA_REG_ST_DSC 0x10
+#define ATA_REG_ST_DRQ 0x08
+#define ATA_REG_ST_CORR 0x04
+#define ATA_REG_ST_ERR 0x01
+#define ATA_REG_ERR 0xd
+#define ATA_REG_DC 0xe
+#define ATA_REG_DC_IEN 0x02
+#define ATA_REG_DC_SRST 0x04
+
+#define ATA_CMD_READ_SECTORS 0x20
+#define ATA_CMD_WRITE_SECTORS 0x30
+#define ATA_CMD_EXEC_DRIVE_DIAG 0x90
+#define ATA_CMD_READ_MULTIPLE 0xC4
+#define ATA_CMD_WRITE_MULTIPLE 0xC5
+#define ATA_CMD_SET_MULTIPLE 0xC6
+#define ATA_CMD_IDENTIFY_DRIVE 0xEC
+#define ATA_CMD_SET_FEATURES 0xEF
+
+#define ATA_FEATURE_ENABLE_APM 0x05
+#define ATA_FEATURE_DISABLE_APM 0x85
+#define ATA_APM_DISABLED 0x00
+#define ATA_APM_MIN_POWER 0x01
+#define ATA_APM_WITH_STANDBY 0x7f
+#define ATA_APM_WITHOUT_STANDBY 0x80
+#define ATA_APM_MAX_PERFORMANCE 0xfe
+
+#define CF_SECT_SIZE 0x200
+/* That is the ratio CF_SECT_SIZE/512 (the kernel sector size) */
+#define CF_KERNEL_MUL 1
+#define ATA_MAX_SECT_PER_CMD 0x100
+
+#define CF_TRANS_FAILED 0
+#define CF_TRANS_OK 1
+#define CF_TRANS_IN_PROGRESS 2
+
+
+enum trans_state {
+ TS_IDLE = 0,
+ TS_AFTER_RESET,
+ TS_READY,
+ TS_CMD,
+ TS_TRANS
+};
+
+//
+// #if DEBUG
+// static unsigned long busy_time;
+// #endif
+
+/** Struct to hold the cfdev
+Actually, all the data here only has one instance. However, for
+reasons of programming conformity, it is passed around as a pointer
+*/
+struct cf_mips_dev {
+ void *base; /* base address for I/O */
+ void *baddr; /* remapped address */
+
+ int pin; /* gpio pin */
+ int irq; /* gpio irq */
+
+ unsigned head;
+ unsigned cyl;
+ unsigned spt;
+ unsigned sectors;
+
+ unsigned short block_size;
+ unsigned dtype ; // ATA or CF
+ struct request_queue *queue;
+ struct gendisk *gd;
+
+ /* Transaction state */
+ enum trans_state tstate;
+ char *tbuf;
+ unsigned long tbuf_size;
+ sector_t tsect_start;
+ unsigned tsector_count;
+ unsigned tsectors_left;
+ int tread;
+ unsigned tcmd;
+ int async_mode;
+ unsigned long irq_enable_time;
+
+ struct request *active_req; /* A request is being carried out. Is that different from tstate? */
+ int users;
+ struct timer_list to_timer;
+ struct tasklet_struct tasklet;
+
+ /** This lock ensures that the requests to this device are all done
+ atomically. Transfers can run in parallel, requests are all queued
+ one-by-one */
+ spinlock_t lock;
+};
+
+int cf_do_transfer(struct cf_mips_dev* dev,sector_t sector, unsigned long nsect,
+ char* buffer, int is_write);
+int cf_init(struct cf_mips_dev* dev);
+void cf_cleanup(struct cf_mips_dev* dev);
+
+void cf_async_trans_done(struct cf_mips_dev* dev, int result);
+// void *cf_get_next_buf(unsigned long *buf_size);
+
+#endif
--- /dev/null
+/* CF-mips driver
+ This is a block driver for the direct (mmaped) interface to the CF-slot,
+ found in Routerboard.com's RB532 board
+ See SDK provided from routerboard.com.
+
+ Module adapted By P.Christeas <p_christeas@yahoo.com>, 2005-6.
+ Cleaned up and adapted to platform_device by Felix Fietkau <nbd@openwrt.org>
+
+ This work is redistributed under the terms of the GNU General Public License.
+*/
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/time.h>
+#include <linux/wait.h>
+#include <linux/fs.h>
+#include <linux/genhd.h>
+#include <linux/blkdev.h>
+#include <linux/blkpg.h>
+#include <linux/hdreg.h>
+#include <linux/platform_device.h>
+
+#include <asm/uaccess.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+#include <asm/rc32434/rb.h>
+
+#ifdef DEBUG
+#define DEBUGP printk
+#define DLEVEL 1
+#else
+#define DEBUGP(format, args...)
+#define DLEVEL 0
+#endif
+
+#define CF_MIPS_MAJOR 13
+#define MAJOR_NR CF_MIPS_MAJOR
+#define CF_MAX_PART 16 /* max 15 partitions */
+
+#include "ata.h"
+
+//extern struct block_device_operations cf_bdops;
+
+// static struct hd_struct cf_parts[CF_MAX_PART];
+// static int cf_part_sizes[CF_MAX_PART];
+// static int cf_hsect_sizes[CF_MAX_PART];
+// static int cf_max_sectors[CF_MAX_PART];
+// static int cf_blksize_sizes[CF_MAX_PART];
+
+// static spinlock_t lock = SPIN_LOCK_UNLOCKED;
+
+// volatile int cf_busy = 0;
+
+static struct request *active_req = NULL;
+
+static int cf_open (struct inode *, struct file *);
+static int cf_release (struct inode *, struct file *);
+static int cf_ioctl (struct inode *, struct file *, unsigned, unsigned long);
+
+static void cf_request(request_queue_t * q);
+static int cf_transfer(const struct request *req);
+
+/*long (*unlocked_ioctl) (struct file *, unsigned, unsigned long);
+long (*compat_ioctl) (struct file *, unsigned, unsigned long);*/
+// int (*direct_access) (struct block_device *, sector_t, unsigned long *);
+// int (*media_changed) (struct gendisk *);
+// int (*revalidate_disk) (struct gendisk *);
+
+static struct block_device_operations cf_bdops = {
+ .owner = THIS_MODULE,
+ .open = cf_open,
+ .release = cf_release,
+ .ioctl = cf_ioctl,
+ .media_changed = NULL,
+ .unlocked_ioctl = NULL,
+ .revalidate_disk = NULL,
+ .compat_ioctl = NULL,
+ .direct_access = NULL
+};
+
+
+int cf_mips_probe(struct platform_device *pdev)
+{
+ struct gendisk* cf_gendisk=NULL;
+ struct cf_device *cdev = (struct cf_device *) pdev->dev.platform_data;
+ struct cf_mips_dev *dev;
+ struct resource *r;
+ int reg_result;
+
+ reg_result = register_blkdev(MAJOR_NR, "cf-mips");
+ if (reg_result < 0) {
+ printk(KERN_WARNING "cf-mips: can't get major %d\n", MAJOR_NR);
+ return reg_result;
+ }
+
+ dev = (struct cf_mips_dev *)kmalloc(sizeof(struct cf_mips_dev),GFP_KERNEL);
+ if (!dev)
+ goto out_err;
+ memset(dev, 0, sizeof(struct cf_mips_dev));
+ cdev->dev = dev;
+
+ dev->pin = cdev->gpio_pin;
+ dev->irq = platform_get_irq_byname(pdev, "cf_irq");
+ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cf_membase");
+ dev->base = (void *) r->start;
+
+ if (cf_init(dev)) goto out_err;
+ printk("init done");
+
+ spin_lock_init(&dev->lock);
+ dev->queue = blk_init_queue(cf_request,&dev->lock);
+ if (!dev->queue){
+ printk(KERN_ERR "cf-mips: no mem for queue\n");
+ goto out_err;
+ }
+ blk_queue_max_sectors(dev->queue,ATA_MAX_SECT_PER_CMD);
+
+ /* For memory devices, it is always better to avoid crossing segments
+ inside the same request. */
+/* if (dev->dtype==0x848A){
+ printk(KERN_INFO "Setting boundary for cf to 0x%x",(dev->block_size*512)-1);
+ blk_queue_segment_boundary(dev->queue, (dev->block_size*512)-1);
+ }*/
+
+ dev->gd = alloc_disk(CF_MAX_PART);
+ cf_gendisk = dev->gd;
+ cdev->gd = dev->gd;
+ if (!cf_gendisk) goto out_err; /* Last of these goto's */
+
+ cf_gendisk->major = MAJOR_NR;
+ cf_gendisk->first_minor = 0;
+ cf_gendisk->queue=dev->queue;
+ BUG_ON(cf_gendisk->minors != CF_MAX_PART);
+ strcpy(cf_gendisk->disk_name,"cfa");
+ cf_gendisk->fops = &cf_bdops;
+ cf_gendisk->flags = 0 ; /* is not yet GENHD_FL_REMOVABLE */
+ cf_gendisk->private_data=dev;
+
+ set_capacity(cf_gendisk,dev->sectors * CF_KERNEL_MUL);
+
+ /* Let the disk go live */
+ add_disk(cf_gendisk);
+#if 0
+ result = cf_init();
+
+ /* default cfg for all partitions */
+ memset(cf_parts, 0, sizeof (cf_parts[0]) * CF_MAX_PART);
+ memset(cf_part_sizes, 0, sizeof (cf_part_sizes[0]) * CF_MAX_PART);
+ for (i = 0; i < CF_MAX_PART; ++i) {
+ cf_hsect_sizes[i] = CF_SECT_SIZE;
+ cf_max_sectors[i] = ATA_MAX_SECT_PER_CMD;
+ cf_blksize_sizes[i] = BLOCK_SIZE;
+ }
+
+ /* setup info for whole disk (partition 0) */
+ cf_part_sizes[0] = cf_sectors / 2;
+ cf_parts[0].nr_sects = cf_sectors;
+
+ blk_size[MAJOR_NR] = cf_part_sizes;
+ blksize_size[MAJOR_NR] = cf_blksize_sizes;
+ max_sectors[MAJOR_NR] = cf_max_sectors;
+ hardsect_size[MAJOR_NR] = cf_hsect_sizes;
+ read_ahead[MAJOR_NR] = 8; /* (4kB) */
+
+ blk_init_queue(BLK_DEFAULT_QUEUE(MAJOR_NR), DEVICE_REQUEST);
+
+ add_gendisk(&cf_gendisk);
+#endif
+// printk(KERN_INFO "cf-mips partition check: \n");
+// register_disk(cf_gendisk, MKDEV(MAJOR_NR, 0), CF_MAX_PART,
+// &cf_bdops, dev->sectors);
+ return 0;
+
+out_err:
+ if (dev->queue){
+ blk_cleanup_queue(dev->queue);
+ }
+ if (reg_result) {
+ unregister_blkdev(MAJOR_NR, "cf-mips");
+ return reg_result;
+ }
+ if (dev){
+ cf_cleanup(dev);
+ kfree(dev);
+ }
+ return 1;
+}
+
+static int
+cf_mips_remove(struct platform_device *pdev)
+{
+ struct cf_device *cdev = (struct cf_device *) pdev->dev.platform_data;
+ struct cf_mips_dev *dev = (struct cf_mips_dev *) cdev->dev;
+
+ unregister_blkdev(MAJOR_NR, "cf-mips");
+ blk_cleanup_queue(dev->queue);
+
+ del_gendisk(dev->gd);
+ cf_cleanup(dev);
+ return 0;
+}
+
+
+static struct platform_driver cf_driver = {
+ .driver.name = "rb500-cf",
+ .probe = cf_mips_probe,
+ .remove = cf_mips_remove,
+};
+
+static int __init cf_mips_init(void)
+{
+ printk(KERN_INFO "cf-mips module loaded\n");
+ return platform_driver_register(&cf_driver);
+}
+
+static void cf_mips_cleanup(void)
+{
+ platform_driver_unregister(&cf_driver);
+ printk(KERN_INFO "cf-mips module removed\n");
+}
+
+module_init(cf_mips_init);
+module_exit(cf_mips_cleanup);
+
+MODULE_LICENSE("GPL");
+MODULE_ALIAS_BLOCKDEV_MAJOR(CF_MIPS_MAJOR);
+
+
+static int cf_open(struct inode *inode, struct file *filp)
+{
+ struct cf_mips_dev *dev=inode->i_bdev->bd_disk->private_data;
+ int minor = MINOR(inode->i_rdev);
+
+ if (minor >= CF_MAX_PART)
+ return -ENODEV;
+ //DEBUGP(KERN_INFO "cf-mips module opened, minor %d\n", minor);
+ spin_lock(&dev->lock);
+ dev->users++;
+ spin_unlock(&dev->lock);
+ filp->private_data=dev;
+
+ /* dirty workaround to set CFRDY GPIO as an input when some other
+ program sets it as an output */
+ gpio_set_value(dev->pin, 0);
+ return 0; /* success */
+}
+
+static int cf_release(struct inode *inode, struct file *filp)
+{
+ int minor = MINOR(inode->i_rdev);
+ struct cf_mips_dev *dev=inode->i_bdev->bd_disk->private_data;
+ spin_lock(&dev->lock);
+ dev->users--;
+ spin_unlock(&dev->lock);
+ return 0;
+}
+
+static int cf_ioctl(struct inode *inode, struct file *filp,
+ unsigned int cmd, unsigned long arg)
+{
+ unsigned minor = MINOR(inode->i_rdev);
+ struct cf_mips_dev *dev=inode->i_bdev->bd_disk->private_data;
+
+ DEBUGP(KERN_INFO "cf_ioctl cmd %u\n", cmd);
+ switch (cmd) {
+ case BLKRRPART: /* re-read partition table */
+ if (!capable(CAP_SYS_ADMIN))
+ return -EACCES;
+ printk(KERN_INFO "cf-mips partition check: \n");
+ register_disk(dev->gd);
+ return 0;
+
+ case HDIO_GETGEO:
+ {
+ struct hd_geometry geo;
+ geo.cylinders = dev->cyl;
+ geo.heads = dev->head;
+ geo.sectors = dev->spt;
+ geo.start = (*dev->gd->part)[minor].start_sect;
+ if (copy_to_user((void *) arg, &geo, sizeof (geo)))
+ return -EFAULT;
+ }
+ return 0;
+ }
+
+ return -EINVAL; /* unknown command */
+}
+
+static void cf_request(request_queue_t * q)
+{
+ struct cf_mips_dev* dev;
+
+ struct request * req;
+ int status;
+
+ /* We could have q->queuedata = dev , but haven't yet. */
+ if (active_req)
+ return;
+
+ while ((req=elv_next_request(q))!=NULL){
+ dev=req->rq_disk->private_data;
+ status=cf_transfer(req);
+ if (status==CF_TRANS_IN_PROGRESS){
+ active_req=req;
+ return;
+ }
+ end_request(req,status);
+ }
+}
+
+static int cf_transfer(const struct request *req)
+{
+ struct cf_mips_dev* dev=req->rq_disk->private_data;
+
+ if (!blk_fs_request(req)){
+ if (printk_ratelimit())
+ printk(KERN_WARNING "cf-mips: skipping non-fs request 0x%x\n",req->cmd[0]);
+ return CF_TRANS_FAILED;
+ }
+
+ return cf_do_transfer(dev,req->sector,req->current_nr_sectors,req->buffer,rq_data_dir(req));
+}
+
+void cf_async_trans_done(struct cf_mips_dev * dev,int result)
+{
+ struct request *req;
+
+ spin_lock(&dev->lock);
+ req=active_req;
+ active_req=NULL;
+ end_request(req,result);
+ spin_unlock(&dev->lock);
+
+ spin_lock(&dev->lock);
+ cf_request(dev->queue);
+ spin_unlock(&dev->lock);
+}
+
--- /dev/null
+/*
+ * linux/drivers/leds/leds-rb500.c
+ *
+ * Copyright (C) 2006
+ * Twente Institute for Wireless and Mobile Communications BV
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details (see file GPLv2).
+ *
+ * Author: Tjalling Hattink <tjalling.hattink@ti-wmc.nl>
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+#include <asm/rc32434/rb.h>
+
+static void rb500led_amber_set(struct led_classdev *led_cdev, enum led_brightness value)
+{
+ if (value)
+ changeLatchU5(LO_ULED, 0);
+ else
+ changeLatchU5(0, LO_ULED);
+}
+
+static struct led_classdev rb500_amber_led = {
+ .name = "rb500led:amber",
+ .default_trigger = "ide-disk",
+ .brightness_set = rb500led_amber_set,
+};
+
+static int rb500led_probe(struct platform_device *pdev)
+{
+ int ret;
+
+ changeLatchU5(0, LO_ULED);
+
+ ret = led_classdev_register(&pdev->dev, &rb500_amber_led);
+
+ return ret;
+}
+
+static int rb500led_remove(struct platform_device *pdev)
+{
+ led_classdev_unregister(&rb500_amber_led);
+
+ return 0;
+}
+
+static struct platform_driver rb500led_driver = {
+ .probe = rb500led_probe,
+ .remove = rb500led_remove,
+ .driver = {
+ .name = "rb500-led",
+ },
+};
+
+static int __init rb500led_init(void)
+{
+ return platform_driver_register(&rb500led_driver);
+}
+
+static void __exit rb500led_exit(void)
+{
+ platform_driver_unregister(&rb500led_driver);
+}
+
+module_init(rb500led_init);
+module_exit(rb500led_exit);
+
+MODULE_AUTHOR("tjalling.hattink@ti-wmc.nl");
+MODULE_DESCRIPTION("Mikrotik RB500 LED driver");
+MODULE_LICENSE("GPL");
--- /dev/null
+/**************************************************************************
+ *
+ * BRIEF MODULE DESCRIPTION
+ * Driver for the IDT RC32434 on-chip ethernet controller.
+ *
+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
+ * Copyright 2006 Felix Fietkau <nbd@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ * May 2004 rkt, neb
+ *
+ * Based on the driver developed by B. Maruthanayakam, H. Kou and others.
+ *
+ * Aug 2004 Sadik
+ *
+ * Added NAPI
+ *
+ **************************************************************************
+ */
+
+#include <linux/autoconf.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/moduleparam.h>
+#include <linux/sched.h>
+#include <linux/ctype.h>
+#include <linux/types.h>
+#include <linux/fcntl.h>
+#include <linux/interrupt.h>
+#include <linux/ptrace.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/proc_fs.h>
+#include <linux/in.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/delay.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/errno.h>
+#include <linux/platform_device.h>
+#include <asm/bootinfo.h>
+#include <asm/system.h>
+#include <asm/bitops.h>
+#include <asm/pgtable.h>
+#include <asm/segment.h>
+#include <asm/io.h>
+#include <asm/dma.h>
+
+#include <asm/rc32434/rb.h>
+#include "rc32434_eth.h"
+
+#define DRIVER_VERSION "(mar2904)"
+
+#define DRIVER_NAME "rc32434 Ethernet driver. " DRIVER_VERSION
+
+#define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \
+ ((dev)->dev_addr[1]))
+#define STATION_ADDRESS_LOW(dev) (((dev)->dev_addr[2] << 24) | \
+ ((dev)->dev_addr[3] << 16) | \
+ ((dev)->dev_addr[4] << 8) | \
+ ((dev)->dev_addr[5]))
+
+#define MII_CLOCK 1250000 /* no more than 2.5MHz */
+#define CONFIG_IDT_USE_NAPI 1
+
+
+static inline void rc32434_abort_tx(struct net_device *dev)
+{
+ struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
+ rc32434_abort_dma(dev, lp->tx_dma_regs);
+
+}
+
+static inline void rc32434_abort_rx(struct net_device *dev)
+{
+ struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
+ rc32434_abort_dma(dev, lp->rx_dma_regs);
+
+}
+
+static inline void rc32434_start_tx(struct rc32434_local *lp, volatile DMAD_t td)
+{
+ rc32434_start_dma(lp->tx_dma_regs, CPHYSADDR(td));
+}
+
+static inline void rc32434_start_rx(struct rc32434_local *lp, volatile DMAD_t rd)
+{
+ rc32434_start_dma(lp->rx_dma_regs, CPHYSADDR(rd));
+}
+
+static inline void rc32434_chain_tx(struct rc32434_local *lp, volatile DMAD_t td)
+{
+ rc32434_chain_dma(lp->tx_dma_regs, CPHYSADDR(td));
+}
+
+static inline void rc32434_chain_rx(struct rc32434_local *lp, volatile DMAD_t rd)
+{
+ rc32434_chain_dma(lp->rx_dma_regs, CPHYSADDR(rd));
+}
+
+#ifdef RC32434_PROC_DEBUG
+static int rc32434_read_proc(char *buf, char **start, off_t fpos,
+ int length, int *eof, void *data)
+{
+ struct net_device *dev = (struct net_device *)data;
+ struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
+ int len = 0;
+
+ /* print out header */
+ len += sprintf(buf + len, "\n\tKorina Ethernet Debug\n\n");
+ len += sprintf (buf + len,
+ "DMA halt count = %10d, DMA run count = %10d\n",
+ lp->dma_halt_cnt, lp->dma_run_cnt);
+
+ if (fpos >= len) {
+ *start = buf;
+ *eof = 1;
+ return 0;
+ }
+ *start = buf + fpos;
+
+ if ((len -= fpos) > length)
+ return length;
+ *eof = 1;
+
+ return len;
+
+}
+#endif
+
+
+/*
+ * Restart the RC32434 ethernet controller.
+ */
+static int rc32434_restart(struct net_device *dev)
+{
+ struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
+
+ /*
+ * Disable interrupts
+ */
+ disable_irq(lp->rx_irq);
+ disable_irq(lp->tx_irq);
+#ifdef RC32434_REVISION
+ disable_irq(lp->ovr_irq);
+#endif
+ disable_irq(lp->und_irq);
+
+ /* Mask F E bit in Tx DMA */
+ __raw_writel(__raw_readl(&lp->tx_dma_regs->dmasm) | DMASM_f_m | DMASM_e_m, &lp->tx_dma_regs->dmasm);
+ /* Mask D H E bit in Rx DMA */
+ __raw_writel(__raw_readl(&lp->rx_dma_regs->dmasm) | DMASM_d_m | DMASM_h_m | DMASM_e_m, &lp->rx_dma_regs->dmasm);
+
+ rc32434_init(dev);
+ rc32434_multicast_list(dev);
+
+ enable_irq(lp->und_irq);
+#ifdef RC32434_REVISION
+ enable_irq(lp->ovr_irq);
+#endif
+ enable_irq(lp->tx_irq);
+ enable_irq(lp->rx_irq);
+
+ return 0;
+}
+
+static int rc32434_probe(struct platform_device *pdev)
+{
+ struct korina_device *bif = (struct korina_device *) pdev->dev.platform_data;
+ struct rc32434_local *lp = NULL;
+ struct net_device *dev = NULL;
+ struct resource *r;
+ int i, retval,err;
+
+ dev = alloc_etherdev(sizeof(struct rc32434_local));
+ if(!dev) {
+ ERR("Korina_eth: alloc_etherdev failed\n");
+ return -1;
+ }
+
+ platform_set_drvdata(pdev, dev);
+ SET_NETDEV_DEV(dev, &pdev->dev);
+ bif->dev = dev;
+
+ memcpy(dev->dev_addr, bif->mac, 6);
+
+ /* Initialize the device structure. */
+ if (dev->priv == NULL) {
+ lp = (struct rc32434_local *)kmalloc(sizeof(*lp), GFP_KERNEL);
+ memset(lp, 0, sizeof(struct rc32434_local));
+ }
+ else {
+ lp = (struct rc32434_local *)dev->priv;
+ }
+
+ lp->rx_irq = platform_get_irq_byname(pdev, "korina_rx");
+ lp->tx_irq = platform_get_irq_byname(pdev, "korina_tx");
+ lp->ovr_irq = platform_get_irq_byname(pdev, "korina_ovr");
+ lp->und_irq = platform_get_irq_byname(pdev, "korina_und");
+
+ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_regs");
+ dev->base_addr = r->start;
+ lp->eth_regs = ioremap_nocache(r->start, r->end - r->start);
+ if (!lp->eth_regs) {
+ ERR("Can't remap eth registers\n");
+ retval = -ENXIO;
+ goto probe_err_out;
+ }
+
+ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_dma_rx");
+ lp->rx_dma_regs = ioremap_nocache(r->start, r->end - r->start);
+ if (!lp->rx_dma_regs) {
+ ERR("Can't remap Rx DMA registers\n");
+ retval = -ENXIO;
+ goto probe_err_out;
+ }
+
+ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_dma_tx");
+ lp->tx_dma_regs = ioremap_nocache(r->start, r->end - r->start);
+ if (!lp->tx_dma_regs) {
+ ERR("Can't remap Tx DMA registers\n");
+ retval = -ENXIO;
+ goto probe_err_out;
+ }
+
+#ifdef RC32434_PROC_DEBUG
+ lp->ps = create_proc_read_entry (bif->name, 0, proc_net,
+ rc32434_read_proc, dev);
+#endif
+
+ lp->td_ring = (DMAD_t)kmalloc(TD_RING_SIZE + RD_RING_SIZE, GFP_KERNEL);
+ if (!lp->td_ring) {
+ ERR("Can't allocate descriptors\n");
+ retval = -ENOMEM;
+ goto probe_err_out;
+ }
+
+ dma_cache_inv((unsigned long)(lp->td_ring), TD_RING_SIZE + RD_RING_SIZE);
+
+ /* now convert TD_RING pointer to KSEG1 */
+ lp->td_ring = (DMAD_t )KSEG1ADDR(lp->td_ring);
+ lp->rd_ring = &lp->td_ring[RC32434_NUM_TDS];
+
+
+ spin_lock_init(&lp->lock);
+
+ /* just use the rx dma irq */
+ dev->irq = lp->rx_irq;
+
+ dev->priv = lp;
+ lp->dev = dev;
+
+ dev->open = rc32434_open;
+ dev->stop = rc32434_close;
+ dev->hard_start_xmit = rc32434_send_packet;
+ dev->get_stats = rc32434_get_stats;
+ dev->set_multicast_list = &rc32434_multicast_list;
+ dev->tx_timeout = rc32434_tx_timeout;
+ dev->watchdog_timeo = RC32434_TX_TIMEOUT;
+
+ netif_napi_add(dev, &lp->napi, rc32434_poll, 64);
+ lp->tx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
+ tasklet_init(lp->tx_tasklet, rc32434_tx_tasklet, (unsigned long)dev);
+
+ if ((err = register_netdev(dev))) {
+ printk(KERN_ERR "rc32434 ethernet. Cannot register net device %d\n", err);
+ free_netdev(dev);
+ retval = -EINVAL;
+ goto probe_err_out;
+ }
+
+ INFO("Rx IRQ %d, Tx IRQ %d, ", lp->rx_irq, lp->tx_irq);
+ for (i = 0; i < 6; i++) {
+ printk("%2.2x", dev->dev_addr[i]);
+ if (i<5)
+ printk(":");
+ }
+ printk("\n");
+
+ return 0;
+
+ probe_err_out:
+ rc32434_cleanup_module();
+ ERR(" failed. Returns %d\n", retval);
+ return retval;
+
+}
+
+static int rc32434_remove(struct platform_device *pdev)
+{
+ struct korina_device *bif = (struct korina_device *) pdev->dev.platform_data;
+
+ if (bif->dev != NULL) {
+ struct rc32434_local *lp = (struct rc32434_local *)bif->dev->priv;
+ if (lp != NULL) {
+ if (lp->eth_regs)
+ iounmap((void*)lp->eth_regs);
+ if (lp->rx_dma_regs)
+ iounmap((void*)lp->rx_dma_regs);
+ if (lp->tx_dma_regs)
+ iounmap((void*)lp->tx_dma_regs);
+ if (lp->td_ring)
+ kfree((void*)KSEG0ADDR(lp->td_ring));
+
+#ifdef RC32434_PROC_DEBUG
+ if (lp->ps) {
+ remove_proc_entry(bif->name, proc_net);
+ }
+#endif
+ kfree(lp);
+ }
+
+ platform_set_drvdata(pdev, NULL);
+ unregister_netdev(bif->dev);
+ free_netdev(bif->dev);
+ kfree(bif->dev);
+ }
+ return 0;
+}
+
+
+static int rc32434_open(struct net_device *dev)
+{
+ struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
+
+ /* Initialize */
+ if (rc32434_init(dev)) {
+ ERR("Error: cannot open the Ethernet device\n");
+ return -EAGAIN;
+ }
+
+ /* Install the interrupt handler that handles the Done Finished Ovr and Und Events */
+ if (request_irq(lp->rx_irq, &rc32434_rx_dma_interrupt,
+ IRQF_SHARED | IRQF_DISABLED,
+ "Korina ethernet Rx", dev)) {
+ ERR(": unable to get Rx DMA IRQ %d\n",
+ lp->rx_irq);
+ return -EAGAIN;
+ }
+ if (request_irq(lp->tx_irq, &rc32434_tx_dma_interrupt,
+ IRQF_SHARED | IRQF_DISABLED,
+ "Korina ethernet Tx", dev)) {
+ ERR(": unable to get Tx DMA IRQ %d\n",
+ lp->tx_irq);
+ free_irq(lp->rx_irq, dev);
+ return -EAGAIN;
+ }
+
+#ifdef RC32434_REVISION
+ /* Install handler for overrun error. */
+ if (request_irq(lp->ovr_irq, &rc32434_ovr_interrupt,
+ IRQF_SHARED | IRQF_DISABLED,
+ "Ethernet Overflow", dev)) {
+ ERR(": unable to get OVR IRQ %d\n",
+ lp->ovr_irq);
+ free_irq(lp->rx_irq, dev);
+ free_irq(lp->tx_irq, dev);
+ return -EAGAIN;
+ }
+#endif
+
+ /* Install handler for underflow error. */
+ if (request_irq(lp->und_irq, &rc32434_und_interrupt,
+ IRQF_SHARED | IRQF_DISABLED,
+ "Ethernet Underflow", dev)) {
+ ERR(": unable to get UND IRQ %d\n",
+ lp->und_irq);
+ free_irq(lp->rx_irq, dev);
+ free_irq(lp->tx_irq, dev);
+#ifdef RC32434_REVISION
+ free_irq(lp->ovr_irq, dev);
+#endif
+ return -EAGAIN;
+ }
+
+
+ return 0;
+}
+
+
+
+
+static int rc32434_close(struct net_device *dev)
+{
+ struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
+ u32 tmp;
+
+ /* Disable interrupts */
+ disable_irq(lp->rx_irq);
+ disable_irq(lp->tx_irq);
+#ifdef RC32434_REVISION
+ disable_irq(lp->ovr_irq);
+#endif
+ disable_irq(lp->und_irq);
+
+ tmp = __raw_readl(&lp->tx_dma_regs->dmasm);
+ tmp = tmp | DMASM_f_m | DMASM_e_m;
+ __raw_writel(tmp, &lp->tx_dma_regs->dmasm);
+
+ tmp = __raw_readl(&lp->rx_dma_regs->dmasm);
+ tmp = tmp | DMASM_d_m | DMASM_h_m | DMASM_e_m;
+ __raw_writel(tmp, &lp->rx_dma_regs->dmasm);
+
+ free_irq(lp->rx_irq, dev);
+ free_irq(lp->tx_irq, dev);
+#ifdef RC32434_REVISION
+ free_irq(lp->ovr_irq, dev);
+#endif
+ free_irq(lp->und_irq, dev);
+ return 0;
+}
+
+
+/* transmit packet */
+static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev)
+{
+ struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
+ unsigned long flags;
+ u32 length;
+ DMAD_t td;
+
+
+ spin_lock_irqsave(&lp->lock, flags);
+
+ td = &lp->td_ring[lp->tx_chain_tail];
+
+ /* stop queue when full, drop pkts if queue already full */
+ if(lp->tx_count >= (RC32434_NUM_TDS - 2)) {
+ lp->tx_full = 1;
+
+ if(lp->tx_count == (RC32434_NUM_TDS - 2)) {
+ netif_stop_queue(dev);
+ }
+ else {
+ lp->stats.tx_dropped++;
+ dev_kfree_skb_any(skb);
+ spin_unlock_irqrestore(&lp->lock, flags);
+ return 1;
+ }
+ }
+
+ lp->tx_count ++;
+
+ lp->tx_skb[lp->tx_chain_tail] = skb;
+
+ length = skb->len;
+ dma_cache_wback((u32)skb->data, skb->len);
+
+ /* Setup the transmit descriptor. */
+ dma_cache_inv((u32) td, sizeof(*td));
+ td->ca = CPHYSADDR(skb->data);
+
+ if(__raw_readl(&(lp->tx_dma_regs->dmandptr)) == 0) {
+ if( lp->tx_chain_status == empty ) {
+ td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
+ lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
+ __raw_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
+ lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */
+ }
+ else {
+ td->control = DMA_COUNT(length) |DMAD_cof_m|DMAD_iof_m; /* Update tail */
+ lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */
+ lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */
+ lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
+ __raw_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
+ lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */
+ lp->tx_chain_status = empty;
+ }
+ }
+ else {
+ if( lp->tx_chain_status == empty ) {
+ td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
+ lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
+ lp->tx_chain_status = filled;
+ }
+ else {
+ td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
+ lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */
+ lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */
+ lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
+ }
+ }
+ dma_cache_wback((u32) td, sizeof(*td));
+
+ dev->trans_start = jiffies;
+
+ spin_unlock_irqrestore(&lp->lock, flags);
+
+ return 0;
+}
+
+
+/* Ethernet MII-PHY Handler */
+static void rc32434_mii_handler(unsigned long data)
+{
+ struct net_device *dev = (struct net_device *)data;
+ struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
+ unsigned long flags;
+ unsigned long duplex_status;
+ int port_addr = (lp->rx_irq == 0x2c? 1:0) << 8;
+
+ spin_lock_irqsave(&lp->lock, flags);
+
+ /* Two ports are using the same MII, the difference is the PHY address */
+ __raw_writel(0, &rc32434_eth0_regs->miimcfg);
+ __raw_writel(0, &rc32434_eth0_regs->miimcmd);
+ __raw_writel(port_addr |0x05, &rc32434_eth0_regs->miimaddr);
+ __raw_writel(MIIMCMD_scn_m, &rc32434_eth0_regs->miimcmd);
+ while(__raw_readl(&rc32434_eth0_regs->miimind) & MIIMIND_nv_m);
+
+ ERR("irq:%x port_addr:%x RDD:%x\n",
+ lp->rx_irq, port_addr, __raw_readl(&rc32434_eth0_regs->miimrdd));
+ duplex_status = (__raw_readl(&rc32434_eth0_regs->miimrdd) & 0x140)? ETHMAC2_fd_m: 0;
+ if(duplex_status != lp->duplex_mode) {
+ ERR("The MII-PHY is Auto-negotiated to %s-Duplex mode for Eth-%x\n", duplex_status? "Full":"Half", lp->rx_irq == 0x2c? 1:0);
+ lp->duplex_mode = duplex_status;
+ rc32434_restart(dev);
+ }
+
+ lp->mii_phy_timer.expires = jiffies + 10 * HZ;
+ add_timer(&lp->mii_phy_timer);
+
+ spin_unlock_irqrestore(&lp->lock, flags);
+
+}
+
+#ifdef RC32434_REVISION
+/* Ethernet Rx Overflow interrupt */
+static irqreturn_t
+rc32434_ovr_interrupt(int irq, void *dev_id)
+{
+ struct net_device *dev = (struct net_device *)dev_id;
+ struct rc32434_local *lp;
+ unsigned int ovr;
+ irqreturn_t retval = IRQ_NONE;
+
+ ASSERT(dev != NULL);
+
+ lp = (struct rc32434_local *)dev->priv;
+ spin_lock(&lp->lock);
+ ovr = __raw_readl(&lp->eth_regs->ethintfc);
+
+ if(ovr & ETHINTFC_ovr_m) {
+ netif_stop_queue(dev);
+
+ /* clear OVR bit */
+ __raw_writel((ovr & ~ETHINTFC_ovr_m), &lp->eth_regs->ethintfc);
+
+ /* Restart interface */
+ rc32434_restart(dev);
+ retval = IRQ_HANDLED;
+ }
+ spin_unlock(&lp->lock);
+
+ return retval;
+}
+
+#endif
+
+
+/* Ethernet Tx Underflow interrupt */
+static irqreturn_t
+rc32434_und_interrupt(int irq, void *dev_id)
+{
+ struct net_device *dev = (struct net_device *)dev_id;
+ struct rc32434_local *lp;
+ unsigned int und;
+ irqreturn_t retval = IRQ_NONE;
+
+ ASSERT(dev != NULL);
+
+ lp = (struct rc32434_local *)dev->priv;
+
+ spin_lock(&lp->lock);
+
+ und = __raw_readl(&lp->eth_regs->ethintfc);
+
+ if(und & ETHINTFC_und_m) {
+ netif_stop_queue(dev);
+
+ __raw_writel((und & ~ETHINTFC_und_m), &lp->eth_regs->ethintfc);
+
+ /* Restart interface */
+ rc32434_restart(dev);
+ retval = IRQ_HANDLED;
+ }
+
+ spin_unlock(&lp->lock);
+
+ return retval;
+}
+
+
+/* Ethernet Rx DMA interrupt */
+static irqreturn_t
+rc32434_rx_dma_interrupt(int irq, void *dev_id)
+{
+ struct net_device *dev = (struct net_device *)dev_id;
+ struct rc32434_local* lp;
+ volatile u32 dmas,dmasm;
+ irqreturn_t retval;
+
+ ASSERT(dev != NULL);
+
+ lp = (struct rc32434_local *)dev->priv;
+
+ dmas = __raw_readl(&lp->rx_dma_regs->dmas);
+ if(dmas & (DMAS_d_m|DMAS_h_m|DMAS_e_m)) {
+ /* Mask D H E bit in Rx DMA */
+ dmasm = __raw_readl(&lp->rx_dma_regs->dmasm);
+ __raw_writel(dmasm | (DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
+ netif_rx_schedule(dev, &lp->napi);
+
+ if (dmas & DMAS_e_m)
+ ERR(": DMA error\n");
+
+ retval = IRQ_HANDLED;
+ }
+ else
+ retval = IRQ_NONE;
+
+ return retval;
+}
+
+
+static int rc32434_rx(struct net_device *dev, int limit)
+{
+ struct rc32434_local *lp = netdev_priv(dev);
+ volatile DMAD_t rd = &lp->rd_ring[lp->rx_next_done];
+ struct sk_buff *skb, *skb_new;
+ u8 *pkt_buf;
+ u32 devcs, pkt_len, dmas, rx_free_desc;
+ u32 pktuncrc_len;
+ int count;
+
+ dma_cache_inv((u32)rd, sizeof(*rd));
+ for (count = 0; count < limit; count++) {
+ /* init the var. used for the later operations within the while loop */
+ skb_new = NULL;
+ devcs = rd->devcs;
+ pkt_len = RCVPKT_LENGTH(devcs);
+ skb = lp->rx_skb[lp->rx_next_done];
+
+ if ((devcs & ( ETHRX_ld_m)) != ETHRX_ld_m) {
+ /* check that this is a whole packet */
+ /* WARNING: DMA_FD bit incorrectly set in Rc32434 (errata ref #077) */
+ lp->stats.rx_errors++;
+ lp->stats.rx_dropped++;
+ }
+ else if ( (devcs & ETHRX_rok_m) ) {
+
+ /* must be the (first and) last descriptor then */
+ pkt_buf = (u8*)lp->rx_skb[lp->rx_next_done]->data;
+
+ pktuncrc_len = pkt_len - 4;
+ /* invalidate the cache */
+ dma_cache_inv((unsigned long)pkt_buf, pktuncrc_len);
+
+ /* Malloc up new buffer. */
+ skb_new = netdev_alloc_skb(dev, RC32434_RBSIZE + 2);
+
+ if (skb_new != NULL){
+ /* Make room */
+ skb_put(skb, pktuncrc_len);
+
+ skb->protocol = eth_type_trans(skb, dev);
+
+ /* pass the packet to upper layers */
+ netif_receive_skb(skb);
+
+ dev->last_rx = jiffies;
+ lp->stats.rx_packets++;
+ lp->stats.rx_bytes += pktuncrc_len;
+
+ if (IS_RCV_MP(devcs))
+ lp->stats.multicast++;
+
+ /* 16 bit align */
+ skb_reserve(skb_new, 2);
+
+ skb_new->dev = dev;
+ lp->rx_skb[lp->rx_next_done] = skb_new;
+ }
+ else {
+ ERR("no memory, dropping rx packet.\n");
+ lp->stats.rx_errors++;
+ lp->stats.rx_dropped++;
+ }
+ }
+ else {
+ /* This should only happen if we enable accepting broken packets */
+ lp->stats.rx_errors++;
+ lp->stats.rx_dropped++;
+
+ /* add statistics counters */
+ if (IS_RCV_CRC_ERR(devcs)) {
+ DBG(2, "RX CRC error\n");
+ lp->stats.rx_crc_errors++;
+ }
+ else if (IS_RCV_LOR_ERR(devcs)) {
+ DBG(2, "RX LOR error\n");
+ lp->stats.rx_length_errors++;
+ }
+ else if (IS_RCV_LE_ERR(devcs)) {
+ DBG(2, "RX LE error\n");
+ lp->stats.rx_length_errors++;
+ }
+ else if (IS_RCV_OVR_ERR(devcs)) {
+ lp->stats.rx_over_errors++;
+ }
+ else if (IS_RCV_CV_ERR(devcs)) {
+ /* code violation */
+ DBG(2, "RX CV error\n");
+ lp->stats.rx_frame_errors++;
+ }
+ else if (IS_RCV_CES_ERR(devcs)) {
+ DBG(2, "RX Preamble error\n");
+ }
+ }
+ rd->devcs = 0;
+
+ /* restore descriptor's curr_addr */
+ if(skb_new) {
+ rd->ca = CPHYSADDR(skb_new->data);
+ }
+ else
+ rd->ca = CPHYSADDR(skb->data);
+
+ rd->control = DMA_COUNT(RC32434_RBSIZE) |DMAD_cod_m |DMAD_iod_m;
+ lp->rd_ring[(lp->rx_next_done-1)& RC32434_RDS_MASK].control &= ~(DMAD_cod_m);
+
+ lp->rx_next_done = (lp->rx_next_done + 1) & RC32434_RDS_MASK;
+ dma_cache_wback((u32)rd, sizeof(*rd));
+ rd = &lp->rd_ring[lp->rx_next_done];
+ __raw_writel( ~DMAS_d_m, &lp->rx_dma_regs->dmas);
+ }
+
+ dmas = __raw_readl(&lp->rx_dma_regs->dmas);
+
+ if(dmas & DMAS_h_m) {
+ /* Mask off halt and error bits */
+ __raw_writel( ~(DMAS_h_m | DMAS_e_m), &lp->rx_dma_regs->dmas);
+#ifdef RC32434_PROC_DEBUG
+ lp->dma_halt_cnt++;
+#endif
+ rd->devcs = 0;
+ skb = lp->rx_skb[lp->rx_next_done];
+ rd->ca = CPHYSADDR(skb->data);
+ dma_cache_wback((u32)rd, sizeof(*rd));
+ rc32434_chain_rx(lp,rd);
+ }
+
+ return count;
+}
+
+static int rc32434_poll(struct napi_struct *napi, int budget)
+{
+ struct rc32434_local *lp =
+ container_of(napi, struct rc32434_local, napi);
+ struct net_device *dev = lp->dev;
+ int work_done;
+
+ work_done = rc32434_rx(dev, budget);
+ if (work_done < budget) {
+ netif_rx_complete(dev, napi);
+
+ /* Mask off interrupts */
+ writel(readl(&lp->rx_dma_regs->dmasm) &
+ (DMASM_d_m | DMASM_h_m |DMASM_e_m),
+ &lp->rx_dma_regs->dmasm);
+ }
+ return work_done;
+}
+
+
+
+/* Ethernet Tx DMA interrupt */
+static irqreturn_t
+rc32434_tx_dma_interrupt(int irq, void *dev_id)
+{
+ struct net_device *dev = (struct net_device *)dev_id;
+ struct rc32434_local *lp;
+ volatile u32 dmas,dmasm;
+ irqreturn_t retval;
+
+ ASSERT(dev != NULL);
+
+ lp = (struct rc32434_local *)dev->priv;
+
+ dmas = __raw_readl(&lp->tx_dma_regs->dmas);
+
+ if (dmas & (DMAS_f_m | DMAS_e_m)) {
+ dmasm = __raw_readl(&lp->tx_dma_regs->dmasm);
+ /* Mask F E bit in Tx DMA */
+ __raw_writel(dmasm | (DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
+
+ tasklet_hi_schedule(lp->tx_tasklet);
+
+ if(lp->tx_chain_status == filled && (__raw_readl(&(lp->tx_dma_regs->dmandptr)) == 0)) {
+ __raw_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr));
+ lp->tx_chain_status = empty;
+ lp->tx_chain_head = lp->tx_chain_tail;
+ dev->trans_start = jiffies;
+ }
+
+ if (dmas & DMAS_e_m)
+ ERR(": DMA error\n");
+
+ retval = IRQ_HANDLED;
+ }
+ else
+ retval = IRQ_NONE;
+
+ return retval;
+}
+
+
+static void rc32434_tx_tasklet(unsigned long tx_data_dev)
+{
+ struct net_device *dev = (struct net_device *)tx_data_dev;
+ struct rc32434_local* lp = (struct rc32434_local *)dev->priv;
+ volatile DMAD_t td = &lp->td_ring[lp->tx_next_done];
+ u32 devcs;
+ unsigned long flags;
+ volatile u32 dmas;
+
+ spin_lock_irqsave(&lp->lock, flags);
+
+ /* process all desc that are done */
+ while(IS_DMA_FINISHED(td->control)) {
+ if(lp->tx_full == 1) {
+ netif_wake_queue(dev);
+ lp->tx_full = 0;
+ }
+
+ devcs = lp->td_ring[lp->tx_next_done].devcs;
+ if ((devcs & (ETHTX_fd_m | ETHTX_ld_m)) != (ETHTX_fd_m | ETHTX_ld_m)) {
+ lp->stats.tx_errors++;
+ lp->stats.tx_dropped++;
+
+ /* should never happen */
+ DBG(1, __FUNCTION__ ": split tx ignored\n");
+ }
+ else if (IS_TX_TOK(devcs)) {
+ lp->stats.tx_packets++;
+ lp->stats.tx_bytes+=lp->tx_skb[lp->tx_next_done]->len;
+ }
+ else {
+ lp->stats.tx_errors++;
+ lp->stats.tx_dropped++;
+
+ /* underflow */
+ if (IS_TX_UND_ERR(devcs))
+ lp->stats.tx_fifo_errors++;
+
+ /* oversized frame */
+ if (IS_TX_OF_ERR(devcs))
+ lp->stats.tx_aborted_errors++;
+
+ /* excessive deferrals */
+ if (IS_TX_ED_ERR(devcs))
+ lp->stats.tx_carrier_errors++;
+
+ /* collisions: medium busy */
+ if (IS_TX_EC_ERR(devcs))
+ lp->stats.collisions++;
+
+ /* late collision */
+ if (IS_TX_LC_ERR(devcs))
+ lp->stats.tx_window_errors++;
+
+ }
+
+ /* We must always free the original skb */
+ if (lp->tx_skb[lp->tx_next_done] != NULL) {
+ dev_kfree_skb_any(lp->tx_skb[lp->tx_next_done]);
+ lp->tx_skb[lp->tx_next_done] = NULL;
+ }
+
+ lp->td_ring[lp->tx_next_done].control = DMAD_iof_m;
+ lp->td_ring[lp->tx_next_done].devcs = ETHTX_fd_m | ETHTX_ld_m;
+ lp->td_ring[lp->tx_next_done].link = 0;
+ lp->td_ring[lp->tx_next_done].ca = 0;
+ lp->tx_count --;
+
+ /* go on to next transmission */
+ lp->tx_next_done = (lp->tx_next_done + 1) & RC32434_TDS_MASK;
+ td = &lp->td_ring[lp->tx_next_done];
+
+ }
+
+ dmas = __raw_readl(&lp->tx_dma_regs->dmas);
+ __raw_writel( ~dmas, &lp->tx_dma_regs->dmas);
+
+ /* Enable F E bit in Tx DMA */
+ __raw_writel(__raw_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
+ spin_unlock_irqrestore(&lp->lock, flags);
+
+}
+
+
+static struct net_device_stats * rc32434_get_stats(struct net_device *dev)
+{
+ struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
+ return &lp->stats;
+}
+
+
+/*
+ * Set or clear the multicast filter for this adaptor.
+ */
+static void rc32434_multicast_list(struct net_device *dev)
+{
+ /* listen to broadcasts always and to treat */
+ /* IFF bits independantly */
+ struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
+ unsigned long flags;
+ u32 recognise = ETHARC_ab_m; /* always accept broadcasts */
+
+ if (dev->flags & IFF_PROMISC) /* set promiscuous mode */
+ recognise |= ETHARC_pro_m;
+
+ if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 15))
+ recognise |= ETHARC_am_m; /* all multicast & bcast */
+ else if (dev->mc_count > 0) {
+ DBG(2, __FUNCTION__ ": mc_count %d\n", dev->mc_count);
+ recognise |= ETHARC_am_m; /* for the time being */
+ }
+
+ spin_lock_irqsave(&lp->lock, flags);
+ __raw_writel(recognise, &lp->eth_regs->etharc);
+ spin_unlock_irqrestore(&lp->lock, flags);
+}
+
+
+static void rc32434_tx_timeout(struct net_device *dev)
+{
+ struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
+ unsigned long flags;
+
+ spin_lock_irqsave(&lp->lock, flags);
+ rc32434_restart(dev);
+ spin_unlock_irqrestore(&lp->lock, flags);
+
+}
+
+
+/*
+ * Initialize the RC32434 ethernet controller.
+ */
+static int rc32434_init(struct net_device *dev)
+{
+ struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
+ int i, j;
+
+ /* Disable DMA */
+ rc32434_abort_tx(dev);
+ rc32434_abort_rx(dev);
+
+ /* reset ethernet logic */
+ __raw_writel(0, &lp->eth_regs->ethintfc);
+ while((__raw_readl(&lp->eth_regs->ethintfc) & ETHINTFC_rip_m))
+ dev->trans_start = jiffies;
+
+ /* Enable Ethernet Interface */
+ __raw_writel(ETHINTFC_en_m, &lp->eth_regs->ethintfc);
+
+ tasklet_disable(lp->tx_tasklet);
+
+ /* Initialize the transmit Descriptors */
+ for (i = 0; i < RC32434_NUM_TDS; i++) {
+ lp->td_ring[i].control = DMAD_iof_m;
+ lp->td_ring[i].devcs = ETHTX_fd_m | ETHTX_ld_m;
+ lp->td_ring[i].ca = 0;
+ lp->td_ring[i].link = 0;
+ if (lp->tx_skb[i] != NULL) {
+ dev_kfree_skb_any(lp->tx_skb[i]);
+ lp->tx_skb[i] = NULL;
+ }
+ }
+ lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail = lp->tx_full = lp->tx_count = 0;
+ lp-> tx_chain_status = empty;
+
+ /*
+ * Initialize the receive descriptors so that they
+ * become a circular linked list, ie. let the last
+ * descriptor point to the first again.
+ */
+ for (i=0; i<RC32434_NUM_RDS; i++) {
+ struct sk_buff *skb = lp->rx_skb[i];
+
+ if (lp->rx_skb[i] == NULL) {
+ skb = dev_alloc_skb(RC32434_RBSIZE + 2);
+ if (skb == NULL) {
+ ERR("No memory in the system\n");
+ for (j = 0; j < RC32434_NUM_RDS; j ++)
+ if (lp->rx_skb[j] != NULL)
+ dev_kfree_skb_any(lp->rx_skb[j]);
+
+ return 1;
+ }
+ else {
+ skb->dev = dev;
+ skb_reserve(skb, 2);
+ lp->rx_skb[i] = skb;
+ lp->rd_ring[i].ca = CPHYSADDR(skb->data);
+
+ }
+ }
+ lp->rd_ring[i].control = DMAD_iod_m | DMA_COUNT(RC32434_RBSIZE);
+ lp->rd_ring[i].devcs = 0;
+ lp->rd_ring[i].ca = CPHYSADDR(skb->data);
+ lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[i+1]);
+
+ }
+ /* loop back */
+ lp->rd_ring[RC32434_NUM_RDS-1].link = CPHYSADDR(&lp->rd_ring[0]);
+ lp->rx_next_done = 0;
+
+ lp->rd_ring[RC32434_NUM_RDS-1].control |= DMAD_cod_m;
+ lp->rx_chain_head = 0;
+ lp->rx_chain_tail = 0;
+ lp->rx_chain_status = empty;
+
+ __raw_writel(0, &lp->rx_dma_regs->dmas);
+ /* Start Rx DMA */
+ rc32434_start_rx(lp, &lp->rd_ring[0]);
+
+ /* Enable F E bit in Tx DMA */
+ __raw_writel(__raw_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
+ /* Enable D H E bit in Rx DMA */
+ __raw_writel(__raw_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
+
+ /* Accept only packets destined for this Ethernet device address */
+ __raw_writel(ETHARC_ab_m, &lp->eth_regs->etharc);
+
+ /* Set all Ether station address registers to their initial values */
+ __raw_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0);
+ __raw_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0);
+
+ __raw_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1);
+ __raw_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1);
+
+ __raw_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2);
+ __raw_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2);
+
+ __raw_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3);
+ __raw_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3);
+
+
+ /* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */
+ __raw_writel(ETHMAC2_pe_m | ETHMAC2_cen_m | ETHMAC2_fd_m, &lp->eth_regs->ethmac2);
+ //ETHMAC2_flc_m ETHMAC2_fd_m lp->duplex_mode
+
+ /* Back to back inter-packet-gap */
+ __raw_writel(0x15, &lp->eth_regs->ethipgt);
+ /* Non - Back to back inter-packet-gap */
+ __raw_writel(0x12, &lp->eth_regs->ethipgr);
+
+ /* Management Clock Prescaler Divisor */
+ /* Clock independent setting */
+ __raw_writel(((idt_cpu_freq)/MII_CLOCK+1) & ~1,
+ &lp->eth_regs->ethmcp);
+
+ /* don't transmit until fifo contains 48b */
+ __raw_writel(48, &lp->eth_regs->ethfifott);
+
+ __raw_writel(ETHMAC1_re_m, &lp->eth_regs->ethmac1);
+
+ napi_enable(&lp->napi);
+ tasklet_enable(lp->tx_tasklet);
+
+ netif_start_queue(dev);
+
+ return 0;
+}
+
+static struct platform_driver korina_driver = {
+ .driver.name = "korina",
+ .probe = rc32434_probe,
+ .remove = rc32434_remove,
+};
+
+static int __init rc32434_init_module(void)
+{
+ return platform_driver_register(&korina_driver);
+}
+
+static void rc32434_cleanup_module(void)
+{
+ return platform_driver_unregister(&korina_driver);
+}
+
+module_init(rc32434_init_module);
+module_exit(rc32434_cleanup_module);
--- /dev/null
+/**************************************************************************
+ *
+ * BRIEF MODULE DESCRIPTION
+ * Definitions for IDT RC32434 on-chip ethernet controller.
+ *
+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ * May 2004 rkt, neb
+ *
+ * Initial Release
+ *
+ * Aug 2004
+ *
+ * Added NAPI
+ *
+ **************************************************************************
+ */
+
+
+#include <asm/rc32434/rc32434.h>
+#include <asm/rc32434/dma_v.h>
+#include <asm/rc32434/eth_v.h>
+
+#define CONFIG_IDT_USE_NAPI 1
+#define RC32434_DEBUG 2
+//#define RC32434_PROC_DEBUG
+#undef RC32434_DEBUG
+
+#ifdef RC32434_DEBUG
+
+/* use 0 for production, 1 for verification, >2 for debug */
+static int rc32434_debug = RC32434_DEBUG;
+#define ASSERT(expr) \
+ if(!(expr)) { \
+ printk( "Assertion failed! %s,%s,%s,line=%d\n", \
+ #expr,__FILE__,__FUNCTION__,__LINE__); }
+#define DBG(lvl, format, arg...) if (rc32434_debug > lvl) printk(KERN_INFO "%s: " format, dev->name , ## arg)
+#else
+#define ASSERT(expr) do {} while (0)
+#define DBG(lvl, format, arg...) do {} while (0)
+#endif
+
+#define INFO(format, arg...) printk(KERN_INFO "%s: " format, dev->name , ## arg)
+#define ERR(format, arg...) printk(KERN_ERR "%s: " format, dev->name , ## arg)
+#define WARN(format, arg...) printk(KERN_WARNING "%s: " format, dev->name , ## arg)
+
+/* the following must be powers of two */
+#ifdef CONFIG_IDT_USE_NAPI
+#define RC32434_NUM_RDS 64 /* number of receive descriptors */
+#define RC32434_NUM_TDS 64 /* number of transmit descriptors */
+#else
+#define RC32434_NUM_RDS 128 /* number of receive descriptors */
+#define RC32434_NUM_TDS 128 /* number of transmit descriptors */
+#endif
+
+#define RC32434_RBSIZE 1536 /* size of one resource buffer = Ether MTU */
+#define RC32434_RDS_MASK (RC32434_NUM_RDS-1)
+#define RC32434_TDS_MASK (RC32434_NUM_TDS-1)
+#define RD_RING_SIZE (RC32434_NUM_RDS * sizeof(struct DMAD_s))
+#define TD_RING_SIZE (RC32434_NUM_TDS * sizeof(struct DMAD_s))
+
+#define RC32434_TX_TIMEOUT HZ * 100
+
+#define rc32434_eth0_regs ((ETH_t)(ETH0_VirtualAddress))
+#define rc32434_eth1_regs ((ETH_t)(ETH1_VirtualAddress))
+
+enum status { filled, empty};
+#define IS_DMA_FINISHED(X) (((X) & (DMAD_f_m)) != 0)
+#define IS_DMA_DONE(X) (((X) & (DMAD_d_m)) != 0)
+
+
+/* Information that need to be kept for each board. */
+struct rc32434_local {
+ ETH_t eth_regs;
+ DMA_Chan_t rx_dma_regs;
+ DMA_Chan_t tx_dma_regs;
+ volatile DMAD_t td_ring; /* transmit descriptor ring */
+ volatile DMAD_t rd_ring; /* receive descriptor ring */
+
+ struct sk_buff* tx_skb[RC32434_NUM_TDS]; /* skbuffs for pkt to trans */
+ struct sk_buff* rx_skb[RC32434_NUM_RDS]; /* skbuffs for pkt to trans */
+
+ struct tasklet_struct * tx_tasklet;
+
+ int rx_next_done;
+ int rx_chain_head;
+ int rx_chain_tail;
+ enum status rx_chain_status;
+
+ int tx_next_done;
+ int tx_chain_head;
+ int tx_chain_tail;
+ enum status tx_chain_status;
+ int tx_count;
+ int tx_full;
+
+ struct timer_list mii_phy_timer;
+ unsigned long duplex_mode;
+
+ int rx_irq;
+ int tx_irq;
+ int ovr_irq;
+ int und_irq;
+
+ struct net_device_stats stats;
+ spinlock_t lock;
+
+ /* debug /proc entry */
+ struct proc_dir_entry *ps;
+ int dma_halt_cnt; int dma_run_cnt;
+ struct napi_struct napi;
+ struct net_device *dev;
+};
+
+extern unsigned int idt_cpu_freq;
+
+/* Index to functions, as function prototypes. */
+static int rc32434_open(struct net_device *dev);
+static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev);
+static void rc32434_mii_handler(unsigned long data);
+static irqreturn_t rc32434_und_interrupt(int irq, void *dev_id);
+static irqreturn_t rc32434_rx_dma_interrupt(int irq, void *dev_id);
+static irqreturn_t rc32434_tx_dma_interrupt(int irq, void *dev_id);
+#ifdef RC32434_REVISION
+static irqreturn_t rc32434_ovr_interrupt(int irq, void *dev_id);
+#endif
+static int rc32434_close(struct net_device *dev);
+static struct net_device_stats *rc32434_get_stats(struct net_device *dev);
+static void rc32434_multicast_list(struct net_device *dev);
+static int rc32434_init(struct net_device *dev);
+static void rc32434_tx_timeout(struct net_device *dev);
+
+static void rc32434_tx_tasklet(unsigned long tx_data_dev);
+static int rc32434_poll(struct napi_struct *napi, int budget);
+static void rc32434_cleanup_module(void);
+
+
+static inline void rc32434_abort_dma(struct net_device *dev, DMA_Chan_t ch)
+{
+ if (__raw_readl(&ch->dmac) & DMAC_run_m) {
+ __raw_writel(0x10, &ch->dmac);
+
+ while (!(__raw_readl(&ch->dmas) & DMAS_h_m))
+ dev->trans_start = jiffies;
+
+ __raw_writel(0, &ch->dmas);
+ }
+
+ __raw_writel(0, &ch->dmadptr);
+ __raw_writel(0, &ch->dmandptr);
+}
--- /dev/null
+/*
+ * RC32434_WDT 0.01: IDT Interprise 79RC32434 watchdog driver
+ * Copyright (c) Ondrej Zajicek <santiago@crfreenet.org>, 2006
+ *
+ * based on
+ *
+ * SoftDog 0.05: A Software Watchdog Device
+ *
+ * (c) Copyright 1996 Alan Cox <alan@redhat.com>, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/miscdevice.h>
+#include <linux/watchdog.h>
+#include <linux/reboot.h>
+#include <linux/smp_lock.h>
+#include <linux/init.h>
+#include <asm/bootinfo.h>
+#include <asm/time.h>
+#include <asm/uaccess.h>
+#include <asm/rc32434/integ.h>
+
+#define DEFAULT_TIMEOUT 15 /* (secs) Default is 15 seconds */
+#define MAX_TIMEOUT 20
+/*
+ * (secs) Max is 20 seconds
+ * (max frequency of counter is ~200 MHz, counter is 32-bit unsigned int)
+ */
+
+#define NAME "rc32434_wdt"
+#define VERSION "0.1"
+
+static INTEG_t rc_wdt = (INTEG_t) INTEG_VirtualAddress;
+
+static int expect_close = 0;
+static int access = 0;
+static int timeout = 0;
+
+static int nowayout = WATCHDOG_NOWAYOUT;
+module_param(nowayout, int, 0);
+MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
+MODULE_LICENSE("GPL");
+
+
+static inline void start_wdt(void)
+{
+ rc_wdt -> wtcount = 0;
+ rc_wdt -> errcs |= ERRCS_wre_m;
+ rc_wdt -> wtc |= WTC_en_m;
+}
+
+static inline void stop_wdt(void)
+{
+ rc_wdt -> wtc &= ~WTC_en_m;
+ rc_wdt -> errcs &= ~ERRCS_wre_m;
+}
+
+static inline void set_wdt(int new_timeout)
+{
+ u32 cmp = new_timeout * mips_hpt_frequency;
+ u32 state;
+
+ timeout = new_timeout;
+ /*
+ * store and disable WTC
+ */
+ state = rc_wdt -> wtc & WTC_en_m;
+ rc_wdt -> wtc &= ~WTC_en_m;
+
+ rc_wdt -> wtcount = 0;
+ rc_wdt -> wtcompare = cmp;
+
+ /*
+ * restore WTC
+ */
+ rc_wdt -> wtc |= state;
+}
+
+static inline void update_wdt(void)
+{
+ rc_wdt -> wtcount = 0;
+}
+
+/*
+ * Allow only one person to hold it open
+ */
+
+static int wdt_open(struct inode *inode, struct file *file)
+{
+ if (access)
+ return -EBUSY;
+ if (nowayout) {
+ __module_get(THIS_MODULE);
+ }
+ /*
+ * Activate timer
+ */
+ start_wdt();
+ printk(KERN_INFO NAME ": enabling watchdog timer\n");
+ access = 1;
+ return 0;
+}
+
+static int wdt_release(struct inode *inode, struct file *file)
+{
+ /*
+ * Shut off the timer.
+ * Lock it in if it's a module and we set nowayout
+ */
+ if (expect_close && nowayout == 0) {
+ stop_wdt ();
+ printk(KERN_INFO NAME ": disabling watchdog timer\n");
+ module_put(THIS_MODULE);
+ } else {
+ printk (KERN_CRIT NAME ": device closed unexpectedly. WDT will not stop!\n");
+ }
+ access = 0;
+ return 0;
+}
+
+static ssize_t wdt_write(struct file *file, const char *data, size_t len, loff_t *ppos)
+{
+ /*
+ * Refresh the timer.
+ */
+ if (len) {
+ if (!nowayout) {
+ size_t i;
+
+ /* In case it was set long ago */
+ expect_close = 0;
+
+ for (i = 0; i != len; i++) {
+ char c;
+ if (get_user(c, data + i))
+ return -EFAULT;
+ if (c == 'V')
+ expect_close = 1;
+ }
+ }
+ update_wdt ();
+ return len;
+ }
+ return 0;
+}
+
+static int wdt_ioctl(struct inode *inode, struct file *file,
+ unsigned int cmd, unsigned long arg)
+{
+ int new_timeout;
+ static struct watchdog_info ident = {
+ .options = WDIOF_SETTIMEOUT |
+ WDIOF_KEEPALIVEPING |
+ WDIOF_MAGICCLOSE,
+ .firmware_version = 0,
+ .identity = "RC32434_WDT Watchdog",
+ };
+ switch (cmd) {
+ default:
+ return -ENOTTY;
+ case WDIOC_GETSUPPORT:
+ if(copy_to_user((struct watchdog_info *)arg, &ident, sizeof(ident)))
+ return -EFAULT;
+ return 0;
+ case WDIOC_GETSTATUS:
+ case WDIOC_GETBOOTSTATUS:
+ return put_user(0,(int *)arg);
+ case WDIOC_KEEPALIVE:
+ update_wdt();
+ return 0;
+ case WDIOC_SETTIMEOUT:
+ if (get_user(new_timeout, (int *)arg))
+ return -EFAULT;
+ if (new_timeout < 1)
+ return -EINVAL;
+ if (new_timeout > MAX_TIMEOUT)
+ return -EINVAL;
+ set_wdt(new_timeout);
+ /* Fall */
+ case WDIOC_GETTIMEOUT:
+ return put_user(timeout, (int *)arg);
+ }
+}
+
+static struct file_operations wdt_fops = {
+ owner: THIS_MODULE,
+ llseek: no_llseek,
+ write: wdt_write,
+ ioctl: wdt_ioctl,
+ open: wdt_open,
+ release: wdt_release,
+};
+
+static struct miscdevice wdt_miscdev = {
+ minor: WATCHDOG_MINOR,
+ name: "watchdog",
+ fops: &wdt_fops,
+};
+
+static char banner[] __initdata = KERN_INFO NAME ": Watchdog Timer version " VERSION ", timer margin: %d sec\n";
+
+static int __init watchdog_init(void)
+{
+ int ret;
+
+ /*
+ * There should be check for RC32434 SoC
+ */
+ if (mips_machgroup != MACH_GROUP_MIKROTIK) return -1;
+
+ ret = misc_register(&wdt_miscdev);
+
+ if (ret)
+ return ret;
+
+ stop_wdt();
+ set_wdt(DEFAULT_TIMEOUT);
+
+ printk(banner, timeout);
+
+ return 0;
+}
+
+static void __exit watchdog_exit(void)
+{
+ misc_deregister(&wdt_miscdev);
+}
+
+module_init(watchdog_init);
+module_exit(watchdog_exit);
--- /dev/null
+#ifndef __IDT_DDR_H__
+#define __IDT_DDR_H__
+
+/*******************************************************************************
+ *
+ * Copyright 2002 Integrated Device Technology, Inc.
+ * All rights reserved.
+ *
+ * DDR register definition.
+ *
+ * File : $Id: ddr.h,v 1.2 2002/06/06 18:34:03 astichte Exp $
+ *
+ * Author : ryan.holmQVist@idt.com
+ * Date : 20011005
+ * Update :
+ * $Log: ddr.h,v $
+ * Revision 1.2 2002/06/06 18:34:03 astichte
+ * Added XXX_PhysicalAddress and XXX_VirtualAddress
+ *
+ * Revision 1.1 2002/05/29 17:33:21 sysarch
+ * jba File moved from vcode/include/idt/acacia
+ *
+ *
+ ******************************************************************************/
+
+enum
+{
+ DDR0_PhysicalAddress = 0x18018000,
+ DDR_PhysicalAddress = DDR0_PhysicalAddress, // Default
+
+ DDR0_VirtualAddress = 0xb8018000,
+ DDR_VirtualAddress = DDR0_VirtualAddress, // Default
+} ;
+
+typedef struct DDR_s
+{
+ u32 ddrbase ;
+ u32 ddrmask ;
+ u32 res1;
+ u32 res2;
+ u32 ddrc ;
+ u32 ddrabase ;
+ u32 ddramask ;
+ u32 ddramap ;
+ u32 ddrcust;
+ u32 ddrrdc;
+ u32 ddrspare;
+} volatile *DDR_t ;
+
+enum
+{
+ DDR0BASE_baseaddr_b = 16,
+ DDR0BASE_baseaddr_m = 0xffff0000,
+
+ DDR0MASK_mask_b = 16,
+ DDR0MASK_mask_m = 0xffff0000,
+
+ DDR1BASE_baseaddr_b = 16,
+ DDR1BASE_baseaddr_m = 0xffff0000,
+
+ DDR1MASK_mask_b = 16,
+ DDR1MASK_mask_m = 0xffff0000,
+
+ DDRC_ata_b = 5,
+ DDRC_ata_m = 0x000000E0,
+ DDRC_dbw_b = 8,
+ DDRC_dbw_m = 0x00000100,
+ DDRC_wr_b = 9,
+ DDRC_wr_m = 0x00000600,
+ DDRC_ps_b = 11,
+ DDRC_ps_m = 0x00001800,
+ DDRC_dtype_b = 13,
+ DDRC_dtype_m = 0x0000e000,
+ DDRC_rfc_b = 16,
+ DDRC_rfc_m = 0x000f0000,
+ DDRC_rp_b = 20,
+ DDRC_rp_m = 0x00300000,
+ DDRC_ap_b = 22,
+ DDRC_ap_m = 0x00400000,
+ DDRC_rcd_b = 23,
+ DDRC_rcd_m = 0x01800000,
+ DDRC_cl_b = 25,
+ DDRC_cl_m = 0x06000000,
+ DDRC_dbm_b = 27,
+ DDRC_dbm_m = 0x08000000,
+ DDRC_sds_b = 28,
+ DDRC_sds_m = 0x10000000,
+ DDRC_atp_b = 29,
+ DDRC_atp_m = 0x60000000,
+ DDRC_re_b = 31,
+ DDRC_re_m = 0x80000000,
+
+ DDRRDC_ces_b = 0,
+ DDRRDC_ces_m = 0x00000001,
+ DDRRDC_ace_b = 1,
+ DDRRDC_ace_m = 0x00000002,
+
+ DDRABASE_baseaddr_b = 16,
+ DDRABASE_baseaddr_m = 0xffff0000,
+
+ DDRAMASK_mask_b = 16,
+ DDRAMASK_mask_m = 0xffff0000,
+
+ DDRAMAP_map_b = 16,
+ DDRAMAP_map_m = 0xffff0000,
+
+ DDRCUST_cs_b = 0,
+ DDRCUST_cs_m = 0x00000003,
+ DDRCUST_we_b = 2,
+ DDRCUST_we_m = 0x00000004,
+ DDRCUST_ras_b = 3,
+ DDRCUST_ras_m = 0x00000008,
+ DDRCUST_cas_b = 4,
+ DDRCUST_cas_m = 0x00000010,
+ DDRCUST_cke_b = 5,
+ DDRCUST_cke_m = 0x00000020,
+ DDRCUST_ba_b = 6,
+ DDRCUST_ba_m = 0x000000c0,
+
+ RCOUNT_rcount_b = 0,
+ RCOUNT_rcount_m = 0x0000ffff,
+
+ RCOMPARE_rcompare_b = 0,
+ RCOMPARE_rcompare_m = 0x0000ffff,
+
+ RTC_ce_b = 0,
+ RTC_ce_m = 0x00000001,
+ RTC_to_b = 1,
+ RTC_to_m = 0x00000002,
+ RTC_rqe_b = 2,
+ RTC_rqe_m = 0x00000004,
+
+ DDRDQSC_dm_b = 0,
+ DDRDQSC_dm_m = 0x00000003,
+ DDRDQSC_dqsbs_b = 2,
+ DDRDQSC_dqsbs_m = 0x000000fc,
+ DDRDQSC_db_b = 8,
+ DDRDQSC_db_m = 0x00000100,
+ DDRDQSC_dbsp_b = 9,
+ DDRDQSC_dbsp_m = 0x01fffe00,
+ DDRDQSC_bdp_b = 25,
+ DDRDQSC_bdp_m = 0x7e000000,
+
+ DDRDLLC_eao_b = 0,
+ DDRDLLC_eao_m = 0x00000001,
+ DDRDLLC_eo_b = 1,
+ DDRDLLC_eo_m = 0x0000003e,
+ DDRDLLC_fs_b = 6,
+ DDRDLLC_fs_m = 0x000000c0,
+ DDRDLLC_as_b = 8,
+ DDRDLLC_as_m = 0x00000700,
+ DDRDLLC_sp_b = 11,
+ DDRDLLC_sp_m = 0x001ff800,
+
+ DDRDLLFC_men_b = 0,
+ DDRDLLFC_men_m = 0x00000001,
+ DDRDLLFC_aen_b = 1,
+ DDRDLLFC_aen_m = 0x00000002,
+ DDRDLLFC_ff_b = 2,
+ DDRDLLFC_ff_m = 0x00000004,
+
+ DDRDLLTA_addr_b = 2,
+ DDRDLLTA_addr_m = 0xfffffffc,
+
+ DDRDLLED_dbe_b = 0,
+ DDRDLLED_dbe_m = 0x00000001,
+ DDRDLLED_dte_b = 1,
+ DDRDLLED_dte_m = 0x00000002,
+
+
+} ;
+
+#endif // __IDT_DDR_H__
--- /dev/null
+#ifndef __IDT_DMA_H__
+#define __IDT_DMA_H__
+
+/*******************************************************************************
+ *
+ * Copyright 2002 Integrated Device Technology, Inc.
+ * All rights reserved.
+ *
+ * DMA register definition.
+ *
+ * File : $Id: dma.h,v 1.3 2002/06/06 18:34:03 astichte Exp $
+ *
+ * Author : ryan.holmQVist@idt.com
+ * Date : 20011005
+ * Update :
+ * $Log: dma.h,v $
+ * Revision 1.3 2002/06/06 18:34:03 astichte
+ * Added XXX_PhysicalAddress and XXX_VirtualAddress
+ *
+ * Revision 1.2 2002/06/05 18:30:46 astichte
+ * Removed IDTField
+ *
+ * Revision 1.1 2002/05/29 17:33:21 sysarch
+ * jba File moved from vcode/include/idt/acacia
+ *
+ *
+ ******************************************************************************/
+
+enum
+{
+ DMA0_PhysicalAddress = 0x18040000,
+ DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
+
+ DMA0_VirtualAddress = 0xb8040000,
+ DMA_VirtualAddress = DMA0_VirtualAddress, // Default
+} ;
+
+/*
+ * DMA descriptor (in physical memory).
+ */
+
+typedef struct DMAD_s
+{
+ u32 control ; // Control. use DMAD_*
+ u32 ca ; // Current Address.
+ u32 devcs ; // Device control and status.
+ u32 link ; // Next descriptor in chain.
+} volatile *DMAD_t ;
+
+enum
+{
+ DMAD_size = sizeof (struct DMAD_s),
+ DMAD_count_b = 0, // in DMAD_t -> control
+ DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
+ DMAD_ds_b = 20, // in DMAD_t -> control
+ DMAD_ds_m = 0x00300000, // in DMAD_t -> control
+ DMAD_ds_ethRcv_v = 0,
+ DMAD_ds_ethXmt_v = 0,
+ DMAD_ds_memToFifo_v = 0,
+ DMAD_ds_fifoToMem_v = 0,
+ DMAD_ds_pciToMem_v = 0,
+ DMAD_ds_memToPci_v = 0,
+
+ DMAD_devcmd_b = 22, // in DMAD_t -> control
+ DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
+ DMAD_devcmd_byte_v = 0, //memory-to-memory
+ DMAD_devcmd_halfword_v = 1, //memory-to-memory
+ DMAD_devcmd_word_v = 2, //memory-to-memory
+ DMAD_devcmd_2words_v = 3, //memory-to-memory
+ DMAD_devcmd_4words_v = 4, //memory-to-memory
+ DMAD_devcmd_6words_v = 5, //memory-to-memory
+ DMAD_devcmd_8words_v = 6, //memory-to-memory
+ DMAD_devcmd_16words_v = 7, //memory-to-memory
+ DMAD_cof_b = 25, // chain on finished
+ DMAD_cof_m = 0x02000000, //
+ DMAD_cod_b = 26, // chain on done
+ DMAD_cod_m = 0x04000000, //
+ DMAD_iof_b = 27, // interrupt on finished
+ DMAD_iof_m = 0x08000000, //
+ DMAD_iod_b = 28, // interrupt on done
+ DMAD_iod_m = 0x10000000, //
+ DMAD_t_b = 29, // terminated
+ DMAD_t_m = 0x20000000, //
+ DMAD_d_b = 30, // done
+ DMAD_d_m = 0x40000000, //
+ DMAD_f_b = 31, // finished
+ DMAD_f_m = 0x80000000, //
+} ;
+
+/*
+ * DMA register (within Internal Register Map).
+ */
+
+struct DMA_Chan_s
+{
+ u32 dmac ; // Control.
+ u32 dmas ; // Status.
+ u32 dmasm ; // Mask.
+ u32 dmadptr ; // Descriptor pointer.
+ u32 dmandptr ; // Next descriptor pointer.
+};
+
+typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
+
+//DMA_Channels use DMACH_count instead
+
+enum
+{
+ DMAC_run_b = 0, //
+ DMAC_run_m = 0x00000001, //
+ DMAC_dm_b = 1, // done mask
+ DMAC_dm_m = 0x00000002, //
+ DMAC_mode_b = 2, //
+ DMAC_mode_m = 0x0000000c, //
+ DMAC_mode_auto_v = 0,
+ DMAC_mode_burst_v = 1,
+ DMAC_mode_transfer_v = 2, //usually used
+ DMAC_mode_reserved_v = 3,
+ DMAC_a_b = 4, //
+ DMAC_a_m = 0x00000010, //
+
+ DMAS_f_b = 0, // finished (sticky)
+ DMAS_f_m = 0x00000001, //
+ DMAS_d_b = 1, // done (sticky)
+ DMAS_d_m = 0x00000002, //
+ DMAS_c_b = 2, // chain (sticky)
+ DMAS_c_m = 0x00000004, //
+ DMAS_e_b = 3, // error (sticky)
+ DMAS_e_m = 0x00000008, //
+ DMAS_h_b = 4, // halt (sticky)
+ DMAS_h_m = 0x00000010, //
+
+ DMASM_f_b = 0, // finished (1=mask)
+ DMASM_f_m = 0x00000001, //
+ DMASM_d_b = 1, // done (1=mask)
+ DMASM_d_m = 0x00000002, //
+ DMASM_c_b = 2, // chain (1=mask)
+ DMASM_c_m = 0x00000004, //
+ DMASM_e_b = 3, // error (1=mask)
+ DMASM_e_m = 0x00000008, //
+ DMASM_h_b = 4, // halt (1=mask)
+ DMASM_h_m = 0x00000010, //
+} ;
+
+/*
+ * DMA channel definitions
+ */
+
+enum
+{
+ DMACH_ethRcv = 0,
+ DMACH_ethXmt = 1,
+ DMACH_memToFifo = 2,
+ DMACH_fifoToMem = 3,
+ DMACH_pciToMem = 4,
+ DMACH_memToPci = 5,
+
+ DMACH_count //must be last
+};
+
+
+typedef struct DMAC_s
+{
+ struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
+} volatile *DMA_t ;
+
+#endif // __IDT_DMA_H__
+
--- /dev/null
+#ifndef __IDT_DMA_V_H__
+#define __IDT_DMA_V_H__
+
+/*******************************************************************************
+ *
+ * Copyright 2002 Integrated Device Technology, Inc.
+ * All rights reserved.
+ *
+ * DMA register definition.
+ *
+ * File : $Id: dma.h,v 1.3 2002/06/06 18:34:03 astichte Exp $
+ *
+ * Author : ryan.holmQVist@idt.com
+ * Date : 20011005
+ * Update :
+ * $Log: dma.h,v $
+ * Revision 1.3 2002/06/06 18:34:03 astichte
+ * Added XXX_PhysicalAddress and XXX_VirtualAddress
+ *
+ * Revision 1.2 2002/06/05 18:30:46 astichte
+ * Removed IDTField
+ *
+ * Revision 1.1 2002/05/29 17:33:21 sysarch
+ * jba File moved from vcode/include/idt/acacia
+ *
+ *
+ ******************************************************************************/
+#include <asm/rc32434/dma.h>
+#include <asm/rc32434/rc32434.h>
+#define DMA_CHAN_OFFSET 0x14
+#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
+#define DMA_COUNT(count) \
+ ((count) & DMAD_count_m)
+
+#define DMA_HALT_TIMEOUT 500
+
+
+static inline int rc32434_halt_dma(DMA_Chan_t ch)
+{
+ int timeout=1;
+ if (local_readl(&ch->dmac) & DMAC_run_m) {
+ local_writel(0, &ch->dmac);
+ for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
+ if (local_readl(&ch->dmas) & DMAS_h_m) {
+ local_writel(0, &ch->dmas);
+ break;
+ }
+ }
+ }
+
+ return timeout ? 0 : 1;
+}
+
+static inline void rc32434_start_dma(DMA_Chan_t ch, u32 dma_addr)
+{
+ local_writel(0, &ch->dmandptr);
+ local_writel(dma_addr, &ch->dmadptr);
+}
+
+static inline void rc32434_chain_dma(DMA_Chan_t ch, u32 dma_addr)
+{
+ local_writel(dma_addr, &ch->dmandptr);
+}
+
+#endif // __IDT_DMA_V_H__
+
+
+
+
+
+
+
--- /dev/null
+#ifndef __IDT_ETH_H__
+#define __IDT_ETH_H__
+
+/*******************************************************************************
+ *
+ * Copyright 2002 Integrated Device Technology, Inc.
+ * All rights reserved.
+ *
+ * Ethernet register definition.
+ *
+ * File : $Id: eth.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
+ *
+ * Author : Allen.Stichter@idt.com
+ * Date : 20020605
+ * Update :
+ * $Log: eth.h,v $
+ * Revision 1.3 2002/06/06 18:34:04 astichte
+ * Added XXX_PhysicalAddress and XXX_VirtualAddress
+ *
+ * Revision 1.2 2002/06/05 18:19:46 astichte
+ * Added
+ *
+ * Revision 1.1 2002/05/29 17:33:22 sysarch
+ * jba File moved from vcode/include/idt/acacia
+ *
+ ******************************************************************************/
+
+enum
+{
+ ETH0_PhysicalAddress = 0x18060000,
+ ETH_PhysicalAddress = ETH0_PhysicalAddress, // Default
+
+ ETH0_VirtualAddress = 0xb8060000,
+ ETH_VirtualAddress = ETH0_VirtualAddress, // Default
+} ;
+
+typedef struct
+{
+ u32 ethintfc ;
+ u32 ethfifott ;
+ u32 etharc ;
+ u32 ethhash0 ;
+ u32 ethhash1 ;
+ u32 ethu0 [4] ; // Reserved.
+ u32 ethpfs ;
+ u32 ethmcp ;
+ u32 eth_u1 [10] ; // Reserved.
+ u32 ethspare ;
+ u32 eth_u2 [42] ; // Reserved.
+ u32 ethsal0 ;
+ u32 ethsah0 ;
+ u32 ethsal1 ;
+ u32 ethsah1 ;
+ u32 ethsal2 ;
+ u32 ethsah2 ;
+ u32 ethsal3 ;
+ u32 ethsah3 ;
+ u32 ethrbc ;
+ u32 ethrpc ;
+ u32 ethrupc ;
+ u32 ethrfc ;
+ u32 ethtbc ;
+ u32 ethgpf ;
+ u32 eth_u9 [50] ; // Reserved.
+ u32 ethmac1 ;
+ u32 ethmac2 ;
+ u32 ethipgt ;
+ u32 ethipgr ;
+ u32 ethclrt ;
+ u32 ethmaxf ;
+ u32 eth_u10 ; // Reserved.
+ u32 ethmtest ;
+ u32 miimcfg ;
+ u32 miimcmd ;
+ u32 miimaddr ;
+ u32 miimwtd ;
+ u32 miimrdd ;
+ u32 miimind ;
+ u32 eth_u11 ; // Reserved.
+ u32 eth_u12 ; // Reserved.
+ u32 ethcfsa0 ;
+ u32 ethcfsa1 ;
+ u32 ethcfsa2 ;
+} volatile *ETH_t;
+
+enum
+{
+ ETHINTFC_en_b = 0,
+ ETHINTFC_en_m = 0x00000001,
+ ETHINTFC_its_b = 1,
+ ETHINTFC_its_m = 0x00000002,
+ ETHINTFC_rip_b = 2,
+ ETHINTFC_rip_m = 0x00000004,
+ ETHINTFC_jam_b = 3,
+ ETHINTFC_jam_m = 0x00000008,
+ ETHINTFC_ovr_b = 4,
+ ETHINTFC_ovr_m = 0x00000010,
+ ETHINTFC_und_b = 5,
+ ETHINTFC_und_m = 0x00000020,
+ ETHINTFC_iom_b = 6,
+ ETHINTFC_iom_m = 0x000000c0,
+
+ ETHFIFOTT_tth_b = 0,
+ ETHFIFOTT_tth_m = 0x0000007f,
+
+ ETHARC_pro_b = 0,
+ ETHARC_pro_m = 0x00000001,
+ ETHARC_am_b = 1,
+ ETHARC_am_m = 0x00000002,
+ ETHARC_afm_b = 2,
+ ETHARC_afm_m = 0x00000004,
+ ETHARC_ab_b = 3,
+ ETHARC_ab_m = 0x00000008,
+
+ ETHSAL_byte5_b = 0,
+ ETHSAL_byte5_m = 0x000000ff,
+ ETHSAL_byte4_b = 8,
+ ETHSAL_byte4_m = 0x0000ff00,
+ ETHSAL_byte3_b = 16,
+ ETHSAL_byte3_m = 0x00ff0000,
+ ETHSAL_byte2_b = 24,
+ ETHSAL_byte2_m = 0xff000000,
+
+ ETHSAH_byte1_b = 0,
+ ETHSAH_byte1_m = 0x000000ff,
+ ETHSAH_byte0_b = 8,
+ ETHSAH_byte0_m = 0x0000ff00,
+
+ ETHGPF_ptv_b = 0,
+ ETHGPF_ptv_m = 0x0000ffff,
+
+ ETHPFS_pfd_b = 0,
+ ETHPFS_pfd_m = 0x00000001,
+
+ ETHCFSA0_cfsa4_b = 0,
+ ETHCFSA0_cfsa4_m = 0x000000ff,
+ ETHCFSA0_cfsa5_b = 8,
+ ETHCFSA0_cfsa5_m = 0x0000ff00,
+
+ ETHCFSA1_cfsa2_b = 0,
+ ETHCFSA1_cfsa2_m = 0x000000ff,
+ ETHCFSA1_cfsa3_b = 8,
+ ETHCFSA1_cfsa3_m = 0x0000ff00,
+
+ ETHCFSA2_cfsa0_b = 0,
+ ETHCFSA2_cfsa0_m = 0x000000ff,
+ ETHCFSA2_cfsa1_b = 8,
+ ETHCFSA2_cfsa1_m = 0x0000ff00,
+
+ ETHMAC1_re_b = 0,
+ ETHMAC1_re_m = 0x00000001,
+ ETHMAC1_paf_b = 1,
+ ETHMAC1_paf_m = 0x00000002,
+ ETHMAC1_rfc_b = 2,
+ ETHMAC1_rfc_m = 0x00000004,
+ ETHMAC1_tfc_b = 3,
+ ETHMAC1_tfc_m = 0x00000008,
+ ETHMAC1_lb_b = 4,
+ ETHMAC1_lb_m = 0x00000010,
+ ETHMAC1_mr_b = 31,
+ ETHMAC1_mr_m = 0x80000000,
+
+ ETHMAC2_fd_b = 0,
+ ETHMAC2_fd_m = 0x00000001,
+ ETHMAC2_flc_b = 1,
+ ETHMAC2_flc_m = 0x00000002,
+ ETHMAC2_hfe_b = 2,
+ ETHMAC2_hfe_m = 0x00000004,
+ ETHMAC2_dc_b = 3,
+ ETHMAC2_dc_m = 0x00000008,
+ ETHMAC2_cen_b = 4,
+ ETHMAC2_cen_m = 0x00000010,
+ ETHMAC2_pe_b = 5,
+ ETHMAC2_pe_m = 0x00000020,
+ ETHMAC2_vpe_b = 6,
+ ETHMAC2_vpe_m = 0x00000040,
+ ETHMAC2_ape_b = 7,
+ ETHMAC2_ape_m = 0x00000080,
+ ETHMAC2_ppe_b = 8,
+ ETHMAC2_ppe_m = 0x00000100,
+ ETHMAC2_lpe_b = 9,
+ ETHMAC2_lpe_m = 0x00000200,
+ ETHMAC2_nb_b = 12,
+ ETHMAC2_nb_m = 0x00001000,
+ ETHMAC2_bp_b = 13,
+ ETHMAC2_bp_m = 0x00002000,
+ ETHMAC2_ed_b = 14,
+ ETHMAC2_ed_m = 0x00004000,
+
+ ETHIPGT_ipgt_b = 0,
+ ETHIPGT_ipgt_m = 0x0000007f,
+
+ ETHIPGR_ipgr2_b = 0,
+ ETHIPGR_ipgr2_m = 0x0000007f,
+ ETHIPGR_ipgr1_b = 8,
+ ETHIPGR_ipgr1_m = 0x00007f00,
+
+ ETHCLRT_maxret_b = 0,
+ ETHCLRT_maxret_m = 0x0000000f,
+ ETHCLRT_colwin_b = 8,
+ ETHCLRT_colwin_m = 0x00003f00,
+
+ ETHMAXF_maxf_b = 0,
+ ETHMAXF_maxf_m = 0x0000ffff,
+
+ ETHMTEST_tb_b = 2,
+ ETHMTEST_tb_m = 0x00000004,
+
+ ETHMCP_div_b = 0,
+ ETHMCP_div_m = 0x000000ff,
+
+ MIIMCFG_rsv_b = 0,
+ MIIMCFG_rsv_m = 0x0000000c,
+
+ MIIMCMD_rd_b = 0,
+ MIIMCMD_rd_m = 0x00000001,
+ MIIMCMD_scn_b = 1,
+ MIIMCMD_scn_m = 0x00000002,
+
+ MIIMADDR_regaddr_b = 0,
+ MIIMADDR_regaddr_m = 0x0000001f,
+ MIIMADDR_phyaddr_b = 8,
+ MIIMADDR_phyaddr_m = 0x00001f00,
+
+ MIIMWTD_wdata_b = 0,
+ MIIMWTD_wdata_m = 0x0000ffff,
+
+ MIIMRDD_rdata_b = 0,
+ MIIMRDD_rdata_m = 0x0000ffff,
+
+ MIIMIND_bsy_b = 0,
+ MIIMIND_bsy_m = 0x00000001,
+ MIIMIND_scn_b = 1,
+ MIIMIND_scn_m = 0x00000002,
+ MIIMIND_nv_b = 2,
+ MIIMIND_nv_m = 0x00000004,
+
+} ;
+
+/*
+ * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
+ */
+enum
+{
+ ETHRX_fd_b = 0,
+ ETHRX_fd_m = 0x00000001,
+ ETHRX_ld_b = 1,
+ ETHRX_ld_m = 0x00000002,
+ ETHRX_rok_b = 2,
+ ETHRX_rok_m = 0x00000004,
+ ETHRX_fm_b = 3,
+ ETHRX_fm_m = 0x00000008,
+ ETHRX_mp_b = 4,
+ ETHRX_mp_m = 0x00000010,
+ ETHRX_bp_b = 5,
+ ETHRX_bp_m = 0x00000020,
+ ETHRX_vlt_b = 6,
+ ETHRX_vlt_m = 0x00000040,
+ ETHRX_cf_b = 7,
+ ETHRX_cf_m = 0x00000080,
+ ETHRX_ovr_b = 8,
+ ETHRX_ovr_m = 0x00000100,
+ ETHRX_crc_b = 9,
+ ETHRX_crc_m = 0x00000200,
+ ETHRX_cv_b = 10,
+ ETHRX_cv_m = 0x00000400,
+ ETHRX_db_b = 11,
+ ETHRX_db_m = 0x00000800,
+ ETHRX_le_b = 12,
+ ETHRX_le_m = 0x00001000,
+ ETHRX_lor_b = 13,
+ ETHRX_lor_m = 0x00002000,
+ ETHRX_ces_b = 14,
+ ETHRX_ces_m = 0x00004000,
+ ETHRX_length_b = 16,
+ ETHRX_length_m = 0xffff0000,
+
+ ETHTX_fd_b = 0,
+ ETHTX_fd_m = 0x00000001,
+ ETHTX_ld_b = 1,
+ ETHTX_ld_m = 0x00000002,
+ ETHTX_oen_b = 2,
+ ETHTX_oen_m = 0x00000004,
+ ETHTX_pen_b = 3,
+ ETHTX_pen_m = 0x00000008,
+ ETHTX_cen_b = 4,
+ ETHTX_cen_m = 0x00000010,
+ ETHTX_hen_b = 5,
+ ETHTX_hen_m = 0x00000020,
+ ETHTX_tok_b = 6,
+ ETHTX_tok_m = 0x00000040,
+ ETHTX_mp_b = 7,
+ ETHTX_mp_m = 0x00000080,
+ ETHTX_bp_b = 8,
+ ETHTX_bp_m = 0x00000100,
+ ETHTX_und_b = 9,
+ ETHTX_und_m = 0x00000200,
+ ETHTX_of_b = 10,
+ ETHTX_of_m = 0x00000400,
+ ETHTX_ed_b = 11,
+ ETHTX_ed_m = 0x00000800,
+ ETHTX_ec_b = 12,
+ ETHTX_ec_m = 0x00001000,
+ ETHTX_lc_b = 13,
+ ETHTX_lc_m = 0x00002000,
+ ETHTX_td_b = 14,
+ ETHTX_td_m = 0x00004000,
+ ETHTX_crc_b = 15,
+ ETHTX_crc_m = 0x00008000,
+ ETHTX_le_b = 16,
+ ETHTX_le_m = 0x00010000,
+ ETHTX_cc_b = 17,
+ ETHTX_cc_m = 0x001E0000,
+} ;
+
+#endif // __IDT_ETH_H__
+
+
+
+
--- /dev/null
+#ifndef __IDT_ETH_V_H__
+#define __IDT_ETH_V_H__
+
+/*******************************************************************************
+ *
+ * Copyright 2002 Integrated Device Technology, Inc.
+ * All rights reserved.
+ *
+ * Ethernet register definition.
+ *
+ * File : $Id: eth.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
+ *
+ * Author : Allen.Stichter@idt.com
+ * Date : 20020605
+ * Update :
+ * $Log: eth.h,v $
+ * Revision 1.3 2002/06/06 18:34:04 astichte
+ * Added XXX_PhysicalAddress and XXX_VirtualAddress
+ *
+ * Revision 1.2 2002/06/05 18:19:46 astichte
+ * Added
+ *
+ * Revision 1.1 2002/05/29 17:33:22 sysarch
+ * jba File moved from vcode/include/idt/acacia
+ *
+ ******************************************************************************/
+
+#include <asm/rc32434/eth.h>
+
+#define IS_TX_TOK(X) (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b ) /* Transmit Okay */
+#define IS_TX_MP(X) (((X) & (1<<ETHTX_mp_b)) >> ETHTX_mp_b ) /* Multicast */
+#define IS_TX_BP(X) (((X) & (1<<ETHTX_bp_b)) >> ETHTX_bp_b ) /* Broadcast */
+#define IS_TX_UND_ERR(X) (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b ) /* Transmit FIFO Underflow */
+#define IS_TX_OF_ERR(X) (((X) & (1<<ETHTX_of_b)) >> ETHTX_of_b ) /* Oversized frame */
+#define IS_TX_ED_ERR(X) (((X) & (1<<ETHTX_ed_b)) >> ETHTX_ed_b ) /* Excessive deferral */
+#define IS_TX_EC_ERR(X) (((X) & (1<<ETHTX_ec_b)) >> ETHTX_ec_b) /* Excessive collisions */
+#define IS_TX_LC_ERR(X) (((X) & (1<<ETHTX_lc_b)) >> ETHTX_lc_b ) /* Late Collision */
+#define IS_TX_TD_ERR(X) (((X) & (1<<ETHTX_td_b)) >> ETHTX_td_b ) /* Transmit deferred*/
+#define IS_TX_CRC_ERR(X) (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b ) /* CRC Error */
+#define IS_TX_LE_ERR(X) (((X) & (1<<ETHTX_le_b)) >> ETHTX_le_b ) /* Length Error */
+
+#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b) /* Collision Count */
+
+#define IS_RCV_ROK(X) (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b) /* Receive Okay */
+#define IS_RCV_FM(X) (((X) & (1<<ETHRX_fm_b)) >> ETHRX_fm_b) /* Is Filter Match */
+#define IS_RCV_MP(X) (((X) & (1<<ETHRX_mp_b)) >> ETHRX_mp_b) /* Is it MP */
+#define IS_RCV_BP(X) (((X) & (1<<ETHRX_bp_b)) >> ETHRX_bp_b) /* Is it BP */
+#define IS_RCV_VLT(X) (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b) /* VLAN Tag Detect */
+#define IS_RCV_CF(X) (((X) & (1<<ETHRX_cf_b)) >> ETHRX_cf_b) /* Control Frame */
+#define IS_RCV_OVR_ERR(X) (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b) /* Receive Overflow */
+#define IS_RCV_CRC_ERR(X) (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b) /* CRC Error */
+#define IS_RCV_CV_ERR(X) (((X) & (1<<ETHRX_cv_b)) >> ETHRX_cv_b) /* Code Violation */
+#define IS_RCV_DB_ERR(X) (((X) & (1<<ETHRX_db_b)) >> ETHRX_db_b) /* Dribble Bits */
+#define IS_RCV_LE_ERR(X) (((X) & (1<<ETHRX_le_b)) >> ETHRX_le_b) /* Length error */
+#define IS_RCV_LOR_ERR(X) (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b) /* Length Out of Range */
+#define IS_RCV_CES_ERR(X) (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b) /* Preamble error */
+#define RCVPKT_LENGTH(X) (((X) & ETHRX_length_m) >> ETHRX_length_b) /* Length of the received packet */
+#endif // __IDT_ETH_V_H__
+
+
+
+
+
--- /dev/null
+/*
+ * Copyright 2002 Integrated Device Technology, Inc.
+ * All rights reserved.
+ *
+ * GPIO register definition.
+ *
+ * Author : ryan.holmQVist@idt.com
+ * Date : 20011005
+ * Copyright (C) 2001, 2002 Ryan Holm <ryan.holmQVist@idt.com>
+ * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
+ */
+
+#ifndef _RC32434_GPIO_H_
+#define _RC32434_GPIO_H_
+
+#include <linux/types.h>
+
+struct rb500_gpio_reg {
+ u32 gpiofunc; /* GPIO Function Register
+ * gpiofunc[x]==0 bit = gpio
+ * func[x]==1 bit = altfunc
+ */
+ u32 gpiocfg; /* GPIO Configuration Register
+ * gpiocfg[x]==0 bit = input
+ * gpiocfg[x]==1 bit = output
+ */
+ u32 gpiod; /* GPIO Data Register
+ * gpiod[x] read/write gpio pinX status
+ */
+ u32 gpioilevel; /* GPIO Interrupt Status Register
+ * interrupt level (see gpioistat)
+ */
+ u32 gpioistat; /* Gpio Interrupt Status Register
+ * istat[x] = (gpiod[x] == level[x])
+ * cleared in ISR (STICKY bits)
+ */
+ u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
+};
+
+/* UART GPIO signals */
+#define RC32434_UART0_SOUT (1 << 0)
+#define RC32434_UART0_SIN (1 << 1)
+#define RC32434_UART0_RTS (1 << 2)
+#define RC32434_UART0_CTS (1 << 3)
+
+/* M & P bus GPIO signals */
+#define RC32434_MP_BIT_22 (1 << 4)
+#define RC32434_MP_BIT_23 (1 << 5)
+#define RC32434_MP_BIT_24 (1 << 6)
+#define RC32434_MP_BIT_25 (1 << 7)
+
+/* CPU GPIO signals */
+#define RC32434_CPU_GPIO (1 << 8)
+
+/* Reserved GPIO signals */
+#define RC32434_AF_SPARE_6 (1 << 9)
+#define RC32434_AF_SPARE_4 (1 << 10)
+#define RC32434_AF_SPARE_3 (1 << 11)
+#define RC32434_AF_SPARE_2 (1 << 12)
+
+/* PCI messaging unit */
+#define RC32434_PCI_MSU_GPIO (1 << 13)
+
+extern int rb500_gpio_get_value(unsigned gpio);
+extern void rb500_gpio_set_value(unsigned gpio, int value);
+extern int rb500_gpio_direction_input(unsigned gpio);
+extern int rb500_gpio_direction_output(unsigned gpio, int value);
+extern void rb500_gpio_set_int_level(unsigned gpio, int value);
+extern int rb500_gpio_get_int_level(unsigned gpio);
+extern void rb500_gpio_set_int_status(unsigned gpio, int value);
+extern int rb500_gpio_get_int_status(unsigned gpio);
+extern void rb500_gpio_set_func(unsigned gpio, int value);
+extern int rb500_gpio_get_func(unsigned gpio);
+
+
+/* Wrappers for the arch-neutral GPIO API */
+
+static inline int gpio_request(unsigned gpio, const char *label)
+{
+ /* Not yet implemented */
+ return 0;
+}
+
+static inline void gpio_free(unsigned gpio)
+{
+ /* Not yet implemented */
+}
+
+static inline int gpio_direction_input(unsigned gpio)
+{
+ return rb500_gpio_direction_input(gpio);
+}
+
+static inline int gpio_direction_output(unsigned gpio, int value)
+{
+ return rb500_gpio_direction_output(gpio, value);
+}
+
+static inline int gpio_get_value(unsigned gpio)
+{
+ return rb500_gpio_get_value(gpio);
+}
+
+static inline void gpio_set_value(unsigned gpio, int value)
+{
+ rb500_gpio_set_value(gpio, value);
+}
+
+static inline int gpio_to_irq(unsigned gpio)
+{
+ return gpio;
+}
+
+static inline int irq_to_gpio(unsigned irq)
+{
+ return irq;
+}
+
+/* For cansleep */
+#include <asm-generic/gpio.h>
+
+#endif /* _RC32434_GPIO_H_ */
--- /dev/null
+#ifndef __IDT_INTEG_H__
+#define __IDT_INTEG_H__
+
+/*******************************************************************************
+ *
+ * Copyright 2002 Integrated Device Technology, Inc.
+ * All rights reserved.
+ *
+ * System Integrity register definition.
+ *
+ * File : $Id: integ.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
+ *
+ * Author : ryan.holmQVist@idt.com
+ * Date : 20011005
+ * Update :
+ * $Log: integ.h,v $
+ * Revision 1.3 2002/06/06 18:34:04 astichte
+ * Added XXX_PhysicalAddress and XXX_VirtualAddress
+ *
+ * Revision 1.2 2002/06/05 18:32:33 astichte
+ * Removed IDTField
+ *
+ * Revision 1.1 2002/05/29 17:33:22 sysarch
+ * jba File moved from vcode/include/idt/acacia
+ *
+ ******************************************************************************/
+
+enum
+{
+ INTEG0_PhysicalAddress = 0x18030000,
+ INTEG_PhysicalAddress = INTEG0_PhysicalAddress, // Default
+
+ INTEG0_VirtualAddress = 0xb8030000,
+ INTEG_VirtualAddress = INTEG0_VirtualAddress, // Default
+} ;
+
+// if you are looing for CEA, try rst.h
+typedef struct
+{
+ u32 filler [0xc] ; // 0x30 bytes unused.
+ u32 errcs ; // sticky use ERRCS_
+ u32 wtcount ; // Watchdog timer count reg.
+ u32 wtcompare ; // Watchdog timer timeout value.
+ u32 wtc ; // Watchdog timer control. use WTC_
+} volatile *INTEG_t ;
+
+enum
+{
+ ERRCS_wto_b = 0, // In INTEG_t -> errcs
+ ERRCS_wto_m = 0x00000001,
+ ERRCS_wne_b = 1, // In INTEG_t -> errcs
+ ERRCS_wne_m = 0x00000002,
+ ERRCS_ucw_b = 2, // In INTEG_t -> errcs
+ ERRCS_ucw_m = 0x00000004,
+ ERRCS_ucr_b = 3, // In INTEG_t -> errcs
+ ERRCS_ucr_m = 0x00000008,
+ ERRCS_upw_b = 4, // In INTEG_t -> errcs
+ ERRCS_upw_m = 0x00000010,
+ ERRCS_upr_b = 5, // In INTEG_t -> errcs
+ ERRCS_upr_m = 0x00000020,
+ ERRCS_udw_b = 6, // In INTEG_t -> errcs
+ ERRCS_udw_m = 0x00000040,
+ ERRCS_udr_b = 7, // In INTEG_t -> errcs
+ ERRCS_udr_m = 0x00000080,
+ ERRCS_sae_b = 8, // In INTEG_t -> errcs
+ ERRCS_sae_m = 0x00000100,
+ ERRCS_wre_b = 9, // In INTEG_t -> errcs
+ ERRCS_wre_m = 0x00000200,
+
+ WTC_en_b = 0, // In INTEG_t -> wtc
+ WTC_en_m = 0x00000001,
+ WTC_to_b = 1, // In INTEG_t -> wtc
+ WTC_to_m = 0x00000002,
+} ;
+
+#endif // __IDT_INTEG_H__
--- /dev/null
+#ifndef __ASM_MACH_MIPS_IRQ_H
+#define __ASM_MACH_MIPS_IRQ_H
+
+#define NR_IRQS 256
+#include_next <irq.h>
+
+#endif /* __ASM_MACH_MIPS_IRQ_H */
--- /dev/null
+/**************************************************************************
+ *
+ * BRIEF MODULE DESCRIPTION
+ * PCI register definitio
+ *
+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ * May 2004 rkt, neb.
+ *
+ * Initial Release
+ *
+ *
+ *
+ **************************************************************************
+ */
+
+#ifndef __IDT_PCI_H__
+#define __IDT_PCI_H__
+
+enum
+{
+ PCI0_PhysicalAddress = 0x18080000,
+ PCI_PhysicalAddress = PCI0_PhysicalAddress,
+
+ PCI0_VirtualAddress = 0xB8080000,
+ PCI_VirtualAddress = PCI0_VirtualAddress,
+} ;
+
+enum
+{
+ PCI_LbaCount = 4, // Local base addresses.
+} ;
+
+typedef struct
+{
+ u32 a ; // Address.
+ u32 c ; // Control.
+ u32 m ; // mapping.
+} PCI_Map_s ;
+
+typedef struct
+{
+ u32 pcic ;
+ u32 pcis ;
+ u32 pcism ;
+ u32 pcicfga ;
+ u32 pcicfgd ;
+ PCI_Map_s pcilba [PCI_LbaCount] ;
+ u32 pcidac ;
+ u32 pcidas ;
+ u32 pcidasm ;
+ u32 pcidad ;
+ u32 pcidma8c ;
+ u32 pcidma9c ;
+ u32 pcitc ;
+} volatile *PCI_t ;
+
+// PCI messaging unit.
+enum
+{
+ PCIM_Count = 2,
+} ;
+typedef struct
+{
+ u32 pciim [PCIM_Count] ;
+ u32 pciom [PCIM_Count] ;
+ u32 pciid ;
+ u32 pciiic ;
+ u32 pciiim ;
+ u32 pciiod ;
+ u32 pciioic ;
+ u32 pciioim ;
+} volatile *PCIM_t ;
+
+/*******************************************************************************
+ *
+ * PCI Control Register
+ *
+ ******************************************************************************/
+enum
+{
+ PCIC_en_b = 0,
+ PCIC_en_m = 0x00000001,
+ PCIC_tnr_b = 1,
+ PCIC_tnr_m = 0x00000002,
+ PCIC_sce_b = 2,
+ PCIC_sce_m = 0x00000004,
+ PCIC_ien_b = 3,
+ PCIC_ien_m = 0x00000008,
+ PCIC_aaa_b = 4,
+ PCIC_aaa_m = 0x00000010,
+ PCIC_eap_b = 5,
+ PCIC_eap_m = 0x00000020,
+ PCIC_pcim_b = 6,
+ PCIC_pcim_m = 0x000001c0,
+ PCIC_pcim_disabled_v = 0,
+ PCIC_pcim_tnr_v = 1, // Satellite - target not ready
+ PCIC_pcim_suspend_v = 2, // Satellite - suspended CPU.
+ PCIC_pcim_extern_v = 3, // Host - external arbiter.
+ PCIC_pcim_fixed_v = 4, // Host - fixed priority arb.
+ PCIC_pcim_roundrobin_v = 5, // Host - round robin priority.
+ PCIC_pcim_reserved6_v = 6,
+ PCIC_pcim_reserved7_v = 7,
+ PCIC_igm_b = 9,
+ PCIC_igm_m = 0x00000200,
+} ;
+
+/*******************************************************************************
+ *
+ * PCI Status Register
+ *
+ ******************************************************************************/
+enum {
+ PCIS_eed_b = 0,
+ PCIS_eed_m = 0x00000001,
+ PCIS_wr_b = 1,
+ PCIS_wr_m = 0x00000002,
+ PCIS_nmi_b = 2,
+ PCIS_nmi_m = 0x00000004,
+ PCIS_ii_b = 3,
+ PCIS_ii_m = 0x00000008,
+ PCIS_cwe_b = 4,
+ PCIS_cwe_m = 0x00000010,
+ PCIS_cre_b = 5,
+ PCIS_cre_m = 0x00000020,
+ PCIS_mdpe_b = 6,
+ PCIS_mdpe_m = 0x00000040,
+ PCIS_sta_b = 7,
+ PCIS_sta_m = 0x00000080,
+ PCIS_rta_b = 8,
+ PCIS_rta_m = 0x00000100,
+ PCIS_rma_b = 9,
+ PCIS_rma_m = 0x00000200,
+ PCIS_sse_b = 10,
+ PCIS_sse_m = 0x00000400,
+ PCIS_ose_b = 11,
+ PCIS_ose_m = 0x00000800,
+ PCIS_pe_b = 12,
+ PCIS_pe_m = 0x00001000,
+ PCIS_tae_b = 13,
+ PCIS_tae_m = 0x00002000,
+ PCIS_rle_b = 14,
+ PCIS_rle_m = 0x00004000,
+ PCIS_bme_b = 15,
+ PCIS_bme_m = 0x00008000,
+ PCIS_prd_b = 16,
+ PCIS_prd_m = 0x00010000,
+ PCIS_rip_b = 17,
+ PCIS_rip_m = 0x00020000,
+} ;
+
+/*******************************************************************************
+ *
+ * PCI Status Mask Register
+ *
+ ******************************************************************************/
+enum {
+ PCISM_eed_b = 0,
+ PCISM_eed_m = 0x00000001,
+ PCISM_wr_b = 1,
+ PCISM_wr_m = 0x00000002,
+ PCISM_nmi_b = 2,
+ PCISM_nmi_m = 0x00000004,
+ PCISM_ii_b = 3,
+ PCISM_ii_m = 0x00000008,
+ PCISM_cwe_b = 4,
+ PCISM_cwe_m = 0x00000010,
+ PCISM_cre_b = 5,
+ PCISM_cre_m = 0x00000020,
+ PCISM_mdpe_b = 6,
+ PCISM_mdpe_m = 0x00000040,
+ PCISM_sta_b = 7,
+ PCISM_sta_m = 0x00000080,
+ PCISM_rta_b = 8,
+ PCISM_rta_m = 0x00000100,
+ PCISM_rma_b = 9,
+ PCISM_rma_m = 0x00000200,
+ PCISM_sse_b = 10,
+ PCISM_sse_m = 0x00000400,
+ PCISM_ose_b = 11,
+ PCISM_ose_m = 0x00000800,
+ PCISM_pe_b = 12,
+ PCISM_pe_m = 0x00001000,
+ PCISM_tae_b = 13,
+ PCISM_tae_m = 0x00002000,
+ PCISM_rle_b = 14,
+ PCISM_rle_m = 0x00004000,
+ PCISM_bme_b = 15,
+ PCISM_bme_m = 0x00008000,
+ PCISM_prd_b = 16,
+ PCISM_prd_m = 0x00010000,
+ PCISM_rip_b = 17,
+ PCISM_rip_m = 0x00020000,
+} ;
+
+/*******************************************************************************
+ *
+ * PCI Configuration Address Register
+ *
+ ******************************************************************************/
+enum {
+ PCICFGA_reg_b = 2,
+ PCICFGA_reg_m = 0x000000fc,
+ PCICFGA_reg_id_v = 0x00>>2, //use PCFGID_
+ PCICFGA_reg_04_v = 0x04>>2, //use PCFG04_
+ PCICFGA_reg_08_v = 0x08>>2, //use PCFG08_
+ PCICFGA_reg_0C_v = 0x0C>>2, //use PCFG0C_
+ PCICFGA_reg_pba0_v = 0x10>>2, //use PCIPBA_
+ PCICFGA_reg_pba1_v = 0x14>>2, //use PCIPBA_
+ PCICFGA_reg_pba2_v = 0x18>>2, //use PCIPBA_
+ PCICFGA_reg_pba3_v = 0x1c>>2, //use PCIPBA_
+ PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
+ PCICFGA_reg_3C_v = 0x3C>>2, //use PCFG3C_
+ PCICFGA_reg_pba0c_v = 0x44>>2, //use PCIPBAC_
+ PCICFGA_reg_pba0m_v = 0x48>>2,
+ PCICFGA_reg_pba1c_v = 0x4c>>2, //use PCIPBAC_
+ PCICFGA_reg_pba1m_v = 0x50>>2,
+ PCICFGA_reg_pba2c_v = 0x54>>2, //use PCIPBAC_
+ PCICFGA_reg_pba2m_v = 0x58>>2,
+ PCICFGA_reg_pba3c_v = 0x5c>>2, //use PCIPBAC_
+ PCICFGA_reg_pba3m_v = 0x60>>2,
+ PCICFGA_reg_pmgt_v = 0x64>>2,
+ PCICFGA_func_b = 8,
+ PCICFGA_func_m = 0x00000700,
+ PCICFGA_dev_b = 11,
+ PCICFGA_dev_m = 0x0000f800,
+ PCICFGA_dev_internal_v = 0,
+ PCICFGA_bus_b = 16,
+ PCICFGA_bus_m = 0x00ff0000,
+ PCICFGA_bus_type0_v = 0, //local bus
+ PCICFGA_en_b = 31, // read only
+ PCICFGA_en_m = 0x80000000,
+} ;
+
+enum {
+ PCFGID_vendor_b = 0,
+ PCFGID_vendor_m = 0x0000ffff,
+ PCFGID_vendor_IDT_v = 0x111d,
+ PCFGID_device_b = 16,
+ PCFGID_device_m = 0xffff0000,
+ PCFGID_device_Korinade_v = 0x0214,
+
+ PCFG04_command_ioena_b = 1,
+ PCFG04_command_ioena_m = 0x00000001,
+ PCFG04_command_memena_b = 2,
+ PCFG04_command_memena_m = 0x00000002,
+ PCFG04_command_bmena_b = 3,
+ PCFG04_command_bmena_m = 0x00000004,
+ PCFG04_command_mwinv_b = 5,
+ PCFG04_command_mwinv_m = 0x00000010,
+ PCFG04_command_parena_b = 7,
+ PCFG04_command_parena_m = 0x00000040,
+ PCFG04_command_serrena_b = 9,
+ PCFG04_command_serrena_m = 0x00000100,
+ PCFG04_command_fastbbena_b = 10,
+ PCFG04_command_fastbbena_m = 0x00000200,
+ PCFG04_status_b = 16,
+ PCFG04_status_m = 0xffff0000,
+ PCFG04_status_66MHz_b = 21, // 66 MHz enable
+ PCFG04_status_66MHz_m = 0x00200000,
+ PCFG04_status_fbb_b = 23,
+ PCFG04_status_fbb_m = 0x00800000,
+ PCFG04_status_mdpe_b = 24,
+ PCFG04_status_mdpe_m = 0x01000000,
+ PCFG04_status_dst_b = 25,
+ PCFG04_status_dst_m = 0x06000000,
+ PCFG04_status_sta_b = 27,
+ PCFG04_status_sta_m = 0x08000000,
+ PCFG04_status_rta_b = 28,
+ PCFG04_status_rta_m = 0x10000000,
+ PCFG04_status_rma_b = 29,
+ PCFG04_status_rma_m = 0x20000000,
+ PCFG04_status_sse_b = 30,
+ PCFG04_status_sse_m = 0x40000000,
+ PCFG04_status_pe_b = 31,
+ PCFG04_status_pe_m = 0x40000000,
+
+ PCFG08_revId_b = 0,
+ PCFG08_revId_m = 0x000000ff,
+ PCFG08_classCode_b = 0,
+ PCFG08_classCode_m = 0xffffff00,
+ PCFG08_classCode_bridge_v = 06,
+ PCFG08_classCode_proc_v = 0x0b3000, // processor-MIPS
+ PCFG0C_cacheline_b = 0,
+ PCFG0C_cacheline_m = 0x000000ff,
+ PCFG0C_masterLatency_b = 8,
+ PCFG0C_masterLatency_m = 0x0000ff00,
+ PCFG0C_headerType_b = 16,
+ PCFG0C_headerType_m = 0x00ff0000,
+ PCFG0C_bist_b = 24,
+ PCFG0C_bist_m = 0xff000000,
+
+ PCIPBA_msi_b = 0,
+ PCIPBA_msi_m = 0x00000001,
+ PCIPBA_p_b = 3,
+ PCIPBA_p_m = 0x00000004,
+ PCIPBA_baddr_b = 8,
+ PCIPBA_baddr_m = 0xffffff00,
+
+ PCFGSS_vendorId_b = 0,
+ PCFGSS_vendorId_m = 0x0000ffff,
+ PCFGSS_id_b = 16,
+ PCFGSS_id_m = 0xffff0000,
+
+ PCFG3C_interruptLine_b = 0,
+ PCFG3C_interruptLine_m = 0x000000ff,
+ PCFG3C_interruptPin_b = 8,
+ PCFG3C_interruptPin_m = 0x0000ff00,
+ PCFG3C_minGrant_b = 16,
+ PCFG3C_minGrant_m = 0x00ff0000,
+ PCFG3C_maxLat_b = 24,
+ PCFG3C_maxLat_m = 0xff000000,
+
+ PCIPBAC_msi_b = 0,
+ PCIPBAC_msi_m = 0x00000001,
+ PCIPBAC_p_b = 1,
+ PCIPBAC_p_m = 0x00000002,
+ PCIPBAC_size_b = 2,
+ PCIPBAC_size_m = 0x0000007c,
+ PCIPBAC_sb_b = 7,
+ PCIPBAC_sb_m = 0x00000080,
+ PCIPBAC_pp_b = 8,
+ PCIPBAC_pp_m = 0x00000100,
+ PCIPBAC_mr_b = 9,
+ PCIPBAC_mr_m = 0x00000600,
+ PCIPBAC_mr_read_v =0, //no prefetching
+ PCIPBAC_mr_readLine_v =1,
+ PCIPBAC_mr_readMult_v =2,
+ PCIPBAC_mrl_b = 11,
+ PCIPBAC_mrl_m = 0x00000800,
+ PCIPBAC_mrm_b = 12,
+ PCIPBAC_mrm_m = 0x00001000,
+ PCIPBAC_trp_b = 13,
+ PCIPBAC_trp_m = 0x00002000,
+
+ PCFG40_trdyTimeout_b = 0,
+ PCFG40_trdyTimeout_m = 0x000000ff,
+ PCFG40_retryLim_b = 8,
+ PCFG40_retryLim_m = 0x0000ff00,
+};
+
+/*******************************************************************************
+ *
+ * PCI Local Base Address [0|1|2|3] Register
+ *
+ ******************************************************************************/
+enum {
+ PCILBA_baddr_b = 0, // In PCI_t -> pcilba [] .a
+ PCILBA_baddr_m = 0xffffff00,
+} ;
+/*******************************************************************************
+ *
+ * PCI Local Base Address Control Register
+ *
+ ******************************************************************************/
+enum {
+ PCILBAC_msi_b = 0, // In pPci->pcilba[i].c
+ PCILBAC_msi_m = 0x00000001,
+ PCILBAC_msi_mem_v = 0,
+ PCILBAC_msi_io_v = 1,
+ PCILBAC_size_b = 2, // In pPci->pcilba[i].c
+ PCILBAC_size_m = 0x0000007c,
+ PCILBAC_sb_b = 7, // In pPci->pcilba[i].c
+ PCILBAC_sb_m = 0x00000080,
+ PCILBAC_rt_b = 8, // In pPci->pcilba[i].c
+ PCILBAC_rt_m = 0x00000100,
+ PCILBAC_rt_noprefetch_v = 0, // mem read
+ PCILBAC_rt_prefetch_v = 1, // mem readline
+} ;
+
+/*******************************************************************************
+ *
+ * PCI Local Base Address [0|1|2|3] Mapping Register
+ *
+ ******************************************************************************/
+enum {
+ PCILBAM_maddr_b = 8,
+ PCILBAM_maddr_m = 0xffffff00,
+} ;
+
+/*******************************************************************************
+ *
+ * PCI Decoupled Access Control Register
+ *
+ ******************************************************************************/
+enum {
+ PCIDAC_den_b = 0,
+ PCIDAC_den_m = 0x00000001,
+} ;
+
+/*******************************************************************************
+ *
+ * PCI Decoupled Access Status Register
+ *
+ ******************************************************************************/
+enum {
+ PCIDAS_d_b = 0,
+ PCIDAS_d_m = 0x00000001,
+ PCIDAS_b_b = 1,
+ PCIDAS_b_m = 0x00000002,
+ PCIDAS_e_b = 2,
+ PCIDAS_e_m = 0x00000004,
+ PCIDAS_ofe_b = 3,
+ PCIDAS_ofe_m = 0x00000008,
+ PCIDAS_off_b = 4,
+ PCIDAS_off_m = 0x00000010,
+ PCIDAS_ife_b = 5,
+ PCIDAS_ife_m = 0x00000020,
+ PCIDAS_iff_b = 6,
+ PCIDAS_iff_m = 0x00000040,
+} ;
+
+/*******************************************************************************
+ *
+ * PCI DMA Channel 8 Configuration Register
+ *
+ ******************************************************************************/
+enum
+{
+ PCIDMA8C_mbs_b = 0, // Maximum Burst Size.
+ PCIDMA8C_mbs_m = 0x00000fff, // { pcidma8c }
+ PCIDMA8C_our_b = 12, // Optimize Unaligned Burst Reads.
+ PCIDMA8C_our_m = 0x00001000, // { pcidma8c }
+} ;
+
+/*******************************************************************************
+ *
+ * PCI DMA Channel 9 Configuration Register
+ *
+ ******************************************************************************/
+enum
+{
+ PCIDMA9C_mbs_b = 0, // Maximum Burst Size.
+ PCIDMA9C_mbs_m = 0x00000fff, // { pcidma9c }
+} ;
+
+/*******************************************************************************
+ *
+ * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
+ *
+ ******************************************************************************/
+enum {
+ PCIDMAD_pt_b = 22, // in DEVCMD field (descriptor)
+ PCIDMAD_pt_m = 0x00c00000, // preferred transaction field
+ // These are for reads (DMA channel 8)
+ PCIDMAD_devcmd_mr_v = 0, //memory read
+ PCIDMAD_devcmd_mrl_v = 1, //memory read line
+ PCIDMAD_devcmd_mrm_v = 2, //memory read multiple
+ PCIDMAD_devcmd_ior_v = 3, //I/O read
+ // These are for writes (DMA channel 9)
+ PCIDMAD_devcmd_mw_v = 0, //memory write
+ PCIDMAD_devcmd_mwi_v = 1, //memory write invalidate
+ PCIDMAD_devcmd_iow_v = 3, //I/O write
+
+ // Swap byte field applies to both DMA channel 8 and 9
+ PCIDMAD_sb_b = 24, // in DEVCMD field (descriptor)
+ PCIDMAD_sb_m = 0x01000000, // swap byte field
+} ;
+
+
+/*******************************************************************************
+ *
+ * PCI Target Control Register
+ *
+ ******************************************************************************/
+enum
+{
+ PCITC_rtimer_b = 0, // In PCITC_t -> pcitc
+ PCITC_rtimer_m = 0x000000ff,
+ PCITC_dtimer_b = 8, // In PCITC_t -> pcitc
+ PCITC_dtimer_m = 0x0000ff00,
+ PCITC_rdr_b = 18, // In PCITC_t -> pcitc
+ PCITC_rdr_m = 0x00040000,
+ PCITC_ddt_b = 19, // In PCITC_t -> pcitc
+ PCITC_ddt_m = 0x00080000,
+} ;
+/*******************************************************************************
+ *
+ * PCI messaging unit [applies to both inbound and outbound registers ]
+ *
+ ******************************************************************************/
+enum
+{
+ PCIM_m0_b = 0, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
+ PCIM_m0_m = 0x00000001, // inbound or outbound message 0
+ PCIM_m1_b = 1, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
+ PCIM_m1_m = 0x00000002, // inbound or outbound message 1
+ PCIM_db_b = 2, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
+ PCIM_db_m = 0x00000004, // inbound or outbound doorbell
+};
+
+
+
+
+
+
+#define PCI_MSG_VirtualAddress 0xB8088010
+#define rc32434_pci ((volatile PCI_t) PCI0_VirtualAddress)
+#define rc32434_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
+
+#define PCIM_SHFT 0x6
+#define PCIM_BIT_LEN 0x7
+#define PCIM_H_EA 0x3
+#define PCIM_H_IA_FIX 0x4
+#define PCIM_H_IA_RR 0x5
+
+#define PCI_ADDR_START 0x50000000
+
+#define CPUTOPCI_MEM_WIN 0x02000000
+#define CPUTOPCI_IO_WIN 0x00100000
+#define PCILBA_SIZE_SHFT 2
+#define PCILBA_SIZE_MASK 0x1F
+#define SIZE_256MB 0x1C
+#define SIZE_128MB 0x1B
+#define SIZE_64MB 0x1A
+#define SIZE_32MB 0x19
+#define SIZE_16MB 0x18
+#define SIZE_4MB 0x16
+#define SIZE_2MB 0x15
+#define SIZE_1MB 0x14
+#define KORINA_CONFIG0_ADDR 0x80000000
+#define KORINA_CONFIG1_ADDR 0x80000004
+#define KORINA_CONFIG2_ADDR 0x80000008
+#define KORINA_CONFIG3_ADDR 0x8000000C
+#define KORINA_CONFIG4_ADDR 0x80000010
+#define KORINA_CONFIG5_ADDR 0x80000014
+#define KORINA_CONFIG6_ADDR 0x80000018
+#define KORINA_CONFIG7_ADDR 0x8000001C
+#define KORINA_CONFIG8_ADDR 0x80000020
+#define KORINA_CONFIG9_ADDR 0x80000024
+#define KORINA_CONFIG10_ADDR 0x80000028
+#define KORINA_CONFIG11_ADDR 0x8000002C
+#define KORINA_CONFIG12_ADDR 0x80000030
+#define KORINA_CONFIG13_ADDR 0x80000034
+#define KORINA_CONFIG14_ADDR 0x80000038
+#define KORINA_CONFIG15_ADDR 0x8000003C
+#define KORINA_CONFIG16_ADDR 0x80000040
+#define KORINA_CONFIG17_ADDR 0x80000044
+#define KORINA_CONFIG18_ADDR 0x80000048
+#define KORINA_CONFIG19_ADDR 0x8000004C
+#define KORINA_CONFIG20_ADDR 0x80000050
+#define KORINA_CONFIG21_ADDR 0x80000054
+#define KORINA_CONFIG22_ADDR 0x80000058
+#define KORINA_CONFIG23_ADDR 0x8000005C
+#define KORINA_CONFIG24_ADDR 0x80000060
+#define KORINA_CONFIG25_ADDR 0x80000064
+#define KORINA_CMD (PCFG04_command_ioena_m | \
+ PCFG04_command_memena_m | \
+ PCFG04_command_bmena_m | \
+ PCFG04_command_mwinv_m | \
+ PCFG04_command_parena_m | \
+ PCFG04_command_serrena_m )
+
+#define KORINA_STAT (PCFG04_status_mdpe_m | \
+ PCFG04_status_sta_m | \
+ PCFG04_status_rta_m | \
+ PCFG04_status_rma_m | \
+ PCFG04_status_sse_m | \
+ PCFG04_status_pe_m)
+
+#define KORINA_CNFG1 ((KORINA_STAT<<16)|KORINA_CMD)
+
+#define KORINA_REVID 0
+#define KORINA_CLASS_CODE 0
+#define KORINA_CNFG2 ((KORINA_CLASS_CODE<<8) | \
+ KORINA_REVID)
+
+#define KORINA_CACHE_LINE_SIZE 4
+#define KORINA_MASTER_LAT 0x3c
+#define KORINA_HEADER_TYPE 0
+#define KORINA_BIST 0
+
+#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
+ (KORINA_HEADER_TYPE<<16) | \
+ (KORINA_MASTER_LAT<<8) | \
+ KORINA_CACHE_LINE_SIZE )
+
+#define KORINA_BAR0 0x00000008 /* 128 MB Memory */
+#define KORINA_BAR1 0x18800001 /* 1 MB IO */
+#define KORINA_BAR2 0x18000001 /* 2 MB IO window for Korina
+ internal Registers */
+#define KORINA_BAR3 0x48000008 /* Spare 128 MB Memory */
+
+#define KORINA_CNFG4 KORINA_BAR0
+#define KORINA_CNFG5 KORINA_BAR1
+#define KORINA_CNFG6 KORINA_BAR2
+#define KORINA_CNFG7 KORINA_BAR3
+
+#define KORINA_SUBSYS_VENDOR_ID 0x011d
+#define KORINA_SUBSYSTEM_ID 0x0214
+#define KORINA_CNFG8 0
+#define KORINA_CNFG9 0
+#define KORINA_CNFG10 0
+#define KORINA_CNFG11 ((KORINA_SUBSYS_VENDOR_ID<<16) | \
+ KORINA_SUBSYSTEM_ID)
+#define KORINA_INT_LINE 1
+#define KORINA_INT_PIN 1
+#define KORINA_MIN_GNT 8
+#define KORINA_MAX_LAT 0x38
+#define KORINA_CNFG12 0
+#define KORINA_CNFG13 0
+#define KORINA_CNFG14 0
+#define KORINA_CNFG15 ((KORINA_MAX_LAT<<24) | \
+ (KORINA_MIN_GNT<<16) | \
+ (KORINA_INT_PIN<<8) | \
+ KORINA_INT_LINE)
+#define KORINA_RETRY_LIMIT 0x80
+#define KORINA_TRDY_LIMIT 0x80
+#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
+ KORINA_TRDY_LIMIT)
+#define PCI_PBAxC_R 0x0
+#define PCI_PBAxC_RL 0x1
+#define PCI_PBAxC_RM 0x2
+#define SIZE_SHFT 2
+
+#if defined(__MIPSEB__)
+#define KORINA_PBA0C ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
+ ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
+ PCIPBAC_pp_m | \
+ (SIZE_128MB<<SIZE_SHFT) | \
+ PCIPBAC_p_m)
+#else
+#define KORINA_PBA0C ( PCIPBAC_mrl_m | \
+ ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
+ PCIPBAC_pp_m | \
+ (SIZE_128MB<<SIZE_SHFT) | \
+ PCIPBAC_p_m)
+#endif
+#define KORINA_CNFG17 KORINA_PBA0C
+#define KORINA_PBA0M 0x0
+#define KORINA_CNFG18 KORINA_PBA0M
+
+#if defined(__MIPSEB__)
+#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
+ PCIPBAC_msi_m)
+#else
+#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | \
+ PCIPBAC_msi_m)
+#endif
+#define KORINA_CNFG19 KORINA_PBA1C
+#define KORINA_PBA1M 0x0
+#define KORINA_CNFG20 KORINA_PBA1M
+
+#if defined(__MIPSEB__)
+#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
+ PCIPBAC_msi_m)
+#else
+#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | \
+ PCIPBAC_msi_m)
+#endif
+#define KORINA_CNFG21 KORINA_PBA2C
+#define KORINA_PBA2M 0x18000000
+#define KORINA_CNFG22 KORINA_PBA2M
+#define KORINA_PBA3C 0
+#define KORINA_CNFG23 KORINA_PBA3C
+#define KORINA_PBA3M 0
+#define KORINA_CNFG24 KORINA_PBA3M
+
+
+
+#define PCITC_DTIMER_VAL 8
+#define PCITC_RTIMER_VAL 0x10
+
+
+
+
+#endif // __IDT_PCI_H__
+
+
+
--- /dev/null
+/*
+ * Copyright (C) 2004 IDT Inc.
+ * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef __MIPS_RB_H__
+#define __MIPS_RB_H__
+#include <linux/genhd.h>
+
+#define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(0x18000000))
+#define DEV0BASE 0x010000
+#define DEV0MASK 0x010004
+#define DEV0C 0x010008
+#define DEV0TC 0x01000C
+#define DEV1BASE 0x010010
+#define DEV1MASK 0x010014
+#define DEV1C 0x010018
+#define DEV1TC 0x01001C
+#define DEV2BASE 0x010020
+#define DEV2MASK 0x010024
+#define DEV2C 0x010028
+#define DEV2TC 0x01002C
+#define DEV3BASE 0x010030
+#define DEV3MASK 0x010034
+#define DEV3C 0x010038
+#define DEV3TC 0x01003C
+#define BTCS 0x010040
+#define BTCOMPARE 0x010044
+#define GPIOFUNC 0x050000
+#define GPIOCFG 0x050004
+#define GPIOD 0x050008
+#define GPIOILEVEL 0x05000C
+#define GPIOISTAT 0x050010
+#define GPIONMIEN 0x050014
+#define IMASK6 0x038038
+
+#define LO_WPX (1 << 0)
+#define LO_ALE (1 << 1)
+#define LO_CLE (1 << 2)
+#define LO_CEX (1 << 3)
+#define LO_FOFF (1 << 5)
+#define LO_SPICS (1 << 6)
+#define LO_ULED (1 << 7)
+
+typedef enum {
+ FUNC = 0x00,
+ CFG = 0x04,
+ DATA = 0x08,
+ ILEVEL = 0x0c,
+ ISTAT = 0x10,
+ NMIEN = 0x14
+} gpio_func;
+
+extern void changeLatchU5(unsigned char orMask, unsigned char nandMask);
+extern unsigned get434Reg(unsigned regOffs);
+extern void set434Reg(unsigned regOffs, unsigned bit, unsigned len, unsigned val);
+extern void gpio_set(gpio_func func, u32 mask, u32 value);
+extern u32 gpio_get(gpio_func func);
+
+#define get434Reg(x) (*(volatile unsigned *) (IDT434_REG_BASE + (x)))
+
+struct korina_device {
+ char *name;
+ unsigned char mac[6];
+ struct net_device *dev;
+};
+
+struct cf_device {
+ int gpio_pin;
+ void *dev;
+ struct gendisk *gd;
+};
+
+#endif
--- /dev/null
+/*
+ ***************************************************************************
+ * Definitions for IDT RC323434 CPU.
+ *
+ ****************************************************************************
+ * Kiran Rao
+ *
+ * Original form
+ ****************************************************************************
+ * P. Sadik Oct 08, 2003
+ *
+ * Started revision history
+ * Made IDT_BUS_FREQ a kernel configuration parameter
+ ****************************************************************************
+ * P. Sadik Oct 10, 2003
+ *
+ * Removed IDT_BUS_FREQ, since this parameter is no longer required. Instead
+ * idt_cpu_freq is used everywhere
+ ****************************************************************************
+ * P. Sadik Oct 20, 2003
+ *
+ * Removed RC32434_BASE_BAUD
+ ****************************************************************************
+*/
+#ifndef _RC32434_H_
+#define _RC32434_H_
+
+#include <linux/autoconf.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+
+#define RC32434_REG_BASE 0x18000000
+
+#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
+
+
+#define IDT_CLOCK_MULT 2
+#define MIPS_CPU_TIMER_IRQ 7
+/* Interrupt Controller */
+#define IC_GROUP0_PEND (RC32434_REG_BASE + 0x38000)
+#define IC_GROUP0_MASK (RC32434_REG_BASE + 0x38008)
+#define IC_GROUP_OFFSET 0x0C
+
+#define NUM_INTR_GROUPS 5
+/* 16550 UARTs */
+
+#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
+#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
+#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
+#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */
+#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
+
+
+#ifdef __MIPSEB__
+#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003)
+#else
+#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000)
+#endif
+
+#define RC32434_UART0_IRQ GROUP3_IRQ_BASE + 0
+// #define EB434_UART1_IRQ GROUP4_IRQ_BASE + 11
+
+#define local_readl(addr) __raw_readl(addr)
+#define local_writel(l,addr) __raw_writel(l,addr)
+
+/* cpu pipeline flush */
+static inline void rc32434_sync(void)
+{
+ __asm__ volatile ("sync");
+}
+
+static inline void rc32434_sync_udelay(int us)
+{
+ __asm__ volatile ("sync");
+ udelay(us);
+}
+
+static inline void rc32434_sync_delay(int ms)
+{
+ __asm__ volatile ("sync");
+ mdelay(ms);
+}
+
+/*
+ * C access to CLZ and CLO instructions
+ * (count leading zeroes/ones).
+ */
+static inline int rc32434_clz(unsigned long val)
+{
+ int ret;
+ __asm__ volatile (
+ ".set\tnoreorder\n\t"
+ ".set\tnoat\n\t"
+ ".set\tmips32\n\t"
+ "clz\t%0,%1\n\t"
+ ".set\tmips0\n\t"
+ ".set\tat\n\t"
+ ".set\treorder"
+ : "=r" (ret)
+ : "r" (val));
+
+ return ret;
+}
+static inline int rc32434_clo(unsigned long val)
+{
+ int ret;
+ __asm__ volatile (
+ ".set\tnoreorder\n\t"
+ ".set\tnoat\n\t"
+ ".set\tmips32\n\t"
+ "clo\t%0,%1\n\t"
+ ".set\tmips0\n\t"
+ ".set\tat\n\t"
+ ".set\treorder"
+ : "=r" (ret)
+ : "r" (val));
+
+ return ret;
+}
+
+#endif /* _RC32434_H_ */
--- /dev/null
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
+#define __ASM_MIPS_MACH_MIPS_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR 0
+#define R4600_V1_HIT_CACHEOP_WAR 0
+#define R4600_V2_HIT_CACHEOP_WAR 0
+#define R5432_CP0_INTERRUPT_WAR 0
+#define BCM1250_M3_WAR 0
+#define SIBYTE_1956_WAR 0
+#define MIPS4K_ICACHE_REFILL_WAR 1
+#define MIPS_CACHE_SYNC_WAR 0
+#define TX49XX_ICACHE_INDEX_INV_WAR 0
+#define RM9000_CDEX_SMP_WAR 0
+#define ICACHE_REFILLS_WORKAROUND_WAR 0
+#define R10000_LLSC_WAR 0
+#define MIPS34K_MISSED_ITLB_WAR 0
+
+#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
+++ /dev/null
-diff -urN linux-2.6.24.7/arch/mips/Kconfig linux-2.6.24.7.new/arch/mips/Kconfig
---- linux-2.6.24.7/arch/mips/Kconfig 2008-05-07 01:22:34.000000000 +0200
-+++ linux-2.6.24.7.new/arch/mips/Kconfig 2008-07-15 15:29:51.000000000 +0200
-@@ -687,6 +687,23 @@
- This enables support for the Wind River MIPS32 4KC PPMC evaluation
- board, which is based on GT64120 bridge chip.
-
-+config MIKROTIK_RB500
-+ bool "Support for RB5xx boards"
-+ select HW_HAS_PCI
-+ select CEVT_R4K
-+ select CSRC_R4K
-+ select IRQ_CPU
-+ select SYS_HAS_CPU_MIPS32_R1
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select SWAP_IO_SPACE
-+ select DMA_NONCOHERENT
-+ select GENERIC_GPIO
-+ help
-+ Support the Mikrotik(tm) Routerboard 500 series,
-+ such as the RB532.
-+
-+
- endchoice
-
- source "arch/mips/au1000/Kconfig"
-@@ -967,6 +982,7 @@
- default "4" if MACH_DECSTATION
- default "7" if SGI_IP27 || SNI_RM
- default "4" if PMC_MSP4200_EVAL
-+ default "4" if MIKROTIK_RB500
- default "5"
-
- config HAVE_STD_PC_SERIAL_PORT
-diff -urN linux-2.6.24.7/arch/mips/Makefile linux-2.6.24.7.new/arch/mips/Makefile
---- linux-2.6.24.7/arch/mips/Makefile 2008-07-15 15:27:55.000000000 +0200
-+++ linux-2.6.24.7.new/arch/mips/Makefile 2008-07-15 15:30:21.000000000 +0200
-@@ -297,6 +297,13 @@
- cflags-$(CONFIG_LEMOTE_FULONG) += -Iinclude/asm-mips/mach-lemote
-
- #
-+# Routerboard 532 board
-+#
-+core-$(CONFIG_MIKROTIK_RB500) += arch/mips/rb500/
-+cflags-$(CONFIG_MIKROTIK_RB500) += -Iinclude/asm-mips/rc32434
-+load-$(CONFIG_MIKROTIK_RB500) += 0xffffffff80101000
-+
-+#
- # For all MIPS, Inc. eval boards
- #
- core-$(CONFIG_MIPS_BOARDS_GEN) += arch/mips/mips-boards/generic/
-diff -urN linux-2.6.24.7/arch/mips/pci/Makefile linux-2.6.24.7.new/arch/mips/pci/Makefile
---- linux-2.6.24.7/arch/mips/pci/Makefile 2008-05-07 01:22:34.000000000 +0200
-+++ linux-2.6.24.7.new/arch/mips/pci/Makefile 2008-07-15 15:30:46.000000000 +0200
-@@ -48,3 +48,4 @@
- obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
- obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
- obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
-+obj-$(CONFIG_MIKROTIK_RB500) += pci-rc32434.o ops-rc32434.o fixup-rb500.o
-diff -urN linux-2.6.24.7/drivers/pci/Makefile linux-2.6.24.7.new/drivers/pci/Makefile
---- linux-2.6.24.7/drivers/pci/Makefile 2008-05-07 01:22:34.000000000 +0200
-+++ linux-2.6.24.7.new/drivers/pci/Makefile 2008-07-15 15:31:20.000000000 +0200
-@@ -35,6 +35,7 @@
- obj-$(CONFIG_PPC64) += setup-bus.o
- obj-$(CONFIG_MIPS) += setup-bus.o setup-irq.o
- obj-$(CONFIG_X86_VISWS) += setup-irq.o
-+obj-$(CONFIG_MIKROTIK_RB500) += setup-irq.o
-
- #
- # ACPI Related PCI FW Functions
-diff -urN linux-2.6.24.7/include/asm-mips/bootinfo.h linux-2.6.24.7.new/include/asm-mips/bootinfo.h
---- linux-2.6.24.7/include/asm-mips/bootinfo.h 2008-05-07 01:22:34.000000000 +0200
-+++ linux-2.6.24.7.new/include/asm-mips/bootinfo.h 2008-07-15 15:32:06.000000000 +0200
-@@ -198,6 +198,14 @@
- #define MACH_GROUP_BRCM 23 /* Broadcom */
- #define MACH_BCM47XX 1 /* Broadcom BCM47XX */
-
-+
-+/*
-+ * Valid machtype for group Mikrotik
-+ */
-+#define MACH_GROUP_MIKROTIK 29 /* Mikrotik Boards */
-+#define MACH_MIKROTIK_RB532 0 /* Mikrotik RouterBoard 532 */
-+#define MACH_MIKROTIK_RB532A 1 /* Mikrotik RouterBoard 532A */
-+
- #define CL_SIZE COMMAND_LINE_SIZE
-
- const char *get_system_type(void);
-diff -urN linux-2.6.24.7/include/asm-mips/cpu.h linux-2.6.24.7.new/include/asm-mips/cpu.h
---- linux-2.6.24.7/include/asm-mips/cpu.h 2008-05-07 01:22:34.000000000 +0200
-+++ linux-2.6.24.7.new/include/asm-mips/cpu.h 2008-07-15 15:32:22.000000000 +0200
-@@ -196,7 +196,7 @@
- */
- CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_74K, CPU_AU1000,
- CPU_AU1100, CPU_AU1200, CPU_AU1500, CPU_AU1550, CPU_PR4450,
-- CPU_BCM3302, CPU_BCM4710,
-+ CPU_BCM3302, CPU_BCM4710, CPU_RC32300,
-
- /*
- * MIPS64 class processors
+++ /dev/null
-Index: linux-2.6.23.17/drivers/net/Kconfig
-===================================================================
---- linux-2.6.23.17.orig/drivers/net/Kconfig
-+++ linux-2.6.23.17/drivers/net/Kconfig
-@@ -348,6 +348,13 @@ config AX88796
- AX88796 driver, using platform bus to provide
- chip detection and resources
-
-+config KORINA
-+ tristate "Korina Local Ethernet support"
-+ depends on NET_ETHERNET && ( IDT_EB434 || MIKROTIK_RB500)
-+ help
-+ IDT RC32434 has one local ethernet port. Say Y here to enable it.
-+ To compile this driver as a module, choose M here.
-+
- config MACE
- tristate "MACE (Power Mac ethernet) support"
- depends on PPC_PMAC && PPC32
-Index: linux-2.6.23.17/drivers/net/Makefile
-===================================================================
---- linux-2.6.23.17.orig/drivers/net/Makefile
-+++ linux-2.6.23.17/drivers/net/Makefile
-@@ -25,6 +25,8 @@ ucc_geth_driver-objs := ucc_geth.o ucc_g
- #
- obj-$(CONFIG_PLIP) += plip.o
-
-+obj-$(CONFIG_KORINA) += korina.o
-+
- obj-$(CONFIG_ROADRUNNER) += rrunner.o
-
- obj-$(CONFIG_HAPPYMEAL) += sunhme.o
+++ /dev/null
-Index: linux-2.6.23.17/drivers/block/Kconfig
-===================================================================
---- linux-2.6.23.17.orig/drivers/block/Kconfig
-+++ linux-2.6.23.17/drivers/block/Kconfig
-@@ -426,6 +426,14 @@ config SUNVDC
- Support for virtual disk devices as a client under Sun
- Logical Domains.
-
-+config BLK_DEV_CF_MIPS
-+ bool "CF slot of RB532 board"
-+ depends on MIKROTIK_RB500
-+ default y
-+ help
-+ The Routerboard 532 has a CF slot on it. Enable the special block
-+ device driver for it.
-+
- source "drivers/s390/block/Kconfig"
-
- config XILINX_SYSACE
-Index: linux-2.6.23.17/drivers/block/Makefile
-===================================================================
---- linux-2.6.23.17.orig/drivers/block/Makefile
-+++ linux-2.6.23.17/drivers/block/Makefile
-@@ -21,6 +21,7 @@ obj-$(CONFIG_BLK_DEV_DAC960) += DAC960.o
- obj-$(CONFIG_XILINX_SYSACE) += xsysace.o
- obj-$(CONFIG_CDROM_PKTCDVD) += pktcdvd.o
- obj-$(CONFIG_SUNVDC) += sunvdc.o
-+obj-$(CONFIG_BLK_DEV_CF_MIPS) += rb500/
-
- obj-$(CONFIG_BLK_DEV_UMEM) += umem.o
- obj-$(CONFIG_BLK_DEV_NBD) += nbd.o
+++ /dev/null
-Index: linux-2.6.23.17/arch/mips/kernel/head.S
-===================================================================
---- linux-2.6.23.17.orig/arch/mips/kernel/head.S
-+++ linux-2.6.23.17/arch/mips/kernel/head.S
-@@ -132,6 +132,10 @@
-
- j kernel_entry
- nop
-+
-+EXPORT(_image_cmdline)
-+ .ascii "CMDLINE:"
-+
- #ifndef CONFIG_NO_EXCEPT_FILL
- /*
- * Reserved space for exception handlers.
+++ /dev/null
-Index: linux-2.6.23.17/arch/mips/pci/pci.c
-===================================================================
---- linux-2.6.23.17.orig/arch/mips/pci/pci.c
-+++ linux-2.6.23.17/arch/mips/pci/pci.c
-@@ -64,8 +64,10 @@ pcibios_align_resource(void *data, struc
- /*
- * Put everything into 0x00-0xff region modulo 0x400
- */
-+#ifndef CONFIG_MIKROTIK_RB500
- if (start & 0x300)
- start = (start + 0x3ff) & ~0x3ff;
-+#endif
- } else if (res->flags & IORESOURCE_MEM) {
- /* Make sure we start at our min on all hoses */
- if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)
+++ /dev/null
-Index: linux-2.6.23.17/drivers/serial/8250.c
-===================================================================
---- linux-2.6.23.17.orig/drivers/serial/8250.c
-+++ linux-2.6.23.17/drivers/serial/8250.c
-@@ -433,6 +433,13 @@ serial_out(struct uart_8250_port *up, in
- default:
- outb(value, up->port.iobase + offset);
- }
-+
-+#if defined(CONFIG_IDT_EB434) || defined(CONFIG_MIKROTIK_RB500)
-+ __SLOW_DOWN_IO;
-+ __SLOW_DOWN_IO;
-+ __SLOW_DOWN_IO;
-+ __SLOW_DOWN_IO;
-+#endif
- }
-
- static void
+++ /dev/null
-Index: linux-2.6.23.17/drivers/net/via-rhine.c
-===================================================================
---- linux-2.6.23.17.orig/drivers/net/via-rhine.c
-+++ linux-2.6.23.17/drivers/net/via-rhine.c
-@@ -33,6 +33,8 @@
- #define DRV_VERSION "1.4.3"
- #define DRV_RELDATE "2007-03-06"
-
-+#define PKT_ALIGN 1
-+
-
- /* A few user-configurable values.
- These may be modified when a driver module is loaded. */
-@@ -40,6 +42,7 @@
- static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
- static int max_interrupt_work = 20;
-
-+#ifndef PKT_ALIGN
- /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
- Setting to > 1518 effectively disables this feature. */
- #if defined(__alpha__) || defined(__arm__) || defined(__hppa__) \
-@@ -49,6 +52,7 @@ static int rx_copybreak = 1518;
- #else
- static int rx_copybreak;
- #endif
-+#endif /* PKT_ALIGN */
-
- /* Work-around for broken BIOSes: they are unable to get the chip back out of
- power state D3 so PXE booting fails. bootparam(7): via-rhine.avoid_D3=1 */
-@@ -111,6 +115,7 @@ static const int multicast_filter_limit
- #include <asm/io.h>
- #include <asm/irq.h>
- #include <asm/uaccess.h>
-+#include <asm/unaligned.h>
- #include <linux/dmi.h>
-
- /* These identify the driver base version and may not be removed. */
-@@ -130,12 +135,14 @@ MODULE_LICENSE("GPL");
-
- module_param(max_interrupt_work, int, 0);
- module_param(debug, int, 0);
--module_param(rx_copybreak, int, 0);
- module_param(avoid_D3, bool, 0);
- MODULE_PARM_DESC(max_interrupt_work, "VIA Rhine maximum events handled per interrupt");
- MODULE_PARM_DESC(debug, "VIA Rhine debug level (0-7)");
--MODULE_PARM_DESC(rx_copybreak, "VIA Rhine copy breakpoint for copy-only-tiny-frames");
- MODULE_PARM_DESC(avoid_D3, "Avoid power state D3 (work-around for broken BIOSes)");
-+#ifndef PKT_ALIGN
-+module_param(rx_copybreak, int, 0);
-+MODULE_PARM_DESC(rx_copybreak, "VIA Rhine copy breakpoint for copy-only-tiny-frames");
-+#endif
-
- /*
- Theory of Operation
-@@ -927,7 +934,7 @@ static void alloc_rbufs(struct net_devic
-
- /* Fill in the Rx buffers. Handle allocation failure gracefully. */
- for (i = 0; i < RX_RING_SIZE; i++) {
-- struct sk_buff *skb = dev_alloc_skb(rp->rx_buf_sz);
-+ struct sk_buff *skb = dev_alloc_skb(rp->rx_buf_sz + 4);
- rp->rx_skbuff[i] = skb;
- if (skb == NULL)
- break;
-@@ -1484,7 +1491,9 @@ static int rhine_rx(struct net_device *d
- struct sk_buff *skb;
- /* Length should omit the CRC */
- int pkt_len = data_size - 4;
--
-+#ifdef PKT_ALIGN
-+ int i;
-+#else
- /* Check if the packet is long enough to accept without
- copying to a minimally-sized skbuff. */
- if (pkt_len < rx_copybreak &&
-@@ -1503,7 +1512,9 @@ static int rhine_rx(struct net_device *d
- rp->rx_skbuff_dma[entry],
- rp->rx_buf_sz,
- PCI_DMA_FROMDEVICE);
-- } else {
-+ } else
-+#endif
-+ {
- skb = rp->rx_skbuff[entry];
- if (skb == NULL) {
- printk(KERN_ERR "%s: Inconsistent Rx "
-@@ -1517,6 +1528,14 @@ static int rhine_rx(struct net_device *d
- rp->rx_skbuff_dma[entry],
- rp->rx_buf_sz,
- PCI_DMA_FROMDEVICE);
-+#ifdef PKT_ALIGN
-+ /* align the data to the ip header - should be faster than copying the entire packet */
-+ for (i = pkt_len - (pkt_len % 4); i >= 0; i -= 4) {
-+ put_unaligned(*((u32 *) (skb->data + i)), (u32 *) (skb->data + i + 2));
-+ }
-+ skb->data += 2;
-+ skb->tail += 2;
-+#endif
- }
- skb->protocol = eth_type_trans(skb, dev);
- #ifdef CONFIG_VIA_RHINE_NAPI
+++ /dev/null
-diff -urN linux-2.6.24.7/drivers/leds/Kconfig linux-2.6.24.7.new/drivers/leds/Kconfig
---- linux-2.6.24.7/drivers/leds/Kconfig 2008-07-15 15:27:55.000000000 +0200
-+++ linux-2.6.24.7.new/drivers/leds/Kconfig 2008-07-15 15:35:24.000000000 +0200
-@@ -120,6 +120,12 @@
- help
- This option enables support for the CM-X270 LEDs.
-
-+config LEDS_RB500
-+ tristate "LED Support for RB5xx boards"
-+ depends on LEDS_CLASS && MIKROTIK_RB500
-+ help
-+ This option enables support for the yellow user LED on RB5xx boards.
-+
- comment "LED Triggers"
-
- config LEDS_TRIGGERS
-diff -urN linux-2.6.24.7/drivers/leds/Makefile linux-2.6.24.7.new/drivers/leds/Makefile
---- linux-2.6.24.7/drivers/leds/Makefile 2008-07-15 15:27:55.000000000 +0200
-+++ linux-2.6.24.7.new/drivers/leds/Makefile 2008-07-15 15:35:38.000000000 +0200
-@@ -20,6 +20,7 @@
- obj-$(CONFIG_LEDS_COBALT_RAQ) += leds-cobalt-raq.o
- obj-$(CONFIG_LEDS_GPIO) += leds-gpio.o
- obj-$(CONFIG_LEDS_CM_X270) += leds-cm-x270.o
-+obj-$(CONFIG_LEDS_RB500) += leds-rb500.o
-
- # LED Triggers
- obj-$(CONFIG_LEDS_TRIGGER_TIMER) += ledtrig-timer.o
+++ /dev/null
-diff -urN linux-2.6.24.7/arch/mips/kernel/time.c linux-2.6.24.7.new/arch/mips/kernel/time.c
---- linux-2.6.24.7/arch/mips/kernel/time.c 2008-05-07 01:22:34.000000000 +0200
-+++ linux-2.6.24.7.new/arch/mips/kernel/time.c 2008-07-15 15:38:33.000000000 +0200
-@@ -75,6 +75,7 @@
- */
-
- unsigned int mips_hpt_frequency;
-+EXPORT_SYMBOL(mips_hpt_frequency);
-
- void __init clocksource_set_clock(struct clocksource *cs, unsigned int clock)
- {
-diff -urN linux-2.6.24.7/drivers/watchdog/Kconfig linux-2.6.24.7.new/drivers/watchdog/Kconfig
---- linux-2.6.24.7/drivers/watchdog/Kconfig 2008-05-07 01:22:34.000000000 +0200
-+++ linux-2.6.24.7.new/drivers/watchdog/Kconfig 2008-07-15 15:39:24.000000000 +0200
-@@ -639,6 +639,18 @@
- help
- Hardware driver for the TI AR7 Watchdog Timer.
-
-+config RC32434_WDT
-+ tristate "IDT Interprise 79RC32434 SoC hardware watchdog"
-+ depends on WATCHDOG && MIKROTIK_RB500
-+ help
-+ This is a driver for hardware watchdog integrated in IDT Interprise
-+ 79RC32434 SoC. This watchdog simply watches your kernel to make sure
-+ it doesn't freeze, and if it does, it reboots your computer after a
-+ certain amount of time.
-+
-+ To compile this driver as a module, choose M here: the module will be
-+ called rc32434_wdt.
-+
- # PARISC Architecture
-
- # POWERPC Architecture
+++ /dev/null
-diff -urN linux-2.6.24.7/arch/mips/lib/iomap-pci.c linux-2.6.24.7.new/arch/mips/lib/iomap-pci.c
---- linux-2.6.24.7/arch/mips/lib/iomap-pci.c 2008-05-07 01:22:34.000000000 +0200
-+++ linux-2.6.24.7.new/arch/mips/lib/iomap-pci.c 2008-07-15 16:24:22.000000000 +0200
-@@ -32,7 +32,7 @@
- "report it to linux-mips@linux-mips.org or your "
- "vendor.\n", name);
- #ifdef CONFIG_PCI_DOMAINS
-- panic("To avoid data corruption io_map_base MUST be set with "
-+ printk(KERN_WARNING "To avoid data corruption io_map_base MUST be set with "
- "multiple PCI domains.");
- #endif
- }
--- /dev/null
+diff -urN linux-2.6.24.7/arch/mips/Kconfig linux-2.6.24.7.new/arch/mips/Kconfig
+--- linux-2.6.24.7/arch/mips/Kconfig 2008-05-07 01:22:34.000000000 +0200
++++ linux-2.6.24.7.new/arch/mips/Kconfig 2008-07-15 15:29:51.000000000 +0200
+@@ -687,6 +687,23 @@
+ This enables support for the Wind River MIPS32 4KC PPMC evaluation
+ board, which is based on GT64120 bridge chip.
+
++config MIKROTIK_RB500
++ bool "Support for RB5xx boards"
++ select HW_HAS_PCI
++ select CEVT_R4K
++ select CSRC_R4K
++ select IRQ_CPU
++ select SYS_HAS_CPU_MIPS32_R1
++ select SYS_SUPPORTS_LITTLE_ENDIAN
++ select SYS_SUPPORTS_32BIT_KERNEL
++ select SWAP_IO_SPACE
++ select DMA_NONCOHERENT
++ select GENERIC_GPIO
++ help
++ Support the Mikrotik(tm) Routerboard 500 series,
++ such as the RB532.
++
++
+ endchoice
+
+ source "arch/mips/au1000/Kconfig"
+@@ -967,6 +982,7 @@
+ default "4" if MACH_DECSTATION
+ default "7" if SGI_IP27 || SNI_RM
+ default "4" if PMC_MSP4200_EVAL
++ default "4" if MIKROTIK_RB500
+ default "5"
+
+ config HAVE_STD_PC_SERIAL_PORT
+diff -urN linux-2.6.24.7/arch/mips/Makefile linux-2.6.24.7.new/arch/mips/Makefile
+--- linux-2.6.24.7/arch/mips/Makefile 2008-07-15 15:27:55.000000000 +0200
++++ linux-2.6.24.7.new/arch/mips/Makefile 2008-07-15 15:30:21.000000000 +0200
+@@ -297,6 +297,13 @@
+ cflags-$(CONFIG_LEMOTE_FULONG) += -Iinclude/asm-mips/mach-lemote
+
+ #
++# Routerboard 532 board
++#
++core-$(CONFIG_MIKROTIK_RB500) += arch/mips/rb500/
++cflags-$(CONFIG_MIKROTIK_RB500) += -Iinclude/asm-mips/rc32434
++load-$(CONFIG_MIKROTIK_RB500) += 0xffffffff80101000
++
++#
+ # For all MIPS, Inc. eval boards
+ #
+ core-$(CONFIG_MIPS_BOARDS_GEN) += arch/mips/mips-boards/generic/
+diff -urN linux-2.6.24.7/arch/mips/pci/Makefile linux-2.6.24.7.new/arch/mips/pci/Makefile
+--- linux-2.6.24.7/arch/mips/pci/Makefile 2008-05-07 01:22:34.000000000 +0200
++++ linux-2.6.24.7.new/arch/mips/pci/Makefile 2008-07-15 15:30:46.000000000 +0200
+@@ -48,3 +48,4 @@
+ obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
+ obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
+ obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
++obj-$(CONFIG_MIKROTIK_RB500) += pci-rc32434.o ops-rc32434.o fixup-rb500.o
+diff -urN linux-2.6.24.7/drivers/pci/Makefile linux-2.6.24.7.new/drivers/pci/Makefile
+--- linux-2.6.24.7/drivers/pci/Makefile 2008-05-07 01:22:34.000000000 +0200
++++ linux-2.6.24.7.new/drivers/pci/Makefile 2008-07-15 15:31:20.000000000 +0200
+@@ -35,6 +35,7 @@
+ obj-$(CONFIG_PPC64) += setup-bus.o
+ obj-$(CONFIG_MIPS) += setup-bus.o setup-irq.o
+ obj-$(CONFIG_X86_VISWS) += setup-irq.o
++obj-$(CONFIG_MIKROTIK_RB500) += setup-irq.o
+
+ #
+ # ACPI Related PCI FW Functions
+diff -urN linux-2.6.24.7/include/asm-mips/bootinfo.h linux-2.6.24.7.new/include/asm-mips/bootinfo.h
+--- linux-2.6.24.7/include/asm-mips/bootinfo.h 2008-05-07 01:22:34.000000000 +0200
++++ linux-2.6.24.7.new/include/asm-mips/bootinfo.h 2008-07-15 15:32:06.000000000 +0200
+@@ -198,6 +198,14 @@
+ #define MACH_GROUP_BRCM 23 /* Broadcom */
+ #define MACH_BCM47XX 1 /* Broadcom BCM47XX */
+
++
++/*
++ * Valid machtype for group Mikrotik
++ */
++#define MACH_GROUP_MIKROTIK 29 /* Mikrotik Boards */
++#define MACH_MIKROTIK_RB532 0 /* Mikrotik RouterBoard 532 */
++#define MACH_MIKROTIK_RB532A 1 /* Mikrotik RouterBoard 532A */
++
+ #define CL_SIZE COMMAND_LINE_SIZE
+
+ const char *get_system_type(void);
+diff -urN linux-2.6.24.7/include/asm-mips/cpu.h linux-2.6.24.7.new/include/asm-mips/cpu.h
+--- linux-2.6.24.7/include/asm-mips/cpu.h 2008-05-07 01:22:34.000000000 +0200
++++ linux-2.6.24.7.new/include/asm-mips/cpu.h 2008-07-15 15:32:22.000000000 +0200
+@@ -196,7 +196,7 @@
+ */
+ CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_74K, CPU_AU1000,
+ CPU_AU1100, CPU_AU1200, CPU_AU1500, CPU_AU1550, CPU_PR4450,
+- CPU_BCM3302, CPU_BCM4710,
++ CPU_BCM3302, CPU_BCM4710, CPU_RC32300,
+
+ /*
+ * MIPS64 class processors
--- /dev/null
+Index: linux-2.6.23.17/drivers/net/Kconfig
+===================================================================
+--- linux-2.6.23.17.orig/drivers/net/Kconfig
++++ linux-2.6.23.17/drivers/net/Kconfig
+@@ -348,6 +348,13 @@ config AX88796
+ AX88796 driver, using platform bus to provide
+ chip detection and resources
+
++config KORINA
++ tristate "Korina Local Ethernet support"
++ depends on NET_ETHERNET && ( IDT_EB434 || MIKROTIK_RB500)
++ help
++ IDT RC32434 has one local ethernet port. Say Y here to enable it.
++ To compile this driver as a module, choose M here.
++
+ config MACE
+ tristate "MACE (Power Mac ethernet) support"
+ depends on PPC_PMAC && PPC32
+Index: linux-2.6.23.17/drivers/net/Makefile
+===================================================================
+--- linux-2.6.23.17.orig/drivers/net/Makefile
++++ linux-2.6.23.17/drivers/net/Makefile
+@@ -25,6 +25,8 @@ ucc_geth_driver-objs := ucc_geth.o ucc_g
+ #
+ obj-$(CONFIG_PLIP) += plip.o
+
++obj-$(CONFIG_KORINA) += korina.o
++
+ obj-$(CONFIG_ROADRUNNER) += rrunner.o
+
+ obj-$(CONFIG_HAPPYMEAL) += sunhme.o
--- /dev/null
+Index: linux-2.6.23.17/drivers/block/Kconfig
+===================================================================
+--- linux-2.6.23.17.orig/drivers/block/Kconfig
++++ linux-2.6.23.17/drivers/block/Kconfig
+@@ -426,6 +426,14 @@ config SUNVDC
+ Support for virtual disk devices as a client under Sun
+ Logical Domains.
+
++config BLK_DEV_CF_MIPS
++ bool "CF slot of RB532 board"
++ depends on MIKROTIK_RB500
++ default y
++ help
++ The Routerboard 532 has a CF slot on it. Enable the special block
++ device driver for it.
++
+ source "drivers/s390/block/Kconfig"
+
+ config XILINX_SYSACE
+Index: linux-2.6.23.17/drivers/block/Makefile
+===================================================================
+--- linux-2.6.23.17.orig/drivers/block/Makefile
++++ linux-2.6.23.17/drivers/block/Makefile
+@@ -21,6 +21,7 @@ obj-$(CONFIG_BLK_DEV_DAC960) += DAC960.o
+ obj-$(CONFIG_XILINX_SYSACE) += xsysace.o
+ obj-$(CONFIG_CDROM_PKTCDVD) += pktcdvd.o
+ obj-$(CONFIG_SUNVDC) += sunvdc.o
++obj-$(CONFIG_BLK_DEV_CF_MIPS) += rb500/
+
+ obj-$(CONFIG_BLK_DEV_UMEM) += umem.o
+ obj-$(CONFIG_BLK_DEV_NBD) += nbd.o
--- /dev/null
+Index: linux-2.6.23.17/arch/mips/kernel/head.S
+===================================================================
+--- linux-2.6.23.17.orig/arch/mips/kernel/head.S
++++ linux-2.6.23.17/arch/mips/kernel/head.S
+@@ -132,6 +132,10 @@
+
+ j kernel_entry
+ nop
++
++EXPORT(_image_cmdline)
++ .ascii "CMDLINE:"
++
+ #ifndef CONFIG_NO_EXCEPT_FILL
+ /*
+ * Reserved space for exception handlers.
--- /dev/null
+Index: linux-2.6.23.17/arch/mips/pci/pci.c
+===================================================================
+--- linux-2.6.23.17.orig/arch/mips/pci/pci.c
++++ linux-2.6.23.17/arch/mips/pci/pci.c
+@@ -64,8 +64,10 @@ pcibios_align_resource(void *data, struc
+ /*
+ * Put everything into 0x00-0xff region modulo 0x400
+ */
++#ifndef CONFIG_MIKROTIK_RB500
+ if (start & 0x300)
+ start = (start + 0x3ff) & ~0x3ff;
++#endif
+ } else if (res->flags & IORESOURCE_MEM) {
+ /* Make sure we start at our min on all hoses */
+ if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)
--- /dev/null
+Index: linux-2.6.23.17/drivers/serial/8250.c
+===================================================================
+--- linux-2.6.23.17.orig/drivers/serial/8250.c
++++ linux-2.6.23.17/drivers/serial/8250.c
+@@ -433,6 +433,13 @@ serial_out(struct uart_8250_port *up, in
+ default:
+ outb(value, up->port.iobase + offset);
+ }
++
++#if defined(CONFIG_IDT_EB434) || defined(CONFIG_MIKROTIK_RB500)
++ __SLOW_DOWN_IO;
++ __SLOW_DOWN_IO;
++ __SLOW_DOWN_IO;
++ __SLOW_DOWN_IO;
++#endif
+ }
+
+ static void
--- /dev/null
+Index: linux-2.6.23.17/drivers/net/via-rhine.c
+===================================================================
+--- linux-2.6.23.17.orig/drivers/net/via-rhine.c
++++ linux-2.6.23.17/drivers/net/via-rhine.c
+@@ -33,6 +33,8 @@
+ #define DRV_VERSION "1.4.3"
+ #define DRV_RELDATE "2007-03-06"
+
++#define PKT_ALIGN 1
++
+
+ /* A few user-configurable values.
+ These may be modified when a driver module is loaded. */
+@@ -40,6 +42,7 @@
+ static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
+ static int max_interrupt_work = 20;
+
++#ifndef PKT_ALIGN
+ /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
+ Setting to > 1518 effectively disables this feature. */
+ #if defined(__alpha__) || defined(__arm__) || defined(__hppa__) \
+@@ -49,6 +52,7 @@ static int rx_copybreak = 1518;
+ #else
+ static int rx_copybreak;
+ #endif
++#endif /* PKT_ALIGN */
+
+ /* Work-around for broken BIOSes: they are unable to get the chip back out of
+ power state D3 so PXE booting fails. bootparam(7): via-rhine.avoid_D3=1 */
+@@ -111,6 +115,7 @@ static const int multicast_filter_limit
+ #include <asm/io.h>
+ #include <asm/irq.h>
+ #include <asm/uaccess.h>
++#include <asm/unaligned.h>
+ #include <linux/dmi.h>
+
+ /* These identify the driver base version and may not be removed. */
+@@ -130,12 +135,14 @@ MODULE_LICENSE("GPL");
+
+ module_param(max_interrupt_work, int, 0);
+ module_param(debug, int, 0);
+-module_param(rx_copybreak, int, 0);
+ module_param(avoid_D3, bool, 0);
+ MODULE_PARM_DESC(max_interrupt_work, "VIA Rhine maximum events handled per interrupt");
+ MODULE_PARM_DESC(debug, "VIA Rhine debug level (0-7)");
+-MODULE_PARM_DESC(rx_copybreak, "VIA Rhine copy breakpoint for copy-only-tiny-frames");
+ MODULE_PARM_DESC(avoid_D3, "Avoid power state D3 (work-around for broken BIOSes)");
++#ifndef PKT_ALIGN
++module_param(rx_copybreak, int, 0);
++MODULE_PARM_DESC(rx_copybreak, "VIA Rhine copy breakpoint for copy-only-tiny-frames");
++#endif
+
+ /*
+ Theory of Operation
+@@ -927,7 +934,7 @@ static void alloc_rbufs(struct net_devic
+
+ /* Fill in the Rx buffers. Handle allocation failure gracefully. */
+ for (i = 0; i < RX_RING_SIZE; i++) {
+- struct sk_buff *skb = dev_alloc_skb(rp->rx_buf_sz);
++ struct sk_buff *skb = dev_alloc_skb(rp->rx_buf_sz + 4);
+ rp->rx_skbuff[i] = skb;
+ if (skb == NULL)
+ break;
+@@ -1484,7 +1491,9 @@ static int rhine_rx(struct net_device *d
+ struct sk_buff *skb;
+ /* Length should omit the CRC */
+ int pkt_len = data_size - 4;
+-
++#ifdef PKT_ALIGN
++ int i;
++#else
+ /* Check if the packet is long enough to accept without
+ copying to a minimally-sized skbuff. */
+ if (pkt_len < rx_copybreak &&
+@@ -1503,7 +1512,9 @@ static int rhine_rx(struct net_device *d
+ rp->rx_skbuff_dma[entry],
+ rp->rx_buf_sz,
+ PCI_DMA_FROMDEVICE);
+- } else {
++ } else
++#endif
++ {
+ skb = rp->rx_skbuff[entry];
+ if (skb == NULL) {
+ printk(KERN_ERR "%s: Inconsistent Rx "
+@@ -1517,6 +1528,14 @@ static int rhine_rx(struct net_device *d
+ rp->rx_skbuff_dma[entry],
+ rp->rx_buf_sz,
+ PCI_DMA_FROMDEVICE);
++#ifdef PKT_ALIGN
++ /* align the data to the ip header - should be faster than copying the entire packet */
++ for (i = pkt_len - (pkt_len % 4); i >= 0; i -= 4) {
++ put_unaligned(*((u32 *) (skb->data + i)), (u32 *) (skb->data + i + 2));
++ }
++ skb->data += 2;
++ skb->tail += 2;
++#endif
+ }
+ skb->protocol = eth_type_trans(skb, dev);
+ #ifdef CONFIG_VIA_RHINE_NAPI
--- /dev/null
+diff -urN linux-2.6.24.7/drivers/leds/Kconfig linux-2.6.24.7.new/drivers/leds/Kconfig
+--- linux-2.6.24.7/drivers/leds/Kconfig 2008-07-15 15:27:55.000000000 +0200
++++ linux-2.6.24.7.new/drivers/leds/Kconfig 2008-07-15 15:35:24.000000000 +0200
+@@ -120,6 +120,12 @@
+ help
+ This option enables support for the CM-X270 LEDs.
+
++config LEDS_RB500
++ tristate "LED Support for RB5xx boards"
++ depends on LEDS_CLASS && MIKROTIK_RB500
++ help
++ This option enables support for the yellow user LED on RB5xx boards.
++
+ comment "LED Triggers"
+
+ config LEDS_TRIGGERS
+diff -urN linux-2.6.24.7/drivers/leds/Makefile linux-2.6.24.7.new/drivers/leds/Makefile
+--- linux-2.6.24.7/drivers/leds/Makefile 2008-07-15 15:27:55.000000000 +0200
++++ linux-2.6.24.7.new/drivers/leds/Makefile 2008-07-15 15:35:38.000000000 +0200
+@@ -20,6 +20,7 @@
+ obj-$(CONFIG_LEDS_COBALT_RAQ) += leds-cobalt-raq.o
+ obj-$(CONFIG_LEDS_GPIO) += leds-gpio.o
+ obj-$(CONFIG_LEDS_CM_X270) += leds-cm-x270.o
++obj-$(CONFIG_LEDS_RB500) += leds-rb500.o
+
+ # LED Triggers
+ obj-$(CONFIG_LEDS_TRIGGER_TIMER) += ledtrig-timer.o
--- /dev/null
+diff -urN linux-2.6.24.7/arch/mips/kernel/time.c linux-2.6.24.7.new/arch/mips/kernel/time.c
+--- linux-2.6.24.7/arch/mips/kernel/time.c 2008-05-07 01:22:34.000000000 +0200
++++ linux-2.6.24.7.new/arch/mips/kernel/time.c 2008-07-15 15:38:33.000000000 +0200
+@@ -75,6 +75,7 @@
+ */
+
+ unsigned int mips_hpt_frequency;
++EXPORT_SYMBOL(mips_hpt_frequency);
+
+ void __init clocksource_set_clock(struct clocksource *cs, unsigned int clock)
+ {
+diff -urN linux-2.6.24.7/drivers/watchdog/Kconfig linux-2.6.24.7.new/drivers/watchdog/Kconfig
+--- linux-2.6.24.7/drivers/watchdog/Kconfig 2008-05-07 01:22:34.000000000 +0200
++++ linux-2.6.24.7.new/drivers/watchdog/Kconfig 2008-07-15 15:39:24.000000000 +0200
+@@ -639,6 +639,18 @@
+ help
+ Hardware driver for the TI AR7 Watchdog Timer.
+
++config RC32434_WDT
++ tristate "IDT Interprise 79RC32434 SoC hardware watchdog"
++ depends on WATCHDOG && MIKROTIK_RB500
++ help
++ This is a driver for hardware watchdog integrated in IDT Interprise
++ 79RC32434 SoC. This watchdog simply watches your kernel to make sure
++ it doesn't freeze, and if it does, it reboots your computer after a
++ certain amount of time.
++
++ To compile this driver as a module, choose M here: the module will be
++ called rc32434_wdt.
++
+ # PARISC Architecture
+
+ # POWERPC Architecture
--- /dev/null
+diff -urN linux-2.6.24.7/arch/mips/lib/iomap-pci.c linux-2.6.24.7.new/arch/mips/lib/iomap-pci.c
+--- linux-2.6.24.7/arch/mips/lib/iomap-pci.c 2008-05-07 01:22:34.000000000 +0200
++++ linux-2.6.24.7.new/arch/mips/lib/iomap-pci.c 2008-07-15 16:24:22.000000000 +0200
+@@ -32,7 +32,7 @@
+ "report it to linux-mips@linux-mips.org or your "
+ "vendor.\n", name);
+ #ifdef CONFIG_PCI_DOMAINS
+- panic("To avoid data corruption io_map_base MUST be set with "
++ printk(KERN_WARNING "To avoid data corruption io_map_base MUST be set with "
+ "multiple PCI domains.");
+ #endif
+ }
+++ /dev/null
-# CONFIG_60XX_WDT is not set
-# CONFIG_64BIT is not set
-# CONFIG_8139TOO is not set
-# CONFIG_ACQUIRE_WDT is not set
-# CONFIG_ADVANTECH_WDT is not set
-# CONFIG_AGP is not set
-# CONFIG_ALIM1535_WDT is not set
-# CONFIG_ALIM7101_WDT is not set
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_ARCH_MAY_HAVE_PC_FDC=y
-CONFIG_ARCH_POPULATES_NODE_MAP=y
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-CONFIG_ARCH_SUPPORTS_OPROFILE=y
-CONFIG_ATA=m
-# CONFIG_ATA_NONSTANDARD is not set
-CONFIG_ATA_PIIX=m
-# CONFIG_AUDIT_ARCH is not set
-CONFIG_BASE_SMALL=0
-CONFIG_BINFMT_AOUT=m
-CONFIG_BINFMT_MISC=m
-CONFIG_BITREVERSE=y
-CONFIG_BLK_DEV_IDE=m
-CONFIG_BLK_DEV_IDEDISK=m
-# CONFIG_BLK_DEV_IDEDMA is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BOUNCE=y
-# CONFIG_BROADCOM_PHY is not set
-CONFIG_CLOCKSOURCE_WATCHDOG=y
-# CONFIG_COMPAT_VDSO is not set
-# CONFIG_CPU5_WDT is not set
-# CONFIG_CPU_FREQ is not set
-# CONFIG_CPU_IDLE is not set
-CONFIG_CRYPTO_AES_586=m
-CONFIG_CRYPTO_TWOFISH_586=m
-# CONFIG_CS5535_GPIO is not set
-# CONFIG_DCDBAS is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEFAULT_CFQ=y
-# CONFIG_DEFAULT_DEADLINE is not set
-CONFIG_DEFAULT_IOSCHED="cfq"
-# CONFIG_DELL_RBU is not set
-CONFIG_DEVPORT=y
-# CONFIG_DMADEVICES is not set
-CONFIG_DMI=y
-CONFIG_DMIID=y
-CONFIG_DOUBLEFAULT=y
-# CONFIG_E100 is not set
-CONFIG_EARLY_PRINTK=y
-# CONFIG_EDAC is not set
-# CONFIG_EDD is not set
-# CONFIG_EUROTECH_WDT is not set
-# CONFIG_FIXED_PHY is not set
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FS_POSIX_ACL=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-# CONFIG_GENERIC_CPU is not set
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_GENERIC_ISA_DMA=y
-# CONFIG_GENERIC_TIME_VSYSCALL is not set
-# CONFIG_GEN_RTC is not set
-# CONFIG_HANGCHECK_TIMER is not set
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HIBERNATION_UP_POSSIBLE=y
-CONFIG_HID=m
-CONFIG_HID_SUPPORT=y
-# CONFIG_HIGHMEM4G is not set
-# CONFIG_HIGHMEM64G is not set
-# CONFIG_HIGH_RES_TIMERS is not set
-# CONFIG_HPET_TIMER is not set
-CONFIG_HUGETLBFS=y
-CONFIG_HUGETLB_PAGE=y
-CONFIG_HW_RANDOM=y
-# CONFIG_HW_RANDOM_AMD is not set
-# CONFIG_HW_RANDOM_GEODE is not set
-# CONFIG_HW_RANDOM_INTEL is not set
-# CONFIG_HW_RANDOM_VIA is not set
-CONFIG_HZ=250
-# CONFIG_HZ_100 is not set
-CONFIG_HZ_250=y
-CONFIG_I2C=m
-# CONFIG_I2C_ALGOBIT is not set
-CONFIG_I2C_BOARDINFO=y
-# CONFIG_I6300ESB_WDT is not set
-# CONFIG_I8K is not set
-# CONFIG_IB700_WDT is not set
-# CONFIG_IBMASR is not set
-# CONFIG_IBM_ASM is not set
-# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_IBM_NEW_EMAC_RGMII is not set
-# CONFIG_IBM_NEW_EMAC_TAH is not set
-# CONFIG_IBM_NEW_EMAC_ZMII is not set
-CONFIG_ICPLUS_PHY=y
-CONFIG_IDE=m
-# CONFIG_IDEPCI_PCIBUS_ORDER is not set
-CONFIG_IDE_ARCH_OBSOLETE_INIT=y
-# CONFIG_IDE_ARM is not set
-# CONFIG_IDE_GENERIC is not set
-# CONFIG_IDE_PROC_FS is not set
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=m
-# CONFIG_INPUT_GPIO_BUTTONS is not set
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_YEALINK=m
-CONFIG_INSTRUMENTATION=y
-CONFIG_IOSCHED_CFQ=y
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_ISA is not set
-CONFIG_ISA_DMA_API=y
-# CONFIG_IT8712F_WDT is not set
-# CONFIG_ITCO_WDT is not set
-CONFIG_JFS_FS=m
-CONFIG_KEXEC=y
-CONFIG_KTIME_SCALAR=y
-# CONFIG_KVM is not set
-CONFIG_LBD=y
-CONFIG_LEDS_GPIO=y
-# CONFIG_LGUEST is not set
-CONFIG_LSF=y
-# CONFIG_M386 is not set
-CONFIG_M486=y
-# CONFIG_M586 is not set
-# CONFIG_M586MMX is not set
-# CONFIG_M586TSC is not set
-# CONFIG_M686 is not set
-# CONFIG_MACHZ_WDT is not set
-# CONFIG_MACINTOSH_DRIVERS is not set
-# CONFIG_MARKERS is not set
-CONFIG_MATH_EMULATION=y
-# CONFIG_MCA is not set
-# CONFIG_MCORE2 is not set
-# CONFIG_MCRUSOE is not set
-# CONFIG_MCYRIXIII is not set
-# CONFIG_MDIO_BITBANG is not set
-# CONFIG_MEFFICEON is not set
-# CONFIG_MGEODEGX1 is not set
-# CONFIG_MGEODE_LX is not set
-# CONFIG_MICROCODE is not set
-# CONFIG_MK6 is not set
-# CONFIG_MK7 is not set
-# CONFIG_MK8 is not set
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_MPENTIUM4 is not set
-# CONFIG_MPENTIUMII is not set
-# CONFIG_MPENTIUMIII is not set
-# CONFIG_MPENTIUMM is not set
-# CONFIG_MPSC is not set
-CONFIG_MTD=y
-# CONFIG_MTD_ABSENT is not set
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_MTD_BLOCK2MTD is not set
-CONFIG_MTD_CFI=y
-# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-# CONFIG_MTD_CFI_INTELEXT is not set
-# CONFIG_MTD_CFI_STAA is not set
-CONFIG_MTD_CFI_UTIL=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-CONFIG_MTD_CONCAT=y
-# CONFIG_MTD_DEBUG is not set
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-CONFIG_MTD_GEN_PROBE=y
-# CONFIG_MTD_JEDECPROBE is not set
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_NETSC520 is not set
-# CONFIG_MTD_ONENAND is not set
-CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_PHYSMAP is not set
-# CONFIG_MTD_PLATRAM is not set
-# CONFIG_MTD_PMC551 is not set
-# CONFIG_MTD_PNC2000 is not set
-# CONFIG_MTD_RAM is not set
-CONFIG_MTD_RDC3210=y
-CONFIG_MTD_RDC3210_ALLOW_JFFS2=y
-CONFIG_MTD_RDC3210_BUSWIDTH=2
-# CONFIG_MTD_RDC3210_FACTORY_PRESENT is not set
-CONFIG_MTD_RDC3210_SIZE=0x400000
-# CONFIG_MTD_RDC3210_STATIC_MAP is not set
-# CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_SC520CDP is not set
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_TS5500 is not set
-# CONFIG_MTRR is not set
-# CONFIG_MVIAC3_2 is not set
-# CONFIG_MVIAC7 is not set
-# CONFIG_MWINCHIP2 is not set
-# CONFIG_MWINCHIP3D is not set
-# CONFIG_MWINCHIPC6 is not set
-# CONFIG_NATSEMI is not set
-# CONFIG_NE2K_PCI is not set
-# CONFIG_NET_VENDOR_3COM is not set
-CONFIG_NLS_ISO8859_2=m
-CONFIG_NOHIGHMEM=y
-CONFIG_NO_HZ=y
-CONFIG_NR_QUICK=1
-# CONFIG_NSC_GPIO is not set
-CONFIG_NVRAM=y
-CONFIG_PAGE_OFFSET=0xC0000000
-# CONFIG_PARAVIRT_GUEST is not set
-CONFIG_PATA_ARTOP=m
-# CONFIG_PATA_CS5536 is not set
-# CONFIG_PC8736x_GPIO is not set
-# CONFIG_PC87413_WDT is not set
-CONFIG_PCCARD=m
-CONFIG_PCCARD_NONSTATIC=m
-CONFIG_PCI=y
-# CONFIG_PCIEPORTBUS is not set
-# CONFIG_PCIPCWATCHDOG is not set
-CONFIG_PCI_BIOS=y
-CONFIG_PCI_DIRECT=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_GOANY=y
-# CONFIG_PCI_GOBIOS is not set
-# CONFIG_PCI_GODIRECT is not set
-# CONFIG_PCI_GOMMCONFIG is not set
-CONFIG_PCMCIA=m
-CONFIG_PHYLIB=y
-CONFIG_PHYSICAL_ALIGN=0x100000
-CONFIG_PHYSICAL_START=0x100000
-# CONFIG_QSEMI_PHY is not set
-CONFIG_QUICKLIST=y
-CONFIG_R6040=m
-# CONFIG_R6040_NAPI is not set
-# CONFIG_RELOCATABLE is not set
-# CONFIG_RTC is not set
-# CONFIG_RWSEM_GENERIC_SPINLOCK is not set
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-# CONFIG_SBC7240_WDT is not set
-# CONFIG_SBC8360_WDT is not set
-# CONFIG_SBC_EPX_C3_WATCHDOG is not set
-# CONFIG_SC1200_WDT is not set
-# CONFIG_SC520_WDT is not set
-CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
-# CONFIG_SCSI_MULTI_LUN is not set
-CONFIG_SCSI_WAIT_SCAN=m
-# CONFIG_SCx200 is not set
-# CONFIG_SCx200_ACB is not set
-CONFIG_SEMAPHORE_SLEEPERS=y
-# CONFIG_SERIAL_8250_EXTENDED is not set
-CONFIG_SLABINFO=y
-# CONFIG_SMP is not set
-# CONFIG_SMSC37B787_WDT is not set
-# CONFIG_SMSC_PHY is not set
-CONFIG_SOFT_WATCHDOG=m
-# CONFIG_SONYPI is not set
-# CONFIG_SPARSEMEM_STATIC is not set
-# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
-CONFIG_SSB_POSSIBLE=y
-CONFIG_SYSVIPC_SYSCTL=y
-# CONFIG_TELCLOCK is not set
-CONFIG_TICK_ONESHOT=y
-# CONFIG_TOSHIBA is not set
-CONFIG_UID16=y
-CONFIG_USB=m
-# CONFIG_USBPCWATCHDOG is not set
-CONFIG_USB_EHCI_HCD=m
-# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
-# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
-CONFIG_USB_OHCI_HCD=m
-CONFIG_USB_PWC=m
-# CONFIG_USB_PWC_DEBUG is not set
-# CONFIG_USB_SERIAL_CH341 is not set
-# CONFIG_USB_SERIAL_OTI6858 is not set
-# CONFIG_USB_UHCI_HCD is not set
-# CONFIG_USER_NS is not set
-CONFIG_V4L_USB_DRIVERS=y
-# CONFIG_VGASTATE is not set
-# CONFIG_VIA_RHINE is not set
-CONFIG_VIDEO_CAPTURE_DRIVERS=y
-CONFIG_VIDEO_CPIA2=m
-CONFIG_VIDEO_V4L1=y
-CONFIG_VIRTUALIZATION=y
-# CONFIG_VM86 is not set
-# CONFIG_VMSPLIT_1G is not set
-# CONFIG_VMSPLIT_2G is not set
-# CONFIG_VMSPLIT_2G_OPT is not set
-CONFIG_VMSPLIT_3G=y
-# CONFIG_VMSPLIT_3G_OPT is not set
-CONFIG_VM_EVENT_COUNTERS=y
-# CONFIG_WAFER_WDT is not set
-CONFIG_X86=y
-CONFIG_X86_32=y
-# CONFIG_X86_64 is not set
-CONFIG_X86_ALIGNMENT_16=y
-# CONFIG_X86_BIGSMP is not set
-CONFIG_X86_BIOS_REBOOT=y
-CONFIG_X86_BSWAP=y
-CONFIG_X86_CMPXCHG=y
-CONFIG_X86_CPUID=y
-# CONFIG_X86_ELAN is not set
-# CONFIG_X86_ES7000 is not set
-CONFIG_X86_F00F_BUG=y
-# CONFIG_X86_GENERIC is not set
-# CONFIG_X86_GENERICARCH is not set
-CONFIG_X86_INVLPG=y
-CONFIG_X86_L1_CACHE_SHIFT=4
-# CONFIG_X86_MCE is not set
-CONFIG_X86_MINIMUM_CPU_FAMILY=4
-CONFIG_X86_MSR=y
-# CONFIG_X86_NUMAQ is not set
-# CONFIG_X86_PAE is not set
-# CONFIG_X86_PC is not set
-CONFIG_X86_POPAD_OK=y
-CONFIG_X86_PPRO_FENCE=y
-CONFIG_X86_RDC=y
-CONFIG_X86_REBOOTFIXUPS=y
-# CONFIG_X86_SUMMIT is not set
-# CONFIG_X86_UP_APIC is not set
-# CONFIG_X86_VISWS is not set
-# CONFIG_X86_VOYAGER is not set
-# CONFIG_X86_VSMP is not set
-CONFIG_X86_WP_WORKS_OK=y
-CONFIG_X86_XADD=y
-# CONFIG_ZONE_DMA32 is not set
--- /dev/null
+# CONFIG_60XX_WDT is not set
+# CONFIG_64BIT is not set
+# CONFIG_8139TOO is not set
+# CONFIG_ACQUIRE_WDT is not set
+# CONFIG_ADVANTECH_WDT is not set
+# CONFIG_AGP is not set
+# CONFIG_ALIM1535_WDT is not set
+# CONFIG_ALIM7101_WDT is not set
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_ATA=m
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_ATA_PIIX=m
+# CONFIG_AUDIT_ARCH is not set
+CONFIG_BASE_SMALL=0
+CONFIG_BINFMT_AOUT=m
+CONFIG_BINFMT_MISC=m
+CONFIG_BITREVERSE=y
+CONFIG_BLK_DEV_IDE=m
+CONFIG_BLK_DEV_IDEDISK=m
+# CONFIG_BLK_DEV_IDEDMA is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+CONFIG_BOUNCE=y
+# CONFIG_BROADCOM_PHY is not set
+CONFIG_CLOCKSOURCE_WATCHDOG=y
+# CONFIG_COMPAT_VDSO is not set
+# CONFIG_CPU5_WDT is not set
+# CONFIG_CPU_FREQ is not set
+# CONFIG_CPU_IDLE is not set
+CONFIG_CRYPTO_AES_586=m
+CONFIG_CRYPTO_TWOFISH_586=m
+# CONFIG_CS5535_GPIO is not set
+# CONFIG_DCDBAS is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_DELL_RBU is not set
+CONFIG_DEVPORT=y
+# CONFIG_DMADEVICES is not set
+CONFIG_DMI=y
+CONFIG_DMIID=y
+CONFIG_DOUBLEFAULT=y
+# CONFIG_E100 is not set
+CONFIG_EARLY_PRINTK=y
+# CONFIG_EDAC is not set
+# CONFIG_EDD is not set
+# CONFIG_EUROTECH_WDT is not set
+# CONFIG_FIXED_PHY is not set
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+# CONFIG_GENERIC_CPU is not set
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_ISA_DMA=y
+# CONFIG_GENERIC_TIME_VSYSCALL is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_HANGCHECK_TIMER is not set
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HIBERNATION_UP_POSSIBLE=y
+CONFIG_HID=m
+CONFIG_HID_SUPPORT=y
+# CONFIG_HIGHMEM4G is not set
+# CONFIG_HIGHMEM64G is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+# CONFIG_HPET_TIMER is not set
+CONFIG_HUGETLBFS=y
+CONFIG_HUGETLB_PAGE=y
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_AMD is not set
+# CONFIG_HW_RANDOM_GEODE is not set
+# CONFIG_HW_RANDOM_INTEL is not set
+# CONFIG_HW_RANDOM_VIA is not set
+CONFIG_HZ=250
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+CONFIG_I2C=m
+# CONFIG_I2C_ALGOBIT is not set
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I6300ESB_WDT is not set
+# CONFIG_I8K is not set
+# CONFIG_IB700_WDT is not set
+# CONFIG_IBMASR is not set
+# CONFIG_IBM_ASM is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+CONFIG_ICPLUS_PHY=y
+CONFIG_IDE=m
+# CONFIG_IDEPCI_PCIBUS_ORDER is not set
+CONFIG_IDE_ARCH_OBSOLETE_INIT=y
+# CONFIG_IDE_ARM is not set
+# CONFIG_IDE_GENERIC is not set
+# CONFIG_IDE_PROC_FS is not set
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=m
+# CONFIG_INPUT_GPIO_BUTTONS is not set
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_YEALINK=m
+CONFIG_INSTRUMENTATION=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_ISA is not set
+CONFIG_ISA_DMA_API=y
+# CONFIG_IT8712F_WDT is not set
+# CONFIG_ITCO_WDT is not set
+CONFIG_JFS_FS=m
+CONFIG_KEXEC=y
+CONFIG_KTIME_SCALAR=y
+# CONFIG_KVM is not set
+CONFIG_LBD=y
+CONFIG_LEDS_GPIO=y
+# CONFIG_LGUEST is not set
+CONFIG_LSF=y
+# CONFIG_M386 is not set
+CONFIG_M486=y
+# CONFIG_M586 is not set
+# CONFIG_M586MMX is not set
+# CONFIG_M586TSC is not set
+# CONFIG_M686 is not set
+# CONFIG_MACHZ_WDT is not set
+# CONFIG_MACINTOSH_DRIVERS is not set
+# CONFIG_MARKERS is not set
+CONFIG_MATH_EMULATION=y
+# CONFIG_MCA is not set
+# CONFIG_MCORE2 is not set
+# CONFIG_MCRUSOE is not set
+# CONFIG_MCYRIXIII is not set
+# CONFIG_MDIO_BITBANG is not set
+# CONFIG_MEFFICEON is not set
+# CONFIG_MGEODEGX1 is not set
+# CONFIG_MGEODE_LX is not set
+# CONFIG_MICROCODE is not set
+# CONFIG_MK6 is not set
+# CONFIG_MK7 is not set
+# CONFIG_MK8 is not set
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MPENTIUM4 is not set
+# CONFIG_MPENTIUMII is not set
+# CONFIG_MPENTIUMIII is not set
+# CONFIG_MPENTIUMM is not set
+# CONFIG_MPSC is not set
+CONFIG_MTD=y
+# CONFIG_MTD_ABSENT is not set
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_MTD_BLOCK2MTD is not set
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_CONCAT=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_NETSC520 is not set
+# CONFIG_MTD_ONENAND is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_PLATRAM is not set
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_PNC2000 is not set
+# CONFIG_MTD_RAM is not set
+CONFIG_MTD_RDC3210=y
+CONFIG_MTD_RDC3210_ALLOW_JFFS2=y
+CONFIG_MTD_RDC3210_BUSWIDTH=2
+# CONFIG_MTD_RDC3210_FACTORY_PRESENT is not set
+CONFIG_MTD_RDC3210_SIZE=0x400000
+# CONFIG_MTD_RDC3210_STATIC_MAP is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_SC520CDP is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_TS5500 is not set
+# CONFIG_MTRR is not set
+# CONFIG_MVIAC3_2 is not set
+# CONFIG_MVIAC7 is not set
+# CONFIG_MWINCHIP2 is not set
+# CONFIG_MWINCHIP3D is not set
+# CONFIG_MWINCHIPC6 is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NOHIGHMEM=y
+CONFIG_NO_HZ=y
+CONFIG_NR_QUICK=1
+# CONFIG_NSC_GPIO is not set
+CONFIG_NVRAM=y
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PARAVIRT_GUEST is not set
+CONFIG_PATA_ARTOP=m
+# CONFIG_PATA_CS5536 is not set
+# CONFIG_PC8736x_GPIO is not set
+# CONFIG_PC87413_WDT is not set
+CONFIG_PCCARD=m
+CONFIG_PCCARD_NONSTATIC=m
+CONFIG_PCI=y
+# CONFIG_PCIEPORTBUS is not set
+# CONFIG_PCIPCWATCHDOG is not set
+CONFIG_PCI_BIOS=y
+CONFIG_PCI_DIRECT=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_GOANY=y
+# CONFIG_PCI_GOBIOS is not set
+# CONFIG_PCI_GODIRECT is not set
+# CONFIG_PCI_GOMMCONFIG is not set
+CONFIG_PCMCIA=m
+CONFIG_PHYLIB=y
+CONFIG_PHYSICAL_ALIGN=0x100000
+CONFIG_PHYSICAL_START=0x100000
+# CONFIG_QSEMI_PHY is not set
+CONFIG_QUICKLIST=y
+CONFIG_R6040=m
+# CONFIG_R6040_NAPI is not set
+# CONFIG_RELOCATABLE is not set
+# CONFIG_RTC is not set
+# CONFIG_RWSEM_GENERIC_SPINLOCK is not set
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+# CONFIG_SBC7240_WDT is not set
+# CONFIG_SBC8360_WDT is not set
+# CONFIG_SBC_EPX_C3_WATCHDOG is not set
+# CONFIG_SC1200_WDT is not set
+# CONFIG_SC520_WDT is not set
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+# CONFIG_SCSI_MULTI_LUN is not set
+CONFIG_SCSI_WAIT_SCAN=m
+# CONFIG_SCx200 is not set
+# CONFIG_SCx200_ACB is not set
+CONFIG_SEMAPHORE_SLEEPERS=y
+# CONFIG_SERIAL_8250_EXTENDED is not set
+CONFIG_SLABINFO=y
+# CONFIG_SMP is not set
+# CONFIG_SMSC37B787_WDT is not set
+# CONFIG_SMSC_PHY is not set
+CONFIG_SOFT_WATCHDOG=m
+# CONFIG_SONYPI is not set
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SSB_POSSIBLE=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_TELCLOCK is not set
+CONFIG_TICK_ONESHOT=y
+# CONFIG_TOSHIBA is not set
+CONFIG_UID16=y
+CONFIG_USB=m
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_USB_EHCI_HCD=m
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_HCD=m
+CONFIG_USB_PWC=m
+# CONFIG_USB_PWC_DEBUG is not set
+# CONFIG_USB_SERIAL_CH341 is not set
+# CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USER_NS is not set
+CONFIG_V4L_USB_DRIVERS=y
+# CONFIG_VGASTATE is not set
+# CONFIG_VIA_RHINE is not set
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+CONFIG_VIDEO_CPIA2=m
+CONFIG_VIDEO_V4L1=y
+CONFIG_VIRTUALIZATION=y
+# CONFIG_VM86 is not set
+# CONFIG_VMSPLIT_1G is not set
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_2G_OPT is not set
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_3G_OPT is not set
+CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_WAFER_WDT is not set
+CONFIG_X86=y
+CONFIG_X86_32=y
+# CONFIG_X86_64 is not set
+CONFIG_X86_ALIGNMENT_16=y
+# CONFIG_X86_BIGSMP is not set
+CONFIG_X86_BIOS_REBOOT=y
+CONFIG_X86_BSWAP=y
+CONFIG_X86_CMPXCHG=y
+CONFIG_X86_CPUID=y
+# CONFIG_X86_ELAN is not set
+# CONFIG_X86_ES7000 is not set
+CONFIG_X86_F00F_BUG=y
+# CONFIG_X86_GENERIC is not set
+# CONFIG_X86_GENERICARCH is not set
+CONFIG_X86_INVLPG=y
+CONFIG_X86_L1_CACHE_SHIFT=4
+# CONFIG_X86_MCE is not set
+CONFIG_X86_MINIMUM_CPU_FAMILY=4
+CONFIG_X86_MSR=y
+# CONFIG_X86_NUMAQ is not set
+# CONFIG_X86_PAE is not set
+# CONFIG_X86_PC is not set
+CONFIG_X86_POPAD_OK=y
+CONFIG_X86_PPRO_FENCE=y
+CONFIG_X86_RDC=y
+CONFIG_X86_REBOOTFIXUPS=y
+# CONFIG_X86_SUMMIT is not set
+# CONFIG_X86_UP_APIC is not set
+# CONFIG_X86_VISWS is not set
+# CONFIG_X86_VOYAGER is not set
+# CONFIG_X86_VSMP is not set
+CONFIG_X86_WP_WORKS_OK=y
+CONFIG_X86_XADD=y
+# CONFIG_ZONE_DMA32 is not set
+++ /dev/null
-diff -urN linux-2.6.17/drivers/mtd/maps/Kconfig linux-2.6.17.new/drivers/mtd/maps/Kconfig
---- linux-2.6.17/drivers/mtd/maps/Kconfig 2006-06-18 03:49:35.000000000 +0200
-+++ linux-2.6.17.new/drivers/mtd/maps/Kconfig 2006-09-24 20:28:11.000000000 +0200
-@@ -76,6 +76,50 @@
- PNC-2000 is the name of Network Camera product from PHOTRON
- Ltd. in Japan. It uses CFI-compliant flash.
-
-+config MTD_RDC3210
-+ tristate "CFI Flash device mapped on RDC3210"
-+ depends on X86 && MTD_CFI && MTD_PARTITIONS
-+ help
-+ RDC-3210 is the flash device we find on Ralink reference board.
-+
-+config MTD_RDC3210_STATIC_MAP
-+ bool "Partitions on RDC3210 mapped statically" if MTD_RDC3210
-+ select MTD_RDC3210_FACTORY_PRESENT
-+ help
-+ The mapping driver will use the static partition map for the
-+ RDC-3210 flash device.
-+
-+config MTD_RDC3210_FACTORY_PRESENT
-+ bool "Reserve a partition on RDC3210 for factory presets"
-+ depends on MTD_RDC3210
-+ default y
-+ help
-+ The mapping driver will reserve a partition on the RDC-3210 flash
-+ device for resetting flash contents to factory defaults.
-+
-+config MTD_RDC3210_ALLOW_JFFS2
-+ bool "JFFS2 filesystem usable in a partition on RDC3210"
-+ depends on MTD_RDC3210 && !MTD_RDC3210_STATIC_MAP
-+ help
-+ The mapping driver will align a partition on the RDC-3210 flash
-+ device to an erase-block boundary so that a JFFS2 filesystem may
-+ reside on it.
-+
-+config MTD_RDC3210_SIZE
-+ hex "Amount of flash memory on RDC3210"
-+ depends on MTD_RDC3210
-+ default "0x400000"
-+ help
-+ Total size in bytes of the RDC-3210 flash device
-+
-+config MTD_RDC3210_BUSWIDTH
-+ int "Width of CFI Flash device mapped on RDC3210"
-+ depends on MTD_RDC3210
-+ default "2"
-+ help
-+ Number of bytes addressed on the RDC-3210 flash device before
-+ addressing the same chip again
-+
- config MTD_SC520CDP
- tristate "CFI Flash device mapped on AMD SC520 CDP"
- depends on X86 && MTD_CFI && MTD_CONCAT
-diff -urN linux-2.6.17/drivers/mtd/maps/Makefile linux-2.6.17.new/drivers/mtd/maps/Makefile
---- linux-2.6.17/drivers/mtd/maps/Makefile 2006-06-18 03:49:35.000000000 +0200
-+++ linux-2.6.17.new/drivers/mtd/maps/Makefile 2006-09-24 20:26:10.000000000 +0200
-@@ -28,6 +28,7 @@
- obj-$(CONFIG_MTD_PHYSMAP) += physmap.o
- obj-$(CONFIG_MTD_PNC2000) += pnc2000.o
- obj-$(CONFIG_MTD_PCMCIA) += pcmciamtd.o
-+obj-$(CONFIG_MTD_RDC3210) += rdc3210.o
- obj-$(CONFIG_MTD_RPXLITE) += rpxlite.o
- obj-$(CONFIG_MTD_TQM8XXL) += tqm8xxl.o
- obj-$(CONFIG_MTD_SA1100) += sa1100-flash.o
+++ /dev/null
-diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
-index 97b64d7..f8c1d32 100644
---- a/arch/x86/Kconfig
-+++ b/arch/x86/Kconfig
-@@ -79,6 +79,10 @@ config GENERIC_BUG
- default y
- depends on BUG
-
-+config GENERIC_GPIO
-+ bool
-+ default n
-+
- config GENERIC_HWEIGHT
- bool
- default y
+++ /dev/null
-diff -urN linux-2.6.17/drivers/net/Kconfig linux-2.6.17.new/drivers/net/Kconfig
---- linux-2.6.17/drivers/net/Kconfig 2006-06-18 03:49:35.000000000 +0200
-+++ linux-2.6.17.new/drivers/net/Kconfig 2006-09-25 13:14:27.000000000 +0200
-@@ -1358,6 +1358,24 @@
- <file:Documentation/networking/net-modules.txt>. The module will be
- called apricot.
-
-+config R6040
-+ tristate "RDC Fast-Ethernet support (EXPERIMENTAL)"
-+ depends on NET_PCI && EXPERIMENTAL
-+ select MII
-+ help
-+ If you have a network (Ethernet) controller of this type, say Y and
-+ read the Ethernet-HOWTO, available from
-+ <http://www.tldp.org/docs.html#howto>.
-+
-+ To compile this driver as a module, choose M here and read
-+ <file:Documentation/networking/net-modules.txt>. The module will be
-+ called r6040.
-+
-+
-+config R6040_NAPI
-+ bool "NAPI support for R6040"
-+ depends on R6040
-+ default y
- config B44
- tristate "Broadcom 4400 ethernet support (EXPERIMENTAL)"
- depends on NET_PCI && PCI && EXPERIMENTAL
-diff -urN linux-2.6.17/drivers/net/Makefile linux-2.6.17.new/drivers/net/Makefile
---- linux-2.6.17/drivers/net/Makefile 2006-06-18 03:49:35.000000000 +0200
-+++ linux-2.6.17.new/drivers/net/Makefile 2006-09-25 13:14:45.000000000 +0200
-@@ -106,6 +106,7 @@
- obj-$(CONFIG_NE3210) += ne3210.o 8390.o
- obj-$(CONFIG_NET_SB1250_MAC) += sb1250-mac.o
- obj-$(CONFIG_B44) += b44.o
-+obj-$(CONFIG_R6040) += r6040.o
- obj-$(CONFIG_FORCEDETH) += forcedeth.o
- obj-$(CONFIG_NE_H8300) += ne-h8300.o 8390.o
-
+++ /dev/null
---- linux-2.6.19.2/init/do_mounts.c 2007-01-10 11:10:37.000000000 -0800
-+++ foo/init/do_mounts.c 2007-04-05 13:15:37.000000000 -0700
-@@ -243,6 +243,8 @@
- {
- char *s = page;
-
-+ if (!root_fs_names)
-+ root_fs_names = "squashfs,jffs2";
- if (root_fs_names) {
- strcpy(page, root_fs_names);
- while (*s++) {
+++ /dev/null
-diff -urN linux-2.6.24/arch/x86/Kconfig linux-2.6.24.new/arch/x86/Kconfig
---- linux-2.6.24/arch/x86/Kconfig 2008-01-24 23:58:37.000000000 +0100
-+++ linux-2.6.24.new/arch/x86/Kconfig 2008-02-11 18:24:27.000000000 +0100
-@@ -300,6 +300,17 @@
- supposed to run on these EM64T-based machines. Only choose this option
- if you have one of these machines.
-
-+config X86_RDC
-+ bool "Support for RDC 3211 boards"
-+ select GENERIC_GPIO
-+ select LEDS_GPIO
-+ select LEDS_CLASS
-+ help
-+ Support for RDC 3211 systems. Say 'Y' here if the kernel is
-+ supposed to run on an IA-32 RDC R3211 system.
-+ Only choose this option if you have such as system, otherwise you
-+ should say N here.
-+
- endchoice
-
- config SCHED_NO_NO_OMIT_FRAME_POINTER
-diff -urN linux-2.6.24/arch/x86/kernel/reboot_fixups_32.c linux-2.6.24.new/arch/x86/kernel/reboot_fixups_32.c
---- linux-2.6.24/arch/x86/kernel/reboot_fixups_32.c 2008-01-24 23:58:37.000000000 +0100
-+++ linux-2.6.24.new/arch/x86/kernel/reboot_fixups_32.c 2008-02-11 18:26:18.000000000 +0100
-@@ -30,6 +30,17 @@
- udelay(50); /* shouldn't get here but be safe and spin a while */
- }
-
-+static void r8610_reset(struct pci_dev *dev)
-+{
-+ int i;
-+
-+ outl(0x80003840,0xCF8);
-+ i=inl(0xCFC);
-+ i |= 0x1600;
-+ outl(i,0xCFC);
-+ outb(1,0x92);
-+}
-+
- struct device_fixup {
- unsigned int vendor;
- unsigned int device;
-@@ -40,6 +51,7 @@
- { PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY, cs5530a_warm_reset },
- { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, cs5536_warm_reset },
- { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SC1100_BRIDGE, cs5530a_warm_reset },
-+{ PCI_VENDOR_ID_RDC, PCI_DEVICE_ID_RDC_R6030, r8610_reset },
- };
-
- /*
-diff -urN linux-2.6.24/arch/x86/Makefile_32 linux-2.6.24.new/arch/x86/Makefile_32
---- linux-2.6.24/arch/x86/Makefile_32 2008-01-24 23:58:37.000000000 +0100
-+++ linux-2.6.24.new/arch/x86/Makefile_32 2008-02-11 18:25:12.000000000 +0100
-@@ -99,6 +99,11 @@
- mcore-$(CONFIG_X86_ES7000) := arch/x86/mach-default
- core-$(CONFIG_X86_ES7000) := arch/x86/mach-es7000/
-
-+# RDC subarch support
-+mflags-$(CONFIG_X86_RDC) := -Iinclude/asm-x86/mach-rdc
-+mcore-$(CONFIG_X86_RDC) := arch/x86/mach-default
-+core-$(CONFIG_X86_RDC) += arch/x86/mach-rdc/
-+
- # Xen paravirtualization support
- core-$(CONFIG_XEN) += arch/x86/xen/
-
-diff -urN linux-2.6.24/include/asm-x86/timex.h linux-2.6.24.new/include/asm-x86/timex.h
---- linux-2.6.24/include/asm-x86/timex.h 2008-01-24 23:58:37.000000000 +0100
-+++ linux-2.6.24.new/include/asm-x86/timex.h 2008-02-11 18:25:43.000000000 +0100
-@@ -7,6 +7,8 @@
-
- #ifdef CONFIG_X86_ELAN
- # define PIT_TICK_RATE 1189200 /* AMD Elan has different frequency! */
-+#elif defined(CONFIG_X86_RDC)
-+# define PIT_TICK_RATE 1041667 /* Underlying HZ for R8610 */
- #else
- # define PIT_TICK_RATE 1193182 /* Underlying HZ */
- #endif
+++ /dev/null
---- linux-2.6.24.7/arch/x86/kernel/setup_32.c 2008-05-07 01:22:34.000000000 +0200
-+++ linux-2.6.24.7.new/arch/x86/kernel/setup_32.c 2008-08-05 14:54:58.000000000 +0200
-@@ -609,6 +609,7 @@
- print_memory_map("user");
- }
-
-+ strcat(boot_command_line, " init=/etc/preinit");
- strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
- *cmdline_p = command_line;
-
+++ /dev/null
-diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
-index 55f307f..4a1aa34 100644
---- a/include/linux/pci_ids.h
-+++ b/include/linux/pci_ids.h
-@@ -2076,6 +2076,13 @@
- #define PCI_DEVICE_ID_HERC_WIN 0x5732
- #define PCI_DEVICE_ID_HERC_UNI 0x5832
-
-+#define PCI_VENDOR_ID_RDC 0x17f3
-+#define PCI_DEVICE_ID_RDC_R6020 0x6020
-+#define PCI_DEVICE_ID_RDC_R6030 0x6030
-+#define PCI_DEVICE_ID_RDC_R6040 0x6040
-+#define PCI_DEVICE_ID_RDC_R6060 0x6060
-+#define PCI_DEVICE_ID_RDC_R6061 0x6061
-+
- #define PCI_VENDOR_ID_SITECOM 0x182d
- #define PCI_DEVICE_ID_SITECOM_DC105V2 0x3069
-
+++ /dev/null
-diff -urN linux-2.6.19.2/scripts/Makefile.lib linux-2.6.19.2.new/scripts/Makefile.lib
---- linux-2.6.19.2/scripts/Makefile.lib 2007-01-10 20:10:37.000000000 +0100
-+++ linux-2.6.19.2.new/scripts/Makefile.lib 2007-04-15 23:51:54.000000000 +0200
-@@ -162,4 +162,9 @@
- quiet_cmd_gzip = GZIP $@
- cmd_gzip = gzip -f -9 < $< > $@
-
--
-+# LZMA
-+#
-+quiet_cmd_lzma = LZMA $@
-+cmd_lzma = bash -e scripts/lzma_kern $< $@ -lc7 -lp0 -pb0
-+# to use lzmacomp,
-+# cmd_lzma = lzmacomp $< 700 > $@
-diff -u linux/scripts/lzma_kern linux/scripts/lzma_kern
---- linux/scripts/lzma_kern 2007-07-27 20:18:17.013014750 -0700
-+++ linux/scripts/lzma_kern 2007-07-27 20:18:17.013014750 -0700
-@@ -0,0 +1,4 @@
-+get-size() { echo "$5" ;}
-+printf -v len '%.8x' "$(get-size $(ls -l "$1"))"
-+lzma e "$@"
-+echo -ne "\x$(echo $len | cut -c 7,8)\x$(echo $len | cut -c 5,6)\x$(echo $len | cut -c 3,4)\x$(echo $len | cut -c 1,2)" >> "$2"
-diff -urN linux-2.6.24/arch/x86/boot/compressed/Makefile_32 linux-2.6.24.new/arch/x86/boot/compressed/Makefile_32
---- linux-2.6.24/arch/x86/boot/compressed/Makefile_32 2008-01-24 23:58:37.000000000 +0100
-+++ linux-2.6.24.new/arch/x86/boot/compressed/Makefile_32 2008-02-13 15:21:03.000000000 +0100
-@@ -4,8 +4,8 @@
- # create a compressed vmlinux image from the original vmlinux
- #
-
--targets := vmlinux vmlinux.bin vmlinux.bin.gz head_32.o misc_32.o piggy.o \
-- vmlinux.bin.all vmlinux.relocs
-+targets := vmlinux vmlinux.bin vmlinux.bin.lzma head_32.o piggy.o \
-+ vmlinux.bin.all vmlinux.relocs lzma_misc.o
- EXTRA_AFLAGS := -traditional
-
- LDFLAGS_vmlinux := -T
-@@ -17,7 +17,7 @@
- $(call cc-option,-fno-stack-protector)
- LDFLAGS := -m elf_i386
-
--$(obj)/vmlinux: $(src)/vmlinux_32.lds $(obj)/head_32.o $(obj)/misc_32.o $(obj)/piggy.o FORCE
-+$(obj)/vmlinux: $(src)/vmlinux_32.lds $(obj)/head_32.o $(obj)/lzma_misc.o $(obj)/piggy.o FORCE
- $(call if_changed,ld)
- @:
-
-@@ -37,14 +37,14 @@
- $(call if_changed,relocbin)
-
- ifdef CONFIG_RELOCATABLE
--$(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin.all FORCE
-- $(call if_changed,gzip)
-+$(obj)/vmlinux.bin.lzma: $(obj)/vmlinux.bin.all FORCE
-+ $(call if_changed,lzma)
- else
--$(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin FORCE
-- $(call if_changed,gzip)
-+$(obj)/vmlinux.bin.lzma: $(obj)/vmlinux.bin FORCE
-+ $(call if_changed,lzma)
- endif
-
- LDFLAGS_piggy.o := -r --format binary --oformat elf32-i386 -T
-
--$(obj)/piggy.o: $(src)/vmlinux_32.scr $(obj)/vmlinux.bin.gz FORCE
-+$(obj)/piggy.o: $(src)/vmlinux_32.scr $(obj)/vmlinux.bin.lzma FORCE
- $(call if_changed,ld)
--- /dev/null
+diff -urN linux-2.6.17/drivers/mtd/maps/Kconfig linux-2.6.17.new/drivers/mtd/maps/Kconfig
+--- linux-2.6.17/drivers/mtd/maps/Kconfig 2006-06-18 03:49:35.000000000 +0200
++++ linux-2.6.17.new/drivers/mtd/maps/Kconfig 2006-09-24 20:28:11.000000000 +0200
+@@ -76,6 +76,50 @@
+ PNC-2000 is the name of Network Camera product from PHOTRON
+ Ltd. in Japan. It uses CFI-compliant flash.
+
++config MTD_RDC3210
++ tristate "CFI Flash device mapped on RDC3210"
++ depends on X86 && MTD_CFI && MTD_PARTITIONS
++ help
++ RDC-3210 is the flash device we find on Ralink reference board.
++
++config MTD_RDC3210_STATIC_MAP
++ bool "Partitions on RDC3210 mapped statically" if MTD_RDC3210
++ select MTD_RDC3210_FACTORY_PRESENT
++ help
++ The mapping driver will use the static partition map for the
++ RDC-3210 flash device.
++
++config MTD_RDC3210_FACTORY_PRESENT
++ bool "Reserve a partition on RDC3210 for factory presets"
++ depends on MTD_RDC3210
++ default y
++ help
++ The mapping driver will reserve a partition on the RDC-3210 flash
++ device for resetting flash contents to factory defaults.
++
++config MTD_RDC3210_ALLOW_JFFS2
++ bool "JFFS2 filesystem usable in a partition on RDC3210"
++ depends on MTD_RDC3210 && !MTD_RDC3210_STATIC_MAP
++ help
++ The mapping driver will align a partition on the RDC-3210 flash
++ device to an erase-block boundary so that a JFFS2 filesystem may
++ reside on it.
++
++config MTD_RDC3210_SIZE
++ hex "Amount of flash memory on RDC3210"
++ depends on MTD_RDC3210
++ default "0x400000"
++ help
++ Total size in bytes of the RDC-3210 flash device
++
++config MTD_RDC3210_BUSWIDTH
++ int "Width of CFI Flash device mapped on RDC3210"
++ depends on MTD_RDC3210
++ default "2"
++ help
++ Number of bytes addressed on the RDC-3210 flash device before
++ addressing the same chip again
++
+ config MTD_SC520CDP
+ tristate "CFI Flash device mapped on AMD SC520 CDP"
+ depends on X86 && MTD_CFI && MTD_CONCAT
+diff -urN linux-2.6.17/drivers/mtd/maps/Makefile linux-2.6.17.new/drivers/mtd/maps/Makefile
+--- linux-2.6.17/drivers/mtd/maps/Makefile 2006-06-18 03:49:35.000000000 +0200
++++ linux-2.6.17.new/drivers/mtd/maps/Makefile 2006-09-24 20:26:10.000000000 +0200
+@@ -28,6 +28,7 @@
+ obj-$(CONFIG_MTD_PHYSMAP) += physmap.o
+ obj-$(CONFIG_MTD_PNC2000) += pnc2000.o
+ obj-$(CONFIG_MTD_PCMCIA) += pcmciamtd.o
++obj-$(CONFIG_MTD_RDC3210) += rdc3210.o
+ obj-$(CONFIG_MTD_RPXLITE) += rpxlite.o
+ obj-$(CONFIG_MTD_TQM8XXL) += tqm8xxl.o
+ obj-$(CONFIG_MTD_SA1100) += sa1100-flash.o
--- /dev/null
+diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
+index 97b64d7..f8c1d32 100644
+--- a/arch/x86/Kconfig
++++ b/arch/x86/Kconfig
+@@ -79,6 +79,10 @@ config GENERIC_BUG
+ default y
+ depends on BUG
+
++config GENERIC_GPIO
++ bool
++ default n
++
+ config GENERIC_HWEIGHT
+ bool
+ default y
--- /dev/null
+diff -urN linux-2.6.17/drivers/net/Kconfig linux-2.6.17.new/drivers/net/Kconfig
+--- linux-2.6.17/drivers/net/Kconfig 2006-06-18 03:49:35.000000000 +0200
++++ linux-2.6.17.new/drivers/net/Kconfig 2006-09-25 13:14:27.000000000 +0200
+@@ -1358,6 +1358,24 @@
+ <file:Documentation/networking/net-modules.txt>. The module will be
+ called apricot.
+
++config R6040
++ tristate "RDC Fast-Ethernet support (EXPERIMENTAL)"
++ depends on NET_PCI && EXPERIMENTAL
++ select MII
++ help
++ If you have a network (Ethernet) controller of this type, say Y and
++ read the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++ To compile this driver as a module, choose M here and read
++ <file:Documentation/networking/net-modules.txt>. The module will be
++ called r6040.
++
++
++config R6040_NAPI
++ bool "NAPI support for R6040"
++ depends on R6040
++ default y
+ config B44
+ tristate "Broadcom 4400 ethernet support (EXPERIMENTAL)"
+ depends on NET_PCI && PCI && EXPERIMENTAL
+diff -urN linux-2.6.17/drivers/net/Makefile linux-2.6.17.new/drivers/net/Makefile
+--- linux-2.6.17/drivers/net/Makefile 2006-06-18 03:49:35.000000000 +0200
++++ linux-2.6.17.new/drivers/net/Makefile 2006-09-25 13:14:45.000000000 +0200
+@@ -106,6 +106,7 @@
+ obj-$(CONFIG_NE3210) += ne3210.o 8390.o
+ obj-$(CONFIG_NET_SB1250_MAC) += sb1250-mac.o
+ obj-$(CONFIG_B44) += b44.o
++obj-$(CONFIG_R6040) += r6040.o
+ obj-$(CONFIG_FORCEDETH) += forcedeth.o
+ obj-$(CONFIG_NE_H8300) += ne-h8300.o 8390.o
+
--- /dev/null
+--- linux-2.6.19.2/init/do_mounts.c 2007-01-10 11:10:37.000000000 -0800
++++ foo/init/do_mounts.c 2007-04-05 13:15:37.000000000 -0700
+@@ -243,6 +243,8 @@
+ {
+ char *s = page;
+
++ if (!root_fs_names)
++ root_fs_names = "squashfs,jffs2";
+ if (root_fs_names) {
+ strcpy(page, root_fs_names);
+ while (*s++) {
--- /dev/null
+diff -urN linux-2.6.24/arch/x86/Kconfig linux-2.6.24.new/arch/x86/Kconfig
+--- linux-2.6.24/arch/x86/Kconfig 2008-01-24 23:58:37.000000000 +0100
++++ linux-2.6.24.new/arch/x86/Kconfig 2008-02-11 18:24:27.000000000 +0100
+@@ -300,6 +300,17 @@
+ supposed to run on these EM64T-based machines. Only choose this option
+ if you have one of these machines.
+
++config X86_RDC
++ bool "Support for RDC 3211 boards"
++ select GENERIC_GPIO
++ select LEDS_GPIO
++ select LEDS_CLASS
++ help
++ Support for RDC 3211 systems. Say 'Y' here if the kernel is
++ supposed to run on an IA-32 RDC R3211 system.
++ Only choose this option if you have such as system, otherwise you
++ should say N here.
++
+ endchoice
+
+ config SCHED_NO_NO_OMIT_FRAME_POINTER
+diff -urN linux-2.6.24/arch/x86/kernel/reboot_fixups_32.c linux-2.6.24.new/arch/x86/kernel/reboot_fixups_32.c
+--- linux-2.6.24/arch/x86/kernel/reboot_fixups_32.c 2008-01-24 23:58:37.000000000 +0100
++++ linux-2.6.24.new/arch/x86/kernel/reboot_fixups_32.c 2008-02-11 18:26:18.000000000 +0100
+@@ -30,6 +30,17 @@
+ udelay(50); /* shouldn't get here but be safe and spin a while */
+ }
+
++static void r8610_reset(struct pci_dev *dev)
++{
++ int i;
++
++ outl(0x80003840,0xCF8);
++ i=inl(0xCFC);
++ i |= 0x1600;
++ outl(i,0xCFC);
++ outb(1,0x92);
++}
++
+ struct device_fixup {
+ unsigned int vendor;
+ unsigned int device;
+@@ -40,6 +51,7 @@
+ { PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY, cs5530a_warm_reset },
+ { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, cs5536_warm_reset },
+ { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SC1100_BRIDGE, cs5530a_warm_reset },
++{ PCI_VENDOR_ID_RDC, PCI_DEVICE_ID_RDC_R6030, r8610_reset },
+ };
+
+ /*
+diff -urN linux-2.6.24/arch/x86/Makefile_32 linux-2.6.24.new/arch/x86/Makefile_32
+--- linux-2.6.24/arch/x86/Makefile_32 2008-01-24 23:58:37.000000000 +0100
++++ linux-2.6.24.new/arch/x86/Makefile_32 2008-02-11 18:25:12.000000000 +0100
+@@ -99,6 +99,11 @@
+ mcore-$(CONFIG_X86_ES7000) := arch/x86/mach-default
+ core-$(CONFIG_X86_ES7000) := arch/x86/mach-es7000/
+
++# RDC subarch support
++mflags-$(CONFIG_X86_RDC) := -Iinclude/asm-x86/mach-rdc
++mcore-$(CONFIG_X86_RDC) := arch/x86/mach-default
++core-$(CONFIG_X86_RDC) += arch/x86/mach-rdc/
++
+ # Xen paravirtualization support
+ core-$(CONFIG_XEN) += arch/x86/xen/
+
+diff -urN linux-2.6.24/include/asm-x86/timex.h linux-2.6.24.new/include/asm-x86/timex.h
+--- linux-2.6.24/include/asm-x86/timex.h 2008-01-24 23:58:37.000000000 +0100
++++ linux-2.6.24.new/include/asm-x86/timex.h 2008-02-11 18:25:43.000000000 +0100
+@@ -7,6 +7,8 @@
+
+ #ifdef CONFIG_X86_ELAN
+ # define PIT_TICK_RATE 1189200 /* AMD Elan has different frequency! */
++#elif defined(CONFIG_X86_RDC)
++# define PIT_TICK_RATE 1041667 /* Underlying HZ for R8610 */
+ #else
+ # define PIT_TICK_RATE 1193182 /* Underlying HZ */
+ #endif
--- /dev/null
+--- linux-2.6.24.7/arch/x86/kernel/setup_32.c 2008-05-07 01:22:34.000000000 +0200
++++ linux-2.6.24.7.new/arch/x86/kernel/setup_32.c 2008-08-05 14:54:58.000000000 +0200
+@@ -609,6 +609,7 @@
+ print_memory_map("user");
+ }
+
++ strcat(boot_command_line, " init=/etc/preinit");
+ strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
+ *cmdline_p = command_line;
+
--- /dev/null
+diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
+index 55f307f..4a1aa34 100644
+--- a/include/linux/pci_ids.h
++++ b/include/linux/pci_ids.h
+@@ -2076,6 +2076,13 @@
+ #define PCI_DEVICE_ID_HERC_WIN 0x5732
+ #define PCI_DEVICE_ID_HERC_UNI 0x5832
+
++#define PCI_VENDOR_ID_RDC 0x17f3
++#define PCI_DEVICE_ID_RDC_R6020 0x6020
++#define PCI_DEVICE_ID_RDC_R6030 0x6030
++#define PCI_DEVICE_ID_RDC_R6040 0x6040
++#define PCI_DEVICE_ID_RDC_R6060 0x6060
++#define PCI_DEVICE_ID_RDC_R6061 0x6061
++
+ #define PCI_VENDOR_ID_SITECOM 0x182d
+ #define PCI_DEVICE_ID_SITECOM_DC105V2 0x3069
+
--- /dev/null
+diff -urN linux-2.6.19.2/scripts/Makefile.lib linux-2.6.19.2.new/scripts/Makefile.lib
+--- linux-2.6.19.2/scripts/Makefile.lib 2007-01-10 20:10:37.000000000 +0100
++++ linux-2.6.19.2.new/scripts/Makefile.lib 2007-04-15 23:51:54.000000000 +0200
+@@ -162,4 +162,9 @@
+ quiet_cmd_gzip = GZIP $@
+ cmd_gzip = gzip -f -9 < $< > $@
+
+-
++# LZMA
++#
++quiet_cmd_lzma = LZMA $@
++cmd_lzma = bash -e scripts/lzma_kern $< $@ -lc7 -lp0 -pb0
++# to use lzmacomp,
++# cmd_lzma = lzmacomp $< 700 > $@
+diff -u linux/scripts/lzma_kern linux/scripts/lzma_kern
+--- linux/scripts/lzma_kern 2007-07-27 20:18:17.013014750 -0700
++++ linux/scripts/lzma_kern 2007-07-27 20:18:17.013014750 -0700
+@@ -0,0 +1,4 @@
++get-size() { echo "$5" ;}
++printf -v len '%.8x' "$(get-size $(ls -l "$1"))"
++lzma e "$@"
++echo -ne "\x$(echo $len | cut -c 7,8)\x$(echo $len | cut -c 5,6)\x$(echo $len | cut -c 3,4)\x$(echo $len | cut -c 1,2)" >> "$2"
+diff -urN linux-2.6.24/arch/x86/boot/compressed/Makefile_32 linux-2.6.24.new/arch/x86/boot/compressed/Makefile_32
+--- linux-2.6.24/arch/x86/boot/compressed/Makefile_32 2008-01-24 23:58:37.000000000 +0100
++++ linux-2.6.24.new/arch/x86/boot/compressed/Makefile_32 2008-02-13 15:21:03.000000000 +0100
+@@ -4,8 +4,8 @@
+ # create a compressed vmlinux image from the original vmlinux
+ #
+
+-targets := vmlinux vmlinux.bin vmlinux.bin.gz head_32.o misc_32.o piggy.o \
+- vmlinux.bin.all vmlinux.relocs
++targets := vmlinux vmlinux.bin vmlinux.bin.lzma head_32.o piggy.o \
++ vmlinux.bin.all vmlinux.relocs lzma_misc.o
+ EXTRA_AFLAGS := -traditional
+
+ LDFLAGS_vmlinux := -T
+@@ -17,7 +17,7 @@
+ $(call cc-option,-fno-stack-protector)
+ LDFLAGS := -m elf_i386
+
+-$(obj)/vmlinux: $(src)/vmlinux_32.lds $(obj)/head_32.o $(obj)/misc_32.o $(obj)/piggy.o FORCE
++$(obj)/vmlinux: $(src)/vmlinux_32.lds $(obj)/head_32.o $(obj)/lzma_misc.o $(obj)/piggy.o FORCE
+ $(call if_changed,ld)
+ @:
+
+@@ -37,14 +37,14 @@
+ $(call if_changed,relocbin)
+
+ ifdef CONFIG_RELOCATABLE
+-$(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin.all FORCE
+- $(call if_changed,gzip)
++$(obj)/vmlinux.bin.lzma: $(obj)/vmlinux.bin.all FORCE
++ $(call if_changed,lzma)
+ else
+-$(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin FORCE
+- $(call if_changed,gzip)
++$(obj)/vmlinux.bin.lzma: $(obj)/vmlinux.bin FORCE
++ $(call if_changed,lzma)
+ endif
+
+ LDFLAGS_piggy.o := -r --format binary --oformat elf32-i386 -T
+
+-$(obj)/piggy.o: $(src)/vmlinux_32.scr $(obj)/vmlinux.bin.gz FORCE
++$(obj)/piggy.o: $(src)/vmlinux_32.scr $(obj)/vmlinux.bin.lzma FORCE
+ $(call if_changed,ld)
+++ /dev/null
-# CONFIG_3C515 is not set
-# CONFIG_60XX_WDT is not set
-# CONFIG_64BIT is not set
-CONFIG_8139TOO=m
-# CONFIG_8139TOO_8129 is not set
-CONFIG_8139TOO_PIO=y
-# CONFIG_8139TOO_TUNE_TWISTER is not set
-# CONFIG_8139_OLD_RX_RESET is not set
-# CONFIG_AC3200 is not set
-CONFIG_AC97_BUS=m
-# CONFIG_ACQUIRE_WDT is not set
-# CONFIG_ADVANTECH_WDT is not set
-# CONFIG_AGP is not set
-# CONFIG_AIRO_CS is not set
-# CONFIG_ALIM1535_WDT is not set
-# CONFIG_ALIM7101_WDT is not set
-# CONFIG_APRICOT is not set
-CONFIG_ARCH_DEFCONFIG="arch/x86/configs/i386_defconfig"
-CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
-CONFIG_ARCH_HAS_CPU_RELAX=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_MAY_HAVE_PC_FDC=y
-CONFIG_ARCH_POPULATES_NODE_MAP=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUPPORTS_AOUT=y
-CONFIG_ARCH_SUPPORTS_MSI=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-# CONFIG_AT1700 is not set
-CONFIG_ATA=m
-# CONFIG_ATA_NONSTANDARD is not set
-CONFIG_ATA_PIIX=m
-# CONFIG_AUDIT_ARCH is not set
-CONFIG_BASE_SMALL=0
-# CONFIG_BINFMT_AOUT is not set
-CONFIG_BINFMT_MISC=y
-CONFIG_BITREVERSE=y
-# CONFIG_BLK_DEV_4DRIVES is not set
-# CONFIG_BLK_DEV_ALI14XX is not set
-# CONFIG_BLK_DEV_DTC2278 is not set
-CONFIG_BLK_DEV_GENERIC=y
-# CONFIG_BLK_DEV_HT6560B is not set
-CONFIG_BLK_DEV_IDE=y
-CONFIG_BLK_DEV_IDEDISK=y
-CONFIG_BLK_DEV_IDEDMA=y
-CONFIG_BLK_DEV_IDEDMA_PCI=y
-CONFIG_BLK_DEV_IDEDMA_SFF=y
-CONFIG_BLK_DEV_IDEPCI=y
-# CONFIG_BLK_DEV_QD65XX is not set
-CONFIG_BLK_DEV_SC1200=y
-# CONFIG_BLK_DEV_UMC8672 is not set
-CONFIG_BLK_DEV_VIA82CXXX=y
-# CONFIG_BLK_DEV_XD is not set
-CONFIG_BOUNCE=y
-# CONFIG_BT_HIDP is not set
-CONFIG_CLASSIC_RCU=y
-CONFIG_CLOCKSOURCE_WATCHDOG=y
-CONFIG_COMPAT_VDSO=y
-# CONFIG_CPU5_WDT is not set
-CONFIG_CPU_FREQ=y
-# CONFIG_CPU_FREQ_DEBUG is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_FREQ_STAT_DETAILS=y
-CONFIG_CPU_FREQ_TABLE=y
-# CONFIG_CPU_IDLE is not set
-CONFIG_CRYPTO_AEAD=m
-CONFIG_CRYPTO_AES_586=m
-CONFIG_CRYPTO_AUTHENC=m
-CONFIG_CRYPTO_GF128MUL=m
-# CONFIG_CRYPTO_SALSA20_586 is not set
-CONFIG_CRYPTO_TWOFISH_586=m
-# CONFIG_CS5535_GPIO is not set
-# CONFIG_CS89x0 is not set
-# CONFIG_DCDBAS is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEFAULT_IO_DELAY_TYPE=0
-# CONFIG_DELL_RBU is not set
-# CONFIG_DEPCA is not set
-CONFIG_DEVPORT=y
-# CONFIG_DMADEVICES is not set
-# CONFIG_DMASCC is not set
-CONFIG_DMI=y
-# CONFIG_DMIID is not set
-CONFIG_DNOTIFY=y
-CONFIG_DOUBLEFAULT=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_E1000=m
-# CONFIG_E1000E_ENABLED is not set
-# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
-CONFIG_E1000_NAPI=y
-CONFIG_EARLY_PRINTK=y
-# CONFIG_EDAC is not set
-# CONFIG_EDD is not set
-# CONFIG_EISA is not set
-# CONFIG_EL1 is not set
-# CONFIG_EL16 is not set
-# CONFIG_EL2 is not set
-# CONFIG_EL3 is not set
-CONFIG_ELF_CORE=y
-# CONFIG_ELPLUS is not set
-# CONFIG_EMBEDDED is not set
-# CONFIG_EUROTECH_WDT is not set
-CONFIG_EXT2_FS=y
-CONFIG_FAST_CMPXCHG_LOCAL=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FS_POSIX_ACL=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-# CONFIG_GENERIC_CPU is not set
-# CONFIG_GENERIC_GPIO is not set
-CONFIG_GENERIC_IOMAP=y
-CONFIG_GENERIC_ISA_DMA=y
-# CONFIG_GENERIC_LOCKBREAK is not set
-# CONFIG_GENERIC_TIME_VSYSCALL is not set
-# CONFIG_HANGCHECK_TIMER is not set
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-CONFIG_HAVE_KVM=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_HAVE_OPROFILE=y
-# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
-CONFIG_HID=y
-CONFIG_HID_SUPPORT=y
-# CONFIG_HIGHMEM4G is not set
-# CONFIG_HIGHMEM64G is not set
-# CONFIG_HIGH_RES_TIMERS is not set
-# CONFIG_HPET_TIMER is not set
-# CONFIG_HP_WATCHDOG is not set
-CONFIG_HT_IRQ=y
-# CONFIG_HUGETLBFS is not set
-CONFIG_HWMON=m
-# CONFIG_HWMON_DEBUG_CHIP is not set
-CONFIG_HWMON_VID=m
-CONFIG_HW_CONSOLE=y
-CONFIG_HW_RANDOM=y
-# CONFIG_HW_RANDOM_AMD is not set
-CONFIG_HW_RANDOM_GEODE=y
-# CONFIG_HW_RANDOM_INTEL is not set
-CONFIG_HW_RANDOM_VIA=y
-CONFIG_I2C=m
-CONFIG_I2C_ALGOBIT=m
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=m
-# CONFIG_I6300ESB_WDT is not set
-# CONFIG_I82365 is not set
-# CONFIG_I8K is not set
-# CONFIG_IB700_WDT is not set
-# CONFIG_IBMASR is not set
-# CONFIG_IBM_ASM is not set
-# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_IBM_NEW_EMAC_RGMII is not set
-# CONFIG_IBM_NEW_EMAC_TAH is not set
-# CONFIG_IBM_NEW_EMAC_ZMII is not set
-CONFIG_IDE=y
-CONFIG_IDEPCI_PCIBUS_ORDER=y
-CONFIG_IDE_ARCH_OBSOLETE_INIT=y
-CONFIG_IDE_GENERIC=y
-# CONFIG_IDE_PROC_FS is not set
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-# CONFIG_INPUT_EVDEV is not set
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_INPUT_MOUSE=y
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_IOMMU_HELPER is not set
-CONFIG_IO_DELAY_0X80=y
-# CONFIG_IO_DELAY_0XED is not set
-# CONFIG_IO_DELAY_NONE is not set
-CONFIG_IO_DELAY_TYPE_0X80=0
-CONFIG_IO_DELAY_TYPE_0XED=1
-CONFIG_IO_DELAY_TYPE_NONE=3
-CONFIG_IO_DELAY_TYPE_UDELAY=2
-# CONFIG_IO_DELAY_UDELAY is not set
-# CONFIG_IPWIRELESS is not set
-CONFIG_ISA=y
-CONFIG_ISAPNP=y
-CONFIG_ISA_DMA_API=y
-# CONFIG_IT8712F_WDT is not set
-# CONFIG_ITCO_WDT is not set
-CONFIG_KALLSYMS=y
-CONFIG_KEXEC=y
-CONFIG_KEYBOARD_ATKBD=y
-# CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_KEYBOARD_STOWAWAY is not set
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_KPROBES is not set
-CONFIG_KTIME_SCALAR=y
-# CONFIG_LANCE is not set
-# CONFIG_LATENCYTOP is not set
-# CONFIG_LEDS_ALIX is not set
-# CONFIG_LEDS_CLEVO_MAIL is not set
-CONFIG_LEDS_NET48XX=m
-# CONFIG_LEDS_WRAP is not set
-CONFIG_LZO_COMPRESS=m
-CONFIG_LZO_DECOMPRESS=m
-CONFIG_M386=y
-# CONFIG_M486 is not set
-# CONFIG_M586 is not set
-# CONFIG_M586MMX is not set
-# CONFIG_M586TSC is not set
-# CONFIG_M686 is not set
-# CONFIG_MACHZ_WDT is not set
-# CONFIG_MACINTOSH_DRIVERS is not set
-CONFIG_MATH_EMULATION=y
-# CONFIG_MCA is not set
-# CONFIG_MCORE2 is not set
-# CONFIG_MCRUSOE is not set
-# CONFIG_MCYRIXIII is not set
-# CONFIG_MDA_CONSOLE is not set
-# CONFIG_MEFFICEON is not set
-# CONFIG_MEMSTICK is not set
-# CONFIG_MGEODEGX1 is not set
-# CONFIG_MGEODE_LX is not set
-CONFIG_MICROCODE=y
-CONFIG_MICROCODE_OLD_INTERFACE=y
-# CONFIG_MIXCOMWD is not set
-# CONFIG_MK6 is not set
-# CONFIG_MK7 is not set
-# CONFIG_MK8 is not set
-CONFIG_MOUSE_PS2=y
-CONFIG_MOUSE_PS2_ALPS=y
-CONFIG_MOUSE_PS2_LIFEBOOK=y
-CONFIG_MOUSE_PS2_LOGIPS2PP=y
-CONFIG_MOUSE_PS2_SYNAPTICS=y
-# CONFIG_MOUSE_PS2_TOUCHKIT is not set
-CONFIG_MOUSE_PS2_TRACKPOINT=y
-# CONFIG_MOUSE_SERIAL is not set
-# CONFIG_MOUSE_VSXXXAA is not set
-# CONFIG_MPENTIUM4 is not set
-# CONFIG_MPENTIUMII is not set
-# CONFIG_MPENTIUMIII is not set
-# CONFIG_MPENTIUMM is not set
-# CONFIG_MPSC is not set
-CONFIG_MTD=y
-# CONFIG_MTD_ABSENT is not set
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_BLOCK2MTD=y
-# CONFIG_MTD_CFI is not set
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-CONFIG_MTD_CHAR=y
-# CONFIG_MTD_CMDLINE_PARTS is not set
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_CONCAT is not set
-# CONFIG_MTD_DEBUG is not set
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-# CONFIG_MTD_JEDECPROBE is not set
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_ONENAND is not set
-CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_PLATRAM is not set
-# CONFIG_MTD_PMC551 is not set
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_TS5500 is not set
-CONFIG_MTRR=y
-# CONFIG_MVIAC3_2 is not set
-# CONFIG_MVIAC7 is not set
-# CONFIG_MWINCHIP2 is not set
-# CONFIG_MWINCHIP3D is not set
-# CONFIG_MWINCHIPC6 is not set
-CONFIG_NAMESPACES=y
-CONFIG_NATSEMI=m
-CONFIG_NE2K_PCI=m
-CONFIG_NET_VENDOR_3COM=y
-# CONFIG_NET_VENDOR_RACAL is not set
-# CONFIG_NET_VENDOR_SMC is not set
-CONFIG_NOHIGHMEM=y
-CONFIG_NSC_GPIO=m
-CONFIG_NVRAM=y
-# CONFIG_OCF_OCF is not set
-CONFIG_PAGE_OFFSET=0xC0000000
-# CONFIG_PARAVIRT_GUEST is not set
-# CONFIG_PATA_CS5536 is not set
-CONFIG_PC8736x_GPIO=m
-# CONFIG_PC87413_WDT is not set
-CONFIG_PCCARD=m
-CONFIG_PCCARD_NONSTATIC=m
-CONFIG_PCI=y
-# CONFIG_PCIEPORTBUS is not set
-# CONFIG_PCIPCWATCHDOG is not set
-CONFIG_PCI_BIOS=y
-CONFIG_PCI_DIRECT=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_GOANY=y
-# CONFIG_PCI_GOBIOS is not set
-# CONFIG_PCI_GODIRECT is not set
-# CONFIG_PCI_GOMMCONFIG is not set
-CONFIG_PCMCIA=m
-CONFIG_PCMCIA_IOCTL=y
-CONFIG_PCMCIA_LOAD_CIS=y
-CONFIG_PCMCIA_PROBE=y
-CONFIG_PCNET32=m
-CONFIG_PCNET32_NAPI=y
-# CONFIG_PCWATCHDOG is not set
-CONFIG_PHYSICAL_ALIGN=0x100000
-CONFIG_PHYSICAL_START=0x100000
-CONFIG_PNP=y
-# CONFIG_PNPACPI is not set
-# CONFIG_PNPBIOS is not set
-# CONFIG_PNP_DEBUG is not set
-CONFIG_PROC_PAGE_MONITOR=y
-# CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set
-# CONFIG_R6040 is not set
-# CONFIG_RELOCATABLE is not set
-CONFIG_RTC=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
-# CONFIG_SBC7240_WDT is not set
-# CONFIG_SBC8360_WDT is not set
-# CONFIG_SBC_EPX_C3_WATCHDOG is not set
-CONFIG_SC1200_WDT=m
-# CONFIG_SC520_WDT is not set
-# CONFIG_SCC is not set
-# CONFIG_SCHED_HRTICK is not set
-CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
-# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
-CONFIG_SCSI_WAIT_SCAN=m
-CONFIG_SCx200=y
-CONFIG_SCx200HR_TIMER=y
-CONFIG_SCx200_ACB=m
-CONFIG_SCx200_GPIO=m
-CONFIG_SCx200_I2C=m
-CONFIG_SCx200_I2C_SCL=12
-CONFIG_SCx200_I2C_SDA=13
-CONFIG_SCx200_WDT=m
-CONFIG_SEMAPHORE_SLEEPERS=y
-CONFIG_SENSORS_PC87360=m
-# CONFIG_SERIAL_8250_CS is not set
-# CONFIG_SERIAL_8250_EXTENDED is not set
-CONFIG_SERIAL_8250_PCI=y
-CONFIG_SERIAL_8250_PNP=y
-CONFIG_SERIO=y
-# CONFIG_SERIO_CT82C710 is not set
-CONFIG_SERIO_I8042=y
-CONFIG_SERIO_LIBPS2=y
-# CONFIG_SERIO_PCIPS2 is not set
-# CONFIG_SERIO_RAW is not set
-CONFIG_SERIO_SERPORT=y
-CONFIG_SLABINFO=y
-# CONFIG_SMP is not set
-# CONFIG_SMSC37B787_WDT is not set
-CONFIG_SND_AC97_CODEC=m
-CONFIG_SND_HDA_CODEC_ANALOG=y
-CONFIG_SND_HDA_CODEC_ATIHDMI=y
-CONFIG_SND_HDA_CODEC_CMEDIA=y
-CONFIG_SND_HDA_CODEC_CONEXANT=y
-CONFIG_SND_HDA_CODEC_REALTEK=y
-CONFIG_SND_HDA_CODEC_SI3054=y
-CONFIG_SND_HDA_CODEC_SIGMATEL=y
-CONFIG_SND_HDA_CODEC_VIA=y
-CONFIG_SND_HDA_GENERIC=y
-# CONFIG_SND_HDA_HWDEP is not set
-CONFIG_SND_HDA_INTEL=m
-# CONFIG_SND_HDA_POWER_SAVE is not set
-CONFIG_SND_INTEL8X0=m
-# CONFIG_SND_SC6000 is not set
-# CONFIG_SND_SIS7019 is not set
-CONFIG_SOFT_WATCHDOG=m
-# CONFIG_SONYPI is not set
-CONFIG_SPARSEMEM_STATIC=y
-# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
-CONFIG_SSB_POSSIBLE=y
-CONFIG_SYSVIPC_SYSCTL=y
-# CONFIG_TCIC is not set
-# CONFIG_TELCLOCK is not set
-# CONFIG_THERMAL is not set
-# CONFIG_TICK_ONESHOT is not set
-# CONFIG_TOSHIBA is not set
-# CONFIG_TYPHOON is not set
-CONFIG_UID16=y
-CONFIG_USB=m
-# CONFIG_USBPCWATCHDOG is not set
-CONFIG_USB_EHCI_HCD=m
-# CONFIG_USB_NET_DM9601 is not set
-# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
-# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
-CONFIG_USB_OHCI_HCD=m
-# CONFIG_USB_R8A66597_HCD is not set
-# CONFIG_USB_SERIAL_OTI6858 is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_UHCI_HCD=m
-# CONFIG_USER_NS is not set
-# CONFIG_VGACON_SOFT_SCROLLBACK is not set
-# CONFIG_VGASTATE is not set
-CONFIG_VGA_CONSOLE=y
-CONFIG_VIA_RHINE=m
-CONFIG_VIA_RHINE_MMIO=y
-CONFIG_VIA_RHINE_NAPI=y
-# CONFIG_VIDEO_SELECT is not set
-CONFIG_VIDEO_V4L2_COMMON=m
-# CONFIG_VIRTUALIZATION is not set
-CONFIG_VM86=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_VORTEX=m
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-# CONFIG_WAFER_WDT is not set
-# CONFIG_WDT is not set
-CONFIG_X86=y
-CONFIG_X86_32=y
-# CONFIG_X86_64 is not set
-# CONFIG_X86_BIGSMP is not set
-CONFIG_X86_BIOS_REBOOT=y
-# CONFIG_X86_CMPXCHG is not set
-# CONFIG_X86_CPUFREQ_NFORCE2 is not set
-# CONFIG_X86_CPUID is not set
-# CONFIG_X86_ELAN is not set
-# CONFIG_X86_ES7000 is not set
-# CONFIG_X86_E_POWERSAVER is not set
-CONFIG_X86_F00F_BUG=y
-CONFIG_X86_FIND_SMP_CONFIG=y
-CONFIG_X86_GENERIC=y
-# CONFIG_X86_GENERICARCH is not set
-CONFIG_X86_GX_SUSPMOD=m
-CONFIG_X86_INTEL_USERCOPY=y
-CONFIG_X86_IO_APIC=y
-CONFIG_X86_L1_CACHE_SHIFT=7
-CONFIG_X86_LOCAL_APIC=y
-# CONFIG_X86_LONGRUN is not set
-CONFIG_X86_MCE=y
-# CONFIG_X86_MCE_NONFATAL is not set
-# CONFIG_X86_MCE_P4THERMAL is not set
-CONFIG_X86_MINIMUM_CPU_FAMILY=3
-CONFIG_X86_MPPARSE=y
-# CONFIG_X86_MSR is not set
-# CONFIG_X86_NUMAQ is not set
-# CONFIG_X86_P4_CLOCKMOD is not set
-# CONFIG_X86_PAE is not set
-CONFIG_X86_PC=y
-# CONFIG_X86_POWERNOW_K6 is not set
-# CONFIG_X86_POWERNOW_K7 is not set
-# CONFIG_X86_POWERNOW_K8 is not set
-CONFIG_X86_PPRO_FENCE=y
-# CONFIG_X86_RDC321X is not set
-# CONFIG_X86_REBOOTFIXUPS is not set
-# CONFIG_X86_SPEEDSTEP_CENTRINO is not set
-# CONFIG_X86_SPEEDSTEP_ICH is not set
-# CONFIG_X86_SPEEDSTEP_LIB is not set
-# CONFIG_X86_SPEEDSTEP_SMI is not set
-# CONFIG_X86_SUMMIT is not set
-CONFIG_X86_UP_APIC=y
-CONFIG_X86_UP_IOAPIC=y
-# CONFIG_X86_VISWS is not set
-# CONFIG_X86_VOYAGER is not set
-# CONFIG_X86_VSMP is not set
-CONFIG_YENTA_ENE_TUNE=y
-CONFIG_YENTA_O2=y
-CONFIG_YENTA_RICOH=y
-CONFIG_YENTA_TI=y
-CONFIG_YENTA_TOSHIBA=y
-# CONFIG_ZONE_DMA32 is not set
--- /dev/null
+# CONFIG_3C515 is not set
+# CONFIG_60XX_WDT is not set
+# CONFIG_64BIT is not set
+CONFIG_8139TOO=m
+# CONFIG_8139TOO_8129 is not set
+CONFIG_8139TOO_PIO=y
+# CONFIG_8139TOO_TUNE_TWISTER is not set
+# CONFIG_8139_OLD_RX_RESET is not set
+# CONFIG_AC3200 is not set
+CONFIG_AC97_BUS=m
+# CONFIG_ACQUIRE_WDT is not set
+# CONFIG_ADVANTECH_WDT is not set
+# CONFIG_AGP is not set
+# CONFIG_AIRO_CS is not set
+# CONFIG_ALIM1535_WDT is not set
+# CONFIG_ALIM7101_WDT is not set
+# CONFIG_APRICOT is not set
+CONFIG_ARCH_DEFCONFIG="arch/x86/configs/i386_defconfig"
+CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
+CONFIG_ARCH_HAS_CPU_RELAX=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_ARCH_SUPPORTS_MSI=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_AT1700 is not set
+CONFIG_ATA=m
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_ATA_PIIX=m
+# CONFIG_AUDIT_ARCH is not set
+CONFIG_BASE_SMALL=0
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_MISC=y
+CONFIG_BITREVERSE=y
+# CONFIG_BLK_DEV_4DRIVES is not set
+# CONFIG_BLK_DEV_ALI14XX is not set
+# CONFIG_BLK_DEV_DTC2278 is not set
+CONFIG_BLK_DEV_GENERIC=y
+# CONFIG_BLK_DEV_HT6560B is not set
+CONFIG_BLK_DEV_IDE=y
+CONFIG_BLK_DEV_IDEDISK=y
+CONFIG_BLK_DEV_IDEDMA=y
+CONFIG_BLK_DEV_IDEDMA_PCI=y
+CONFIG_BLK_DEV_IDEDMA_SFF=y
+CONFIG_BLK_DEV_IDEPCI=y
+# CONFIG_BLK_DEV_QD65XX is not set
+CONFIG_BLK_DEV_SC1200=y
+# CONFIG_BLK_DEV_UMC8672 is not set
+CONFIG_BLK_DEV_VIA82CXXX=y
+# CONFIG_BLK_DEV_XD is not set
+CONFIG_BOUNCE=y
+# CONFIG_BT_HIDP is not set
+CONFIG_CLASSIC_RCU=y
+CONFIG_CLOCKSOURCE_WATCHDOG=y
+CONFIG_COMPAT_VDSO=y
+# CONFIG_CPU5_WDT is not set
+CONFIG_CPU_FREQ=y
+# CONFIG_CPU_FREQ_DEBUG is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_STAT_DETAILS=y
+CONFIG_CPU_FREQ_TABLE=y
+# CONFIG_CPU_IDLE is not set
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_AES_586=m
+CONFIG_CRYPTO_AUTHENC=m
+CONFIG_CRYPTO_GF128MUL=m
+# CONFIG_CRYPTO_SALSA20_586 is not set
+CONFIG_CRYPTO_TWOFISH_586=m
+# CONFIG_CS5535_GPIO is not set
+# CONFIG_CS89x0 is not set
+# CONFIG_DCDBAS is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEFAULT_IO_DELAY_TYPE=0
+# CONFIG_DELL_RBU is not set
+# CONFIG_DEPCA is not set
+CONFIG_DEVPORT=y
+# CONFIG_DMADEVICES is not set
+# CONFIG_DMASCC is not set
+CONFIG_DMI=y
+# CONFIG_DMIID is not set
+CONFIG_DNOTIFY=y
+CONFIG_DOUBLEFAULT=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_E1000=m
+# CONFIG_E1000E_ENABLED is not set
+# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
+CONFIG_E1000_NAPI=y
+CONFIG_EARLY_PRINTK=y
+# CONFIG_EDAC is not set
+# CONFIG_EDD is not set
+# CONFIG_EISA is not set
+# CONFIG_EL1 is not set
+# CONFIG_EL16 is not set
+# CONFIG_EL2 is not set
+# CONFIG_EL3 is not set
+CONFIG_ELF_CORE=y
+# CONFIG_ELPLUS is not set
+# CONFIG_EMBEDDED is not set
+# CONFIG_EUROTECH_WDT is not set
+CONFIG_EXT2_FS=y
+CONFIG_FAST_CMPXCHG_LOCAL=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+# CONFIG_GENERIC_CPU is not set
+# CONFIG_GENERIC_GPIO is not set
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_ISA_DMA=y
+# CONFIG_GENERIC_LOCKBREAK is not set
+# CONFIG_GENERIC_TIME_VSYSCALL is not set
+# CONFIG_HANGCHECK_TIMER is not set
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_KVM=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
+CONFIG_HID=y
+CONFIG_HID_SUPPORT=y
+# CONFIG_HIGHMEM4G is not set
+# CONFIG_HIGHMEM64G is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+# CONFIG_HPET_TIMER is not set
+# CONFIG_HP_WATCHDOG is not set
+CONFIG_HT_IRQ=y
+# CONFIG_HUGETLBFS is not set
+CONFIG_HWMON=m
+# CONFIG_HWMON_DEBUG_CHIP is not set
+CONFIG_HWMON_VID=m
+CONFIG_HW_CONSOLE=y
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_AMD is not set
+CONFIG_HW_RANDOM_GEODE=y
+# CONFIG_HW_RANDOM_INTEL is not set
+CONFIG_HW_RANDOM_VIA=y
+CONFIG_I2C=m
+CONFIG_I2C_ALGOBIT=m
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=m
+# CONFIG_I6300ESB_WDT is not set
+# CONFIG_I82365 is not set
+# CONFIG_I8K is not set
+# CONFIG_IB700_WDT is not set
+# CONFIG_IBMASR is not set
+# CONFIG_IBM_ASM is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+CONFIG_IDE=y
+CONFIG_IDEPCI_PCIBUS_ORDER=y
+CONFIG_IDE_ARCH_OBSOLETE_INIT=y
+CONFIG_IDE_GENERIC=y
+# CONFIG_IDE_PROC_FS is not set
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=y
+# CONFIG_INPUT_EVDEV is not set
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_INPUT_MOUSE=y
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_IOMMU_HELPER is not set
+CONFIG_IO_DELAY_0X80=y
+# CONFIG_IO_DELAY_0XED is not set
+# CONFIG_IO_DELAY_NONE is not set
+CONFIG_IO_DELAY_TYPE_0X80=0
+CONFIG_IO_DELAY_TYPE_0XED=1
+CONFIG_IO_DELAY_TYPE_NONE=3
+CONFIG_IO_DELAY_TYPE_UDELAY=2
+# CONFIG_IO_DELAY_UDELAY is not set
+# CONFIG_IPWIRELESS is not set
+CONFIG_ISA=y
+CONFIG_ISAPNP=y
+CONFIG_ISA_DMA_API=y
+# CONFIG_IT8712F_WDT is not set
+# CONFIG_ITCO_WDT is not set
+CONFIG_KALLSYMS=y
+CONFIG_KEXEC=y
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KPROBES is not set
+CONFIG_KTIME_SCALAR=y
+# CONFIG_LANCE is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_LEDS_ALIX is not set
+# CONFIG_LEDS_CLEVO_MAIL is not set
+CONFIG_LEDS_NET48XX=m
+# CONFIG_LEDS_WRAP is not set
+CONFIG_LZO_COMPRESS=m
+CONFIG_LZO_DECOMPRESS=m
+CONFIG_M386=y
+# CONFIG_M486 is not set
+# CONFIG_M586 is not set
+# CONFIG_M586MMX is not set
+# CONFIG_M586TSC is not set
+# CONFIG_M686 is not set
+# CONFIG_MACHZ_WDT is not set
+# CONFIG_MACINTOSH_DRIVERS is not set
+CONFIG_MATH_EMULATION=y
+# CONFIG_MCA is not set
+# CONFIG_MCORE2 is not set
+# CONFIG_MCRUSOE is not set
+# CONFIG_MCYRIXIII is not set
+# CONFIG_MDA_CONSOLE is not set
+# CONFIG_MEFFICEON is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_MGEODEGX1 is not set
+# CONFIG_MGEODE_LX is not set
+CONFIG_MICROCODE=y
+CONFIG_MICROCODE_OLD_INTERFACE=y
+# CONFIG_MIXCOMWD is not set
+# CONFIG_MK6 is not set
+# CONFIG_MK7 is not set
+# CONFIG_MK8 is not set
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LIFEBOOK=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MPENTIUM4 is not set
+# CONFIG_MPENTIUMII is not set
+# CONFIG_MPENTIUMIII is not set
+# CONFIG_MPENTIUMM is not set
+# CONFIG_MPSC is not set
+CONFIG_MTD=y
+# CONFIG_MTD_ABSENT is not set
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_BLOCK2MTD=y
+# CONFIG_MTD_CFI is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CHAR=y
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_CONCAT is not set
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_ONENAND is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_PLATRAM is not set
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_TS5500 is not set
+CONFIG_MTRR=y
+# CONFIG_MVIAC3_2 is not set
+# CONFIG_MVIAC7 is not set
+# CONFIG_MWINCHIP2 is not set
+# CONFIG_MWINCHIP3D is not set
+# CONFIG_MWINCHIPC6 is not set
+CONFIG_NAMESPACES=y
+CONFIG_NATSEMI=m
+CONFIG_NE2K_PCI=m
+CONFIG_NET_VENDOR_3COM=y
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_NET_VENDOR_SMC is not set
+CONFIG_NOHIGHMEM=y
+CONFIG_NSC_GPIO=m
+CONFIG_NVRAM=y
+# CONFIG_OCF_OCF is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PARAVIRT_GUEST is not set
+# CONFIG_PATA_CS5536 is not set
+CONFIG_PC8736x_GPIO=m
+# CONFIG_PC87413_WDT is not set
+CONFIG_PCCARD=m
+CONFIG_PCCARD_NONSTATIC=m
+CONFIG_PCI=y
+# CONFIG_PCIEPORTBUS is not set
+# CONFIG_PCIPCWATCHDOG is not set
+CONFIG_PCI_BIOS=y
+CONFIG_PCI_DIRECT=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_GOANY=y
+# CONFIG_PCI_GOBIOS is not set
+# CONFIG_PCI_GODIRECT is not set
+# CONFIG_PCI_GOMMCONFIG is not set
+CONFIG_PCMCIA=m
+CONFIG_PCMCIA_IOCTL=y
+CONFIG_PCMCIA_LOAD_CIS=y
+CONFIG_PCMCIA_PROBE=y
+CONFIG_PCNET32=m
+CONFIG_PCNET32_NAPI=y
+# CONFIG_PCWATCHDOG is not set
+CONFIG_PHYSICAL_ALIGN=0x100000
+CONFIG_PHYSICAL_START=0x100000
+CONFIG_PNP=y
+# CONFIG_PNPACPI is not set
+# CONFIG_PNPBIOS is not set
+# CONFIG_PNP_DEBUG is not set
+CONFIG_PROC_PAGE_MONITOR=y
+# CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set
+# CONFIG_R6040 is not set
+# CONFIG_RELOCATABLE is not set
+CONFIG_RTC=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+# CONFIG_SBC7240_WDT is not set
+# CONFIG_SBC8360_WDT is not set
+# CONFIG_SBC_EPX_C3_WATCHDOG is not set
+CONFIG_SC1200_WDT=m
+# CONFIG_SC520_WDT is not set
+# CONFIG_SCC is not set
+# CONFIG_SCHED_HRTICK is not set
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
+CONFIG_SCSI_WAIT_SCAN=m
+CONFIG_SCx200=y
+CONFIG_SCx200HR_TIMER=y
+CONFIG_SCx200_ACB=m
+CONFIG_SCx200_GPIO=m
+CONFIG_SCx200_I2C=m
+CONFIG_SCx200_I2C_SCL=12
+CONFIG_SCx200_I2C_SDA=13
+CONFIG_SCx200_WDT=m
+CONFIG_SEMAPHORE_SLEEPERS=y
+CONFIG_SENSORS_PC87360=m
+# CONFIG_SERIAL_8250_CS is not set
+# CONFIG_SERIAL_8250_EXTENDED is not set
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_PNP=y
+CONFIG_SERIO=y
+# CONFIG_SERIO_CT82C710 is not set
+CONFIG_SERIO_I8042=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_PCIPS2 is not set
+# CONFIG_SERIO_RAW is not set
+CONFIG_SERIO_SERPORT=y
+CONFIG_SLABINFO=y
+# CONFIG_SMP is not set
+# CONFIG_SMSC37B787_WDT is not set
+CONFIG_SND_AC97_CODEC=m
+CONFIG_SND_HDA_CODEC_ANALOG=y
+CONFIG_SND_HDA_CODEC_ATIHDMI=y
+CONFIG_SND_HDA_CODEC_CMEDIA=y
+CONFIG_SND_HDA_CODEC_CONEXANT=y
+CONFIG_SND_HDA_CODEC_REALTEK=y
+CONFIG_SND_HDA_CODEC_SI3054=y
+CONFIG_SND_HDA_CODEC_SIGMATEL=y
+CONFIG_SND_HDA_CODEC_VIA=y
+CONFIG_SND_HDA_GENERIC=y
+# CONFIG_SND_HDA_HWDEP is not set
+CONFIG_SND_HDA_INTEL=m
+# CONFIG_SND_HDA_POWER_SAVE is not set
+CONFIG_SND_INTEL8X0=m
+# CONFIG_SND_SC6000 is not set
+# CONFIG_SND_SIS7019 is not set
+CONFIG_SOFT_WATCHDOG=m
+# CONFIG_SONYPI is not set
+CONFIG_SPARSEMEM_STATIC=y
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SSB_POSSIBLE=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_TCIC is not set
+# CONFIG_TELCLOCK is not set
+# CONFIG_THERMAL is not set
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_TOSHIBA is not set
+# CONFIG_TYPHOON is not set
+CONFIG_UID16=y
+CONFIG_USB=m
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_USB_EHCI_HCD=m
+# CONFIG_USB_NET_DM9601 is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_HCD=m
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_SERIAL_OTI6858 is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_UHCI_HCD=m
+# CONFIG_USER_NS is not set
+# CONFIG_VGACON_SOFT_SCROLLBACK is not set
+# CONFIG_VGASTATE is not set
+CONFIG_VGA_CONSOLE=y
+CONFIG_VIA_RHINE=m
+CONFIG_VIA_RHINE_MMIO=y
+CONFIG_VIA_RHINE_NAPI=y
+# CONFIG_VIDEO_SELECT is not set
+CONFIG_VIDEO_V4L2_COMMON=m
+# CONFIG_VIRTUALIZATION is not set
+CONFIG_VM86=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VORTEX=m
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_WAFER_WDT is not set
+# CONFIG_WDT is not set
+CONFIG_X86=y
+CONFIG_X86_32=y
+# CONFIG_X86_64 is not set
+# CONFIG_X86_BIGSMP is not set
+CONFIG_X86_BIOS_REBOOT=y
+# CONFIG_X86_CMPXCHG is not set
+# CONFIG_X86_CPUFREQ_NFORCE2 is not set
+# CONFIG_X86_CPUID is not set
+# CONFIG_X86_ELAN is not set
+# CONFIG_X86_ES7000 is not set
+# CONFIG_X86_E_POWERSAVER is not set
+CONFIG_X86_F00F_BUG=y
+CONFIG_X86_FIND_SMP_CONFIG=y
+CONFIG_X86_GENERIC=y
+# CONFIG_X86_GENERICARCH is not set
+CONFIG_X86_GX_SUSPMOD=m
+CONFIG_X86_INTEL_USERCOPY=y
+CONFIG_X86_IO_APIC=y
+CONFIG_X86_L1_CACHE_SHIFT=7
+CONFIG_X86_LOCAL_APIC=y
+# CONFIG_X86_LONGRUN is not set
+CONFIG_X86_MCE=y
+# CONFIG_X86_MCE_NONFATAL is not set
+# CONFIG_X86_MCE_P4THERMAL is not set
+CONFIG_X86_MINIMUM_CPU_FAMILY=3
+CONFIG_X86_MPPARSE=y
+# CONFIG_X86_MSR is not set
+# CONFIG_X86_NUMAQ is not set
+# CONFIG_X86_P4_CLOCKMOD is not set
+# CONFIG_X86_PAE is not set
+CONFIG_X86_PC=y
+# CONFIG_X86_POWERNOW_K6 is not set
+# CONFIG_X86_POWERNOW_K7 is not set
+# CONFIG_X86_POWERNOW_K8 is not set
+CONFIG_X86_PPRO_FENCE=y
+# CONFIG_X86_RDC321X is not set
+# CONFIG_X86_REBOOTFIXUPS is not set
+# CONFIG_X86_SPEEDSTEP_CENTRINO is not set
+# CONFIG_X86_SPEEDSTEP_ICH is not set
+# CONFIG_X86_SPEEDSTEP_LIB is not set
+# CONFIG_X86_SPEEDSTEP_SMI is not set
+# CONFIG_X86_SUMMIT is not set
+CONFIG_X86_UP_APIC=y
+CONFIG_X86_UP_IOAPIC=y
+# CONFIG_X86_VISWS is not set
+# CONFIG_X86_VOYAGER is not set
+# CONFIG_X86_VSMP is not set
+CONFIG_YENTA_ENE_TUNE=y
+CONFIG_YENTA_O2=y
+CONFIG_YENTA_RICOH=y
+CONFIG_YENTA_TI=y
+CONFIG_YENTA_TOSHIBA=y
+# CONFIG_ZONE_DMA32 is not set
projects / openwrt / svn-archive / archive.git / commitdiff