sparc64: Fix Niagara2 perf event handling.

For chips like Niagara2 that have true overflow indications
in the %pcr (which we don't actually need and don't use)
the interrupt signal persists until the overflow bits are
cleared by an explicit %pcr write.

Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c
index fa5936e1c3b9e8d632c024d5dd6ea0ce8863eba1..198fb4e79ba2875289a58cae60acb47c3442fb23 100644 (file)
--- a/arch/sparc/kernel/perf_event.c
+++ b/arch/sparc/kernel/perf_event.c
@@ -986,6 +986,17 @@ static int __kprobes perf_event_nmi_handler(struct notifier_block *self,
        data.addr = 0;
 
        cpuc = &__get_cpu_var(cpu_hw_events);
+
+       /* If the PMU has the TOE IRQ enable bits, we need to do a
+        * dummy write to the %pcr to clear the overflow bits and thus
+        * the interrupt.
+        *
+        * Do this before we peek at the counters to determine
+        * overflow so we don't lose any events.
+        */
+       if (sparc_pmu->irq_bit)
+               pcr_ops->write(cpuc->pcr);
+
        for (idx = 0; idx < MAX_HWEVENTS; idx++) {
                struct perf_event *event = cpuc->events[idx];
                struct hw_perf_event *hwc;