MIPS: Loongson: Fix GENMASK misuse

Arguments are supposed to be ordered high then low.

Fixes: 6a6f9b7dafd50efc1b2 ("MIPS: Loongson: Add CFUCFG&CSR support")
Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com>
Reviewed-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Paul Burton <paulburton@kernel.org>
Cc: chenhuacai@gmail.com
Cc: jhogan@kernel.org
Cc: jiaxun.yang@flygoat.com
Cc: linux-mips@linux-mips.org
Cc: linux-mips@vger.kernel.org
Cc: paul.burton@mips.com
Cc: ralf@linux-mips.org
Cc: wuzhangjin@gmail.com
Cc: zhangfx@lemote.com

diff --git a/arch/mips/include/asm/mach-loongson64/loongson_regs.h b/arch/mips/include/asm/mach-loongson64/loongson_regs.h
index 6e3569ab8936ed048c318bfa1c04605d9e84c4a1..363a47a5d26e8a10594ba8aa197c09e1eeeac9bc 100644 (file)
--- a/arch/mips/include/asm/mach-loongson64/loongson_regs.h
+++ b/arch/mips/include/asm/mach-loongson64/loongson_regs.h
@@ -86,7 +86,7 @@ static inline u32 read_cpucfg(u32 reg)
 #define LOONGSON_CFG2_LGFTP    BIT(19)
 #define LOONGSON_CFG2_LGFTPREV GENMASK(22, 20)
 #define LOONGSON_CFG2_LLFTP    BIT(23)
-#define LOONGSON_CFG2_LLFTPREV GENMASK(24, 26)
+#define LOONGSON_CFG2_LLFTPREV GENMASK(26, 24)
 #define LOONGSON_CFG2_LCSRP    BIT(27)
 #define LOONGSON_CFG2_LDISBLIKELY      BIT(28)