Merge branch 'drm-intel-fixes' into drm-intel-next

diff --cc drivers/gpu/drm/i915/i915_dma.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_drv.h
index 78cdd158287aee6d2ff6f981ac961c745f12affa,ce7914c4c044662153545e7c2d87e277432fbc34..6867e193d85e6f9e8b9ab07eadef040f42904624
--- 1/drivers/gpu/drm/i915/i915_drv.h
--- 2/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@@ -264,9 -262,9 +264,10 @@@ enum intel_pch 
  };
  
  #define QUIRK_PIPEA_FORCE (1<<0)
+ #define QUIRK_LVDS_SSC_DISABLE (1<<1)
  
  struct intel_fbdev;
 +struct intel_fbc_work;
  
  typedef struct drm_i915_private {
        struct drm_device *dev;
@@@ -1199,11 -1195,10 +1200,13 @@@ void i915_gem_free_all_phys_object(stru
  void i915_gem_release(struct drm_device *dev, struct drm_file *file);
  
  uint32_t
- i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj);
+ i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
+                                   uint32_t size,
+                                   int tiling_mode);
  
 +int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
 +                                  enum i915_cache_level cache_level);
 +
  /* i915_gem_gtt.c */
  void i915_gem_restore_gtt_mappings(struct drm_device *dev);
  int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj);

diff --cc drivers/gpu/drm/i915/i915_gem.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_display.c
index 261ffe47a5d24132c94f04e487dd9715752912e0,5609c065aaf4a92206a34277b2fe2a78f23096c2..97d28013db795559ae730ef2ee26209cd6d410d5
--- 1/drivers/gpu/drm/i915/intel_display.c
--- 2/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@@ -4469,136 -4309,10 +4473,137 @@@ static void intel_update_watermarks(str
  
  static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
  {
-       return dev_priv->lvds_use_ssc && i915_panel_use_ssc;
+       return dev_priv->lvds_use_ssc && i915_panel_use_ssc
+               && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
  }
  
 +/**
 + * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
 + * @crtc: CRTC structure
 + *
 + * A pipe may be connected to one or more outputs.  Based on the depth of the
 + * attached framebuffer, choose a good color depth to use on the pipe.
 + *
 + * If possible, match the pipe depth to the fb depth.  In some cases, this
 + * isn't ideal, because the connected output supports a lesser or restricted
 + * set of depths.  Resolve that here:
 + *    LVDS typically supports only 6bpc, so clamp down in that case
 + *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
 + *    Displays may support a restricted set as well, check EDID and clamp as
 + *      appropriate.
 + *
 + * RETURNS:
 + * Dithering requirement (i.e. false if display bpc and pipe bpc match,
 + * true if they don't match).
 + */
 +static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
 +                                       unsigned int *pipe_bpp)
 +{
 +      struct drm_device *dev = crtc->dev;
 +      struct drm_i915_private *dev_priv = dev->dev_private;
 +      struct drm_encoder *encoder;
 +      struct drm_connector *connector;
 +      unsigned int display_bpc = UINT_MAX, bpc;
 +
 +      /* Walk the encoders & connectors on this crtc, get min bpc */
 +      list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 +              struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
 +
 +              if (encoder->crtc != crtc)
 +                      continue;
 +
 +              if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
 +                      unsigned int lvds_bpc;
 +
 +                      if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
 +                          LVDS_A3_POWER_UP)
 +                              lvds_bpc = 8;
 +                      else
 +                              lvds_bpc = 6;
 +
 +                      if (lvds_bpc < display_bpc) {
 +                              DRM_DEBUG_DRIVER("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
 +                              display_bpc = lvds_bpc;
 +                      }
 +                      continue;
 +              }
 +
 +              if (intel_encoder->type == INTEL_OUTPUT_EDP) {
 +                      /* Use VBT settings if we have an eDP panel */
 +                      unsigned int edp_bpc = dev_priv->edp.bpp / 3;
 +
 +                      if (edp_bpc < display_bpc) {
 +                              DRM_DEBUG_DRIVER("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
 +                              display_bpc = edp_bpc;
 +                      }
 +                      continue;
 +              }
 +
 +              /* Not one of the known troublemakers, check the EDID */
 +              list_for_each_entry(connector, &dev->mode_config.connector_list,
 +                                  head) {
 +                      if (connector->encoder != encoder)
 +                              continue;
 +
 +                      if (connector->display_info.bpc < display_bpc) {
 +                              DRM_DEBUG_DRIVER("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
 +                              display_bpc = connector->display_info.bpc;
 +                      }
 +              }
 +
 +              /*
 +               * HDMI is either 12 or 8, so if the display lets 10bpc sneak
 +               * through, clamp it down.  (Note: >12bpc will be caught below.)
 +               */
 +              if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
 +                      if (display_bpc > 8 && display_bpc < 12) {
 +                              DRM_DEBUG_DRIVER("forcing bpc to 12 for HDMI\n");
 +                              display_bpc = 12;
 +                      } else {
 +                              DRM_DEBUG_DRIVER("forcing bpc to 8 for HDMI\n");
 +                              display_bpc = 8;
 +                      }
 +              }
 +      }
 +
 +      /*
 +       * We could just drive the pipe at the highest bpc all the time and
 +       * enable dithering as needed, but that costs bandwidth.  So choose
 +       * the minimum value that expresses the full color range of the fb but
 +       * also stays within the max display bpc discovered above.
 +       */
 +
 +      switch (crtc->fb->depth) {
 +      case 8:
 +              bpc = 8; /* since we go through a colormap */
 +              break;
 +      case 15:
 +      case 16:
 +              bpc = 6; /* min is 18bpp */
 +              break;
 +      case 24:
 +              bpc = min((unsigned int)8, display_bpc);
 +              break;
 +      case 30:
 +              bpc = min((unsigned int)10, display_bpc);
 +              break;
 +      case 48:
 +              bpc = min((unsigned int)12, display_bpc);
 +              break;
 +      default:
 +              DRM_DEBUG("unsupported depth, assuming 24 bits\n");
 +              bpc = min((unsigned int)8, display_bpc);
 +              break;
 +      }
 +
 +      DRM_DEBUG_DRIVER("setting pipe bpc to %d (max display bpc %d)\n",
 +                       bpc, display_bpc);
 +
 +      *pipe_bpp = bpc * 3;
 +
 +      return display_bpc != bpc;
 +}
 +
  static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
                              struct drm_display_mode *mode,
                              struct drm_display_mode *adjusted_mode,

diff --cc drivers/gpu/drm/i915/intel_ringbuffer.c
Simple merge