drm/i915: Clean up rotation DSPCNTR/DVSCNTR/etc. setup

Move the plane control register rotation setup away from the
coordinate munging code. This will result in neater looking
code once we add reflection support for CHV.

v2: Drop the BIT(), drop some usless parens,

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1479142440-25283-3-git-send-email-ville.syrjala@linux.intel.com

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 10dd1ef57c30991eeb78a7d7a7ad5825dd2edc4c..ecc7b5b444f61434405e0b5359a32ee4d2f68763 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3075,6 +3075,9 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
            fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
                dspcntr |= DISPPLANE_TILED;
 
+       if (rotation & DRM_ROTATE_180)
+               dspcntr |= DISPPLANE_ROTATE_180;
+
        if (IS_G4X(dev_priv))
                dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
 
@@ -3085,10 +3088,8 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
                        intel_compute_tile_offset(&x, &y, plane_state, 0);
 
        if (rotation & DRM_ROTATE_180) {
-               dspcntr |= DISPPLANE_ROTATE_180;
-
-               x += (crtc_state->pipe_src_w - 1);
-               y += (crtc_state->pipe_src_h - 1);
+               x += crtc_state->pipe_src_w - 1;
+               y += crtc_state->pipe_src_h - 1;
        }
 
        linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
@@ -3180,6 +3181,9 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
        if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
                dspcntr |= DISPPLANE_TILED;
 
+       if (rotation & DRM_ROTATE_180)
+               dspcntr |= DISPPLANE_ROTATE_180;
+
        if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv))
                dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
 
@@ -3188,13 +3192,11 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
        intel_crtc->dspaddr_offset =
                intel_compute_tile_offset(&x, &y, plane_state, 0);
 
-       if (rotation & DRM_ROTATE_180) {
-               dspcntr |= DISPPLANE_ROTATE_180;
-
-               if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
-                       x += (crtc_state->pipe_src_w - 1);
-                       y += (crtc_state->pipe_src_h - 1);
-               }
+       /* HSW+ does this automagically in hardware */
+       if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv) &&
+           rotation & DRM_ROTATE_180) {
+               x += crtc_state->pipe_src_w - 1;
+               y += crtc_state->pipe_src_h - 1;
        }
 
        linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);

diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index ea85d27af21787c4db5a72f3289f2fc0579a1714..7951b70bf792e2cad67ff02b1ec08a336bb8d548 100644 (file)
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -427,6 +427,9 @@ vlv_update_plane(struct drm_plane *dplane,
        if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
                sprctl |= SP_TILED;
 
+       if (rotation & DRM_ROTATE_180)
+               sprctl |= SP_ROTATE_180;
+
        /* Sizes are 0 based */
        src_w--;
        src_h--;
@@ -437,8 +440,6 @@ vlv_update_plane(struct drm_plane *dplane,
        sprsurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
 
        if (rotation & DRM_ROTATE_180) {
-               sprctl |= SP_ROTATE_180;
-
                x += src_w;
                y += src_h;
        }
@@ -546,6 +547,9 @@ ivb_update_plane(struct drm_plane *plane,
        if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
                sprctl |= SPRITE_TILED;
 
+       if (rotation & DRM_ROTATE_180)
+               sprctl |= SPRITE_ROTATE_180;
+
        if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
                sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;
        else
@@ -566,14 +570,11 @@ ivb_update_plane(struct drm_plane *plane,
        intel_add_fb_offsets(&x, &y, plane_state, 0);
        sprsurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
 
-       if (rotation & DRM_ROTATE_180) {
-               sprctl |= SPRITE_ROTATE_180;
-
-               /* HSW and BDW does this automagically in hardware */
-               if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
-                       x += src_w;
-                       y += src_h;
-               }
+       /* HSW+ does this automagically in hardware */
+       if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv) &&
+           rotation & DRM_ROTATE_180) {
+               x += src_w;
+               y += src_h;
        }
 
        linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
@@ -684,6 +685,9 @@ ilk_update_plane(struct drm_plane *plane,
        if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
                dvscntr |= DVS_TILED;
 
+       if (rotation & DRM_ROTATE_180)
+               dvscntr |= DVS_ROTATE_180;
+
        if (IS_GEN6(dev_priv))
                dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
 
@@ -701,8 +705,6 @@ ilk_update_plane(struct drm_plane *plane,
        dvssurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
 
        if (rotation & DRM_ROTATE_180) {
-               dvscntr |= DVS_ROTATE_180;
-
                x += src_w;
                y += src_h;
        }