The clock phase properties are having two uint32 values. The minItems
and maxItems are set to 2 for the same. So the property type should be
'uint32-array' and not 'uint32'. Modify it to correct the same.
Reported-by: Rob Herring <robh@kernel.org>
Signed-off-by: Manish Narani <manish.narani@xilinx.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
- reg
"^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$":
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 2
maxItems: 2
- allOf:
- - $ref: /schemas/types.yaml#/definitions/uint32
- - minimum: 0
- maximum: 359
- description:
- Set the clock (phase) delays which are to be configured in the
- controller while switching to particular speed mode. These values
- are in pair of degrees.
+ items:
+ minimum: 0
+ maximum: 359
+ description:
+ Set the clock (phase) delays which are to be configured in the
+ controller while switching to particular speed mode. These values
+ are in pair of degrees.
dependencies:
cd-debounce-delay-ms: [ cd-gpios ]