gpu: host1x: Program the channel stream ID
authorThierry Reding <treding@nvidia.com>
Fri, 1 Feb 2019 13:28:23 +0000 (14:28 +0100)
committerThierry Reding <treding@nvidia.com>
Thu, 7 Feb 2019 17:28:33 +0000 (18:28 +0100)
When processing command streams, make sure the host1x's stream ID is
programmed for the channel so that addresses are properly translated
through the SMMU.

Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/gpu/host1x/hw/channel_hw.c
drivers/gpu/host1x/hw/host1x06_hardware.h
drivers/gpu/host1x/hw/host1x07_hardware.h
drivers/gpu/host1x/hw/hw_host1x06_channel.h [new file with mode: 0644]
drivers/gpu/host1x/hw/hw_host1x07_channel.h [new file with mode: 0644]

index 95ea81172a83460d95139428d64f980f460c3263..3067af4452cddf632497a7cf18bb25ef3b7c7f97 100644 (file)
@@ -17,6 +17,7 @@
  */
 
 #include <linux/host1x.h>
+#include <linux/iommu.h>
 #include <linux/slab.h>
 
 #include <trace/events/host1x.h>
@@ -89,6 +90,16 @@ static inline void synchronize_syncpt_base(struct host1x_job *job)
                         HOST1X_UCLASS_LOAD_SYNCPT_BASE_VALUE_F(value));
 }
 
+static void host1x_channel_set_streamid(struct host1x_channel *channel)
+{
+#if HOST1X_HW >= 6
+       struct iommu_fwspec *spec = dev_iommu_fwspec_get(channel->dev->parent);
+       u32 sid = spec ? spec->ids[0] & 0xffff : 0x7f;
+
+       host1x_ch_writel(channel, sid, HOST1X_CHANNEL_SMMU_STREAMID);
+#endif
+}
+
 static int channel_submit(struct host1x_job *job)
 {
        struct host1x_channel *ch = job->channel;
@@ -120,6 +131,8 @@ static int channel_submit(struct host1x_job *job)
                goto error;
        }
 
+       host1x_channel_set_streamid(ch);
+
        /* begin a CDMA submit */
        err = host1x_cdma_begin(&ch->cdma, job);
        if (err) {
index 3039c92ea605ca8b2b864f63e6f39da1f70aef64..eab753b91f2403bc7e6363c4c12e3bd587361bb9 100644 (file)
@@ -22,6 +22,7 @@
 #include <linux/types.h>
 #include <linux/bitops.h>
 
+#include "hw_host1x06_channel.h"
 #include "hw_host1x06_uclass.h"
 #include "hw_host1x06_vm.h"
 #include "hw_host1x06_hypervisor.h"
index 1353e7ab71dd49686327d44cb89e7b524c34d2a3..a79f57dc87bbf1c2ce01239bd4956baf0a0f0c79 100644 (file)
@@ -22,6 +22,7 @@
 #include <linux/types.h>
 #include <linux/bitops.h>
 
+#include "hw_host1x07_channel.h"
 #include "hw_host1x07_uclass.h"
 #include "hw_host1x07_vm.h"
 #include "hw_host1x07_hypervisor.h"
diff --git a/drivers/gpu/host1x/hw/hw_host1x06_channel.h b/drivers/gpu/host1x/hw/hw_host1x06_channel.h
new file mode 100644 (file)
index 0000000..18ae1c5
--- /dev/null
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 NVIDIA Corporation.
+ */
+
+#ifndef HOST1X_HW_HOST1X06_CHANNEL_H
+#define HOST1X_HW_HOST1X06_CHANNEL_H
+
+#define HOST1X_CHANNEL_SMMU_STREAMID 0x084
+
+#endif
diff --git a/drivers/gpu/host1x/hw/hw_host1x07_channel.h b/drivers/gpu/host1x/hw/hw_host1x07_channel.h
new file mode 100644 (file)
index 0000000..96fa72b
--- /dev/null
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 NVIDIA Corporation.
+ */
+
+#ifndef HOST1X_HW_HOST1X07_CHANNEL_H
+#define HOST1X_HW_HOST1X07_CHANNEL_H
+
+#define HOST1X_CHANNEL_SMMU_STREAMID 0x084
+
+#endif