-LINUX_VERSION-6.6 = .28
-LINUX_KERNEL_HASH-6.6.28 = 818716ed13e7dba6aaeae24e3073993e260812ed128d10272e94b922ee6d3394
+LINUX_VERSION-6.6 = .29
+LINUX_KERNEL_HASH-6.6.29 = 7f26f74c08082c86b1daf866e4d49c5d8276cc1906a89d0e367e457ec167cbd0
if (xhci->quirks & XHCI_NEC_HOST)
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
-@@ -1907,6 +1907,7 @@ struct xhci_hcd {
+@@ -1912,6 +1912,7 @@ struct xhci_hcd {
#define XHCI_RESET_TO_DEFAULT BIT_ULL(44)
#define XHCI_ZHAOXIN_TRB_FETCH BIT_ULL(45)
#define XHCI_ZHAOXIN_HOST BIT_ULL(46)
+++ /dev/null
-From: Pablo Neira Ayuso <pablo@netfilter.org>
-Date: Thu, 11 Apr 2024 13:28:59 +0200
-Subject: [PATCH] netfilter: flowtable: validate pppoe header
-
-Ensure there is sufficient room to access the protocol field of the
-PPPoe header. Validate it once before the flowtable lookup, then use a
-helper function to access protocol field.
-
-Reported-by: syzbot+b6f07e1c07ef40199081@syzkaller.appspotmail.com
-Fixes: 72efd585f714 ("netfilter: flowtable: add pppoe support")
-Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
----
-
---- a/include/net/netfilter/nf_flow_table.h
-+++ b/include/net/netfilter/nf_flow_table.h
-@@ -335,7 +335,7 @@ int nf_flow_rule_route_ipv6(struct net *
- int nf_flow_table_offload_init(void);
- void nf_flow_table_offload_exit(void);
-
--static inline __be16 nf_flow_pppoe_proto(const struct sk_buff *skb)
-+static inline __be16 __nf_flow_pppoe_proto(const struct sk_buff *skb)
- {
- __be16 proto;
-
-@@ -351,6 +351,16 @@ static inline __be16 nf_flow_pppoe_proto
- return 0;
- }
-
-+static inline bool nf_flow_pppoe_proto(struct sk_buff *skb, __be16 *inner_proto)
-+{
-+ if (!pskb_may_pull(skb, PPPOE_SES_HLEN))
-+ return false;
-+
-+ *inner_proto = __nf_flow_pppoe_proto(skb);
-+
-+ return true;
-+}
-+
- #define NF_FLOW_TABLE_STAT_INC(net, count) __this_cpu_inc((net)->ft.stat->count)
- #define NF_FLOW_TABLE_STAT_DEC(net, count) __this_cpu_dec((net)->ft.stat->count)
- #define NF_FLOW_TABLE_STAT_INC_ATOMIC(net, count) \
---- a/net/netfilter/nf_flow_table_inet.c
-+++ b/net/netfilter/nf_flow_table_inet.c
-@@ -21,7 +21,8 @@ nf_flow_offload_inet_hook(void *priv, st
- proto = veth->h_vlan_encapsulated_proto;
- break;
- case htons(ETH_P_PPP_SES):
-- proto = nf_flow_pppoe_proto(skb);
-+ if (!nf_flow_pppoe_proto(skb, &proto))
-+ return NF_ACCEPT;
- break;
- default:
- proto = skb->protocol;
---- a/net/netfilter/nf_flow_table_ip.c
-+++ b/net/netfilter/nf_flow_table_ip.c
-@@ -273,10 +273,11 @@ static unsigned int nf_flow_xmit_xfrm(st
- return NF_STOLEN;
- }
-
--static bool nf_flow_skb_encap_protocol(const struct sk_buff *skb, __be16 proto,
-+static bool nf_flow_skb_encap_protocol(struct sk_buff *skb, __be16 proto,
- u32 *offset)
- {
- struct vlan_ethhdr *veth;
-+ __be16 inner_proto;
-
- switch (skb->protocol) {
- case htons(ETH_P_8021Q):
-@@ -287,7 +288,8 @@ static bool nf_flow_skb_encap_protocol(c
- }
- break;
- case htons(ETH_P_PPP_SES):
-- if (nf_flow_pppoe_proto(skb) == proto) {
-+ if (nf_flow_pppoe_proto(skb, &inner_proto) &&
-+ inner_proto == proto) {
- *offset += PPPOE_SES_HLEN;
- return true;
- }
-@@ -316,7 +318,7 @@ static void nf_flow_encap_pop(struct sk_
- skb_reset_network_header(skb);
- break;
- case htons(ETH_P_PPP_SES):
-- skb->protocol = nf_flow_pppoe_proto(skb);
-+ skb->protocol = __nf_flow_pppoe_proto(skb);
- skb_pull(skb, PPPOE_SES_HLEN);
- skb_reset_network_header(skb);
- break;
+++ /dev/null
-From: Pablo Neira Ayuso <pablo@netfilter.org>
-Date: Thu, 11 Apr 2024 13:29:00 +0200
-Subject: [PATCH] netfilter: flowtable: incorrect pppoe tuple
-
-pppoe traffic reaching ingress path does not match the flowtable entry
-because the pppoe header is expected to be at the network header offset.
-This bug causes a mismatch in the flow table lookup, so pppoe packets
-enter the classical forwarding path.
-
-Fixes: 72efd585f714 ("netfilter: flowtable: add pppoe support")
-Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
----
-
---- a/net/netfilter/nf_flow_table_ip.c
-+++ b/net/netfilter/nf_flow_table_ip.c
-@@ -157,7 +157,7 @@ static void nf_flow_tuple_encap(struct s
- tuple->encap[i].proto = skb->protocol;
- break;
- case htons(ETH_P_PPP_SES):
-- phdr = (struct pppoe_hdr *)skb_mac_header(skb);
-+ phdr = (struct pppoe_hdr *)skb_network_header(skb);
- tuple->encap[i].id = ntohs(phdr->sid);
- tuple->encap[i].proto = skb->protocol;
- break;
--- a/drivers/net/ethernet/mediatek/mtk_wed.c
+++ b/drivers/net/ethernet/mediatek/mtk_wed.c
-@@ -1713,19 +1713,20 @@ mtk_wed_irq_set_mask(struct mtk_wed_devi
+@@ -1709,19 +1709,20 @@ mtk_wed_irq_set_mask(struct mtk_wed_devi
int mtk_wed_flow_add(int index)
{
struct mtk_wed_hw *hw = hw_list[index];
goto out;
}
-@@ -1744,14 +1745,15 @@ void mtk_wed_flow_remove(int index)
+@@ -1740,14 +1741,15 @@ void mtk_wed_flow_remove(int index)
{
struct mtk_wed_hw *hw = hw_list[index];
wdma_clr(dev, MTK_WDMA_GLO_CFG,
MTK_WDMA_GLO_CFG_RX_INFO3_PRERES);
@@ -606,7 +606,7 @@ mtk_wed_stop(struct mtk_wed_device *dev)
+ wdma_w32(dev, MTK_WDMA_INT_MASK, 0);
wdma_w32(dev, MTK_WDMA_INT_GRP2, 0);
- wed_w32(dev, MTK_WED_WPDMA_INT_MASK, 0);
- if (dev->hw->version == 1)
+ if (mtk_wed_is_v1(dev->hw))
return;
wed_w32(dev, MTK_WED_EXT_INT_MASK1, 0);
-@@ -625,7 +625,7 @@ mtk_wed_deinit(struct mtk_wed_device *de
+@@ -624,7 +624,7 @@ mtk_wed_deinit(struct mtk_wed_device *de
MTK_WED_CTRL_WED_TX_BM_EN |
MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
return;
wed_clr(dev, MTK_WED_CTRL,
-@@ -731,7 +731,7 @@ mtk_wed_bus_init(struct mtk_wed_device *
+@@ -730,7 +730,7 @@ mtk_wed_bus_init(struct mtk_wed_device *
static void
mtk_wed_set_wpdma(struct mtk_wed_device *dev)
{
wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_phys);
} else {
mtk_wed_bus_init(dev);
-@@ -762,7 +762,7 @@ mtk_wed_hw_init_early(struct mtk_wed_dev
+@@ -761,7 +761,7 @@ mtk_wed_hw_init_early(struct mtk_wed_dev
MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY;
wed_m32(dev, MTK_WED_WDMA_GLO_CFG, mask, set);
u32 offset = dev->hw->index ? 0x04000400 : 0;
wdma_set(dev, MTK_WDMA_GLO_CFG,
-@@ -935,7 +935,7 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+@@ -934,7 +934,7 @@ mtk_wed_hw_init(struct mtk_wed_device *d
wed_w32(dev, MTK_WED_TX_BM_BUF_LEN, MTK_WED_PKT_SIZE);
wed_w32(dev, MTK_WED_TX_BM_TKID,
FIELD_PREP(MTK_WED_TX_BM_TKID_START,
dev->wlan.token_start) |
-@@ -968,7 +968,7 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+@@ -967,7 +967,7 @@ mtk_wed_hw_init(struct mtk_wed_device *d
mtk_wed_reset(dev, MTK_WED_RESET_TX_BM);
wed_set(dev, MTK_WED_CTRL,
MTK_WED_CTRL_WED_TX_BM_EN |
MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
-@@ -1218,7 +1218,7 @@ mtk_wed_reset_dma(struct mtk_wed_device
+@@ -1217,7 +1217,7 @@ mtk_wed_reset_dma(struct mtk_wed_device
}
dev->init_done = false;
return;
if (!busy) {
-@@ -1344,7 +1344,7 @@ mtk_wed_configure_irq(struct mtk_wed_dev
+@@ -1343,7 +1343,7 @@ mtk_wed_configure_irq(struct mtk_wed_dev
MTK_WED_CTRL_WED_TX_BM_EN |
MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER,
MTK_WED_PCIE_INT_TRIGGER_STATUS);
-@@ -1417,7 +1417,7 @@ mtk_wed_dma_enable(struct mtk_wed_device
+@@ -1416,7 +1416,7 @@ mtk_wed_dma_enable(struct mtk_wed_device
MTK_WDMA_GLO_CFG_RX_INFO1_PRERES |
MTK_WDMA_GLO_CFG_RX_INFO2_PRERES);
wdma_set(dev, MTK_WDMA_GLO_CFG,
MTK_WDMA_GLO_CFG_RX_INFO3_PRERES);
} else {
-@@ -1466,7 +1466,7 @@ mtk_wed_start(struct mtk_wed_device *dev
+@@ -1465,7 +1465,7 @@ mtk_wed_start(struct mtk_wed_device *dev
mtk_wed_set_ext_int(dev, true);
u32 val = dev->wlan.wpdma_phys | MTK_PCIE_MIRROR_MAP_EN |
FIELD_PREP(MTK_PCIE_MIRROR_MAP_WED_ID,
dev->hw->index);
-@@ -1551,7 +1551,7 @@ mtk_wed_attach(struct mtk_wed_device *de
+@@ -1550,7 +1550,7 @@ mtk_wed_attach(struct mtk_wed_device *de
}
mtk_wed_hw_init_early(dev);
regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP,
BIT(hw->index), 0);
} else {
-@@ -1619,7 +1619,7 @@ static int
+@@ -1618,7 +1618,7 @@ static int
mtk_wed_txfree_ring_setup(struct mtk_wed_device *dev, void __iomem *regs)
{
struct mtk_wed_ring *ring = &dev->txfree_ring;
/*
* For txfree event handling, the same DMA ring is shared between WED
-@@ -1677,7 +1677,7 @@ mtk_wed_irq_get(struct mtk_wed_device *d
+@@ -1676,7 +1676,7 @@ mtk_wed_irq_get(struct mtk_wed_device *d
{
u32 val, ext_mask = MTK_WED_EXT_INT_STATUS_ERROR_MASK;
ext_mask |= MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR;
else
ext_mask |= MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH |
-@@ -1844,7 +1844,7 @@ mtk_wed_setup_tc(struct mtk_wed_device *
+@@ -1840,7 +1840,7 @@ mtk_wed_setup_tc(struct mtk_wed_device *
{
struct mtk_wed_hw *hw = wed->hw;
return -EOPNOTSUPP;
switch (type) {
-@@ -1918,9 +1918,9 @@ void mtk_wed_add_hw(struct device_node *
+@@ -1914,9 +1914,9 @@ void mtk_wed_add_hw(struct device_node *
hw->wdma = wdma;
hw->index = index;
hw->irq = irq;
--- a/drivers/net/ethernet/mediatek/mtk_wed.c
+++ b/drivers/net/ethernet/mediatek/mtk_wed.c
@@ -606,7 +606,7 @@ mtk_wed_stop(struct mtk_wed_device *dev)
+ wdma_w32(dev, MTK_WDMA_INT_MASK, 0);
wdma_w32(dev, MTK_WDMA_INT_GRP2, 0);
- wed_w32(dev, MTK_WED_WPDMA_INT_MASK, 0);
- if (mtk_wed_is_v1(dev->hw))
+ if (!mtk_wed_get_rx_capa(dev))
return;
wed_w32(dev, MTK_WED_EXT_INT_MASK1, 0);
-@@ -733,16 +733,21 @@ mtk_wed_set_wpdma(struct mtk_wed_device
+@@ -732,16 +732,21 @@ mtk_wed_set_wpdma(struct mtk_wed_device
{
if (mtk_wed_is_v1(dev->hw)) {
wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_phys);
}
static void
-@@ -974,15 +979,17 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+@@ -973,15 +978,17 @@ mtk_wed_hw_init(struct mtk_wed_device *d
MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
} else {
wed_clr(dev, MTK_WED_TX_TKID_CTRL, MTK_WED_TX_TKID_CTRL_PAUSE);
}
wed_clr(dev, MTK_WED_TX_BM_CTRL, MTK_WED_TX_BM_CTRL_PAUSE);
-@@ -1354,8 +1361,6 @@ mtk_wed_configure_irq(struct mtk_wed_dev
+@@ -1353,8 +1360,6 @@ mtk_wed_configure_irq(struct mtk_wed_dev
wed_clr(dev, MTK_WED_WDMA_INT_CTRL, wdma_mask);
} else {
/* initail tx interrupt trigger */
wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX,
MTK_WED_WPDMA_INT_CTRL_TX0_DONE_EN |
-@@ -1374,15 +1379,20 @@ mtk_wed_configure_irq(struct mtk_wed_dev
+@@ -1373,15 +1378,20 @@ mtk_wed_configure_irq(struct mtk_wed_dev
FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_TRIG,
dev->wlan.txfree_tbit));
wed_w32(dev, MTK_WED_WDMA_INT_CLR, wdma_mask);
wed_set(dev, MTK_WED_WDMA_INT_CTRL,
-@@ -1401,6 +1411,8 @@ mtk_wed_configure_irq(struct mtk_wed_dev
+@@ -1400,6 +1410,8 @@ mtk_wed_configure_irq(struct mtk_wed_dev
static void
mtk_wed_dma_enable(struct mtk_wed_device *dev)
{
wed_set(dev, MTK_WED_WPDMA_INT_CTRL, MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV);
wed_set(dev, MTK_WED_GLO_CFG,
-@@ -1420,33 +1432,33 @@ mtk_wed_dma_enable(struct mtk_wed_device
+@@ -1419,33 +1431,33 @@ mtk_wed_dma_enable(struct mtk_wed_device
if (mtk_wed_is_v1(dev->hw)) {
wdma_set(dev, MTK_WDMA_GLO_CFG,
MTK_WDMA_GLO_CFG_RX_INFO3_PRERES);
}
static void
-@@ -1473,7 +1485,7 @@ mtk_wed_start(struct mtk_wed_device *dev
+@@ -1472,7 +1484,7 @@ mtk_wed_start(struct mtk_wed_device *dev
val |= BIT(0) | (BIT(1) * !!dev->hw->index);
regmap_write(dev->hw->mirror, dev->hw->index * 4, val);
/* driver set mid ready and only once */
wed_w32(dev, MTK_WED_EXT_INT_MASK1,
MTK_WED_EXT_INT_STATUS_WPDMA_MID_RDY);
-@@ -1485,7 +1497,6 @@ mtk_wed_start(struct mtk_wed_device *dev
+@@ -1484,7 +1496,6 @@ mtk_wed_start(struct mtk_wed_device *dev
if (mtk_wed_rro_cfg(dev))
return;
}
mtk_wed_set_512_support(dev, dev->wlan.wcid_512);
-@@ -1551,13 +1562,14 @@ mtk_wed_attach(struct mtk_wed_device *de
+@@ -1550,13 +1561,14 @@ mtk_wed_attach(struct mtk_wed_device *de
}
mtk_wed_hw_init_early(dev);
static void
wed_m32(struct mtk_wed_device *dev, u32 reg, u32 mask, u32 val)
{
-@@ -747,7 +767,7 @@ mtk_wed_set_wpdma(struct mtk_wed_device
+@@ -746,7 +766,7 @@ mtk_wed_set_wpdma(struct mtk_wed_device
return;
wed_w32(dev, MTK_WED_WPDMA_RX_GLO_CFG, dev->wlan.wpdma_rx_glo);
}
static void
-@@ -941,22 +961,10 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+@@ -940,22 +960,10 @@ mtk_wed_hw_init(struct mtk_wed_device *d
wed_w32(dev, MTK_WED_TX_BM_BUF_LEN, MTK_WED_PKT_SIZE);
if (mtk_wed_is_v1(dev->hw)) {
wed_w32(dev, MTK_WED_TX_BM_DYN_THR,
FIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO_V2, 0) |
MTK_WED_TX_BM_DYN_THR_HI_V2);
-@@ -971,6 +979,11 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+@@ -970,6 +978,11 @@ mtk_wed_hw_init(struct mtk_wed_device *d
MTK_WED_TX_TKID_DYN_THR_HI);
}
mtk_wed_reset(dev, MTK_WED_RESET_TX_BM);
if (mtk_wed_is_v1(dev->hw)) {
-@@ -1105,13 +1118,8 @@ mtk_wed_rx_reset(struct mtk_wed_device *
+@@ -1104,13 +1117,8 @@ mtk_wed_rx_reset(struct mtk_wed_device *
if (ret) {
mtk_wed_reset(dev, MTK_WED_RESET_WED_RX_DMA);
} else {
wed_w32(dev, MTK_WED_RESET_IDX, 0);
}
-@@ -1164,7 +1172,8 @@ mtk_wed_reset_dma(struct mtk_wed_device
+@@ -1163,7 +1171,8 @@ mtk_wed_reset_dma(struct mtk_wed_device
if (busy) {
mtk_wed_reset(dev, MTK_WED_RESET_WED_TX_DMA);
} else {
wed_w32(dev, MTK_WED_RESET_IDX, 0);
}
-@@ -1256,7 +1265,6 @@ static int
+@@ -1255,7 +1264,6 @@ static int
mtk_wed_wdma_rx_ring_setup(struct mtk_wed_device *dev, int idx, int size,
bool reset)
{
struct mtk_wed_ring *wdma;
if (idx >= ARRAY_SIZE(dev->rx_wdma))
-@@ -1264,7 +1272,7 @@ mtk_wed_wdma_rx_ring_setup(struct mtk_we
+@@ -1263,7 +1271,7 @@ mtk_wed_wdma_rx_ring_setup(struct mtk_we
wdma = &dev->rx_wdma[idx];
if (!reset && mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE,
return -ENOMEM;
wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_BASE,
-@@ -1285,7 +1293,6 @@ static int
+@@ -1284,7 +1292,6 @@ static int
mtk_wed_wdma_tx_ring_setup(struct mtk_wed_device *dev, int idx, int size,
bool reset)
{
struct mtk_wed_ring *wdma;
if (idx >= ARRAY_SIZE(dev->tx_wdma))
-@@ -1293,7 +1300,7 @@ mtk_wed_wdma_tx_ring_setup(struct mtk_we
+@@ -1292,7 +1299,7 @@ mtk_wed_wdma_tx_ring_setup(struct mtk_we
wdma = &dev->tx_wdma[idx];
if (!reset && mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE,
return -ENOMEM;
wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_BASE,
-@@ -1932,7 +1939,12 @@ void mtk_wed_add_hw(struct device_node *
+@@ -1928,7 +1935,12 @@ void mtk_wed_add_hw(struct device_node *
hw->irq = irq;
hw->version = eth->soc->version;
hw->mirror = syscon_regmap_lookup_by_phandle(eth_np,
"mediatek,pcie-mirror");
hw->hifsys = syscon_regmap_lookup_by_phandle(eth_np,
-@@ -1946,6 +1958,8 @@ void mtk_wed_add_hw(struct device_node *
+@@ -1942,6 +1954,8 @@ void mtk_wed_add_hw(struct device_node *
regmap_write(hw->mirror, 0, 0);
regmap_write(hw->mirror, 4, 0);
}
}
mtk_wed_set_512_support(dev, false);
-@@ -652,6 +699,14 @@ mtk_wed_deinit(struct mtk_wed_device *de
+@@ -651,6 +698,14 @@ mtk_wed_deinit(struct mtk_wed_device *de
MTK_WED_CTRL_RX_ROUTE_QM_EN |
MTK_WED_CTRL_WED_RX_BM_EN |
MTK_WED_CTRL_RX_RRO_QM_EN);
}
static void
-@@ -701,21 +756,37 @@ mtk_wed_detach(struct mtk_wed_device *de
+@@ -700,21 +755,37 @@ mtk_wed_detach(struct mtk_wed_device *de
mutex_unlock(&hw_lock);
}
wed_w32(dev, MTK_WED_PCIE_INT_CTRL,
FIELD_PREP(MTK_WED_PCIE_INT_CTRL_POLL_EN, 2));
-@@ -723,19 +794,9 @@ mtk_wed_bus_init(struct mtk_wed_device *
+@@ -722,19 +793,9 @@ mtk_wed_bus_init(struct mtk_wed_device *
/* pcie interrupt control: pola/source selection */
wed_set(dev, MTK_WED_PCIE_INT_CTRL,
MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA |
break;
}
case MTK_WED_BUS_AXI:
-@@ -773,18 +834,19 @@ mtk_wed_set_wpdma(struct mtk_wed_device
+@@ -772,18 +833,19 @@ mtk_wed_set_wpdma(struct mtk_wed_device
static void
mtk_wed_hw_init_early(struct mtk_wed_device *dev)
{
wed_m32(dev, MTK_WED_WDMA_GLO_CFG, mask, set);
if (mtk_wed_is_v1(dev->hw)) {
-@@ -932,11 +994,18 @@ mtk_wed_route_qm_hw_init(struct mtk_wed_
+@@ -931,11 +993,18 @@ mtk_wed_route_qm_hw_init(struct mtk_wed_
}
/* configure RX_ROUTE_QM */
/* enable RX_ROUTE_QM */
wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_RX_ROUTE_QM_EN);
}
-@@ -949,22 +1018,30 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+@@ -948,22 +1017,30 @@ mtk_wed_hw_init(struct mtk_wed_device *d
dev->init_done = true;
mtk_wed_set_ext_int(dev, false);
wed_w32(dev, MTK_WED_TX_BM_DYN_THR,
FIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO_V2, 0) |
MTK_WED_TX_BM_DYN_THR_HI_V2);
-@@ -974,9 +1051,6 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+@@ -973,9 +1050,6 @@ mtk_wed_hw_init(struct mtk_wed_device *d
dev->tx_buf_ring.size / 128) |
FIELD_PREP(MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM,
dev->tx_buf_ring.size / 128));
}
wed_w32(dev, dev->hw->soc->regmap.tx_bm_tkid,
-@@ -986,26 +1060,62 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+@@ -985,26 +1059,62 @@ mtk_wed_hw_init(struct mtk_wed_device *d
mtk_wed_reset(dev, MTK_WED_RESET_TX_BM);
}
static void
-@@ -1303,6 +1413,24 @@ mtk_wed_wdma_tx_ring_setup(struct mtk_we
+@@ -1302,6 +1412,24 @@ mtk_wed_wdma_tx_ring_setup(struct mtk_we
dev->hw->soc->wdma_desc_size, true))
return -ENOMEM;
wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_BASE,
wdma->desc_phys);
wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_COUNT,
-@@ -1368,6 +1496,9 @@ mtk_wed_configure_irq(struct mtk_wed_dev
+@@ -1367,6 +1495,9 @@ mtk_wed_configure_irq(struct mtk_wed_dev
wed_clr(dev, MTK_WED_WDMA_INT_CTRL, wdma_mask);
} else {
/* initail tx interrupt trigger */
wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX,
MTK_WED_WPDMA_INT_CTRL_TX0_DONE_EN |
-@@ -1420,33 +1551,60 @@ mtk_wed_dma_enable(struct mtk_wed_device
+@@ -1419,33 +1550,60 @@ mtk_wed_dma_enable(struct mtk_wed_device
{
int i;
wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
MTK_WED_WPDMA_GLO_CFG_TX_TKID_KEEP |
MTK_WED_WPDMA_GLO_CFG_TX_DMAD_DW3_PREV);
-@@ -1458,11 +1616,22 @@ mtk_wed_dma_enable(struct mtk_wed_device
+@@ -1457,11 +1615,22 @@ mtk_wed_dma_enable(struct mtk_wed_device
MTK_WED_WDMA_GLO_CFG_TX_DRV_EN |
MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK);
for (i = 0; i < MTK_WED_RX_QUEUES; i++)
mtk_wed_check_wfdma_rx_fill(dev, i);
-@@ -1502,6 +1671,12 @@ mtk_wed_start(struct mtk_wed_device *dev
+@@ -1501,6 +1670,12 @@ mtk_wed_start(struct mtk_wed_device *dev
wed_r32(dev, MTK_WED_EXT_INT_MASK1);
wed_r32(dev, MTK_WED_EXT_INT_MASK2);
if (mtk_wed_rro_cfg(dev))
return;
}
-@@ -1553,6 +1728,7 @@ mtk_wed_attach(struct mtk_wed_device *de
+@@ -1552,6 +1727,7 @@ mtk_wed_attach(struct mtk_wed_device *de
dev->irq = hw->irq;
dev->wdma_idx = hw->index;
dev->version = hw->version;
if (hw->eth->dma_dev == hw->eth->dev &&
of_dma_is_coherent(hw->eth->dev->of_node))
-@@ -1620,6 +1796,23 @@ mtk_wed_tx_ring_setup(struct mtk_wed_dev
+@@ -1619,6 +1795,23 @@ mtk_wed_tx_ring_setup(struct mtk_wed_dev
ring->reg_base = MTK_WED_RING_TX(idx);
ring->wpdma = regs;
/* WED -> WPDMA */
wpdma_tx_w32(dev, idx, MTK_WED_RING_OFS_BASE, ring->desc_phys);
wpdma_tx_w32(dev, idx, MTK_WED_RING_OFS_COUNT, MTK_WED_TX_RING_SIZE);
-@@ -1694,15 +1887,13 @@ mtk_wed_rx_ring_setup(struct mtk_wed_dev
+@@ -1693,15 +1886,13 @@ mtk_wed_rx_ring_setup(struct mtk_wed_dev
static u32
mtk_wed_irq_get(struct mtk_wed_device *dev, u32 mask)
{
val = wed_r32(dev, MTK_WED_EXT_INT_STATUS);
wed_w32(dev, MTK_WED_EXT_INT_STATUS, val);
-@@ -1943,6 +2134,9 @@ void mtk_wed_add_hw(struct device_node *
+@@ -1939,6 +2130,9 @@ void mtk_wed_add_hw(struct device_node *
case 2:
hw->soc = &mt7986_data;
break;
}
static void
-@@ -1546,6 +1537,7 @@ mtk_wed_configure_irq(struct mtk_wed_dev
+@@ -1545,6 +1536,7 @@ mtk_wed_configure_irq(struct mtk_wed_dev
wed_w32(dev, MTK_WED_INT_MASK, irq_mask);
}
static void
mtk_wed_dma_enable(struct mtk_wed_device *dev)
{
-@@ -1633,8 +1625,26 @@ mtk_wed_dma_enable(struct mtk_wed_device
+@@ -1632,8 +1624,26 @@ mtk_wed_dma_enable(struct mtk_wed_device
wdma_set(dev, MTK_WDMA_WRBK_TX_CFG, MTK_WDMA_WRBK_TX_CFG_WRBK_EN);
}
mtk_wed_tx_buffer_alloc(struct mtk_wed_device *dev)
{
u32 desc_size = dev->hw->soc->tx_ring_desc_size;
-@@ -709,6 +840,7 @@ __mtk_wed_detach(struct mtk_wed_device *
+@@ -708,6 +839,7 @@ __mtk_wed_detach(struct mtk_wed_device *
mtk_wdma_rx_reset(dev);
mtk_wed_reset(dev, MTK_WED_RESET_WED);
mtk_wed_free_tx_buffer(dev);
mtk_wed_free_tx_rings(dev);
-@@ -1129,23 +1261,6 @@ mtk_wed_ring_reset(struct mtk_wed_ring *
+@@ -1128,23 +1260,6 @@ mtk_wed_ring_reset(struct mtk_wed_ring *
}
}
static int
mtk_wed_rx_reset(struct mtk_wed_device *dev)
{
-@@ -1692,6 +1807,7 @@ mtk_wed_start(struct mtk_wed_device *dev
+@@ -1691,6 +1806,7 @@ mtk_wed_start(struct mtk_wed_device *dev
}
mtk_wed_set_512_support(dev, dev->wlan.wcid_512);
mtk_wed_dma_enable(dev);
dev->running = true;
-@@ -1748,6 +1864,10 @@ mtk_wed_attach(struct mtk_wed_device *de
+@@ -1747,6 +1863,10 @@ mtk_wed_attach(struct mtk_wed_device *de
if (ret)
goto out;
}
static void
-@@ -935,6 +1056,8 @@ mtk_wed_bus_init(struct mtk_wed_device *
+@@ -934,6 +1055,8 @@ mtk_wed_bus_init(struct mtk_wed_device *
static void
mtk_wed_set_wpdma(struct mtk_wed_device *dev)
{
if (mtk_wed_is_v1(dev->hw)) {
wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_phys);
return;
-@@ -952,6 +1075,15 @@ mtk_wed_set_wpdma(struct mtk_wed_device
+@@ -951,6 +1074,15 @@ mtk_wed_set_wpdma(struct mtk_wed_device
wed_w32(dev, MTK_WED_WPDMA_RX_GLO_CFG, dev->wlan.wpdma_rx_glo);
wed_w32(dev, dev->hw->soc->regmap.wpdma_rx_ring0, dev->wlan.wpdma_rx);
}
static void
-@@ -1763,6 +1895,165 @@ mtk_wed_dma_enable(struct mtk_wed_device
+@@ -1762,6 +1894,165 @@ mtk_wed_dma_enable(struct mtk_wed_device
}
static void
mtk_wed_start(struct mtk_wed_device *dev, u32 irq_mask)
{
int i;
-@@ -2216,6 +2507,10 @@ void mtk_wed_add_hw(struct device_node *
+@@ -2212,6 +2503,10 @@ void mtk_wed_add_hw(struct device_node *
.detach = mtk_wed_detach,
.ppe_check = mtk_wed_ppe_check,
.setup_tc = mtk_wed_setup_tc,
wdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_TX);
wdma_w32(dev, MTK_WDMA_RESET_IDX, 0);
-@@ -1406,13 +1570,33 @@ mtk_wed_rx_reset(struct mtk_wed_device *
+@@ -1405,13 +1569,33 @@ mtk_wed_rx_reset(struct mtk_wed_device *
if (ret)
return ret;
wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX,
MTK_WED_WPDMA_RX_D_RST_CRX_IDX |
MTK_WED_WPDMA_RX_D_RST_DRV_IDX);
-@@ -1440,23 +1624,52 @@ mtk_wed_rx_reset(struct mtk_wed_device *
+@@ -1439,23 +1623,52 @@ mtk_wed_rx_reset(struct mtk_wed_device *
wed_w32(dev, MTK_WED_RROQM_RST_IDX, 0);
}
mtk_wed_reset(dev, MTK_WED_RESET_WDMA_TX_DRV);
/* reset wed rx dma */
-@@ -1477,6 +1690,14 @@ mtk_wed_rx_reset(struct mtk_wed_device *
+@@ -1476,6 +1689,14 @@ mtk_wed_rx_reset(struct mtk_wed_device *
MTK_WED_CTRL_WED_RX_BM_BUSY);
mtk_wed_reset(dev, MTK_WED_RESET_RX_BM);
/* wo change to enable state */
val = MTK_WED_WO_STATE_ENABLE;
ret = mtk_wed_mcu_send_msg(wo, MTK_WED_MODULE_ID_WO,
-@@ -1494,6 +1715,7 @@ mtk_wed_rx_reset(struct mtk_wed_device *
+@@ -1493,6 +1714,7 @@ mtk_wed_rx_reset(struct mtk_wed_device *
false);
}
mtk_wed_free_rx_buffer(dev);
return 0;
}
-@@ -1527,15 +1749,41 @@ mtk_wed_reset_dma(struct mtk_wed_device
+@@ -1526,15 +1748,41 @@ mtk_wed_reset_dma(struct mtk_wed_device
/* 2. reset WDMA rx DMA */
busy = !!mtk_wdma_rx_reset(dev);
wed_w32(dev, MTK_WED_WDMA_RESET_IDX,
MTK_WED_WDMA_RESET_IDX_RX | MTK_WED_WDMA_RESET_IDX_DRV);
wed_w32(dev, MTK_WED_WDMA_RESET_IDX, 0);
-@@ -1551,8 +1799,13 @@ mtk_wed_reset_dma(struct mtk_wed_device
+@@ -1550,8 +1798,13 @@ mtk_wed_reset_dma(struct mtk_wed_device
wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
for (i = 0; i < 100; i++) {
break;
}
-@@ -1574,6 +1827,8 @@ mtk_wed_reset_dma(struct mtk_wed_device
+@@ -1573,6 +1826,8 @@ mtk_wed_reset_dma(struct mtk_wed_device
mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_INT_AGENT);
mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_TX_DRV);
mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_RX_DRV);
} else {
wed_w32(dev, MTK_WED_WPDMA_RESET_IDX,
MTK_WED_WPDMA_RESET_IDX_TX |
-@@ -1590,7 +1845,14 @@ mtk_wed_reset_dma(struct mtk_wed_device
+@@ -1589,7 +1844,14 @@ mtk_wed_reset_dma(struct mtk_wed_device
wed_w32(dev, MTK_WED_RESET_IDX, 0);
}
}
static int
-@@ -1842,6 +2104,7 @@ mtk_wed_dma_enable(struct mtk_wed_device
+@@ -1841,6 +2103,7 @@ mtk_wed_dma_enable(struct mtk_wed_device
MTK_WED_WPDMA_GLO_CFG_RX_DRV_UNS_VER_FORCE_4);
wdma_set(dev, MTK_WDMA_PREF_RX_CFG, MTK_WDMA_PREF_RX_CFG_PREF_EN);
}
wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
-@@ -1905,6 +2168,12 @@ mtk_wed_start_hw_rro(struct mtk_wed_devi
+@@ -1904,6 +2167,12 @@ mtk_wed_start_hw_rro(struct mtk_wed_devi
if (!mtk_wed_get_rx_capa(dev) || !dev->wlan.hw_rro)
return;
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-@@ -3003,13 +3003,25 @@ static void stmmac_tx_timer_arm(struct s
+@@ -2988,13 +2988,25 @@ static void stmmac_tx_timer_arm(struct s
{
struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
u32 tx_coal_timer = priv->tx_coal_timer[queue];
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-@@ -2551,9 +2551,13 @@ static void stmmac_bump_dma_threshold(st
+@@ -2536,9 +2536,13 @@ static void stmmac_bump_dma_threshold(st
* @priv: driver private structure
* @budget: napi budget limiting this functions packet handling
* @queue: TX queue index
{
struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
struct stmmac_txq_stats *txq_stats = &priv->xstats.txq_stats[queue];
-@@ -2713,7 +2717,7 @@ static int stmmac_tx_clean(struct stmmac
+@@ -2698,7 +2702,7 @@ static int stmmac_tx_clean(struct stmmac
/* We still have pending packets, let's call for a new scheduling */
if (tx_q->dirty_tx != tx_q->cur_tx)
u64_stats_update_begin(&txq_stats->napi_syncp);
u64_stats_add(&txq_stats->napi.tx_packets, tx_packets);
-@@ -5605,6 +5609,7 @@ static int stmmac_napi_poll_tx(struct na
+@@ -5590,6 +5594,7 @@ static int stmmac_napi_poll_tx(struct na
container_of(napi, struct stmmac_channel, tx_napi);
struct stmmac_priv *priv = ch->priv_data;
struct stmmac_txq_stats *txq_stats;
u32 chan = ch->index;
int work_done;
-@@ -5613,7 +5618,7 @@ static int stmmac_napi_poll_tx(struct na
+@@ -5598,7 +5603,7 @@ static int stmmac_napi_poll_tx(struct na
u64_stats_inc(&txq_stats->napi.poll);
u64_stats_update_end(&txq_stats->napi_syncp);
work_done = min(work_done, budget);
if (work_done < budget && napi_complete_done(napi, work_done)) {
-@@ -5624,6 +5629,10 @@ static int stmmac_napi_poll_tx(struct na
+@@ -5609,6 +5614,10 @@ static int stmmac_napi_poll_tx(struct na
spin_unlock_irqrestore(&ch->lock, flags);
}
return work_done;
}
-@@ -5632,6 +5641,7 @@ static int stmmac_napi_poll_rxtx(struct
+@@ -5617,6 +5626,7 @@ static int stmmac_napi_poll_rxtx(struct
struct stmmac_channel *ch =
container_of(napi, struct stmmac_channel, rxtx_napi);
struct stmmac_priv *priv = ch->priv_data;
int rx_done, tx_done, rxtx_done;
struct stmmac_rxq_stats *rxq_stats;
struct stmmac_txq_stats *txq_stats;
-@@ -5647,7 +5657,7 @@ static int stmmac_napi_poll_rxtx(struct
+@@ -5632,7 +5642,7 @@ static int stmmac_napi_poll_rxtx(struct
u64_stats_inc(&txq_stats->napi.poll);
u64_stats_update_end(&txq_stats->napi_syncp);
tx_done = min(tx_done, budget);
rx_done = stmmac_rx_zc(priv, budget, chan);
-@@ -5672,6 +5682,10 @@ static int stmmac_napi_poll_rxtx(struct
+@@ -5657,6 +5667,10 @@ static int stmmac_napi_poll_rxtx(struct
spin_unlock_irqrestore(&ch->lock, flags);
}
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -3021,15 +3021,6 @@ static void mt753x_phylink_mac_link_down
+@@ -3037,15 +3037,6 @@ static void mt753x_phylink_mac_link_down
mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
}
static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port,
unsigned int mode,
phy_interface_t interface,
-@@ -3117,8 +3108,6 @@ mt7531_cpu_port_config(struct dsa_switch
+@@ -3133,8 +3124,6 @@ mt7531_cpu_port_config(struct dsa_switch
return ret;
mt7530_write(priv, MT7530_PMCR_P(port),
PMCR_CPU_PORT_SETTING(priv->id));
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2343,24 +2343,40 @@ mt7530_free_irq_common(struct mt7530_pri
+@@ -2345,24 +2345,40 @@ mt7530_free_irq_common(struct mt7530_pri
static void
mt7530_free_irq(struct mt7530_priv *priv)
{
bus->priv = priv;
bus->name = KBUILD_MODNAME "-mii";
snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++);
-@@ -2371,16 +2387,18 @@ mt7530_setup_mdio(struct mt7530_priv *pr
+@@ -2373,16 +2389,18 @@ mt7530_setup_mdio(struct mt7530_priv *pr
bus->parent = dev;
bus->phy_mask = ~ds->phys_mii_mask;
/* Add the CPU port to the CPU port bitmap for MT7531 and the switch on
* the MT7988 SoC. Trapped frames will be forwarded to the CPU port that
* is affine to the inbound user port.
-@@ -3289,6 +3285,36 @@ static int mt753x_set_mac_eee(struct dsa
+@@ -3305,6 +3301,36 @@ static int mt753x_set_mac_eee(struct dsa
return 0;
}
static int mt7988_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
{
return 0;
-@@ -3344,6 +3370,7 @@ const struct dsa_switch_ops mt7530_switc
+@@ -3360,6 +3386,7 @@ const struct dsa_switch_ops mt7530_switc
.phylink_mac_link_up = mt753x_phylink_mac_link_up,
.get_mac_eee = mt753x_get_mac_eee,
.set_mac_eee = mt753x_set_mac_eee,
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
-@@ -41,8 +41,8 @@ enum mt753x_id {
+@@ -45,8 +45,8 @@ enum mt753x_id {
#define UNU_FFP(x) (((x) & 0xff) << 8)
#define UNU_FFP_MASK UNU_FFP(~0)
#define CPU_EN BIT(7)
#define MIRROR_EN BIT(3)
#define MIRROR_PORT(x) ((x) & 0x7)
#define MIRROR_MASK 0x7
-@@ -785,6 +785,7 @@ struct mt753x_info {
+@@ -790,6 +790,7 @@ struct mt753x_info {
* @irq_domain: IRQ domain of the switch irq_chip
* @irq_enable: IRQ enable bits, synced to SYS_INT_EN
* @create_sgmii: Pointer to function creating SGMII PCS instance(s)
*/
struct mt7530_priv {
struct device *dev;
-@@ -811,6 +812,7 @@ struct mt7530_priv {
+@@ -816,6 +817,7 @@ struct mt7530_priv {
struct irq_domain *irq_domain;
u32 irq_enable;
int (*create_sgmii)(struct mt7530_priv *priv, bool dual_sgmii);
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
-@@ -708,7 +708,7 @@ struct mt7530_port {
+@@ -713,7 +713,7 @@ struct mt7530_port {
/* Port 5 interface select definitions */
enum p5_interface_select {
P5_INTF_SEL_PHY_P0,
P5_INTF_SEL_PHY_P4,
P5_INTF_SEL_GMAC5,
-@@ -801,7 +801,7 @@ struct mt7530_priv {
+@@ -806,7 +806,7 @@ struct mt7530_priv {
bool mcm;
phy_interface_t p6_interface;
phy_interface_t p5_interface;
default:
return "unknown";
}
-@@ -2685,6 +2671,12 @@ mt7531_setup(struct dsa_switch *ds)
+@@ -2694,6 +2680,12 @@ mt7531_setup(struct dsa_switch *ds)
return -ENODEV;
}
/* all MACs must be forced link-down before sw reset */
for (i = 0; i < MT7530_NUM_PORTS; i++)
mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK);
-@@ -2694,21 +2686,18 @@ mt7531_setup(struct dsa_switch *ds)
+@@ -2703,21 +2695,18 @@ mt7531_setup(struct dsa_switch *ds)
SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
SYS_CTRL_REG_RST);
mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
MT7531_GPIO0_INTERRUPT);
-@@ -2768,11 +2757,6 @@ static void mt7530_mac_port_get_caps(str
+@@ -2784,11 +2773,6 @@ static void mt7530_mac_port_get_caps(str
}
}
static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port,
struct phylink_config *config)
{
-@@ -2785,7 +2769,7 @@ static void mt7531_mac_port_get_caps(str
+@@ -2801,7 +2785,7 @@ static void mt7531_mac_port_get_caps(str
break;
case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */
phy_interface_set_rgmii(config->supported_interfaces);
break;
}
-@@ -2852,7 +2836,7 @@ static int mt7531_rgmii_setup(struct mt7
+@@ -2868,7 +2852,7 @@ static int mt7531_rgmii_setup(struct mt7
{
u32 val;
dev_err(priv->dev, "RGMII mode is not available for port %d\n",
port);
return -EINVAL;
-@@ -3095,7 +3079,7 @@ mt7531_cpu_port_config(struct dsa_switch
+@@ -3111,7 +3095,7 @@ mt7531_cpu_port_config(struct dsa_switch
switch (port) {
case 5:
interface = PHY_INTERFACE_MODE_RGMII;
else
interface = PHY_INTERFACE_MODE_2500BASEX;
-@@ -3247,7 +3231,7 @@ mt753x_setup(struct dsa_switch *ds)
+@@ -3263,7 +3247,7 @@ mt753x_setup(struct dsa_switch *ds)
mt7530_free_irq_common(priv);
if (priv->create_sgmii) {
}
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
-@@ -712,7 +712,6 @@ enum p5_interface_select {
+@@ -717,7 +717,6 @@ enum p5_interface_select {
P5_INTF_SEL_PHY_P0,
P5_INTF_SEL_PHY_P4,
P5_INTF_SEL_GMAC5,
};
struct mt7530_priv;
-@@ -781,6 +780,8 @@ struct mt753x_info {
+@@ -786,6 +785,8 @@ struct mt753x_info {
* registers
* @p6_interface Holding the current port 6 interface
* @p5_intf_sel: Holding the current port 5 interface select
* @irq: IRQ number of the switch
* @irq_domain: IRQ domain of the switch irq_chip
* @irq_enable: IRQ enable bits, synced to SYS_INT_EN
-@@ -802,6 +803,7 @@ struct mt7530_priv {
+@@ -807,6 +808,7 @@ struct mt7530_priv {
phy_interface_t p6_interface;
phy_interface_t p5_interface;
enum p5_interface_select p5_intf_sel;
u8 mirror_rx;
u8 mirror_tx;
struct mt7530_port ports[MT7530_NUM_PORTS];
-@@ -811,7 +813,7 @@ struct mt7530_priv {
+@@ -816,7 +818,7 @@ struct mt7530_priv {
int irq;
struct irq_domain *irq_domain;
u32 irq_enable;
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2735,12 +2735,14 @@ static void mt7530_mac_port_get_caps(str
+@@ -2751,12 +2751,14 @@ static void mt7530_mac_port_get_caps(str
struct phylink_config *config)
{
switch (port) {
phy_interface_set_rgmii(config->supported_interfaces);
__set_bit(PHY_INTERFACE_MODE_MII,
config->supported_interfaces);
-@@ -2748,7 +2750,8 @@ static void mt7530_mac_port_get_caps(str
+@@ -2764,7 +2766,8 @@ static void mt7530_mac_port_get_caps(str
config->supported_interfaces);
break;
__set_bit(PHY_INTERFACE_MODE_RGMII,
config->supported_interfaces);
__set_bit(PHY_INTERFACE_MODE_TRGMII,
-@@ -2763,19 +2766,24 @@ static void mt7531_mac_port_get_caps(str
+@@ -2779,19 +2782,24 @@ static void mt7531_mac_port_get_caps(str
struct mt7530_priv *priv = ds->priv;
switch (port) {
__set_bit(PHY_INTERFACE_MODE_SGMII,
config->supported_interfaces);
__set_bit(PHY_INTERFACE_MODE_1000BASEX,
-@@ -2794,11 +2802,13 @@ static void mt7988_mac_port_get_caps(str
+@@ -2810,11 +2818,13 @@ static void mt7988_mac_port_get_caps(str
phy_interface_zero(config->supported_interfaces);
switch (port) {
case 6:
__set_bit(PHY_INTERFACE_MODE_INTERNAL,
config->supported_interfaces);
-@@ -2962,12 +2972,12 @@ mt753x_phylink_mac_config(struct dsa_swi
+@@ -2978,12 +2988,12 @@ mt753x_phylink_mac_config(struct dsa_swi
u32 mcr_cur, mcr_new;
switch (port) {
if (priv->p5_interface == state->interface)
break;
-@@ -2977,7 +2987,7 @@ mt753x_phylink_mac_config(struct dsa_swi
+@@ -2993,7 +3003,7 @@ mt753x_phylink_mac_config(struct dsa_swi
if (priv->p5_intf_sel != P5_DISABLED)
priv->p5_interface = state->interface;
break;
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2523,16 +2523,15 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2529,16 +2529,15 @@ mt7530_setup(struct dsa_switch *ds)
return ret;
/* Setup port 5 */
for_each_child_of_node(dn, mac_np) {
if (!of_device_is_compatible(mac_np,
"mediatek,eth-mac"))
-@@ -2563,6 +2562,8 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2569,6 +2568,8 @@ mt7530_setup(struct dsa_switch *ds)
of_node_put(phy_node);
break;
}
}
#ifdef CONFIG_GPIOLIB
-@@ -2573,8 +2574,6 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2579,8 +2580,6 @@ mt7530_setup(struct dsa_switch *ds)
}
#endif /* CONFIG_GPIOLIB */
default:
dev_err(ds->dev, "Unsupported p5_intf_sel %d\n",
priv->p5_intf_sel);
-@@ -2528,8 +2525,6 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2534,8 +2531,6 @@ mt7530_setup(struct dsa_switch *ds)
* Set priv->p5_intf_sel to the appropriate value if PHY muxing
* is detected.
*/
for_each_child_of_node(dn, mac_np) {
if (!of_device_is_compatible(mac_np,
"mediatek,eth-mac"))
-@@ -2561,7 +2556,9 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2567,7 +2562,9 @@ mt7530_setup(struct dsa_switch *ds)
break;
}
switch (interface) {
case PHY_INTERFACE_MODE_RGMII:
trgint = 0;
-@@ -2456,6 +2449,12 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2458,6 +2451,12 @@ mt7530_setup(struct dsa_switch *ds)
return -ENODEV;
}
return 0;
}
-@@ -2810,11 +2814,10 @@ mt7530_mac_config(struct dsa_switch *ds,
+@@ -2826,11 +2830,10 @@ mt7530_mac_config(struct dsa_switch *ds,
{
struct mt7530_priv *priv = ds->priv;
static void
mt7531_pll_setup(struct mt7530_priv *priv)
{
-@@ -2801,14 +2789,6 @@ static void mt7988_mac_port_get_caps(str
+@@ -2817,14 +2805,6 @@ static void mt7988_mac_port_get_caps(str
}
static int
mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
phy_interface_t interface)
{
-@@ -2973,8 +2953,6 @@ mt753x_phylink_mac_config(struct dsa_swi
+@@ -2989,8 +2969,6 @@ mt753x_phylink_mac_config(struct dsa_swi
if (priv->p6_interface == state->interface)
break;
if (mt753x_mac_config(ds, port, mode, state) < 0)
goto unsupported;
-@@ -3291,11 +3269,6 @@ mt753x_conduit_state_change(struct dsa_s
+@@ -3307,11 +3285,6 @@ mt753x_conduit_state_change(struct dsa_s
mt7530_rmw(priv, MT7530_MFC, CPU_EN | CPU_PORT_MASK, val);
}
static int mt7988_setup(struct dsa_switch *ds)
{
struct mt7530_priv *priv = ds->priv;
-@@ -3359,7 +3332,6 @@ const struct mt753x_info mt753x_table[]
+@@ -3375,7 +3348,6 @@ const struct mt753x_info mt753x_table[]
.phy_write_c22 = mt7530_phy_write_c22,
.phy_read_c45 = mt7530_phy_read_c45,
.phy_write_c45 = mt7530_phy_write_c45,
.mac_port_get_caps = mt7530_mac_port_get_caps,
.mac_port_config = mt7530_mac_config,
},
-@@ -3371,7 +3343,6 @@ const struct mt753x_info mt753x_table[]
+@@ -3387,7 +3359,6 @@ const struct mt753x_info mt753x_table[]
.phy_write_c22 = mt7530_phy_write_c22,
.phy_read_c45 = mt7530_phy_read_c45,
.phy_write_c45 = mt7530_phy_write_c45,
.mac_port_get_caps = mt7530_mac_port_get_caps,
.mac_port_config = mt7530_mac_config,
},
-@@ -3383,7 +3354,6 @@ const struct mt753x_info mt753x_table[]
+@@ -3399,7 +3370,6 @@ const struct mt753x_info mt753x_table[]
.phy_write_c22 = mt7531_ind_c22_phy_write,
.phy_read_c45 = mt7531_ind_c45_phy_read,
.phy_write_c45 = mt7531_ind_c45_phy_write,
.cpu_port_config = mt7531_cpu_port_config,
.mac_port_get_caps = mt7531_mac_port_get_caps,
.mac_port_config = mt7531_mac_config,
-@@ -3396,7 +3366,6 @@ const struct mt753x_info mt753x_table[]
+@@ -3412,7 +3382,6 @@ const struct mt753x_info mt753x_table[]
.phy_write_c22 = mt7531_ind_c22_phy_write,
.phy_read_c45 = mt7531_ind_c45_phy_read,
.phy_write_c45 = mt7531_ind_c45_phy_write,
.cpu_port_config = mt7988_cpu_port_config,
.mac_port_get_caps = mt7988_mac_port_get_caps,
.mac_port_config = mt7988_mac_config,
-@@ -3426,9 +3395,8 @@ mt7530_probe_common(struct mt7530_priv *
+@@ -3442,9 +3411,8 @@ mt7530_probe_common(struct mt7530_priv *
/* Sanity check if these required device operations are filled
* properly.
*/
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
-@@ -729,8 +729,6 @@ struct mt753x_pcs {
+@@ -734,8 +734,6 @@ struct mt753x_pcs {
* @phy_write_c22: Holding the way writing PHY port using C22
* @phy_read_c45: Holding the way reading PHY port using C45
* @phy_write_c45: Holding the way writing PHY port using C45
* @phy_mode_supported: Check if the PHY type is being supported on a certain
* port
* @mac_port_validate: Holding the way to set addition validate type for a
-@@ -751,7 +749,6 @@ struct mt753x_info {
+@@ -756,7 +754,6 @@ struct mt753x_info {
int regnum);
int (*phy_write_c45)(struct mt7530_priv *priv, int port, int devad,
int regnum, u16 val);
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2774,7 +2774,7 @@ static void mt7988_mac_port_get_caps(str
+@@ -2790,7 +2790,7 @@ static void mt7988_mac_port_get_caps(str
switch (port) {
/* Ports which are connected to switch PHYs. There is no MII pinout. */
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2770,8 +2770,6 @@ static void mt7531_mac_port_get_caps(str
+@@ -2786,8 +2786,6 @@ static void mt7531_mac_port_get_caps(str
static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port,
struct phylink_config *config)
{
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2853,17 +2853,6 @@ static bool mt753x_is_mac_port(u32 port)
+@@ -2869,17 +2869,6 @@ static bool mt753x_is_mac_port(u32 port)
}
static int
mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
phy_interface_t interface)
{
-@@ -2903,6 +2892,9 @@ mt753x_mac_config(struct dsa_switch *ds,
+@@ -2919,6 +2908,9 @@ mt753x_mac_config(struct dsa_switch *ds,
{
struct mt7530_priv *priv = ds->priv;
return priv->info->mac_port_config(ds, port, mode, state->interface);
}
-@@ -3366,7 +3358,6 @@ const struct mt753x_info mt753x_table[]
+@@ -3382,7 +3374,6 @@ const struct mt753x_info mt753x_table[]
.phy_write_c45 = mt7531_ind_c45_phy_write,
.cpu_port_config = mt7988_cpu_port_config,
.mac_port_get_caps = mt7988_mac_port_get_caps,
},
};
EXPORT_SYMBOL_GPL(mt753x_table);
-@@ -3394,8 +3385,7 @@ mt7530_probe_common(struct mt7530_priv *
+@@ -3410,8 +3401,7 @@ mt7530_probe_common(struct mt7530_priv *
* properly.
*/
if (!priv->info->sw_setup || !priv->info->phy_read_c22 ||
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2252,7 +2252,7 @@ mt7530_setup_irq(struct mt7530_priv *pri
+@@ -2254,7 +2254,7 @@ mt7530_setup_irq(struct mt7530_priv *pri
}
/* This register must be set for MT7530 to properly fire interrupts */
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2648,14 +2648,12 @@ mt7531_setup(struct dsa_switch *ds)
+@@ -2657,14 +2657,12 @@ mt7531_setup(struct dsa_switch *ds)
val = mt7530_read(priv, MT7531_TOP_SIG_SR);
priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN);
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2784,7 +2784,7 @@ static void mt7988_mac_port_get_caps(str
+@@ -2800,7 +2800,7 @@ static void mt7988_mac_port_get_caps(str
}
}
mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
phy_interface_t interface)
{
-@@ -2794,22 +2794,14 @@ mt7530_mac_config(struct dsa_switch *ds,
+@@ -2810,22 +2810,14 @@ mt7530_mac_config(struct dsa_switch *ds,
mt7530_setup_port5(priv->ds, interface);
else if (port == 6)
mt7530_setup_port6(priv->ds, interface);
val = mt7530_read(priv, MT7531_CLKGEN_CTRL);
val |= GP_CLK_EN;
val &= ~GP_MODE_MASK;
-@@ -2837,20 +2829,14 @@ static int mt7531_rgmii_setup(struct mt7
+@@ -2853,20 +2845,14 @@ static int mt7531_rgmii_setup(struct mt7
case PHY_INTERFACE_MODE_RGMII_ID:
break;
default:
mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
phy_interface_t interface)
{
-@@ -2858,42 +2844,21 @@ mt7531_mac_config(struct dsa_switch *ds,
+@@ -2874,42 +2860,21 @@ mt7531_mac_config(struct dsa_switch *ds,
struct phy_device *phydev;
struct dsa_port *dp;
}
static struct phylink_pcs *
-@@ -2922,17 +2887,11 @@ mt753x_phylink_mac_config(struct dsa_swi
+@@ -2938,17 +2903,11 @@ mt753x_phylink_mac_config(struct dsa_swi
u32 mcr_cur, mcr_new;
switch (port) {
if (priv->p5_intf_sel != P5_DISABLED)
priv->p5_interface = state->interface;
-@@ -2941,16 +2900,10 @@ mt753x_phylink_mac_config(struct dsa_swi
+@@ -2957,16 +2916,10 @@ mt753x_phylink_mac_config(struct dsa_swi
if (priv->p6_interface == state->interface)
break;
}
mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
-@@ -3033,7 +2986,6 @@ mt7531_cpu_port_config(struct dsa_switch
+@@ -3049,7 +3002,6 @@ mt7531_cpu_port_config(struct dsa_switch
struct mt7530_priv *priv = ds->priv;
phy_interface_t interface;
int speed;
switch (port) {
case 5:
-@@ -3058,9 +3010,8 @@ mt7531_cpu_port_config(struct dsa_switch
+@@ -3074,9 +3026,8 @@ mt7531_cpu_port_config(struct dsa_switch
else
speed = SPEED_1000;
mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL,
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
-@@ -755,9 +755,9 @@ struct mt753x_info {
+@@ -760,9 +760,9 @@ struct mt753x_info {
void (*mac_port_validate)(struct dsa_switch *ds, int port,
phy_interface_t interface,
unsigned long *supported);
- priv->p6_interface = PHY_INTERFACE_MODE_NA;
-
- mt753x_trap_frames(priv);
+ if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_40MHZ)
+ mt7530_pll_setup(priv);
- /* Enable and reset MIB counters */
-@@ -2474,9 +2462,7 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2477,9 +2465,7 @@ mt7530_setup(struct dsa_switch *ds)
mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
if (dsa_is_cpu_port(ds, i)) {
} else {
mt7530_port_disable(ds, i);
-@@ -2580,9 +2566,7 @@ mt7531_setup_common(struct dsa_switch *d
+@@ -2586,9 +2572,7 @@ mt7531_setup_common(struct dsa_switch *d
mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR);
if (dsa_is_cpu_port(ds, i)) {
} else {
mt7530_port_disable(ds, i);
-@@ -2671,10 +2655,6 @@ mt7531_setup(struct dsa_switch *ds)
+@@ -2680,10 +2664,6 @@ mt7531_setup(struct dsa_switch *ds)
mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
MT7531_GPIO0_INTERRUPT);
- priv->p5_interface = PHY_INTERFACE_MODE_NA;
- priv->p6_interface = PHY_INTERFACE_MODE_NA;
-
- /* Enable PHY core PLL, since phy_device has not yet been created
- * provided for phy_[read,write]_mmd_indirect is called, we provide
- * our own mt7531_ind_mmd_phy_[read,write] to complete this
-@@ -2886,26 +2866,9 @@ mt753x_phylink_mac_config(struct dsa_swi
+ /* Enable Energy-Efficient Ethernet (EEE) and PHY core PLL, since
+ * phy_device has not yet been created provided for
+ * phy_[read,write]_mmd_indirect is called, we provide our own
+@@ -2902,26 +2882,9 @@ mt753x_phylink_mac_config(struct dsa_swi
struct mt7530_priv *priv = ds->priv;
u32 mcr_cur, mcr_new;
mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
mcr_new = mcr_cur;
mcr_new &= ~PMCR_LINK_SETTINGS_MASK;
-@@ -2941,17 +2904,10 @@ static void mt753x_phylink_mac_link_up(s
+@@ -2957,17 +2920,10 @@ static void mt753x_phylink_mac_link_up(s
mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
mcr |= PMCR_FORCE_SPEED_1000;
break;
case SPEED_100:
-@@ -2969,6 +2925,7 @@ static void mt753x_phylink_mac_link_up(s
+@@ -2985,6 +2941,7 @@ static void mt753x_phylink_mac_link_up(s
if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) {
switch (speed) {
case SPEED_1000:
mcr |= PMCR_FORCE_EEE1G;
break;
case SPEED_100:
-@@ -2980,61 +2937,6 @@ static void mt753x_phylink_mac_link_up(s
+@@ -2996,61 +2953,6 @@ static void mt753x_phylink_mac_link_up(s
mt7530_set(priv, MT7530_PMCR_P(port), mcr);
}
static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port,
struct phylink_config *config)
{
-@@ -3293,7 +3195,6 @@ const struct mt753x_info mt753x_table[]
+@@ -3309,7 +3211,6 @@ const struct mt753x_info mt753x_table[]
.phy_write_c22 = mt7531_ind_c22_phy_write,
.phy_read_c45 = mt7531_ind_c45_phy_read,
.phy_write_c45 = mt7531_ind_c45_phy_write,
.mac_port_get_caps = mt7531_mac_port_get_caps,
.mac_port_config = mt7531_mac_config,
},
-@@ -3305,7 +3206,6 @@ const struct mt753x_info mt753x_table[]
+@@ -3321,7 +3222,6 @@ const struct mt753x_info mt753x_table[]
.phy_write_c22 = mt7531_ind_c22_phy_write,
.phy_read_c45 = mt7531_ind_c45_phy_read,
.phy_write_c45 = mt7531_ind_c45_phy_write,
};
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
-@@ -336,13 +336,6 @@ enum mt7530_vlan_port_acc_frm {
+@@ -340,13 +340,6 @@ enum mt7530_vlan_port_acc_frm {
PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
PMCR_FORCE_FDX | PMCR_FORCE_LNK | \
PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100)
#define MT7530_PMEEECR_P(x) (0x3004 + (x) * 0x100)
#define WAKEUP_TIME_1000(x) (((x) & 0xFF) << 24)
-@@ -749,7 +742,6 @@ struct mt753x_info {
+@@ -754,7 +747,6 @@ struct mt753x_info {
int regnum);
int (*phy_write_c45)(struct mt7530_priv *priv, int port, int devad,
int regnum, u16 val);
void (*mac_port_get_caps)(struct dsa_switch *ds, int port,
struct phylink_config *config);
void (*mac_port_validate)(struct dsa_switch *ds, int port,
-@@ -775,7 +767,6 @@ struct mt753x_info {
+@@ -780,7 +772,6 @@ struct mt753x_info {
* @ports: Holding the state among ports
* @reg_mutex: The lock for protecting among process accessing
* registers
* @p5_intf_sel: Holding the current port 5 interface select
* @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch
* has got SGMII
-@@ -797,8 +788,6 @@ struct mt7530_priv {
+@@ -802,8 +793,6 @@ struct mt7530_priv {
const struct mt753x_info *info;
unsigned int id;
bool mcm;
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2831,16 +2831,6 @@ mt7531_mac_config(struct dsa_switch *ds,
+@@ -2847,16 +2847,6 @@ mt7531_mac_config(struct dsa_switch *ds,
}
}
static struct phylink_pcs *
mt753x_phylink_mac_select_pcs(struct dsa_switch *ds, int port,
phy_interface_t interface)
-@@ -2866,8 +2856,8 @@ mt753x_phylink_mac_config(struct dsa_swi
+@@ -2882,8 +2872,8 @@ mt753x_phylink_mac_config(struct dsa_swi
struct mt7530_priv *priv = ds->priv;
u32 mcr_cur, mcr_new;
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -3009,17 +3009,9 @@ static int
+@@ -3025,17 +3025,9 @@ static int
mt753x_setup(struct dsa_switch *ds)
{
struct mt7530_priv *priv = ds->priv;
if (ret)
return ret;
-@@ -3031,6 +3023,14 @@ mt753x_setup(struct dsa_switch *ds)
+@@ -3047,6 +3039,14 @@ mt753x_setup(struct dsa_switch *ds)
if (ret && priv->irq)
mt7530_free_irq_common(priv);
mutex_unlock(&priv->reg_mutex);
}
-@@ -2454,6 +2452,12 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2457,6 +2455,12 @@ mt7530_setup(struct dsa_switch *ds)
mt7530_mib_reset(ds);
for (i = 0; i < MT7530_NUM_PORTS; i++) {
/* Disable forwarding by default on all ports */
mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
PCR_MATRIX_CLR);
-@@ -2556,6 +2560,12 @@ mt7531_setup_common(struct dsa_switch *d
+@@ -2562,6 +2566,12 @@ mt7531_setup_common(struct dsa_switch *d
UNU_FFP_MASK);
for (i = 0; i < MT7530_NUM_PORTS; i++) {
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2864,23 +2864,13 @@ mt753x_phylink_mac_config(struct dsa_swi
+@@ -2880,23 +2880,13 @@ mt753x_phylink_mac_config(struct dsa_swi
const struct phylink_link_state *state)
{
struct mt7530_priv *priv = ds->priv;
static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port,
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
-@@ -329,8 +329,6 @@ enum mt7530_vlan_port_acc_frm {
+@@ -333,8 +333,6 @@ enum mt7530_vlan_port_acc_frm {
MT7531_FORCE_DPX | \
MT7531_FORCE_RX_FC | \
MT7531_FORCE_TX_FC)
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2389,6 +2389,12 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2391,6 +2391,12 @@ mt7530_setup(struct dsa_switch *ds)
}
}
+++ /dev/null
-From fa14c96eab3ec5b7cb44b06c0a54a851849a9810 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
-Date: Wed, 20 Mar 2024 23:45:30 +0300
-Subject: [PATCH 29/30] net: dsa: mt7530: fix improper frames on all 25MHz and
- 40MHz XTAL MT7530
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The MT7530 switch after reset initialises with a core clock frequency that
-works with a 25MHz XTAL connected to it. For 40MHz XTAL, the core clock
-frequency must be set to 500MHz.
-
-The mt7530_pll_setup() function is responsible of setting the core clock
-frequency. Currently, it runs on MT7530 with 25MHz and 40MHz XTAL. This
-causes MT7530 switch with 25MHz XTAL to egress and ingress frames
-improperly.
-
-Introduce a check to run it only on MT7530 with 40MHz XTAL.
-
-The core clock frequency is set by writing to a switch PHY's register.
-Access to the PHY's register is done via the MDIO bus the switch is also
-on. Therefore, it works only when the switch makes switch PHYs listen on
-the MDIO bus the switch is on. This is controlled either by the state of
-the ESW_P1_LED_1 pin after reset deassertion or modifying bit 5 of the
-modifiable trap register.
-
-When ESW_P1_LED_1 is pulled high, PHY indirect access is used. That means
-accessing PHY registers via the PHY indirect access control register of the
-switch.
-
-When ESW_P1_LED_1 is pulled low, PHY direct access is used. That means
-accessing PHY registers via the MDIO bus the switch is on.
-
-For MT7530 switch with 40MHz XTAL on a board with ESW_P1_LED_1 pulled high,
-the core clock frequency won't be set to 500MHz, causing the switch to
-egress and ingress frames improperly.
-
-Run mt7530_pll_setup() after PHY direct access is set on the modifiable
-trap register.
-
-With these two changes, all MT7530 switches with 25MHz and 40MHz, and
-P1_LED_1 pulled high or low, will egress and ingress frames properly.
-
-Link: https://github.com/BPI-SINOVOIP/BPI-R2-bsp/blob/4a5dd143f2172ec97a2872fa29c7c4cd520f45b5/linux-mt/drivers/net/ethernet/mediatek/gsw_mt7623.c#L1039
-Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 switch")
-Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
-Link: https://lore.kernel.org/r/20240320-for-net-mt7530-fix-25mhz-xtal-with-direct-phy-access-v1-1-d92f605f1160@arinc9.com
-Signed-off-by: Paolo Abeni <pabeni@redhat.com>
----
- drivers/net/dsa/mt7530.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -2435,8 +2435,6 @@ mt7530_setup(struct dsa_switch *ds)
- SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
- SYS_CTRL_REG_RST);
-
-- mt7530_pll_setup(priv);
--
- /* Lower Tx driving for TRGMII path */
- for (i = 0; i < NUM_TRGMII_CTRL; i++)
- mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
-@@ -2452,6 +2450,9 @@ mt7530_setup(struct dsa_switch *ds)
- val |= MHWTRAP_MANUAL;
- mt7530_write(priv, MT7530_MHWTRAP, val);
-
-+ if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_40MHZ)
-+ mt7530_pll_setup(priv);
-+
- mt753x_trap_frames(priv);
-
- /* Enable and reset MIB counters */
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2389,12 +2389,6 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2391,12 +2391,6 @@ mt7530_setup(struct dsa_switch *ds)
}
}
+++ /dev/null
-From ef972fc9f5743da589ce9546dd565d6c56e679b8 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
-Date: Mon, 8 Apr 2024 10:08:53 +0300
-Subject: [PATCH 1/2] net: dsa: mt7530: fix enabling EEE on MT7531 switch on
- all boards
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The commit 40b5d2f15c09 ("net: dsa: mt7530: Add support for EEE features")
-brought EEE support but did not enable EEE on MT7531 switch MACs. EEE is
-enabled on MT7531 switch MACs by pulling the LAN2LED0 pin low on the board
-(bootstrapping), unsetting the EEE_DIS bit on the trap register, or setting
-the internal EEE switch bit on the CORE_PLL_GROUP4 register. Thanks to
-SkyLake Huang (黃啟澤) from MediaTek for providing information on the
-internal EEE switch bit.
-
-There are existing boards that were not designed to pull the pin low.
-Because of that, the EEE status currently depends on the board design.
-
-The EEE_DIS bit on the trap pertains to the LAN2LED0 pin which is usually
-used to control an LED. Once the bit is unset, the pin will be low. That
-will make the active low LED turn on. The pin is controlled by the switch
-PHY. It seems that the PHY controls the pin in the way that it inverts the
-pin state. That means depending on the wiring of the LED connected to
-LAN2LED0 on the board, the LED may be on without an active link.
-
-To not cause this unwanted behaviour whilst enabling EEE on all boards, set
-the internal EEE switch bit on the CORE_PLL_GROUP4 register.
-
-My testing on MT7531 shows a certain amount of traffic loss when EEE is
-enabled. That said, I haven't come across a board that enables EEE. So
-enable EEE on the switch MACs but disable EEE advertisement on the switch
-PHYs. This way, we don't change the behaviour of the majority of the boards
-that have this switch. The mediatek-ge PHY driver already disables EEE
-advertisement on the switch PHYs but my testing shows that it is somehow
-enabled afterwards. Disabling EEE advertisement before the PHY driver
-initialises keeps it off.
-
-With this change, EEE can now be enabled using ethtool.
-
-Fixes: 40b5d2f15c09 ("net: dsa: mt7530: Add support for EEE features")
-Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
-Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
----
- drivers/net/dsa/mt7530.c | 17 ++++++++++++-----
- drivers/net/dsa/mt7530.h | 1 +
- 2 files changed, 13 insertions(+), 5 deletions(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -2666,18 +2666,25 @@ mt7531_setup(struct dsa_switch *ds)
- mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
- MT7531_GPIO0_INTERRUPT);
-
-- /* Enable PHY core PLL, since phy_device has not yet been created
-- * provided for phy_[read,write]_mmd_indirect is called, we provide
-- * our own mt7531_ind_mmd_phy_[read,write] to complete this
-- * function.
-+ /* Enable Energy-Efficient Ethernet (EEE) and PHY core PLL, since
-+ * phy_device has not yet been created provided for
-+ * phy_[read,write]_mmd_indirect is called, we provide our own
-+ * mt7531_ind_mmd_phy_[read,write] to complete this function.
- */
- val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR,
- MDIO_MMD_VEND2, CORE_PLL_GROUP4);
-- val |= MT7531_PHY_PLL_BYPASS_MODE;
-+ val |= MT7531_RG_SYSPLL_DMY2 | MT7531_PHY_PLL_BYPASS_MODE;
- val &= ~MT7531_PHY_PLL_OFF;
- mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2,
- CORE_PLL_GROUP4, val);
-
-+ /* Disable EEE advertisement on the switch PHYs. */
-+ for (i = MT753X_CTRL_PHY_ADDR;
-+ i < MT753X_CTRL_PHY_ADDR + MT7530_NUM_PHYS; i++) {
-+ mt7531_ind_c45_phy_write(priv, i, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
-+ 0);
-+ }
-+
- mt7531_setup_common(ds);
-
- /* Setup VLAN ID 0 for VLAN-unaware bridges */
---- a/drivers/net/dsa/mt7530.h
-+++ b/drivers/net/dsa/mt7530.h
-@@ -621,6 +621,7 @@ enum mt7531_clk_skew {
- #define RG_SYSPLL_DDSFBK_EN BIT(12)
- #define RG_SYSPLL_BIAS_EN BIT(11)
- #define RG_SYSPLL_BIAS_LPF_EN BIT(10)
-+#define MT7531_RG_SYSPLL_DMY2 BIT(6)
- #define MT7531_PHY_PLL_OFF BIT(5)
- #define MT7531_PHY_PLL_BYPASS_MODE BIT(4)
-
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2850,28 +2850,34 @@ mt7531_mac_config(struct dsa_switch *ds,
+@@ -2858,28 +2858,34 @@ mt7531_mac_config(struct dsa_switch *ds,
}
static struct phylink_pcs *
if ((port == 5 || port == 6) && priv->info->mac_port_config)
priv->info->mac_port_config(ds, port, mode, state->interface);
-@@ -2881,23 +2887,25 @@ mt753x_phylink_mac_config(struct dsa_swi
+@@ -2889,23 +2895,25 @@ mt753x_phylink_mac_config(struct dsa_swi
mt7530_set(priv, MT7530_PMCR_P(port), PMCR_EXT_PHY);
}
u32 mcr;
mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
-@@ -2932,7 +2940,7 @@ static void mt753x_phylink_mac_link_up(s
+@@ -2940,7 +2948,7 @@ static void mt753x_phylink_mac_link_up(s
}
}
}
static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port,
-@@ -3152,16 +3160,19 @@ const struct dsa_switch_ops mt7530_switc
+@@ -3160,16 +3168,19 @@ const struct dsa_switch_ops mt7530_switc
.port_mirror_add = mt753x_port_mirror_add,
.port_mirror_del = mt753x_port_mirror_del,
.phylink_get_caps = mt753x_phylink_get_caps,
const struct mt753x_info mt753x_table[] = {
[ID_MT7621] = {
.id = ID_MT7621,
-@@ -3239,6 +3250,7 @@ mt7530_probe_common(struct mt7530_priv *
+@@ -3247,6 +3258,7 @@ mt7530_probe_common(struct mt7530_priv *
priv->dev = dev;
priv->ds->priv = priv;
priv->ds->ops = &mt7530_switch_ops;
+++ /dev/null
-From d4097ddef078a113643a6dcde01e99741f852adb Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
-Date: Sat, 13 Apr 2024 16:01:39 +0300
-Subject: [PATCH 2/5] net: dsa: mt7530: fix mirroring frames received on local
- port
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This switch intellectual property provides a bit on the ARL global control
-register which controls allowing mirroring frames which are received on the
-local port (monitor port). This bit is unset after reset.
-
-This ability must be enabled to fully support the port mirroring feature on
-this switch intellectual property.
-
-Therefore, this patch fixes the traffic not being reflected on a port,
-which would be configured like below:
-
- tc qdisc add dev swp0 clsact
-
- tc filter add dev swp0 ingress matchall skip_sw \
- action mirred egress mirror dev swp0
-
-As a side note, this configuration provides the hairpinning feature for a
-single port.
-
-Fixes: 37feab6076aa ("net: dsa: mt7530: add support for port mirroring")
-Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/dsa/mt7530.c | 6 ++++++
- drivers/net/dsa/mt7530.h | 4 ++++
- 2 files changed, 10 insertions(+)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -2480,6 +2480,9 @@ mt7530_setup(struct dsa_switch *ds)
- PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
- }
-
-+ /* Allow mirroring frames received on the local port (monitor port). */
-+ mt7530_set(priv, MT753X_AGC, LOCAL_EN);
-+
- /* Setup VLAN ID 0 for VLAN-unaware bridges */
- ret = mt7530_setup_vlan0(priv);
- if (ret)
-@@ -2591,6 +2594,9 @@ mt7531_setup_common(struct dsa_switch *d
- PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
- }
-
-+ /* Allow mirroring frames received on the local port (monitor port). */
-+ mt7530_set(priv, MT753X_AGC, LOCAL_EN);
-+
- /* Flush the FDB table */
- ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
- if (ret < 0)
---- a/drivers/net/dsa/mt7530.h
-+++ b/drivers/net/dsa/mt7530.h
-@@ -32,6 +32,10 @@ enum mt753x_id {
- #define SYSC_REG_RSTCTRL 0x34
- #define RESET_MCM BIT(2)
-
-+/* Register for ARL global control */
-+#define MT753X_AGC 0xc
-+#define LOCAL_EN BIT(7)
-+
- /* Registers to mac forward control for unknown frames */
- #define MT7530_MFC 0x10
- #define BC_FFP(x) (((x) & 0xff) << 24)
+++ /dev/null
-From 019a17a5e76940ea86114838d1d638d4dc8d3750 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
-Date: Sat, 13 Apr 2024 16:01:40 +0300
-Subject: [PATCH 3/5] net: dsa: mt7530: fix port mirroring for MT7988 SoC
- switch
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The "MT7988A Wi-Fi 7 Generation Router Platform: Datasheet (Open Version)
-v0.1" document shows bits 16 to 18 as the MIRROR_PORT field of the CPU
-forward control register. Currently, the MT7530 DSA subdriver configures
-bits 0 to 2 of the CPU forward control register which breaks the port
-mirroring feature for the MT7988 SoC switch.
-
-Fix this by using the MT7531_MIRROR_PORT_GET() and MT7531_MIRROR_PORT_SET()
-macros which utilise the correct bits.
-
-Fixes: 110c18bfed41 ("net: dsa: mt7530: introduce driver for MT7988 built-in switch")
-Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
-Acked-by: Daniel Golle <daniel@makrotopia.org>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/dsa/mt7530.c | 10 ++++++----
- 1 file changed, 6 insertions(+), 4 deletions(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -1883,14 +1883,16 @@ mt7530_port_vlan_del(struct dsa_switch *
-
- static int mt753x_mirror_port_get(unsigned int id, u32 val)
- {
-- return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) :
-- MIRROR_PORT(val);
-+ return (id == ID_MT7531 || id == ID_MT7988) ?
-+ MT7531_MIRROR_PORT_GET(val) :
-+ MIRROR_PORT(val);
- }
-
- static int mt753x_mirror_port_set(unsigned int id, u32 val)
- {
-- return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) :
-- MIRROR_PORT(val);
-+ return (id == ID_MT7531 || id == ID_MT7988) ?
-+ MT7531_MIRROR_PORT_SET(val) :
-+ MIRROR_PORT(val);
- }
-
- static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,
#define QUECTEL_VENDOR_ID 0x2c7c
/* These Quectel products use Quectel's vendor ID */
-@@ -1152,6 +1157,11 @@ static const struct usb_device_id option
+@@ -1156,6 +1161,11 @@ static const struct usb_device_id option
{ USB_DEVICE(QUALCOMM_VENDOR_ID, 0x0023)}, /* ONYX 3G device */
{ USB_DEVICE(QUALCOMM_VENDOR_ID, 0x9000), /* SIMCom SIM5218 */
.driver_info = NCTRL(0) | NCTRL(1) | NCTRL(2) | NCTRL(3) | RSVD(4) },
/* Quectel products using Qualcomm vendor ID */
{ USB_DEVICE(QUALCOMM_VENDOR_ID, QUECTEL_PRODUCT_UC15)},
{ USB_DEVICE(QUALCOMM_VENDOR_ID, QUECTEL_PRODUCT_UC20),
-@@ -1193,6 +1203,11 @@ static const struct usb_device_id option
+@@ -1197,6 +1207,11 @@ static const struct usb_device_id option
.driver_info = ZLP },
{ USB_DEVICE(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_BG96),
.driver_info = RSVD(4) },
--- a/net/bridge/br_input.c
+++ b/net/bridge/br_input.c
-@@ -239,6 +239,9 @@ static void __br_handle_local_finish(str
+@@ -244,6 +244,9 @@ static void __br_handle_local_finish(str
/* note: already called with rcu_read_lock */
static int br_handle_local_finish(struct net *net, struct sock *sk, struct sk_buff *skb)
{
__br_handle_local_finish(skb);
/* return 1 to signal the okfn() was called so it's ok to use the skb */
-@@ -408,6 +411,17 @@ forward:
+@@ -415,6 +418,17 @@ forward:
goto defer_stp_filtering;
switch (p->state) {
--- a/net/netfilter/nf_tables_api.c
+++ b/net/netfilter/nf_tables_api.c
-@@ -8260,7 +8260,7 @@ static int nft_register_flowtable_net_ho
+@@ -8268,7 +8268,7 @@ static int nft_register_flowtable_net_ho
err = flowtable->data.type->setup(&flowtable->data,
hook->ops.dev,
FLOW_BLOCK_BIND);
if (!(p->flags & BR_BCAST_FLOOD) && skb->dev != br->dev)
--- a/net/bridge/br_input.c
+++ b/net/bridge/br_input.c
-@@ -362,6 +362,8 @@ static rx_handler_result_t br_handle_fra
+@@ -367,6 +367,8 @@ static rx_handler_result_t br_handle_fra
fwd_mask |= p->group_fwd_mask;
switch (dest[5]) {
case 0x00: /* Bridge Group Address */
#endif /* __LINUX_USB_PCI_QUIRKS_H */
--- a/include/linux/usb/hcd.h
+++ b/include/linux/usb/hcd.h
-@@ -484,7 +484,14 @@ extern int usb_hcd_pci_probe(struct pci_
+@@ -485,7 +485,14 @@ extern int usb_hcd_pci_probe(struct pci_
extern void usb_hcd_pci_remove(struct pci_dev *dev);
extern void usb_hcd_pci_shutdown(struct pci_dev *dev);
/*
* We need to store the untouched command line for future reference.
* We also need to store the touched command line since the parameter
-@@ -896,6 +919,7 @@ void start_kernel(void)
+@@ -898,6 +921,7 @@ void start_kernel(void)
pr_notice("%s", linux_banner);
early_security_init();
setup_arch(&command_line);
#include <linux/bootconfig.h>
#include <linux/console.h>
#include <linux/nmi.h>
-@@ -930,6 +931,17 @@ void start_kernel(void)
+@@ -932,6 +933,17 @@ void start_kernel(void)
pr_notice("Kernel command line: %s\n", saved_command_line);
/* parameters may set static keys */
jump_label_init();
--- a/drivers/net/ethernet/mediatek/mtk_wed.c
+++ b/drivers/net/ethernet/mediatek/mtk_wed.c
-@@ -1321,6 +1321,24 @@ mtk_wed_rro_alloc(struct mtk_wed_device
+@@ -1320,6 +1320,24 @@ mtk_wed_rro_alloc(struct mtk_wed_device
struct device_node *np;
int index;
index = of_property_match_string(dev->hw->node, "memory-region-names",
"wo-dlm");
if (index < 0)
-@@ -1337,6 +1355,7 @@ mtk_wed_rro_alloc(struct mtk_wed_device
+@@ -1336,6 +1354,7 @@ mtk_wed_rro_alloc(struct mtk_wed_device
return -ENODEV;
dev->rro.miod_phys = rmem->base;
+++ /dev/null
-From: Felix Fietkau <nbd@nbd.name>
-Date: Thu, 18 Jan 2024 12:51:32 +0100
-Subject: [PATCH] net: ethernet: mtk_eth_soc: fix WED + wifi reset
-
-The WLAN + WED reset sequence relies on being able to receive interrupts from
-the card, in order to synchronize individual steps with the firmware.
-When WED is stopped, leave interrupts running and rely on the driver turning
-off unwanted ones.
-WED DMA also needs to be disabled before resetting.
-
-Fixes: f78cd9c783e0 ("net: ethernet: mtk_wed: update mtk_wed_stop")
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/drivers/net/ethernet/mediatek/mtk_wed.c
-+++ b/drivers/net/ethernet/mediatek/mtk_wed.c
-@@ -1072,13 +1072,13 @@ mtk_wed_dma_disable(struct mtk_wed_devic
- static void
- mtk_wed_stop(struct mtk_wed_device *dev)
- {
-+ mtk_wed_dma_disable(dev);
- mtk_wed_set_ext_int(dev, false);
-
- wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER, 0);
- wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, 0);
- wdma_w32(dev, MTK_WDMA_INT_MASK, 0);
- wdma_w32(dev, MTK_WDMA_INT_GRP2, 0);
-- wed_w32(dev, MTK_WED_WPDMA_INT_MASK, 0);
-
- if (!mtk_wed_get_rx_capa(dev))
- return;
-@@ -1091,7 +1091,6 @@ static void
- mtk_wed_deinit(struct mtk_wed_device *dev)
- {
- mtk_wed_stop(dev);
-- mtk_wed_dma_disable(dev);
-
- wed_clr(dev, MTK_WED_CTRL,
- MTK_WED_CTRL_WDMA_INT_AGENT_EN |
-@@ -2622,9 +2621,6 @@ mtk_wed_irq_get(struct mtk_wed_device *d
- static void
- mtk_wed_irq_set_mask(struct mtk_wed_device *dev, u32 mask)
- {
-- if (!dev->running)
-- return;
--
- mtk_wed_set_ext_int(dev, !!mask);
- wed_w32(dev, MTK_WED_INT_MASK, mask);
- }
static int kernel_init(void *);
/*
-@@ -928,6 +932,18 @@ void start_kernel(void)
+@@ -930,6 +934,18 @@ void start_kernel(void)
boot_cpu_hotplug_init();
pr_notice("Kernel command line: %s\n", saved_command_line);
--- a/drivers/tty/serial/serial_core.c
+++ b/drivers/tty/serial/serial_core.c
-@@ -467,6 +467,9 @@ uart_get_baud_rate(struct uart_port *por
+@@ -480,6 +480,9 @@ uart_get_baud_rate(struct uart_port *por
break;
}
projects / openwrt / staging / jow.git / commitdiff