drm/i915/gt: prefer struct drm_device based logging

Prefer struct drm_device based logging over struct device based logging.

No functional changes.

Cc: Wambui Karuga <wambui.karugax@gmail.com>
Reviewed-by: Wambui Karuga <wambui.karugax@gmail.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200402114819.17232-16-jani.nikula@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index ae07bcd7c226204df8885c43631ccbb0640fd3c3..eebd1190506f65a1629affbc5429aaf97ee8adfb 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -1080,7 +1080,7 @@ static int i915_gmch_probe(struct i915_ggtt *ggtt)
        ggtt->vm.vma_ops.clear_pages = clear_pages;
 
        if (unlikely(ggtt->do_idle_maps))
-               dev_notice(i915->drm.dev,
+               drm_notice(&i915->drm,
                           "Applying Ironlake quirks for intel_iommu\n");
 
        return 0;
@@ -1145,7 +1145,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private *i915)
                return ret;
 
        if (intel_vtd_active())
-               dev_info(i915->drm.dev, "VT-d active for gfx access\n");
+               drm_info(&i915->drm, "VT-d active for gfx access\n");
 
        return 0;
 }

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index 2e40400d1ecdf6502a70bdea8bab1226f84ea38f..3e8a56c7d818e6c05a084d33163a478bac37e7a1 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -204,7 +204,7 @@ int intel_gt_resume(struct intel_gt *gt)
        /* Only when the HW is re-initialised, can we replay the requests */
        err = intel_gt_init_hw(gt);
        if (err) {
-               dev_err(gt->i915->drm.dev,
+               drm_err(&gt->i915->drm,
                        "Failed to initialize GPU, declaring it wedged!\n");
                goto err_wedged;
        }
@@ -220,7 +220,7 @@ int intel_gt_resume(struct intel_gt *gt)
 
                intel_engine_pm_put(engine);
                if (err) {
-                       dev_err(gt->i915->drm.dev,
+                       drm_err(&gt->i915->drm,
                                "Failed to restart %s (%d)\n",
                                engine->name, err);
                        goto err_wedged;

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 7adc73a5b7094b91c4787cf7b6cb14da77968142..6fbad5e2343f967f4a25af630a92464edb50bb98 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3129,7 +3129,7 @@ check_redzone(const void *vaddr, const struct intel_engine_cs *engine)
        vaddr += engine->context_size;
 
        if (memchr_inv(vaddr, CONTEXT_REDZONE, I915_GTT_PAGE_SIZE))
-               dev_err_once(engine->i915->drm.dev,
+               drm_err_once(&engine->i915->drm,
                             "%s context redzone overwritten!\n",
                             engine->name);
 }
@@ -3625,7 +3625,7 @@ static void enable_error_interrupt(struct intel_engine_cs *engine)
 
        status = ENGINE_READ(engine, RING_ESR);
        if (unlikely(status)) {
-               dev_err(engine->i915->drm.dev,
+               drm_err(&engine->i915->drm,
                        "engine '%s' resumed still in error: %08x\n",
                        engine->name, status);
                __intel_gt_reset(engine->gt, engine->mask);

diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 09d3e5a45397ef2f674d35e1fca024011d16f57c..1c1923ec8be7404a32fd79184a94fe0dad856b02 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -468,7 +468,7 @@ static bool rc6_supported(struct intel_rc6 *rc6)
                return false;
 
        if (IS_GEN9_LP(i915) && !bxt_check_bios_rc6_setup(rc6)) {
-               dev_notice(i915->drm.dev,
+               drm_notice(&i915->drm,
                           "RC6 and powersaving disabled by BIOS\n");
                return false;
        }
@@ -500,7 +500,7 @@ static bool pctx_corrupted(struct intel_rc6 *rc6)
        if (intel_uncore_read(rc6_to_uncore(rc6), GEN8_RC6_CTX_INFO))
                return false;
 
-       dev_notice(i915->drm.dev,
+       drm_notice(&i915->drm,
                   "RC6 context corruption, disabling runtime power management\n");
        return true;
 }

diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index 003f26b429983a5a2af3715a7ff76cd0bdb639eb..39070b514e65a4a602cb891a4b6a691827b5e4e0 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -109,7 +109,7 @@ static bool mark_guilty(struct i915_request *rq)
                goto out;
        }
 
-       dev_notice(ctx->i915->drm.dev,
+       drm_notice(&ctx->i915->drm,
                   "%s context reset due to GPU hang\n",
                   ctx->name);
 
@@ -1031,7 +1031,7 @@ void intel_gt_reset(struct intel_gt *gt,
                goto unlock;
 
        if (reason)
-               dev_notice(gt->i915->drm.dev,
+               drm_notice(&gt->i915->drm,
                           "Resetting chip for %s\n", reason);
        atomic_inc(&gt->i915->gpu_error.reset_count);
 
@@ -1039,7 +1039,7 @@ void intel_gt_reset(struct intel_gt *gt,
 
        if (!intel_has_gpu_reset(gt)) {
                if (i915_modparams.reset)
-                       dev_err(gt->i915->drm.dev, "GPU reset not supported\n");
+                       drm_err(&gt->i915->drm, "GPU reset not supported\n");
                else
                        drm_dbg(&gt->i915->drm, "GPU reset disabled\n");
                goto error;
@@ -1049,7 +1049,7 @@ void intel_gt_reset(struct intel_gt *gt,
                intel_runtime_pm_disable_interrupts(gt->i915);
 
        if (do_reset(gt, stalled_mask)) {
-               dev_err(gt->i915->drm.dev, "Failed to reset chip\n");
+               drm_err(&gt->i915->drm, "Failed to reset chip\n");
                goto taint;
        }
 
@@ -1111,7 +1111,7 @@ static inline int intel_gt_reset_engine(struct intel_engine_cs *engine)
 /**
  * intel_engine_reset - reset GPU engine to recover from a hang
  * @engine: engine to reset
- * @msg: reason for GPU reset; or NULL for no dev_notice()
+ * @msg: reason for GPU reset; or NULL for no drm_notice()
  *
  * Reset a specific GPU engine. Useful if a hang is detected.
  * Returns zero on successful reset or otherwise an error code.
@@ -1136,7 +1136,7 @@ int intel_engine_reset(struct intel_engine_cs *engine, const char *msg)
        reset_prepare_engine(engine);
 
        if (msg)
-               dev_notice(engine->i915->drm.dev,
+               drm_notice(&engine->i915->drm,
                           "Resetting %s for %s\n", engine->name, msg);
        atomic_inc(&engine->i915->gpu_error.reset_engine_count[engine->uabi_class]);
 
@@ -1381,7 +1381,7 @@ static void intel_wedge_me(struct work_struct *work)
 {
        struct intel_wedge_me *w = container_of(work, typeof(*w), work.work);
 
-       dev_err(w->gt->i915->drm.dev,
+       drm_err(&w->gt->i915->drm,
                "%s timed out, cancelling all in-flight rendering.\n",
                w->name);
        intel_gt_set_wedged(w->gt);