powerpc/64: More definitions for POWER9

This adds definitions for bits in the DSISR register which are used
by POWER9 for various translation-related exception conditions, and
for some more bits in the partition table entry that will be needed
by KVM.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

diff --git a/arch/powerpc/include/asm/book3s/64/mmu.h b/arch/powerpc/include/asm/book3s/64/mmu.h
index cea522c3bcae15324465fcac9f50fb2d536c45f2..d73e9dfa5237f4e11d63810c5439ab93b1b4f645 100644 (file)
--- a/arch/powerpc/include/asm/book3s/64/mmu.h
+++ b/arch/powerpc/include/asm/book3s/64/mmu.h
@@ -44,10 +44,20 @@ struct patb_entry {
 };
 extern struct patb_entry *partition_tb;
 
+/* Bits in patb0 field */
 #define PATB_HR                (1UL << 63)
-#define PATB_GR                (1UL << 63)
 #define RPDB_MASK      0x0ffffffffffff00fUL
 #define RPDB_SHIFT     (1UL << 8)
+#define RTS1_SHIFT     61              /* top 2 bits of radix tree size */
+#define RTS1_MASK      (3UL << RTS1_SHIFT)
+#define RTS2_SHIFT     5               /* bottom 3 bits of radix tree size */
+#define RTS2_MASK      (7UL << RTS2_SHIFT)
+#define RPDS_MASK      0x1f            /* root page dir. size field */
+
+/* Bits in patb1 field */
+#define PATB_GR                (1UL << 63)     /* guest uses radix; must match HR */
+#define PRTS_MASK      0x1f            /* process table size field */
+
 /*
  * Limit process table to PAGE_SIZE table. This
  * also limit the max pid we can support.

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 0d4531aa2052d77fb8036b05f3550c33cfdde49e..aa44a83ad3ec33c12292eecb721bed44a168f5dc 100644 (file)
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -274,10 +274,14 @@
 #define SPRN_DSISR     0x012   /* Data Storage Interrupt Status Register */
 #define   DSISR_NOHPTE         0x40000000      /* no translation found */
 #define   DSISR_PROTFAULT      0x08000000      /* protection fault */
+#define   DSISR_BADACCESS      0x04000000      /* bad access to CI or G */
 #define   DSISR_ISSTORE                0x02000000      /* access was a store */
 #define   DSISR_DABRMATCH      0x00400000      /* hit data breakpoint */
 #define   DSISR_NOSEGMENT      0x00200000      /* SLB miss */
 #define   DSISR_KEYFAULT       0x00200000      /* Key fault */
+#define   DSISR_UNSUPP_MMU     0x00080000      /* Unsupported MMU config */
+#define   DSISR_SET_RC         0x00040000      /* Failed setting of R/C bits */
+#define   DSISR_PGDIRFAULT      0x00020000      /* Fault on page directory */
 #define SPRN_TBRL      0x10C   /* Time Base Read Lower Register (user, R/O) */
 #define SPRN_TBRU      0x10D   /* Time Base Read Upper Register (user, R/O) */
 #define SPRN_CIR       0x11B   /* Chip Information Register (hyper, R/0) */