arm64: tegra: Add configuration for PCIe C5 sideband signals

Add support to configure PCIe C5's sideband signals PERST# and CLKREQ#
as output and bi-directional signals respectively which unlike other
PCIe controllers sideband signals are not configured by default.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>

diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index adebbbf36bd00f3a8fdb86184f08aa72eae71efa..3c0cf54f0aab36a88bdf3c1a288c0786eeeb21e8 100644 (file)
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -3,8 +3,9 @@
 #include <dt-bindings/gpio/tegra194-gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/mailbox/tegra186-hsp.h>
-#include <dt-bindings/reset/tegra194-reset.h>
+#include <dt-bindings/pinctrl/pinctrl-tegra.h>
 #include <dt-bindings/power/tegra194-powergate.h>
+#include <dt-bindings/reset/tegra194-reset.h>
 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
 
 / {
@@ -130,6 +131,38 @@
                        };
                };
 
+               pinmux: pinmux@2430000 {
+                       compatible = "nvidia,tegra194-pinmux";
+                       reg = <0x2430000 0x17000
+                              0xc300000 0x4000>;
+
+                       status = "okay";
+
+                       pex_rst_c5_out_state: pex_rst_c5_out {
+                               pex_rst {
+                                       nvidia,pins = "pex_l5_rst_n_pgg1";
+                                       nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+                                       nvidia,lpdr = <TEGRA_PIN_ENABLE>;
+                                       nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                       nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
+                                       nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                       nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                               };
+                       };
+
+                       clkreq_c5_bi_dir_state: clkreq_c5_bi_dir {
+                               clkreq {
+                                       nvidia,pins = "pex_l5_clkreq_n_pgg0";
+                                       nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+                                       nvidia,lpdr = <TEGRA_PIN_ENABLE>;
+                                       nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                       nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
+                                       nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                       nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                               };
+                       };
+               };
+
                uarta: serial@3100000 {
                        compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
                        reg = <0x03100000 0x40>;
@@ -1365,6 +1398,9 @@
                num-viewport = <8>;
                linux,pci-domain = <5>;
 
+               pinctrl-names = "default";
+               pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
+
                clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>,
                        <&bpmp TEGRA194_CLK_PEX1_CORE_5M>;
                clock-names = "core", "core_m";