ARM: dts: Add usb2phy to exynos5250

Add support to PHY of USB2 of the Exynos5250 SoC.

Signed-off-by: Kamil Debski <k.debski@samsung.com>
[gautam.vivek@samsung.com: Split the usb phy entries]
[gautam.vivek@samsung.com: Added phy entry for OHCI also along with EHCI]
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Vikas Sajjan <vikas.sajjan@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 8e9b9a31d9593358fb4816120d4078dd35bc9de3..cb296429b3ece4652b754338eb556e3b3154a614 100644 (file)
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -577,6 +577,12 @@
 
                clocks = <&clock CLK_USB2>;
                clock-names = "usbhost";
+               #address-cells = <1>;
+               #size-cells = <0>;
+               port@0 {
+                       reg = <0>;
+                       phys = <&usb2_phy_gen 1>;
+               };
        };
 
        usb@12120000 {
@@ -586,6 +592,12 @@
 
                clocks = <&clock CLK_USB2>;
                clock-names = "usbhost";
+               #address-cells = <1>;
+               #size-cells = <0>;
+               port@0 {
+                       reg = <0>;
+                       phys = <&usb2_phy_gen 1>;
+               };
        };
 
        usb2_phy: usbphy@12130000 {
@@ -603,6 +615,16 @@
                };
        };
 
+       usb2_phy_gen: phy@12130000 {
+               compatible = "samsung,exynos5250-usb2-phy";
+               reg = <0x12130000 0x100>;
+               clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
+               clock-names = "phy", "ref";
+               #phy-cells = <1>;
+               samsung,sysreg-phandle = <&sysreg_system_controller>;
+               samsung,pmureg-phandle = <&pmu_system_controller>;
+       };
+
        pwm: pwm@12dd0000 {
                compatible = "samsung,exynos4210-pwm";
                reg = <0x12dd0000 0x100>;