Hexagon: add support for additional exceptions

Add multi-reg-write and unaligned-PC exceptions.

Signed-off-by: Richard Kuo <rkuo@codeaurora.org>

diff --git a/arch/hexagon/kernel/traps.c b/arch/hexagon/kernel/traps.c
index d59ee62f772de844d13de60a38da6afcfd105f39..12164a30e8ff41268638efa3aefeb5d681b7f325 100644 (file)
--- a/arch/hexagon/kernel/traps.c
+++ b/arch/hexagon/kernel/traps.c
@@ -65,6 +65,10 @@ static const char *ex_name(int ex)
                return "Write protection fault";
        case HVM_GE_C_XMAL:
                return "Misaligned instruction";
+       case HVM_GE_C_WREG:
+               return "Multiple writes to same register in packet";
+       case HVM_GE_C_PCAL:
+               return "Program counter values that are not properly aligned";
        case HVM_GE_C_RMAL:
                return "Misaligned data load";
        case HVM_GE_C_WMAL:
@@ -324,6 +328,12 @@ void do_genex(struct pt_regs *regs)
        case HVM_GE_C_XMAL:
                misaligned_instruction(regs);
                break;
+       case HVM_GE_C_WREG:
+               illegal_instruction(regs);
+               break;
+       case HVM_GE_C_PCAL:
+               misaligned_instruction(regs);
+               break;
        case HVM_GE_C_RMAL:
                misaligned_data_load(regs);
                break;