drm/amdgpu/gfx8: Tidy up various PG helpers
authorTom St Denis <tom.stdenis@amd.com>
Fri, 3 Jun 2016 16:52:03 +0000 (12:52 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 7 Jul 2016 18:51:18 +0000 (14:51 -0400)
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

index cf114a28f7554e71c557f2556be7bfc78a43fa16..fb656b65b9a65c86616cb58a9357fba44983d380 100644 (file)
@@ -5257,20 +5257,15 @@ static void gfx_v8_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *ade
                                             enable ?
                                             AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE);
 
-       if (enable) {
-               /* Enable static MGPG */
-               temp = data = RREG32(mmRLC_PG_CNTL);
+       temp = data = RREG32(mmRLC_PG_CNTL);
+       /* Enable static MGPG */
+       if (enable)
                data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
-
-               if (temp != data)
-                       WREG32(mmRLC_PG_CNTL, data);
-       } else {
-               temp = data = RREG32(mmRLC_PG_CNTL);
+       else
                data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
 
-               if (temp != data)
-                       WREG32(mmRLC_PG_CNTL, data);
-       }
+       if (temp != data)
+               WREG32(mmRLC_PG_CNTL, data);
 }
 
 static void gfx_v8_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
@@ -5278,20 +5273,15 @@ static void gfx_v8_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *ad
 {
        uint32_t data, temp;
 
-       if (enable) {
-               /* Enable dynamic MGPG */
-               temp = data = RREG32(mmRLC_PG_CNTL);
+       temp = data = RREG32(mmRLC_PG_CNTL);
+       /* Enable dynamic MGPG */
+       if (enable)
                data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
-
-               if (temp != data)
-                       WREG32(mmRLC_PG_CNTL, data);
-       } else {
-               temp = data = RREG32(mmRLC_PG_CNTL);
+       else
                data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
 
-               if (temp != data)
-                       WREG32(mmRLC_PG_CNTL, data);
-       }
+       if (temp != data)
+               WREG32(mmRLC_PG_CNTL, data);
 }
 
 static void polaris11_enable_gfx_quick_mg_power_gating(struct amdgpu_device *adev,
@@ -5299,20 +5289,15 @@ static void polaris11_enable_gfx_quick_mg_power_gating(struct amdgpu_device *ade
 {
        uint32_t data, temp;
 
-       if (enable) {
-               /* Enable quick PG */
-               temp = data = RREG32(mmRLC_PG_CNTL);
+       temp = data = RREG32(mmRLC_PG_CNTL);
+       /* Enable quick PG */
+       if (enable)
                data |= 0x100000;
-
-               if (temp != data)
-                       WREG32(mmRLC_PG_CNTL, data);
-       } else {
-               temp = data = RREG32(mmRLC_PG_CNTL);
+       else
                data &= ~0x100000;
 
-               if (temp != data)
-                       WREG32(mmRLC_PG_CNTL, data);
-       }
+       if (temp != data)
+               WREG32(mmRLC_PG_CNTL, data);
 }
 
 static void cz_enable_gfx_cg_power_gating(struct amdgpu_device *adev,