powerpc/fsl: Added aliased MSIIR register address to MSI node in dts

The MSIIR register for each MSI bank is aliased to a different
address. The MSI node reg property was updated to contain this
address:

e.g. reg = <0x41600 0x200 0x44140 4>;

The first region contains the address and length of the MSI
register set and the second region contains the address of
the aliased MSIIR register at 0x44140.

Signed-off-by: Diana CRACIUN <Diana.Craciun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
index 5d586e1ccaf504d6a6834b38605f864fd168eb23..5693877ab377d6007cdb9e7f4ae7705faec581d7 100644 (file)
--- a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
@@ -6,8 +6,10 @@ Required properties:
   etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" depending on
   the parent type.
 
-- reg : should contain the address and the length of the shared message
-  interrupt register set.
+- reg : It may contain one or two regions. The first region should contain
+  the address and the length of the shared message interrupt register set.
+  The second region should contain the address of aliased MSIIR register for
+  platforms that have such an alias.
 
 - msi-available-ranges: use <start count> style section to define which
   msi interrupt can be used in the 256 msi interrupts. This property is

diff --git a/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi
index b9bada6a87dc60a423e92f321e61f6f3e1d02227..08f42271f86a5aa92404b82cc77f4eb13fabc119 100644 (file)
--- a/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi
@@ -53,7 +53,7 @@ timer@41100 {
 
 msi0: msi@41600 {
        compatible = "fsl,mpic-msi";
-       reg = <0x41600 0x200>;
+       reg = <0x41600 0x200 0x44140 4>;
        msi-available-ranges = <0 0x100>;
        interrupts = <
                0xe0 0 0 0
@@ -68,7 +68,7 @@ msi0: msi@41600 {
 
 msi1: msi@41800 {
        compatible = "fsl,mpic-msi";
-       reg = <0x41800 0x200>;
+       reg = <0x41800 0x200 0x45140 4>;
        msi-available-ranges = <0 0x100>;
        interrupts = <
                0xe8 0 0 0
@@ -83,7 +83,7 @@ msi1: msi@41800 {
 
 msi2: msi@41a00 {
        compatible = "fsl,mpic-msi";
-       reg = <0x41a00 0x200>;
+       reg = <0x41a00 0x200 0x46140 4>;
        msi-available-ranges = <0 0x100>;
        interrupts = <
                0xf0 0 0 0