mtd: spi-nor: Fix quad enable for Spansion like flashes
authorMichael Walle <michael@walle.cc>
Thu, 16 Jan 2020 09:37:00 +0000 (10:37 +0100)
committerMiquel Raynal <miquel.raynal@bootlin.com>
Fri, 17 Jan 2020 21:45:05 +0000 (22:45 +0100)
The commit 7b678c69c0ca ("mtd: spi-nor: Merge spansion Quad Enable
methods") forgot to actually set the QE bit in some cases. Thus this
breaks quad mode accesses to flashes which support readback of the
status register-2. Fix it.

Fixes: 7b678c69c0ca ("mtd: spi-nor: Merge spansion Quad Enable methods")
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
drivers/mtd/spi-nor/spi-nor.c

index 97f68d70cd23756e7a37211522896dd44101aae2..b0cd443dd758d1a098b8885ef034c71e41b4dacd 100644 (file)
@@ -2124,6 +2124,8 @@ static int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor)
        if (nor->bouncebuf[0] & SR2_QUAD_EN_BIT1)
                return 0;
 
+       nor->bouncebuf[0] |= SR2_QUAD_EN_BIT1;
+
        return spi_nor_write_16bit_cr_and_check(nor, nor->bouncebuf[0]);
 }