+++ /dev/null
-CONFIG_AG71XX=y
-CONFIG_AG71XX_AR8216_SUPPORT=y
-# CONFIG_AG71XX_DEBUG is not set
-# CONFIG_AG71XX_DEBUG_FS is not set
-CONFIG_AR8216_PHY=y
-# CONFIG_ARCH_DMA_ADDR_T_64BIT is not set
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
-CONFIG_ARCH_POPULATES_NODE_MAP=y
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ATH79=y
-CONFIG_ATH79_DEV_AP9X_PCI=y
-CONFIG_ATH79_DEV_DSA=y
-CONFIG_ATH79_DEV_ETH=y
-CONFIG_ATH79_DEV_GPIO_BUTTONS=y
-CONFIG_ATH79_DEV_LEDS_GPIO=y
-CONFIG_ATH79_DEV_M25P80=y
-CONFIG_ATH79_DEV_SPI=y
-CONFIG_ATH79_DEV_USB=y
-CONFIG_ATH79_DEV_WMAC=y
-CONFIG_ATH79_MACH_ALFA_AP96=y
-CONFIG_ATH79_MACH_ALFA_NX=y
-CONFIG_ATH79_MACH_ALL0258N=y
-CONFIG_ATH79_MACH_AP113=y
-CONFIG_ATH79_MACH_AP121=y
-CONFIG_ATH79_MACH_AP81=y
-CONFIG_ATH79_MACH_AP83=y
-CONFIG_ATH79_MACH_AP96=y
-CONFIG_ATH79_MACH_AW_NR580=y
-CONFIG_ATH79_MACH_DB120=y
-CONFIG_ATH79_MACH_DIR_600_A1=y
-CONFIG_ATH79_MACH_DIR_615_C1=y
-CONFIG_ATH79_MACH_DIR_825_B1=y
-CONFIG_ATH79_MACH_EAP7660D=y
-CONFIG_ATH79_MACH_HORNET_UB=y
-CONFIG_ATH79_MACH_JA76PF=y
-CONFIG_ATH79_MACH_JWAP003=y
-CONFIG_ATH79_MACH_MZK_W04NU=y
-CONFIG_ATH79_MACH_MZK_W300NH=y
-CONFIG_ATH79_MACH_NBG460N=y
-CONFIG_ATH79_MACH_OM2P=y
-CONFIG_ATH79_MACH_PB42=y
-CONFIG_ATH79_MACH_PB44=y
-CONFIG_ATH79_MACH_PB92=y
-CONFIG_ATH79_MACH_RB4XX=y
-CONFIG_ATH79_MACH_RB750=y
-CONFIG_ATH79_MACH_RW2458N=y
-CONFIG_ATH79_MACH_TEW_632BRP=y
-CONFIG_ATH79_MACH_TEW_673GRU=y
-CONFIG_ATH79_MACH_TL_MR11U=y
-CONFIG_ATH79_MACH_TL_MR3020=y
-CONFIG_ATH79_MACH_TL_MR3X20=y
-CONFIG_ATH79_MACH_TL_WA901ND=y
-CONFIG_ATH79_MACH_TL_WA901ND_V2=y
-CONFIG_ATH79_MACH_TL_WR1043ND=y
-CONFIG_ATH79_MACH_TL_WR2543N=y
-CONFIG_ATH79_MACH_TL_WR703N=y
-CONFIG_ATH79_MACH_TL_WR741ND=y
-CONFIG_ATH79_MACH_TL_WR741ND_V4=y
-CONFIG_ATH79_MACH_TL_WR841N_V1=y
-CONFIG_ATH79_MACH_TL_WR941ND=y
-CONFIG_ATH79_MACH_UBNT=y
-CONFIG_ATH79_MACH_UBNT_XM=y
-CONFIG_ATH79_MACH_WHR_HP_G300N=y
-CONFIG_ATH79_MACH_WNDR3700=y
-CONFIG_ATH79_MACH_WNR2000=y
-CONFIG_ATH79_MACH_WP543=y
-CONFIG_ATH79_MACH_WPE72=y
-CONFIG_ATH79_MACH_WRT160NL=y
-CONFIG_ATH79_MACH_WRT400N=y
-CONFIG_ATH79_MACH_WZR_HP_AG300H=y
-CONFIG_ATH79_MACH_WZR_HP_G300NH=y
-CONFIG_ATH79_MACH_WZR_HP_G300NH2=y
-CONFIG_ATH79_MACH_WZR_HP_G450H=y
-CONFIG_ATH79_MACH_ZCN_1523H=y
-CONFIG_ATH79_NVRAM=y
-CONFIG_ATH79_PCI_ATH9K_FIXUP=y
-# CONFIG_ATH79_WDT is not set
-CONFIG_BCMA_POSSIBLE=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_CEVT_R4K=y
-CONFIG_CEVT_R4K_LIB=y
-CONFIG_CMDLINE="rootfstype=squashfs,yaffs,jffs2 noinitrd"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_CPU_BIG_ENDIAN=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_MIPS32=y
-CONFIG_CPU_MIPS32_R2=y
-CONFIG_CPU_MIPSR2=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CSRC_R4K=y
-CONFIG_CSRC_R4K_LIB=y
-CONFIG_DECOMPRESS_LZMA=y
-CONFIG_DMA_NONCOHERENT=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_NXP_74HC153=y
-CONFIG_GPIO_PCF857X=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IRQ_WORK=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HW_HAS_PCI=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-# CONFIG_I2C_PXA_PCI is not set
-CONFIG_IMAGE_CMDLINE_HACK=y
-CONFIG_INITRAMFS_ROOT_GID=0
-CONFIG_INITRAMFS_ROOT_UID=0
-CONFIG_INITRAMFS_SOURCE="../../root"
-CONFIG_IP17XX_PHY=y
-CONFIG_IRQ_CPU=y
-CONFIG_IRQ_FORCED_THREADING=y
-# CONFIG_LANTIQ is not set
-# CONFIG_LEDS_GPIO is not set
-# CONFIG_LEDS_RB750 is not set
-# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
-# CONFIG_LEDS_TRIGGER_NETDEV is not set
-# CONFIG_LEDS_TRIGGER_TIMER is not set
-# CONFIG_LEDS_WNDR3700_USB is not set
-# CONFIG_M25PXX_USE_FAST_READ is not set
-CONFIG_MARVELL_PHY=y
-CONFIG_MDIO_BOARDINFO=y
-CONFIG_MICREL_PHY=y
-# CONFIG_MINIX_FS_NATIVE_ENDIAN is not set
-CONFIG_MIPS=y
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-CONFIG_MIPS_MACHINE=y
-CONFIG_MIPS_MT_DISABLED=y
-# CONFIG_MLX4_CORE is not set
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_MYLOADER_PARTS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-2
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_TPLINK_PARTS=y
-CONFIG_MTD_WRT160NL_PARTS=y
-CONFIG_MYLOADER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MV88E6060=y
-CONFIG_NET_DSA_MV88E6063=y
-CONFIG_NET_DSA_TAG_TRAILER=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PCI=y
-CONFIG_PCI_AR724X=y
-CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYLIB=y
-# CONFIG_PREEMPT_RCU is not set
-# CONFIG_QUOTACTL is not set
-CONFIG_RTL8306_PHY=y
-CONFIG_RTL8366RB_PHY=y
-CONFIG_RTL8366S_PHY=y
-CONFIG_RTL8366_SMI=y
-CONFIG_RTL8367_PHY=y
-# CONFIG_SCSI_DMA is not set
-CONFIG_SERIAL_8250_NR_UARTS=1
-CONFIG_SERIAL_8250_RUNTIME_UARTS=1
-CONFIG_SERIAL_AR933X=y
-CONFIG_SERIAL_AR933X_CONSOLE=y
-CONFIG_SERIAL_AR933X_NR_UARTS=2
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-CONFIG_SOC_AR71XX=y
-CONFIG_SOC_AR724X=y
-CONFIG_SOC_AR913X=y
-CONFIG_SOC_AR933X=y
-CONFIG_SOC_AR934X=y
-CONFIG_SPI=y
-CONFIG_SPI_AP83=y
-CONFIG_SPI_ATH79=y
-CONFIG_SPI_BITBANG=y
-# CONFIG_SPI_GPIO is not set
-CONFIG_SPI_MASTER=y
-# CONFIG_SPI_RB4XX is not set
-# CONFIG_SPI_RB4XX_CPLD is not set
-# CONFIG_SPI_VSC7385 is not set
-CONFIG_SWCONFIG=y
-CONFIG_SWCONFIG_LEDS=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
-CONFIG_USB_ARCH_HAS_XHCI=y
-CONFIG_USB_SUPPORT=y
-CONFIG_XZ_DEC=y
-CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-From 781c5ae32a2e8aede2e1756dfbea1abb3cf09ffc Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Sun, 5 Jun 2011 23:38:44 +0200
-Subject: [PATCH 01/27] MIPS: ath79: Change number of available IRQs
-
-The status register of the miscellaneous interrupt controller is 32 bits
-wide, but the actual value of NR_IRQS covers only 8 of them. Change
-NR_IRQS in order to make all of those interrupt lines usable.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Cc: linux-mips@linux-mips.org
-Patchwork: https://patchwork.linux-mips.org/patch/2441/
-Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
----
- arch/mips/include/asm/mach-ath79/irq.h | 4 ++--
- 1 files changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/mips/include/asm/mach-ath79/irq.h
-+++ b/arch/mips/include/asm/mach-ath79/irq.h
-@@ -10,10 +10,10 @@
- #define __ASM_MACH_ATH79_IRQ_H
-
- #define MIPS_CPU_IRQ_BASE 0
--#define NR_IRQS 16
-+#define NR_IRQS 40
-
- #define ATH79_MISC_IRQ_BASE 8
--#define ATH79_MISC_IRQ_COUNT 8
-+#define ATH79_MISC_IRQ_COUNT 32
-
- #define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2)
- #define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3)
+++ /dev/null
-From 9951cfc88b5d818391bebc7a56b678942b89721e Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Sun, 5 Jun 2011 23:38:45 +0200
-Subject: [PATCH 02/27] MIPS: ath79: Handle more MISC IRQs
-
-The AR724X SoCs have more IRQ sources hooked into the MISC IRQ controller.
-The patch adds support for them.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Cc: linux-mips@linux-mips.org
-Patchwork: https://patchwork.linux-mips.org/patch/2440/
-Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
----
- arch/mips/ath79/irq.c | 12 ++++++++++++
- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 4 ++++
- arch/mips/include/asm/mach-ath79/irq.h | 4 ++++
- 3 files changed, 20 insertions(+), 0 deletions(-)
-
---- a/arch/mips/ath79/irq.c
-+++ b/arch/mips/ath79/irq.c
-@@ -46,6 +46,15 @@ static void ath79_misc_irq_handler(unsig
- else if (pending & MISC_INT_TIMER)
- generic_handle_irq(ATH79_MISC_IRQ_TIMER);
-
-+ else if (pending & MISC_INT_TIMER2)
-+ generic_handle_irq(ATH79_MISC_IRQ_TIMER2);
-+
-+ else if (pending & MISC_INT_TIMER3)
-+ generic_handle_irq(ATH79_MISC_IRQ_TIMER3);
-+
-+ else if (pending & MISC_INT_TIMER4)
-+ generic_handle_irq(ATH79_MISC_IRQ_TIMER4);
-+
- else if (pending & MISC_INT_OHCI)
- generic_handle_irq(ATH79_MISC_IRQ_OHCI);
-
-@@ -58,6 +67,9 @@ static void ath79_misc_irq_handler(unsig
- else if (pending & MISC_INT_WDOG)
- generic_handle_irq(ATH79_MISC_IRQ_WDOG);
-
-+ else if (pending & MISC_INT_ETHSW)
-+ generic_handle_irq(ATH79_MISC_IRQ_ETHSW);
-+
- else
- spurious_interrupt();
- }
---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -130,6 +130,10 @@
-
- #define AR724X_RESET_REG_RESET_MODULE 0x1c
-
-+#define MISC_INT_ETHSW BIT(12)
-+#define MISC_INT_TIMER4 BIT(10)
-+#define MISC_INT_TIMER3 BIT(9)
-+#define MISC_INT_TIMER2 BIT(8)
- #define MISC_INT_DMA BIT(7)
- #define MISC_INT_OHCI BIT(6)
- #define MISC_INT_PERFC BIT(5)
---- a/arch/mips/include/asm/mach-ath79/irq.h
-+++ b/arch/mips/include/asm/mach-ath79/irq.h
-@@ -30,6 +30,10 @@
- #define ATH79_MISC_IRQ_PERFC (ATH79_MISC_IRQ_BASE + 5)
- #define ATH79_MISC_IRQ_OHCI (ATH79_MISC_IRQ_BASE + 6)
- #define ATH79_MISC_IRQ_DMA (ATH79_MISC_IRQ_BASE + 7)
-+#define ATH79_MISC_IRQ_TIMER2 (ATH79_MISC_IRQ_BASE + 8)
-+#define ATH79_MISC_IRQ_TIMER3 (ATH79_MISC_IRQ_BASE + 9)
-+#define ATH79_MISC_IRQ_TIMER4 (ATH79_MISC_IRQ_BASE + 10)
-+#define ATH79_MISC_IRQ_ETHSW (ATH79_MISC_IRQ_BASE + 12)
-
- #include_next <irq.h>
-
+++ /dev/null
-From cb888b2552199ace429731b772d5257c598d53df Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Sun, 5 Jun 2011 23:38:46 +0200
-Subject: [PATCH 03/27] MIPS: ath79: add common USB Host Controller device
-
-Add common platform_device and helper code to make the registration of
-the built-in USB controllers easier on the board which are using them.
-Also register the USB controller on the AP81 and PB44 boards.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
-Cc: linux-mips@linux-mips.org
-Patchwork: https://patchwork.linux-mips.org/patch/2442/
-Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
----
- arch/mips/ath79/Kconfig | 5 +
- arch/mips/ath79/Makefile | 1 +
- arch/mips/ath79/dev-usb.c | 178 ++++++++++++++++++++++++
- arch/mips/ath79/dev-usb.h | 17 +++
- arch/mips/ath79/mach-ap81.c | 2 +
- arch/mips/ath79/mach-pb44.c | 2 +
- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 32 ++++-
- 7 files changed, 236 insertions(+), 1 deletions(-)
- create mode 100644 arch/mips/ath79/dev-usb.c
- create mode 100644 arch/mips/ath79/dev-usb.h
-
---- a/arch/mips/ath79/Kconfig
-+++ b/arch/mips/ath79/Kconfig
-@@ -9,6 +9,7 @@ config ATH79_MACH_AP81
- select ATH79_DEV_GPIO_BUTTONS
- select ATH79_DEV_LEDS_GPIO
- select ATH79_DEV_SPI
-+ select ATH79_DEV_USB
- help
- Say 'Y' here if you want your kernel to support the
- Atheros AP81 reference board.
-@@ -19,6 +20,7 @@ config ATH79_MACH_PB44
- select ATH79_DEV_GPIO_BUTTONS
- select ATH79_DEV_LEDS_GPIO
- select ATH79_DEV_SPI
-+ select ATH79_DEV_USB
- help
- Say 'Y' here if you want your kernel to support the
- Atheros PB44 reference board.
-@@ -52,4 +54,7 @@ config ATH79_DEV_LEDS_GPIO
- config ATH79_DEV_SPI
- def_bool n
-
-+config ATH79_DEV_USB
-+ def_bool n
-+
- endif
---- a/arch/mips/ath79/Makefile
-+++ b/arch/mips/ath79/Makefile
-@@ -20,6 +20,7 @@ obj-$(CONFIG_ATH79_DEV_AR913X_WMAC) += d
- obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o
- obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o
- obj-$(CONFIG_ATH79_DEV_SPI) += dev-spi.o
-+obj-$(CONFIG_ATH79_DEV_USB) += dev-usb.o
-
- #
- # Machines
---- /dev/null
-+++ b/arch/mips/ath79/dev-usb.c
-@@ -0,0 +1,178 @@
-+/*
-+ * Atheros AR7XXX/AR9XXX USB Host Controller device
-+ *
-+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
-+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-+ *
-+ * Parts of this file are based on Atheros' 2.6.15 BSP
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/delay.h>
-+#include <linux/irq.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/platform_device.h>
-+
-+#include <asm/mach-ath79/ath79.h>
-+#include <asm/mach-ath79/ar71xx_regs.h>
-+#include "common.h"
-+#include "dev-usb.h"
-+
-+static struct resource ath79_ohci_resources[] = {
-+ [0] = {
-+ /* .start and .end fields are filled dynamically */
-+ .flags = IORESOURCE_MEM,
-+ },
-+ [1] = {
-+ .start = ATH79_MISC_IRQ_OHCI,
-+ .end = ATH79_MISC_IRQ_OHCI,
-+ .flags = IORESOURCE_IRQ,
-+ },
-+};
-+
-+static u64 ath79_ohci_dmamask = DMA_BIT_MASK(32);
-+static struct platform_device ath79_ohci_device = {
-+ .name = "ath79-ohci",
-+ .id = -1,
-+ .resource = ath79_ohci_resources,
-+ .num_resources = ARRAY_SIZE(ath79_ohci_resources),
-+ .dev = {
-+ .dma_mask = &ath79_ohci_dmamask,
-+ .coherent_dma_mask = DMA_BIT_MASK(32),
-+ },
-+};
-+
-+static struct resource ath79_ehci_resources[] = {
-+ [0] = {
-+ /* .start and .end fields are filled dynamically */
-+ .flags = IORESOURCE_MEM,
-+ },
-+ [1] = {
-+ .start = ATH79_CPU_IRQ_USB,
-+ .end = ATH79_CPU_IRQ_USB,
-+ .flags = IORESOURCE_IRQ,
-+ },
-+};
-+
-+static u64 ath79_ehci_dmamask = DMA_BIT_MASK(32);
-+static struct platform_device ath79_ehci_device = {
-+ .name = "ath79-ehci",
-+ .id = -1,
-+ .resource = ath79_ehci_resources,
-+ .num_resources = ARRAY_SIZE(ath79_ehci_resources),
-+ .dev = {
-+ .dma_mask = &ath79_ehci_dmamask,
-+ .coherent_dma_mask = DMA_BIT_MASK(32),
-+ },
-+};
-+
-+#define AR71XX_USB_RESET_MASK (AR71XX_RESET_USB_HOST | \
-+ AR71XX_RESET_USB_PHY | \
-+ AR71XX_RESET_USB_OHCI_DLL)
-+
-+static void __init ath79_usb_setup(void)
-+{
-+ void __iomem *usb_ctrl_base;
-+
-+ ath79_device_reset_set(AR71XX_USB_RESET_MASK);
-+ mdelay(1000);
-+ ath79_device_reset_clear(AR71XX_USB_RESET_MASK);
-+
-+ usb_ctrl_base = ioremap(AR71XX_USB_CTRL_BASE, AR71XX_USB_CTRL_SIZE);
-+
-+ /* Turning on the Buff and Desc swap bits */
-+ __raw_writel(0xf0000, usb_ctrl_base + AR71XX_USB_CTRL_REG_CONFIG);
-+
-+ /* WAR for HW bug. Here it adjusts the duration between two SOFS */
-+ __raw_writel(0x20c00, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ);
-+
-+ iounmap(usb_ctrl_base);
-+
-+ mdelay(900);
-+
-+ ath79_ohci_resources[0].start = AR71XX_OHCI_BASE;
-+ ath79_ohci_resources[0].end = AR71XX_OHCI_BASE + AR71XX_OHCI_SIZE - 1;
-+ platform_device_register(&ath79_ohci_device);
-+
-+ ath79_ehci_resources[0].start = AR71XX_EHCI_BASE;
-+ ath79_ehci_resources[0].end = AR71XX_EHCI_BASE + AR71XX_EHCI_SIZE - 1;
-+ ath79_ehci_device.name = "ar71xx-ehci";
-+ platform_device_register(&ath79_ehci_device);
-+}
-+
-+static void __init ar7240_usb_setup(void)
-+{
-+ void __iomem *usb_ctrl_base;
-+
-+ ath79_device_reset_clear(AR7240_RESET_OHCI_DLL);
-+ ath79_device_reset_set(AR7240_RESET_USB_HOST);
-+
-+ mdelay(1000);
-+
-+ ath79_device_reset_set(AR7240_RESET_OHCI_DLL);
-+ ath79_device_reset_clear(AR7240_RESET_USB_HOST);
-+
-+ usb_ctrl_base = ioremap(AR7240_USB_CTRL_BASE, AR7240_USB_CTRL_SIZE);
-+
-+ /* WAR for HW bug. Here it adjusts the duration between two SOFS */
-+ __raw_writel(0x3, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ);
-+
-+ iounmap(usb_ctrl_base);
-+
-+ ath79_ohci_resources[0].start = AR7240_OHCI_BASE;
-+ ath79_ohci_resources[0].end = AR7240_OHCI_BASE + AR7240_OHCI_SIZE - 1;
-+ platform_device_register(&ath79_ohci_device);
-+}
-+
-+static void __init ar724x_usb_setup(void)
-+{
-+ ath79_device_reset_set(AR724X_RESET_USBSUS_OVERRIDE);
-+ mdelay(10);
-+
-+ ath79_device_reset_clear(AR724X_RESET_USB_HOST);
-+ mdelay(10);
-+
-+ ath79_device_reset_clear(AR724X_RESET_USB_PHY);
-+ mdelay(10);
-+
-+ ath79_ehci_resources[0].start = AR724X_EHCI_BASE;
-+ ath79_ehci_resources[0].end = AR724X_EHCI_BASE + AR724X_EHCI_SIZE - 1;
-+ ath79_ehci_device.name = "ar724x-ehci";
-+ platform_device_register(&ath79_ehci_device);
-+}
-+
-+static void __init ar913x_usb_setup(void)
-+{
-+ ath79_device_reset_set(AR913X_RESET_USBSUS_OVERRIDE);
-+ mdelay(10);
-+
-+ ath79_device_reset_clear(AR913X_RESET_USB_HOST);
-+ mdelay(10);
-+
-+ ath79_device_reset_clear(AR913X_RESET_USB_PHY);
-+ mdelay(10);
-+
-+ ath79_ehci_resources[0].start = AR913X_EHCI_BASE;
-+ ath79_ehci_resources[0].end = AR913X_EHCI_BASE + AR913X_EHCI_SIZE - 1;
-+ ath79_ehci_device.name = "ar913x-ehci";
-+ platform_device_register(&ath79_ehci_device);
-+}
-+
-+void __init ath79_register_usb(void)
-+{
-+ if (soc_is_ar71xx())
-+ ath79_usb_setup();
-+ else if (soc_is_ar7240())
-+ ar7240_usb_setup();
-+ else if (soc_is_ar7241() || soc_is_ar7242())
-+ ar724x_usb_setup();
-+ else if (soc_is_ar913x())
-+ ar913x_usb_setup();
-+ else
-+ BUG();
-+}
---- /dev/null
-+++ b/arch/mips/ath79/dev-usb.h
-@@ -0,0 +1,17 @@
-+/*
-+ * Atheros AR71XX/AR724X/AR913X USB Host Controller support
-+ *
-+ * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
-+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+
-+#ifndef _ATH79_DEV_USB_H
-+#define _ATH79_DEV_USB_H
-+
-+void ath79_register_usb(void);
-+
-+#endif /* _ATH79_DEV_USB_H */
---- a/arch/mips/ath79/mach-ap81.c
-+++ b/arch/mips/ath79/mach-ap81.c
-@@ -14,6 +14,7 @@
- #include "dev-gpio-buttons.h"
- #include "dev-leds-gpio.h"
- #include "dev-spi.h"
-+#include "dev-usb.h"
-
- #define AP81_GPIO_LED_STATUS 1
- #define AP81_GPIO_LED_AOSS 3
-@@ -92,6 +93,7 @@ static void __init ap81_setup(void)
- ath79_register_spi(&ap81_spi_data, ap81_spi_info,
- ARRAY_SIZE(ap81_spi_info));
- ath79_register_ar913x_wmac(cal_data);
-+ ath79_register_usb();
- }
-
- MIPS_MACHINE(ATH79_MACH_AP81, "AP81", "Atheros AP81 reference board",
---- a/arch/mips/ath79/mach-pb44.c
-+++ b/arch/mips/ath79/mach-pb44.c
-@@ -18,6 +18,7 @@
- #include "dev-gpio-buttons.h"
- #include "dev-leds-gpio.h"
- #include "dev-spi.h"
-+#include "dev-usb.h"
-
- #define PB44_GPIO_I2C_SCL 0
- #define PB44_GPIO_I2C_SDA 1
-@@ -112,6 +113,7 @@ static void __init pb44_init(void)
- pb44_gpio_keys);
- ath79_register_spi(&pb44_spi_data, pb44_spi_info,
- ARRAY_SIZE(pb44_spi_info));
-+ ath79_register_usb();
- }
-
- MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board",
---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -20,6 +20,10 @@
- #include <linux/bitops.h>
-
- #define AR71XX_APB_BASE 0x18000000
-+#define AR71XX_EHCI_BASE 0x1b000000
-+#define AR71XX_EHCI_SIZE 0x1000
-+#define AR71XX_OHCI_BASE 0x1c000000
-+#define AR71XX_OHCI_SIZE 0x1000
- #define AR71XX_SPI_BASE 0x1f000000
- #define AR71XX_SPI_SIZE 0x01000000
-
-@@ -27,6 +31,8 @@
- #define AR71XX_DDR_CTRL_SIZE 0x100
- #define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
- #define AR71XX_UART_SIZE 0x100
-+#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
-+#define AR71XX_USB_CTRL_SIZE 0x100
- #define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000)
- #define AR71XX_GPIO_SIZE 0x100
- #define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
-@@ -34,6 +40,16 @@
- #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
- #define AR71XX_RESET_SIZE 0x100
-
-+#define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
-+#define AR7240_USB_CTRL_SIZE 0x100
-+#define AR7240_OHCI_BASE 0x1b000000
-+#define AR7240_OHCI_SIZE 0x1000
-+
-+#define AR724X_EHCI_BASE 0x1b000000
-+#define AR724X_EHCI_SIZE 0x1000
-+
-+#define AR913X_EHCI_BASE 0x1b000000
-+#define AR913X_EHCI_SIZE 0x1000
- #define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
- #define AR913X_WMAC_SIZE 0x30000
-
-@@ -105,6 +121,12 @@
- #define AR913X_AHB_DIV_MASK 0x1
-
- /*
-+ * USB_CONFIG block
-+ */
-+#define AR71XX_USB_CTRL_REG_FLADJ 0x00
-+#define AR71XX_USB_CTRL_REG_CONFIG 0x04
-+
-+/*
- * RESET block
- */
- #define AR71XX_RESET_REG_TIMER 0x00
-@@ -162,14 +184,22 @@
- #define AR71XX_RESET_PCI_BUS BIT(1)
- #define AR71XX_RESET_PCI_CORE BIT(0)
-
-+#define AR7240_RESET_USB_HOST BIT(5)
-+#define AR7240_RESET_OHCI_DLL BIT(3)
-+
- #define AR724X_RESET_GE1_MDIO BIT(23)
- #define AR724X_RESET_GE0_MDIO BIT(22)
- #define AR724X_RESET_PCIE_PHY_SERIAL BIT(10)
- #define AR724X_RESET_PCIE_PHY BIT(7)
- #define AR724X_RESET_PCIE BIT(6)
--#define AR724X_RESET_OHCI_DLL BIT(3)
-+#define AR724X_RESET_USB_HOST BIT(5)
-+#define AR724X_RESET_USB_PHY BIT(4)
-+#define AR724X_RESET_USBSUS_OVERRIDE BIT(3)
-
- #define AR913X_RESET_AMBA2WMAC BIT(22)
-+#define AR913X_RESET_USBSUS_OVERRIDE BIT(10)
-+#define AR913X_RESET_USB_HOST BIT(5)
-+#define AR913X_RESET_USB_PHY BIT(4)
-
- #define REV_ID_MAJOR_MASK 0xfff0
- #define REV_ID_MAJOR_AR71XX 0x00a0
+++ /dev/null
-From 44f70a7cd3c0a8481877174a0f12b013c5667933 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Mon, 20 Jun 2011 21:26:01 +0200
-Subject: [PATCH 04/27] MIPS: ath79: Remove superfluous parentheses
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Cc: linux-mips@linux-mips.org
-Cc: Kathy Giori <kgiori@qca.qualcomm.com>
-Cc: "Luis R. Rodriguez" <rodrigue@qca.qualcomm.com>
-Patchwork: https://patchwork.linux-mips.org/patch/2519/
-Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
----
- arch/mips/ath79/setup.c | 6 +++---
- 1 files changed, 3 insertions(+), 3 deletions(-)
-
---- a/arch/mips/ath79/setup.c
-+++ b/arch/mips/ath79/setup.c
-@@ -101,19 +101,19 @@ static void __init ath79_detect_sys_type
- case REV_ID_MAJOR_AR7240:
- ath79_soc = ATH79_SOC_AR7240;
- chip = "7240";
-- rev = (id & AR724X_REV_ID_REVISION_MASK);
-+ rev = id & AR724X_REV_ID_REVISION_MASK;
- break;
-
- case REV_ID_MAJOR_AR7241:
- ath79_soc = ATH79_SOC_AR7241;
- chip = "7241";
-- rev = (id & AR724X_REV_ID_REVISION_MASK);
-+ rev = id & AR724X_REV_ID_REVISION_MASK;
- break;
-
- case REV_ID_MAJOR_AR7242:
- ath79_soc = ATH79_SOC_AR7242;
- chip = "7242";
-- rev = (id & AR724X_REV_ID_REVISION_MASK);
-+ rev = id & AR724X_REV_ID_REVISION_MASK;
- break;
-
- case REV_ID_MAJOR_AR913X:
+++ /dev/null
-From a6b04a056cd63e9241b94bc5dcc8847fa4cb1d34 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Thu, 23 Jun 2011 18:13:14 +0200
-Subject: [PATCH 05/27] MIPS: ath79: add revision id for the AR933X SoCs
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Cc: linux-mips@linux-mips.org
-Cc: Kathy Giori <kgiori@qca.qualcomm.com>
-Cc: "Luis R. Rodriguez" <rodrigue@qca.qualcomm.com>
-Patchwork: https://patchwork.linux-mips.org/patch/2538/
-Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
----
- arch/mips/ath79/setup.c | 12 ++++++++++++
- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 4 ++++
- arch/mips/include/asm/mach-ath79/ath79.h | 4 +++-
- 3 files changed, 19 insertions(+), 1 deletions(-)
-
---- a/arch/mips/ath79/setup.c
-+++ b/arch/mips/ath79/setup.c
-@@ -116,6 +116,18 @@ static void __init ath79_detect_sys_type
- rev = id & AR724X_REV_ID_REVISION_MASK;
- break;
-
-+ case REV_ID_MAJOR_AR9330:
-+ ath79_soc = ATH79_SOC_AR9330;
-+ chip = "9330";
-+ rev = id & AR933X_REV_ID_REVISION_MASK;
-+ break;
-+
-+ case REV_ID_MAJOR_AR9331:
-+ ath79_soc = ATH79_SOC_AR9331;
-+ chip = "9331";
-+ rev = id & AR933X_REV_ID_REVISION_MASK;
-+ break;
-+
- case REV_ID_MAJOR_AR913X:
- minor = id & AR913X_REV_ID_MINOR_MASK;
- rev = id >> AR913X_REV_ID_REVISION_SHIFT;
---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -207,6 +207,8 @@
- #define REV_ID_MAJOR_AR7240 0x00c0
- #define REV_ID_MAJOR_AR7241 0x0100
- #define REV_ID_MAJOR_AR7242 0x1100
-+#define REV_ID_MAJOR_AR9330 0x0110
-+#define REV_ID_MAJOR_AR9331 0x1110
-
- #define AR71XX_REV_ID_MINOR_MASK 0x3
- #define AR71XX_REV_ID_MINOR_AR7130 0x0
-@@ -221,6 +223,8 @@
- #define AR913X_REV_ID_REVISION_MASK 0x3
- #define AR913X_REV_ID_REVISION_SHIFT 2
-
-+#define AR933X_REV_ID_REVISION_MASK 0x3
-+
- #define AR724X_REV_ID_REVISION_MASK 0x3
-
- /*
---- a/arch/mips/include/asm/mach-ath79/ath79.h
-+++ b/arch/mips/include/asm/mach-ath79/ath79.h
-@@ -26,7 +26,9 @@ enum ath79_soc_type {
- ATH79_SOC_AR7241,
- ATH79_SOC_AR7242,
- ATH79_SOC_AR9130,
-- ATH79_SOC_AR9132
-+ ATH79_SOC_AR9132,
-+ ATH79_SOC_AR9330,
-+ ATH79_SOC_AR9331,
- };
-
- extern enum ath79_soc_type ath79_soc;
+++ /dev/null
-From 84ead7964e423c37a73da30a1a2c4c486f74242d Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Mon, 20 Jun 2011 21:26:03 +0200
-Subject: [PATCH 06/27] MIPS: ath79: Add early printk support for the AR933X SoCs
-
-The AR933X SoCs are using a different UART, thus require
-different code for early printk support.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Cc: linux-mips@linux-mips.org
-Cc: Kathy Giori <kgiori@qca.qualcomm.com>
-Cc: "Luis R. Rodriguez" <rodrigue@qca.qualcomm.com>
-Patchwork: https://patchwork.linux-mips.org/patch/2521/
-Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
----
- arch/mips/ath79/early_printk.c | 76 +++++++++++++++++++++---
- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 3 +
- arch/mips/include/asm/mach-ath79/ar933x_uart.h | 67 +++++++++++++++++++++
- 3 files changed, 137 insertions(+), 9 deletions(-)
- create mode 100644 arch/mips/include/asm/mach-ath79/ar933x_uart.h
-
---- a/arch/mips/ath79/early_printk.c
-+++ b/arch/mips/ath79/early_printk.c
-@@ -1,7 +1,7 @@
- /*
-- * Atheros AR71XX/AR724X/AR913X SoC early printk support
-+ * Atheros AR7XXX/AR9XXX SoC early printk support
- *
-- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
-+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
-@@ -10,27 +10,85 @@
- */
-
- #include <linux/io.h>
-+#include <linux/errno.h>
- #include <linux/serial_reg.h>
- #include <asm/addrspace.h>
-
-+#include <asm/mach-ath79/ath79.h>
- #include <asm/mach-ath79/ar71xx_regs.h>
-+#include <asm/mach-ath79/ar933x_uart.h>
-
--static inline void prom_wait_thre(void __iomem *base)
-+static void (*_prom_putchar) (unsigned char);
-+
-+static inline void prom_putchar_wait(void __iomem *reg, u32 mask, u32 val)
- {
-- u32 lsr;
-+ u32 t;
-
- do {
-- lsr = __raw_readl(base + UART_LSR * 4);
-- if (lsr & UART_LSR_THRE)
-+ t = __raw_readl(reg);
-+ if ((t & mask) == val)
- break;
- } while (1);
- }
-
--void prom_putchar(unsigned char ch)
-+static void prom_putchar_ar71xx(unsigned char ch)
- {
- void __iomem *base = (void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE));
-
-- prom_wait_thre(base);
-+ prom_putchar_wait(base + UART_LSR * 4, UART_LSR_THRE, UART_LSR_THRE);
- __raw_writel(ch, base + UART_TX * 4);
-- prom_wait_thre(base);
-+ prom_putchar_wait(base + UART_LSR * 4, UART_LSR_THRE, UART_LSR_THRE);
-+}
-+
-+static void prom_putchar_ar933x(unsigned char ch)
-+{
-+ void __iomem *base = (void __iomem *)(KSEG1ADDR(AR933X_UART_BASE));
-+
-+ prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR,
-+ AR933X_UART_DATA_TX_CSR);
-+ __raw_writel(AR933X_UART_DATA_TX_CSR | ch, base + AR933X_UART_DATA_REG);
-+ prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR,
-+ AR933X_UART_DATA_TX_CSR);
-+}
-+
-+static void prom_putchar_dummy(unsigned char ch)
-+{
-+ /* nothing to do */
-+}
-+
-+static void prom_putchar_init(void)
-+{
-+ void __iomem *base;
-+ u32 id;
-+
-+ base = (void __iomem *)(KSEG1ADDR(AR71XX_RESET_BASE));
-+ id = __raw_readl(base + AR71XX_RESET_REG_REV_ID);
-+ id &= REV_ID_MAJOR_MASK;
-+
-+ switch (id) {
-+ case REV_ID_MAJOR_AR71XX:
-+ case REV_ID_MAJOR_AR7240:
-+ case REV_ID_MAJOR_AR7241:
-+ case REV_ID_MAJOR_AR7242:
-+ case REV_ID_MAJOR_AR913X:
-+ _prom_putchar = prom_putchar_ar71xx;
-+ break;
-+
-+ case REV_ID_MAJOR_AR9330:
-+ case REV_ID_MAJOR_AR9331:
-+ _prom_putchar = prom_putchar_ar933x;
-+ break;
-+
-+ default:
-+ _prom_putchar = prom_putchar_dummy;
-+ break;
-+ }
-+}
-+
-+void prom_putchar(unsigned char ch)
-+{
-+ if (!_prom_putchar)
-+ prom_putchar_init();
-+
-+ _prom_putchar(ch);
- }
---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -53,6 +53,9 @@
- #define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
- #define AR913X_WMAC_SIZE 0x30000
-
-+#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
-+#define AR933X_UART_SIZE 0x14
-+
- /*
- * DDR_CTRL block
- */
---- /dev/null
-+++ b/arch/mips/include/asm/mach-ath79/ar933x_uart.h
-@@ -0,0 +1,67 @@
-+/*
-+ * Atheros AR933X UART defines
-+ *
-+ * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+
-+#ifndef __AR933X_UART_H
-+#define __AR933X_UART_H
-+
-+#define AR933X_UART_REGS_SIZE 20
-+#define AR933X_UART_FIFO_SIZE 16
-+
-+#define AR933X_UART_DATA_REG 0x00
-+#define AR933X_UART_CS_REG 0x04
-+#define AR933X_UART_CLOCK_REG 0x08
-+#define AR933X_UART_INT_REG 0x0c
-+#define AR933X_UART_INT_EN_REG 0x10
-+
-+#define AR933X_UART_DATA_TX_RX_MASK 0xff
-+#define AR933X_UART_DATA_RX_CSR BIT(8)
-+#define AR933X_UART_DATA_TX_CSR BIT(9)
-+
-+#define AR933X_UART_CS_PARITY_S 0
-+#define AR933X_UART_CS_PARITY_M 0x3
-+#define AR933X_UART_CS_PARITY_NONE 0
-+#define AR933X_UART_CS_PARITY_ODD 1
-+#define AR933X_UART_CS_PARITY_EVEN 2
-+#define AR933X_UART_CS_IF_MODE_S 2
-+#define AR933X_UART_CS_IF_MODE_M 0x3
-+#define AR933X_UART_CS_IF_MODE_NONE 0
-+#define AR933X_UART_CS_IF_MODE_DTE 1
-+#define AR933X_UART_CS_IF_MODE_DCE 2
-+#define AR933X_UART_CS_FLOW_CTRL_S 4
-+#define AR933X_UART_CS_FLOW_CTRL_M 0x3
-+#define AR933X_UART_CS_DMA_EN BIT(6)
-+#define AR933X_UART_CS_TX_READY_ORIDE BIT(7)
-+#define AR933X_UART_CS_RX_READY_ORIDE BIT(8)
-+#define AR933X_UART_CS_TX_READY BIT(9)
-+#define AR933X_UART_CS_RX_BREAK BIT(10)
-+#define AR933X_UART_CS_TX_BREAK BIT(11)
-+#define AR933X_UART_CS_HOST_INT BIT(12)
-+#define AR933X_UART_CS_HOST_INT_EN BIT(13)
-+#define AR933X_UART_CS_TX_BUSY BIT(14)
-+#define AR933X_UART_CS_RX_BUSY BIT(15)
-+
-+#define AR933X_UART_CLOCK_STEP_M 0xffff
-+#define AR933X_UART_CLOCK_SCALE_M 0xfff
-+#define AR933X_UART_CLOCK_SCALE_S 16
-+#define AR933X_UART_CLOCK_STEP_M 0xffff
-+
-+#define AR933X_UART_INT_RX_VALID BIT(0)
-+#define AR933X_UART_INT_TX_READY BIT(1)
-+#define AR933X_UART_INT_RX_FRAMING_ERR BIT(2)
-+#define AR933X_UART_INT_RX_OFLOW_ERR BIT(3)
-+#define AR933X_UART_INT_TX_OFLOW_ERR BIT(4)
-+#define AR933X_UART_INT_RX_PARITY_ERR BIT(5)
-+#define AR933X_UART_INT_RX_BREAK_ON BIT(6)
-+#define AR933X_UART_INT_RX_BREAK_OFF BIT(7)
-+#define AR933X_UART_INT_RX_FULL BIT(8)
-+#define AR933X_UART_INT_TX_EMPTY BIT(9)
-+#define AR933X_UART_INT_ALLINTS 0x3ff
-+
-+#endif /* __AR933X_UART_H */
+++ /dev/null
-From 29c8b2eef2011bf9392479487a51f6927892bfd6 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Mon, 20 Jun 2011 21:26:04 +0200
-Subject: [PATCH 07/27] MIPS: ath79: add AR933X specific clock init
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Cc: linux-mips@linux-mips.org
-Cc: Kathy Giori <kgiori@qca.qualcomm.com>
-Cc: "Luis R. Rodriguez" <rodrigue@qca.qualcomm.com>
-Patchwork: https://patchwork.linux-mips.org/patch/2522/
-Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
----
- arch/mips/ath79/clock.c | 55 ++++++++++++++++++++++++
- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 22 +++++++++
- arch/mips/include/asm/mach-ath79/ath79.h | 6 +++
- 3 files changed, 83 insertions(+), 0 deletions(-)
-
---- a/arch/mips/ath79/clock.c
-+++ b/arch/mips/ath79/clock.c
-@@ -110,6 +110,59 @@ static void __init ar913x_clocks_init(vo
- ath79_uart_clk.rate = ath79_ahb_clk.rate;
- }
-
-+static void __init ar933x_clocks_init(void)
-+{
-+ u32 clock_ctrl;
-+ u32 cpu_config;
-+ u32 freq;
-+ u32 t;
-+
-+ t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
-+ if (t & AR933X_BOOTSTRAP_REF_CLK_40)
-+ ath79_ref_clk.rate = (40 * 1000 * 1000);
-+ else
-+ ath79_ref_clk.rate = (25 * 1000 * 1000);
-+
-+ clock_ctrl = ath79_pll_rr(AR933X_PLL_CLOCK_CTRL_REG);
-+ if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
-+ ath79_cpu_clk.rate = ath79_ref_clk.rate;
-+ ath79_ahb_clk.rate = ath79_ref_clk.rate;
-+ ath79_ddr_clk.rate = ath79_ref_clk.rate;
-+ } else {
-+ cpu_config = ath79_pll_rr(AR933X_PLL_CPU_CONFIG_REG);
-+
-+ t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
-+ AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
-+ freq = ath79_ref_clk.rate / t;
-+
-+ t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
-+ AR933X_PLL_CPU_CONFIG_NINT_MASK;
-+ freq *= t;
-+
-+ t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
-+ AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
-+ if (t == 0)
-+ t = 1;
-+
-+ freq >>= t;
-+
-+ t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
-+ AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
-+ ath79_cpu_clk.rate = freq / t;
-+
-+ t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
-+ AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
-+ ath79_ddr_clk.rate = freq / t;
-+
-+ t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
-+ AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
-+ ath79_ahb_clk.rate = freq / t;
-+ }
-+
-+ ath79_wdt_clk.rate = ath79_ref_clk.rate;
-+ ath79_uart_clk.rate = ath79_ref_clk.rate;
-+}
-+
- void __init ath79_clocks_init(void)
- {
- if (soc_is_ar71xx())
-@@ -118,6 +171,8 @@ void __init ath79_clocks_init(void)
- ar724x_clocks_init();
- else if (soc_is_ar913x())
- ar913x_clocks_init();
-+ else if (soc_is_ar933x())
-+ ar933x_clocks_init();
- else
- BUG();
-
---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -123,6 +123,24 @@
- #define AR913X_AHB_DIV_SHIFT 19
- #define AR913X_AHB_DIV_MASK 0x1
-
-+#define AR933X_PLL_CPU_CONFIG_REG 0x00
-+#define AR933X_PLL_CLOCK_CTRL_REG 0x08
-+
-+#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10
-+#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f
-+#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16
-+#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
-+#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23
-+#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
-+
-+#define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2)
-+#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5
-+#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3
-+#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10
-+#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3
-+#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15
-+#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7
-+
- /*
- * USB_CONFIG block
- */
-@@ -155,6 +173,8 @@
-
- #define AR724X_RESET_REG_RESET_MODULE 0x1c
-
-+#define AR933X_RESET_REG_BOOTSTRAP 0xac
-+
- #define MISC_INT_ETHSW BIT(12)
- #define MISC_INT_TIMER4 BIT(10)
- #define MISC_INT_TIMER3 BIT(9)
-@@ -204,6 +224,8 @@
- #define AR913X_RESET_USB_HOST BIT(5)
- #define AR913X_RESET_USB_PHY BIT(4)
-
-+#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
-+
- #define REV_ID_MAJOR_MASK 0xfff0
- #define REV_ID_MAJOR_AR71XX 0x00a0
- #define REV_ID_MAJOR_AR913X 0x00b0
---- a/arch/mips/include/asm/mach-ath79/ath79.h
-+++ b/arch/mips/include/asm/mach-ath79/ath79.h
-@@ -68,6 +68,12 @@ static inline int soc_is_ar913x(void)
- ath79_soc == ATH79_SOC_AR9132);
- }
-
-+static inline int soc_is_ar933x(void)
-+{
-+ return (ath79_soc == ATH79_SOC_AR9330 ||
-+ ath79_soc == ATH79_SOC_AR9331);
-+}
-+
- extern void __iomem *ath79_ddr_base;
- extern void __iomem *ath79_pll_base;
- extern void __iomem *ath79_reset_base;
+++ /dev/null
-From 00624e5d91c0e76f38730633eff51fc7630dd27b Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Mon, 20 Jun 2011 21:26:05 +0200
-Subject: [PATCH 08/27] MIPS: ath79: Add AR933X specific glue for ath79_device_reset_{set,clear}
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Cc: linux-mips@linux-mips.org
-Cc: Kathy Giori <kgiori@qca.qualcomm.com>
-Cc: "Luis R. Rodriguez" <rodrigue@qca.qualcomm.com>
-Patchwork: https://patchwork.linux-mips.org/patch/2523/
-Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
----
- arch/mips/ath79/common.c | 4 ++++
- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 1 +
- 2 files changed, 5 insertions(+), 0 deletions(-)
-
---- a/arch/mips/ath79/common.c
-+++ b/arch/mips/ath79/common.c
-@@ -64,6 +64,8 @@ void ath79_device_reset_set(u32 mask)
- reg = AR724X_RESET_REG_RESET_MODULE;
- else if (soc_is_ar913x())
- reg = AR913X_RESET_REG_RESET_MODULE;
-+ else if (soc_is_ar933x())
-+ reg = AR933X_RESET_REG_RESET_MODULE;
- else
- BUG();
-
-@@ -86,6 +88,8 @@ void ath79_device_reset_clear(u32 mask)
- reg = AR724X_RESET_REG_RESET_MODULE;
- else if (soc_is_ar913x())
- reg = AR913X_RESET_REG_RESET_MODULE;
-+ else if (soc_is_ar933x())
-+ reg = AR933X_RESET_REG_RESET_MODULE;
- else
- BUG();
-
---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -173,6 +173,7 @@
-
- #define AR724X_RESET_REG_RESET_MODULE 0x1c
-
-+#define AR933X_RESET_REG_RESET_MODULE 0x1c
- #define AR933X_RESET_REG_BOOTSTRAP 0xac
-
- #define MISC_INT_ETHSW BIT(12)
+++ /dev/null
-From f2963f6a811da75e2531fd1312aa124cd73f15d5 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Mon, 20 Jun 2011 21:26:06 +0200
-Subject: [PATCH 09/27] MIPS: ath79: Add AR933X specific IRQ initialization
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Cc: linux-mips@linux-mips.org
-Cc: Kathy Giori <kgiori@qca.qualcomm.com>
-Cc: "Luis R. Rodriguez" <rodrigue@qca.qualcomm.com>
-Patchwork: https://patchwork.linux-mips.org/patch/2530/
-Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
----
- arch/mips/ath79/irq.c | 5 ++++-
- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 5 +++++
- 2 files changed, 9 insertions(+), 1 deletions(-)
-
---- a/arch/mips/ath79/irq.c
-+++ b/arch/mips/ath79/irq.c
-@@ -129,7 +129,7 @@ static void __init ath79_misc_irq_init(v
-
- if (soc_is_ar71xx() || soc_is_ar913x())
- ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
-- else if (soc_is_ar724x())
-+ else if (soc_is_ar724x() || soc_is_ar933x())
- ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
- else
- BUG();
-@@ -186,6 +186,9 @@ void __init arch_init_irq(void)
- } else if (soc_is_ar913x()) {
- ath79_ip2_flush_reg = AR913X_DDR_REG_FLUSH_WMAC;
- ath79_ip3_flush_reg = AR913X_DDR_REG_FLUSH_USB;
-+ } else if (soc_is_ar933x()) {
-+ ath79_ip2_flush_reg = AR933X_DDR_REG_FLUSH_WMAC;
-+ ath79_ip3_flush_reg = AR933X_DDR_REG_FLUSH_USB;
- } else
- BUG();
-
---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -82,6 +82,11 @@
- #define AR913X_DDR_REG_FLUSH_USB 0x84
- #define AR913X_DDR_REG_FLUSH_WMAC 0x88
-
-+#define AR933X_DDR_REG_FLUSH_GE0 0x7c
-+#define AR933X_DDR_REG_FLUSH_GE1 0x80
-+#define AR933X_DDR_REG_FLUSH_USB 0x84
-+#define AR933X_DDR_REG_FLUSH_WMAC 0x88
-+
- /*
- * PLL block
- */
+++ /dev/null
-From e39670cd076caecfa75f5d97803a275dbd1ec4ab Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Mon, 20 Jun 2011 21:26:07 +0200
-Subject: [PATCH 10/27] MIPS: ath79: add AR933X specific GPIO initialization
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Cc: linux-mips@linux-mips.org
-Cc: Kathy Giori <kgiori@qca.qualcomm.com>
-Cc: "Luis R. Rodriguez" <rodrigue@qca.qualcomm.com>
-Patchwork: https://patchwork.linux-mips.org/patch/2524/
-Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
----
- arch/mips/ath79/gpio.c | 2 ++
- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 1 +
- 2 files changed, 3 insertions(+), 0 deletions(-)
-
---- a/arch/mips/ath79/gpio.c
-+++ b/arch/mips/ath79/gpio.c
-@@ -153,6 +153,8 @@ void __init ath79_gpio_init(void)
- ath79_gpio_count = AR724X_GPIO_COUNT;
- else if (soc_is_ar913x())
- ath79_gpio_count = AR913X_GPIO_COUNT;
-+ else if (soc_is_ar933x())
-+ ath79_gpio_count = AR933X_GPIO_COUNT;
- else
- BUG();
-
---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -298,5 +298,6 @@
- #define AR71XX_GPIO_COUNT 16
- #define AR724X_GPIO_COUNT 18
- #define AR913X_GPIO_COUNT 22
-+#define AR933X_GPIO_COUNT 30
-
- #endif /* __ASM_MACH_AR71XX_REGS_H */
+++ /dev/null
-From 7ab361d321763ef6296f35eb18ae05be8e28e64a Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Mon, 20 Jun 2011 21:26:08 +0200
-Subject: [PATCH 11/27] MIPS: ath79: Add config symbol for the AR933X SoCs
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Cc: linux-mips@linux-mips.org
-Cc: Kathy Giori <kgiori@qca.qualcomm.com>
-Cc: "Luis R. Rodriguez" <rodrigue@qca.qualcomm.com>
-Patchwork: https://patchwork.linux-mips.org/patch/2525/
-Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
----
- arch/mips/ath79/Kconfig | 3 +++
- 1 files changed, 3 insertions(+), 0 deletions(-)
-
---- a/arch/mips/ath79/Kconfig
-+++ b/arch/mips/ath79/Kconfig
-@@ -41,6 +41,9 @@ config SOC_AR913X
- select USB_ARCH_HAS_EHCI
- def_bool n
-
-+config SOC_AR933X
-+ def_bool n
-+
- config ATH79_DEV_AR913X_WMAC
- depends on SOC_AR913X
- def_bool n
+++ /dev/null
-From 7191a2673adbddbbb5aea3489892119e698e77b6 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Mon, 20 Jun 2011 21:26:09 +0200
-Subject: [PATCH 12/27] USB: ehci-ath79: Add device_id entry for the AR933X SoCs
-
-Also make the USB_EHCI_ATH79 selectable for the AR933X SoCs.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Cc: linux-mips@linux-mips.org
-Cc: Kathy Giori <kgiori@qca.qualcomm.com>
-Cc: "Luis R. Rodriguez" <rodrigue@qca.qualcomm.com>
-Cc: Greg Kroah-Hartman <gregkh@suse.de>
-Cc: Alan Stern <stern@rowland.harvard.edu>
-Cc: linux-usb@vger.kernel.org
-Patchwork: https://patchwork.linux-mips.org/patch/2529/
-Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
----
- drivers/usb/host/Kconfig | 2 +-
- drivers/usb/host/ehci-ath79.c | 4 ++++
- 2 files changed, 5 insertions(+), 1 deletions(-)
-
---- a/drivers/usb/host/Kconfig
-+++ b/drivers/usb/host/Kconfig
-@@ -210,7 +210,7 @@ config USB_CNS3XXX_EHCI
-
- config USB_EHCI_ATH79
- bool "EHCI support for AR7XXX/AR9XXX SoCs"
-- depends on USB_EHCI_HCD && (SOC_AR71XX || SOC_AR724X || SOC_AR913X)
-+ depends on USB_EHCI_HCD && (SOC_AR71XX || SOC_AR724X || SOC_AR913X || SOC_AR933X)
- select USB_EHCI_ROOT_HUB_TT
- default y
- ---help---
---- a/drivers/usb/host/ehci-ath79.c
-+++ b/drivers/usb/host/ehci-ath79.c
-@@ -33,6 +33,10 @@ static const struct platform_device_id e
- .driver_data = EHCI_ATH79_IP_V2,
- },
- {
-+ .name = "ar933x-ehci",
-+ .driver_data = EHCI_ATH79_IP_V2,
-+ },
-+ {
- /* terminating entry */
- },
- };
+++ /dev/null
-From 1355a27c85ae89225e738b9016656a406542ed1b Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Mon, 20 Jun 2011 21:26:10 +0200
-Subject: [PATCH 13/27] MIPS: ath79: add AR933X specific USB platform device registration
-
-Also select the USB_ARCH_HAS_EHCI symbol in order to make the
-EHCI driver available.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Cc: linux-mips@linux-mips.org
-Cc: Kathy Giori <kgiori@qca.qualcomm.com>
-Cc: "Luis R. Rodriguez" <rodrigue@qca.qualcomm.com>
-Patchwork: https://patchwork.linux-mips.org/patch/2527/
-Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
----
- arch/mips/ath79/Kconfig | 1 +
- arch/mips/ath79/dev-usb.c | 19 +++++++++++++++++++
- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 7 +++++++
- 3 files changed, 27 insertions(+), 0 deletions(-)
-
---- a/arch/mips/ath79/Kconfig
-+++ b/arch/mips/ath79/Kconfig
-@@ -42,6 +42,7 @@ config SOC_AR913X
- def_bool n
-
- config SOC_AR933X
-+ select USB_ARCH_HAS_EHCI
- def_bool n
-
- config ATH79_DEV_AR913X_WMAC
---- a/arch/mips/ath79/dev-usb.c
-+++ b/arch/mips/ath79/dev-usb.c
-@@ -163,6 +163,23 @@ static void __init ar913x_usb_setup(void
- platform_device_register(&ath79_ehci_device);
- }
-
-+static void __init ar933x_usb_setup(void)
-+{
-+ ath79_device_reset_set(AR933X_RESET_USBSUS_OVERRIDE);
-+ mdelay(10);
-+
-+ ath79_device_reset_clear(AR933X_RESET_USB_HOST);
-+ mdelay(10);
-+
-+ ath79_device_reset_clear(AR933X_RESET_USB_PHY);
-+ mdelay(10);
-+
-+ ath79_ehci_resources[0].start = AR933X_EHCI_BASE;
-+ ath79_ehci_resources[0].end = AR933X_EHCI_BASE + AR933X_EHCI_SIZE - 1;
-+ ath79_ehci_device.name = "ar933x-ehci";
-+ platform_device_register(&ath79_ehci_device);
-+}
-+
- void __init ath79_register_usb(void)
- {
- if (soc_is_ar71xx())
-@@ -173,6 +190,8 @@ void __init ath79_register_usb(void)
- ar724x_usb_setup();
- else if (soc_is_ar913x())
- ar913x_usb_setup();
-+ else if (soc_is_ar933x())
-+ ar933x_usb_setup();
- else
- BUG();
- }
---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -56,6 +56,9 @@
- #define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
- #define AR933X_UART_SIZE 0x14
-
-+#define AR933X_EHCI_BASE 0x1b000000
-+#define AR933X_EHCI_SIZE 0x1000
-+
- /*
- * DDR_CTRL block
- */
-@@ -230,6 +233,10 @@
- #define AR913X_RESET_USB_HOST BIT(5)
- #define AR913X_RESET_USB_PHY BIT(4)
-
-+#define AR933X_RESET_USB_HOST BIT(5)
-+#define AR933X_RESET_USB_PHY BIT(4)
-+#define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
-+
- #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
-
- #define REV_ID_MAJOR_MASK 0xfff0
+++ /dev/null
-From 1de387abd06fb67aaa8e27a48e378ffd9aaddd74 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Mon, 20 Jun 2011 19:26:11 +0200
-Subject: [PATCH 14/27] SERIAL: AR933X: Add driver for the built-in UART of the SoC
-
-This patch adds the driver for the built-in UART of the
-Atheros AR933X SoCs.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Cc: linux-mips@linux-mips.org
-Cc: Kathy Giori <kgiori@qca.qualcomm.com>
-Cc: "Luis R. Rodriguez" <rodrigue@qca.qualcomm.com>
-Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
-Cc: linux-serial@vger.kernel.org
-Patchwork: https://patchwork.linux-mips.org/patch/2526/
-Signed-off-by: Alan Cox <alan@linux.intel.com>
-Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
----
- .../include/asm/mach-ath79/ar933x_uart_platform.h | 18 +
- drivers/tty/serial/Kconfig | 23 +
- drivers/tty/serial/Makefile | 1 +
- drivers/tty/serial/ar933x_uart.c | 688 ++++++++++++++++++++
- include/linux/serial_core.h | 4 +
- 5 files changed, 734 insertions(+), 0 deletions(-)
- create mode 100644 arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h
- create mode 100644 drivers/tty/serial/ar933x_uart.c
-
---- /dev/null
-+++ b/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h
-@@ -0,0 +1,18 @@
-+/*
-+ * Platform data definition for Atheros AR933X UART
-+ *
-+ * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+
-+#ifndef _AR933X_UART_PLATFORM_H
-+#define _AR933X_UART_PLATFORM_H
-+
-+struct ar933x_uart_platform_data {
-+ unsigned uartclk;
-+};
-+
-+#endif /* _AR933X_UART_PLATFORM_H */
---- a/drivers/tty/serial/Kconfig
-+++ b/drivers/tty/serial/Kconfig
-@@ -1610,4 +1610,27 @@ config SERIAL_XILINX_PS_UART_CONSOLE
- help
- Enable a Xilinx PS UART port to be the system console.
-
-+config SERIAL_AR933X
-+ bool "AR933X serial port support"
-+ depends on SOC_AR933X
-+ select SERIAL_CORE
-+ help
-+ If you have an Atheros AR933X SOC based board and want to use the
-+ built-in UART of the SoC, say Y to this option.
-+
-+config SERIAL_AR933X_CONSOLE
-+ bool "Console on AR933X serial port"
-+ depends on SERIAL_AR933X=y
-+ select SERIAL_CORE_CONSOLE
-+ help
-+ Enable a built-in UART port of the AR933X to be the system console.
-+
-+config SERIAL_AR933X_NR_UARTS
-+ int "Maximum number of AR933X serial ports"
-+ depends on SERIAL_AR933X
-+ default "2"
-+ help
-+ Set this to the number of serial ports you want the driver
-+ to support.
-+
- endmenu
---- a/drivers/tty/serial/Makefile
-+++ b/drivers/tty/serial/Makefile
-@@ -94,3 +94,4 @@ obj-$(CONFIG_SERIAL_MSM_SMD) += msm_smd_
- obj-$(CONFIG_SERIAL_MXS_AUART) += mxs-auart.o
- obj-$(CONFIG_SERIAL_LANTIQ) += lantiq.o
- obj-$(CONFIG_SERIAL_XILINX_PS_UART) += xilinx_uartps.o
-+obj-$(CONFIG_SERIAL_AR933X) += ar933x_uart.o
---- /dev/null
-+++ b/drivers/tty/serial/ar933x_uart.c
-@@ -0,0 +1,688 @@
-+/*
-+ * Atheros AR933X SoC built-in UART driver
-+ *
-+ * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
-+ *
-+ * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/ioport.h>
-+#include <linux/init.h>
-+#include <linux/console.h>
-+#include <linux/sysrq.h>
-+#include <linux/delay.h>
-+#include <linux/platform_device.h>
-+#include <linux/tty.h>
-+#include <linux/tty_flip.h>
-+#include <linux/serial_core.h>
-+#include <linux/serial.h>
-+#include <linux/slab.h>
-+#include <linux/io.h>
-+#include <linux/irq.h>
-+
-+#include <asm/mach-ath79/ar933x_uart.h>
-+#include <asm/mach-ath79/ar933x_uart_platform.h>
-+
-+#define DRIVER_NAME "ar933x-uart"
-+
-+#define AR933X_DUMMY_STATUS_RD 0x01
-+
-+static struct uart_driver ar933x_uart_driver;
-+
-+struct ar933x_uart_port {
-+ struct uart_port port;
-+ unsigned int ier; /* shadow Interrupt Enable Register */
-+};
-+
-+static inline unsigned int ar933x_uart_read(struct ar933x_uart_port *up,
-+ int offset)
-+{
-+ return readl(up->port.membase + offset);
-+}
-+
-+static inline void ar933x_uart_write(struct ar933x_uart_port *up,
-+ int offset, unsigned int value)
-+{
-+ writel(value, up->port.membase + offset);
-+}
-+
-+static inline void ar933x_uart_rmw(struct ar933x_uart_port *up,
-+ unsigned int offset,
-+ unsigned int mask,
-+ unsigned int val)
-+{
-+ unsigned int t;
-+
-+ t = ar933x_uart_read(up, offset);
-+ t &= ~mask;
-+ t |= val;
-+ ar933x_uart_write(up, offset, t);
-+}
-+
-+static inline void ar933x_uart_rmw_set(struct ar933x_uart_port *up,
-+ unsigned int offset,
-+ unsigned int val)
-+{
-+ ar933x_uart_rmw(up, offset, 0, val);
-+}
-+
-+static inline void ar933x_uart_rmw_clear(struct ar933x_uart_port *up,
-+ unsigned int offset,
-+ unsigned int val)
-+{
-+ ar933x_uart_rmw(up, offset, val, 0);
-+}
-+
-+static inline void ar933x_uart_start_tx_interrupt(struct ar933x_uart_port *up)
-+{
-+ up->ier |= AR933X_UART_INT_TX_EMPTY;
-+ ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
-+}
-+
-+static inline void ar933x_uart_stop_tx_interrupt(struct ar933x_uart_port *up)
-+{
-+ up->ier &= ~AR933X_UART_INT_TX_EMPTY;
-+ ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
-+}
-+
-+static inline void ar933x_uart_putc(struct ar933x_uart_port *up, int ch)
-+{
-+ unsigned int rdata;
-+
-+ rdata = ch & AR933X_UART_DATA_TX_RX_MASK;
-+ rdata |= AR933X_UART_DATA_TX_CSR;
-+ ar933x_uart_write(up, AR933X_UART_DATA_REG, rdata);
-+}
-+
-+static unsigned int ar933x_uart_tx_empty(struct uart_port *port)
-+{
-+ struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
-+ unsigned long flags;
-+ unsigned int rdata;
-+
-+ spin_lock_irqsave(&up->port.lock, flags);
-+ rdata = ar933x_uart_read(up, AR933X_UART_DATA_REG);
-+ spin_unlock_irqrestore(&up->port.lock, flags);
-+
-+ return (rdata & AR933X_UART_DATA_TX_CSR) ? 0 : TIOCSER_TEMT;
-+}
-+
-+static unsigned int ar933x_uart_get_mctrl(struct uart_port *port)
-+{
-+ return TIOCM_CAR;
-+}
-+
-+static void ar933x_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
-+{
-+}
-+
-+static void ar933x_uart_start_tx(struct uart_port *port)
-+{
-+ struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
-+
-+ ar933x_uart_start_tx_interrupt(up);
-+}
-+
-+static void ar933x_uart_stop_tx(struct uart_port *port)
-+{
-+ struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
-+
-+ ar933x_uart_stop_tx_interrupt(up);
-+}
-+
-+static void ar933x_uart_stop_rx(struct uart_port *port)
-+{
-+ struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
-+
-+ up->ier &= ~AR933X_UART_INT_RX_VALID;
-+ ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
-+}
-+
-+static void ar933x_uart_break_ctl(struct uart_port *port, int break_state)
-+{
-+ struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&up->port.lock, flags);
-+ if (break_state == -1)
-+ ar933x_uart_rmw_set(up, AR933X_UART_CS_REG,
-+ AR933X_UART_CS_TX_BREAK);
-+ else
-+ ar933x_uart_rmw_clear(up, AR933X_UART_CS_REG,
-+ AR933X_UART_CS_TX_BREAK);
-+ spin_unlock_irqrestore(&up->port.lock, flags);
-+}
-+
-+static void ar933x_uart_enable_ms(struct uart_port *port)
-+{
-+}
-+
-+static void ar933x_uart_set_termios(struct uart_port *port,
-+ struct ktermios *new,
-+ struct ktermios *old)
-+{
-+ struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
-+ unsigned int cs;
-+ unsigned long flags;
-+ unsigned int baud, scale;
-+
-+ /* Only CS8 is supported */
-+ new->c_cflag &= ~CSIZE;
-+ new->c_cflag |= CS8;
-+
-+ /* Only one stop bit is supported */
-+ new->c_cflag &= ~CSTOPB;
-+
-+ cs = 0;
-+ if (new->c_cflag & PARENB) {
-+ if (!(new->c_cflag & PARODD))
-+ cs |= AR933X_UART_CS_PARITY_EVEN;
-+ else
-+ cs |= AR933X_UART_CS_PARITY_ODD;
-+ } else {
-+ cs |= AR933X_UART_CS_PARITY_NONE;
-+ }
-+
-+ /* Mark/space parity is not supported */
-+ new->c_cflag &= ~CMSPAR;
-+
-+ baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
-+ scale = (port->uartclk / (16 * baud)) - 1;
-+
-+ /*
-+ * Ok, we're now changing the port state. Do it with
-+ * interrupts disabled.
-+ */
-+ spin_lock_irqsave(&up->port.lock, flags);
-+
-+ /* Update the per-port timeout. */
-+ uart_update_timeout(port, new->c_cflag, baud);
-+
-+ up->port.ignore_status_mask = 0;
-+
-+ /* ignore all characters if CREAD is not set */
-+ if ((new->c_cflag & CREAD) == 0)
-+ up->port.ignore_status_mask |= AR933X_DUMMY_STATUS_RD;
-+
-+ ar933x_uart_write(up, AR933X_UART_CLOCK_REG,
-+ scale << AR933X_UART_CLOCK_SCALE_S | 8192);
-+
-+ /* setup configuration register */
-+ ar933x_uart_rmw(up, AR933X_UART_CS_REG, AR933X_UART_CS_PARITY_M, cs);
-+
-+ /* enable host interrupt */
-+ ar933x_uart_rmw_set(up, AR933X_UART_CS_REG,
-+ AR933X_UART_CS_HOST_INT_EN);
-+
-+ spin_unlock_irqrestore(&up->port.lock, flags);
-+
-+ if (tty_termios_baud_rate(new))
-+ tty_termios_encode_baud_rate(new, baud, baud);
-+}
-+
-+static void ar933x_uart_rx_chars(struct ar933x_uart_port *up)
-+{
-+ struct tty_struct *tty;
-+ int max_count = 256;
-+
-+ tty = tty_port_tty_get(&up->port.state->port);
-+ do {
-+ unsigned int rdata;
-+ unsigned char ch;
-+
-+ rdata = ar933x_uart_read(up, AR933X_UART_DATA_REG);
-+ if ((rdata & AR933X_UART_DATA_RX_CSR) == 0)
-+ break;
-+
-+ /* remove the character from the FIFO */
-+ ar933x_uart_write(up, AR933X_UART_DATA_REG,
-+ AR933X_UART_DATA_RX_CSR);
-+
-+ if (!tty) {
-+ /* discard the data if no tty available */
-+ continue;
-+ }
-+
-+ up->port.icount.rx++;
-+ ch = rdata & AR933X_UART_DATA_TX_RX_MASK;
-+
-+ if (uart_handle_sysrq_char(&up->port, ch))
-+ continue;
-+
-+ if ((up->port.ignore_status_mask & AR933X_DUMMY_STATUS_RD) == 0)
-+ tty_insert_flip_char(tty, ch, TTY_NORMAL);
-+ } while (max_count-- > 0);
-+
-+ if (tty) {
-+ tty_flip_buffer_push(tty);
-+ tty_kref_put(tty);
-+ }
-+}
-+
-+static void ar933x_uart_tx_chars(struct ar933x_uart_port *up)
-+{
-+ struct circ_buf *xmit = &up->port.state->xmit;
-+ int count;
-+
-+ if (uart_tx_stopped(&up->port))
-+ return;
-+
-+ count = up->port.fifosize;
-+ do {
-+ unsigned int rdata;
-+
-+ rdata = ar933x_uart_read(up, AR933X_UART_DATA_REG);
-+ if ((rdata & AR933X_UART_DATA_TX_CSR) == 0)
-+ break;
-+
-+ if (up->port.x_char) {
-+ ar933x_uart_putc(up, up->port.x_char);
-+ up->port.icount.tx++;
-+ up->port.x_char = 0;
-+ continue;
-+ }
-+
-+ if (uart_circ_empty(xmit))
-+ break;
-+
-+ ar933x_uart_putc(up, xmit->buf[xmit->tail]);
-+
-+ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
-+ up->port.icount.tx++;
-+ } while (--count > 0);
-+
-+ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
-+ uart_write_wakeup(&up->port);
-+
-+ if (!uart_circ_empty(xmit))
-+ ar933x_uart_start_tx_interrupt(up);
-+}
-+
-+static irqreturn_t ar933x_uart_interrupt(int irq, void *dev_id)
-+{
-+ struct ar933x_uart_port *up = dev_id;
-+ unsigned int status;
-+
-+ status = ar933x_uart_read(up, AR933X_UART_CS_REG);
-+ if ((status & AR933X_UART_CS_HOST_INT) == 0)
-+ return IRQ_NONE;
-+
-+ spin_lock(&up->port.lock);
-+
-+ status = ar933x_uart_read(up, AR933X_UART_INT_REG);
-+ status &= ar933x_uart_read(up, AR933X_UART_INT_EN_REG);
-+
-+ if (status & AR933X_UART_INT_RX_VALID) {
-+ ar933x_uart_write(up, AR933X_UART_INT_REG,
-+ AR933X_UART_INT_RX_VALID);
-+ ar933x_uart_rx_chars(up);
-+ }
-+
-+ if (status & AR933X_UART_INT_TX_EMPTY) {
-+ ar933x_uart_write(up, AR933X_UART_INT_REG,
-+ AR933X_UART_INT_TX_EMPTY);
-+ ar933x_uart_stop_tx_interrupt(up);
-+ ar933x_uart_tx_chars(up);
-+ }
-+
-+ spin_unlock(&up->port.lock);
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static int ar933x_uart_startup(struct uart_port *port)
-+{
-+ struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
-+ unsigned long flags;
-+ int ret;
-+
-+ ret = request_irq(up->port.irq, ar933x_uart_interrupt,
-+ up->port.irqflags, dev_name(up->port.dev), up);
-+ if (ret)
-+ return ret;
-+
-+ spin_lock_irqsave(&up->port.lock, flags);
-+
-+ /* Enable HOST interrupts */
-+ ar933x_uart_rmw_set(up, AR933X_UART_CS_REG,
-+ AR933X_UART_CS_HOST_INT_EN);
-+
-+ /* Enable RX interrupts */
-+ up->ier = AR933X_UART_INT_RX_VALID;
-+ ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
-+
-+ spin_unlock_irqrestore(&up->port.lock, flags);
-+
-+ return 0;
-+}
-+
-+static void ar933x_uart_shutdown(struct uart_port *port)
-+{
-+ struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
-+
-+ /* Disable all interrupts */
-+ up->ier = 0;
-+ ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
-+
-+ /* Disable break condition */
-+ ar933x_uart_rmw_clear(up, AR933X_UART_CS_REG,
-+ AR933X_UART_CS_TX_BREAK);
-+
-+ free_irq(up->port.irq, up);
-+}
-+
-+static const char *ar933x_uart_type(struct uart_port *port)
-+{
-+ return (port->type == PORT_AR933X) ? "AR933X UART" : NULL;
-+}
-+
-+static void ar933x_uart_release_port(struct uart_port *port)
-+{
-+ /* Nothing to release ... */
-+}
-+
-+static int ar933x_uart_request_port(struct uart_port *port)
-+{
-+ /* UARTs always present */
-+ return 0;
-+}
-+
-+static void ar933x_uart_config_port(struct uart_port *port, int flags)
-+{
-+ if (flags & UART_CONFIG_TYPE)
-+ port->type = PORT_AR933X;
-+}
-+
-+static int ar933x_uart_verify_port(struct uart_port *port,
-+ struct serial_struct *ser)
-+{
-+ if (ser->type != PORT_UNKNOWN &&
-+ ser->type != PORT_AR933X)
-+ return -EINVAL;
-+
-+ if (ser->irq < 0 || ser->irq >= NR_IRQS)
-+ return -EINVAL;
-+
-+ if (ser->baud_base < 28800)
-+ return -EINVAL;
-+
-+ return 0;
-+}
-+
-+static struct uart_ops ar933x_uart_ops = {
-+ .tx_empty = ar933x_uart_tx_empty,
-+ .set_mctrl = ar933x_uart_set_mctrl,
-+ .get_mctrl = ar933x_uart_get_mctrl,
-+ .stop_tx = ar933x_uart_stop_tx,
-+ .start_tx = ar933x_uart_start_tx,
-+ .stop_rx = ar933x_uart_stop_rx,
-+ .enable_ms = ar933x_uart_enable_ms,
-+ .break_ctl = ar933x_uart_break_ctl,
-+ .startup = ar933x_uart_startup,
-+ .shutdown = ar933x_uart_shutdown,
-+ .set_termios = ar933x_uart_set_termios,
-+ .type = ar933x_uart_type,
-+ .release_port = ar933x_uart_release_port,
-+ .request_port = ar933x_uart_request_port,
-+ .config_port = ar933x_uart_config_port,
-+ .verify_port = ar933x_uart_verify_port,
-+};
-+
-+#ifdef CONFIG_SERIAL_AR933X_CONSOLE
-+
-+static struct ar933x_uart_port *
-+ar933x_console_ports[CONFIG_SERIAL_AR933X_NR_UARTS];
-+
-+static void ar933x_uart_wait_xmitr(struct ar933x_uart_port *up)
-+{
-+ unsigned int status;
-+ unsigned int timeout = 60000;
-+
-+ /* Wait up to 60ms for the character(s) to be sent. */
-+ do {
-+ status = ar933x_uart_read(up, AR933X_UART_DATA_REG);
-+ if (--timeout == 0)
-+ break;
-+ udelay(1);
-+ } while ((status & AR933X_UART_DATA_TX_CSR) == 0);
-+}
-+
-+static void ar933x_uart_console_putchar(struct uart_port *port, int ch)
-+{
-+ struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
-+
-+ ar933x_uart_wait_xmitr(up);
-+ ar933x_uart_putc(up, ch);
-+}
-+
-+static void ar933x_uart_console_write(struct console *co, const char *s,
-+ unsigned int count)
-+{
-+ struct ar933x_uart_port *up = ar933x_console_ports[co->index];
-+ unsigned long flags;
-+ unsigned int int_en;
-+ int locked = 1;
-+
-+ local_irq_save(flags);
-+
-+ if (up->port.sysrq)
-+ locked = 0;
-+ else if (oops_in_progress)
-+ locked = spin_trylock(&up->port.lock);
-+ else
-+ spin_lock(&up->port.lock);
-+
-+ /*
-+ * First save the IER then disable the interrupts
-+ */
-+ int_en = ar933x_uart_read(up, AR933X_UART_INT_EN_REG);
-+ ar933x_uart_write(up, AR933X_UART_INT_EN_REG, 0);
-+
-+ uart_console_write(&up->port, s, count, ar933x_uart_console_putchar);
-+
-+ /*
-+ * Finally, wait for transmitter to become empty
-+ * and restore the IER
-+ */
-+ ar933x_uart_wait_xmitr(up);
-+ ar933x_uart_write(up, AR933X_UART_INT_EN_REG, int_en);
-+
-+ ar933x_uart_write(up, AR933X_UART_INT_REG, AR933X_UART_INT_ALLINTS);
-+
-+ if (locked)
-+ spin_unlock(&up->port.lock);
-+
-+ local_irq_restore(flags);
-+}
-+
-+static int ar933x_uart_console_setup(struct console *co, char *options)
-+{
-+ struct ar933x_uart_port *up;
-+ int baud = 115200;
-+ int bits = 8;
-+ int parity = 'n';
-+ int flow = 'n';
-+
-+ if (co->index < 0 || co->index >= CONFIG_SERIAL_AR933X_NR_UARTS)
-+ return -EINVAL;
-+
-+ up = ar933x_console_ports[co->index];
-+ if (!up)
-+ return -ENODEV;
-+
-+ if (options)
-+ uart_parse_options(options, &baud, &parity, &bits, &flow);
-+
-+ return uart_set_options(&up->port, co, baud, parity, bits, flow);
-+}
-+
-+static struct console ar933x_uart_console = {
-+ .name = "ttyATH",
-+ .write = ar933x_uart_console_write,
-+ .device = uart_console_device,
-+ .setup = ar933x_uart_console_setup,
-+ .flags = CON_PRINTBUFFER,
-+ .index = -1,
-+ .data = &ar933x_uart_driver,
-+};
-+
-+static void ar933x_uart_add_console_port(struct ar933x_uart_port *up)
-+{
-+ ar933x_console_ports[up->port.line] = up;
-+}
-+
-+#define AR933X_SERIAL_CONSOLE (&ar933x_uart_console)
-+
-+#else
-+
-+static inline void ar933x_uart_add_console_port(struct ar933x_uart_port *up) {}
-+
-+#define AR933X_SERIAL_CONSOLE NULL
-+
-+#endif /* CONFIG_SERIAL_AR933X_CONSOLE */
-+
-+static struct uart_driver ar933x_uart_driver = {
-+ .owner = THIS_MODULE,
-+ .driver_name = DRIVER_NAME,
-+ .dev_name = "ttyATH",
-+ .nr = CONFIG_SERIAL_AR933X_NR_UARTS,
-+ .cons = AR933X_SERIAL_CONSOLE,
-+};
-+
-+static int __devinit ar933x_uart_probe(struct platform_device *pdev)
-+{
-+ struct ar933x_uart_platform_data *pdata;
-+ struct ar933x_uart_port *up;
-+ struct uart_port *port;
-+ struct resource *mem_res;
-+ struct resource *irq_res;
-+ int id;
-+ int ret;
-+
-+ pdata = pdev->dev.platform_data;
-+ if (!pdata)
-+ return -EINVAL;
-+
-+ id = pdev->id;
-+ if (id == -1)
-+ id = 0;
-+
-+ if (id > CONFIG_SERIAL_AR933X_NR_UARTS)
-+ return -EINVAL;
-+
-+ mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ if (!mem_res) {
-+ dev_err(&pdev->dev, "no MEM resource\n");
-+ return -EINVAL;
-+ }
-+
-+ irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-+ if (!irq_res) {
-+ dev_err(&pdev->dev, "no IRQ resource\n");
-+ return -EINVAL;
-+ }
-+
-+ up = kzalloc(sizeof(struct ar933x_uart_port), GFP_KERNEL);
-+ if (!up)
-+ return -ENOMEM;
-+
-+ port = &up->port;
-+ port->mapbase = mem_res->start;
-+
-+ port->membase = ioremap(mem_res->start, AR933X_UART_REGS_SIZE);
-+ if (!port->membase) {
-+ ret = -ENOMEM;
-+ goto err_free_up;
-+ }
-+
-+ port->line = id;
-+ port->irq = irq_res->start;
-+ port->dev = &pdev->dev;
-+ port->type = PORT_AR933X;
-+ port->iotype = UPIO_MEM32;
-+ port->uartclk = pdata->uartclk;
-+
-+ port->regshift = 2;
-+ port->fifosize = AR933X_UART_FIFO_SIZE;
-+ port->ops = &ar933x_uart_ops;
-+
-+ ar933x_uart_add_console_port(up);
-+
-+ ret = uart_add_one_port(&ar933x_uart_driver, &up->port);
-+ if (ret)
-+ goto err_unmap;
-+
-+ platform_set_drvdata(pdev, up);
-+ return 0;
-+
-+err_unmap:
-+ iounmap(up->port.membase);
-+err_free_up:
-+ kfree(up);
-+ return ret;
-+}
-+
-+static int __devexit ar933x_uart_remove(struct platform_device *pdev)
-+{
-+ struct ar933x_uart_port *up;
-+
-+ up = platform_get_drvdata(pdev);
-+ platform_set_drvdata(pdev, NULL);
-+
-+ if (up) {
-+ uart_remove_one_port(&ar933x_uart_driver, &up->port);
-+ iounmap(up->port.membase);
-+ kfree(up);
-+ }
-+
-+ return 0;
-+}
-+
-+static struct platform_driver ar933x_uart_platform_driver = {
-+ .probe = ar933x_uart_probe,
-+ .remove = __devexit_p(ar933x_uart_remove),
-+ .driver = {
-+ .name = DRIVER_NAME,
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+static int __init ar933x_uart_init(void)
-+{
-+ int ret;
-+
-+ ar933x_uart_driver.nr = CONFIG_SERIAL_AR933X_NR_UARTS;
-+ ret = uart_register_driver(&ar933x_uart_driver);
-+ if (ret)
-+ goto err_out;
-+
-+ ret = platform_driver_register(&ar933x_uart_platform_driver);
-+ if (ret)
-+ goto err_unregister_uart_driver;
-+
-+ return 0;
-+
-+err_unregister_uart_driver:
-+ uart_unregister_driver(&ar933x_uart_driver);
-+err_out:
-+ return ret;
-+}
-+
-+static void __exit ar933x_uart_exit(void)
-+{
-+ platform_driver_unregister(&ar933x_uart_platform_driver);
-+ uart_unregister_driver(&ar933x_uart_driver);
-+}
-+
-+module_init(ar933x_uart_init);
-+module_exit(ar933x_uart_exit);
-+
-+MODULE_DESCRIPTION("Atheros AR933X UART driver");
-+MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
-+MODULE_LICENSE("GPL v2");
-+MODULE_ALIAS("platform:" DRIVER_NAME);
---- a/include/linux/serial_core.h
-+++ b/include/linux/serial_core.h
-@@ -207,6 +207,10 @@
- /* Xilinx PSS UART */
- #define PORT_XUARTPS 98
-
-+/* Atheros AR933X SoC */
-+#define PORT_AR933X 99
-+
-+
- #ifdef __KERNEL__
-
- #include <linux/compiler.h>
+++ /dev/null
-From d9215f4c69b414f589eeeff002af7ef58b96b172 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Mon, 20 Jun 2011 19:26:12 +0200
-Subject: [PATCH 15/27] MIPS: ath79: register UART device for the AR933X SoCs
-
-The AR933X SoCs does not have a 8250 compatible UART, they
-are using a different UART core. Register a different platform
-device for the different UART.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Cc: linux-mips@linux-mips.org
-Cc: Kathy Giori <kgiori@qca.qualcomm.com>
-Cc: "Luis R. Rodriguez" <rodrigue@qca.qualcomm.com>
-Patchwork: https://patchwork.linux-mips.org/patch/2528/
-Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
----
- arch/mips/ath79/dev-common.c | 38 ++++++++++++++++++++++++++++++++++++--
- 1 files changed, 36 insertions(+), 2 deletions(-)
-
---- a/arch/mips/ath79/dev-common.c
-+++ b/arch/mips/ath79/dev-common.c
-@@ -20,6 +20,7 @@
-
- #include <asm/mach-ath79/ath79.h>
- #include <asm/mach-ath79/ar71xx_regs.h>
-+#include <asm/mach-ath79/ar933x_uart_platform.h>
- #include "common.h"
- #include "dev-common.h"
-
-@@ -54,6 +55,30 @@ static struct platform_device ath79_uart
- },
- };
-
-+static struct resource ar933x_uart_resources[] = {
-+ {
-+ .start = AR933X_UART_BASE,
-+ .end = AR933X_UART_BASE + AR71XX_UART_SIZE - 1,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ {
-+ .start = ATH79_MISC_IRQ_UART,
-+ .end = ATH79_MISC_IRQ_UART,
-+ .flags = IORESOURCE_IRQ,
-+ },
-+};
-+
-+static struct ar933x_uart_platform_data ar933x_uart_data;
-+static struct platform_device ar933x_uart_device = {
-+ .name = "ar933x-uart",
-+ .id = -1,
-+ .resource = ar933x_uart_resources,
-+ .num_resources = ARRAY_SIZE(ar933x_uart_resources),
-+ .dev = {
-+ .platform_data = &ar933x_uart_data,
-+ },
-+};
-+
- void __init ath79_register_uart(void)
- {
- struct clk *clk;
-@@ -62,8 +87,17 @@ void __init ath79_register_uart(void)
- if (IS_ERR(clk))
- panic("unable to get UART clock, err=%ld", PTR_ERR(clk));
-
-- ath79_uart_data[0].uartclk = clk_get_rate(clk);
-- platform_device_register(&ath79_uart_device);
-+ if (soc_is_ar71xx() ||
-+ soc_is_ar724x() ||
-+ soc_is_ar913x()) {
-+ ath79_uart_data[0].uartclk = clk_get_rate(clk);
-+ platform_device_register(&ath79_uart_device);
-+ } else if (soc_is_ar933x()) {
-+ ar933x_uart_data.uartclk = clk_get_rate(clk);
-+ platform_device_register(&ar933x_uart_device);
-+ } else {
-+ BUG();
-+ }
- }
-
- static struct platform_device ath79_wdt_device = {
+++ /dev/null
-From d7b27740e8376c1c147297b526f9a8e330c1fe17 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Mon, 20 Jun 2011 19:26:13 +0200
-Subject: [PATCH 16/27] MIPS: ath79: Add initial support for the Atheros AP121 reference board
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Cc: linux-mips@linux-mips.org
-Cc: Kathy Giori <kgiori@qca.qualcomm.com>
-Cc: "Luis R. Rodriguez" <rodrigue@qca.qualcomm.com>
-Patchwork: https://patchwork.linux-mips.org/patch/2531/
-Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
----
- arch/mips/ath79/Kconfig | 11 +++++
- arch/mips/ath79/Makefile | 1 +
- arch/mips/ath79/mach-ap121.c | 88 ++++++++++++++++++++++++++++++++++++++++++
- arch/mips/ath79/machtypes.h | 1 +
- 4 files changed, 101 insertions(+), 0 deletions(-)
- create mode 100644 arch/mips/ath79/mach-ap121.c
-
---- a/arch/mips/ath79/Kconfig
-+++ b/arch/mips/ath79/Kconfig
-@@ -2,6 +2,17 @@ if ATH79
-
- menu "Atheros AR71XX/AR724X/AR913X machine selection"
-
-+config ATH79_MACH_AP121
-+ bool "Atheros AP121 reference board"
-+ select SOC_AR933X
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_SPI
-+ select ATH79_DEV_USB
-+ help
-+ Say 'Y' here if you want your kernel to support the
-+ Atheros AP121 reference board.
-+
- config ATH79_MACH_AP81
- bool "Atheros AP81 reference board"
- select SOC_AR913X
---- a/arch/mips/ath79/Makefile
-+++ b/arch/mips/ath79/Makefile
-@@ -25,5 +25,6 @@ obj-$(CONFIG_ATH79_DEV_USB) += dev-usb.
- #
- # Machines
- #
-+obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o
- obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o
- obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o
---- /dev/null
-+++ b/arch/mips/ath79/mach-ap121.c
-@@ -0,0 +1,88 @@
-+/*
-+ * Atheros AP121 board support
-+ *
-+ * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+
-+#include "machtypes.h"
-+#include "dev-gpio-buttons.h"
-+#include "dev-leds-gpio.h"
-+#include "dev-spi.h"
-+#include "dev-usb.h"
-+
-+#define AP121_GPIO_LED_WLAN 0
-+#define AP121_GPIO_LED_USB 1
-+
-+#define AP121_GPIO_BTN_JUMPSTART 11
-+#define AP121_GPIO_BTN_RESET 12
-+
-+#define AP121_KEYS_POLL_INTERVAL 20 /* msecs */
-+#define AP121_KEYS_DEBOUNCE_INTERVAL (3 * AP121_KEYS_POLL_INTERVAL)
-+
-+#define AP121_CAL_DATA_ADDR 0x1fff1000
-+
-+static struct gpio_led ap121_leds_gpio[] __initdata = {
-+ {
-+ .name = "ap121:green:usb",
-+ .gpio = AP121_GPIO_LED_USB,
-+ .active_low = 0,
-+ },
-+ {
-+ .name = "ap121:green:wlan",
-+ .gpio = AP121_GPIO_LED_WLAN,
-+ .active_low = 0,
-+ },
-+};
-+
-+static struct gpio_keys_button ap121_gpio_keys[] __initdata = {
-+ {
-+ .desc = "jumpstart button",
-+ .type = EV_KEY,
-+ .code = KEY_WPS_BUTTON,
-+ .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL,
-+ .gpio = AP121_GPIO_BTN_JUMPSTART,
-+ .active_low = 1,
-+ },
-+ {
-+ .desc = "reset button",
-+ .type = EV_KEY,
-+ .code = KEY_RESTART,
-+ .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL,
-+ .gpio = AP121_GPIO_BTN_RESET,
-+ .active_low = 1,
-+ }
-+};
-+
-+static struct spi_board_info ap121_spi_info[] = {
-+ {
-+ .bus_num = 0,
-+ .chip_select = 0,
-+ .max_speed_hz = 25000000,
-+ .modalias = "mx25l1606e",
-+ }
-+};
-+
-+static struct ath79_spi_platform_data ap121_spi_data = {
-+ .bus_num = 0,
-+ .num_chipselect = 1,
-+};
-+
-+static void __init ap121_setup(void)
-+{
-+ ath79_register_leds_gpio(-1, ARRAY_SIZE(ap121_leds_gpio),
-+ ap121_leds_gpio);
-+ ath79_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL,
-+ ARRAY_SIZE(ap121_gpio_keys),
-+ ap121_gpio_keys);
-+
-+ ath79_register_spi(&ap121_spi_data, ap121_spi_info,
-+ ARRAY_SIZE(ap121_spi_info));
-+ ath79_register_usb();
-+}
-+
-+MIPS_MACHINE(ATH79_MACH_AP121, "AP121", "Atheros AP121 reference board",
-+ ap121_setup);
---- a/arch/mips/ath79/machtypes.h
-+++ b/arch/mips/ath79/machtypes.h
-@@ -16,6 +16,7 @@
-
- enum ath79_mach_type {
- ATH79_MACH_GENERIC = 0,
-+ ATH79_MACH_AP121, /* Atheros AP121 reference board */
- ATH79_MACH_AP81, /* Atheros AP81 reference board */
- ATH79_MACH_PB44, /* Atheros PB44 reference board */
- };
+++ /dev/null
-From 958e444a5a7750c407ed0c90af28f74295478e99 Mon Sep 17 00:00:00 2001
-From: Rene Bolldorf <xsecute@googlemail.com>
-Date: Thu, 17 Nov 2011 14:25:09 +0000
-Subject: [PATCH 17/27] MIPS: Initial PCI support for Atheros 724x SoCs.
-
-[ralf@linux-mips.org: Fixed the odd formatting of all break statements.]
-
-Signed-off-by: Rene Bolldorf <xsecute@googlemail.com>
-Cc: linux-mips@linux-mips.org
-Cc: linux-kernel@vger.kernel.org
-Patchwork: https://patchwork.linux-mips.org/patch/3019/
-Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
----
- arch/mips/include/asm/mach-ath79/pci-ath724x.h | 21 +++
- arch/mips/pci/Makefile | 1 +
- arch/mips/pci/pci-ath724x.c | 174 ++++++++++++++++++++++++
- 3 files changed, 196 insertions(+), 0 deletions(-)
- create mode 100644 arch/mips/include/asm/mach-ath79/pci-ath724x.h
- create mode 100644 arch/mips/pci/pci-ath724x.c
-
---- /dev/null
-+++ b/arch/mips/include/asm/mach-ath79/pci-ath724x.h
-@@ -0,0 +1,21 @@
-+/*
-+ * Atheros 724x PCI support
-+ *
-+ * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+
-+#ifndef __ASM_MACH_ATH79_PCI_ATH724X_H
-+#define __ASM_MACH_ATH79_PCI_ATH724X_H
-+
-+struct ath724x_pci_data {
-+ int irq;
-+ void *pdata;
-+};
-+
-+void ath724x_pci_add_data(struct ath724x_pci_data *data, int size);
-+
-+#endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */
---- a/arch/mips/pci/Makefile
-+++ b/arch/mips/pci/Makefile
-@@ -19,6 +19,7 @@ obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o
- obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \
- ops-bcm63xx.o
- obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o
-+obj-$(CONFIG_SOC_AR724X) += pci-ath724x.o
-
- #
- # These are still pretty much in the old state, watch, go blind.
---- /dev/null
-+++ b/arch/mips/pci/pci-ath724x.c
-@@ -0,0 +1,174 @@
-+/*
-+ * Atheros 724x PCI support
-+ *
-+ * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+
-+#include <linux/pci.h>
-+#include <asm/mach-ath79/pci-ath724x.h>
-+
-+#define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys))
-+#define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val))
-+
-+#define ATH724X_PCI_DEV_BASE 0x14000000
-+#define ATH724X_PCI_MEM_BASE 0x10000000
-+#define ATH724X_PCI_MEM_SIZE 0x08000000
-+
-+static DEFINE_SPINLOCK(ath724x_pci_lock);
-+static struct ath724x_pci_data *pci_data;
-+static int pci_data_size;
-+
-+static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
-+ int size, uint32_t *value)
-+{
-+ unsigned long flags, addr, tval, mask;
-+
-+ if (devfn)
-+ return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+ if (where & (size - 1))
-+ return PCIBIOS_BAD_REGISTER_NUMBER;
-+
-+ spin_lock_irqsave(&ath724x_pci_lock, flags);
-+
-+ switch (size) {
-+ case 1:
-+ addr = where & ~3;
-+ mask = 0xff000000 >> ((where % 4) * 8);
-+ tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
-+ tval = tval & ~mask;
-+ *value = (tval >> ((4 - (where % 4))*8));
-+ break;
-+ case 2:
-+ addr = where & ~3;
-+ mask = 0xffff0000 >> ((where % 4)*8);
-+ tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
-+ tval = tval & ~mask;
-+ *value = (tval >> ((4 - (where % 4))*8));
-+ break;
-+ case 4:
-+ *value = reg_read(ATH724X_PCI_DEV_BASE + where);
-+ break;
-+ default:
-+ spin_unlock_irqrestore(&ath724x_pci_lock, flags);
-+
-+ return PCIBIOS_BAD_REGISTER_NUMBER;
-+ }
-+
-+ spin_unlock_irqrestore(&ath724x_pci_lock, flags);
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
-+ int size, uint32_t value)
-+{
-+ unsigned long flags, tval, addr, mask;
-+
-+ if (devfn)
-+ return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+ if (where & (size - 1))
-+ return PCIBIOS_BAD_REGISTER_NUMBER;
-+
-+ spin_lock_irqsave(&ath724x_pci_lock, flags);
-+
-+ switch (size) {
-+ case 1:
-+ addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
-+ mask = 0xff000000 >> ((where % 4)*8);
-+ tval = reg_read(addr);
-+ tval = tval & ~mask;
-+ tval |= (value << ((4 - (where % 4))*8)) & mask;
-+ reg_write(addr, tval);
-+ break;
-+ case 2:
-+ addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
-+ mask = 0xffff0000 >> ((where % 4)*8);
-+ tval = reg_read(addr);
-+ tval = tval & ~mask;
-+ tval |= (value << ((4 - (where % 4))*8)) & mask;
-+ reg_write(addr, tval);
-+ break;
-+ case 4:
-+ reg_write((ATH724X_PCI_DEV_BASE + where), value);
-+ break;
-+ default:
-+ spin_unlock_irqrestore(&ath724x_pci_lock, flags);
-+
-+ return PCIBIOS_BAD_REGISTER_NUMBER;
-+ }
-+
-+ spin_unlock_irqrestore(&ath724x_pci_lock, flags);
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static struct pci_ops ath724x_pci_ops = {
-+ .read = ath724x_pci_read,
-+ .write = ath724x_pci_write,
-+};
-+
-+static struct resource ath724x_io_resource = {
-+ .name = "PCI IO space",
-+ .start = 0,
-+ .end = 0,
-+ .flags = IORESOURCE_IO,
-+};
-+
-+static struct resource ath724x_mem_resource = {
-+ .name = "PCI memory space",
-+ .start = ATH724X_PCI_MEM_BASE,
-+ .end = ATH724X_PCI_MEM_BASE + ATH724X_PCI_MEM_SIZE - 1,
-+ .flags = IORESOURCE_MEM,
-+};
-+
-+static struct pci_controller ath724x_pci_controller = {
-+ .pci_ops = &ath724x_pci_ops,
-+ .io_resource = &ath724x_io_resource,
-+ .mem_resource = &ath724x_mem_resource,
-+};
-+
-+void ath724x_pci_add_data(struct ath724x_pci_data *data, int size)
-+{
-+ pci_data = data;
-+ pci_data_size = size;
-+}
-+
-+int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
-+{
-+ unsigned int devfn = dev->devfn;
-+ int irq = -1;
-+
-+ if (devfn > pci_data_size - 1)
-+ return irq;
-+
-+ irq = pci_data[devfn].irq;
-+
-+ return irq;
-+}
-+
-+int pcibios_plat_dev_init(struct pci_dev *dev)
-+{
-+ unsigned int devfn = dev->devfn;
-+
-+ if (devfn > pci_data_size - 1)
-+ return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+ dev->dev.platform_data = pci_data[devfn].pdata;
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static int __init ath724x_pcibios_init(void)
-+{
-+ register_pci_controller(&ath724x_pci_controller);
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+arch_initcall(ath724x_pcibios_init);
+++ /dev/null
-From e6a1210bef8b48a946f1afb6d951f4b2448219ac Mon Sep 17 00:00:00 2001
-From: Rene Bolldorf <xsecute@googlemail.com>
-Date: Fri, 18 Nov 2011 00:17:42 +0000
-Subject: [PATCH 18/27] Initial support for the Ubiquiti Networks XM board (rev 1.0).
-
-Signed-off-by: Rene Bolldorf <xsecute@googlemail.com>
-Cc: linux-mips@linux-mips.org
-Cc: linux-kernel@vger.kernel.org
-Patchwork: https://patchwork.linux-mips.org/patch/3020/
-Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
----
- arch/mips/ath79/Kconfig | 11 ++++
- arch/mips/ath79/Makefile | 1 +
- arch/mips/ath79/mach-ubnt-xm.c | 119 ++++++++++++++++++++++++++++++++++++++++
- arch/mips/ath79/machtypes.h | 1 +
- 4 files changed, 132 insertions(+), 0 deletions(-)
- create mode 100644 arch/mips/ath79/mach-ubnt-xm.c
-
---- a/arch/mips/ath79/Kconfig
-+++ b/arch/mips/ath79/Kconfig
-@@ -36,6 +36,16 @@ config ATH79_MACH_PB44
- Say 'Y' here if you want your kernel to support the
- Atheros PB44 reference board.
-
-+config ATH79_MACH_UBNT_XM
-+ bool "Ubiquiti Networks XM (rev 1.0) board"
-+ select SOC_AR724X
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_SPI
-+ help
-+ Say 'Y' here if you want your kernel to support the
-+ Ubiquiti Networks XM (rev 1.0) board.
-+
- endmenu
-
- config SOC_AR71XX
-@@ -46,6 +56,7 @@ config SOC_AR71XX
- config SOC_AR724X
- select USB_ARCH_HAS_EHCI
- select USB_ARCH_HAS_OHCI
-+ select HW_HAS_PCI
- def_bool n
-
- config SOC_AR913X
---- a/arch/mips/ath79/Makefile
-+++ b/arch/mips/ath79/Makefile
-@@ -28,3 +28,4 @@ obj-$(CONFIG_ATH79_DEV_USB) += dev-usb.
- obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o
- obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o
- obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o
-+obj-$(CONFIG_ATH79_MACH_UBNT_XM) += mach-ubnt-xm.o
---- /dev/null
-+++ b/arch/mips/ath79/mach-ubnt-xm.c
-@@ -0,0 +1,119 @@
-+/*
-+ * Ubiquiti Networks XM (rev 1.0) board support
-+ *
-+ * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
-+ *
-+ * Derived from: mach-pb44.c
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/pci.h>
-+
-+#ifdef CONFIG_PCI
-+#include <linux/ath9k_platform.h>
-+#include <asm/mach-ath79/pci-ath724x.h>
-+#endif /* CONFIG_PCI */
-+
-+#include "machtypes.h"
-+#include "dev-gpio-buttons.h"
-+#include "dev-leds-gpio.h"
-+#include "dev-spi.h"
-+
-+#define UBNT_XM_GPIO_LED_L1 0
-+#define UBNT_XM_GPIO_LED_L2 1
-+#define UBNT_XM_GPIO_LED_L3 11
-+#define UBNT_XM_GPIO_LED_L4 7
-+
-+#define UBNT_XM_GPIO_BTN_RESET 12
-+
-+#define UBNT_XM_KEYS_POLL_INTERVAL 20
-+#define UBNT_XM_KEYS_DEBOUNCE_INTERVAL (3 * UBNT_XM_KEYS_POLL_INTERVAL)
-+
-+#define UBNT_XM_PCI_IRQ 48
-+#define UBNT_XM_EEPROM_ADDR (u8 *) KSEG1ADDR(0x1fff1000)
-+
-+static struct gpio_led ubnt_xm_leds_gpio[] __initdata = {
-+ {
-+ .name = "ubnt-xm:red:link1",
-+ .gpio = UBNT_XM_GPIO_LED_L1,
-+ .active_low = 0,
-+ }, {
-+ .name = "ubnt-xm:orange:link2",
-+ .gpio = UBNT_XM_GPIO_LED_L2,
-+ .active_low = 0,
-+ }, {
-+ .name = "ubnt-xm:green:link3",
-+ .gpio = UBNT_XM_GPIO_LED_L3,
-+ .active_low = 0,
-+ }, {
-+ .name = "ubnt-xm:green:link4",
-+ .gpio = UBNT_XM_GPIO_LED_L4,
-+ .active_low = 0,
-+ },
-+};
-+
-+static struct gpio_keys_button ubnt_xm_gpio_keys[] __initdata = {
-+ {
-+ .desc = "reset",
-+ .type = EV_KEY,
-+ .code = KEY_RESTART,
-+ .debounce_interval = UBNT_XM_KEYS_DEBOUNCE_INTERVAL,
-+ .gpio = UBNT_XM_GPIO_BTN_RESET,
-+ .active_low = 1,
-+ }
-+};
-+
-+static struct spi_board_info ubnt_xm_spi_info[] = {
-+ {
-+ .bus_num = 0,
-+ .chip_select = 0,
-+ .max_speed_hz = 25000000,
-+ .modalias = "mx25l6405d",
-+ }
-+};
-+
-+static struct ath79_spi_platform_data ubnt_xm_spi_data = {
-+ .bus_num = 0,
-+ .num_chipselect = 1,
-+};
-+
-+#ifdef CONFIG_PCI
-+static struct ath9k_platform_data ubnt_xm_eeprom_data;
-+
-+static struct ath724x_pci_data ubnt_xm_pci_data[] = {
-+ {
-+ .irq = UBNT_XM_PCI_IRQ,
-+ .pdata = &ubnt_xm_eeprom_data,
-+ },
-+};
-+#endif /* CONFIG_PCI */
-+
-+static void __init ubnt_xm_init(void)
-+{
-+ ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xm_leds_gpio),
-+ ubnt_xm_leds_gpio);
-+
-+ ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL,
-+ ARRAY_SIZE(ubnt_xm_gpio_keys),
-+ ubnt_xm_gpio_keys);
-+
-+ ath79_register_spi(&ubnt_xm_spi_data, ubnt_xm_spi_info,
-+ ARRAY_SIZE(ubnt_xm_spi_info));
-+
-+#ifdef CONFIG_PCI
-+ memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR,
-+ sizeof(ubnt_xm_eeprom_data.eeprom_data));
-+
-+ ath724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data));
-+#endif /* CONFIG_PCI */
-+
-+}
-+
-+MIPS_MACHINE(ATH79_MACH_UBNT_XM,
-+ "UBNT-XM",
-+ "Ubiquiti Networks XM (rev 1.0) board",
-+ ubnt_xm_init);
---- a/arch/mips/ath79/machtypes.h
-+++ b/arch/mips/ath79/machtypes.h
-@@ -19,6 +19,7 @@ enum ath79_mach_type {
- ATH79_MACH_AP121, /* Atheros AP121 reference board */
- ATH79_MACH_AP81, /* Atheros AP81 reference board */
- ATH79_MACH_PB44, /* Atheros PB44 reference board */
-+ ATH79_MACH_UBNT_XM, /* Ubiquiti Networks XM board rev 1.0 */
- };
-
- #endif /* _ATH79_MACHTYPE_H */
+++ /dev/null
-From d3cdd75072bc5df5b18dcafb45cbe9a3a62b840b Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Fri, 18 Nov 2011 00:17:46 +0000
-Subject: [PATCH 19/27] MIPS: ath79: Store the SoC revision in a global variable
-
-Knowing the exact revision of the SoC is required to make runtime decisions
-in various code paths. We have determined the SoC revision already, so we
-only need to store that in a global variable.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Cc: Imre Kaloz <kaloz@openwrt.org>
-Cc: linux-mips@linux-mips.org
-Patchwork: https://patchwork.linux-mips.org/patch/3027/
-Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
----
- arch/mips/ath79/common.c | 1 +
- arch/mips/ath79/setup.c | 2 ++
- arch/mips/include/asm/mach-ath79/ath79.h | 1 +
- 3 files changed, 4 insertions(+), 0 deletions(-)
-
---- a/arch/mips/ath79/common.c
-+++ b/arch/mips/ath79/common.c
-@@ -30,6 +30,7 @@ u32 ath79_ddr_freq;
- EXPORT_SYMBOL_GPL(ath79_ddr_freq);
-
- enum ath79_soc_type ath79_soc;
-+unsigned int ath79_soc_rev;
-
- void __iomem *ath79_pll_base;
- void __iomem *ath79_reset_base;
---- a/arch/mips/ath79/setup.c
-+++ b/arch/mips/ath79/setup.c
-@@ -149,6 +149,8 @@ static void __init ath79_detect_sys_type
- panic("ath79: unknown SoC, id:0x%08x\n", id);
- }
-
-+ ath79_soc_rev = rev;
-+
- sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
- pr_info("SoC: %s\n", ath79_sys_type);
- }
---- a/arch/mips/include/asm/mach-ath79/ath79.h
-+++ b/arch/mips/include/asm/mach-ath79/ath79.h
-@@ -32,6 +32,7 @@ enum ath79_soc_type {
- };
-
- extern enum ath79_soc_type ath79_soc;
-+extern unsigned int ath79_soc_rev;
-
- static inline int soc_is_ar71xx(void)
- {
+++ /dev/null
-From cc2140939233382c1e58abc1d0a1b88fdd6215e6 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Fri, 18 Nov 2011 00:17:53 +0000
-Subject: [PATCH 20/27] MIPS: ath79: Remove 'ar913x' from common variable and function names
-
-The wireless MAC specific variables and the registration code can be shared
-between multiple SoCs. Remove the 'ar913x' part from the function and
-variable names to avoid confusions.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Cc: Imre Kaloz <kaloz@openwrt.org>
-Cc: linux-mips@linux-mips.org
-Patchwork: https://patchwork.linux-mips.org/patch/3028/
-Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
----
- arch/mips/ath79/dev-ar913x-wmac.c | 20 ++++++++++----------
- arch/mips/ath79/dev-ar913x-wmac.h | 8 ++++----
- arch/mips/ath79/mach-ap81.c | 2 +-
- 3 files changed, 15 insertions(+), 15 deletions(-)
-
---- a/arch/mips/ath79/dev-ar913x-wmac.c
-+++ b/arch/mips/ath79/dev-ar913x-wmac.c
-@@ -19,9 +19,9 @@
- #include <asm/mach-ath79/ar71xx_regs.h>
- #include "dev-ar913x-wmac.h"
-
--static struct ath9k_platform_data ar913x_wmac_data;
-+static struct ath9k_platform_data ath79_wmac_data;
-
--static struct resource ar913x_wmac_resources[] = {
-+static struct resource ath79_wmac_resources[] = {
- {
- .start = AR913X_WMAC_BASE,
- .end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1,
-@@ -33,21 +33,21 @@ static struct resource ar913x_wmac_resou
- },
- };
-
--static struct platform_device ar913x_wmac_device = {
-+static struct platform_device ath79_wmac_device = {
- .name = "ath9k",
- .id = -1,
-- .resource = ar913x_wmac_resources,
-- .num_resources = ARRAY_SIZE(ar913x_wmac_resources),
-+ .resource = ath79_wmac_resources,
-+ .num_resources = ARRAY_SIZE(ath79_wmac_resources),
- .dev = {
-- .platform_data = &ar913x_wmac_data,
-+ .platform_data = &ath79_wmac_data,
- },
- };
-
--void __init ath79_register_ar913x_wmac(u8 *cal_data)
-+void __init ath79_register_wmac(u8 *cal_data)
- {
- if (cal_data)
-- memcpy(ar913x_wmac_data.eeprom_data, cal_data,
-- sizeof(ar913x_wmac_data.eeprom_data));
-+ memcpy(ath79_wmac_data.eeprom_data, cal_data,
-+ sizeof(ath79_wmac_data.eeprom_data));
-
- /* reset the WMAC */
- ath79_device_reset_set(AR913X_RESET_AMBA2WMAC);
-@@ -56,5 +56,5 @@ void __init ath79_register_ar913x_wmac(u
- ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC);
- mdelay(10);
-
-- platform_device_register(&ar913x_wmac_device);
-+ platform_device_register(&ath79_wmac_device);
- }
---- a/arch/mips/ath79/dev-ar913x-wmac.h
-+++ b/arch/mips/ath79/dev-ar913x-wmac.h
-@@ -9,9 +9,9 @@
- * by the Free Software Foundation.
- */
-
--#ifndef _ATH79_DEV_AR913X_WMAC_H
--#define _ATH79_DEV_AR913X_WMAC_H
-+#ifndef _ATH79_DEV_WMAC_H
-+#define _ATH79_DEV_WMAC_H
-
--void ath79_register_ar913x_wmac(u8 *cal_data);
-+void ath79_register_wmac(u8 *cal_data);
-
--#endif /* _ATH79_DEV_AR913X_WMAC_H */
-+#endif /* _ATH79_DEV_WMAC_H */
---- a/arch/mips/ath79/mach-ap81.c
-+++ b/arch/mips/ath79/mach-ap81.c
-@@ -92,7 +92,7 @@ static void __init ap81_setup(void)
- ap81_gpio_keys);
- ath79_register_spi(&ap81_spi_data, ap81_spi_info,
- ARRAY_SIZE(ap81_spi_info));
-- ath79_register_ar913x_wmac(cal_data);
-+ ath79_register_wmac(cal_data);
- ath79_register_usb();
- }
-
+++ /dev/null
-From 6e3f244874b8ae660136531b696ad05abe549607 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Fri, 18 Nov 2011 00:17:53 +0000
-Subject: [PATCH 21/27] MIPS: ath79: Separate AR913x SoC specific WMAC setup code
-
-The device registration code can be shared between the different SoCs, but
-the required setup code varies Move AR913x specific setup code into a
-separate function in order to make adding support for another SoCs easier.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Cc: Imre Kaloz <kaloz@openwrt.org>
-Cc: linux-mips@linux-mips.org
-Patchwork: https://patchwork.linux-mips.org/patch/3029/
-Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
----
- arch/mips/ath79/dev-ar913x-wmac.c | 24 +++++++++++++++++-------
- 1 files changed, 17 insertions(+), 7 deletions(-)
-
---- a/arch/mips/ath79/dev-ar913x-wmac.c
-+++ b/arch/mips/ath79/dev-ar913x-wmac.c
-@@ -23,8 +23,7 @@ static struct ath9k_platform_data ath79_
-
- static struct resource ath79_wmac_resources[] = {
- {
-- .start = AR913X_WMAC_BASE,
-- .end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1,
-+ /* .start and .end fields are filled dynamically */
- .flags = IORESOURCE_MEM,
- }, {
- .start = ATH79_CPU_IRQ_IP2,
-@@ -43,12 +42,8 @@ static struct platform_device ath79_wmac
- },
- };
-
--void __init ath79_register_wmac(u8 *cal_data)
-+static void __init ar913x_wmac_setup(void)
- {
-- if (cal_data)
-- memcpy(ath79_wmac_data.eeprom_data, cal_data,
-- sizeof(ath79_wmac_data.eeprom_data));
--
- /* reset the WMAC */
- ath79_device_reset_set(AR913X_RESET_AMBA2WMAC);
- mdelay(10);
-@@ -56,5 +51,20 @@ void __init ath79_register_wmac(u8 *cal_
- ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC);
- mdelay(10);
-
-+ ath79_wmac_resources[0].start = AR913X_WMAC_BASE;
-+ ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1;
-+}
-+
-+void __init ath79_register_wmac(u8 *cal_data)
-+{
-+ if (soc_is_ar913x())
-+ ar913x_wmac_setup();
-+ else
-+ BUG();
-+
-+ if (cal_data)
-+ memcpy(ath79_wmac_data.eeprom_data, cal_data,
-+ sizeof(ath79_wmac_data.eeprom_data));
-+
- platform_device_register(&ath79_wmac_device);
- }
+++ /dev/null
-From e2201a02b529acc65a5a1b19a52b93f9c2d98088 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Fri, 18 Nov 2011 00:17:53 +0000
-Subject: [PATCH 22/27] MIPS: ath79: Add AR933x specific WMAC setup code
-
-The wireless MAC of the AR933x SoCs uses different base address, and
-requires different setup code.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Cc: Imre Kaloz <kaloz@openwrt.org>
-Cc: linux-mips@linux-mips.org
-Patchwork: https://patchwork.linux-mips.org/patch/3030/
-Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
----
- arch/mips/ath79/dev-ar913x-wmac.c | 43 ++++++++++++++++++++++-
- arch/mips/ath79/dev-ar913x-wmac.h | 4 +-
- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 4 ++-
- 3 files changed, 46 insertions(+), 5 deletions(-)
-
---- a/arch/mips/ath79/dev-ar913x-wmac.c
-+++ b/arch/mips/ath79/dev-ar913x-wmac.c
-@@ -1,7 +1,7 @@
- /*
-- * Atheros AR913X SoC built-in WMAC device support
-+ * Atheros AR913X/AR933X SoC built-in WMAC device support
- *
-- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
-+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
-@@ -55,10 +55,49 @@ static void __init ar913x_wmac_setup(voi
- ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1;
- }
-
-+
-+static int ar933x_wmac_reset(void)
-+{
-+ ath79_device_reset_clear(AR933X_RESET_WMAC);
-+ ath79_device_reset_set(AR933X_RESET_WMAC);
-+
-+ return 0;
-+}
-+
-+static int ar933x_r1_get_wmac_revision(void)
-+{
-+ return ath79_soc_rev;
-+}
-+
-+static void __init ar933x_wmac_setup(void)
-+{
-+ u32 t;
-+
-+ ar933x_wmac_reset();
-+
-+ ath79_wmac_device.name = "ar933x_wmac";
-+
-+ ath79_wmac_resources[0].start = AR933X_WMAC_BASE;
-+ ath79_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1;
-+
-+ t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
-+ if (t & AR933X_BOOTSTRAP_REF_CLK_40)
-+ ath79_wmac_data.is_clk_25mhz = false;
-+ else
-+ ath79_wmac_data.is_clk_25mhz = true;
-+
-+ if (ath79_soc_rev == 1)
-+ ath79_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision;
-+
-+ ath79_wmac_data.external_reset = ar933x_wmac_reset;
-+}
-+
- void __init ath79_register_wmac(u8 *cal_data)
- {
- if (soc_is_ar913x())
- ar913x_wmac_setup();
-+ if (soc_is_ar933x())
-+ ar933x_wmac_setup();
- else
- BUG();
-
---- a/arch/mips/ath79/dev-ar913x-wmac.h
-+++ b/arch/mips/ath79/dev-ar913x-wmac.h
-@@ -1,7 +1,7 @@
- /*
-- * Atheros AR913X SoC built-in WMAC device support
-+ * Atheros AR913X/AR933X SoC built-in WMAC device support
- *
-- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
-+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -55,7 +55,8 @@
-
- #define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
- #define AR933X_UART_SIZE 0x14
--
-+#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
-+#define AR933X_WMAC_SIZE 0x20000
- #define AR933X_EHCI_BASE 0x1b000000
- #define AR933X_EHCI_SIZE 0x1000
-
-@@ -233,6 +234,7 @@
- #define AR913X_RESET_USB_HOST BIT(5)
- #define AR913X_RESET_USB_PHY BIT(4)
-
-+#define AR933X_RESET_WMAC BIT(11)
- #define AR933X_RESET_USB_HOST BIT(5)
- #define AR933X_RESET_USB_PHY BIT(4)
- #define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
+++ /dev/null
-From b784c5ab6423d0327d34d08e3532a16a4563e845 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Fri, 18 Nov 2011 00:17:54 +0000
-Subject: [PATCH 23/27] MIPS: ath79: Rename ATH79_DEV_AR913X_WMAC option to ATH79_DEV_WMAC
-
-The ATH79_DEV_AR913X_WMAC option was used to select the AR913x specific
-wireless MAC registration code. The registration code now supports the
-AR933X SoCs as well. Rename the option to reflect the changes.
-
-Also make the new option depends on SOC_AR933X.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Cc: Imre Kaloz <kaloz@openwrt.org>
-Cc: linux-mips@linux-mips.org
-Patchwork: https://patchwork.linux-mips.org/patch/3031/
-Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
----
- arch/mips/ath79/Kconfig | 11 ++++++-----
- arch/mips/ath79/Makefile | 2 +-
- 2 files changed, 7 insertions(+), 6 deletions(-)
-
---- a/arch/mips/ath79/Kconfig
-+++ b/arch/mips/ath79/Kconfig
-@@ -9,6 +9,7 @@ config ATH79_MACH_AP121
- select ATH79_DEV_LEDS_GPIO
- select ATH79_DEV_SPI
- select ATH79_DEV_USB
-+ select ATH79_DEV_WMAC
- help
- Say 'Y' here if you want your kernel to support the
- Atheros AP121 reference board.
-@@ -16,11 +17,11 @@ config ATH79_MACH_AP121
- config ATH79_MACH_AP81
- bool "Atheros AP81 reference board"
- select SOC_AR913X
-- select ATH79_DEV_AR913X_WMAC
- select ATH79_DEV_GPIO_BUTTONS
- select ATH79_DEV_LEDS_GPIO
- select ATH79_DEV_SPI
- select ATH79_DEV_USB
-+ select ATH79_DEV_WMAC
- help
- Say 'Y' here if you want your kernel to support the
- Atheros AP81 reference board.
-@@ -67,10 +68,6 @@ config SOC_AR933X
- select USB_ARCH_HAS_EHCI
- def_bool n
-
--config ATH79_DEV_AR913X_WMAC
-- depends on SOC_AR913X
-- def_bool n
--
- config ATH79_DEV_GPIO_BUTTONS
- def_bool n
-
-@@ -83,4 +80,8 @@ config ATH79_DEV_SPI
- config ATH79_DEV_USB
- def_bool n
-
-+config ATH79_DEV_WMAC
-+ depends on (SOC_AR913X || SOC_AR933X)
-+ def_bool n
-+
- endif
---- a/arch/mips/ath79/Makefile
-+++ b/arch/mips/ath79/Makefile
-@@ -16,11 +16,11 @@ obj-$(CONFIG_EARLY_PRINTK) += early_pri
- # Devices
- #
- obj-y += dev-common.o
--obj-$(CONFIG_ATH79_DEV_AR913X_WMAC) += dev-ar913x-wmac.o
- obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o
- obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o
- obj-$(CONFIG_ATH79_DEV_SPI) += dev-spi.o
- obj-$(CONFIG_ATH79_DEV_USB) += dev-usb.o
-+obj-$(CONFIG_ATH79_DEV_WMAC) += dev-ar913x-wmac.o
-
- #
- # Machines
+++ /dev/null
-From 7091af5ca0aad47826a4e3f699a7985e2d8aa886 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Fri, 18 Nov 2011 00:17:54 +0000
-Subject: [PATCH 24/27] MIPS: ath79: Register the wireless MAC device on the AP121 board
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Cc: Imre Kaloz <kaloz@openwrt.org>
-Cc: linux-mips@linux-mips.org
-Patchwork: https://patchwork.linux-mips.org/patch/3032/
-Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
----
- arch/mips/ath79/mach-ap121.c | 4 ++++
- 1 files changed, 4 insertions(+), 0 deletions(-)
-
---- a/arch/mips/ath79/mach-ap121.c
-+++ b/arch/mips/ath79/mach-ap121.c
-@@ -13,6 +13,7 @@
- #include "dev-leds-gpio.h"
- #include "dev-spi.h"
- #include "dev-usb.h"
-+#include "dev-ar913x-wmac.h"
-
- #define AP121_GPIO_LED_WLAN 0
- #define AP121_GPIO_LED_USB 1
-@@ -73,6 +74,8 @@ static struct ath79_spi_platform_data ap
-
- static void __init ap121_setup(void)
- {
-+ u8 *cal_data = (u8 *) KSEG1ADDR(AP121_CAL_DATA_ADDR);
-+
- ath79_register_leds_gpio(-1, ARRAY_SIZE(ap121_leds_gpio),
- ap121_leds_gpio);
- ath79_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL,
-@@ -82,6 +85,7 @@ static void __init ap121_setup(void)
- ath79_register_spi(&ap121_spi_data, ap121_spi_info,
- ARRAY_SIZE(ap121_spi_info));
- ath79_register_usb();
-+ ath79_register_wmac(cal_data);
- }
-
- MIPS_MACHINE(ATH79_MACH_AP121, "AP121", "Atheros AP121 reference board",
+++ /dev/null
-From ece52fe72b70e35f72edf940233d125257a5f4bc Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Fri, 18 Nov 2011 00:17:54 +0000
-Subject: [PATCH 25/27] MIPS: ath79: Rename dev-ar913x-wmac.h to dev-wmac.h
-
-The 'ar913x' part was removed from the common variable and function names,
-so remove that from the relevant header file name as well.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Cc: Imre Kaloz <kaloz@openwrt.org>
-Cc: linux-mips@linux-mips.org
-Patchwork: https://patchwork.linux-mips.org/patch/3033/
-Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
----
- arch/mips/ath79/dev-ar913x-wmac.c | 2 +-
- arch/mips/ath79/dev-ar913x-wmac.h | 17 -----------------
- arch/mips/ath79/dev-wmac.h | 17 +++++++++++++++++
- arch/mips/ath79/mach-ap121.c | 2 +-
- arch/mips/ath79/mach-ap81.c | 2 +-
- 5 files changed, 20 insertions(+), 20 deletions(-)
- delete mode 100644 arch/mips/ath79/dev-ar913x-wmac.h
- create mode 100644 arch/mips/ath79/dev-wmac.h
-
---- a/arch/mips/ath79/dev-ar913x-wmac.c
-+++ b/arch/mips/ath79/dev-ar913x-wmac.c
-@@ -17,7 +17,7 @@
-
- #include <asm/mach-ath79/ath79.h>
- #include <asm/mach-ath79/ar71xx_regs.h>
--#include "dev-ar913x-wmac.h"
-+#include "dev-wmac.h"
-
- static struct ath9k_platform_data ath79_wmac_data;
-
---- a/arch/mips/ath79/dev-ar913x-wmac.h
-+++ /dev/null
-@@ -1,17 +0,0 @@
--/*
-- * Atheros AR913X/AR933X SoC built-in WMAC device support
-- *
-- * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
-- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-- *
-- * This program is free software; you can redistribute it and/or modify it
-- * under the terms of the GNU General Public License version 2 as published
-- * by the Free Software Foundation.
-- */
--
--#ifndef _ATH79_DEV_WMAC_H
--#define _ATH79_DEV_WMAC_H
--
--void ath79_register_wmac(u8 *cal_data);
--
--#endif /* _ATH79_DEV_WMAC_H */
---- /dev/null
-+++ b/arch/mips/ath79/dev-wmac.h
-@@ -0,0 +1,17 @@
-+/*
-+ * Atheros AR913X/AR933X SoC built-in WMAC device support
-+ *
-+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
-+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+
-+#ifndef _ATH79_DEV_WMAC_H
-+#define _ATH79_DEV_WMAC_H
-+
-+void ath79_register_wmac(u8 *cal_data);
-+
-+#endif /* _ATH79_DEV_WMAC_H */
---- a/arch/mips/ath79/mach-ap121.c
-+++ b/arch/mips/ath79/mach-ap121.c
-@@ -13,7 +13,7 @@
- #include "dev-leds-gpio.h"
- #include "dev-spi.h"
- #include "dev-usb.h"
--#include "dev-ar913x-wmac.h"
-+#include "dev-wmac.h"
-
- #define AP121_GPIO_LED_WLAN 0
- #define AP121_GPIO_LED_USB 1
---- a/arch/mips/ath79/mach-ap81.c
-+++ b/arch/mips/ath79/mach-ap81.c
-@@ -10,7 +10,7 @@
- */
-
- #include "machtypes.h"
--#include "dev-ar913x-wmac.h"
-+#include "dev-wmac.h"
- #include "dev-gpio-buttons.h"
- #include "dev-leds-gpio.h"
- #include "dev-spi.h"
+++ /dev/null
-From c1999a36c113e583f785728b3d8f7a26412c61cd Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Fri, 18 Nov 2011 00:17:54 +0000
-Subject: [PATCH 26/27] MIPS: ath79: Rename dev-ar913x-wmac.c to dev-wmac.c
-
-Rename the file as a last step of the 'ar913x' removal changes.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Cc: Imre Kaloz <kaloz@openwrt.org>
-Cc: linux-mips@linux-mips.org
-Patchwork: https://patchwork.linux-mips.org/patch/3034/
-Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
----
- arch/mips/ath79/Makefile | 2 +-
- arch/mips/ath79/dev-ar913x-wmac.c | 109 -------------------------------------
- arch/mips/ath79/dev-wmac.c | 109 +++++++++++++++++++++++++++++++++++++
- 3 files changed, 110 insertions(+), 110 deletions(-)
- delete mode 100644 arch/mips/ath79/dev-ar913x-wmac.c
- create mode 100644 arch/mips/ath79/dev-wmac.c
-
---- a/arch/mips/ath79/Makefile
-+++ b/arch/mips/ath79/Makefile
-@@ -20,7 +20,7 @@ obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS) +=
- obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o
- obj-$(CONFIG_ATH79_DEV_SPI) += dev-spi.o
- obj-$(CONFIG_ATH79_DEV_USB) += dev-usb.o
--obj-$(CONFIG_ATH79_DEV_WMAC) += dev-ar913x-wmac.o
-+obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wmac.o
-
- #
- # Machines
---- a/arch/mips/ath79/dev-ar913x-wmac.c
-+++ /dev/null
-@@ -1,109 +0,0 @@
--/*
-- * Atheros AR913X/AR933X SoC built-in WMAC device support
-- *
-- * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
-- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-- *
-- * This program is free software; you can redistribute it and/or modify it
-- * under the terms of the GNU General Public License version 2 as published
-- * by the Free Software Foundation.
-- */
--
--#include <linux/init.h>
--#include <linux/delay.h>
--#include <linux/irq.h>
--#include <linux/platform_device.h>
--#include <linux/ath9k_platform.h>
--
--#include <asm/mach-ath79/ath79.h>
--#include <asm/mach-ath79/ar71xx_regs.h>
--#include "dev-wmac.h"
--
--static struct ath9k_platform_data ath79_wmac_data;
--
--static struct resource ath79_wmac_resources[] = {
-- {
-- /* .start and .end fields are filled dynamically */
-- .flags = IORESOURCE_MEM,
-- }, {
-- .start = ATH79_CPU_IRQ_IP2,
-- .end = ATH79_CPU_IRQ_IP2,
-- .flags = IORESOURCE_IRQ,
-- },
--};
--
--static struct platform_device ath79_wmac_device = {
-- .name = "ath9k",
-- .id = -1,
-- .resource = ath79_wmac_resources,
-- .num_resources = ARRAY_SIZE(ath79_wmac_resources),
-- .dev = {
-- .platform_data = &ath79_wmac_data,
-- },
--};
--
--static void __init ar913x_wmac_setup(void)
--{
-- /* reset the WMAC */
-- ath79_device_reset_set(AR913X_RESET_AMBA2WMAC);
-- mdelay(10);
--
-- ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC);
-- mdelay(10);
--
-- ath79_wmac_resources[0].start = AR913X_WMAC_BASE;
-- ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1;
--}
--
--
--static int ar933x_wmac_reset(void)
--{
-- ath79_device_reset_clear(AR933X_RESET_WMAC);
-- ath79_device_reset_set(AR933X_RESET_WMAC);
--
-- return 0;
--}
--
--static int ar933x_r1_get_wmac_revision(void)
--{
-- return ath79_soc_rev;
--}
--
--static void __init ar933x_wmac_setup(void)
--{
-- u32 t;
--
-- ar933x_wmac_reset();
--
-- ath79_wmac_device.name = "ar933x_wmac";
--
-- ath79_wmac_resources[0].start = AR933X_WMAC_BASE;
-- ath79_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1;
--
-- t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
-- if (t & AR933X_BOOTSTRAP_REF_CLK_40)
-- ath79_wmac_data.is_clk_25mhz = false;
-- else
-- ath79_wmac_data.is_clk_25mhz = true;
--
-- if (ath79_soc_rev == 1)
-- ath79_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision;
--
-- ath79_wmac_data.external_reset = ar933x_wmac_reset;
--}
--
--void __init ath79_register_wmac(u8 *cal_data)
--{
-- if (soc_is_ar913x())
-- ar913x_wmac_setup();
-- if (soc_is_ar933x())
-- ar933x_wmac_setup();
-- else
-- BUG();
--
-- if (cal_data)
-- memcpy(ath79_wmac_data.eeprom_data, cal_data,
-- sizeof(ath79_wmac_data.eeprom_data));
--
-- platform_device_register(&ath79_wmac_device);
--}
---- /dev/null
-+++ b/arch/mips/ath79/dev-wmac.c
-@@ -0,0 +1,109 @@
-+/*
-+ * Atheros AR913X/AR933X SoC built-in WMAC device support
-+ *
-+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
-+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/delay.h>
-+#include <linux/irq.h>
-+#include <linux/platform_device.h>
-+#include <linux/ath9k_platform.h>
-+
-+#include <asm/mach-ath79/ath79.h>
-+#include <asm/mach-ath79/ar71xx_regs.h>
-+#include "dev-wmac.h"
-+
-+static struct ath9k_platform_data ath79_wmac_data;
-+
-+static struct resource ath79_wmac_resources[] = {
-+ {
-+ /* .start and .end fields are filled dynamically */
-+ .flags = IORESOURCE_MEM,
-+ }, {
-+ .start = ATH79_CPU_IRQ_IP2,
-+ .end = ATH79_CPU_IRQ_IP2,
-+ .flags = IORESOURCE_IRQ,
-+ },
-+};
-+
-+static struct platform_device ath79_wmac_device = {
-+ .name = "ath9k",
-+ .id = -1,
-+ .resource = ath79_wmac_resources,
-+ .num_resources = ARRAY_SIZE(ath79_wmac_resources),
-+ .dev = {
-+ .platform_data = &ath79_wmac_data,
-+ },
-+};
-+
-+static void __init ar913x_wmac_setup(void)
-+{
-+ /* reset the WMAC */
-+ ath79_device_reset_set(AR913X_RESET_AMBA2WMAC);
-+ mdelay(10);
-+
-+ ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC);
-+ mdelay(10);
-+
-+ ath79_wmac_resources[0].start = AR913X_WMAC_BASE;
-+ ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1;
-+}
-+
-+
-+static int ar933x_wmac_reset(void)
-+{
-+ ath79_device_reset_clear(AR933X_RESET_WMAC);
-+ ath79_device_reset_set(AR933X_RESET_WMAC);
-+
-+ return 0;
-+}
-+
-+static int ar933x_r1_get_wmac_revision(void)
-+{
-+ return ath79_soc_rev;
-+}
-+
-+static void __init ar933x_wmac_setup(void)
-+{
-+ u32 t;
-+
-+ ar933x_wmac_reset();
-+
-+ ath79_wmac_device.name = "ar933x_wmac";
-+
-+ ath79_wmac_resources[0].start = AR933X_WMAC_BASE;
-+ ath79_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1;
-+
-+ t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
-+ if (t & AR933X_BOOTSTRAP_REF_CLK_40)
-+ ath79_wmac_data.is_clk_25mhz = false;
-+ else
-+ ath79_wmac_data.is_clk_25mhz = true;
-+
-+ if (ath79_soc_rev == 1)
-+ ath79_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision;
-+
-+ ath79_wmac_data.external_reset = ar933x_wmac_reset;
-+}
-+
-+void __init ath79_register_wmac(u8 *cal_data)
-+{
-+ if (soc_is_ar913x())
-+ ar913x_wmac_setup();
-+ if (soc_is_ar933x())
-+ ar933x_wmac_setup();
-+ else
-+ BUG();
-+
-+ if (cal_data)
-+ memcpy(ath79_wmac_data.eeprom_data, cal_data,
-+ sizeof(ath79_wmac_data.eeprom_data));
-+
-+ platform_device_register(&ath79_wmac_device);
-+}
+++ /dev/null
-From 156560a512a39284148d556ab96e2e833e816666 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Fri, 23 Dec 2011 19:25:42 +0100
-Subject: [PATCH 27/27] watchdog: ath79_wdt: flush register writes
-
-The watchdog register writes required to have a flush
-in order to commit the values to the register. Without
-the flush, the driver not function correctly on AR934X
-SoCs.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
-Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
----
- drivers/watchdog/ath79_wdt.c | 6 ++++++
- 1 files changed, 6 insertions(+), 0 deletions(-)
-
---- a/drivers/watchdog/ath79_wdt.c
-+++ b/drivers/watchdog/ath79_wdt.c
-@@ -68,17 +68,23 @@ static int max_timeout;
- static inline void ath79_wdt_keepalive(void)
- {
- ath79_reset_wr(AR71XX_RESET_REG_WDOG, wdt_freq * timeout);
-+ /* flush write */
-+ ath79_reset_rr(AR71XX_RESET_REG_WDOG);
- }
-
- static inline void ath79_wdt_enable(void)
- {
- ath79_wdt_keepalive();
- ath79_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_FCR);
-+ /* flush write */
-+ ath79_reset_rr(AR71XX_RESET_REG_WDOG_CTRL);
- }
-
- static inline void ath79_wdt_disable(void)
- {
- ath79_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_NONE);
-+ /* flush write */
-+ ath79_reset_rr(AR71XX_RESET_REG_WDOG_CTRL);
- }
-
- static int ath79_wdt_set_timeout(int val)
+++ /dev/null
-From cf6855546330c3d349d41496975f32255bb6fd07 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Fri, 9 Dec 2011 22:02:57 +0100
-Subject: [PATCH 01/35] MIPS: ath79: avoid a kernel bug on AR913X
-
-Wireless mac registration causes a BUG on AR913X SoCs due to
-a missing 'else'.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
----
- arch/mips/ath79/dev-wmac.c | 2 +-
- 1 files changed, 1 insertions(+), 1 deletions(-)
-
---- a/arch/mips/ath79/dev-wmac.c
-+++ b/arch/mips/ath79/dev-wmac.c
-@@ -96,7 +96,7 @@ void __init ath79_register_wmac(u8 *cal_
- {
- if (soc_is_ar913x())
- ar913x_wmac_setup();
-- if (soc_is_ar933x())
-+ else if (soc_is_ar933x())
- ar933x_wmac_setup();
- else
- BUG();
+++ /dev/null
-From c98b48027516a2e71688a5957e4e0120f4aa8c61 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Fri, 18 Nov 2011 09:47:44 +0100
-Subject: [PATCH 02/35] MIPS: ath79: separate common PCI code
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The 'pcibios_map_irq' and 'pcibios_plat_dev_init'
-are common functions and only instance one of them
-can be present in a single kernel.
-
-Currently these functions can be built only if the
-CONFIG_SOC_AR724X option is selected. However the
-ath79 platform contain support for the AR71XX SoCs,.
-The AR71XX SoCs have a differnet PCI controller,
-and those will require a different code.
-
-Move the common PCI code into a separeate file in
-order to be able to use that with other SoCs as
-well.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Acked-by: René Bolldorf <xsecute@googlemail.com>
-
-v4: - add an Acked-by tag from René
-v3: - no changes
-v2: - no changes
----
- arch/mips/ath79/Makefile | 1 +
- arch/mips/ath79/pci.c | 46 +++++++++++++++++++++++++++++++++++++++++++
- arch/mips/pci/pci-ath724x.c | 34 -------------------------------
- 3 files changed, 47 insertions(+), 34 deletions(-)
- create mode 100644 arch/mips/ath79/pci.c
-
---- a/arch/mips/ath79/Makefile
-+++ b/arch/mips/ath79/Makefile
-@@ -11,6 +11,7 @@
- obj-y := prom.o setup.o irq.o common.o clock.o gpio.o
-
- obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
-+obj-$(CONFIG_PCI) += pci.o
-
- #
- # Devices
---- /dev/null
-+++ b/arch/mips/ath79/pci.c
-@@ -0,0 +1,46 @@
-+/*
-+ * Atheros AR71XX/AR724X specific PCI setup code
-+ *
-+ * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+
-+#include <linux/pci.h>
-+#include <asm/mach-ath79/pci-ath724x.h>
-+
-+static struct ath724x_pci_data *pci_data;
-+static int pci_data_size;
-+
-+void ath724x_pci_add_data(struct ath724x_pci_data *data, int size)
-+{
-+ pci_data = data;
-+ pci_data_size = size;
-+}
-+
-+int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
-+{
-+ unsigned int devfn = dev->devfn;
-+ int irq = -1;
-+
-+ if (devfn > pci_data_size - 1)
-+ return irq;
-+
-+ irq = pci_data[devfn].irq;
-+
-+ return irq;
-+}
-+
-+int pcibios_plat_dev_init(struct pci_dev *dev)
-+{
-+ unsigned int devfn = dev->devfn;
-+
-+ if (devfn > pci_data_size - 1)
-+ return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+ dev->dev.platform_data = pci_data[devfn].pdata;
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
---- a/arch/mips/pci/pci-ath724x.c
-+++ b/arch/mips/pci/pci-ath724x.c
-@@ -9,7 +9,6 @@
- */
-
- #include <linux/pci.h>
--#include <asm/mach-ath79/pci-ath724x.h>
-
- #define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys))
- #define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val))
-@@ -19,8 +18,6 @@
- #define ATH724X_PCI_MEM_SIZE 0x08000000
-
- static DEFINE_SPINLOCK(ath724x_pci_lock);
--static struct ath724x_pci_data *pci_data;
--static int pci_data_size;
-
- static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
- int size, uint32_t *value)
-@@ -133,37 +130,6 @@ static struct pci_controller ath724x_pci
- .mem_resource = &ath724x_mem_resource,
- };
-
--void ath724x_pci_add_data(struct ath724x_pci_data *data, int size)
--{
-- pci_data = data;
-- pci_data_size = size;
--}
--
--int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
--{
-- unsigned int devfn = dev->devfn;
-- int irq = -1;
--
-- if (devfn > pci_data_size - 1)
-- return irq;
--
-- irq = pci_data[devfn].irq;
--
-- return irq;
--}
--
--int pcibios_plat_dev_init(struct pci_dev *dev)
--{
-- unsigned int devfn = dev->devfn;
--
-- if (devfn > pci_data_size - 1)
-- return PCIBIOS_DEVICE_NOT_FOUND;
--
-- dev->dev.platform_data = pci_data[devfn].pdata;
--
-- return PCIBIOS_SUCCESSFUL;
--}
--
- static int __init ath724x_pcibios_init(void)
- {
- register_pci_controller(&ath724x_pci_controller);
+++ /dev/null
-From 204fd70abd99099f6c2e2213a2baa1d51c03a039 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Fri, 18 Nov 2011 09:50:50 +0100
-Subject: [PATCH 03/35] MIPS: ath79: rename pci-ath724x.h
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The declared function in this header file is used by the
-ath79 platform code only. Move the header to the platform
-directory.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Acked-by: René Bolldorf <xsecute@googlemail.com>
-
-v4: - add an Acked-by tag from René
-v3: - move include "pci.h" out of the #ifdef CONFIG_PCI section
-v2: - no changes
----
- arch/mips/ath79/mach-ubnt-xm.c | 2 +-
- arch/mips/ath79/pci.c | 2 +-
- arch/mips/ath79/pci.h | 21 +++++++++++++++++++++
- arch/mips/include/asm/mach-ath79/pci-ath724x.h | 21 ---------------------
- 4 files changed, 23 insertions(+), 23 deletions(-)
- create mode 100644 arch/mips/ath79/pci.h
- delete mode 100644 arch/mips/include/asm/mach-ath79/pci-ath724x.h
-
---- a/arch/mips/ath79/mach-ubnt-xm.c
-+++ b/arch/mips/ath79/mach-ubnt-xm.c
-@@ -15,13 +15,13 @@
-
- #ifdef CONFIG_PCI
- #include <linux/ath9k_platform.h>
--#include <asm/mach-ath79/pci-ath724x.h>
- #endif /* CONFIG_PCI */
-
- #include "machtypes.h"
- #include "dev-gpio-buttons.h"
- #include "dev-leds-gpio.h"
- #include "dev-spi.h"
-+#include "pci.h"
-
- #define UBNT_XM_GPIO_LED_L1 0
- #define UBNT_XM_GPIO_LED_L2 1
---- a/arch/mips/ath79/pci.c
-+++ b/arch/mips/ath79/pci.c
-@@ -9,7 +9,7 @@
- */
-
- #include <linux/pci.h>
--#include <asm/mach-ath79/pci-ath724x.h>
-+#include "pci.h"
-
- static struct ath724x_pci_data *pci_data;
- static int pci_data_size;
---- /dev/null
-+++ b/arch/mips/ath79/pci.h
-@@ -0,0 +1,21 @@
-+/*
-+ * Atheros 724x PCI support
-+ *
-+ * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+
-+#ifndef __ASM_MACH_ATH79_PCI_ATH724X_H
-+#define __ASM_MACH_ATH79_PCI_ATH724X_H
-+
-+struct ath724x_pci_data {
-+ int irq;
-+ void *pdata;
-+};
-+
-+void ath724x_pci_add_data(struct ath724x_pci_data *data, int size);
-+
-+#endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */
---- a/arch/mips/include/asm/mach-ath79/pci-ath724x.h
-+++ /dev/null
-@@ -1,21 +0,0 @@
--/*
-- * Atheros 724x PCI support
-- *
-- * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
-- *
-- * This program is free software; you can redistribute it and/or modify it
-- * under the terms of the GNU General Public License version 2 as published
-- * by the Free Software Foundation.
-- */
--
--#ifndef __ASM_MACH_ATH79_PCI_ATH724X_H
--#define __ASM_MACH_ATH79_PCI_ATH724X_H
--
--struct ath724x_pci_data {
-- int irq;
-- void *pdata;
--};
--
--void ath724x_pci_add_data(struct ath724x_pci_data *data, int size);
--
--#endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */
+++ /dev/null
-From 7e59b95e3424c078de0d75d699433da0dd289fc1 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Fri, 18 Nov 2011 10:13:37 +0100
-Subject: [PATCH 04/35] MIPS: ath79: make ath724x_pcibios_init visible for external code
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: René Bolldorf <xsecute@googlemail.com>
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-
-v4: - add a sob tag
-v3: - no changes
-v2: - fix a typo in my e-mail address
----
- arch/mips/include/asm/mach-ath79/pci.h | 20 ++++++++++++++++++++
- arch/mips/pci/pci-ath724x.c | 3 ++-
- 2 files changed, 22 insertions(+), 1 deletions(-)
- create mode 100644 arch/mips/include/asm/mach-ath79/pci.h
-
---- /dev/null
-+++ b/arch/mips/include/asm/mach-ath79/pci.h
-@@ -0,0 +1,20 @@
-+/*
-+ * Atheros 724x PCI support
-+ *
-+ * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+
-+#ifndef __ASM_MACH_ATH79_PCI_H
-+#define __ASM_MACH_ATH79_PCI_H
-+
-+#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR724X)
-+int ath724x_pcibios_init(void);
-+#else
-+static inline int ath724x_pcibios_init(void) { return 0 };
-+#endif
-+
-+#endif /* __ASM_MACH_ATH79_PCI_H */
---- a/arch/mips/pci/pci-ath724x.c
-+++ b/arch/mips/pci/pci-ath724x.c
-@@ -9,6 +9,7 @@
- */
-
- #include <linux/pci.h>
-+#include <asm/mach-ath79/pci.h>
-
- #define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys))
- #define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val))
-@@ -130,7 +131,7 @@ static struct pci_controller ath724x_pci
- .mem_resource = &ath724x_mem_resource,
- };
-
--static int __init ath724x_pcibios_init(void)
-+int __init ath724x_pcibios_init(void)
- {
- register_pci_controller(&ath724x_pci_controller);
-
+++ /dev/null
-From fbf38a9b03d0c47ed602f090ebb2d8ecc0d51d04 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Fri, 18 Nov 2011 10:25:26 +0100
-Subject: [PATCH 05/35] MIPS: ath79: add a common PCI registration function
-
-The current code unconditionally registers the AR724X
-specific PCI controller, even if the kernel is running
-on a different SoC.
-
-Add a common function for PCI controller registration,
-and only register the AR724X PCI controller if the kernel
-is running on an AR724X SoC.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-
-v4: - simplify ath79_register_pci function
-v3: - fix compile error if CONFIG_PCI is not defined
- - add __init annotation to ath79_register_pci
-v2: - no changes
----
- arch/mips/ath79/mach-ubnt-xm.c | 1 +
- arch/mips/ath79/pci.c | 10 ++++++++++
- arch/mips/ath79/pci.h | 6 ++++++
- arch/mips/pci/pci-ath724x.c | 2 --
- 4 files changed, 17 insertions(+), 2 deletions(-)
-
---- a/arch/mips/ath79/mach-ubnt-xm.c
-+++ b/arch/mips/ath79/mach-ubnt-xm.c
-@@ -111,6 +111,7 @@ static void __init ubnt_xm_init(void)
- ath724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data));
- #endif /* CONFIG_PCI */
-
-+ ath79_register_pci();
- }
-
- MIPS_MACHINE(ATH79_MACH_UBNT_XM,
---- a/arch/mips/ath79/pci.c
-+++ b/arch/mips/ath79/pci.c
-@@ -9,6 +9,8 @@
- */
-
- #include <linux/pci.h>
-+#include <asm/mach-ath79/ath79.h>
-+#include <asm/mach-ath79/pci.h>
- #include "pci.h"
-
- static struct ath724x_pci_data *pci_data;
-@@ -44,3 +46,11 @@ int pcibios_plat_dev_init(struct pci_dev
-
- return PCIBIOS_SUCCESSFUL;
- }
-+
-+int __init ath79_register_pci(void)
-+{
-+ if (soc_is_ar724x())
-+ return ath724x_pcibios_init();
-+
-+ return -ENODEV;
-+}
---- a/arch/mips/ath79/pci.h
-+++ b/arch/mips/ath79/pci.h
-@@ -18,4 +18,10 @@ struct ath724x_pci_data {
-
- void ath724x_pci_add_data(struct ath724x_pci_data *data, int size);
-
-+#ifdef CONFIG_PCI
-+int ath79_register_pci(void);
-+#else
-+static inline int ath79_register_pci(void) { return 0; }
-+#endif
-+
- #endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */
---- a/arch/mips/pci/pci-ath724x.c
-+++ b/arch/mips/pci/pci-ath724x.c
-@@ -137,5 +137,3 @@ int __init ath724x_pcibios_init(void)
-
- return PCIBIOS_SUCCESSFUL;
- }
--
--arch_initcall(ath724x_pcibios_init);
+++ /dev/null
-From 9510a9988638ae2386277a832fab2df8ca37d75a Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Fri, 18 Nov 2011 11:07:26 +0100
-Subject: [PATCH 06/35] MIPS: ath79: rename pci-ath724x.c to make it reflect the real SoC name
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Acked-by: René Bolldorf <xsecute@googlemail.com>
-
-v4: - add an Acked-by tag from René
-v4: - no changes
-v3: - no changes
-v2: - no changes
----
- arch/mips/pci/Makefile | 2 +-
- arch/mips/pci/pci-ar724x.c | 139 +++++++++++++++++++++++++++++++++++++++++++
- arch/mips/pci/pci-ath724x.c | 139 -------------------------------------------
- 3 files changed, 140 insertions(+), 140 deletions(-)
- create mode 100644 arch/mips/pci/pci-ar724x.c
- delete mode 100644 arch/mips/pci/pci-ath724x.c
-
---- a/arch/mips/pci/Makefile
-+++ b/arch/mips/pci/Makefile
-@@ -19,7 +19,7 @@ obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o
- obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \
- ops-bcm63xx.o
- obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o
--obj-$(CONFIG_SOC_AR724X) += pci-ath724x.o
-+obj-$(CONFIG_SOC_AR724X) += pci-ar724x.o
-
- #
- # These are still pretty much in the old state, watch, go blind.
---- /dev/null
-+++ b/arch/mips/pci/pci-ar724x.c
-@@ -0,0 +1,139 @@
-+/*
-+ * Atheros 724x PCI support
-+ *
-+ * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+
-+#include <linux/pci.h>
-+#include <asm/mach-ath79/pci.h>
-+
-+#define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys))
-+#define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val))
-+
-+#define ATH724X_PCI_DEV_BASE 0x14000000
-+#define ATH724X_PCI_MEM_BASE 0x10000000
-+#define ATH724X_PCI_MEM_SIZE 0x08000000
-+
-+static DEFINE_SPINLOCK(ath724x_pci_lock);
-+
-+static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
-+ int size, uint32_t *value)
-+{
-+ unsigned long flags, addr, tval, mask;
-+
-+ if (devfn)
-+ return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+ if (where & (size - 1))
-+ return PCIBIOS_BAD_REGISTER_NUMBER;
-+
-+ spin_lock_irqsave(&ath724x_pci_lock, flags);
-+
-+ switch (size) {
-+ case 1:
-+ addr = where & ~3;
-+ mask = 0xff000000 >> ((where % 4) * 8);
-+ tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
-+ tval = tval & ~mask;
-+ *value = (tval >> ((4 - (where % 4))*8));
-+ break;
-+ case 2:
-+ addr = where & ~3;
-+ mask = 0xffff0000 >> ((where % 4)*8);
-+ tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
-+ tval = tval & ~mask;
-+ *value = (tval >> ((4 - (where % 4))*8));
-+ break;
-+ case 4:
-+ *value = reg_read(ATH724X_PCI_DEV_BASE + where);
-+ break;
-+ default:
-+ spin_unlock_irqrestore(&ath724x_pci_lock, flags);
-+
-+ return PCIBIOS_BAD_REGISTER_NUMBER;
-+ }
-+
-+ spin_unlock_irqrestore(&ath724x_pci_lock, flags);
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
-+ int size, uint32_t value)
-+{
-+ unsigned long flags, tval, addr, mask;
-+
-+ if (devfn)
-+ return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+ if (where & (size - 1))
-+ return PCIBIOS_BAD_REGISTER_NUMBER;
-+
-+ spin_lock_irqsave(&ath724x_pci_lock, flags);
-+
-+ switch (size) {
-+ case 1:
-+ addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
-+ mask = 0xff000000 >> ((where % 4)*8);
-+ tval = reg_read(addr);
-+ tval = tval & ~mask;
-+ tval |= (value << ((4 - (where % 4))*8)) & mask;
-+ reg_write(addr, tval);
-+ break;
-+ case 2:
-+ addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
-+ mask = 0xffff0000 >> ((where % 4)*8);
-+ tval = reg_read(addr);
-+ tval = tval & ~mask;
-+ tval |= (value << ((4 - (where % 4))*8)) & mask;
-+ reg_write(addr, tval);
-+ break;
-+ case 4:
-+ reg_write((ATH724X_PCI_DEV_BASE + where), value);
-+ break;
-+ default:
-+ spin_unlock_irqrestore(&ath724x_pci_lock, flags);
-+
-+ return PCIBIOS_BAD_REGISTER_NUMBER;
-+ }
-+
-+ spin_unlock_irqrestore(&ath724x_pci_lock, flags);
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static struct pci_ops ath724x_pci_ops = {
-+ .read = ath724x_pci_read,
-+ .write = ath724x_pci_write,
-+};
-+
-+static struct resource ath724x_io_resource = {
-+ .name = "PCI IO space",
-+ .start = 0,
-+ .end = 0,
-+ .flags = IORESOURCE_IO,
-+};
-+
-+static struct resource ath724x_mem_resource = {
-+ .name = "PCI memory space",
-+ .start = ATH724X_PCI_MEM_BASE,
-+ .end = ATH724X_PCI_MEM_BASE + ATH724X_PCI_MEM_SIZE - 1,
-+ .flags = IORESOURCE_MEM,
-+};
-+
-+static struct pci_controller ath724x_pci_controller = {
-+ .pci_ops = &ath724x_pci_ops,
-+ .io_resource = &ath724x_io_resource,
-+ .mem_resource = &ath724x_mem_resource,
-+};
-+
-+int __init ath724x_pcibios_init(void)
-+{
-+ register_pci_controller(&ath724x_pci_controller);
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
---- a/arch/mips/pci/pci-ath724x.c
-+++ /dev/null
-@@ -1,139 +0,0 @@
--/*
-- * Atheros 724x PCI support
-- *
-- * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
-- *
-- * This program is free software; you can redistribute it and/or modify it
-- * under the terms of the GNU General Public License version 2 as published
-- * by the Free Software Foundation.
-- */
--
--#include <linux/pci.h>
--#include <asm/mach-ath79/pci.h>
--
--#define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys))
--#define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val))
--
--#define ATH724X_PCI_DEV_BASE 0x14000000
--#define ATH724X_PCI_MEM_BASE 0x10000000
--#define ATH724X_PCI_MEM_SIZE 0x08000000
--
--static DEFINE_SPINLOCK(ath724x_pci_lock);
--
--static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
-- int size, uint32_t *value)
--{
-- unsigned long flags, addr, tval, mask;
--
-- if (devfn)
-- return PCIBIOS_DEVICE_NOT_FOUND;
--
-- if (where & (size - 1))
-- return PCIBIOS_BAD_REGISTER_NUMBER;
--
-- spin_lock_irqsave(&ath724x_pci_lock, flags);
--
-- switch (size) {
-- case 1:
-- addr = where & ~3;
-- mask = 0xff000000 >> ((where % 4) * 8);
-- tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
-- tval = tval & ~mask;
-- *value = (tval >> ((4 - (where % 4))*8));
-- break;
-- case 2:
-- addr = where & ~3;
-- mask = 0xffff0000 >> ((where % 4)*8);
-- tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
-- tval = tval & ~mask;
-- *value = (tval >> ((4 - (where % 4))*8));
-- break;
-- case 4:
-- *value = reg_read(ATH724X_PCI_DEV_BASE + where);
-- break;
-- default:
-- spin_unlock_irqrestore(&ath724x_pci_lock, flags);
--
-- return PCIBIOS_BAD_REGISTER_NUMBER;
-- }
--
-- spin_unlock_irqrestore(&ath724x_pci_lock, flags);
--
-- return PCIBIOS_SUCCESSFUL;
--}
--
--static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
-- int size, uint32_t value)
--{
-- unsigned long flags, tval, addr, mask;
--
-- if (devfn)
-- return PCIBIOS_DEVICE_NOT_FOUND;
--
-- if (where & (size - 1))
-- return PCIBIOS_BAD_REGISTER_NUMBER;
--
-- spin_lock_irqsave(&ath724x_pci_lock, flags);
--
-- switch (size) {
-- case 1:
-- addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
-- mask = 0xff000000 >> ((where % 4)*8);
-- tval = reg_read(addr);
-- tval = tval & ~mask;
-- tval |= (value << ((4 - (where % 4))*8)) & mask;
-- reg_write(addr, tval);
-- break;
-- case 2:
-- addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
-- mask = 0xffff0000 >> ((where % 4)*8);
-- tval = reg_read(addr);
-- tval = tval & ~mask;
-- tval |= (value << ((4 - (where % 4))*8)) & mask;
-- reg_write(addr, tval);
-- break;
-- case 4:
-- reg_write((ATH724X_PCI_DEV_BASE + where), value);
-- break;
-- default:
-- spin_unlock_irqrestore(&ath724x_pci_lock, flags);
--
-- return PCIBIOS_BAD_REGISTER_NUMBER;
-- }
--
-- spin_unlock_irqrestore(&ath724x_pci_lock, flags);
--
-- return PCIBIOS_SUCCESSFUL;
--}
--
--static struct pci_ops ath724x_pci_ops = {
-- .read = ath724x_pci_read,
-- .write = ath724x_pci_write,
--};
--
--static struct resource ath724x_io_resource = {
-- .name = "PCI IO space",
-- .start = 0,
-- .end = 0,
-- .flags = IORESOURCE_IO,
--};
--
--static struct resource ath724x_mem_resource = {
-- .name = "PCI memory space",
-- .start = ATH724X_PCI_MEM_BASE,
-- .end = ATH724X_PCI_MEM_BASE + ATH724X_PCI_MEM_SIZE - 1,
-- .flags = IORESOURCE_MEM,
--};
--
--static struct pci_controller ath724x_pci_controller = {
-- .pci_ops = &ath724x_pci_ops,
-- .io_resource = &ath724x_io_resource,
-- .mem_resource = &ath724x_mem_resource,
--};
--
--int __init ath724x_pcibios_init(void)
--{
-- register_pci_controller(&ath724x_pci_controller);
--
-- return PCIBIOS_SUCCESSFUL;
--}
+++ /dev/null
-From 0cbee5634678ffbd10bee9e302d013392dd8289e Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Fri, 18 Nov 2011 11:16:33 +0100
-Subject: [PATCH 07/35] MIPS: ath79: replace ath724x to ar724x
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Replace the 'ath724x' to 'ar724x' in function, variable and
-structure names to reflect the name of the real SoC.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Acked-by: René Bolldorf <xsecute@googlemail.com>
-
-v4: - add an Acked-by tag from René
- - refreshed due to the changes in a previous patch
-v3: - no changes
-v2: - no changes
----
- arch/mips/ath79/mach-ubnt-xm.c | 4 +-
- arch/mips/ath79/pci.c | 6 ++--
- arch/mips/ath79/pci.h | 10 +++---
- arch/mips/include/asm/mach-ath79/pci.h | 4 +-
- arch/mips/pci/pci-ar724x.c | 62 ++++++++++++++++----------------
- 5 files changed, 43 insertions(+), 43 deletions(-)
-
---- a/arch/mips/ath79/mach-ubnt-xm.c
-+++ b/arch/mips/ath79/mach-ubnt-xm.c
-@@ -84,7 +84,7 @@ static struct ath79_spi_platform_data ub
- #ifdef CONFIG_PCI
- static struct ath9k_platform_data ubnt_xm_eeprom_data;
-
--static struct ath724x_pci_data ubnt_xm_pci_data[] = {
-+static struct ar724x_pci_data ubnt_xm_pci_data[] = {
- {
- .irq = UBNT_XM_PCI_IRQ,
- .pdata = &ubnt_xm_eeprom_data,
-@@ -108,7 +108,7 @@ static void __init ubnt_xm_init(void)
- memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR,
- sizeof(ubnt_xm_eeprom_data.eeprom_data));
-
-- ath724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data));
-+ ar724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data));
- #endif /* CONFIG_PCI */
-
- ath79_register_pci();
---- a/arch/mips/ath79/pci.c
-+++ b/arch/mips/ath79/pci.c
-@@ -13,10 +13,10 @@
- #include <asm/mach-ath79/pci.h>
- #include "pci.h"
-
--static struct ath724x_pci_data *pci_data;
-+static struct ar724x_pci_data *pci_data;
- static int pci_data_size;
-
--void ath724x_pci_add_data(struct ath724x_pci_data *data, int size)
-+void ar724x_pci_add_data(struct ar724x_pci_data *data, int size)
- {
- pci_data = data;
- pci_data_size = size;
-@@ -50,7 +50,7 @@ int pcibios_plat_dev_init(struct pci_dev
- int __init ath79_register_pci(void)
- {
- if (soc_is_ar724x())
-- return ath724x_pcibios_init();
-+ return ar724x_pcibios_init();
-
- return -ENODEV;
- }
---- a/arch/mips/ath79/pci.h
-+++ b/arch/mips/ath79/pci.h
-@@ -8,15 +8,15 @@
- * by the Free Software Foundation.
- */
-
--#ifndef __ASM_MACH_ATH79_PCI_ATH724X_H
--#define __ASM_MACH_ATH79_PCI_ATH724X_H
-+#ifndef _ATH79_PCI_H
-+#define _ATH79_PCI_H
-
--struct ath724x_pci_data {
-+struct ar724x_pci_data {
- int irq;
- void *pdata;
- };
-
--void ath724x_pci_add_data(struct ath724x_pci_data *data, int size);
-+void ar724x_pci_add_data(struct ar724x_pci_data *data, int size);
-
- #ifdef CONFIG_PCI
- int ath79_register_pci(void);
-@@ -24,4 +24,4 @@ int ath79_register_pci(void);
- static inline int ath79_register_pci(void) { return 0; }
- #endif
-
--#endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */
-+#endif /* _ATH79_PCI_H */
---- a/arch/mips/include/asm/mach-ath79/pci.h
-+++ b/arch/mips/include/asm/mach-ath79/pci.h
-@@ -12,9 +12,9 @@
- #define __ASM_MACH_ATH79_PCI_H
-
- #if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR724X)
--int ath724x_pcibios_init(void);
-+int ar724x_pcibios_init(void);
- #else
--static inline int ath724x_pcibios_init(void) { return 0 };
-+static inline int ar724x_pcibios_init(void) { return 0 };
- #endif
-
- #endif /* __ASM_MACH_ATH79_PCI_H */
---- a/arch/mips/pci/pci-ar724x.c
-+++ b/arch/mips/pci/pci-ar724x.c
-@@ -14,13 +14,13 @@
- #define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys))
- #define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val))
-
--#define ATH724X_PCI_DEV_BASE 0x14000000
--#define ATH724X_PCI_MEM_BASE 0x10000000
--#define ATH724X_PCI_MEM_SIZE 0x08000000
-+#define AR724X_PCI_DEV_BASE 0x14000000
-+#define AR724X_PCI_MEM_BASE 0x10000000
-+#define AR724X_PCI_MEM_SIZE 0x08000000
-
--static DEFINE_SPINLOCK(ath724x_pci_lock);
-+static DEFINE_SPINLOCK(ar724x_pci_lock);
-
--static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
-+static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
- int size, uint32_t *value)
- {
- unsigned long flags, addr, tval, mask;
-@@ -31,38 +31,38 @@ static int ath724x_pci_read(struct pci_b
- if (where & (size - 1))
- return PCIBIOS_BAD_REGISTER_NUMBER;
-
-- spin_lock_irqsave(&ath724x_pci_lock, flags);
-+ spin_lock_irqsave(&ar724x_pci_lock, flags);
-
- switch (size) {
- case 1:
- addr = where & ~3;
- mask = 0xff000000 >> ((where % 4) * 8);
-- tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
-+ tval = reg_read(AR724X_PCI_DEV_BASE + addr);
- tval = tval & ~mask;
- *value = (tval >> ((4 - (where % 4))*8));
- break;
- case 2:
- addr = where & ~3;
- mask = 0xffff0000 >> ((where % 4)*8);
-- tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
-+ tval = reg_read(AR724X_PCI_DEV_BASE + addr);
- tval = tval & ~mask;
- *value = (tval >> ((4 - (where % 4))*8));
- break;
- case 4:
-- *value = reg_read(ATH724X_PCI_DEV_BASE + where);
-+ *value = reg_read(AR724X_PCI_DEV_BASE + where);
- break;
- default:
-- spin_unlock_irqrestore(&ath724x_pci_lock, flags);
-+ spin_unlock_irqrestore(&ar724x_pci_lock, flags);
-
- return PCIBIOS_BAD_REGISTER_NUMBER;
- }
-
-- spin_unlock_irqrestore(&ath724x_pci_lock, flags);
-+ spin_unlock_irqrestore(&ar724x_pci_lock, flags);
-
- return PCIBIOS_SUCCESSFUL;
- }
-
--static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
-+static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
- int size, uint32_t value)
- {
- unsigned long flags, tval, addr, mask;
-@@ -73,11 +73,11 @@ static int ath724x_pci_write(struct pci_
- if (where & (size - 1))
- return PCIBIOS_BAD_REGISTER_NUMBER;
-
-- spin_lock_irqsave(&ath724x_pci_lock, flags);
-+ spin_lock_irqsave(&ar724x_pci_lock, flags);
-
- switch (size) {
- case 1:
-- addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
-+ addr = (AR724X_PCI_DEV_BASE + where) & ~3;
- mask = 0xff000000 >> ((where % 4)*8);
- tval = reg_read(addr);
- tval = tval & ~mask;
-@@ -85,7 +85,7 @@ static int ath724x_pci_write(struct pci_
- reg_write(addr, tval);
- break;
- case 2:
-- addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
-+ addr = (AR724X_PCI_DEV_BASE + where) & ~3;
- mask = 0xffff0000 >> ((where % 4)*8);
- tval = reg_read(addr);
- tval = tval & ~mask;
-@@ -93,47 +93,47 @@ static int ath724x_pci_write(struct pci_
- reg_write(addr, tval);
- break;
- case 4:
-- reg_write((ATH724X_PCI_DEV_BASE + where), value);
-+ reg_write((AR724X_PCI_DEV_BASE + where), value);
- break;
- default:
-- spin_unlock_irqrestore(&ath724x_pci_lock, flags);
-+ spin_unlock_irqrestore(&ar724x_pci_lock, flags);
-
- return PCIBIOS_BAD_REGISTER_NUMBER;
- }
-
-- spin_unlock_irqrestore(&ath724x_pci_lock, flags);
-+ spin_unlock_irqrestore(&ar724x_pci_lock, flags);
-
- return PCIBIOS_SUCCESSFUL;
- }
-
--static struct pci_ops ath724x_pci_ops = {
-- .read = ath724x_pci_read,
-- .write = ath724x_pci_write,
-+static struct pci_ops ar724x_pci_ops = {
-+ .read = ar724x_pci_read,
-+ .write = ar724x_pci_write,
- };
-
--static struct resource ath724x_io_resource = {
-+static struct resource ar724x_io_resource = {
- .name = "PCI IO space",
- .start = 0,
- .end = 0,
- .flags = IORESOURCE_IO,
- };
-
--static struct resource ath724x_mem_resource = {
-+static struct resource ar724x_mem_resource = {
- .name = "PCI memory space",
-- .start = ATH724X_PCI_MEM_BASE,
-- .end = ATH724X_PCI_MEM_BASE + ATH724X_PCI_MEM_SIZE - 1,
-+ .start = AR724X_PCI_MEM_BASE,
-+ .end = AR724X_PCI_MEM_BASE + AR724X_PCI_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- };
-
--static struct pci_controller ath724x_pci_controller = {
-- .pci_ops = &ath724x_pci_ops,
-- .io_resource = &ath724x_io_resource,
-- .mem_resource = &ath724x_mem_resource,
-+static struct pci_controller ar724x_pci_controller = {
-+ .pci_ops = &ar724x_pci_ops,
-+ .io_resource = &ar724x_io_resource,
-+ .mem_resource = &ar724x_mem_resource,
- };
-
--int __init ath724x_pcibios_init(void)
-+int __init ar724x_pcibios_init(void)
- {
-- register_pci_controller(&ath724x_pci_controller);
-+ register_pci_controller(&ar724x_pci_controller);
-
- return PCIBIOS_SUCCESSFUL;
- }
+++ /dev/null
-From db464f2ad82c03f847d8eabbb8251b5c567e6720 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Fri, 18 Nov 2011 11:52:41 +0100
-Subject: [PATCH 08/35] MIPS: ath79: use io-accessor macros in pci-ar724x.c
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Acked-by: René Bolldorf <xsecute@googlemail.com>
-
-v4: - add an Acked-by tag from René
-v3: - no changes
-v2: - no changes
----
- arch/mips/pci/pci-ar724x.c | 38 ++++++++++++++++++++++++--------------
- 1 files changed, 24 insertions(+), 14 deletions(-)
-
---- a/arch/mips/pci/pci-ar724x.c
-+++ b/arch/mips/pci/pci-ar724x.c
-@@ -11,19 +11,19 @@
- #include <linux/pci.h>
- #include <asm/mach-ath79/pci.h>
-
--#define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys))
--#define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val))
--
--#define AR724X_PCI_DEV_BASE 0x14000000
-+#define AR724X_PCI_CFG_BASE 0x14000000
-+#define AR724X_PCI_CFG_SIZE 0x1000
- #define AR724X_PCI_MEM_BASE 0x10000000
- #define AR724X_PCI_MEM_SIZE 0x08000000
-
- static DEFINE_SPINLOCK(ar724x_pci_lock);
-+static void __iomem *ar724x_pci_devcfg_base;
-
- static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
- int size, uint32_t *value)
- {
- unsigned long flags, addr, tval, mask;
-+ void __iomem *base;
-
- if (devfn)
- return PCIBIOS_DEVICE_NOT_FOUND;
-@@ -31,25 +31,27 @@ static int ar724x_pci_read(struct pci_bu
- if (where & (size - 1))
- return PCIBIOS_BAD_REGISTER_NUMBER;
-
-+ base = ar724x_pci_devcfg_base;
-+
- spin_lock_irqsave(&ar724x_pci_lock, flags);
-
- switch (size) {
- case 1:
- addr = where & ~3;
- mask = 0xff000000 >> ((where % 4) * 8);
-- tval = reg_read(AR724X_PCI_DEV_BASE + addr);
-+ tval = __raw_readl(base + addr);
- tval = tval & ~mask;
- *value = (tval >> ((4 - (where % 4))*8));
- break;
- case 2:
- addr = where & ~3;
- mask = 0xffff0000 >> ((where % 4)*8);
-- tval = reg_read(AR724X_PCI_DEV_BASE + addr);
-+ tval = __raw_readl(base + addr);
- tval = tval & ~mask;
- *value = (tval >> ((4 - (where % 4))*8));
- break;
- case 4:
-- *value = reg_read(AR724X_PCI_DEV_BASE + where);
-+ *value = __raw_readl(base + where);
- break;
- default:
- spin_unlock_irqrestore(&ar724x_pci_lock, flags);
-@@ -66,6 +68,7 @@ static int ar724x_pci_write(struct pci_b
- int size, uint32_t value)
- {
- unsigned long flags, tval, addr, mask;
-+ void __iomem *base;
-
- if (devfn)
- return PCIBIOS_DEVICE_NOT_FOUND;
-@@ -73,27 +76,29 @@ static int ar724x_pci_write(struct pci_b
- if (where & (size - 1))
- return PCIBIOS_BAD_REGISTER_NUMBER;
-
-+ base = ar724x_pci_devcfg_base;
-+
- spin_lock_irqsave(&ar724x_pci_lock, flags);
-
- switch (size) {
- case 1:
-- addr = (AR724X_PCI_DEV_BASE + where) & ~3;
-+ addr = where & ~3;
- mask = 0xff000000 >> ((where % 4)*8);
-- tval = reg_read(addr);
-+ tval = __raw_readl(base + addr);
- tval = tval & ~mask;
- tval |= (value << ((4 - (where % 4))*8)) & mask;
-- reg_write(addr, tval);
-+ __raw_writel(tval, base + addr);
- break;
- case 2:
-- addr = (AR724X_PCI_DEV_BASE + where) & ~3;
-+ addr = where & ~3;
- mask = 0xffff0000 >> ((where % 4)*8);
-- tval = reg_read(addr);
-+ tval = __raw_readl(base + addr);
- tval = tval & ~mask;
- tval |= (value << ((4 - (where % 4))*8)) & mask;
-- reg_write(addr, tval);
-+ __raw_writel(tval, base + addr);
- break;
- case 4:
-- reg_write((AR724X_PCI_DEV_BASE + where), value);
-+ __raw_writel(value, (base + where));
- break;
- default:
- spin_unlock_irqrestore(&ar724x_pci_lock, flags);
-@@ -133,6 +138,11 @@ static struct pci_controller ar724x_pci_
-
- int __init ar724x_pcibios_init(void)
- {
-+ ar724x_pci_devcfg_base = ioremap(AR724X_PCI_CFG_BASE,
-+ AR724X_PCI_CFG_SIZE);
-+ if (ar724x_pci_devcfg_base == NULL)
-+ return -ENOMEM;
-+
- register_pci_controller(&ar724x_pci_controller);
-
- return PCIBIOS_SUCCESSFUL;
+++ /dev/null
-From 744ffdd4e90cd6671f46eadf9d7cf55b07618d73 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Fri, 18 Nov 2011 21:37:17 +0100
-Subject: [PATCH 09/35] MIPS: ath79: remove superfluous alignment checks from pci-ar724x.c
-
-The alignment of the 'where' parameters are checked
-in the core PCI code already.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-
-v2: - no changes
----
- arch/mips/pci/pci-ar724x.c | 6 ------
- 1 files changed, 0 insertions(+), 6 deletions(-)
-
---- a/arch/mips/pci/pci-ar724x.c
-+++ b/arch/mips/pci/pci-ar724x.c
-@@ -28,9 +28,6 @@ static int ar724x_pci_read(struct pci_bu
- if (devfn)
- return PCIBIOS_DEVICE_NOT_FOUND;
-
-- if (where & (size - 1))
-- return PCIBIOS_BAD_REGISTER_NUMBER;
--
- base = ar724x_pci_devcfg_base;
-
- spin_lock_irqsave(&ar724x_pci_lock, flags);
-@@ -73,9 +70,6 @@ static int ar724x_pci_write(struct pci_b
- if (devfn)
- return PCIBIOS_DEVICE_NOT_FOUND;
-
-- if (where & (size - 1))
-- return PCIBIOS_BAD_REGISTER_NUMBER;
--
- base = ar724x_pci_devcfg_base;
-
- spin_lock_irqsave(&ar724x_pci_lock, flags);
+++ /dev/null
-From 2e535c334018d58b0bf6df583486abda5bfb2003 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Fri, 18 Nov 2011 22:25:30 +0100
-Subject: [PATCH 10/35] MIPS: ath79: fix broken ar724x_pci_{read,write} functions
-
-The current ar724x_pci_{read,write} functions are
-broken. Due to that, pci_read_config_byte returns
-with bogus values, and pci_write_config_{byte,word}
-unconditionally clears the accessed PCI configuration
-registers instead of changing the value of them.
-
-The patch fixes the broken functions, thus the PCI
-configuration space can be accessed correctly.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-
-v2: - no changes
-
-Output of 'lspci -vv' without the patch:
-
-00:00.0 Network controller: Atheros Communications Inc. AR9285 Wireless
-Network Adapter (PCI-Express) (rev 01)
- Subsystem: Atheros Communications Inc. Device a091
- Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
- Latency: 0
- Interrupt: pin A routed to IRQ 0
- Region 0: Memory at 10000000 (64-bit, non-prefetchable) [size=64K]
- Capabilities: [40] Power Management version 3
- Flags: PMEClk- DSI- D1+ D2- AuxCurrent=375mA PME(D0+,D1+,D2-,D3hot+,D3cold-)
- Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
- Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit-
- Address: 00000000 Data: 0000
- Capabilities: [60] Express (v2) Legacy Endpoint, MSI 00
- DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us
- ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop-
- MaxPayload 128 bytes, MaxReadReq 512 bytes
- DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
- LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM unknown, Latency L0 <512ns, L1 <64us
- ClockPM- Surprise- LLActRep- BwNot-
- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk-
- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
- DevCap2: Completion Timeout: Not Supported, TimeoutDis+
- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-
- LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB
- Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
- Compliance De-emphasis: -6dB
- LnkSta2: Current De-emphasis Level: -6dB
-
-Output of 'lspci -vv' with the patch:
-
-00:00.0 Network controller: Atheros Communications Inc. AR9285 Wireless
-Network Adapter (PCI-Express) (rev 01)
- Subsystem: Atheros Communications Inc. Device a091
- Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
- Latency: 0
- Interrupt: pin A routed to IRQ 48
- Region 0: Memory at 10000000 (64-bit, non-prefetchable) [size=64K]
- Capabilities: [40] Power Management version 3
- Flags: PMEClk- DSI- D1+ D2- AuxCurrent=375mA PME(D0+,D1+,D2-,D3hot+,D3cold-)
- Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
- Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit-
- Address: 00000000 Data: 0000
- Capabilities: [60] Express (v2) Legacy Endpoint, MSI 00
- DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us
- ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop-
- MaxPayload 128 bytes, MaxReadReq 512 bytes
- DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
- LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM unknown, Latency L0 <512ns, L1 <64us
- ClockPM- Surprise- LLActRep- BwNot-
- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk-
- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
- DevCap2: Completion Timeout: Not Supported, TimeoutDis+
- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-
- LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB
- Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
- Compliance De-emphasis: -6dB
- LnkSta2: Current De-emphasis Level: -6dB
- Capabilities: [100 v1] Advanced Error Reporting
- UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
- CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
- AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-
- Capabilities: [140 v1] Virtual Channel
- Caps: LPEVC=0 RefClk=100ns PATEntryBits=1
- Arb: Fixed- WRR32- WRR64- WRR128-
- Ctrl: ArbSelect=Fixed
- Status: InProgress-
- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
- Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff
- Status: NegoPending- InProgress-
- Capabilities: [160 v1] Device Serial Number 00-15-17-ff-ff-24-14-12
- Capabilities: [170 v1] Power Budgeting <?>
----
- arch/mips/pci/pci-ar724x.c | 52 ++++++++++++++++++++++----------------------
- 1 files changed, 26 insertions(+), 26 deletions(-)
-
---- a/arch/mips/pci/pci-ar724x.c
-+++ b/arch/mips/pci/pci-ar724x.c
-@@ -22,8 +22,9 @@ static void __iomem *ar724x_pci_devcfg_b
- static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
- int size, uint32_t *value)
- {
-- unsigned long flags, addr, tval, mask;
-+ unsigned long flags;
- void __iomem *base;
-+ u32 data;
-
- if (devfn)
- return PCIBIOS_DEVICE_NOT_FOUND;
-@@ -31,24 +32,22 @@ static int ar724x_pci_read(struct pci_bu
- base = ar724x_pci_devcfg_base;
-
- spin_lock_irqsave(&ar724x_pci_lock, flags);
-+ data = __raw_readl(base + (where & ~3));
-
- switch (size) {
- case 1:
-- addr = where & ~3;
-- mask = 0xff000000 >> ((where % 4) * 8);
-- tval = __raw_readl(base + addr);
-- tval = tval & ~mask;
-- *value = (tval >> ((4 - (where % 4))*8));
-+ if (where & 1)
-+ data >>= 8;
-+ if (where & 2)
-+ data >>= 16;
-+ data &= 0xff;
- break;
- case 2:
-- addr = where & ~3;
-- mask = 0xffff0000 >> ((where % 4)*8);
-- tval = __raw_readl(base + addr);
-- tval = tval & ~mask;
-- *value = (tval >> ((4 - (where % 4))*8));
-+ if (where & 2)
-+ data >>= 16;
-+ data &= 0xffff;
- break;
- case 4:
-- *value = __raw_readl(base + where);
- break;
- default:
- spin_unlock_irqrestore(&ar724x_pci_lock, flags);
-@@ -57,6 +56,7 @@ static int ar724x_pci_read(struct pci_bu
- }
-
- spin_unlock_irqrestore(&ar724x_pci_lock, flags);
-+ *value = data;
-
- return PCIBIOS_SUCCESSFUL;
- }
-@@ -64,8 +64,10 @@ static int ar724x_pci_read(struct pci_bu
- static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
- int size, uint32_t value)
- {
-- unsigned long flags, tval, addr, mask;
-+ unsigned long flags;
- void __iomem *base;
-+ u32 data;
-+ int s;
-
- if (devfn)
- return PCIBIOS_DEVICE_NOT_FOUND;
-@@ -73,26 +75,21 @@ static int ar724x_pci_write(struct pci_b
- base = ar724x_pci_devcfg_base;
-
- spin_lock_irqsave(&ar724x_pci_lock, flags);
-+ data = __raw_readl(base + (where & ~3));
-
- switch (size) {
- case 1:
-- addr = where & ~3;
-- mask = 0xff000000 >> ((where % 4)*8);
-- tval = __raw_readl(base + addr);
-- tval = tval & ~mask;
-- tval |= (value << ((4 - (where % 4))*8)) & mask;
-- __raw_writel(tval, base + addr);
-+ s = ((where & 3) * 8);
-+ data &= ~(0xff << s);
-+ data |= ((value & 0xff) << s);
- break;
- case 2:
-- addr = where & ~3;
-- mask = 0xffff0000 >> ((where % 4)*8);
-- tval = __raw_readl(base + addr);
-- tval = tval & ~mask;
-- tval |= (value << ((4 - (where % 4))*8)) & mask;
-- __raw_writel(tval, base + addr);
-+ s = ((where & 2) * 8);
-+ data &= ~(0xffff << s);
-+ data |= ((value & 0xffff) << s);
- break;
- case 4:
-- __raw_writel(value, (base + where));
-+ data = value;
- break;
- default:
- spin_unlock_irqrestore(&ar724x_pci_lock, flags);
-@@ -100,6 +97,9 @@ static int ar724x_pci_write(struct pci_b
- return PCIBIOS_BAD_REGISTER_NUMBER;
- }
-
-+ __raw_writel(data, base + (where & ~3));
-+ /* flush write */
-+ __raw_readl(base + (where & ~3));
- spin_unlock_irqrestore(&ar724x_pci_lock, flags);
-
- return PCIBIOS_SUCCESSFUL;
+++ /dev/null
-From b2ee3bd8706521c9bbf43405c767010927c101e5 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Mon, 21 Nov 2011 17:57:51 +0100
-Subject: [PATCH 11/35] MIPS: ath79: add a workaround for a PCI controller bug in AR7240 SoCs
-
-The PCI controller of the AR724X SoCs has a hardware
-bag. If the BAR0 register of the PCI device is set to
-the proper base address, the memory address space of
-the device is not accessible.
-
-When the device driver tries to access the memory
-address space of the PCI device, it leads to data
-bus error, similiar to this:
-
-Data bus error, epc == 801f69a0, ra == 801f698c
-Oops[#1]:
-Cpu 0
-$ 0 : 00000000 00000061 deadbeef 000000ff
-$ 4 : 00000000 000000ff 00000014 00000000
-$ 8 : ff000000 fffffffc 00000000 00000000
-$12 : 000001f5 00000006 00000000 6e637920
-$16 : 81ca4000 81ca0260 81ca4000 804d70f0
-$20 : fffffff4 0000002b 803ad4c4 00000000
-$24 : 00000003 00000000
-$28 : 81c20000 81c21c60 00000000 801f698c
-Hi : 00000000
-Lo : 00000000
-epc : 801f69a0 ath9k_hw_init+0xd0/0xa70
- Not tainted
-ra : 801f698c ath9k_hw_init+0xbc/0xa70
-Status: 1000c103 KERNEL EXL IE
-Cause : 1080001c
-PrId : 00019374 (MIPS 24Kc)
-Modules linked in:
-Process swapper (pid: 1, threadinfo=81c20000, task=81c18000, tls=00000000)
-Stack : 00000000 00000000 00000000 00000000 81c21c78 81ca0260 00000000 804d70f0
- 81ca0260 81c21cc0 81ca0e80 81ca0260 81ca4000 804d70f0 fffffff4 0000002b
- 803ad4c4 00000000 00000000 801e3ae8 81c9d080 81ca0e80 b0000000 800b9b9c
- 00000008 81c9d000 8031aeb0 802d38a0 00000000 81c14c00 81c14c60 00000000
- 81ca0e80 81ca0260 b0000000 801f08a4 81c9c820 81c21d48 81c9c820 80144320
- ...
-Call Trace:
-[<801f69a0>] ath9k_hw_init+0xd0/0xa70
-[<801e3ae8>] ath9k_init_device+0x174/0x680
-[<801f08a4>] ath_pci_probe+0x27c/0x380
-[<8019e490>] pci_device_probe+0x74/0x9c
-[<801bfadc>] driver_probe_device+0x9c/0x1b4
-[<801bfcb0>] __driver_attach+0xbc/0xc4
-[<801bea0c>] bus_for_each_dev+0x5c/0x98
-[<801bf394>] bus_add_driver+0x1d0/0x2a4
-[<801c0364>] driver_register+0x8c/0x16c
-[<8019e72c>] __pci_register_driver+0x4c/0xe4
-[<803d3d40>] ath9k_init+0x3c/0x88
-[<80060930>] do_one_initcall+0x3c/0x1cc
-[<803c297c>] kernel_init+0xa4/0x138
-[<80063c04>] kernel_thread_helper+0x10/0x18
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-
-v2: - apply the workaround on AR7240 only
- - remove unrelated defines
----
- arch/mips/pci/pci-ar724x.c | 36 +++++++++++++++++++++++++++++++++++-
- 1 files changed, 35 insertions(+), 1 deletions(-)
-
---- a/arch/mips/pci/pci-ar724x.c
-+++ b/arch/mips/pci/pci-ar724x.c
-@@ -9,6 +9,7 @@
- */
-
- #include <linux/pci.h>
-+#include <asm/mach-ath79/ath79.h>
- #include <asm/mach-ath79/pci.h>
-
- #define AR724X_PCI_CFG_BASE 0x14000000
-@@ -16,9 +17,14 @@
- #define AR724X_PCI_MEM_BASE 0x10000000
- #define AR724X_PCI_MEM_SIZE 0x08000000
-
-+#define AR7240_BAR0_WAR_VALUE 0xffff
-+
- static DEFINE_SPINLOCK(ar724x_pci_lock);
- static void __iomem *ar724x_pci_devcfg_base;
-
-+static u32 ar724x_pci_bar0_value;
-+static bool ar724x_pci_bar0_is_cached;
-+
- static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
- int size, uint32_t *value)
- {
-@@ -56,7 +62,14 @@ static int ar724x_pci_read(struct pci_bu
- }
-
- spin_unlock_irqrestore(&ar724x_pci_lock, flags);
-- *value = data;
-+
-+ if (where == PCI_BASE_ADDRESS_0 && size == 4 &&
-+ ar724x_pci_bar0_is_cached) {
-+ /* use the cached value */
-+ *value = ar724x_pci_bar0_value;
-+ } else {
-+ *value = data;
-+ }
-
- return PCIBIOS_SUCCESSFUL;
- }
-@@ -72,6 +85,27 @@ static int ar724x_pci_write(struct pci_b
- if (devfn)
- return PCIBIOS_DEVICE_NOT_FOUND;
-
-+ if (soc_is_ar7240() && where == PCI_BASE_ADDRESS_0 && size == 4) {
-+ if (value != 0xffffffff) {
-+ /*
-+ * WAR for a hw issue. If the BAR0 register of the
-+ * device is set to the proper base address, the
-+ * memory space of the device is not accessible.
-+ *
-+ * Cache the intended value so it can be read back,
-+ * and write a SoC specific constant value to the
-+ * BAR0 register in order to make the device memory
-+ * accessible.
-+ */
-+ ar724x_pci_bar0_is_cached = true;
-+ ar724x_pci_bar0_value = value;
-+
-+ value = AR7240_BAR0_WAR_VALUE;
-+ } else {
-+ ar724x_pci_bar0_is_cached = false;
-+ }
-+ }
-+
- base = ar724x_pci_devcfg_base;
-
- spin_lock_irqsave(&ar724x_pci_lock, flags);
+++ /dev/null
-From cfb725275ea25857e8f0e3bf358fff7c84cc787c Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Tue, 22 Nov 2011 13:59:39 +0100
-Subject: [PATCH 12/35] MIPS: ath79: fix a wrong IRQ number
-
-The Ubiquiti XM board setup code uses an invalid
-IRQ number, because it if above of NR_IRQS. This
-leads to failed 'request_irq' calls:
-
- ath9k 0000:00:00.0: request_irq failed
- ath9k: probe of 0000:00:00.0 failed with error -22
-
-Preserve some IRQ numbers for the built-in IRQ
-controller of PCI host controllers in the
-AR71XX/AR724X SoCs, and use the correct IRQ
-number in the board setup code.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-
-v2: - no changes
-
-The IRQ controller code is also missing, that will be
-added in a separate patch.
----
- arch/mips/ath79/mach-ubnt-xm.c | 5 +++--
- arch/mips/include/asm/mach-ath79/irq.h | 6 +++++-
- 2 files changed, 8 insertions(+), 3 deletions(-)
-
---- a/arch/mips/ath79/mach-ubnt-xm.c
-+++ b/arch/mips/ath79/mach-ubnt-xm.c
-@@ -17,6 +17,8 @@
- #include <linux/ath9k_platform.h>
- #endif /* CONFIG_PCI */
-
-+#include <asm/mach-ath79/irq.h>
-+
- #include "machtypes.h"
- #include "dev-gpio-buttons.h"
- #include "dev-leds-gpio.h"
-@@ -33,7 +35,6 @@
- #define UBNT_XM_KEYS_POLL_INTERVAL 20
- #define UBNT_XM_KEYS_DEBOUNCE_INTERVAL (3 * UBNT_XM_KEYS_POLL_INTERVAL)
-
--#define UBNT_XM_PCI_IRQ 48
- #define UBNT_XM_EEPROM_ADDR (u8 *) KSEG1ADDR(0x1fff1000)
-
- static struct gpio_led ubnt_xm_leds_gpio[] __initdata = {
-@@ -86,7 +87,7 @@ static struct ath9k_platform_data ubnt_x
-
- static struct ar724x_pci_data ubnt_xm_pci_data[] = {
- {
-- .irq = UBNT_XM_PCI_IRQ,
-+ .irq = ATH79_PCI_IRQ(0),
- .pdata = &ubnt_xm_eeprom_data,
- },
- };
---- a/arch/mips/include/asm/mach-ath79/irq.h
-+++ b/arch/mips/include/asm/mach-ath79/irq.h
-@@ -10,11 +10,15 @@
- #define __ASM_MACH_ATH79_IRQ_H
-
- #define MIPS_CPU_IRQ_BASE 0
--#define NR_IRQS 40
-+#define NR_IRQS 46
-
- #define ATH79_MISC_IRQ_BASE 8
- #define ATH79_MISC_IRQ_COUNT 32
-
-+#define ATH79_PCI_IRQ_BASE (ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT)
-+#define ATH79_PCI_IRQ_COUNT 6
-+#define ATH79_PCI_IRQ(_x) (ATH79_PCI_IRQ_BASE + (_x))
-+
- #define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2)
- #define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3)
- #define ATH79_CPU_IRQ_GE0 (MIPS_CPU_IRQ_BASE + 4)
+++ /dev/null
-From a4fbc2dec67a5d760e25e3c3a6c392191a5405c6 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Tue, 22 Nov 2011 14:11:19 +0100
-Subject: [PATCH 13/35] MIPS: ath79: add PCI IRQ handling code for AR724X SoCs
-
-The PCI Host Controller of the AR724x SoC has a
-built-in IRQ controller. The current code does
-not supports that, so the IRQ lines wired to this
-controller are not usable. This leads to failed
-'request_irq' calls:
-
- ath9k 0000:00:00.0: request_irq failed
- ath9k: probe of 0000:00:00.0 failed with error -89
-
-This patch adds support for the IRQ controller
-in order to make PCI IRQs work.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-
-v2: - move the interrupt controller related defines from
- the workaround patch
----
- arch/mips/ath79/pci.c | 3 +-
- arch/mips/include/asm/mach-ath79/pci.h | 4 +-
- arch/mips/pci/pci-ar724x.c | 118 +++++++++++++++++++++++++++++++-
- 3 files changed, 120 insertions(+), 5 deletions(-)
-
---- a/arch/mips/ath79/pci.c
-+++ b/arch/mips/ath79/pci.c
-@@ -10,6 +10,7 @@
-
- #include <linux/pci.h>
- #include <asm/mach-ath79/ath79.h>
-+#include <asm/mach-ath79/irq.h>
- #include <asm/mach-ath79/pci.h>
- #include "pci.h"
-
-@@ -50,7 +51,7 @@ int pcibios_plat_dev_init(struct pci_dev
- int __init ath79_register_pci(void)
- {
- if (soc_is_ar724x())
-- return ar724x_pcibios_init();
-+ return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2);
-
- return -ENODEV;
- }
---- a/arch/mips/include/asm/mach-ath79/pci.h
-+++ b/arch/mips/include/asm/mach-ath79/pci.h
-@@ -12,9 +12,9 @@
- #define __ASM_MACH_ATH79_PCI_H
-
- #if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR724X)
--int ar724x_pcibios_init(void);
-+int ar724x_pcibios_init(int irq);
- #else
--static inline int ar724x_pcibios_init(void) { return 0 };
-+static inline int ar724x_pcibios_init(int irq) { return 0 };
- #endif
-
- #endif /* __ASM_MACH_ATH79_PCI_H */
---- a/arch/mips/pci/pci-ar724x.c
-+++ b/arch/mips/pci/pci-ar724x.c
-@@ -8,19 +8,32 @@
- * by the Free Software Foundation.
- */
-
-+#include <linux/irq.h>
- #include <linux/pci.h>
- #include <asm/mach-ath79/ath79.h>
-+#include <asm/mach-ath79/ar71xx_regs.h>
- #include <asm/mach-ath79/pci.h>
-
- #define AR724X_PCI_CFG_BASE 0x14000000
- #define AR724X_PCI_CFG_SIZE 0x1000
-+#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000)
-+#define AR724X_PCI_CTRL_SIZE 0x100
-+
- #define AR724X_PCI_MEM_BASE 0x10000000
- #define AR724X_PCI_MEM_SIZE 0x08000000
-
-+#define AR724X_PCI_REG_INT_STATUS 0x4c
-+#define AR724X_PCI_REG_INT_MASK 0x50
-+
-+#define AR724X_PCI_INT_DEV0 BIT(14)
-+
-+#define AR724X_PCI_IRQ_COUNT 1
-+
- #define AR7240_BAR0_WAR_VALUE 0xffff
-
- static DEFINE_SPINLOCK(ar724x_pci_lock);
- static void __iomem *ar724x_pci_devcfg_base;
-+static void __iomem *ar724x_pci_ctrl_base;
-
- static u32 ar724x_pci_bar0_value;
- static bool ar724x_pci_bar0_is_cached;
-@@ -164,14 +177,115 @@ static struct pci_controller ar724x_pci_
- .mem_resource = &ar724x_mem_resource,
- };
-
--int __init ar724x_pcibios_init(void)
-+static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
-+{
-+ void __iomem *base;
-+ u32 pending;
-+
-+ base = ar724x_pci_ctrl_base;
-+
-+ pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) &
-+ __raw_readl(base + AR724X_PCI_REG_INT_MASK);
-+
-+ if (pending & AR724X_PCI_INT_DEV0)
-+ generic_handle_irq(ATH79_PCI_IRQ(0));
-+
-+ else
-+ spurious_interrupt();
-+}
-+
-+static void ar724x_pci_irq_unmask(struct irq_data *d)
-+{
-+ void __iomem *base;
-+ u32 t;
-+
-+ base = ar724x_pci_ctrl_base;
-+
-+ switch (d->irq) {
-+ case ATH79_PCI_IRQ(0):
-+ t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
-+ __raw_writel(t | AR724X_PCI_INT_DEV0,
-+ base + AR724X_PCI_REG_INT_MASK);
-+ /* flush write */
-+ __raw_readl(base + AR724X_PCI_REG_INT_MASK);
-+ }
-+}
-+
-+static void ar724x_pci_irq_mask(struct irq_data *d)
-+{
-+ void __iomem *base;
-+ u32 t;
-+
-+ base = ar724x_pci_ctrl_base;
-+
-+ switch (d->irq) {
-+ case ATH79_PCI_IRQ(0):
-+ t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
-+ __raw_writel(t & ~AR724X_PCI_INT_DEV0,
-+ base + AR724X_PCI_REG_INT_MASK);
-+
-+ /* flush write */
-+ __raw_readl(base + AR724X_PCI_REG_INT_MASK);
-+
-+ t = __raw_readl(base + AR724X_PCI_REG_INT_STATUS);
-+ __raw_writel(t | AR724X_PCI_INT_DEV0,
-+ base + AR724X_PCI_REG_INT_STATUS);
-+
-+ /* flush write */
-+ __raw_readl(base + AR724X_PCI_REG_INT_STATUS);
-+ }
-+}
-+
-+static struct irq_chip ar724x_pci_irq_chip = {
-+ .name = "AR724X PCI ",
-+ .irq_mask = ar724x_pci_irq_mask,
-+ .irq_unmask = ar724x_pci_irq_unmask,
-+ .irq_mask_ack = ar724x_pci_irq_mask,
-+};
-+
-+static void __init ar724x_pci_irq_init(int irq)
-+{
-+ void __iomem *base;
-+ int i;
-+
-+ base = ar724x_pci_ctrl_base;
-+
-+ __raw_writel(0, base + AR724X_PCI_REG_INT_MASK);
-+ __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);
-+
-+ BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR724X_PCI_IRQ_COUNT);
-+
-+ for (i = ATH79_PCI_IRQ_BASE;
-+ i < ATH79_PCI_IRQ_BASE + AR724X_PCI_IRQ_COUNT; i++)
-+ irq_set_chip_and_handler(i, &ar724x_pci_irq_chip,
-+ handle_level_irq);
-+
-+ irq_set_chained_handler(irq, ar724x_pci_irq_handler);
-+}
-+
-+int __init ar724x_pcibios_init(int irq)
- {
-+ int ret;
-+
-+ ret = -ENOMEM;
-+
- ar724x_pci_devcfg_base = ioremap(AR724X_PCI_CFG_BASE,
- AR724X_PCI_CFG_SIZE);
- if (ar724x_pci_devcfg_base == NULL)
-- return -ENOMEM;
-+ goto err;
-
-+ ar724x_pci_ctrl_base = ioremap(AR724X_PCI_CTRL_BASE,
-+ AR724X_PCI_CTRL_SIZE);
-+ if (ar724x_pci_ctrl_base == NULL)
-+ goto err_unmap_devcfg;
-+
-+ ar724x_pci_irq_init(irq);
- register_pci_controller(&ar724x_pci_controller);
-
- return PCIBIOS_SUCCESSFUL;
-+
-+err_unmap_devcfg:
-+ iounmap(ar724x_pci_devcfg_base);
-+err:
-+ return ret;
- }
+++ /dev/null
-From adeefb0860e92f44c7d66d5fccdb217fccfb8a81 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Sun, 20 Nov 2011 10:19:08 +0100
-Subject: [PATCH 14/35] MIPS: ath79: get rid of some ifdefs in mach-ubnt-xm.c
-
-Remove a superfluous ifdef around an include. Also
-reorganize the board setup code a bit, so another
-ifdef can be removed.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-
-v2: - no changes
----
- arch/mips/ath79/mach-ubnt-xm.c | 23 ++++++++++++-----------
- 1 files changed, 12 insertions(+), 11 deletions(-)
-
---- a/arch/mips/ath79/mach-ubnt-xm.c
-+++ b/arch/mips/ath79/mach-ubnt-xm.c
-@@ -12,10 +12,7 @@
-
- #include <linux/init.h>
- #include <linux/pci.h>
--
--#ifdef CONFIG_PCI
- #include <linux/ath9k_platform.h>
--#endif /* CONFIG_PCI */
-
- #include <asm/mach-ath79/irq.h>
-
-@@ -91,6 +88,17 @@ static struct ar724x_pci_data ubnt_xm_pc
- .pdata = &ubnt_xm_eeprom_data,
- },
- };
-+
-+static void __init ubnt_xm_pci_init(void)
-+{
-+ memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR,
-+ sizeof(ubnt_xm_eeprom_data.eeprom_data));
-+
-+ ar724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data));
-+ ath79_register_pci();
-+}
-+#else
-+static inline void ubnt_xm_pci_init(void) {}
- #endif /* CONFIG_PCI */
-
- static void __init ubnt_xm_init(void)
-@@ -105,14 +113,7 @@ static void __init ubnt_xm_init(void)
- ath79_register_spi(&ubnt_xm_spi_data, ubnt_xm_spi_info,
- ARRAY_SIZE(ubnt_xm_spi_info));
-
--#ifdef CONFIG_PCI
-- memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR,
-- sizeof(ubnt_xm_eeprom_data.eeprom_data));
--
-- ar724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data));
--#endif /* CONFIG_PCI */
--
-- ath79_register_pci();
-+ ubnt_xm_pci_init();
- }
-
- MIPS_MACHINE(ATH79_MACH_UBNT_XM,
+++ /dev/null
-From 83d74abc7d549f5d6292b0474be080983239c0bd Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Sun, 20 Nov 2011 10:29:36 +0100
-Subject: [PATCH 15/35] MIPS: ath79: allow to use board specific pci_plat_dev_init functions
-
-Th current implementation causes NULL pointer dereference
-if 'pci_data' is not set:
-
-pci 0000:00:00.0: BAR 0: assigned [mem 0x10000000-0x1000ffff 64bit]
-pci 0000:00:00.0: BAR 0: set to [mem 0x10000000-0x1000ffff 64bit] (PCI
-address [0x10000000-0x1000ffff])
-CPU 0 Unable to handle kernel paging request at virtual address 00000000, epc == 802daca0, ra == 802e78a4
-Oops[#1]:
-Cpu 0
-$ 0 : 00000000 80420000 00000000 00000000
-$ 4 : 00000000 00000000 00000001 00000001
-$ 8 : 00000001 0000032c 81c54700 00000001
-$12 : 0000032d 0000000f 00000000 ffffffff
-$16 : 81c14c00 00000001 802dac74 80195f98
-$20 : 802ea050 00000000 00000000 00000000
-$24 : 00000003 800617f0
-$28 : 81c20000 81c21e70 00000000 802e78a4
-Hi : 00000000
-Lo : 4190ab00
-epc : 802daca0 0x802daca0
- Not tainted
-ra : 802e78a4 0x802e78a4
-Status: 1000c003 KERNEL EXL IE
-Cause : 00800008
-BadVA : 00000000
-PrId : 00019374 (MIPS 24Kc)
-Modules linked in:
-Process swapper (pid: 1, threadinfo=81c20000, task=81c18000, tls=00000000)
-Stack : 00000000 8027d5d8 802e8ae0 00000000 01000000 802e8b5c 81c50600 00000000
- 802ff290 00000000 80420000 802ea0bc 00000000 00000000 80420000 802ff290
- 80420000 80060930 33390000 00000000 00002308 80140a80 00000028 802d0000
- 00000000 800ba024 802ff004 802ff0c8 802ff290 00000000 00000000 00000000
- 00000000 802d897c 01234567 7f827068 00000000 0045f798 00460000 00000000
-
-This can be avoided by calling the 'ar724x_pci_add_data'
-function from the board specific setup code. However it
-makes no sense to use that function for every board,
-especially when the board does not needs to set the
-platform_data field of any PCI device.
-
-The patch allows the board setup code to specify a board
-specific function if that is required.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-
-v2: - no changes
-
-The pci_irq_map function can throw another NULL pointer
-dereference, that will be fixed in a subsequent patch.
----
- arch/mips/ath79/mach-ubnt-xm.c | 13 ++++++++++++-
- arch/mips/ath79/pci.c | 14 ++++++++------
- arch/mips/ath79/pci.h | 4 +++-
- 3 files changed, 23 insertions(+), 8 deletions(-)
-
---- a/arch/mips/ath79/mach-ubnt-xm.c
-+++ b/arch/mips/ath79/mach-ubnt-xm.c
-@@ -85,16 +85,27 @@ static struct ath9k_platform_data ubnt_x
- static struct ar724x_pci_data ubnt_xm_pci_data[] = {
- {
- .irq = ATH79_PCI_IRQ(0),
-- .pdata = &ubnt_xm_eeprom_data,
- },
- };
-
-+static int ubnt_xm_pci_plat_dev_init(struct pci_dev *dev)
-+{
-+ switch (PCI_SLOT(dev->devfn)) {
-+ case 0:
-+ dev->dev.platform_data = &ubnt_xm_eeprom_data;
-+ break;
-+ }
-+
-+ return 0;
-+}
-+
- static void __init ubnt_xm_pci_init(void)
- {
- memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR,
- sizeof(ubnt_xm_eeprom_data.eeprom_data));
-
- ar724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data));
-+ ath79_pci_set_plat_dev_init(ubnt_xm_pci_plat_dev_init);
- ath79_register_pci();
- }
- #else
---- a/arch/mips/ath79/pci.c
-+++ b/arch/mips/ath79/pci.c
-@@ -14,6 +14,7 @@
- #include <asm/mach-ath79/pci.h>
- #include "pci.h"
-
-+static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev);
- static struct ar724x_pci_data *pci_data;
- static int pci_data_size;
-
-@@ -38,14 +39,15 @@ int __init pcibios_map_irq(const struct
-
- int pcibios_plat_dev_init(struct pci_dev *dev)
- {
-- unsigned int devfn = dev->devfn;
--
-- if (devfn > pci_data_size - 1)
-- return PCIBIOS_DEVICE_NOT_FOUND;
-+ if (ath79_pci_plat_dev_init)
-+ return ath79_pci_plat_dev_init(dev);
-
-- dev->dev.platform_data = pci_data[devfn].pdata;
-+ return 0;
-+}
-
-- return PCIBIOS_SUCCESSFUL;
-+void __init ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev))
-+{
-+ ath79_pci_plat_dev_init = func;
- }
-
- int __init ath79_register_pci(void)
---- a/arch/mips/ath79/pci.h
-+++ b/arch/mips/ath79/pci.h
-@@ -13,14 +13,16 @@
-
- struct ar724x_pci_data {
- int irq;
-- void *pdata;
- };
-
- void ar724x_pci_add_data(struct ar724x_pci_data *data, int size);
-
- #ifdef CONFIG_PCI
-+void ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev));
- int ath79_register_pci(void);
- #else
-+static inline void
-+ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *)) {}
- static inline int ath79_register_pci(void) { return 0; }
- #endif
-
+++ /dev/null
-From 9f6d46372cf2a493eaeeffbefe0a796379f838fa Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Tue, 22 Nov 2011 22:54:32 +0100
-Subject: [PATCH 16/35] MIPS: ath79: add support for the PCI host controller of the AR71XX SoCs
-
-The Atheros AR71XX SoCs have a built-in PCI Host Controller.
-This patch adds a driver for that, and modifies the relevant
-files in order to allow to register the PCI controller from
-board specific setup.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
-
-v2: - add missing pci-ar71xx.c
----
- arch/mips/ath79/Kconfig | 1 +
- arch/mips/include/asm/mach-ath79/pci.h | 6 +
- arch/mips/pci/Makefile | 1 +
- arch/mips/pci/pci-ar71xx.c | 375 ++++++++++++++++++++++++++++++++
- 4 files changed, 383 insertions(+), 0 deletions(-)
- create mode 100644 arch/mips/pci/pci-ar71xx.c
-
---- a/arch/mips/ath79/Kconfig
-+++ b/arch/mips/ath79/Kconfig
-@@ -52,6 +52,7 @@ endmenu
- config SOC_AR71XX
- select USB_ARCH_HAS_EHCI
- select USB_ARCH_HAS_OHCI
-+ select HW_HAS_PCI
- def_bool n
-
- config SOC_AR724X
---- a/arch/mips/include/asm/mach-ath79/pci.h
-+++ b/arch/mips/include/asm/mach-ath79/pci.h
-@@ -11,6 +11,12 @@
- #ifndef __ASM_MACH_ATH79_PCI_H
- #define __ASM_MACH_ATH79_PCI_H
-
-+#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR71XX)
-+int ar71xx_pcibios_init(void);
-+#else
-+static inline int ar71xx_pcibios_init(void) { return 0 };
-+#endif
-+
- #if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR724X)
- int ar724x_pcibios_init(int irq);
- #else
---- a/arch/mips/pci/Makefile
-+++ b/arch/mips/pci/Makefile
-@@ -19,6 +19,7 @@ obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o
- obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \
- ops-bcm63xx.o
- obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o
-+obj-$(CONFIG_SOC_AR71XX) += pci-ar71xx.o
- obj-$(CONFIG_SOC_AR724X) += pci-ar724x.o
-
- #
---- /dev/null
-+++ b/arch/mips/pci/pci-ar71xx.c
-@@ -0,0 +1,375 @@
-+/*
-+ * Atheros AR71xx PCI host controller driver
-+ *
-+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
-+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-+ *
-+ * Parts of this file are based on Atheros' 2.6.15 BSP
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+
-+#include <linux/resource.h>
-+#include <linux/types.h>
-+#include <linux/delay.h>
-+#include <linux/bitops.h>
-+#include <linux/pci.h>
-+#include <linux/pci_regs.h>
-+#include <linux/interrupt.h>
-+
-+#include <asm/mach-ath79/ar71xx_regs.h>
-+#include <asm/mach-ath79/ath79.h>
-+#include <asm/mach-ath79/pci.h>
-+
-+#define AR71XX_PCI_MEM_BASE 0x10000000
-+#define AR71XX_PCI_MEM_SIZE 0x08000000
-+
-+#define AR71XX_PCI_WIN0_OFFS 0x10000000
-+#define AR71XX_PCI_WIN1_OFFS 0x11000000
-+#define AR71XX_PCI_WIN2_OFFS 0x12000000
-+#define AR71XX_PCI_WIN3_OFFS 0x13000000
-+#define AR71XX_PCI_WIN4_OFFS 0x14000000
-+#define AR71XX_PCI_WIN5_OFFS 0x15000000
-+#define AR71XX_PCI_WIN6_OFFS 0x16000000
-+#define AR71XX_PCI_WIN7_OFFS 0x07000000
-+
-+#define AR71XX_PCI_CFG_BASE \
-+ (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
-+#define AR71XX_PCI_CFG_SIZE 0x100
-+
-+#define AR71XX_PCI_REG_CRP_AD_CBE 0x00
-+#define AR71XX_PCI_REG_CRP_WRDATA 0x04
-+#define AR71XX_PCI_REG_CRP_RDDATA 0x08
-+#define AR71XX_PCI_REG_CFG_AD 0x0c
-+#define AR71XX_PCI_REG_CFG_CBE 0x10
-+#define AR71XX_PCI_REG_CFG_WRDATA 0x14
-+#define AR71XX_PCI_REG_CFG_RDDATA 0x18
-+#define AR71XX_PCI_REG_PCI_ERR 0x1c
-+#define AR71XX_PCI_REG_PCI_ERR_ADDR 0x20
-+#define AR71XX_PCI_REG_AHB_ERR 0x24
-+#define AR71XX_PCI_REG_AHB_ERR_ADDR 0x28
-+
-+#define AR71XX_PCI_CRP_CMD_WRITE 0x00010000
-+#define AR71XX_PCI_CRP_CMD_READ 0x00000000
-+#define AR71XX_PCI_CFG_CMD_READ 0x0000000a
-+#define AR71XX_PCI_CFG_CMD_WRITE 0x0000000b
-+
-+#define AR71XX_PCI_INT_CORE BIT(4)
-+#define AR71XX_PCI_INT_DEV2 BIT(2)
-+#define AR71XX_PCI_INT_DEV1 BIT(1)
-+#define AR71XX_PCI_INT_DEV0 BIT(0)
-+
-+#define AR71XX_PCI_IRQ_COUNT 5
-+
-+static DEFINE_SPINLOCK(ar71xx_pci_lock);
-+static void __iomem *ar71xx_pcicfg_base;
-+
-+/* Byte lane enable bits */
-+static const u8 ar71xx_pci_ble_table[4][4] = {
-+ {0x0, 0xf, 0xf, 0xf},
-+ {0xe, 0xd, 0xb, 0x7},
-+ {0xc, 0xf, 0x3, 0xf},
-+ {0xf, 0xf, 0xf, 0xf},
-+};
-+
-+static const u32 ar71xx_pci_read_mask[8] = {
-+ 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0
-+};
-+
-+static inline u32 ar71xx_pci_get_ble(int where, int size, int local)
-+{
-+ u32 t;
-+
-+ t = ar71xx_pci_ble_table[size & 3][where & 3];
-+ BUG_ON(t == 0xf);
-+ t <<= (local) ? 20 : 4;
-+
-+ return t;
-+}
-+
-+static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn,
-+ int where)
-+{
-+ u32 ret;
-+
-+ if (!bus->number) {
-+ /* type 0 */
-+ ret = (1 << PCI_SLOT(devfn)) | (PCI_FUNC(devfn) << 8) |
-+ (where & ~3);
-+ } else {
-+ /* type 1 */
-+ ret = (bus->number << 16) | (PCI_SLOT(devfn) << 11) |
-+ (PCI_FUNC(devfn) << 8) | (where & ~3) | 1;
-+ }
-+
-+ return ret;
-+}
-+
-+static int ar71xx_pci_check_error(int quiet)
-+{
-+ void __iomem *base = ar71xx_pcicfg_base;
-+ u32 pci_err;
-+ u32 ahb_err;
-+
-+ pci_err = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR) & 3;
-+ if (pci_err) {
-+ if (!quiet) {
-+ u32 addr;
-+
-+ addr = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR_ADDR);
-+ pr_crit("ar71xx: %s bus error %d at addr 0x%x\n",
-+ "PCI", pci_err, addr);
-+ }
-+
-+ /* clear PCI error status */
-+ __raw_writel(pci_err, base + AR71XX_PCI_REG_PCI_ERR);
-+ }
-+
-+ ahb_err = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR) & 1;
-+ if (ahb_err) {
-+ if (!quiet) {
-+ u32 addr;
-+
-+ addr = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR_ADDR);
-+ pr_crit("ar71xx: %s bus error %d at addr 0x%x\n",
-+ "AHB", ahb_err, addr);
-+ }
-+
-+ /* clear AHB error status */
-+ __raw_writel(ahb_err, base + AR71XX_PCI_REG_AHB_ERR);
-+ }
-+
-+ return !!(ahb_err | pci_err);
-+}
-+
-+static inline void ar71xx_pci_local_write(int where, int size, u32 value)
-+{
-+ void __iomem *base = ar71xx_pcicfg_base;
-+ u32 ad_cbe;
-+
-+ value = value << (8 * (where & 3));
-+
-+ ad_cbe = AR71XX_PCI_CRP_CMD_WRITE | (where & ~3);
-+ ad_cbe |= ar71xx_pci_get_ble(where, size, 1);
-+
-+ __raw_writel(ad_cbe, base + AR71XX_PCI_REG_CRP_AD_CBE);
-+ __raw_writel(value, base + AR71XX_PCI_REG_CRP_WRDATA);
-+}
-+
-+static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus,
-+ unsigned int devfn,
-+ int where, int size, u32 cmd)
-+{
-+ void __iomem *base = ar71xx_pcicfg_base;
-+ u32 addr;
-+
-+ addr = ar71xx_pci_bus_addr(bus, devfn, where);
-+
-+ __raw_writel(addr, base + AR71XX_PCI_REG_CFG_AD);
-+ __raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0),
-+ base + AR71XX_PCI_REG_CFG_CBE);
-+
-+ return ar71xx_pci_check_error(1);
-+}
-+
-+static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
-+ int where, int size, u32 *value)
-+{
-+ void __iomem *base = ar71xx_pcicfg_base;
-+ unsigned long flags;
-+ u32 data;
-+ int err;
-+ int ret;
-+
-+ ret = PCIBIOS_SUCCESSFUL;
-+ data = ~0;
-+
-+ spin_lock_irqsave(&ar71xx_pci_lock, flags);
-+
-+ err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
-+ AR71XX_PCI_CFG_CMD_READ);
-+ if (err)
-+ ret = PCIBIOS_DEVICE_NOT_FOUND;
-+ else
-+ data = __raw_readl(base + AR71XX_PCI_REG_CFG_RDDATA);
-+
-+ spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
-+
-+ *value = (data >> (8 * (where & 3))) & ar71xx_pci_read_mask[size & 7];
-+
-+ return ret;
-+}
-+
-+static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
-+ int where, int size, u32 value)
-+{
-+ void __iomem *base = ar71xx_pcicfg_base;
-+ unsigned long flags;
-+ int err;
-+ int ret;
-+
-+ value = value << (8 * (where & 3));
-+ ret = PCIBIOS_SUCCESSFUL;
-+
-+ spin_lock_irqsave(&ar71xx_pci_lock, flags);
-+
-+ err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
-+ AR71XX_PCI_CFG_CMD_WRITE);
-+ if (err)
-+ ret = PCIBIOS_DEVICE_NOT_FOUND;
-+ else
-+ __raw_writel(value, base + AR71XX_PCI_REG_CFG_WRDATA);
-+
-+ spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
-+
-+ return ret;
-+}
-+
-+static struct pci_ops ar71xx_pci_ops = {
-+ .read = ar71xx_pci_read_config,
-+ .write = ar71xx_pci_write_config,
-+};
-+
-+static struct resource ar71xx_pci_io_resource = {
-+ .name = "PCI IO space",
-+ .start = 0,
-+ .end = 0,
-+ .flags = IORESOURCE_IO,
-+};
-+
-+static struct resource ar71xx_pci_mem_resource = {
-+ .name = "PCI memory space",
-+ .start = AR71XX_PCI_MEM_BASE,
-+ .end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1,
-+ .flags = IORESOURCE_MEM
-+};
-+
-+static struct pci_controller ar71xx_pci_controller = {
-+ .pci_ops = &ar71xx_pci_ops,
-+ .mem_resource = &ar71xx_pci_mem_resource,
-+ .io_resource = &ar71xx_pci_io_resource,
-+};
-+
-+static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
-+{
-+ void __iomem *base = ath79_reset_base;
-+ u32 pending;
-+
-+ pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
-+ __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
-+
-+ if (pending & AR71XX_PCI_INT_DEV0)
-+ generic_handle_irq(ATH79_PCI_IRQ(0));
-+
-+ else if (pending & AR71XX_PCI_INT_DEV1)
-+ generic_handle_irq(ATH79_PCI_IRQ(1));
-+
-+ else if (pending & AR71XX_PCI_INT_DEV2)
-+ generic_handle_irq(ATH79_PCI_IRQ(2));
-+
-+ else if (pending & AR71XX_PCI_INT_CORE)
-+ generic_handle_irq(ATH79_PCI_IRQ(4));
-+
-+ else
-+ spurious_interrupt();
-+}
-+
-+static void ar71xx_pci_irq_unmask(struct irq_data *d)
-+{
-+ unsigned int irq = d->irq - ATH79_PCI_IRQ_BASE;
-+ void __iomem *base = ath79_reset_base;
-+ u32 t;
-+
-+ t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
-+ __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
-+
-+ /* flush write */
-+ __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
-+}
-+
-+static void ar71xx_pci_irq_mask(struct irq_data *d)
-+{
-+ unsigned int irq = d->irq - ATH79_PCI_IRQ_BASE;
-+ void __iomem *base = ath79_reset_base;
-+ u32 t;
-+
-+ t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
-+ __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
-+
-+ /* flush write */
-+ __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
-+}
-+
-+static struct irq_chip ar71xx_pci_irq_chip = {
-+ .name = "AR71XX PCI",
-+ .irq_mask = ar71xx_pci_irq_mask,
-+ .irq_unmask = ar71xx_pci_irq_unmask,
-+ .irq_mask_ack = ar71xx_pci_irq_mask,
-+};
-+
-+static __init void ar71xx_pci_irq_init(void)
-+{
-+ void __iomem *base = ath79_reset_base;
-+ int i;
-+
-+ __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE);
-+ __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS);
-+
-+ BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR71XX_PCI_IRQ_COUNT);
-+
-+ for (i = ATH79_PCI_IRQ_BASE;
-+ i < ATH79_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++)
-+ irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip,
-+ handle_level_irq);
-+
-+ irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar71xx_pci_irq_handler);
-+}
-+
-+static __init void ar71xx_pci_reset(void)
-+{
-+ void __iomem *ddr_base = ath79_ddr_base;
-+
-+ ath79_device_reset_set(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE);
-+ mdelay(100);
-+
-+ ath79_device_reset_clear(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE);
-+ mdelay(100);
-+
-+ __raw_writel(AR71XX_PCI_WIN0_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN0);
-+ __raw_writel(AR71XX_PCI_WIN1_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN1);
-+ __raw_writel(AR71XX_PCI_WIN2_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN2);
-+ __raw_writel(AR71XX_PCI_WIN3_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN3);
-+ __raw_writel(AR71XX_PCI_WIN4_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN4);
-+ __raw_writel(AR71XX_PCI_WIN5_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN5);
-+ __raw_writel(AR71XX_PCI_WIN6_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN6);
-+ __raw_writel(AR71XX_PCI_WIN7_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN7);
-+
-+ mdelay(100);
-+}
-+
-+__init int ar71xx_pcibios_init(void)
-+{
-+ u32 t;
-+
-+ ar71xx_pcicfg_base = ioremap(AR71XX_PCI_CFG_BASE, AR71XX_PCI_CFG_SIZE);
-+ if (ar71xx_pcicfg_base == NULL)
-+ return -ENOMEM;
-+
-+ ar71xx_pci_reset();
-+
-+ /* setup COMMAND register */
-+ t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
-+ | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
-+ ar71xx_pci_local_write(PCI_COMMAND, 4, t);
-+
-+ /* clear bus errors */
-+ ar71xx_pci_check_error(1);
-+
-+ ar71xx_pci_irq_init();
-+
-+ register_pci_controller(&ar71xx_pci_controller);
-+
-+ return 0;
-+}
+++ /dev/null
-From 8a1a5852aa7f8cfc027b2b0bb51cbbac4309e144 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Sun, 20 Nov 2011 14:32:09 +0100
-Subject: [PATCH 17/35] MIPS: ath79: allow to use SoC specific PCI IRQ maps
-
-The PCI controllers in the AR71XX and in the
-AR724X SoCs are different, and both of them
-uses different IRQ wiring.
-
-The patch modifies the 'pcibios_map_irq' function
-in order to allow to use different IRQ maps for
-the different SoCs. The patch also adds a function,
-which lets the board setup code to override the
-default IRQ map.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-
-v2: - no changes
----
- arch/mips/ath79/pci.c | 72 ++++++++++++++++++++++++++++++++++++++++++++++---
- arch/mips/ath79/pci.h | 9 ++++++
- 2 files changed, 77 insertions(+), 4 deletions(-)
-
---- a/arch/mips/ath79/pci.c
-+++ b/arch/mips/ath79/pci.c
-@@ -8,6 +8,7 @@
- * by the Free Software Foundation.
- */
-
-+#include <linux/init.h>
- #include <linux/pci.h>
- #include <asm/mach-ath79/ath79.h>
- #include <asm/mach-ath79/irq.h>
-@@ -15,9 +16,35 @@
- #include "pci.h"
-
- static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev);
-+static const struct ath79_pci_irq *ath79_pci_irq_map __initdata;
-+static unsigned ath79_pci_nr_irqs __initdata;
- static struct ar724x_pci_data *pci_data;
- static int pci_data_size;
-
-+static const struct ath79_pci_irq ar71xx_pci_irq_map[] __initconst = {
-+ {
-+ .slot = 17,
-+ .pin = 1,
-+ .irq = ATH79_PCI_IRQ(0),
-+ }, {
-+ .slot = 18,
-+ .pin = 1,
-+ .irq = ATH79_PCI_IRQ(1),
-+ }, {
-+ .slot = 19,
-+ .pin = 1,
-+ .irq = ATH79_PCI_IRQ(2),
-+ }
-+};
-+
-+static const struct ath79_pci_irq ar724x_pci_irq_map[] __initconst = {
-+ {
-+ .slot = 0,
-+ .pin = 1,
-+ .irq = ATH79_PCI_IRQ(0),
-+ }
-+};
-+
- void ar724x_pci_add_data(struct ar724x_pci_data *data, int size)
- {
- pci_data = data;
-@@ -26,13 +53,40 @@ void ar724x_pci_add_data(struct ar724x_p
-
- int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
- {
-- unsigned int devfn = dev->devfn;
- int irq = -1;
-+ int i;
-
-- if (devfn > pci_data_size - 1)
-- return irq;
--
-- irq = pci_data[devfn].irq;
-+ if (ath79_pci_nr_irqs == 0 ||
-+ ath79_pci_irq_map == NULL) {
-+ if (soc_is_ar71xx()) {
-+ ath79_pci_irq_map = ar71xx_pci_irq_map;
-+ ath79_pci_nr_irqs = ARRAY_SIZE(ar71xx_pci_irq_map);
-+ } else if (soc_is_ar724x()) {
-+ ath79_pci_irq_map = ar724x_pci_irq_map;
-+ ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map);
-+ } else {
-+ pr_crit("pci %s: invalid irq map\n",
-+ pci_name((struct pci_dev *) dev));
-+ return irq;
-+ }
-+ }
-+
-+ for (i = 0; i < ath79_pci_nr_irqs; i++) {
-+ const struct ath79_pci_irq *entry;
-+
-+ entry = &ath79_pci_irq_map[i];
-+ if (entry->slot == slot && entry->pin == pin) {
-+ irq = entry->irq;
-+ break;
-+ }
-+ }
-+
-+ if (irq < 0)
-+ pr_crit("pci %s: no irq found for pin %u\n",
-+ pci_name((struct pci_dev *) dev), pin);
-+ else
-+ pr_info("pci %s: using irq %d for pin %u\n",
-+ pci_name((struct pci_dev *) dev), irq, pin);
-
- return irq;
- }
-@@ -45,6 +99,13 @@ int pcibios_plat_dev_init(struct pci_dev
- return 0;
- }
-
-+void __init ath79_pci_set_irq_map(unsigned nr_irqs,
-+ const struct ath79_pci_irq *map)
-+{
-+ ath79_pci_nr_irqs = nr_irqs;
-+ ath79_pci_irq_map = map;
-+}
-+
- void __init ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev))
- {
- ath79_pci_plat_dev_init = func;
-@@ -52,6 +113,9 @@ void __init ath79_pci_set_plat_dev_init(
-
- int __init ath79_register_pci(void)
- {
-+ if (soc_is_ar71xx())
-+ return ar71xx_pcibios_init();
-+
- if (soc_is_ar724x())
- return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2);
-
---- a/arch/mips/ath79/pci.h
-+++ b/arch/mips/ath79/pci.h
-@@ -15,13 +15,22 @@ struct ar724x_pci_data {
- int irq;
- };
-
-+struct ath79_pci_irq {
-+ u8 slot;
-+ u8 pin;
-+ int irq;
-+};
-+
- void ar724x_pci_add_data(struct ar724x_pci_data *data, int size);
-
- #ifdef CONFIG_PCI
-+void ath79_pci_set_irq_map(unsigned nr_irqs, const struct ath79_pci_irq *map);
- void ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev));
- int ath79_register_pci(void);
- #else
- static inline void
-+ath79_pci_set_irq_map(unsigned nr_irqs, const struct ath79_pci_irq *map) {}
-+static inline void
- ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *)) {}
- static inline int ath79_register_pci(void) { return 0; }
- #endif
+++ /dev/null
-From 0b026adc7a471edd018a060427e62d06e54be2bc Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Sun, 20 Nov 2011 15:50:32 +0100
-Subject: [PATCH 18/35] MIPS: ath79: remove ar724x_pci_add_data function
-
-The variables set by this function are not used anymore.
-Remove the function and the relevant variables as well.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-
-v2: - no changes
----
- arch/mips/ath79/mach-ubnt-xm.c | 7 -------
- arch/mips/ath79/pci.c | 8 --------
- arch/mips/ath79/pci.h | 6 ------
- 3 files changed, 0 insertions(+), 21 deletions(-)
-
---- a/arch/mips/ath79/mach-ubnt-xm.c
-+++ b/arch/mips/ath79/mach-ubnt-xm.c
-@@ -82,12 +82,6 @@ static struct ath79_spi_platform_data ub
- #ifdef CONFIG_PCI
- static struct ath9k_platform_data ubnt_xm_eeprom_data;
-
--static struct ar724x_pci_data ubnt_xm_pci_data[] = {
-- {
-- .irq = ATH79_PCI_IRQ(0),
-- },
--};
--
- static int ubnt_xm_pci_plat_dev_init(struct pci_dev *dev)
- {
- switch (PCI_SLOT(dev->devfn)) {
-@@ -104,7 +98,6 @@ static void __init ubnt_xm_pci_init(void
- memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR,
- sizeof(ubnt_xm_eeprom_data.eeprom_data));
-
-- ar724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data));
- ath79_pci_set_plat_dev_init(ubnt_xm_pci_plat_dev_init);
- ath79_register_pci();
- }
---- a/arch/mips/ath79/pci.c
-+++ b/arch/mips/ath79/pci.c
-@@ -18,8 +18,6 @@
- static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev);
- static const struct ath79_pci_irq *ath79_pci_irq_map __initdata;
- static unsigned ath79_pci_nr_irqs __initdata;
--static struct ar724x_pci_data *pci_data;
--static int pci_data_size;
-
- static const struct ath79_pci_irq ar71xx_pci_irq_map[] __initconst = {
- {
-@@ -45,12 +43,6 @@ static const struct ath79_pci_irq ar724x
- }
- };
-
--void ar724x_pci_add_data(struct ar724x_pci_data *data, int size)
--{
-- pci_data = data;
-- pci_data_size = size;
--}
--
- int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
- {
- int irq = -1;
---- a/arch/mips/ath79/pci.h
-+++ b/arch/mips/ath79/pci.h
-@@ -11,18 +11,12 @@
- #ifndef _ATH79_PCI_H
- #define _ATH79_PCI_H
-
--struct ar724x_pci_data {
-- int irq;
--};
--
- struct ath79_pci_irq {
- u8 slot;
- u8 pin;
- int irq;
- };
-
--void ar724x_pci_add_data(struct ar724x_pci_data *data, int size);
--
- #ifdef CONFIG_PCI
- void ath79_pci_set_irq_map(unsigned nr_irqs, const struct ath79_pci_irq *map);
- void ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev));
+++ /dev/null
-From 1759a5bc87d0eb8dbb0d8a9794b336813057eb88 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Thu, 25 Nov 2010 17:59:28 +0100
-Subject: [PATCH 19/35] MIPS: ath79: register PCI controller on the PB44 board
-
-The PB44 reference board has two miniPCI slots. Register
-the PCI controller to make those usable.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-
-v2: - no changes
----
- arch/mips/ath79/mach-pb44.c | 2 ++
- 1 files changed, 2 insertions(+), 0 deletions(-)
-
---- a/arch/mips/ath79/mach-pb44.c
-+++ b/arch/mips/ath79/mach-pb44.c
-@@ -19,6 +19,7 @@
- #include "dev-leds-gpio.h"
- #include "dev-spi.h"
- #include "dev-usb.h"
-+#include "pci.h"
-
- #define PB44_GPIO_I2C_SCL 0
- #define PB44_GPIO_I2C_SDA 1
-@@ -114,6 +115,7 @@ static void __init pb44_init(void)
- ath79_register_spi(&pb44_spi_data, pb44_spi_info,
- ARRAY_SIZE(pb44_spi_info));
- ath79_register_usb();
-+ ath79_register_pci();
- }
-
- MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board",
+++ /dev/null
-From e83c294ff219ff709b8179cbff64f293199a6dad Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Tue, 22 Nov 2011 21:13:58 +0100
-Subject: [PATCH 20/35] MIPS: ath79: update copyright headers of PCI related files
-
-Add copyright records according to the recent changes in
-the PCI code. Also fix up the descriptions.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
-
-Just in case if someone is curious about why 2008 and 2009 years are
-present in this change:
-
-The recent PCI specific changes were based on an existing
-code which can be found in the OpenWrt repository, and we
-are working on that since 2008.
-
-v2: - no changes
----
- arch/mips/ath79/pci.c | 4 ++++
- arch/mips/ath79/pci.h | 4 +++-
- arch/mips/include/asm/mach-ath79/pci.h | 4 +++-
- arch/mips/pci/pci-ar724x.c | 3 ++-
- 4 files changed, 12 insertions(+), 3 deletions(-)
-
---- a/arch/mips/ath79/pci.c
-+++ b/arch/mips/ath79/pci.c
-@@ -2,6 +2,10 @@
- * Atheros AR71XX/AR724X specific PCI setup code
- *
- * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
-+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
-+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-+ *
-+ * Parts of this file are based on Atheros' 2.6.15 BSP
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
---- a/arch/mips/ath79/pci.h
-+++ b/arch/mips/ath79/pci.h
-@@ -1,7 +1,9 @@
- /*
-- * Atheros 724x PCI support
-+ * Atheros AR71XX/AR724X PCI support
- *
- * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
-+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
-+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
---- a/arch/mips/include/asm/mach-ath79/pci.h
-+++ b/arch/mips/include/asm/mach-ath79/pci.h
-@@ -1,7 +1,9 @@
- /*
-- * Atheros 724x PCI support
-+ * Atheros AR71XX/AR724X PCI support
- *
- * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
-+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
-+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
---- a/arch/mips/pci/pci-ar724x.c
-+++ b/arch/mips/pci/pci-ar724x.c
-@@ -1,7 +1,8 @@
- /*
-- * Atheros 724x PCI support
-+ * Atheros AR724X PCI host controller driver
- *
- * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
-+ * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
+++ /dev/null
-From f60aed87f838ecfa4033ff1f63f97d05359b3b51 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Sun, 11 Dec 2011 17:36:08 +0100
-Subject: [PATCH 21/35] MIPS: ath79: add early_printk support for AR934X
-
-The patch allows to see kernel messages on AR934X SoCs in
-early boot stage.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
----
- arch/mips/ath79/early_printk.c | 3 +++
- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 6 +++++-
- 2 files changed, 8 insertions(+), 1 deletions(-)
-
---- a/arch/mips/ath79/early_printk.c
-+++ b/arch/mips/ath79/early_printk.c
-@@ -71,6 +71,9 @@ static void prom_putchar_init(void)
- case REV_ID_MAJOR_AR7241:
- case REV_ID_MAJOR_AR7242:
- case REV_ID_MAJOR_AR913X:
-+ case REV_ID_MAJOR_AR9341:
-+ case REV_ID_MAJOR_AR9342:
-+ case REV_ID_MAJOR_AR9344:
- _prom_putchar = prom_putchar_ar71xx;
- break;
-
---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -1,10 +1,11 @@
- /*
- * Atheros AR71XX/AR724X/AR913X SoC register definitions
- *
-+ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
-- * Parts of this file are based on Atheros' 2.6.15 BSP
-+ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
-@@ -249,6 +250,9 @@
- #define REV_ID_MAJOR_AR7242 0x1100
- #define REV_ID_MAJOR_AR9330 0x0110
- #define REV_ID_MAJOR_AR9331 0x1110
-+#define REV_ID_MAJOR_AR9341 0x0120
-+#define REV_ID_MAJOR_AR9342 0x1120
-+#define REV_ID_MAJOR_AR9344 0x2120
-
- #define AR71XX_REV_ID_MINOR_MASK 0x3
- #define AR71XX_REV_ID_MINOR_AR7130 0x0
+++ /dev/null
-From 655a57ed2df5e34c32645e08c3244facba70ae5f Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Fri, 9 Dec 2011 14:39:04 +0100
-Subject: [PATCH 22/35] MIPS: ath79: sort case statements in ath79_detect_sys_type
-
-Sort the case statements alphabetically in order to improve
-readability.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
----
- arch/mips/ath79/setup.c | 24 ++++++++++++------------
- 1 files changed, 12 insertions(+), 12 deletions(-)
-
---- a/arch/mips/ath79/setup.c
-+++ b/arch/mips/ath79/setup.c
-@@ -116,18 +116,6 @@ static void __init ath79_detect_sys_type
- rev = id & AR724X_REV_ID_REVISION_MASK;
- break;
-
-- case REV_ID_MAJOR_AR9330:
-- ath79_soc = ATH79_SOC_AR9330;
-- chip = "9330";
-- rev = id & AR933X_REV_ID_REVISION_MASK;
-- break;
--
-- case REV_ID_MAJOR_AR9331:
-- ath79_soc = ATH79_SOC_AR9331;
-- chip = "9331";
-- rev = id & AR933X_REV_ID_REVISION_MASK;
-- break;
--
- case REV_ID_MAJOR_AR913X:
- minor = id & AR913X_REV_ID_MINOR_MASK;
- rev = id >> AR913X_REV_ID_REVISION_SHIFT;
-@@ -145,6 +133,18 @@ static void __init ath79_detect_sys_type
- }
- break;
-
-+ case REV_ID_MAJOR_AR9330:
-+ ath79_soc = ATH79_SOC_AR9330;
-+ chip = "9330";
-+ rev = id & AR933X_REV_ID_REVISION_MASK;
-+ break;
-+
-+ case REV_ID_MAJOR_AR9331:
-+ ath79_soc = ATH79_SOC_AR9331;
-+ chip = "9331";
-+ rev = id & AR933X_REV_ID_REVISION_MASK;
-+ break;
-+
- default:
- panic("ath79: unknown SoC, id:0x%08x\n", id);
- }
+++ /dev/null
-From 9c19e86a7eccf8efd159ba213290830164f33a71 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Sun, 11 Dec 2011 17:36:42 +0100
-Subject: [PATCH 23/35] MIPS: ath79: add SoC detection code for AR934X
-
-Also add 'soc_is_ar934[124x]' helper functions and a Kconfig
-symbol for the AR934X SoCs.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
----
- arch/mips/ath79/Kconfig | 4 ++++
- arch/mips/ath79/setup.c | 21 ++++++++++++++++++++-
- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 2 ++
- arch/mips/include/asm/mach-ath79/ath79.h | 23 +++++++++++++++++++++++
- 4 files changed, 49 insertions(+), 1 deletions(-)
-
---- a/arch/mips/ath79/Kconfig
-+++ b/arch/mips/ath79/Kconfig
-@@ -69,6 +69,10 @@ config SOC_AR933X
- select USB_ARCH_HAS_EHCI
- def_bool n
-
-+config SOC_AR934X
-+ select USB_ARCH_HAS_EHCI
-+ def_bool n
-+
- config ATH79_DEV_GPIO_BUTTONS
- def_bool n
-
---- a/arch/mips/ath79/setup.c
-+++ b/arch/mips/ath79/setup.c
-@@ -1,10 +1,11 @@
- /*
- * Atheros AR71XX/AR724X/AR913X specific setup
- *
-+ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
- * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
-- * Parts of this file are based on Atheros' 2.6.15 BSP
-+ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
-@@ -145,6 +146,24 @@ static void __init ath79_detect_sys_type
- rev = id & AR933X_REV_ID_REVISION_MASK;
- break;
-
-+ case REV_ID_MAJOR_AR9341:
-+ ath79_soc = ATH79_SOC_AR9341;
-+ chip = "9341";
-+ rev = id & AR934X_REV_ID_REVISION_MASK;
-+ break;
-+
-+ case REV_ID_MAJOR_AR9342:
-+ ath79_soc = ATH79_SOC_AR9342;
-+ chip = "9342";
-+ rev = id & AR934X_REV_ID_REVISION_MASK;
-+ break;
-+
-+ case REV_ID_MAJOR_AR9344:
-+ ath79_soc = ATH79_SOC_AR9344;
-+ chip = "9344";
-+ rev = id & AR934X_REV_ID_REVISION_MASK;
-+ break;
-+
- default:
- panic("ath79: unknown SoC, id:0x%08x\n", id);
- }
---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -271,6 +271,8 @@
-
- #define AR724X_REV_ID_REVISION_MASK 0x3
-
-+#define AR934X_REV_ID_REVISION_MASK 0xf
-+
- /*
- * SPI block
- */
---- a/arch/mips/include/asm/mach-ath79/ath79.h
-+++ b/arch/mips/include/asm/mach-ath79/ath79.h
-@@ -29,6 +29,9 @@ enum ath79_soc_type {
- ATH79_SOC_AR9132,
- ATH79_SOC_AR9330,
- ATH79_SOC_AR9331,
-+ ATH79_SOC_AR9341,
-+ ATH79_SOC_AR9342,
-+ ATH79_SOC_AR9344,
- };
-
- extern enum ath79_soc_type ath79_soc;
-@@ -75,6 +78,26 @@ static inline int soc_is_ar933x(void)
- ath79_soc == ATH79_SOC_AR9331);
- }
-
-+static inline int soc_is_ar9341(void)
-+{
-+ return (ath79_soc == ATH79_SOC_AR9341);
-+}
-+
-+static inline int soc_is_ar9342(void)
-+{
-+ return (ath79_soc == ATH79_SOC_AR9342);
-+}
-+
-+static inline int soc_is_ar9344(void)
-+{
-+ return (ath79_soc == ATH79_SOC_AR9344);
-+}
-+
-+static inline int soc_is_ar934x(void)
-+{
-+ return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
-+}
-+
- extern void __iomem *ath79_ddr_base;
- extern void __iomem *ath79_pll_base;
- extern void __iomem *ath79_reset_base;
+++ /dev/null
-From 783addfa256e79892f889e95ec5cda34f4e91eb7 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Fri, 9 Dec 2011 20:36:32 +0100
-Subject: [PATCH 24/35] MIPS: ath79: add clock initialization code for AR934X
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
----
- arch/mips/ath79/clock.c | 81 ++++++++++++++++++++++++
- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 53 +++++++++++++++
- 2 files changed, 134 insertions(+), 0 deletions(-)
-
---- a/arch/mips/ath79/clock.c
-+++ b/arch/mips/ath79/clock.c
-@@ -1,8 +1,11 @@
- /*
- * Atheros AR71XX/AR724X/AR913X common routines
- *
-+ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
- * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
- *
-+ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
-+ *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
-@@ -163,6 +166,82 @@ static void __init ar933x_clocks_init(vo
- ath79_uart_clk.rate = ath79_ref_clk.rate;
- }
-
-+static void __init ar934x_clocks_init(void)
-+{
-+ u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
-+ u32 cpu_pll, ddr_pll;
-+ u32 bootstrap;
-+
-+ bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
-+ if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
-+ ath79_ref_clk.rate = 40 * 1000 * 1000;
-+ else
-+ ath79_ref_clk.rate = 25 * 1000 * 1000;
-+
-+ pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
-+ out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
-+ AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
-+ ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
-+ AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
-+ nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
-+ AR934X_PLL_CPU_CONFIG_NINT_MASK;
-+ frac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
-+ AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
-+
-+ cpu_pll = nint * ath79_ref_clk.rate / ref_div;
-+ cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 6));
-+ cpu_pll /= (1 << out_div);
-+
-+ pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
-+ out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
-+ AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
-+ ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
-+ AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
-+ nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
-+ AR934X_PLL_DDR_CONFIG_NINT_MASK;
-+ frac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
-+ AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
-+
-+ ddr_pll = nint * ath79_ref_clk.rate / ref_div;
-+ ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 10));
-+ ddr_pll /= (1 << out_div);
-+
-+ clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
-+
-+ postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
-+ AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
-+
-+ if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS)
-+ ath79_cpu_clk.rate = ath79_ref_clk.rate;
-+ else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)
-+ ath79_cpu_clk.rate = cpu_pll / (postdiv + 1);
-+ else
-+ ath79_cpu_clk.rate = ddr_pll / (postdiv + 1);
-+
-+ postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &
-+ AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK;
-+
-+ if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS)
-+ ath79_ddr_clk.rate = ath79_ref_clk.rate;
-+ else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL)
-+ ath79_ddr_clk.rate = ddr_pll / (postdiv + 1);
-+ else
-+ ath79_ddr_clk.rate = cpu_pll / (postdiv + 1);
-+
-+ postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &
-+ AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK;
-+
-+ if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS)
-+ ath79_ahb_clk.rate = ath79_ref_clk.rate;
-+ else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
-+ ath79_ahb_clk.rate = ddr_pll / (postdiv + 1);
-+ else
-+ ath79_ahb_clk.rate = cpu_pll / (postdiv + 1);
-+
-+ ath79_wdt_clk.rate = ath79_ref_clk.rate;
-+ ath79_uart_clk.rate = ath79_ref_clk.rate;
-+}
-+
- void __init ath79_clocks_init(void)
- {
- if (soc_is_ar71xx())
-@@ -173,6 +252,8 @@ void __init ath79_clocks_init(void)
- ar913x_clocks_init();
- else if (soc_is_ar933x())
- ar933x_clocks_init();
-+ else if (soc_is_ar934x())
-+ ar934x_clocks_init();
- else
- BUG();
-
---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -151,6 +151,41 @@
- #define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15
- #define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7
-
-+#define AR934X_PLL_CPU_CONFIG_REG 0x00
-+#define AR934X_PLL_DDR_CONFIG_REG 0x04
-+#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
-+
-+#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
-+#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
-+#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6
-+#define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f
-+#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
-+#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
-+#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
-+#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
-+
-+#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
-+#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
-+#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10
-+#define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f
-+#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
-+#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
-+#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
-+#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
-+
-+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
-+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
-+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
-+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5
-+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
-+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10
-+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
-+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15
-+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
-+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
-+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
-+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
-+
- /*
- * USB_CONFIG block
- */
-@@ -186,6 +221,8 @@
- #define AR933X_RESET_REG_RESET_MODULE 0x1c
- #define AR933X_RESET_REG_BOOTSTRAP 0xac
-
-+#define AR934X_RESET_REG_BOOTSTRAP 0xb0
-+
- #define MISC_INT_ETHSW BIT(12)
- #define MISC_INT_TIMER4 BIT(10)
- #define MISC_INT_TIMER3 BIT(9)
-@@ -242,6 +279,22 @@
-
- #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
-
-+#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
-+#define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22)
-+#define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21)
-+#define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20)
-+#define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19)
-+#define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18)
-+#define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17)
-+#define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16)
-+#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7)
-+#define AR934X_BOOTSTRAP_PCIE_RC BIT(6)
-+#define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5)
-+#define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4)
-+#define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2)
-+#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
-+#define AR934X_BOOTSTRAP_DDR1 BIT(0)
-+
- #define REV_ID_MAJOR_MASK 0xfff0
- #define REV_ID_MAJOR_AR71XX 0x00a0
- #define REV_ID_MAJOR_AR913X 0x00b0
+++ /dev/null
-From c01b6005cfa2d762c2de33d5be2e82f91afaa66f Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Fri, 9 Dec 2011 20:53:47 +0100
-Subject: [PATCH 25/35] MIPS: ath79: add GPIO support code for AR934X
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
----
- arch/mips/ath79/gpio.c | 47 +++++++++++++++++++++++-
- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 1 +
- 2 files changed, 47 insertions(+), 1 deletions(-)
-
---- a/arch/mips/ath79/gpio.c
-+++ b/arch/mips/ath79/gpio.c
-@@ -1,9 +1,12 @@
- /*
- * Atheros AR71XX/AR724X/AR913X GPIO API support
- *
-- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
-+ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
-+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
-+ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
-+ *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
-@@ -89,6 +92,42 @@ static int ath79_gpio_direction_output(s
- return 0;
- }
-
-+static int ar934x_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
-+{
-+ void __iomem *base = ath79_gpio_base;
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&ath79_gpio_lock, flags);
-+
-+ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << offset),
-+ base + AR71XX_GPIO_REG_OE);
-+
-+ spin_unlock_irqrestore(&ath79_gpio_lock, flags);
-+
-+ return 0;
-+}
-+
-+static int ar934x_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
-+ int value)
-+{
-+ void __iomem *base = ath79_gpio_base;
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&ath79_gpio_lock, flags);
-+
-+ if (value)
-+ __raw_writel(1 << offset, base + AR71XX_GPIO_REG_SET);
-+ else
-+ __raw_writel(1 << offset, base + AR71XX_GPIO_REG_CLEAR);
-+
-+ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << offset),
-+ base + AR71XX_GPIO_REG_OE);
-+
-+ spin_unlock_irqrestore(&ath79_gpio_lock, flags);
-+
-+ return 0;
-+}
-+
- static struct gpio_chip ath79_gpio_chip = {
- .label = "ath79",
- .get = ath79_gpio_get_value,
-@@ -155,11 +194,17 @@ void __init ath79_gpio_init(void)
- ath79_gpio_count = AR913X_GPIO_COUNT;
- else if (soc_is_ar933x())
- ath79_gpio_count = AR933X_GPIO_COUNT;
-+ else if (soc_is_ar934x())
-+ ath79_gpio_count = AR934X_GPIO_COUNT;
- else
- BUG();
-
- ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
- ath79_gpio_chip.ngpio = ath79_gpio_count;
-+ if (soc_is_ar934x()) {
-+ ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
-+ ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
-+ }
-
- err = gpiochip_add(&ath79_gpio_chip);
- if (err)
---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -367,5 +367,6 @@
- #define AR724X_GPIO_COUNT 18
- #define AR913X_GPIO_COUNT 22
- #define AR933X_GPIO_COUNT 30
-+#define AR934X_GPIO_COUNT 23
-
- #endif /* __ASM_MACH_AR71XX_REGS_H */
+++ /dev/null
-From e69d89040d4884ea4069352338f555694e65fe70 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Fri, 9 Dec 2011 21:30:03 +0100
-Subject: [PATCH 26/35] MIPS: ath79: rework IP2/IP3 interrupt handling
-
-The current implementation assumes that flushing the
-DDR writeback buffer is required for IP2/IP3 interrupts,
-however this is not true for all SoCs.
-
-Use SoC specific IP2/IP3 handlers instead of flushing
-the buffers in the dispatcher code.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
----
- arch/mips/ath79/irq.c | 92 ++++++++++++++++++++++++++++++++++++++-----------
- 1 files changed, 72 insertions(+), 20 deletions(-)
-
---- a/arch/mips/ath79/irq.c
-+++ b/arch/mips/ath79/irq.c
-@@ -1,7 +1,7 @@
- /*
- * Atheros AR71xx/AR724x/AR913x specific interrupt handling
- *
-- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
-+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- * Parts of this file are based on Atheros' 2.6.15 BSP
-@@ -23,8 +23,8 @@
- #include <asm/mach-ath79/ar71xx_regs.h>
- #include "common.h"
-
--static unsigned int ath79_ip2_flush_reg;
--static unsigned int ath79_ip3_flush_reg;
-+static void (*ath79_ip2_handler)(void);
-+static void (*ath79_ip3_handler)(void);
-
- static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
- {
-@@ -152,10 +152,8 @@ asmlinkage void plat_irq_dispatch(void)
- if (pending & STATUSF_IP7)
- do_IRQ(ATH79_CPU_IRQ_TIMER);
-
-- else if (pending & STATUSF_IP2) {
-- ath79_ddr_wb_flush(ath79_ip2_flush_reg);
-- do_IRQ(ATH79_CPU_IRQ_IP2);
-- }
-+ else if (pending & STATUSF_IP2)
-+ ath79_ip2_handler();
-
- else if (pending & STATUSF_IP4)
- do_IRQ(ATH79_CPU_IRQ_GE0);
-@@ -163,10 +161,8 @@ asmlinkage void plat_irq_dispatch(void)
- else if (pending & STATUSF_IP5)
- do_IRQ(ATH79_CPU_IRQ_GE1);
-
-- else if (pending & STATUSF_IP3) {
-- ath79_ddr_wb_flush(ath79_ip3_flush_reg);
-- do_IRQ(ATH79_CPU_IRQ_USB);
-- }
-+ else if (pending & STATUSF_IP3)
-+ ath79_ip3_handler();
-
- else if (pending & STATUSF_IP6)
- do_IRQ(ATH79_CPU_IRQ_MISC);
-@@ -175,22 +171,78 @@ asmlinkage void plat_irq_dispatch(void)
- spurious_interrupt();
- }
-
-+/*
-+ * The IP2/IP3 lines are tied to a PCI/WMAC/USB device. Drivers for
-+ * these devices typically allocate coherent DMA memory, however the
-+ * DMA controller may still have some unsynchronized data in the FIFO.
-+ * Issue a flush in the handlers to ensure that the driver sees
-+ * the update.
-+ */
-+static void ar71xx_ip2_handler(void)
-+{
-+ ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_PCI);
-+ do_IRQ(ATH79_CPU_IRQ_IP2);
-+}
-+
-+static void ar724x_ip2_handler(void)
-+{
-+ ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_PCIE);
-+ do_IRQ(ATH79_CPU_IRQ_IP2);
-+}
-+
-+static void ar913x_ip2_handler(void)
-+{
-+ ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_WMAC);
-+ do_IRQ(ATH79_CPU_IRQ_IP2);
-+}
-+
-+static void ar933x_ip2_handler(void)
-+{
-+ ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_WMAC);
-+ do_IRQ(ATH79_CPU_IRQ_IP2);
-+}
-+
-+static void ar71xx_ip3_handler(void)
-+{
-+ ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB);
-+ do_IRQ(ATH79_CPU_IRQ_USB);
-+}
-+
-+static void ar724x_ip3_handler(void)
-+{
-+ ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_USB);
-+ do_IRQ(ATH79_CPU_IRQ_USB);
-+}
-+
-+static void ar913x_ip3_handler(void)
-+{
-+ ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_USB);
-+ do_IRQ(ATH79_CPU_IRQ_USB);
-+}
-+
-+static void ar933x_ip3_handler(void)
-+{
-+ ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_USB);
-+ do_IRQ(ATH79_CPU_IRQ_USB);
-+}
-+
- void __init arch_init_irq(void)
- {
- if (soc_is_ar71xx()) {
-- ath79_ip2_flush_reg = AR71XX_DDR_REG_FLUSH_PCI;
-- ath79_ip3_flush_reg = AR71XX_DDR_REG_FLUSH_USB;
-+ ath79_ip2_handler = ar71xx_ip2_handler;
-+ ath79_ip3_handler = ar71xx_ip3_handler;
- } else if (soc_is_ar724x()) {
-- ath79_ip2_flush_reg = AR724X_DDR_REG_FLUSH_PCIE;
-- ath79_ip3_flush_reg = AR724X_DDR_REG_FLUSH_USB;
-+ ath79_ip2_handler = ar724x_ip2_handler;
-+ ath79_ip3_handler = ar724x_ip3_handler;
- } else if (soc_is_ar913x()) {
-- ath79_ip2_flush_reg = AR913X_DDR_REG_FLUSH_WMAC;
-- ath79_ip3_flush_reg = AR913X_DDR_REG_FLUSH_USB;
-+ ath79_ip2_handler = ar913x_ip2_handler;
-+ ath79_ip3_handler = ar913x_ip3_handler;
- } else if (soc_is_ar933x()) {
-- ath79_ip2_flush_reg = AR933X_DDR_REG_FLUSH_WMAC;
-- ath79_ip3_flush_reg = AR933X_DDR_REG_FLUSH_USB;
-- } else
-+ ath79_ip2_handler = ar933x_ip2_handler;
-+ ath79_ip3_handler = ar933x_ip3_handler;
-+ } else {
- BUG();
-+ }
-
- cp0_perfcount_irq = ATH79_MISC_IRQ_PERFC;
- mips_cpu_irq_init();
+++ /dev/null
-From 9db6021011556948d2d28d6957cee451bc2985aa Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Fri, 9 Dec 2011 21:59:50 +0100
-Subject: [PATCH 27/35] MIPS: ath79: add IRQ handling code for AR934X
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
----
- arch/mips/ath79/irq.c | 55 +++++++++++++++++++++++-
- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 25 +++++++++++
- arch/mips/include/asm/mach-ath79/irq.h | 6 ++-
- 3 files changed, 83 insertions(+), 3 deletions(-)
-
---- a/arch/mips/ath79/irq.c
-+++ b/arch/mips/ath79/irq.c
-@@ -1,10 +1,11 @@
- /*
- * Atheros AR71xx/AR724x/AR913x specific interrupt handling
- *
-+ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
- * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
-- * Parts of this file are based on Atheros' 2.6.15 BSP
-+ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
-@@ -129,7 +130,7 @@ static void __init ath79_misc_irq_init(v
-
- if (soc_is_ar71xx() || soc_is_ar913x())
- ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
-- else if (soc_is_ar724x() || soc_is_ar933x())
-+ else if (soc_is_ar724x() || soc_is_ar933x() || soc_is_ar934x())
- ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
- else
- BUG();
-@@ -143,6 +144,39 @@ static void __init ath79_misc_irq_init(v
- irq_set_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler);
- }
-
-+static void ar934x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
-+{
-+ u32 status;
-+
-+ disable_irq_nosync(irq);
-+
-+ status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS);
-+
-+ if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) {
-+ ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_PCIE);
-+ generic_handle_irq(ATH79_IP2_IRQ(0));
-+ } else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) {
-+ ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_WMAC);
-+ generic_handle_irq(ATH79_IP2_IRQ(1));
-+ } else {
-+ spurious_interrupt();
-+ }
-+
-+ enable_irq(irq);
-+}
-+
-+static void ar934x_ip2_irq_init(void)
-+{
-+ int i;
-+
-+ for (i = ATH79_IP2_IRQ_BASE;
-+ i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
-+ irq_set_chip_and_handler(i, &dummy_irq_chip,
-+ handle_level_irq);
-+
-+ irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar934x_ip2_irq_dispatch);
-+}
-+
- asmlinkage void plat_irq_dispatch(void)
- {
- unsigned long pending;
-@@ -202,6 +236,11 @@ static void ar933x_ip2_handler(void)
- do_IRQ(ATH79_CPU_IRQ_IP2);
- }
-
-+static void ar934x_ip2_handler(void)
-+{
-+ do_IRQ(ATH79_CPU_IRQ_IP2);
-+}
-+
- static void ar71xx_ip3_handler(void)
- {
- ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB);
-@@ -226,6 +265,12 @@ static void ar933x_ip3_handler(void)
- do_IRQ(ATH79_CPU_IRQ_USB);
- }
-
-+static void ar934x_ip3_handler(void)
-+{
-+ ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_USB);
-+ do_IRQ(ATH79_CPU_IRQ_USB);
-+}
-+
- void __init arch_init_irq(void)
- {
- if (soc_is_ar71xx()) {
-@@ -240,6 +285,9 @@ void __init arch_init_irq(void)
- } else if (soc_is_ar933x()) {
- ath79_ip2_handler = ar933x_ip2_handler;
- ath79_ip3_handler = ar933x_ip3_handler;
-+ } else if (soc_is_ar934x()) {
-+ ath79_ip2_handler = ar934x_ip2_handler;
-+ ath79_ip3_handler = ar934x_ip3_handler;
- } else {
- BUG();
- }
-@@ -247,4 +295,7 @@ void __init arch_init_irq(void)
- cp0_perfcount_irq = ATH79_MISC_IRQ_PERFC;
- mips_cpu_irq_init();
- ath79_misc_irq_init();
-+
-+ if (soc_is_ar934x())
-+ ar934x_ip2_irq_init();
- }
---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -92,6 +92,12 @@
- #define AR933X_DDR_REG_FLUSH_USB 0x84
- #define AR933X_DDR_REG_FLUSH_WMAC 0x88
-
-+#define AR934X_DDR_REG_FLUSH_GE0 0x9c
-+#define AR934X_DDR_REG_FLUSH_GE1 0xa0
-+#define AR934X_DDR_REG_FLUSH_USB 0xa4
-+#define AR934X_DDR_REG_FLUSH_PCIE 0xa8
-+#define AR934X_DDR_REG_FLUSH_WMAC 0xac
-+
- /*
- * PLL block
- */
-@@ -222,6 +228,7 @@
- #define AR933X_RESET_REG_BOOTSTRAP 0xac
-
- #define AR934X_RESET_REG_BOOTSTRAP 0xb0
-+#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
-
- #define MISC_INT_ETHSW BIT(12)
- #define MISC_INT_TIMER4 BIT(10)
-@@ -295,6 +302,24 @@
- #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
- #define AR934X_BOOTSTRAP_DDR1 BIT(0)
-
-+#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
-+#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
-+#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
-+#define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3)
-+#define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4)
-+#define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5)
-+#define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6)
-+#define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7)
-+#define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8)
-+#define AR934X_PCIE_WMAC_INT_WMAC_ALL \
-+ (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \
-+ AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP)
-+
-+#define AR934X_PCIE_WMAC_INT_PCIE_ALL \
-+ (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \
-+ AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
-+ AR934X_PCIE_WMAC_INT_PCIE_RC3)
-+
- #define REV_ID_MAJOR_MASK 0xfff0
- #define REV_ID_MAJOR_AR71XX 0x00a0
- #define REV_ID_MAJOR_AR913X 0x00b0
---- a/arch/mips/include/asm/mach-ath79/irq.h
-+++ b/arch/mips/include/asm/mach-ath79/irq.h
-@@ -10,7 +10,7 @@
- #define __ASM_MACH_ATH79_IRQ_H
-
- #define MIPS_CPU_IRQ_BASE 0
--#define NR_IRQS 46
-+#define NR_IRQS 48
-
- #define ATH79_MISC_IRQ_BASE 8
- #define ATH79_MISC_IRQ_COUNT 32
-@@ -19,6 +19,10 @@
- #define ATH79_PCI_IRQ_COUNT 6
- #define ATH79_PCI_IRQ(_x) (ATH79_PCI_IRQ_BASE + (_x))
-
-+#define ATH79_IP2_IRQ_BASE (ATH79_PCI_IRQ_BASE + ATH79_PCI_IRQ_COUNT)
-+#define ATH79_IP2_IRQ_COUNT 2
-+#define ATH79_IP2_IRQ(_x) (ATH79_IP2_IRQ_BASE + (_x))
-+
- #define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2)
- #define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3)
- #define ATH79_CPU_IRQ_GE0 (MIPS_CPU_IRQ_BASE + 4)
+++ /dev/null
-From da0f20f8a99de9193fc484a25d1f9edc913c98fd Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Sat, 10 Dec 2011 20:09:39 +0100
-Subject: [PATCH 28/35] MIPS: ath79: add AR934X specific glue to ath79_device_reset_{clear,set}
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
----
- arch/mips/ath79/common.c | 9 ++++++++-
- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 1 +
- 2 files changed, 9 insertions(+), 1 deletions(-)
-
---- a/arch/mips/ath79/common.c
-+++ b/arch/mips/ath79/common.c
-@@ -1,9 +1,12 @@
- /*
- * Atheros AR71XX/AR724X/AR913X common routines
- *
-- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
-+ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
-+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
-+ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
-+ *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
-@@ -67,6 +70,8 @@ void ath79_device_reset_set(u32 mask)
- reg = AR913X_RESET_REG_RESET_MODULE;
- else if (soc_is_ar933x())
- reg = AR933X_RESET_REG_RESET_MODULE;
-+ else if (soc_is_ar934x())
-+ reg = AR934X_RESET_REG_RESET_MODULE;
- else
- BUG();
-
-@@ -91,6 +96,8 @@ void ath79_device_reset_clear(u32 mask)
- reg = AR913X_RESET_REG_RESET_MODULE;
- else if (soc_is_ar933x())
- reg = AR933X_RESET_REG_RESET_MODULE;
-+ else if (soc_is_ar934x())
-+ reg = AR934X_RESET_REG_RESET_MODULE;
- else
- BUG();
-
---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -227,6 +227,7 @@
- #define AR933X_RESET_REG_RESET_MODULE 0x1c
- #define AR933X_RESET_REG_BOOTSTRAP 0xac
-
-+#define AR934X_RESET_REG_RESET_MODULE 0x1c
- #define AR934X_RESET_REG_BOOTSTRAP 0xb0
- #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
-
+++ /dev/null
-From 6b6803a249a27aa708bc5f24aa15270e30f3de61 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Sat, 10 Dec 2011 19:55:05 +0100
-Subject: [PATCH 29/35] MIPS: ath79: register UART device for AR934X SoCs
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
----
- arch/mips/ath79/dev-common.c | 3 ++-
- 1 files changed, 2 insertions(+), 1 deletions(-)
-
---- a/arch/mips/ath79/dev-common.c
-+++ b/arch/mips/ath79/dev-common.c
-@@ -89,7 +89,8 @@ void __init ath79_register_uart(void)
-
- if (soc_is_ar71xx() ||
- soc_is_ar724x() ||
-- soc_is_ar913x()) {
-+ soc_is_ar913x() ||
-+ soc_is_ar934x()) {
- ath79_uart_data[0].uartclk = clk_get_rate(clk);
- platform_device_register(&ath79_uart_device);
- } else if (soc_is_ar933x()) {
+++ /dev/null
-From 58b69cf52387a7351ec13b52d3d6a495fe611c29 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Fri, 9 Dec 2011 22:07:23 +0100
-Subject: [PATCH 30/35] MIPS: ath79: add WMAC registration code for AR934X
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
----
- arch/mips/ath79/Kconfig | 2 +-
- arch/mips/ath79/dev-wmac.c | 30 ++++++++++++++++++++++-
- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 3 ++
- 3 files changed, 32 insertions(+), 3 deletions(-)
-
---- a/arch/mips/ath79/Kconfig
-+++ b/arch/mips/ath79/Kconfig
-@@ -86,7 +86,7 @@ config ATH79_DEV_USB
- def_bool n
-
- config ATH79_DEV_WMAC
-- depends on (SOC_AR913X || SOC_AR933X)
-+ depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X)
- def_bool n
-
- endif
---- a/arch/mips/ath79/dev-wmac.c
-+++ b/arch/mips/ath79/dev-wmac.c
-@@ -1,9 +1,12 @@
- /*
- * Atheros AR913X/AR933X SoC built-in WMAC device support
- *
-+ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
- * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
-+ * Parts of this file are based on Atheros 2.6.15/2.6.31 BSP
-+ *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
-@@ -26,8 +29,7 @@ static struct resource ath79_wmac_resour
- /* .start and .end fields are filled dynamically */
- .flags = IORESOURCE_MEM,
- }, {
-- .start = ATH79_CPU_IRQ_IP2,
-- .end = ATH79_CPU_IRQ_IP2,
-+ /* .start and .end fields are filled dynamically */
- .flags = IORESOURCE_IRQ,
- },
- };
-@@ -53,6 +55,8 @@ static void __init ar913x_wmac_setup(voi
-
- ath79_wmac_resources[0].start = AR913X_WMAC_BASE;
- ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1;
-+ ath79_wmac_resources[1].start = ATH79_CPU_IRQ_IP2;
-+ ath79_wmac_resources[1].end = ATH79_CPU_IRQ_IP2;
- }
-
-
-@@ -79,6 +83,8 @@ static void __init ar933x_wmac_setup(voi
-
- ath79_wmac_resources[0].start = AR933X_WMAC_BASE;
- ath79_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1;
-+ ath79_wmac_resources[1].start = ATH79_CPU_IRQ_IP2;
-+ ath79_wmac_resources[1].end = ATH79_CPU_IRQ_IP2;
-
- t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
- if (t & AR933X_BOOTSTRAP_REF_CLK_40)
-@@ -92,12 +98,32 @@ static void __init ar933x_wmac_setup(voi
- ath79_wmac_data.external_reset = ar933x_wmac_reset;
- }
-
-+static void ar934x_wmac_setup(void)
-+{
-+ u32 t;
-+
-+ ath79_wmac_device.name = "ar934x_wmac";
-+
-+ ath79_wmac_resources[0].start = AR934X_WMAC_BASE;
-+ ath79_wmac_resources[0].end = AR934X_WMAC_BASE + AR934X_WMAC_SIZE - 1;
-+ ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
-+ ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
-+
-+ t = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
-+ if (t & AR934X_BOOTSTRAP_REF_CLK_40)
-+ ath79_wmac_data.is_clk_25mhz = false;
-+ else
-+ ath79_wmac_data.is_clk_25mhz = true;
-+}
-+
- void __init ath79_register_wmac(u8 *cal_data)
- {
- if (soc_is_ar913x())
- ar913x_wmac_setup();
- else if (soc_is_ar933x())
- ar933x_wmac_setup();
-+ else if (soc_is_ar934x())
-+ ar934x_wmac_setup();
- else
- BUG();
-
---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -61,6 +61,9 @@
- #define AR933X_EHCI_BASE 0x1b000000
- #define AR933X_EHCI_SIZE 0x1000
-
-+#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
-+#define AR934X_WMAC_SIZE 0x20000
-+
- /*
- * DDR_CTRL block
- */
+++ /dev/null
-From 2d832612094b5592641364773c5ab2a3658f7120 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Sun, 11 Dec 2011 18:34:13 +0100
-Subject: [PATCH 31/35] MIPS: ath79: add USB platform setup code for AR934X
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
----
- arch/mips/ath79/dev-usb.c | 28 +++++++++++++++++++
- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 35 ++++++++++++++++++++++++
- 2 files changed, 63 insertions(+), 0 deletions(-)
-
---- a/arch/mips/ath79/dev-usb.c
-+++ b/arch/mips/ath79/dev-usb.c
-@@ -180,6 +180,32 @@ static void __init ar933x_usb_setup(void
- platform_device_register(&ath79_ehci_device);
- }
-
-+static void __init ar934x_usb_setup(void)
-+{
-+ u32 bootstrap;
-+
-+ bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
-+ if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE)
-+ return;
-+
-+ ath79_device_reset_clear(AR934X_RESET_USBSUS_OVERRIDE);
-+ udelay(1000);
-+
-+ ath79_device_reset_set(AR934X_RESET_USB_PHY);
-+ udelay(1000);
-+
-+ ath79_device_reset_set(AR934X_RESET_USB_PHY_ANALOG);
-+ udelay(1000);
-+
-+ ath79_device_reset_set(AR934X_RESET_USB_HOST);
-+ udelay(1000);
-+
-+ ath79_ehci_resources[0].start = AR934X_EHCI_BASE;
-+ ath79_ehci_resources[0].end = AR934X_EHCI_BASE + AR934X_EHCI_SIZE - 1;
-+ ath79_ehci_device.name = "ar934x-ehci";
-+ platform_device_register(&ath79_ehci_device);
-+}
-+
- void __init ath79_register_usb(void)
- {
- if (soc_is_ar71xx())
-@@ -192,6 +218,8 @@ void __init ath79_register_usb(void)
- ar913x_usb_setup();
- else if (soc_is_ar933x())
- ar933x_usb_setup();
-+ else if (soc_is_ar934x())
-+ ar934x_usb_setup();
- else
- BUG();
- }
---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -63,6 +63,8 @@
-
- #define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
- #define AR934X_WMAC_SIZE 0x20000
-+#define AR934X_EHCI_BASE 0x1b000000
-+#define AR934X_EHCI_SIZE 0x1000
-
- /*
- * DDR_CTRL block
-@@ -288,6 +290,39 @@
- #define AR933X_RESET_USB_PHY BIT(4)
- #define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
-
-+#define AR934X_RESET_HOST BIT(31)
-+#define AR934X_RESET_SLIC BIT(30)
-+#define AR934X_RESET_HDMA BIT(29)
-+#define AR934X_RESET_EXTERNAL BIT(28)
-+#define AR934X_RESET_RTC BIT(27)
-+#define AR934X_RESET_PCIE_EP_INT BIT(26)
-+#define AR934X_RESET_CHKSUM_ACC BIT(25)
-+#define AR934X_RESET_FULL_CHIP BIT(24)
-+#define AR934X_RESET_GE1_MDIO BIT(23)
-+#define AR934X_RESET_GE0_MDIO BIT(22)
-+#define AR934X_RESET_CPU_NMI BIT(21)
-+#define AR934X_RESET_CPU_COLD BIT(20)
-+#define AR934X_RESET_HOST_RESET_INT BIT(19)
-+#define AR934X_RESET_PCIE_EP BIT(18)
-+#define AR934X_RESET_UART1 BIT(17)
-+#define AR934X_RESET_DDR BIT(16)
-+#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
-+#define AR934X_RESET_NANDF BIT(14)
-+#define AR934X_RESET_GE1_MAC BIT(13)
-+#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12)
-+#define AR934X_RESET_USB_PHY_ANALOG BIT(11)
-+#define AR934X_RESET_HOST_DMA_INT BIT(10)
-+#define AR934X_RESET_GE0_MAC BIT(9)
-+#define AR934X_RESET_ETH_SIWTCH BIT(8)
-+#define AR934X_RESET_PCIE_PHY BIT(7)
-+#define AR934X_RESET_PCIE BIT(6)
-+#define AR934X_RESET_USB_HOST BIT(5)
-+#define AR934X_RESET_USB_PHY BIT(4)
-+#define AR934X_RESET_USBSUS_OVERRIDE BIT(3)
-+#define AR934X_RESET_LUT BIT(2)
-+#define AR934X_RESET_MBOX BIT(1)
-+#define AR934X_RESET_I2S BIT(0)
-+
- #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
-
- #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
+++ /dev/null
-From f299f36542f81f05cff7cdebb50abde202faf6df Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Sat, 17 Dec 2011 10:04:18 +0100
-Subject: [PATCH 32/35] MIPS: ath79: add PCI_AR724X Kconfig symbol
-
-The AR724X specific PCI code can be used for the
-AR934X SoCs, however it can be selected only if
-SOC_AR724X is set.
-
-Introduce a new Kconfig symbol in order to be able
-to use the code for AR934X as well.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
----
- arch/mips/ath79/Kconfig | 4 ++++
- arch/mips/include/asm/mach-ath79/pci.h | 2 +-
- arch/mips/pci/Makefile | 2 +-
- 3 files changed, 6 insertions(+), 2 deletions(-)
-
---- a/arch/mips/ath79/Kconfig
-+++ b/arch/mips/ath79/Kconfig
-@@ -59,6 +59,7 @@ config SOC_AR724X
- select USB_ARCH_HAS_EHCI
- select USB_ARCH_HAS_OHCI
- select HW_HAS_PCI
-+ select PCI_AR724X if PCI
- def_bool n
-
- config SOC_AR913X
-@@ -73,6 +74,9 @@ config SOC_AR934X
- select USB_ARCH_HAS_EHCI
- def_bool n
-
-+config PCI_AR724X
-+ def_bool n
-+
- config ATH79_DEV_GPIO_BUTTONS
- def_bool n
-
---- a/arch/mips/include/asm/mach-ath79/pci.h
-+++ b/arch/mips/include/asm/mach-ath79/pci.h
-@@ -19,7 +19,7 @@ int ar71xx_pcibios_init(void);
- static inline int ar71xx_pcibios_init(void) { return 0 };
- #endif
-
--#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR724X)
-+#if defined(CONFIG_PCI_AR724X)
- int ar724x_pcibios_init(int irq);
- #else
- static inline int ar724x_pcibios_init(int irq) { return 0 };
---- a/arch/mips/pci/Makefile
-+++ b/arch/mips/pci/Makefile
-@@ -20,7 +20,7 @@ obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o
- ops-bcm63xx.o
- obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o
- obj-$(CONFIG_SOC_AR71XX) += pci-ar71xx.o
--obj-$(CONFIG_SOC_AR724X) += pci-ar724x.o
-+obj-$(CONFIG_PCI_AR724X) += pci-ar724x.o
-
- #
- # These are still pretty much in the old state, watch, go blind.
+++ /dev/null
-From e30d942814a606c5258c7adafc6bbb49836573e9 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Sat, 17 Dec 2011 10:13:08 +0100
-Subject: [PATCH 33/35] MIPS: ath79: add PCI registration code for AR934X
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
----
- arch/mips/ath79/Kconfig | 2 ++
- arch/mips/ath79/pci.c | 13 ++++++++++++-
- 2 files changed, 14 insertions(+), 1 deletions(-)
-
---- a/arch/mips/ath79/Kconfig
-+++ b/arch/mips/ath79/Kconfig
-@@ -72,6 +72,8 @@ config SOC_AR933X
-
- config SOC_AR934X
- select USB_ARCH_HAS_EHCI
-+ select HW_HAS_PCI
-+ select PCI_AR724X if PCI
- def_bool n
-
- config PCI_AR724X
---- a/arch/mips/ath79/pci.c
-+++ b/arch/mips/ath79/pci.c
-@@ -14,6 +14,7 @@
-
- #include <linux/init.h>
- #include <linux/pci.h>
-+#include <asm/mach-ath79/ar71xx_regs.h>
- #include <asm/mach-ath79/ath79.h>
- #include <asm/mach-ath79/irq.h>
- #include <asm/mach-ath79/pci.h>
-@@ -57,7 +58,9 @@ int __init pcibios_map_irq(const struct
- if (soc_is_ar71xx()) {
- ath79_pci_irq_map = ar71xx_pci_irq_map;
- ath79_pci_nr_irqs = ARRAY_SIZE(ar71xx_pci_irq_map);
-- } else if (soc_is_ar724x()) {
-+ } else if (soc_is_ar724x() ||
-+ soc_is_ar9342() ||
-+ soc_is_ar9344()) {
- ath79_pci_irq_map = ar724x_pci_irq_map;
- ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map);
- } else {
-@@ -115,5 +118,13 @@ int __init ath79_register_pci(void)
- if (soc_is_ar724x())
- return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2);
-
-+ if (soc_is_ar9342() || soc_is_ar9344()) {
-+ u32 bootstrap;
-+
-+ bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
-+ if (bootstrap & AR934X_BOOTSTRAP_PCIE_RC)
-+ return ar724x_pcibios_init(ATH79_IP2_IRQ(0));
-+ }
-+
- return -ENODEV;
- }
+++ /dev/null
-From a01e8727327cf0fb6382ca8700a3a3f73d93202a Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Fri, 9 Dec 2011 22:23:02 +0100
-Subject: [PATCH 34/35] MIPS: ath79: add initial support for the Atheros DB120 board
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
----
- arch/mips/ath79/Kconfig | 12 +++
- arch/mips/ath79/Makefile | 1 +
- arch/mips/ath79/mach-db120.c | 155 ++++++++++++++++++++++++++++++++++++++++++
- arch/mips/ath79/machtypes.h | 1 +
- 4 files changed, 169 insertions(+), 0 deletions(-)
- create mode 100644 arch/mips/ath79/mach-db120.c
-
---- a/arch/mips/ath79/Kconfig
-+++ b/arch/mips/ath79/Kconfig
-@@ -26,6 +26,18 @@ config ATH79_MACH_AP81
- Say 'Y' here if you want your kernel to support the
- Atheros AP81 reference board.
-
-+config ATH79_MACH_DB120
-+ bool "Atheros DB120 reference board"
-+ select SOC_AR934X
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_SPI
-+ select ATH79_DEV_USB
-+ select ATH79_DEV_WMAC
-+ help
-+ Say 'Y' here if you want your kernel to support the
-+ Atheros DB120 reference board.
-+
- config ATH79_MACH_PB44
- bool "Atheros PB44 reference board"
- select SOC_AR71XX
---- a/arch/mips/ath79/Makefile
-+++ b/arch/mips/ath79/Makefile
-@@ -28,5 +28,6 @@ obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wma
- #
- obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o
- obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o
-+obj-$(CONFIG_ATH79_MACH_DB120) += mach-db120.o
- obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o
- obj-$(CONFIG_ATH79_MACH_UBNT_XM) += mach-ubnt-xm.o
---- /dev/null
-+++ b/arch/mips/ath79/mach-db120.c
-@@ -0,0 +1,155 @@
-+/*
-+ * Atheros DB120 reference board support
-+ *
-+ * Copyright (c) 2011 Qualcomm Atheros
-+ * Copyright (c) 2011 Gabor Juhos <juhosg@openwrt.org>
-+ *
-+ * All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted (subject to the limitations in the
-+ * disclaimer below) provided that the following conditions are met:
-+ *
-+ * * Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions and the following disclaimer.
-+ *
-+ * * Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the
-+ * distribution.
-+ *
-+ * * Neither the name of Qualcomm Atheros nor the names of its
-+ * contributors may be used to endorse or promote products derived
-+ * from this software without specific prior written permission.
-+ *
-+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
-+ * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
-+ * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
-+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#include <linux/pci.h>
-+#include <linux/ath9k_platform.h>
-+
-+#include "machtypes.h"
-+#include "dev-gpio-buttons.h"
-+#include "dev-leds-gpio.h"
-+#include "dev-spi.h"
-+#include "dev-usb.h"
-+#include "dev-wmac.h"
-+#include "pci.h"
-+
-+#define DB120_GPIO_LED_WLAN_5G 12
-+#define DB120_GPIO_LED_WLAN_2G 13
-+#define DB120_GPIO_LED_STATUS 14
-+#define DB120_GPIO_LED_WPS 15
-+
-+#define DB120_GPIO_BTN_WPS 16
-+
-+#define DB120_KEYS_POLL_INTERVAL 20 /* msecs */
-+#define DB120_KEYS_DEBOUNCE_INTERVAL (3 * DB120_KEYS_POLL_INTERVAL)
-+
-+#define DB120_WMAC_CALDATA_OFFSET 0x1000
-+#define DB120_PCIE_CALDATA_OFFSET 0x5000
-+
-+static struct gpio_led db120_leds_gpio[] __initdata = {
-+ {
-+ .name = "db120:green:status",
-+ .gpio = DB120_GPIO_LED_STATUS,
-+ .active_low = 1,
-+ },
-+ {
-+ .name = "db120:green:wps",
-+ .gpio = DB120_GPIO_LED_WPS,
-+ .active_low = 1,
-+ },
-+ {
-+ .name = "db120:green:wlan-5g",
-+ .gpio = DB120_GPIO_LED_WLAN_5G,
-+ .active_low = 1,
-+ },
-+ {
-+ .name = "db120:green:wlan-2g",
-+ .gpio = DB120_GPIO_LED_WLAN_2G,
-+ .active_low = 1,
-+ },
-+};
-+
-+static struct gpio_keys_button db120_gpio_keys[] __initdata = {
-+ {
-+ .desc = "WPS button",
-+ .type = EV_KEY,
-+ .code = KEY_WPS_BUTTON,
-+ .debounce_interval = DB120_KEYS_DEBOUNCE_INTERVAL,
-+ .gpio = DB120_GPIO_BTN_WPS,
-+ .active_low = 1,
-+ },
-+};
-+
-+static struct spi_board_info db120_spi_info[] = {
-+ {
-+ .bus_num = 0,
-+ .chip_select = 0,
-+ .max_speed_hz = 25000000,
-+ .modalias = "s25sl064a",
-+ }
-+};
-+
-+static struct ath79_spi_platform_data db120_spi_data = {
-+ .bus_num = 0,
-+ .num_chipselect = 1,
-+};
-+
-+#ifdef CONFIG_PCI
-+static struct ath9k_platform_data db120_ath9k_data;
-+
-+static int db120_pci_plat_dev_init(struct pci_dev *dev)
-+{
-+ switch (PCI_SLOT(dev->devfn)) {
-+ case 0:
-+ dev->dev.platform_data = &db120_ath9k_data;
-+ break;
-+ }
-+
-+ return 0;
-+}
-+
-+static void __init db120_pci_init(u8 *eeprom)
-+{
-+ memcpy(db120_ath9k_data.eeprom_data, eeprom,
-+ sizeof(db120_ath9k_data.eeprom_data));
-+
-+ ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init);
-+ ath79_register_pci();
-+}
-+#else
-+static inline void db120_pci_init(void) {}
-+#endif /* CONFIG_PCI */
-+
-+static void __init db120_setup(void)
-+{
-+ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
-+
-+ ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio),
-+ db120_leds_gpio);
-+ ath79_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL,
-+ ARRAY_SIZE(db120_gpio_keys),
-+ db120_gpio_keys);
-+ ath79_register_spi(&db120_spi_data, db120_spi_info,
-+ ARRAY_SIZE(db120_spi_info));
-+ ath79_register_usb();
-+ ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET);
-+ db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET);
-+}
-+
-+MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board",
-+ db120_setup);
---- a/arch/mips/ath79/machtypes.h
-+++ b/arch/mips/ath79/machtypes.h
-@@ -18,6 +18,7 @@ enum ath79_mach_type {
- ATH79_MACH_GENERIC = 0,
- ATH79_MACH_AP121, /* Atheros AP121 reference board */
- ATH79_MACH_AP81, /* Atheros AP81 reference board */
-+ ATH79_MACH_DB120, /* Atheros DB120 reference board */
- ATH79_MACH_PB44, /* Atheros PB44 reference board */
- ATH79_MACH_UBNT_XM, /* Ubiquiti Networks XM board rev 1.0 */
- };
+++ /dev/null
-From cbf8930fe259777fb746f0387bf821729061c122 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Sun, 11 Dec 2011 22:09:20 +0100
-Subject: [PATCH 35/35] USB: ehci-ath79: add device_id entry for the AR934X SoCs
-
-Also make the USB_EHCI_ATH79 selectable for the AR934X SoCs.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
-Cc: Alan Stern <stern@rowland.harvard.edu>
-Cc: Greg Kroah-Hartman <gregkh@suse.de>
-Cc: linux-usb@vger.kernel.org
----
- drivers/usb/host/Kconfig | 2 +-
- drivers/usb/host/ehci-ath79.c | 4 ++++
- 2 files changed, 5 insertions(+), 1 deletions(-)
-
---- a/drivers/usb/host/Kconfig
-+++ b/drivers/usb/host/Kconfig
-@@ -210,7 +210,7 @@ config USB_CNS3XXX_EHCI
-
- config USB_EHCI_ATH79
- bool "EHCI support for AR7XXX/AR9XXX SoCs"
-- depends on USB_EHCI_HCD && (SOC_AR71XX || SOC_AR724X || SOC_AR913X || SOC_AR933X)
-+ depends on USB_EHCI_HCD && (SOC_AR71XX || SOC_AR724X || SOC_AR913X || SOC_AR933X || SOC_AR934X)
- select USB_EHCI_ROOT_HUB_TT
- default y
- ---help---
---- a/drivers/usb/host/ehci-ath79.c
-+++ b/drivers/usb/host/ehci-ath79.c
-@@ -37,6 +37,10 @@ static const struct platform_device_id e
- .driver_data = EHCI_ATH79_IP_V2,
- },
- {
-+ .name = "ar934x-ehci",
-+ .driver_data = EHCI_ATH79_IP_V2,
-+ },
-+ {
- /* terminating entry */
- },
- };
+++ /dev/null
-From 8e948c035dd7983eccc3a889f2497e64044f3a31 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Wed, 11 Jan 2012 20:06:35 +0100
-Subject: [PATCH 1/7] spi/ath79: add delay between SCK changes
-
-The driver uses the "as fast as it can" approach
-to drive the SCK signal. However this does not
-work with certain low speed SPI chips (e.g. the
-PCF2123 RTC chip). Add per-bit slowdowns in order
-to be able to use the driver with such chips as
-well.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
----
- drivers/spi/spi-ath79.c | 44 +++++++++++++++++++++++++++++++++++++++++++-
- 1 files changed, 43 insertions(+), 1 deletions(-)
-
---- a/drivers/spi/spi-ath79.c
-+++ b/drivers/spi/spi-ath79.c
-@@ -24,17 +24,24 @@
- #include <linux/spi/spi_bitbang.h>
- #include <linux/bitops.h>
- #include <linux/gpio.h>
-+#include <linux/clk.h>
-+#include <linux/err.h>
-
- #include <asm/mach-ath79/ar71xx_regs.h>
- #include <asm/mach-ath79/ath79_spi_platform.h>
-
- #define DRV_NAME "ath79-spi"
-
-+#define ATH79_SPI_RRW_DELAY_FACTOR 12000
-+#define MHZ (1000 * 1000)
-+
- struct ath79_spi {
- struct spi_bitbang bitbang;
- u32 ioc_base;
- u32 reg_ctrl;
- void __iomem *base;
-+ struct clk *clk;
-+ unsigned rrw_delay;
- };
-
- static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg)
-@@ -52,6 +59,12 @@ static inline struct ath79_spi *ath79_sp
- return spi_master_get_devdata(spi->master);
- }
-
-+static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned nsecs)
-+{
-+ if (nsecs > sp->rrw_delay)
-+ ndelay(nsecs - sp->rrw_delay);
-+}
-+
- static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
- {
- struct ath79_spi *sp = ath79_spidev_to_sp(spi);
-@@ -184,7 +197,9 @@ static u32 ath79_spi_txrx_mode0(struct s
-
- /* setup MSB (to slave) on trailing edge */
- ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
-+ ath79_spi_delay(sp, nsecs);
- ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK);
-+ ath79_spi_delay(sp, nsecs);
-
- word <<= 1;
- }
-@@ -198,6 +213,7 @@ static __devinit int ath79_spi_probe(str
- struct ath79_spi *sp;
- struct ath79_spi_platform_data *pdata;
- struct resource *r;
-+ unsigned long rate;
- int ret;
-
- master = spi_alloc_master(&pdev->dev, sizeof(*sp));
-@@ -239,12 +255,36 @@ static __devinit int ath79_spi_probe(str
- goto err_put_master;
- }
-
-+ sp->clk = clk_get(&pdev->dev, "ahb");
-+ if (IS_ERR(sp->clk)) {
-+ ret = PTR_ERR(sp->clk);
-+ goto err_unmap;
-+ }
-+
-+ ret = clk_enable(sp->clk);
-+ if (ret)
-+ goto err_clk_put;
-+
-+ rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
-+ if (!rate) {
-+ ret = -EINVAL;
-+ goto err_clk_disable;
-+ }
-+
-+ sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate;
-+ dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
-+ sp->rrw_delay);
-+
- ret = spi_bitbang_start(&sp->bitbang);
- if (ret)
-- goto err_unmap;
-+ goto err_clk_disable;
-
- return 0;
-
-+err_clk_disable:
-+ clk_disable(sp->clk);
-+err_clk_put:
-+ clk_put(sp->clk);
- err_unmap:
- iounmap(sp->base);
- err_put_master:
-@@ -259,6 +299,8 @@ static __devexit int ath79_spi_remove(st
- struct ath79_spi *sp = platform_get_drvdata(pdev);
-
- spi_bitbang_stop(&sp->bitbang);
-+ clk_disable(sp->clk);
-+ clk_put(sp->clk);
- iounmap(sp->base);
- platform_set_drvdata(pdev, NULL);
- spi_master_put(sp->bitbang.master);
+++ /dev/null
-From ea7e40aedae58b7a0f0ccd8658063de499734874 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Wed, 11 Jan 2012 20:33:41 +0100
-Subject: [PATCH 2/7] spi/ath79: add missing HIGH->LOW SCK transition
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
----
- drivers/spi/spi-ath79.c | 2 ++
- 1 files changed, 2 insertions(+), 0 deletions(-)
-
---- a/drivers/spi/spi-ath79.c
-+++ b/drivers/spi/spi-ath79.c
-@@ -200,6 +200,8 @@ static u32 ath79_spi_txrx_mode0(struct s
- ath79_spi_delay(sp, nsecs);
- ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK);
- ath79_spi_delay(sp, nsecs);
-+ if (bits == 1)
-+ ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
-
- word <<= 1;
- }
+++ /dev/null
-From ecf57a64feb737dec1da72aab21dccd30a88ba19 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Mon, 9 Jan 2012 15:03:28 +0100
-Subject: [PATCH 3/7] spi/ath79: remove superfluous chip select code
-
-The spi_bitbang driver calls the chipselect function
-of the driver from spi_bitbang_setup in order to
-deselect the given SPI chip, so we don't have to
-initialize the CS line here.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
----
- drivers/spi/spi-ath79.c | 6 ------
- 1 files changed, 0 insertions(+), 6 deletions(-)
-
---- a/drivers/spi/spi-ath79.c
-+++ b/drivers/spi/spi-ath79.c
-@@ -128,12 +128,6 @@ static int ath79_spi_setup_cs(struct spi
- gpio_free(cdata->gpio);
- return status;
- }
-- } else {
-- if (spi->mode & SPI_CS_HIGH)
-- sp->ioc_base |= AR71XX_SPI_IOC_CS0;
-- else
-- sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;
-- ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
- }
-
- return 0;
+++ /dev/null
-From dd5b424b0b3f0370f9b63594ad53c16989b6ad78 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Mon, 9 Jan 2012 15:04:21 +0100
-Subject: [PATCH 4/7] spi/ath79: use gpio_request_one
-
-Use gpio_request_one() instead of multiple gpiolib calls.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
----
- drivers/spi/spi-ath79.c | 26 +++++++++++++-------------
- 1 files changed, 13 insertions(+), 13 deletions(-)
-
---- a/drivers/spi/spi-ath79.c
-+++ b/drivers/spi/spi-ath79.c
-@@ -100,6 +100,7 @@ static int ath79_spi_setup_cs(struct spi
- {
- struct ath79_spi *sp = ath79_spidev_to_sp(spi);
- struct ath79_spi_controller_data *cdata;
-+ int status;
-
- cdata = spi->controller_data;
- if (spi->chip_select && !cdata)
-@@ -115,22 +116,21 @@ static int ath79_spi_setup_cs(struct spi
- /* TODO: setup speed? */
- ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
-
-+ status = 0;
- if (spi->chip_select) {
-- int status = 0;
-+ unsigned long flags;
-
-- status = gpio_request(cdata->gpio, dev_name(&spi->dev));
-- if (status)
-- return status;
--
-- status = gpio_direction_output(cdata->gpio,
-- spi->mode & SPI_CS_HIGH);
-- if (status) {
-- gpio_free(cdata->gpio);
-- return status;
-- }
-+ flags = GPIOF_DIR_OUT;
-+ if (spi->mode & SPI_CS_HIGH)
-+ flags |= GPIOF_INIT_HIGH;
-+ else
-+ flags |= GPIOF_INIT_LOW;
-+
-+ status = gpio_request_one(cdata->gpio, flags,
-+ dev_name(&spi->dev));
- }
-
-- return 0;
-+ return status;
- }
-
- static void ath79_spi_cleanup_cs(struct spi_device *spi)
+++ /dev/null
-From 25e681989198e94656eab9df22b8b761abd2ae26 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Mon, 9 Jan 2012 15:00:46 +0100
-Subject: [PATCH 5/7] spi/ath79: avoid multiple initialization of the SPI controller
-
-Currently we are initializing the SPI controller in
-the chip select line function, and that function is
-called once for each SPI device on the bus. If a
-board has multiple SPI devices, the controller will
-be initialized multiple times.
-
-Introduce ath79_spi_{en,dis}able helper functions,
-and call those from probe/response in order to avoid
-the mutliple initialization of the controller.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
----
- drivers/spi/spi-ath79.c | 41 ++++++++++++++++++++++++-----------------
- 1 files changed, 24 insertions(+), 17 deletions(-)
-
---- a/drivers/spi/spi-ath79.c
-+++ b/drivers/spi/spi-ath79.c
-@@ -96,16 +96,8 @@ static void ath79_spi_chipselect(struct
-
- }
-
--static int ath79_spi_setup_cs(struct spi_device *spi)
-+static void ath79_spi_enable(struct ath79_spi *sp)
- {
-- struct ath79_spi *sp = ath79_spidev_to_sp(spi);
-- struct ath79_spi_controller_data *cdata;
-- int status;
--
-- cdata = spi->controller_data;
-- if (spi->chip_select && !cdata)
-- return -EINVAL;
--
- /* enable GPIO mode */
- ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
-
-@@ -115,6 +107,24 @@ static int ath79_spi_setup_cs(struct spi
-
- /* TODO: setup speed? */
- ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
-+}
-+
-+static void ath79_spi_disable(struct ath79_spi *sp)
-+{
-+ /* restore CTRL register */
-+ ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
-+ /* disable GPIO mode */
-+ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
-+}
-+
-+static int ath79_spi_setup_cs(struct spi_device *spi)
-+{
-+ struct ath79_spi_controller_data *cdata;
-+ int status;
-+
-+ cdata = spi->controller_data;
-+ if (spi->chip_select && !cdata)
-+ return -EINVAL;
-
- status = 0;
- if (spi->chip_select) {
-@@ -135,17 +145,10 @@ static int ath79_spi_setup_cs(struct spi
-
- static void ath79_spi_cleanup_cs(struct spi_device *spi)
- {
-- struct ath79_spi *sp = ath79_spidev_to_sp(spi);
--
- if (spi->chip_select) {
- struct ath79_spi_controller_data *cdata = spi->controller_data;
- gpio_free(cdata->gpio);
- }
--
-- /* restore CTRL register */
-- ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
-- /* disable GPIO mode */
-- ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
- }
-
- static int ath79_spi_setup(struct spi_device *spi)
-@@ -271,12 +274,15 @@ static __devinit int ath79_spi_probe(str
- dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
- sp->rrw_delay);
-
-+ ath79_spi_enable(sp);
- ret = spi_bitbang_start(&sp->bitbang);
- if (ret)
-- goto err_clk_disable;
-+ goto err_disable;
-
- return 0;
-
-+err_disable:
-+ ath79_spi_disable(sp);
- err_clk_disable:
- clk_disable(sp->clk);
- err_clk_put:
-@@ -295,6 +301,7 @@ static __devexit int ath79_spi_remove(st
- struct ath79_spi *sp = platform_get_drvdata(pdev);
-
- spi_bitbang_stop(&sp->bitbang);
-+ ath79_spi_disable(sp);
- clk_disable(sp->clk);
- clk_put(sp->clk);
- iounmap(sp->base);
+++ /dev/null
-From e01dcc2835017b55e936bd150ddab29bfcf2c63c Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Wed, 11 Jan 2012 22:19:32 +0100
-Subject: [PATCH 6/7] spi/ath79: add shutdown handler
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
----
- drivers/spi/spi-ath79.c | 12 +++++++++++-
- 1 files changed, 11 insertions(+), 1 deletions(-)
-
---- a/drivers/spi/spi-ath79.c
-+++ b/drivers/spi/spi-ath79.c
-@@ -296,7 +296,7 @@ err_put_master:
- return ret;
- }
-
--static __devexit int ath79_spi_remove(struct platform_device *pdev)
-+static void __ath79_spi_remove(struct platform_device *pdev)
- {
- struct ath79_spi *sp = platform_get_drvdata(pdev);
-
-@@ -307,13 +307,23 @@ static __devexit int ath79_spi_remove(st
- iounmap(sp->base);
- platform_set_drvdata(pdev, NULL);
- spi_master_put(sp->bitbang.master);
-+}
-
-+static __devexit int ath79_spi_remove(struct platform_device *pdev)
-+{
-+ __ath79_spi_remove(pdev);
- return 0;
- }
-
-+static void ath79_spi_shutdown(struct platform_device *pdev)
-+{
-+ __ath79_spi_remove(pdev);
-+}
-+
- static struct platform_driver ath79_spi_driver = {
- .probe = ath79_spi_probe,
- .remove = __devexit_p(ath79_spi_remove),
-+ .shutdown = ath79_spi_shutdown,
- .driver = {
- .name = DRV_NAME,
- .owner = THIS_MODULE,
+++ /dev/null
-From bdbd9b2861ba73557795915598bb276a8568d130 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Wed, 11 Jan 2012 22:25:11 +0100
-Subject: [PATCH 7/7] spi/ath79: make chipselect logic more flexible
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
----
- arch/mips/ath79/mach-ap121.c | 6 ++
- arch/mips/ath79/mach-ap81.c | 6 ++
- arch/mips/ath79/mach-pb44.c | 6 ++
- arch/mips/ath79/mach-ubnt-xm.c | 6 ++
- .../include/asm/mach-ath79/ath79_spi_platform.h | 8 ++-
- drivers/spi/spi-ath79.c | 63 ++++++++++++--------
- 6 files changed, 69 insertions(+), 26 deletions(-)
-
---- a/arch/mips/ath79/mach-ap121.c
-+++ b/arch/mips/ath79/mach-ap121.c
-@@ -58,12 +58,18 @@ static struct gpio_keys_button ap121_gpi
- }
- };
-
-+static struct ath79_spi_controller_data ap121_spi0_data = {
-+ .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
-+ .cs_line = 0,
-+};
-+
- static struct spi_board_info ap121_spi_info[] = {
- {
- .bus_num = 0,
- .chip_select = 0,
- .max_speed_hz = 25000000,
- .modalias = "mx25l1606e",
-+ .controller_data = &ap121_spi0_data,
- }
- };
-
---- a/arch/mips/ath79/mach-ap81.c
-+++ b/arch/mips/ath79/mach-ap81.c
-@@ -67,12 +67,18 @@ static struct gpio_keys_button ap81_gpio
- }
- };
-
-+static struct ath79_spi_controller_data ap81_spi0_data = {
-+ .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
-+ .cs_line = 0,
-+};
-+
- static struct spi_board_info ap81_spi_info[] = {
- {
- .bus_num = 0,
- .chip_select = 0,
- .max_speed_hz = 25000000,
- .modalias = "m25p64",
-+ .controller_data = &ap81_spi0_data,
- }
- };
-
---- a/arch/mips/ath79/mach-pb44.c
-+++ b/arch/mips/ath79/mach-pb44.c
-@@ -87,12 +87,18 @@ static struct gpio_keys_button pb44_gpio
- }
- };
-
-+static struct ath79_spi_controller_data pb44_spi0_data = {
-+ .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
-+ .cs_line = 0,
-+};
-+
- static struct spi_board_info pb44_spi_info[] = {
- {
- .bus_num = 0,
- .chip_select = 0,
- .max_speed_hz = 25000000,
- .modalias = "m25p64",
-+ .controller_data = &pb44_spi0_data,
- },
- };
-
---- a/arch/mips/ath79/mach-ubnt-xm.c
-+++ b/arch/mips/ath79/mach-ubnt-xm.c
-@@ -65,12 +65,18 @@ static struct gpio_keys_button ubnt_xm_g
- }
- };
-
-+static struct ath79_spi_controller_data ubnt_xm_spi0_data = {
-+ .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
-+ .cs_line = 0,
-+};
-+
- static struct spi_board_info ubnt_xm_spi_info[] = {
- {
- .bus_num = 0,
- .chip_select = 0,
- .max_speed_hz = 25000000,
- .modalias = "mx25l6405d",
-+ .controller_data = &ubnt_xm_spi0_data,
- }
- };
-
---- a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
-+++ b/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
-@@ -16,8 +16,14 @@ struct ath79_spi_platform_data {
- unsigned num_chipselect;
- };
-
-+enum ath79_spi_cs_type {
-+ ATH79_SPI_CS_TYPE_INTERNAL,
-+ ATH79_SPI_CS_TYPE_GPIO,
-+};
-+
- struct ath79_spi_controller_data {
-- unsigned gpio;
-+ enum ath79_spi_cs_type cs_type;
-+ unsigned cs_line;
- };
-
- #endif /* _ATH79_SPI_PLATFORM_H */
---- a/drivers/spi/spi-ath79.c
-+++ b/drivers/spi/spi-ath79.c
-@@ -35,6 +35,8 @@
- #define ATH79_SPI_RRW_DELAY_FACTOR 12000
- #define MHZ (1000 * 1000)
-
-+#define ATH79_SPI_CS_LINE_MAX 2
-+
- struct ath79_spi {
- struct spi_bitbang bitbang;
- u32 ioc_base;
-@@ -69,6 +71,7 @@ static void ath79_spi_chipselect(struct
- {
- struct ath79_spi *sp = ath79_spidev_to_sp(spi);
- int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
-+ struct ath79_spi_controller_data *cdata = spi->controller_data;
-
- if (is_active) {
- /* set initial clock polarity */
-@@ -80,20 +83,21 @@ static void ath79_spi_chipselect(struct
- ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
- }
-
-- if (spi->chip_select) {
-- struct ath79_spi_controller_data *cdata = spi->controller_data;
--
-- /* SPI is normally active-low */
-- gpio_set_value(cdata->gpio, cs_high);
-- } else {
-+ switch (cdata->cs_type) {
-+ case ATH79_SPI_CS_TYPE_INTERNAL:
- if (cs_high)
-- sp->ioc_base |= AR71XX_SPI_IOC_CS0;
-+ sp->ioc_base |= AR71XX_SPI_IOC_CS(cdata->cs_line);
- else
-- sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;
-+ sp->ioc_base &= ~AR71XX_SPI_IOC_CS(cdata->cs_line);
-
- ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
-- }
-+ break;
-
-+ case ATH79_SPI_CS_TYPE_GPIO:
-+ /* SPI is normally active-low */
-+ gpio_set_value(cdata->cs_line, cs_high);
-+ break;
-+ }
- }
-
- static void ath79_spi_enable(struct ath79_spi *sp)
-@@ -120,24 +124,30 @@ static void ath79_spi_disable(struct ath
- static int ath79_spi_setup_cs(struct spi_device *spi)
- {
- struct ath79_spi_controller_data *cdata;
-+ unsigned long flags;
- int status;
-
- cdata = spi->controller_data;
-- if (spi->chip_select && !cdata)
-+ if (!cdata)
- return -EINVAL;
-
- status = 0;
-- if (spi->chip_select) {
-- unsigned long flags;
-+ switch (cdata->cs_type) {
-+ case ATH79_SPI_CS_TYPE_INTERNAL:
-+ if (cdata->cs_line > ATH79_SPI_CS_LINE_MAX)
-+ status = -EINVAL;
-+ break;
-
-+ case ATH79_SPI_CS_TYPE_GPIO:
- flags = GPIOF_DIR_OUT;
- if (spi->mode & SPI_CS_HIGH)
- flags |= GPIOF_INIT_HIGH;
- else
- flags |= GPIOF_INIT_LOW;
-
-- status = gpio_request_one(cdata->gpio, flags,
-+ status = gpio_request_one(cdata->cs_line, flags,
- dev_name(&spi->dev));
-+ break;
- }
-
- return status;
-@@ -145,9 +155,15 @@ static int ath79_spi_setup_cs(struct spi
-
- static void ath79_spi_cleanup_cs(struct spi_device *spi)
- {
-- if (spi->chip_select) {
-- struct ath79_spi_controller_data *cdata = spi->controller_data;
-- gpio_free(cdata->gpio);
-+ struct ath79_spi_controller_data *cdata = spi->controller_data;
-+
-+ switch (cdata->cs_type) {
-+ case ATH79_SPI_CS_TYPE_INTERNAL:
-+ /* nothing to do */
-+ break;
-+ case ATH79_SPI_CS_TYPE_GPIO:
-+ gpio_free(cdata->cs_line);
-+ break;
- }
- }
-
-@@ -215,6 +231,10 @@ static __devinit int ath79_spi_probe(str
- unsigned long rate;
- int ret;
-
-+ pdata = pdev->dev.platform_data;
-+ if (!pdata)
-+ return -EINVAL;
-+
- master = spi_alloc_master(&pdev->dev, sizeof(*sp));
- if (master == NULL) {
- dev_err(&pdev->dev, "failed to allocate spi master\n");
-@@ -224,17 +244,10 @@ static __devinit int ath79_spi_probe(str
- sp = spi_master_get_devdata(master);
- platform_set_drvdata(pdev, sp);
-
-- pdata = pdev->dev.platform_data;
--
- master->setup = ath79_spi_setup;
- master->cleanup = ath79_spi_cleanup;
-- if (pdata) {
-- master->bus_num = pdata->bus_num;
-- master->num_chipselect = pdata->num_chipselect;
-- } else {
-- master->bus_num = -1;
-- master->num_chipselect = 1;
-- }
-+ master->bus_num = pdata->bus_num;
-+ master->num_chipselect = pdata->num_chipselect;
-
- sp->bitbang.master = spi_master_get(master);
- sp->bitbang.chipselect = ath79_spi_chipselect;
+++ /dev/null
---- a/arch/mips/ath79/mach-db120.c
-+++ b/arch/mips/ath79/mach-db120.c
-@@ -95,12 +95,18 @@ static struct gpio_keys_button db120_gpi
- },
- };
-
-+static struct ath79_spi_controller_data db120_spi0_data = {
-+ .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
-+ .cs_line = 0,
-+};
-+
- static struct spi_board_info db120_spi_info[] = {
- {
- .bus_num = 0,
- .chip_select = 0,
- .max_speed_hz = 25000000,
- .modalias = "s25sl064a",
-+ .controller_data = &db120_spi0_data,
- }
- };
-
+++ /dev/null
---- a/arch/mips/ath79/gpio.c
-+++ b/arch/mips/ath79/gpio.c
-@@ -188,8 +188,10 @@ void __init ath79_gpio_init(void)
-
- if (soc_is_ar71xx())
- ath79_gpio_count = AR71XX_GPIO_COUNT;
-- else if (soc_is_ar724x())
-- ath79_gpio_count = AR724X_GPIO_COUNT;
-+ else if (soc_is_ar7240())
-+ ath79_gpio_count = AR7240_GPIO_COUNT;
-+ else if (soc_is_ar7241() || soc_is_ar7242())
-+ ath79_gpio_count = AR7241_GPIO_COUNT;
- else if (soc_is_ar913x())
- ath79_gpio_count = AR913X_GPIO_COUNT;
- else if (soc_is_ar933x())
---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -428,7 +428,8 @@
- #define AR71XX_GPIO_REG_FUNC 0x28
-
- #define AR71XX_GPIO_COUNT 16
--#define AR724X_GPIO_COUNT 18
-+#define AR7240_GPIO_COUNT 18
-+#define AR7241_GPIO_COUNT 20
- #define AR913X_GPIO_COUNT 22
- #define AR933X_GPIO_COUNT 30
- #define AR934X_GPIO_COUNT 23
+++ /dev/null
---- a/arch/mips/ath79/dev-wmac.c
-+++ b/arch/mips/ath79/dev-wmac.c
-@@ -62,8 +62,8 @@ static void __init ar913x_wmac_setup(voi
-
- static int ar933x_wmac_reset(void)
- {
-- ath79_device_reset_clear(AR933X_RESET_WMAC);
- ath79_device_reset_set(AR933X_RESET_WMAC);
-+ ath79_device_reset_clear(AR933X_RESET_WMAC);
-
- return 0;
- }
+++ /dev/null
---- a/arch/mips/include/asm/mach-ath79/pci.h
-+++ b/arch/mips/include/asm/mach-ath79/pci.h
-@@ -16,13 +16,13 @@
- #if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR71XX)
- int ar71xx_pcibios_init(void);
- #else
--static inline int ar71xx_pcibios_init(void) { return 0 };
-+static inline int ar71xx_pcibios_init(void) { return 0; }
- #endif
-
- #if defined(CONFIG_PCI_AR724X)
- int ar724x_pcibios_init(int irq);
- #else
--static inline int ar724x_pcibios_init(int irq) { return 0 };
-+static inline int ar724x_pcibios_init(int irq) { return 0; }
- #endif
-
- #endif /* __ASM_MACH_ATH79_PCI_H */
+++ /dev/null
---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -313,7 +313,7 @@
- #define AR934X_RESET_USB_PHY_ANALOG BIT(11)
- #define AR934X_RESET_HOST_DMA_INT BIT(10)
- #define AR934X_RESET_GE0_MAC BIT(9)
--#define AR934X_RESET_ETH_SIWTCH BIT(8)
-+#define AR934X_RESET_ETH_SWITCH BIT(8)
- #define AR934X_RESET_PCIE_PHY BIT(7)
- #define AR934X_RESET_PCIE BIT(6)
- #define AR934X_RESET_USB_HOST BIT(5)
+++ /dev/null
---- a/arch/mips/ath79/dev-usb.c
-+++ b/arch/mips/ath79/dev-usb.c
-@@ -126,6 +126,8 @@ static void __init ar7240_usb_setup(void
-
- ath79_ohci_resources[0].start = AR7240_OHCI_BASE;
- ath79_ohci_resources[0].end = AR7240_OHCI_BASE + AR7240_OHCI_SIZE - 1;
-+ ath79_ohci_resources[1].start = ATH79_CPU_IRQ_USB;
-+ ath79_ohci_resources[1].end = ATH79_CPU_IRQ_USB;
- platform_device_register(&ath79_ohci_device);
- }
-
+++ /dev/null
---- a/drivers/mtd/maps/physmap.c
-+++ b/drivers/mtd/maps/physmap.c
-@@ -29,6 +29,66 @@ struct physmap_flash_info {
- struct map_info map[MAX_RESOURCES];
- };
-
-+static struct platform_device *physmap_map2pdev(struct map_info *map)
-+{
-+ return (struct platform_device *) map->map_priv_1;
-+}
-+
-+static void physmap_lock(struct map_info *map)
-+{
-+ struct platform_device *pdev;
-+ struct physmap_flash_data *physmap_data;
-+
-+ pdev = physmap_map2pdev(map);
-+ physmap_data = pdev->dev.platform_data;
-+ physmap_data->lock(pdev);
-+}
-+
-+static void physmap_unlock(struct map_info *map)
-+{
-+ struct platform_device *pdev;
-+ struct physmap_flash_data *physmap_data;
-+
-+ pdev = physmap_map2pdev(map);
-+ physmap_data = pdev->dev.platform_data;
-+ physmap_data->unlock(pdev);
-+}
-+
-+static map_word physmap_flash_read_lock(struct map_info *map, unsigned long ofs)
-+{
-+ map_word ret;
-+
-+ physmap_lock(map);
-+ ret = inline_map_read(map, ofs);
-+ physmap_unlock(map);
-+
-+ return ret;
-+}
-+
-+static void physmap_flash_write_lock(struct map_info *map, map_word d,
-+ unsigned long ofs)
-+{
-+ physmap_lock(map);
-+ inline_map_write(map, d, ofs);
-+ physmap_unlock(map);
-+}
-+
-+static void physmap_flash_copy_from_lock(struct map_info *map, void *to,
-+ unsigned long from, ssize_t len)
-+{
-+ physmap_lock(map);
-+ inline_map_copy_from(map, to, from, len);
-+ physmap_unlock(map);
-+}
-+
-+static void physmap_flash_copy_to_lock(struct map_info *map, unsigned long to,
-+ const void *from, ssize_t len)
-+{
-+ physmap_lock(map);
-+ inline_map_copy_to(map, to, from, len);
-+ physmap_unlock(map);
-+}
-+
- static int physmap_flash_remove(struct platform_device *dev)
- {
- struct physmap_flash_info *info;
-@@ -140,6 +200,13 @@ static int physmap_flash_probe(struct pl
-
- simple_map_init(&info->map[i]);
-
-+ if (physmap_data->lock && physmap_data->unlock) {
-+ info->map[i].read = physmap_flash_read_lock;
-+ info->map[i].write = physmap_flash_write_lock;
-+ info->map[i].copy_from = physmap_flash_copy_from_lock;
-+ info->map[i].copy_to = physmap_flash_copy_to_lock;
-+ }
-+
- probe_type = rom_probe_types;
- if (physmap_data->probe_type == NULL) {
- for (; info->mtd[i] == NULL && *probe_type != NULL; probe_type++)
---- a/include/linux/mtd/physmap.h
-+++ b/include/linux/mtd/physmap.h
-@@ -26,6 +26,8 @@ struct physmap_flash_data {
- unsigned int width;
- int (*init)(struct platform_device *);
- void (*exit)(struct platform_device *);
-+ void (*lock)(struct platform_device *);
-+ void (*unlock)(struct platform_device *);
- void (*set_vpp)(struct platform_device *, int);
- unsigned int nr_parts;
- unsigned int pfow_base;
+++ /dev/null
---- a/drivers/mtd/chips/jedec_probe.c
-+++ b/drivers/mtd/chips/jedec_probe.c
-@@ -148,6 +148,7 @@
- #define SST39LF160 0x2782
- #define SST39VF1601 0x234b
- #define SST39VF3201 0x235b
-+#define SST39VF6401B 0x236d
- #define SST39WF1601 0x274b
- #define SST39WF1602 0x274a
- #define SST39LF512 0x00D4
-@@ -1568,6 +1569,18 @@ static const struct amd_flash_info jedec
- ERASEINFO(0x10000,64),
- }
- }, {
-+ .mfr_id = CFI_MFR_SST,
-+ .dev_id = SST39VF6401B,
-+ .name = "SST 39VF6401B",
-+ .devtypes = CFI_DEVICETYPE_X16,
-+ .uaddr = MTD_UADDR_0xAAAA_0x5555,
-+ .dev_size = SIZE_8MiB,
-+ .cmd_set = P_ID_AMD_STD,
-+ .nr_regions = 1,
-+ .regions = {
-+ ERASEINFO(0x10000,128)
-+ }
-+ }, {
- .mfr_id = CFI_MFR_ST,
- .dev_id = M29F800AB,
- .name = "ST M29F800AB",
+++ /dev/null
---- a/drivers/mtd/chips/cfi_cmdset_0002.c
-+++ b/drivers/mtd/chips/cfi_cmdset_0002.c
-@@ -1214,8 +1214,8 @@ static int __xipram do_write_oneword(str
- break;
- }
-
-- if (chip_ready(map, adr))
-- break;
-+ if (chip_good(map, adr, datum))
-+ goto enable_xip;
-
- /* Latency issues. Drop the lock, wait a while and retry */
- UDELAY(map, chip, adr, 1);
-@@ -1231,6 +1231,8 @@ static int __xipram do_write_oneword(str
-
- ret = -EIO;
- }
-+
-+ enable_xip:
- xip_enable(map, chip, adr);
- op_done:
- chip->state = FL_READY;
-@@ -1563,7 +1565,6 @@ static int cfi_amdstd_write_buffers(stru
- return 0;
- }
-
--
- /*
- * Handle devices with one erase region, that only implement
- * the chip erase command.
-@@ -1627,8 +1628,8 @@ static int __xipram do_erase_chip(struct
- chip->erase_suspended = 0;
- }
-
-- if (chip_ready(map, adr))
-- break;
-+ if (chip_good(map, adr, map_word_ff(map)))
-+ goto op_done;
-
- if (time_after(jiffies, timeo)) {
- printk(KERN_WARNING "MTD %s(): software timeout\n",
-@@ -1648,6 +1649,7 @@ static int __xipram do_erase_chip(struct
- ret = -EIO;
- }
-
-+ op_done:
- chip->state = FL_READY;
- xip_enable(map, chip, adr);
- put_chip(map, chip, adr);
-@@ -1715,9 +1717,9 @@ static int __xipram do_erase_oneblock(st
- chip->erase_suspended = 0;
- }
-
-- if (chip_ready(map, adr)) {
-+ if (chip_good(map, adr, map_word_ff(map))) {
- xip_enable(map, chip, adr);
-- break;
-+ goto op_done;
- }
-
- if (time_after(jiffies, timeo)) {
-@@ -1739,6 +1741,7 @@ static int __xipram do_erase_oneblock(st
- ret = -EIO;
- }
-
-+ op_done:
- chip->state = FL_READY;
- put_chip(map, chip, adr);
- mutex_unlock(&chip->mutex);
+++ /dev/null
---- a/drivers/mtd/Kconfig
-+++ b/drivers/mtd/Kconfig
-@@ -148,6 +148,12 @@ config MTD_AR7_PARTS
- ---help---
- TI AR7 partitioning support
-
-+config MTD_WRT160NL_PARTS
-+ tristate "Linksys WRT160NL partitioning support"
-+ depends on MTD_PARTITIONS && ATH79_MACH_WRT160NL
-+ ---help---
-+ Linksys WRT160NL partitioning support
-+
- config MTD_MYLOADER_PARTS
- tristate "MyLoader partition parsing"
- depends on ADM5120 || ATHEROS_AR231X || ATHEROS_AR71XX || ATH79
---- a/drivers/mtd/Makefile
-+++ b/drivers/mtd/Makefile
-@@ -11,6 +11,7 @@ obj-$(CONFIG_MTD_REDBOOT_PARTS) += redbo
- obj-$(CONFIG_MTD_CMDLINE_PARTS) += cmdlinepart.o
- obj-$(CONFIG_MTD_AFS_PARTS) += afs.o
- obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o
-+obj-$(CONFIG_MTD_WRT160NL_PARTS) += wrt160nl_part.o
- obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o
-
- # 'Users' - code which presents functionality to userspace.
+++ /dev/null
---- a/drivers/mtd/Kconfig
-+++ b/drivers/mtd/Kconfig
-@@ -150,7 +150,7 @@ config MTD_AR7_PARTS
-
- config MTD_WRT160NL_PARTS
- tristate "Linksys WRT160NL partitioning support"
-- depends on MTD_PARTITIONS && ATH79_MACH_WRT160NL
-+ depends on ATH79_MACH_WRT160NL
- ---help---
- Linksys WRT160NL partitioning support
-
-@@ -170,6 +170,12 @@ config MTD_MYLOADER_PARTS
- You will still need the parsing functions to be called by the driver
- for your particular device. It won't happen automatically.
-
-+config MTD_TPLINK_PARTS
-+ tristate "TP-Link AR7XXX/AR9XXX partitioning support"
-+ depends on ATH79
-+ ---help---
-+ TBD.
-+
- comment "User Modules And Translation Layers"
-
- config MTD_CHAR
---- a/drivers/mtd/Makefile
-+++ b/drivers/mtd/Makefile
-@@ -13,6 +13,7 @@ obj-$(CONFIG_MTD_AFS_PARTS) += afs.o
- obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o
- obj-$(CONFIG_MTD_WRT160NL_PARTS) += wrt160nl_part.o
- obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o
-+obj-$(CONFIG_MTD_TPLINK_PARTS) += tplinkpart.o
-
- # 'Users' - code which presents functionality to userspace.
- obj-$(CONFIG_MTD_CHAR) += mtdchar.o
+++ /dev/null
---- a/drivers/mtd/devices/m25p80.c
-+++ b/drivers/mtd/devices/m25p80.c
-@@ -100,6 +100,7 @@ struct m25p {
- u16 addr_width;
- u8 erase_opcode;
- u8 *command;
-+ size_t max_read_len;
- };
-
- static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd)
-@@ -352,6 +353,7 @@ static int m25p80_read(struct mtd_info *
- struct m25p *flash = mtd_to_m25p(mtd);
- struct spi_transfer t[2];
- struct spi_message m;
-+ loff_t ofs;
-
- pr_debug("%s: %s from 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
- __func__, (u32)from, len);
-@@ -374,8 +376,6 @@ static int m25p80_read(struct mtd_info *
- t[0].len = m25p_cmdsz(flash) + FAST_READ_DUMMY_BYTE;
- spi_message_add_tail(&t[0], &m);
-
-- t[1].rx_buf = buf;
-- t[1].len = len;
- spi_message_add_tail(&t[1], &m);
-
- /* Byte count starts at zero. */
-@@ -383,13 +383,6 @@ static int m25p80_read(struct mtd_info *
-
- mutex_lock(&flash->lock);
-
-- /* Wait till previous write/erase is done. */
-- if (wait_till_ready(flash)) {
-- /* REVISIT status return?? */
-- mutex_unlock(&flash->lock);
-- return 1;
-- }
--
- /* FIXME switch to OPCODE_FAST_READ. It's required for higher
- * clocks; and at this writing, every chip this driver handles
- * supports that opcode.
-@@ -397,11 +390,44 @@ static int m25p80_read(struct mtd_info *
-
- /* Set up the write data buffer. */
- flash->command[0] = OPCODE_READ;
-- m25p_addr2cmd(flash, from, flash->command);
-
-- spi_sync(flash->spi, &m);
-+ ofs = 0;
-+ while (len) {
-+ size_t readlen;
-+ size_t done;
-+ int ret;
-+
-+ ret = wait_till_ready(flash);
-+ if (ret) {
-+ mutex_unlock(&flash->lock);
-+ return 1;
-+ }
-+
-+ if (flash->max_read_len > 0 &&
-+ flash->max_read_len < len)
-+ readlen = flash->max_read_len;
-+ else
-+ readlen = len;
-+
-+ t[1].rx_buf = buf + ofs;
-+ t[1].len = readlen;
-+
-+ m25p_addr2cmd(flash, from + ofs, flash->command);
-+
-+ spi_sync(flash->spi, &m);
-
-- *retlen = m.actual_length - m25p_cmdsz(flash) - FAST_READ_DUMMY_BYTE;
-+ done = m.actual_length - m25p_cmdsz(flash) -
-+ FAST_READ_DUMMY_BYTE;
-+ if (done != readlen) {
-+ mutex_unlock(&flash->lock);
-+ return 1;
-+ }
-+
-+ ofs += done;
-+ len -= done;
-+ }
-+
-+ *retlen = ofs;
-
- mutex_unlock(&flash->lock);
-
-@@ -924,6 +950,12 @@ static int __devinit m25p_probe(struct s
- flash->mtd.erase = m25p80_erase;
- flash->mtd.read = m25p80_read;
-
-+ if (data && data->max_read_len) {
-+ flash->max_read_len = data->max_read_len;
-+ dev_warn(&spi->dev, "max_read_len set to %d bytes\n",
-+ flash->max_read_len);
-+ }
-+
- /* sst flash chips use AAI word program */
- if (JEDEC_MFR(info->jedec_id) == CFI_MFR_SST)
- flash->mtd.write = sst_write;
---- a/include/linux/spi/flash.h
-+++ b/include/linux/spi/flash.h
-@@ -25,6 +25,7 @@ struct flash_platform_data {
-
- char *type;
-
-+ size_t max_read_len;
- /* we'll likely add more ... use JEDEC IDs, etc */
- };
-
+++ /dev/null
---- a/drivers/mtd/devices/m25p80.c
-+++ b/drivers/mtd/devices/m25p80.c
-@@ -1016,7 +1016,9 @@ static int __devinit m25p_probe(struct s
- /* partitions should match sector boundaries; and it may be good to
- * use readonly partitions for writeprotected sectors (BP2..BP0).
- */
-- return mtd_device_parse_register(&flash->mtd, NULL, &ppdata,
-+ return mtd_device_parse_register(&flash->mtd,
-+ data ? data->part_probes : NULL,
-+ &ppdata,
- data ? data->parts : NULL,
- data ? data->nr_parts : 0);
- }
---- a/include/linux/spi/flash.h
-+++ b/include/linux/spi/flash.h
-@@ -24,6 +24,7 @@ struct flash_platform_data {
- unsigned int nr_parts;
-
- char *type;
-+ const char **part_probes;
-
- size_t max_read_len;
- /* we'll likely add more ... use JEDEC IDs, etc */
+++ /dev/null
---- a/drivers/mtd/redboot.c
-+++ b/drivers/mtd/redboot.c
-@@ -79,31 +79,32 @@ static int parse_redboot_partitions(stru
- static char nullstring[] = "unallocated";
- #endif
-
-+ buf = vmalloc(master->erasesize);
-+ if (!buf)
-+ return -ENOMEM;
-+
-+ restart:
- if ( directory < 0 ) {
- offset = master->size + directory * master->erasesize;
-- while (master->block_isbad &&
-+ while (master->block_isbad &&
- master->block_isbad(master, offset)) {
- if (!offset) {
- nogood:
- printk(KERN_NOTICE "Failed to find a non-bad block to check for RedBoot partition table\n");
-+ vfree(buf);
- return -EIO;
- }
- offset -= master->erasesize;
- }
- } else {
- offset = directory * master->erasesize;
-- while (master->block_isbad &&
-+ while (master->block_isbad &&
- master->block_isbad(master, offset)) {
- offset += master->erasesize;
- if (offset == master->size)
- goto nogood;
- }
- }
-- buf = vmalloc(master->erasesize);
--
-- if (!buf)
-- return -ENOMEM;
--
- printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n",
- master->name, offset);
-
-@@ -175,6 +176,11 @@ static int parse_redboot_partitions(stru
- }
- if (i == numslots) {
- /* Didn't find it */
-+ if (offset + master->erasesize < master->size) {
-+ /* not at the end of the flash yet, maybe next block :) */
-+ directory++;
-+ goto restart;
-+ }
- printk(KERN_NOTICE "No RedBoot partition table detected in %s\n",
- master->name);
- ret = 0;
+++ /dev/null
---- a/drivers/mtd/nand/Kconfig
-+++ b/drivers/mtd/nand/Kconfig
-@@ -537,4 +537,8 @@ config MTD_NAND_FSMC
- Enables support for NAND Flash chips on the ST Microelectronics
- Flexible Static Memory Controller (FSMC)
-
-+config MTD_NAND_RB4XX
-+ tristate "NAND flash driver for RouterBoard 4xx series"
-+ depends on MTD_NAND && ATH79_MACH_RB4XX
-+
- endif # MTD_NAND
---- a/drivers/mtd/nand/Makefile
-+++ b/drivers/mtd/nand/Makefile
-@@ -33,6 +33,7 @@ obj-$(CONFIG_MTD_NAND_CM_X270) += cmx27
- obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o
- obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o
- obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o
-+obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o
- obj-$(CONFIG_MTD_ALAUDA) += alauda.o
- obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o
- obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o
+++ /dev/null
---- a/drivers/mtd/nand/Kconfig
-+++ b/drivers/mtd/nand/Kconfig
-@@ -541,4 +541,8 @@ config MTD_NAND_RB4XX
- tristate "NAND flash driver for RouterBoard 4xx series"
- depends on MTD_NAND && ATH79_MACH_RB4XX
-
-+config MTD_NAND_RB750
-+ tristate "NAND flash driver for the RouterBoard 750"
-+ depends on MTD_NAND && ATH79_MACH_RB750
-+
- endif # MTD_NAND
---- a/drivers/mtd/nand/Makefile
-+++ b/drivers/mtd/nand/Makefile
-@@ -34,6 +34,7 @@ obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx
- obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o
- obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o
- obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o
-+obj-$(CONFIG_MTD_NAND_RB750) += rb750_nand.o
- obj-$(CONFIG_MTD_ALAUDA) += alauda.o
- obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o
- obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o
+++ /dev/null
---- a/drivers/mtd/chips/cfi_cmdset_0002.c
-+++ b/drivers/mtd/chips/cfi_cmdset_0002.c
-@@ -39,7 +39,7 @@
- #include <linux/mtd/xip.h>
-
- #define AMD_BOOTLOC_BUG
--#define FORCE_WORD_WRITE 0
-+#define FORCE_WORD_WRITE 1
-
- #define MAX_WORD_RETRIES 3
-
-@@ -50,7 +50,9 @@
-
- static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
- static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
-+#if !FORCE_WORD_WRITE
- static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
-+#endif
- static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *);
- static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *);
- static void cfi_amdstd_sync (struct mtd_info *);
-@@ -183,6 +185,7 @@ static void fixup_amd_bootblock(struct m
- }
- #endif
-
-+#if !FORCE_WORD_WRITE
- static void fixup_use_write_buffers(struct mtd_info *mtd)
- {
- struct map_info *map = mtd->priv;
-@@ -192,6 +195,7 @@ static void fixup_use_write_buffers(stru
- mtd->write = cfi_amdstd_write_buffers;
- }
- }
-+#endif /* !FORCE_WORD_WRITE */
-
- /* Atmel chips don't use the same PRI format as AMD chips */
- static void fixup_convert_atmel_pri(struct mtd_info *mtd)
-@@ -1374,6 +1378,7 @@ static int cfi_amdstd_write_words(struct
- /*
- * FIXME: interleaved mode not tested, and probably not supported!
- */
-+#if !FORCE_WORD_WRITE
- static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
- unsigned long adr, const u_char *buf,
- int len)
-@@ -1485,7 +1490,6 @@ static int __xipram do_write_buffer(stru
- return ret;
- }
-
--
- static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len,
- size_t *retlen, const u_char *buf)
- {
-@@ -1564,6 +1568,7 @@ static int cfi_amdstd_write_buffers(stru
-
- return 0;
- }
-+#endif /* !FORCE_WORD_WRITE */
-
- /*
- * Handle devices with one erase region, that only implement
+++ /dev/null
---- a/drivers/mtd/devices/m25p80.c
-+++ b/drivers/mtd/devices/m25p80.c
-@@ -977,6 +977,7 @@ static int __devinit m25p_probe(struct s
- if (info->flags & M25P_NO_ERASE)
- flash->mtd.flags |= MTD_NO_ERASE;
-
-+ memset(&ppdata, '\0', sizeof(ppdata));
- ppdata.of_node = spi->dev.of_node;
- flash->mtd.dev.parent = &spi->dev;
- flash->page_size = info->page_size;
+++ /dev/null
---- a/drivers/net/ethernet/atheros/Kconfig
-+++ b/drivers/net/ethernet/atheros/Kconfig
-@@ -5,7 +5,7 @@
- config NET_VENDOR_ATHEROS
- bool "Atheros devices"
- default y
-- depends on PCI
-+ depends on (PCI || ATH79)
- ---help---
- If you have a network (Ethernet) card belonging to this class, say Y
- and read the Ethernet-HOWTO, available from
-@@ -67,4 +67,6 @@ config ATL1C
- To compile this driver as a module, choose M here. The module
- will be called atl1c.
-
-+source drivers/net/ethernet/atheros/ag71xx/Kconfig
-+
- endif # NET_VENDOR_ATHEROS
---- a/drivers/net/ethernet/atheros/Makefile
-+++ b/drivers/net/ethernet/atheros/Makefile
-@@ -2,6 +2,7 @@
- # Makefile for the Atheros network device drivers.
- #
-
-+obj-$(CONFIG_AG71XX) += ag71xx/
- obj-$(CONFIG_ATL1) += atlx/
- obj-$(CONFIG_ATL2) += atlx/
- obj-$(CONFIG_ATL1E) += atl1e/
+++ /dev/null
---- a/net/dsa/tag_trailer.c
-+++ b/net/dsa/tag_trailer.c
-@@ -87,7 +87,7 @@ static int trailer_rcv(struct sk_buff *s
-
- trailer = skb_tail_pointer(skb) - 4;
- if (trailer[0] != 0x80 || (trailer[1] & 0xf8) != 0x00 ||
-- (trailer[3] & 0xef) != 0x00 || trailer[3] != 0x00)
-+ (trailer[2] & 0xef) != 0x00 || (trailer[3] & 0xfe) != 0x00)
- goto out_drop;
-
- source_port = trailer[1] & 7;
+++ /dev/null
---- a/net/dsa/Kconfig
-+++ b/net/dsa/Kconfig
-@@ -36,6 +36,13 @@ config NET_DSA_MV88E6060
- This enables support for the Marvell 88E6060 ethernet switch
- chip.
-
-+config NET_DSA_MV88E6063
-+ bool "Marvell 88E6063 ethernet switch chip support"
-+ select NET_DSA_TAG_TRAILER
-+ ---help---
-+ This enables support for the Marvell 88E6063 ethernet switch
-+ chip
-+
- config NET_DSA_MV88E6XXX_NEED_PPU
- bool
- default n
---- a/net/dsa/Makefile
-+++ b/net/dsa/Makefile
-@@ -6,6 +6,7 @@ obj-$(CONFIG_NET_DSA_TAG_TRAILER) += tag
- # switch drivers
- obj-$(CONFIG_NET_DSA_MV88E6XXX) += mv88e6xxx.o
- obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o
-+obj-$(CONFIG_NET_DSA_MV88E6063) += mv88e6063.o
- obj-$(CONFIG_NET_DSA_MV88E6123_61_65) += mv88e6123_61_65.o
- obj-$(CONFIG_NET_DSA_MV88E6131) += mv88e6131.o
-
+++ /dev/null
---- a/drivers/Makefile
-+++ b/drivers/Makefile
-@@ -51,8 +51,8 @@ obj-$(CONFIG_IDE) += ide/
- obj-$(CONFIG_SCSI) += scsi/
- obj-$(CONFIG_ATA) += ata/
- obj-$(CONFIG_TARGET_CORE) += target/
--obj-$(CONFIG_MTD) += mtd/
- obj-$(CONFIG_SPI) += spi/
-+obj-$(CONFIG_MTD) += mtd/
- obj-y += net/
- obj-$(CONFIG_ATM) += atm/
- obj-$(CONFIG_FUSION) += message/
+++ /dev/null
---- a/include/linux/spi/spi.h
-+++ b/include/linux/spi/spi.h
-@@ -441,6 +441,8 @@ struct spi_transfer {
- dma_addr_t rx_dma;
-
- unsigned cs_change:1;
-+ unsigned verify:1;
-+ unsigned fast_write:1;
- u8 bits_per_word;
- u16 delay_usecs;
- u32 speed_hz;
-@@ -482,6 +484,7 @@ struct spi_message {
- struct spi_device *spi;
-
- unsigned is_dma_mapped:1;
-+ unsigned fast_read:1;
-
- /* REVISIT: we might want a flag affecting the behavior of the
- * last transfer ... allowing things like "read 16 bit length L"
+++ /dev/null
---- a/drivers/spi/Kconfig
-+++ b/drivers/spi/Kconfig
-@@ -289,6 +289,12 @@ config SPI_PXA2XX
- config SPI_PXA2XX_PCI
- def_bool SPI_PXA2XX && X86_32 && PCI
-
-+config SPI_RB4XX
-+ tristate "Mikrotik RB4XX SPI master"
-+ depends on SPI_MASTER && ATH79_MACH_RB4XX
-+ help
-+ SPI controller driver for the Mikrotik RB4xx series boards.
-+
- config SPI_S3C24XX
- tristate "Samsung S3C24XX series SPI"
- depends on ARCH_S3C2410 && EXPERIMENTAL
---- a/drivers/spi/Makefile
-+++ b/drivers/spi/Makefile
-@@ -45,6 +45,7 @@ obj-$(CONFIG_SPI_PL022) += spi-pl022.o
- obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o
- obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx.o
- obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o
-+obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o
- obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o
- spi-s3c24xx-hw-y := spi-s3c24xx.o
- spi-s3c24xx-hw-$(CONFIG_SPI_S3C24XX_FIQ) += spi-s3c24xx-fiq.o
+++ /dev/null
---- a/drivers/spi/Kconfig
-+++ b/drivers/spi/Kconfig
-@@ -441,6 +441,13 @@ config SPI_TLE62X0
- sysfs interface, with each line presented as a kind of GPIO
- exposing both switch control and diagnostic feedback.
-
-+config SPI_RB4XX_CPLD
-+ tristate "MikroTik RB4XX CPLD driver"
-+ depends on ATH79_MACH_RB4XX
-+ help
-+ SPI driver for the Xilinx CPLD chip present on the
-+ MikroTik RB4xx boards.
-+
- #
- # Add new SPI protocol masters in alphabetical order above this line
- #
---- a/drivers/spi/Makefile
-+++ b/drivers/spi/Makefile
-@@ -46,6 +46,7 @@ obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.
- obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx.o
- obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o
- obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o
-+obj-$(CONFIG_SPI_RB4XX_CPLD) += spi-rb4xx-cpld.o
- obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o
- spi-s3c24xx-hw-y := spi-s3c24xx.o
- spi-s3c24xx-hw-$(CONFIG_SPI_S3C24XX_FIQ) += spi-s3c24xx-fiq.o
+++ /dev/null
---- a/drivers/spi/Makefile
-+++ b/drivers/spi/Makefile
-@@ -12,6 +12,7 @@ obj-$(CONFIG_SPI_SPIDEV) += spidev.o
- # SPI master controller drivers (bus)
- obj-$(CONFIG_SPI_ALTERA) += spi-altera.o
- obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o
-+obj-$(CONFIG_SPI_AP83) += spi-ap83.o
- obj-$(CONFIG_SPI_ATH79) += spi-ath79.o
- obj-$(CONFIG_SPI_AU1550) += spi-au1550.o
- obj-$(CONFIG_SPI_BFIN) += spi-bfin5xx.o
---- a/drivers/spi/Kconfig
-+++ b/drivers/spi/Kconfig
-@@ -59,6 +59,14 @@ config SPI_ALTERA
- help
- This is the driver for the Altera SPI Controller.
-
-+config SPI_AP83
-+ tristate "Atheros AP83 specific SPI Controller"
-+ depends on SPI_MASTER && ATH79_MACH_AP83
-+ select SPI_BITBANG
-+ help
-+ This is a specific SPI controller driver for the Atheros AP83
-+ reference board.
-+
- config SPI_ATH79
- tristate "Atheros AR71XX/AR724X/AR913X SPI controller driver"
- depends on ATH79 && GENERIC_GPIO
+++ /dev/null
---- a/drivers/spi/Kconfig
-+++ b/drivers/spi/Kconfig
-@@ -456,6 +456,11 @@ config SPI_RB4XX_CPLD
- SPI driver for the Xilinx CPLD chip present on the
- MikroTik RB4xx boards.
-
-+config SPI_VSC7385
-+ tristate "Vitesse VSC7385 ethernet switch driver"
-+ help
-+ SPI driver for the Vitesse VSC7385 ethernet switch.
-+
- #
- # Add new SPI protocol masters in alphabetical order above this line
- #
---- a/drivers/spi/Makefile
-+++ b/drivers/spi/Makefile
-@@ -61,5 +61,5 @@ obj-$(CONFIG_SPI_TI_SSP) += spi-ti-ssp.
- obj-$(CONFIG_SPI_TLE62X0) += spi-tle62x0.o
- obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o
- obj-$(CONFIG_SPI_TXX9) += spi-txx9.o
-+obj-$(CONFIG_SPI_VSC7385) += spi-vsc7385.o
- obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o
--
+++ /dev/null
---- a/drivers/leds/Kconfig
-+++ b/drivers/leds/Kconfig
-@@ -395,6 +395,13 @@ config LEDS_TRIGGERS
- These triggers allow kernel events to drive the LEDs and can
- be configured via sysfs. If unsure, say Y.
-
-+config LEDS_WNDR3700_USB
-+ tristate "NETGEAR WNDR3700 USB LED driver"
-+ depends on LEDS_CLASS && ATH79_MACH_WNDR3700
-+ help
-+ This option enables support for the USB LED found on the
-+ NETGEAR WNDR3700 board.
-+
- comment "LED Triggers"
-
- config LEDS_TRIGGER_TIMER
---- a/drivers/leds/Makefile
-+++ b/drivers/leds/Makefile
-@@ -33,6 +33,7 @@ obj-$(CONFIG_LEDS_DA903X) += leds-da903
- obj-$(CONFIG_LEDS_WM831X_STATUS) += leds-wm831x-status.o
- obj-$(CONFIG_LEDS_WM8350) += leds-wm8350.o
- obj-$(CONFIG_LEDS_PWM) += leds-pwm.o
-+obj-${CONFIG_LEDS_WNDR3700_USB} += leds-wndr3700-usb.o
- obj-$(CONFIG_LEDS_REGULATOR) += leds-regulator.o
- obj-$(CONFIG_LEDS_INTEL_SS4200) += leds-ss4200.o
- obj-$(CONFIG_LEDS_LT3593) += leds-lt3593.o
+++ /dev/null
---- a/drivers/leds/Kconfig
-+++ b/drivers/leds/Kconfig
-@@ -402,6 +402,10 @@ config LEDS_WNDR3700_USB
- This option enables support for the USB LED found on the
- NETGEAR WNDR3700 board.
-
-+config LEDS_RB750
-+ tristate "LED driver for the Mikrotik RouterBOARD 750"
-+ depends on LEDS_CLASS && ATH79_MACH_RB750
-+
- comment "LED Triggers"
-
- config LEDS_TRIGGER_TIMER
---- a/drivers/leds/Makefile
-+++ b/drivers/leds/Makefile
-@@ -40,6 +40,7 @@ obj-$(CONFIG_LEDS_LT3593) += leds-lt359
- obj-$(CONFIG_LEDS_ADP5520) += leds-adp5520.o
- obj-$(CONFIG_LEDS_DELL_NETBOOKS) += dell-led.o
- obj-$(CONFIG_LEDS_MC13783) += leds-mc13783.o
-+obj-$(CONFIG_LEDS_RB750) += leds-rb750.o
- obj-$(CONFIG_LEDS_NS2) += leds-ns2.o
- obj-$(CONFIG_LEDS_NETXBIG) += leds-netxbig.o
- obj-$(CONFIG_LEDS_ASIC3) += leds-asic3.o
+++ /dev/null
---- a/drivers/gpio/Kconfig
-+++ b/drivers/gpio/Kconfig
-@@ -489,4 +489,13 @@ config GPIO_TPS65910
- help
- Select this option to enable GPIO driver for the TPS65910
- chip family.
-+
-+comment "Other GPIO expanders"
-+
-+config GPIO_NXP_74HC153
-+ tristate "NXP 74HC153 Dual 4-input multiplexer"
-+ help
-+ Platform driver for NXP 74HC153 Dual 4-input Multiplexer. This
-+ provides a GPIO interface supporting input mode only.
-+
- endif
---- a/drivers/gpio/Makefile
-+++ b/drivers/gpio/Makefile
-@@ -35,6 +35,7 @@ obj-$(CONFIG_GPIO_MSM_V2) += gpio-msm-v2
- obj-$(CONFIG_GPIO_MXC) += gpio-mxc.o
- obj-$(CONFIG_GPIO_MXS) += gpio-mxs.o
- obj-$(CONFIG_PLAT_NOMADIK) += gpio-nomadik.o
-+obj-$(CONFIG_GPIO_NXP_74HC153) += gpio-nxp-74hc153.o
- obj-$(CONFIG_ARCH_OMAP) += gpio-omap.o
- obj-$(CONFIG_GPIO_PCA953X) += gpio-pca953x.o
- obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf857x.o
+++ /dev/null
---- a/drivers/spi/spi-bitbang.c
-+++ b/drivers/spi/spi-bitbang.c
-@@ -234,13 +234,14 @@ void spi_bitbang_cleanup(struct spi_devi
- }
- EXPORT_SYMBOL_GPL(spi_bitbang_cleanup);
-
--static int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t)
-+int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t)
- {
- struct spi_bitbang_cs *cs = spi->controller_state;
- unsigned nsecs = cs->nsecs;
-
- return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t);
- }
-+EXPORT_SYMBOL_GPL(spi_bitbang_bufs);
-
- /*----------------------------------------------------------------------*/
-
---- a/include/linux/spi/spi_bitbang.h
-+++ b/include/linux/spi/spi_bitbang.h
-@@ -44,6 +44,7 @@ extern void spi_bitbang_cleanup(struct s
- extern int spi_bitbang_transfer(struct spi_device *spi, struct spi_message *m);
- extern int spi_bitbang_setup_transfer(struct spi_device *spi,
- struct spi_transfer *t);
-+extern int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t);
-
- /* start or stop queue processing */
- extern int spi_bitbang_start(struct spi_bitbang *spi);
+++ /dev/null
---- a/include/linux/spi/spi.h
-+++ b/include/linux/spi/spi.h
-@@ -344,6 +344,12 @@ extern struct spi_master *spi_busnum_to_
-
- /*---------------------------------------------------------------------------*/
-
-+enum spi_transfer_type {
-+ SPI_TRANSFER_GENERIC = 0,
-+ SPI_TRANSFER_FLASH_READ_CMD,
-+ SPI_TRANSFER_FLASH_READ_DATA,
-+};
-+
- /*
- * I/O INTERFACE between SPI controller and protocol drivers
- *
-@@ -446,6 +452,7 @@ struct spi_transfer {
- u8 bits_per_word;
- u16 delay_usecs;
- u32 speed_hz;
-+ enum spi_transfer_type type;
-
- struct list_head transfer_list;
- };
+++ /dev/null
---- a/drivers/mtd/devices/m25p80.c
-+++ b/drivers/mtd/devices/m25p80.c
-@@ -372,10 +372,12 @@ static int m25p80_read(struct mtd_info *
- * OPCODE_FAST_READ (if available) is faster.
- * Should add 1 byte DUMMY_BYTE.
- */
-+ t[0].type = SPI_TRANSFER_FLASH_READ_CMD;
- t[0].tx_buf = flash->command;
- t[0].len = m25p_cmdsz(flash) + FAST_READ_DUMMY_BYTE;
- spi_message_add_tail(&t[0], &m);
-
-+ t[1].type = SPI_TRANSFER_FLASH_READ_DATA;
- spi_message_add_tail(&t[1], &m);
-
- /* Byte count starts at zero. */
+++ /dev/null
---- a/drivers/spi/spi-ath79.c
-+++ b/drivers/spi/spi-ath79.c
-@@ -37,6 +37,11 @@
-
- #define ATH79_SPI_CS_LINE_MAX 2
-
-+enum ath79_spi_state {
-+ ATH79_SPI_STATE_WAIT_CMD = 0,
-+ ATH79_SPI_STATE_WAIT_READ,
-+};
-+
- struct ath79_spi {
- struct spi_bitbang bitbang;
- u32 ioc_base;
-@@ -44,6 +49,11 @@ struct ath79_spi {
- void __iomem *base;
- struct clk *clk;
- unsigned rrw_delay;
-+
-+ enum ath79_spi_state state;
-+ u32 clk_div;
-+ unsigned long read_addr;
-+ unsigned long ahb_rate;
- };
-
- static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg)
-@@ -108,9 +118,6 @@ static void ath79_spi_enable(struct ath7
- /* save CTRL register */
- sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
- sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
--
-- /* TODO: setup speed? */
-- ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
- }
-
- static void ath79_spi_disable(struct ath79_spi *sp)
-@@ -222,6 +229,110 @@ static u32 ath79_spi_txrx_mode0(struct s
- return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
- }
-
-+static int ath79_spi_do_read_flash_data(struct spi_device *spi,
-+ struct spi_transfer *t)
-+{
-+ struct ath79_spi *sp = ath79_spidev_to_sp(spi);
-+
-+ /* disable GPIO mode */
-+ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
-+
-+ memcpy_fromio(t->rx_buf, sp->base + sp->read_addr, t->len);
-+
-+ /* enable GPIO mode */
-+ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
-+
-+ /* restore IOC register */
-+ ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
-+
-+ return t->len;
-+}
-+
-+static int ath79_spi_do_read_flash_cmd(struct spi_device *spi,
-+ struct spi_transfer *t)
-+{
-+ struct ath79_spi *sp = ath79_spidev_to_sp(spi);
-+ int len;
-+ const u8 *p;
-+
-+ sp->read_addr = 0;
-+
-+ len = t->len - 1;
-+ p = t->tx_buf;
-+
-+ while (len--) {
-+ p++;
-+ sp->read_addr <<= 8;
-+ sp->read_addr |= *p;
-+ }
-+
-+ return t->len;
-+}
-+
-+static bool ath79_spi_is_read_cmd(struct spi_device *spi,
-+ struct spi_transfer *t)
-+{
-+ return t->type == SPI_TRANSFER_FLASH_READ_CMD;
-+}
-+
-+static bool ath79_spi_is_data_read(struct spi_device *spi,
-+ struct spi_transfer *t)
-+{
-+ return t->type == SPI_TRANSFER_FLASH_READ_DATA;
-+}
-+
-+static int ath79_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
-+{
-+ struct ath79_spi *sp = ath79_spidev_to_sp(spi);
-+ int ret;
-+
-+ switch (sp->state) {
-+ case ATH79_SPI_STATE_WAIT_CMD:
-+ if (ath79_spi_is_read_cmd(spi, t)) {
-+ ret = ath79_spi_do_read_flash_cmd(spi, t);
-+ sp->state = ATH79_SPI_STATE_WAIT_READ;
-+ } else {
-+ ret = spi_bitbang_bufs(spi, t);
-+ }
-+ break;
-+
-+ case ATH79_SPI_STATE_WAIT_READ:
-+ if (ath79_spi_is_data_read(spi, t)) {
-+ ret = ath79_spi_do_read_flash_data(spi, t);
-+ } else {
-+ dev_warn(&spi->dev, "flash data read expected\n");
-+ ret = -EIO;
-+ }
-+ sp->state = ATH79_SPI_STATE_WAIT_CMD;
-+ break;
-+
-+ default:
-+ BUG();
-+ }
-+
-+ return ret;
-+}
-+
-+static int ath79_spi_setup_transfer(struct spi_device *spi,
-+ struct spi_transfer *t)
-+{
-+ struct ath79_spi *sp = ath79_spidev_to_sp(spi);
-+ struct ath79_spi_controller_data *cdata;
-+ int ret;
-+
-+ ret = spi_bitbang_setup_transfer(spi, t);
-+ if (ret)
-+ return ret;
-+
-+ cdata = spi->controller_data;
-+ if (cdata->is_flash)
-+ sp->bitbang.txrx_bufs = ath79_spi_txrx_bufs;
-+ else
-+ sp->bitbang.txrx_bufs = spi_bitbang_bufs;
-+
-+ return ret;
-+}
-+
- static __devinit int ath79_spi_probe(struct platform_device *pdev)
- {
- struct spi_master *master;
-@@ -244,6 +355,8 @@ static __devinit int ath79_spi_probe(str
- sp = spi_master_get_devdata(master);
- platform_set_drvdata(pdev, sp);
-
-+ sp->state = ATH79_SPI_STATE_WAIT_CMD;
-+
- master->setup = ath79_spi_setup;
- master->cleanup = ath79_spi_cleanup;
- master->bus_num = pdata->bus_num;
-@@ -252,7 +365,7 @@ static __devinit int ath79_spi_probe(str
- sp->bitbang.master = spi_master_get(master);
- sp->bitbang.chipselect = ath79_spi_chipselect;
- sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
-- sp->bitbang.setup_transfer = spi_bitbang_setup_transfer;
-+ sp->bitbang.setup_transfer = ath79_spi_setup_transfer;
- sp->bitbang.flags = SPI_CS_HIGH;
-
- r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-@@ -277,7 +390,8 @@ static __devinit int ath79_spi_probe(str
- if (ret)
- goto err_clk_put;
-
-- rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
-+ sp->ahb_rate = clk_get_rate(sp->clk);
-+ rate = DIV_ROUND_UP(sp->ahb_rate, MHZ);
- if (!rate) {
- ret = -EINVAL;
- goto err_clk_disable;
---- a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
-+++ b/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
-@@ -24,6 +24,7 @@ enum ath79_spi_cs_type {
- struct ath79_spi_controller_data {
- enum ath79_spi_cs_type cs_type;
- unsigned cs_line;
-+ bool is_flash;
- };
-
- #endif /* _ATH79_SPI_PLATFORM_H */
+++ /dev/null
---- a/arch/mips/Makefile
-+++ b/arch/mips/Makefile
-@@ -174,6 +174,7 @@ endif
- #
- libs-$(CONFIG_ARC) += arch/mips/fw/arc/
- libs-$(CONFIG_CFE) += arch/mips/fw/cfe/
-+libs-$(CONFIG_MYLOADER) += arch/mips/fw/myloader/
- libs-$(CONFIG_SNIPROM) += arch/mips/fw/sni/
- libs-y += arch/mips/fw/lib/
-
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -953,6 +953,9 @@ config MIPS_NILE4
- config MIPS_DISABLE_OBSOLETE_IDE
- bool
-
-+config MYLOADER
-+ bool
-+
- config SYNC_R4K
- bool
-
+++ /dev/null
---- a/arch/mips/ath79/dev-wmac.c
-+++ b/arch/mips/ath79/dev-wmac.c
-@@ -15,6 +15,7 @@
- #include <linux/init.h>
- #include <linux/delay.h>
- #include <linux/irq.h>
-+#include <linux/etherdevice.h>
- #include <linux/platform_device.h>
- #include <linux/ath9k_platform.h>
-
-@@ -22,6 +23,7 @@
- #include <asm/mach-ath79/ar71xx_regs.h>
- #include "dev-wmac.h"
-
-+static u8 ath79_wmac_mac[ETH_ALEN];
- static struct ath9k_platform_data ath79_wmac_data;
-
- static struct resource ath79_wmac_resources[] = {
-@@ -116,7 +118,7 @@ static void ar934x_wmac_setup(void)
- ath79_wmac_data.is_clk_25mhz = true;
- }
-
--void __init ath79_register_wmac(u8 *cal_data)
-+void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr)
- {
- if (soc_is_ar913x())
- ar913x_wmac_setup();
-@@ -131,5 +133,10 @@ void __init ath79_register_wmac(u8 *cal_
- memcpy(ath79_wmac_data.eeprom_data, cal_data,
- sizeof(ath79_wmac_data.eeprom_data));
-
-+ if (mac_addr) {
-+ memcpy(ath79_wmac_mac, mac_addr, sizeof(ath79_wmac_mac));
-+ ath79_wmac_data.macaddr = ath79_wmac_mac;
-+ }
-+
- platform_device_register(&ath79_wmac_device);
- }
---- a/arch/mips/ath79/dev-wmac.h
-+++ b/arch/mips/ath79/dev-wmac.h
-@@ -12,6 +12,6 @@
- #ifndef _ATH79_DEV_WMAC_H
- #define _ATH79_DEV_WMAC_H
-
--void ath79_register_wmac(u8 *cal_data);
-+void ath79_register_wmac(u8 *cal_data, u8 *mac_addr);
-
- #endif /* _ATH79_DEV_WMAC_H */
---- a/arch/mips/ath79/mach-ap81.c
-+++ b/arch/mips/ath79/mach-ap81.c
-@@ -98,7 +98,7 @@ static void __init ap81_setup(void)
- ap81_gpio_keys);
- ath79_register_spi(&ap81_spi_data, ap81_spi_info,
- ARRAY_SIZE(ap81_spi_info));
-- ath79_register_wmac(cal_data);
-+ ath79_register_wmac(cal_data, NULL);
- ath79_register_usb();
- }
-
---- a/arch/mips/ath79/mach-db120.c
-+++ b/arch/mips/ath79/mach-db120.c
-@@ -153,7 +153,7 @@ static void __init db120_setup(void)
- ath79_register_spi(&db120_spi_data, db120_spi_info,
- ARRAY_SIZE(db120_spi_info));
- ath79_register_usb();
-- ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET);
-+ ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET, NULL);
- db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET);
- }
-
---- a/arch/mips/ath79/mach-ap121.c
-+++ b/arch/mips/ath79/mach-ap121.c
-@@ -91,7 +91,7 @@ static void __init ap121_setup(void)
- ath79_register_spi(&ap121_spi_data, ap121_spi_info,
- ARRAY_SIZE(ap121_spi_info));
- ath79_register_usb();
-- ath79_register_wmac(cal_data);
-+ ath79_register_wmac(cal_data, NULL);
- }
-
- MIPS_MACHINE(ATH79_MACH_AP121, "AP121", "Atheros AP121 reference board",
+++ /dev/null
---- a/arch/mips/ath79/gpio.c
-+++ b/arch/mips/ath79/gpio.c
-@@ -25,7 +25,9 @@
- #include <asm/mach-ath79/ath79.h>
- #include "common.h"
-
--static void __iomem *ath79_gpio_base;
-+void __iomem *ath79_gpio_base;
-+EXPORT_SYMBOL_GPL(ath79_gpio_base);
-+
- static unsigned long ath79_gpio_count;
- static DEFINE_SPINLOCK(ath79_gpio_lock);
-
---- a/arch/mips/include/asm/mach-ath79/ath79.h
-+++ b/arch/mips/include/asm/mach-ath79/ath79.h
-@@ -99,6 +99,7 @@ static inline int soc_is_ar934x(void)
- }
-
- extern void __iomem *ath79_ddr_base;
-+extern void __iomem *ath79_gpio_base;
- extern void __iomem *ath79_pll_base;
- extern void __iomem *ath79_reset_base;
-
+++ /dev/null
---- a/arch/mips/ath79/common.c
-+++ b/arch/mips/ath79/common.c
-@@ -22,6 +22,7 @@
- #include "common.h"
-
- static DEFINE_SPINLOCK(ath79_device_reset_lock);
-+static DEFINE_MUTEX(ath79_flash_mutex);
-
- u32 ath79_cpu_freq;
- EXPORT_SYMBOL_GPL(ath79_cpu_freq);
-@@ -107,3 +108,16 @@ void ath79_device_reset_clear(u32 mask)
- spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
- }
- EXPORT_SYMBOL_GPL(ath79_device_reset_clear);
-+
-+void ath79_flash_acquire(void)
-+{
-+ mutex_lock(&ath79_flash_mutex);
-+}
-+EXPORT_SYMBOL_GPL(ath79_flash_acquire);
-+
-+void ath79_flash_release(void)
-+{
-+ mutex_unlock(&ath79_flash_mutex);
-+}
-+EXPORT_SYMBOL_GPL(ath79_flash_release);
-+
---- a/arch/mips/include/asm/mach-ath79/ath79.h
-+++ b/arch/mips/include/asm/mach-ath79/ath79.h
-@@ -126,4 +126,7 @@ static inline u32 ath79_reset_rr(unsigne
- void ath79_device_reset_set(u32 mask);
- void ath79_device_reset_clear(u32 mask);
-
-+void ath79_flash_acquire(void);
-+void ath79_flash_release(void);
-+
- #endif /* __ASM_MACH_ATH79_H */
+++ /dev/null
---- a/arch/mips/include/asm/mach-ath79/ath79.h
-+++ b/arch/mips/include/asm/mach-ath79/ath79.h
-@@ -125,6 +125,7 @@ static inline u32 ath79_reset_rr(unsigne
-
- void ath79_device_reset_set(u32 mask);
- void ath79_device_reset_clear(u32 mask);
-+u32 ath79_device_reset_get(u32 mask);
-
- void ath79_flash_acquire(void);
- void ath79_flash_release(void);
---- a/arch/mips/ath79/common.c
-+++ b/arch/mips/ath79/common.c
-@@ -109,6 +109,32 @@ void ath79_device_reset_clear(u32 mask)
- }
- EXPORT_SYMBOL_GPL(ath79_device_reset_clear);
-
-+u32 ath79_device_reset_get(u32 mask)
-+{
-+ unsigned long flags;
-+ u32 reg;
-+ u32 ret;
-+
-+ if (soc_is_ar71xx())
-+ reg = AR71XX_RESET_REG_RESET_MODULE;
-+ else if (soc_is_ar724x())
-+ reg = AR724X_RESET_REG_RESET_MODULE;
-+ else if (soc_is_ar913x())
-+ reg = AR913X_RESET_REG_RESET_MODULE;
-+ else if (soc_is_ar933x())
-+ reg = AR933X_RESET_REG_RESET_MODULE;
-+ else if (soc_is_ar934x())
-+ reg = AR934X_RESET_REG_RESET_MODULE;
-+ else
-+ BUG();
-+
-+ spin_lock_irqsave(&ath79_device_reset_lock, flags);
-+ ret = ath79_reset_rr(reg);
-+ spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
-+ return ret;
-+}
-+EXPORT_SYMBOL_GPL(ath79_device_reset_get);
-+
- void ath79_flash_acquire(void)
- {
- mutex_lock(&ath79_flash_mutex);
+++ /dev/null
---- a/arch/mips/ath79/common.h
-+++ b/arch/mips/ath79/common.h
-@@ -26,6 +26,7 @@ void ath79_ddr_wb_flush(unsigned int reg
- void ath79_gpio_function_enable(u32 mask);
- void ath79_gpio_function_disable(u32 mask);
- void ath79_gpio_function_setup(u32 set, u32 clear);
-+void ath79_gpio_output_select(unsigned gpio, u8 val);
- void ath79_gpio_init(void);
-
- #endif /* __ATH79_COMMON_H */
---- a/arch/mips/ath79/gpio.c
-+++ b/arch/mips/ath79/gpio.c
-@@ -184,6 +184,34 @@ void ath79_gpio_function_setup(u32 set,
- spin_unlock_irqrestore(&ath79_gpio_lock, flags);
- }
-
-+void __init ath79_gpio_output_select(unsigned gpio, u8 val)
-+{
-+ void __iomem *base = ath79_gpio_base;
-+ unsigned long flags;
-+ unsigned int reg;
-+ u32 t, s;
-+
-+ BUG_ON(!soc_is_ar934x());
-+
-+ if (gpio >= AR934X_GPIO_COUNT)
-+ return;
-+
-+ reg = AR934X_GPIO_REG_OUT_FUNC0 + 4 * (gpio / 4);
-+ s = 8 * (gpio % 4);
-+
-+ spin_lock_irqsave(&ath79_gpio_lock, flags);
-+
-+ t = __raw_readl(base + reg);
-+ t &= ~(0xff << s);
-+ t |= val << s;
-+ __raw_writel(t, base + reg);
-+
-+ /* flush write */
-+ (void) __raw_readl(base + reg);
-+
-+ spin_unlock_irqrestore(&ath79_gpio_lock, flags);
-+}
-+
- void __init ath79_gpio_init(void)
- {
- int err;
+++ /dev/null
---- a/arch/mips/ath79/prom.c
-+++ b/arch/mips/ath79/prom.c
-@@ -19,6 +19,8 @@
-
- #include "common.h"
-
-+static char ath79_cmdline_buf[COMMAND_LINE_SIZE] __initdata;
-+
- static inline int is_valid_ram_addr(void *addr)
- {
- if (((u32) addr > KSEG0) &&
-@@ -32,6 +34,41 @@ static inline int is_valid_ram_addr(void
- return 0;
- }
-
-+static void __init ath79_prom_append_cmdline(const char *name,
-+ const char *value)
-+{
-+ snprintf(ath79_cmdline_buf, sizeof(ath79_cmdline_buf),
-+ " %s=%s", name, value);
-+ strlcat(arcs_cmdline, ath79_cmdline_buf, sizeof(arcs_cmdline));
-+}
-+
-+static const char * __init ath79_prom_find_env(char **envp, const char *name)
-+{
-+ const char *ret = NULL;
-+ int len;
-+ char **p;
-+
-+ if (!is_valid_ram_addr(envp))
-+ return NULL;
-+
-+ len = strlen(name);
-+ for (p = envp; is_valid_ram_addr(*p); p++) {
-+ if (strncmp(name, *p, len) == 0 && (*p)[len] == '=') {
-+ ret = *p + len + 1;
-+ break;
-+ }
-+
-+ /* RedBoot env comes in pointer pairs - key, value */
-+ if (strncmp(name, *p, len) == 0 && (*p)[len] == 0)
-+ if (is_valid_ram_addr(*(++p))) {
-+ ret = *p;
-+ break;
-+ }
-+ }
-+
-+ return ret;
-+}
-+
- static __init void ath79_prom_init_cmdline(int argc, char **argv)
- {
- int i;
-@@ -48,7 +85,32 @@ static __init void ath79_prom_init_cmdli
-
- void __init prom_init(void)
- {
-+ const char *env;
-+ char **envp;
-+
- ath79_prom_init_cmdline(fw_arg0, (char **)fw_arg1);
-+
-+ envp = (char **)fw_arg2;
-+ if (!strstr(arcs_cmdline, "ethaddr=")) {
-+ env = ath79_prom_find_env(envp, "ethaddr");
-+ if (env)
-+ ath79_prom_append_cmdline("ethaddr", env);
-+ }
-+
-+ if (!strstr(arcs_cmdline, "board=")) {
-+ env = ath79_prom_find_env(envp, "board");
-+ if (env) {
-+ /* Workaround for buggy bootloaders */
-+ if (strcmp(env, "RouterStation") == 0 ||
-+ strcmp(env, "Ubiquiti AR71xx-based board") == 0)
-+ env = "UBNT-RS";
-+
-+ if (strcmp(env, "RouterStation PRO") == 0)
-+ env = "UBNT-RSPRO";
-+
-+ ath79_prom_append_cmdline("board", env);
-+ }
-+ }
- }
-
- void __init prom_free_prom_memory(void)
+++ /dev/null
---- a/arch/mips/ath79/prom.c
-+++ b/arch/mips/ath79/prom.c
-@@ -16,6 +16,7 @@
-
- #include <asm/bootinfo.h>
- #include <asm/addrspace.h>
-+#include <asm/fw/myloader/myloader.h>
-
- #include "common.h"
-
-@@ -69,6 +70,37 @@ static const char * __init ath79_prom_fi
- return ret;
- }
-
-+static int __init ath79_prom_init_myloader(void)
-+{
-+ struct myloader_info *mylo;
-+ char mac_buf[32];
-+ unsigned char *mac;
-+
-+ mylo = myloader_get_info();
-+ if (!mylo)
-+ return 0;
-+
-+ switch (mylo->did) {
-+ case DEVID_COMPEX_WP543:
-+ ath79_prom_append_cmdline("board", "WP543");
-+ break;
-+ case DEVID_COMPEX_WPE72:
-+ ath79_prom_append_cmdline("board", "WPE72");
-+ break;
-+ default:
-+ pr_warn("prom: unknown device id: %x\n", mylo->did);
-+ return 0;
-+ }
-+
-+ mac = mylo->macs[0];
-+ snprintf(mac_buf, sizeof(mac_buf), "%02x:%02x:%02x:%02x:%02x:%02x",
-+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
-+
-+ ath79_prom_append_cmdline("ethaddr", mac_buf);
-+
-+ return 1;
-+}
-+
- static __init void ath79_prom_init_cmdline(int argc, char **argv)
- {
- int i;
-@@ -88,6 +120,9 @@ void __init prom_init(void)
- const char *env;
- char **envp;
-
-+ if (ath79_prom_init_myloader())
-+ return;
-+
- ath79_prom_init_cmdline(fw_arg0, (char **)fw_arg1);
-
- envp = (char **)fw_arg2;
+++ /dev/null
---- a/arch/mips/ath79/prom.c
-+++ b/arch/mips/ath79/prom.c
-@@ -70,6 +70,35 @@ static const char * __init ath79_prom_fi
- return ret;
- }
-
-+#ifdef CONFIG_IMAGE_CMDLINE_HACK
-+extern char __image_cmdline[];
-+
-+static int __init ath79_use_image_cmdline(void)
-+{
-+ char *p = __image_cmdline;
-+ int replace = 0;
-+
-+ if (*p == '-') {
-+ replace = 1;
-+ p++;
-+ }
-+
-+ if (*p == '\0')
-+ return 0;
-+
-+ if (replace) {
-+ strlcpy(arcs_cmdline, p, sizeof(arcs_cmdline));
-+ } else {
-+ strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
-+ strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
-+ }
-+
-+ return 1;
-+}
-+#else
-+static inline int ath79_use_image_cmdline(void) { return 0; }
-+#endif
-+
- static int __init ath79_prom_init_myloader(void)
- {
- struct myloader_info *mylo;
-@@ -98,6 +127,8 @@ static int __init ath79_prom_init_myload
-
- ath79_prom_append_cmdline("ethaddr", mac_buf);
-
-+ ath79_use_image_cmdline();
-+
- return 1;
- }
-
-@@ -105,6 +136,9 @@ static __init void ath79_prom_init_cmdli
- {
- int i;
-
-+ if (ath79_use_image_cmdline())
-+ return;
-+
- if (!is_valid_ram_addr(argv))
- return;
-
+++ /dev/null
---- a/arch/mips/ath79/setup.c
-+++ b/arch/mips/ath79/setup.c
-@@ -215,6 +215,8 @@ void __init plat_time_init(void)
- mips_hpt_frequency = clk_get_rate(clk) / 2;
- }
-
-+__setup("board=", mips_machtype_setup);
-+
- static int __init ath79_setup(void)
- {
- ath79_gpio_init();
+++ /dev/null
---- a/arch/mips/ath79/dev-wmac.c
-+++ b/arch/mips/ath79/dev-wmac.c
-@@ -24,7 +24,10 @@
- #include "dev-wmac.h"
-
- static u8 ath79_wmac_mac[ETH_ALEN];
--static struct ath9k_platform_data ath79_wmac_data;
-+
-+static struct ath9k_platform_data ath79_wmac_data = {
-+ .led_pin = -1,
-+};
-
- static struct resource ath79_wmac_resources[] = {
- {
+++ /dev/null
---- a/arch/mips/ath79/dev-common.c
-+++ b/arch/mips/ath79/dev-common.c
-@@ -87,6 +87,15 @@ void __init ath79_register_uart(void)
- if (IS_ERR(clk))
- panic("unable to get UART clock, err=%ld", PTR_ERR(clk));
-
-+ if (soc_is_ar71xx())
-+ ath79_gpio_function_enable(AR71XX_GPIO_FUNC_UART_EN);
-+ else if (soc_is_ar724x())
-+ ath79_gpio_function_enable(AR724X_GPIO_FUNC_UART_EN);
-+ else if (soc_is_ar913x())
-+ ath79_gpio_function_enable(AR913X_GPIO_FUNC_UART_EN);
-+ else if (soc_is_ar933x())
-+ ath79_gpio_function_enable(AR933X_GPIO_FUNC_UART_EN);
-+
- if (soc_is_ar71xx() ||
- soc_is_ar724x() ||
- soc_is_ar913x() ||
+++ /dev/null
---- a/arch/mips/ath79/early_printk.c
-+++ b/arch/mips/ath79/early_printk.c
-@@ -56,6 +56,46 @@ static void prom_putchar_dummy(unsigned
- /* nothing to do */
- }
-
-+static void prom_enable_uart(u32 id)
-+{
-+ void __iomem *gpio_base;
-+ u32 uart_en;
-+ u32 t;
-+
-+ switch (id) {
-+ case REV_ID_MAJOR_AR71XX:
-+ uart_en = AR71XX_GPIO_FUNC_UART_EN;
-+ break;
-+
-+ case REV_ID_MAJOR_AR7240:
-+ case REV_ID_MAJOR_AR7241:
-+ case REV_ID_MAJOR_AR7242:
-+ uart_en = AR724X_GPIO_FUNC_UART_EN;
-+ break;
-+
-+ case REV_ID_MAJOR_AR913X:
-+ uart_en = AR913X_GPIO_FUNC_UART_EN;
-+ break;
-+
-+ case REV_ID_MAJOR_AR9330:
-+ case REV_ID_MAJOR_AR9331:
-+ uart_en = AR933X_GPIO_FUNC_UART_EN;
-+ break;
-+
-+ case REV_ID_MAJOR_AR9341:
-+ case REV_ID_MAJOR_AR9342:
-+ case REV_ID_MAJOR_AR9344:
-+ /* TODO */
-+ default:
-+ return;
-+ }
-+
-+ gpio_base = (void __iomem *)(KSEG1ADDR(AR71XX_GPIO_BASE));
-+ t = __raw_readl(gpio_base + AR71XX_GPIO_REG_FUNC);
-+ t |= uart_en;
-+ __raw_writel(t, gpio_base + AR71XX_GPIO_REG_FUNC);
-+}
-+
- static void prom_putchar_init(void)
- {
- void __iomem *base;
-@@ -84,8 +124,10 @@ static void prom_putchar_init(void)
-
- default:
- _prom_putchar = prom_putchar_dummy;
-- break;
-+ return;
- }
-+
-+ prom_enable_uart(id);
- }
-
- void prom_putchar(unsigned char ch)
+++ /dev/null
---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -20,7 +20,13 @@
- #include <linux/io.h>
- #include <linux/bitops.h>
-
-+#define AR71XX_PCI_MEM_BASE 0x10000000
-+#define AR71XX_PCI_MEM_SIZE 0x08000000
- #define AR71XX_APB_BASE 0x18000000
-+#define AR71XX_GE0_BASE 0x19000000
-+#define AR71XX_GE0_SIZE 0x10000
-+#define AR71XX_GE1_BASE 0x1a000000
-+#define AR71XX_GE1_SIZE 0x10000
- #define AR71XX_EHCI_BASE 0x1b000000
- #define AR71XX_EHCI_SIZE 0x1000
- #define AR71XX_OHCI_BASE 0x1c000000
-@@ -40,6 +46,8 @@
- #define AR71XX_PLL_SIZE 0x100
- #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
- #define AR71XX_RESET_SIZE 0x100
-+#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000)
-+#define AR71XX_MII_SIZE 0x100
-
- #define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
- #define AR7240_USB_CTRL_SIZE 0x100
-@@ -56,11 +64,15 @@
-
- #define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
- #define AR933X_UART_SIZE 0x14
-+#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
-+#define AR933X_GMAC_SIZE 0x04
- #define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
- #define AR933X_WMAC_SIZE 0x20000
- #define AR933X_EHCI_BASE 0x1b000000
- #define AR933X_EHCI_SIZE 0x1000
-
-+#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
-+#define AR934X_GMAC_SIZE 0x14
- #define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
- #define AR934X_WMAC_SIZE 0x20000
- #define AR934X_EHCI_BASE 0x1b000000
-@@ -120,6 +132,9 @@
- #define AR71XX_AHB_DIV_SHIFT 20
- #define AR71XX_AHB_DIV_MASK 0x7
-
-+#define AR71XX_ETH0_PLL_SHIFT 17
-+#define AR71XX_ETH1_PLL_SHIFT 19
-+
- #define AR724X_PLL_REG_CPU_CONFIG 0x00
- #define AR724X_PLL_REG_PCIE_CONFIG 0x18
-
-@@ -132,6 +147,8 @@
- #define AR724X_DDR_DIV_SHIFT 22
- #define AR724X_DDR_DIV_MASK 0x3
-
-+#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c
-+
- #define AR913X_PLL_REG_CPU_CONFIG 0x00
- #define AR913X_PLL_REG_ETH_CONFIG 0x04
- #define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
-@@ -144,6 +161,9 @@
- #define AR913X_AHB_DIV_SHIFT 19
- #define AR913X_AHB_DIV_MASK 0x1
-
-+#define AR913X_ETH0_PLL_SHIFT 20
-+#define AR913X_ETH1_PLL_SHIFT 22
-+
- #define AR933X_PLL_CPU_CONFIG_REG 0x00
- #define AR933X_PLL_CLOCK_CTRL_REG 0x08
-
-@@ -165,6 +185,7 @@
- #define AR934X_PLL_CPU_CONFIG_REG 0x00
- #define AR934X_PLL_DDR_CONFIG_REG 0x04
- #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
-+#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c
-
- #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
- #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
-@@ -285,7 +306,11 @@
- #define AR913X_RESET_USB_HOST BIT(5)
- #define AR913X_RESET_USB_PHY BIT(4)
-
-+#define AR933X_RESET_GE1_MDIO BIT(23)
-+#define AR933X_RESET_GE0_MDIO BIT(22)
-+#define AR933X_RESET_GE1_MAC BIT(13)
- #define AR933X_RESET_WMAC BIT(11)
-+#define AR933X_RESET_GE0_MAC BIT(9)
- #define AR933X_RESET_USB_HOST BIT(5)
- #define AR933X_RESET_USB_PHY BIT(4)
- #define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
-@@ -323,6 +348,8 @@
- #define AR934X_RESET_MBOX BIT(1)
- #define AR934X_RESET_I2S BIT(0)
-
-+#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
-+#define AR933X_BOOTSTRAP_EEPBUSY BIT(4)
- #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
-
- #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
-@@ -427,6 +454,14 @@
- #define AR71XX_GPIO_REG_INT_ENABLE 0x24
- #define AR71XX_GPIO_REG_FUNC 0x28
-
-+#define AR934X_GPIO_REG_OUT_FUNC0 0x2c
-+#define AR934X_GPIO_REG_OUT_FUNC1 0x30
-+#define AR934X_GPIO_REG_OUT_FUNC2 0x34
-+#define AR934X_GPIO_REG_OUT_FUNC3 0x38
-+#define AR934X_GPIO_REG_OUT_FUNC4 0x3c
-+#define AR934X_GPIO_REG_OUT_FUNC5 0x40
-+#define AR934X_GPIO_REG_FUNC 0x6c
-+
- #define AR71XX_GPIO_COUNT 16
- #define AR7240_GPIO_COUNT 18
- #define AR7241_GPIO_COUNT 20
-@@ -434,4 +469,124 @@
- #define AR933X_GPIO_COUNT 30
- #define AR934X_GPIO_COUNT 23
-
-+#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
-+#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)
-+#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13)
-+#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12)
-+#define AR71XX_GPIO_FUNC_UART_EN BIT(8)
-+#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4)
-+#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0)
-+
-+#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19)
-+#define AR724X_GPIO_FUNC_SPI_EN BIT(18)
-+#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
-+#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
-+#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12)
-+#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11)
-+#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10)
-+#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9)
-+#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8)
-+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
-+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
-+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
-+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
-+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
-+#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
-+#define AR724X_GPIO_FUNC_UART_EN BIT(1)
-+#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0)
-+
-+#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22)
-+#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21)
-+#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20)
-+#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19)
-+#define AR913X_GPIO_FUNC_I2S1_EN BIT(18)
-+#define AR913X_GPIO_FUNC_I2S0_EN BIT(17)
-+#define AR913X_GPIO_FUNC_SLIC_EN BIT(16)
-+#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9)
-+#define AR913X_GPIO_FUNC_UART_EN BIT(8)
-+#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4)
-+
-+#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31)
-+#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30)
-+#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29)
-+#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27)
-+#define AR933X_GPIO_FUNC_I2SO_EN BIT(26)
-+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25)
-+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24)
-+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23)
-+#define AR933X_GPIO_FUNC_SPI_EN BIT(18)
-+#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
-+#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
-+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
-+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
-+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
-+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
-+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
-+#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
-+#define AR933X_GPIO_FUNC_UART_EN BIT(1)
-+#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0)
-+
-+#define AR934X_GPIO_FUNC_DDR_DQOE_EN BIT(17)
-+#define AR934X_GPIO_FUNC_SPI_CS_1_EN BIT(14)
-+#define AR934X_GPIO_FUNC_SPI_CS_0_EN BIT(13)
-+
-+#define AR934X_GPIO_OUT_GPIO 0x00
-+
-+/*
-+ * MII_CTRL block
-+ */
-+#define AR71XX_MII_REG_MII0_CTRL 0x00
-+#define AR71XX_MII_REG_MII1_CTRL 0x04
-+
-+#define AR71XX_MII_CTRL_IF_MASK 3
-+#define AR71XX_MII_CTRL_SPEED_SHIFT 4
-+#define AR71XX_MII_CTRL_SPEED_MASK 3
-+#define AR71XX_MII_CTRL_SPEED_10 0
-+#define AR71XX_MII_CTRL_SPEED_100 1
-+#define AR71XX_MII_CTRL_SPEED_1000 2
-+
-+#define AR71XX_MII0_CTRL_IF_GMII 0
-+#define AR71XX_MII0_CTRL_IF_MII 1
-+#define AR71XX_MII0_CTRL_IF_RGMII 2
-+#define AR71XX_MII0_CTRL_IF_RMII 3
-+
-+#define AR71XX_MII1_CTRL_IF_RGMII 0
-+#define AR71XX_MII1_CTRL_IF_RMII 1
-+
-+/*
-+ * AR933X GMAC interface
-+ */
-+#define AR933X_GMAC_REG_ETH_CFG 0x00
-+
-+#define AR933X_ETH_CFG_RGMII_GE0 BIT(0)
-+#define AR933X_ETH_CFG_MII_GE0 BIT(1)
-+#define AR933X_ETH_CFG_GMII_GE0 BIT(2)
-+#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3)
-+#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4)
-+#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5)
-+#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7)
-+#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8)
-+#define AR933X_ETH_CFG_RMII_GE0 BIT(9)
-+#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0
-+#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10)
-+
-+/*
-+ * AR934X GMAC Interface
-+ */
-+#define AR934X_GMAC_REG_ETH_CFG 0x00
-+
-+#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0)
-+#define AR934X_ETH_CFG_MII_GMAC0 BIT(1)
-+#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2)
-+#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3)
-+#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4)
-+#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5)
-+#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6)
-+#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7)
-+#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9)
-+#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10)
-+#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11)
-+#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
-+#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
-+
- #endif /* __ASM_MACH_AR71XX_REGS_H */
+++ /dev/null
---- a/arch/mips/ath79/Kconfig
-+++ b/arch/mips/ath79/Kconfig
-@@ -88,6 +88,20 @@ config SOC_AR934X
- select PCI_AR724X if PCI
- def_bool n
-
-+config ATH79_DEV_M25P80
-+ select ATH79_DEV_SPI
-+ def_bool n
-+
-+config ATH79_DEV_AP9X_PCI
-+ select ATH79_PCI_ATH9K_FIXUP
-+ def_bool n
-+
-+config ATH79_DEV_DSA
-+ def_bool n
-+
-+config ATH79_DEV_ETH
-+ def_bool n
-+
- config PCI_AR724X
- def_bool n
-
-@@ -107,4 +121,10 @@ config ATH79_DEV_WMAC
- depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X)
- def_bool n
-
-+config ATH79_NVRAM
-+ def_bool n
-+
-+config ATH79_PCI_ATH9K_FIXUP
-+ def_bool n
-+
- endif
---- a/arch/mips/ath79/Makefile
-+++ b/arch/mips/ath79/Makefile
-@@ -17,13 +17,23 @@ obj-$(CONFIG_PCI) += pci.o
- # Devices
- #
- obj-y += dev-common.o
-+obj-$(CONFIG_ATH79_DEV_AP9X_PCI) += dev-ap9x-pci.o
-+obj-$(CONFIG_ATH79_DEV_DSA) += dev-dsa.o
-+obj-$(CONFIG_ATH79_DEV_ETH) += dev-eth.o
- obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o
- obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o
-+obj-$(CONFIG_ATH79_DEV_M25P80) += dev-m25p80.o
- obj-$(CONFIG_ATH79_DEV_SPI) += dev-spi.o
- obj-$(CONFIG_ATH79_DEV_USB) += dev-usb.o
- obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wmac.o
-
- #
-+# Miscellaneous objects
-+#
-+obj-$(CONFIG_ATH79_NVRAM) += nvram.o
-+obj-$(CONFIG_ATH79_PCI_ATH9K_FIXUP) += pci-ath9k-fixup.o
-+
-+#
- # Machines
- #
- obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o
+++ /dev/null
---- a/arch/mips/ath79/mach-ap121.c
-+++ b/arch/mips/ath79/mach-ap121.c
-@@ -1,19 +1,21 @@
- /*
- * Atheros AP121 board support
- *
-- * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
-+ * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
--#include "machtypes.h"
-+#include "dev-eth.h"
- #include "dev-gpio-buttons.h"
- #include "dev-leds-gpio.h"
-+#include "dev-m25p80.h"
- #include "dev-spi.h"
- #include "dev-usb.h"
- #include "dev-wmac.h"
-+#include "machtypes.h"
-
- #define AP121_GPIO_LED_WLAN 0
- #define AP121_GPIO_LED_USB 1
-@@ -24,7 +26,14 @@
- #define AP121_KEYS_POLL_INTERVAL 20 /* msecs */
- #define AP121_KEYS_DEBOUNCE_INTERVAL (3 * AP121_KEYS_POLL_INTERVAL)
-
--#define AP121_CAL_DATA_ADDR 0x1fff1000
-+#define AP121_MAC0_OFFSET 0x0000
-+#define AP121_MAC1_OFFSET 0x0006
-+#define AP121_CALDATA_OFFSET 0x1000
-+#define AP121_WMAC_MAC_OFFSET 0x1002
-+
-+#define AP121_MINI_GPIO_LED_WLAN 0
-+#define AP121_MINI_GPIO_BTN_JUMPSTART 12
-+#define AP121_MINI_GPIO_BTN_RESET 11
-
- static struct gpio_led ap121_leds_gpio[] __initdata = {
- {
-@@ -58,41 +67,78 @@ static struct gpio_keys_button ap121_gpi
- }
- };
-
--static struct ath79_spi_controller_data ap121_spi0_data = {
-- .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
-- .cs_line = 0,
-+static struct gpio_led ap121_mini_leds_gpio[] __initdata = {
-+ {
-+ .name = "ap121:green:wlan",
-+ .gpio = AP121_MINI_GPIO_LED_WLAN,
-+ .active_low = 0,
-+ },
- };
-
--static struct spi_board_info ap121_spi_info[] = {
-+static struct gpio_keys_button ap121_mini_gpio_keys[] __initdata = {
- {
-- .bus_num = 0,
-- .chip_select = 0,
-- .max_speed_hz = 25000000,
-- .modalias = "mx25l1606e",
-- .controller_data = &ap121_spi0_data,
-+ .desc = "jumpstart button",
-+ .type = EV_KEY,
-+ .code = KEY_WPS_BUTTON,
-+ .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL,
-+ .gpio = AP121_MINI_GPIO_BTN_JUMPSTART,
-+ .active_low = 1,
-+ },
-+ {
-+ .desc = "reset button",
-+ .type = EV_KEY,
-+ .code = KEY_RESTART,
-+ .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL,
-+ .gpio = AP121_MINI_GPIO_BTN_RESET,
-+ .active_low = 1,
- }
- };
-
--static struct ath79_spi_platform_data ap121_spi_data = {
-- .bus_num = 0,
-- .num_chipselect = 1,
--};
-+static void __init ap121_common_setup(void)
-+{
-+ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
-+
-+ ath79_register_m25p80(NULL);
-+ ath79_register_wmac(art + AP121_CALDATA_OFFSET,
-+ art + AP121_WMAC_MAC_OFFSET);
-+
-+ ath79_init_mac(ath79_eth0_data.mac_addr, art + AP121_MAC0_OFFSET, 0);
-+ ath79_init_mac(ath79_eth1_data.mac_addr, art + AP121_MAC1_OFFSET, 0);
-+
-+ ath79_register_mdio(0, 0x0);
-+
-+ /* LAN ports */
-+ ath79_register_eth(1);
-+
-+ /* WAN port */
-+ ath79_register_eth(0);
-+}
-
- static void __init ap121_setup(void)
- {
-- u8 *cal_data = (u8 *) KSEG1ADDR(AP121_CAL_DATA_ADDR);
-+ ap121_common_setup();
-
- ath79_register_leds_gpio(-1, ARRAY_SIZE(ap121_leds_gpio),
- ap121_leds_gpio);
- ath79_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL,
- ARRAY_SIZE(ap121_gpio_keys),
- ap121_gpio_keys);
--
-- ath79_register_spi(&ap121_spi_data, ap121_spi_info,
-- ARRAY_SIZE(ap121_spi_info));
- ath79_register_usb();
-- ath79_register_wmac(cal_data, NULL);
- }
-
- MIPS_MACHINE(ATH79_MACH_AP121, "AP121", "Atheros AP121 reference board",
- ap121_setup);
-+
-+static void __init ap121_mini_setup(void)
-+{
-+ ap121_common_setup();
-+
-+ ath79_register_leds_gpio(-1, ARRAY_SIZE(ap121_mini_leds_gpio),
-+ ap121_mini_leds_gpio);
-+ ath79_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL,
-+ ARRAY_SIZE(ap121_mini_gpio_keys),
-+ ap121_mini_gpio_keys);
-+}
-+
-+MIPS_MACHINE(ATH79_MACH_AP121_MINI, "AP121-MINI", "Atheros AP121-MINI",
-+ ap121_mini_setup);
---- a/arch/mips/ath79/Kconfig
-+++ b/arch/mips/ath79/Kconfig
-@@ -5,9 +5,10 @@ menu "Atheros AR71XX/AR724X/AR913X machi
- config ATH79_MACH_AP121
- bool "Atheros AP121 reference board"
- select SOC_AR933X
-+ select ATH79_DEV_ETH
- select ATH79_DEV_GPIO_BUTTONS
- select ATH79_DEV_LEDS_GPIO
-- select ATH79_DEV_SPI
-+ select ATH79_DEV_M25P80
- select ATH79_DEV_USB
- select ATH79_DEV_WMAC
- help
---- a/arch/mips/ath79/machtypes.h
-+++ b/arch/mips/ath79/machtypes.h
-@@ -17,6 +17,7 @@
- enum ath79_mach_type {
- ATH79_MACH_GENERIC = 0,
- ATH79_MACH_AP121, /* Atheros AP121 reference board */
-+ ATH79_MACH_AP121_MINI, /* Atheros AP121-MINI reference board */
- ATH79_MACH_AP81, /* Atheros AP81 reference board */
- ATH79_MACH_DB120, /* Atheros DB120 reference board */
- ATH79_MACH_PB44, /* Atheros PB44 reference board */
+++ /dev/null
---- a/arch/mips/ath79/mach-ap81.c
-+++ b/arch/mips/ath79/mach-ap81.c
-@@ -9,12 +9,16 @@
- * by the Free Software Foundation.
- */
-
--#include "machtypes.h"
--#include "dev-wmac.h"
-+#include <linux/mtd/mtd.h>
-+#include <linux/mtd/partitions.h>
-+
-+#include "dev-eth.h"
- #include "dev-gpio-buttons.h"
- #include "dev-leds-gpio.h"
--#include "dev-spi.h"
-+#include "dev-m25p80.h"
- #include "dev-usb.h"
-+#include "dev-wmac.h"
-+#include "machtypes.h"
-
- #define AP81_GPIO_LED_STATUS 1
- #define AP81_GPIO_LED_AOSS 3
-@@ -29,6 +33,37 @@
-
- #define AP81_CAL_DATA_ADDR 0x1fff1000
-
-+static struct mtd_partition ap81_partitions[] = {
-+ {
-+ .name = "u-boot",
-+ .offset = 0,
-+ .size = 0x040000,
-+ .mask_flags = MTD_WRITEABLE,
-+ }, {
-+ .name = "u-boot-env",
-+ .offset = 0x040000,
-+ .size = 0x010000,
-+ }, {
-+ .name = "rootfs",
-+ .offset = 0x050000,
-+ .size = 0x500000,
-+ }, {
-+ .name = "uImage",
-+ .offset = 0x550000,
-+ .size = 0x100000,
-+ }, {
-+ .name = "ART",
-+ .offset = 0x650000,
-+ .size = 0x1b0000,
-+ .mask_flags = MTD_WRITEABLE,
-+ }
-+};
-+
-+static struct flash_platform_data ap81_flash_data = {
-+ .parts = ap81_partitions,
-+ .nr_parts = ARRAY_SIZE(ap81_partitions),
-+};
-+
- static struct gpio_led ap81_leds_gpio[] __initdata = {
- {
- .name = "ap81:green:status",
-@@ -67,26 +102,6 @@ static struct gpio_keys_button ap81_gpio
- }
- };
-
--static struct ath79_spi_controller_data ap81_spi0_data = {
-- .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
-- .cs_line = 0,
--};
--
--static struct spi_board_info ap81_spi_info[] = {
-- {
-- .bus_num = 0,
-- .chip_select = 0,
-- .max_speed_hz = 25000000,
-- .modalias = "m25p64",
-- .controller_data = &ap81_spi0_data,
-- }
--};
--
--static struct ath79_spi_platform_data ap81_spi_data = {
-- .bus_num = 0,
-- .num_chipselect = 1,
--};
--
- static void __init ap81_setup(void)
- {
- u8 *cal_data = (u8 *) KSEG1ADDR(AP81_CAL_DATA_ADDR);
-@@ -96,10 +111,24 @@ static void __init ap81_setup(void)
- ath79_register_gpio_keys_polled(-1, AP81_KEYS_POLL_INTERVAL,
- ARRAY_SIZE(ap81_gpio_keys),
- ap81_gpio_keys);
-- ath79_register_spi(&ap81_spi_data, ap81_spi_info,
-- ARRAY_SIZE(ap81_spi_info));
-+ ath79_register_m25p80(&ap81_flash_data);
- ath79_register_wmac(cal_data, NULL);
- ath79_register_usb();
-+
-+ ath79_register_mdio(0, 0x0);
-+
-+ ath79_init_mac(ath79_eth0_data.mac_addr, cal_data, 0);
-+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
-+ ath79_eth0_data.speed = SPEED_100;
-+ ath79_eth0_data.duplex = DUPLEX_FULL;
-+ ath79_eth0_data.has_ar8216 = 1;
-+
-+ ath79_init_mac(ath79_eth1_data.mac_addr, cal_data, 1);
-+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
-+ ath79_eth1_data.phy_mask = 0x10;
-+
-+ ath79_register_eth(0);
-+ ath79_register_eth(1);
- }
-
- MIPS_MACHINE(ATH79_MACH_AP81, "AP81", "Atheros AP81 reference board",
---- a/arch/mips/ath79/Kconfig
-+++ b/arch/mips/ath79/Kconfig
-@@ -18,9 +18,10 @@ config ATH79_MACH_AP121
- config ATH79_MACH_AP81
- bool "Atheros AP81 reference board"
- select SOC_AR913X
-+ select ATH79_DEV_ETH
- select ATH79_DEV_GPIO_BUTTONS
- select ATH79_DEV_LEDS_GPIO
-- select ATH79_DEV_SPI
-+ select ATH79_DEV_M25P80
- select ATH79_DEV_USB
- select ATH79_DEV_WMAC
- help
+++ /dev/null
---- a/arch/mips/ath79/mach-db120.c
-+++ b/arch/mips/ath79/mach-db120.c
-@@ -2,7 +2,7 @@
- * Atheros DB120 reference board support
- *
- * Copyright (c) 2011 Qualcomm Atheros
-- * Copyright (c) 2011 Gabor Juhos <juhosg@openwrt.org>
-+ * Copyright (c) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
- *
- * All rights reserved.
- *
-@@ -38,16 +38,25 @@
- */
-
- #include <linux/pci.h>
-+#include <linux/phy.h>
-+#include <linux/platform_device.h>
- #include <linux/ath9k_platform.h>
-+#include <linux/ar8216_platform.h>
-
--#include "machtypes.h"
-+#include <asm/mach-ath79/ar71xx_regs.h>
-+
-+#include "common.h"
-+#include "dev-ap9x-pci.h"
-+#include "dev-eth.h"
- #include "dev-gpio-buttons.h"
- #include "dev-leds-gpio.h"
-+#include "dev-m25p80.h"
- #include "dev-spi.h"
- #include "dev-usb.h"
- #include "dev-wmac.h"
--#include "pci.h"
-+#include "machtypes.h"
-
-+#define DB120_GPIO_LED_USB 11
- #define DB120_GPIO_LED_WLAN_5G 12
- #define DB120_GPIO_LED_WLAN_2G 13
- #define DB120_GPIO_LED_STATUS 14
-@@ -58,8 +67,10 @@
- #define DB120_KEYS_POLL_INTERVAL 20 /* msecs */
- #define DB120_KEYS_DEBOUNCE_INTERVAL (3 * DB120_KEYS_POLL_INTERVAL)
-
--#define DB120_WMAC_CALDATA_OFFSET 0x1000
--#define DB120_PCIE_CALDATA_OFFSET 0x5000
-+#define DB120_MAC0_OFFSET 0
-+#define DB120_MAC1_OFFSET 6
-+#define DB120_WMAC_CALDATA_OFFSET 0x1000
-+#define DB120_PCIE_CALDATA_OFFSET 0x5000
-
- static struct gpio_led db120_leds_gpio[] __initdata = {
- {
-@@ -82,6 +93,11 @@ static struct gpio_led db120_leds_gpio[]
- .gpio = DB120_GPIO_LED_WLAN_2G,
- .active_low = 1,
- },
-+ {
-+ .name = "db120:green:usb",
-+ .gpio = DB120_GPIO_LED_USB,
-+ .active_low = 1,
-+ }
- };
-
- static struct gpio_keys_button db120_gpio_keys[] __initdata = {
-@@ -95,66 +111,90 @@ static struct gpio_keys_button db120_gpi
- },
- };
-
--static struct ath79_spi_controller_data db120_spi0_data = {
-- .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
-- .cs_line = 0,
-+static struct ar8327_pad_cfg db120_ar8327_pad0_cfg = {
-+ .mode = AR8327_PAD_MAC_RGMII,
-+ .txclk_delay_en = true,
-+ .rxclk_delay_en = true,
-+ .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
-+ .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
- };
-
--static struct spi_board_info db120_spi_info[] = {
-- {
-- .bus_num = 0,
-- .chip_select = 0,
-- .max_speed_hz = 25000000,
-- .modalias = "s25sl064a",
-- .controller_data = &db120_spi0_data,
-+static struct ar8327_platform_data db120_ar8327_data = {
-+ .pad0_cfg = &db120_ar8327_pad0_cfg,
-+ .cpuport_cfg = {
-+ .force_link = 1,
-+ .speed = AR8327_PORT_SPEED_1000,
-+ .duplex = 1,
-+ .txpause = 1,
-+ .rxpause = 1,
- }
- };
-
--static struct ath79_spi_platform_data db120_spi_data = {
-- .bus_num = 0,
-- .num_chipselect = 1,
-+static struct mdio_board_info db120_mdio0_info[] = {
-+ {
-+ .bus_id = "ag71xx-mdio.0",
-+ .phy_addr = 0,
-+ .platform_data = &db120_ar8327_data,
-+ },
- };
-
--#ifdef CONFIG_PCI
--static struct ath9k_platform_data db120_ath9k_data;
--
--static int db120_pci_plat_dev_init(struct pci_dev *dev)
-+static void __init db120_gmac_setup(void)
- {
-- switch (PCI_SLOT(dev->devfn)) {
-- case 0:
-- dev->dev.platform_data = &db120_ath9k_data;
-- break;
-- }
-+ void __iomem *base;
-+ u32 t;
-
-- return 0;
--}
-+ base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
-
--static void __init db120_pci_init(u8 *eeprom)
--{
-- memcpy(db120_ath9k_data.eeprom_data, eeprom,
-- sizeof(db120_ath9k_data.eeprom_data));
-+ t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
-+ t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 |
-+ AR934X_ETH_CFG_MII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE);
-+ t |= AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE;
-+
-+ __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
-
-- ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init);
-- ath79_register_pci();
-+ iounmap(base);
- }
--#else
--static inline void db120_pci_init(void) {}
--#endif /* CONFIG_PCI */
-
- static void __init db120_setup(void)
- {
- u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
-
-+ ath79_gpio_output_select(DB120_GPIO_LED_USB, AR934X_GPIO_OUT_GPIO);
-+ ath79_register_m25p80(NULL);
-+
- ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio),
- db120_leds_gpio);
- ath79_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL,
- ARRAY_SIZE(db120_gpio_keys),
- db120_gpio_keys);
-- ath79_register_spi(&db120_spi_data, db120_spi_info,
-- ARRAY_SIZE(db120_spi_info));
- ath79_register_usb();
- ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET, NULL);
-- db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET);
-+ ap91_pci_init(art + DB120_PCIE_CALDATA_OFFSET, NULL);
-+
-+ db120_gmac_setup();
-+
-+ ath79_register_mdio(1, 0x0);
-+ ath79_register_mdio(0, 0x0);
-+
-+ ath79_init_mac(ath79_eth0_data.mac_addr, art + DB120_MAC0_OFFSET, 0);
-+
-+ mdiobus_register_board_info(db120_mdio0_info,
-+ ARRAY_SIZE(db120_mdio0_info));
-+
-+ /* GMAC0 is connected to an AR8327 switch */
-+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
-+ ath79_eth0_data.phy_mask = BIT(0);
-+ ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
-+ ath79_eth0_pll_data.pll_1000 = 0x06000000;
-+ ath79_register_eth(0);
-+
-+ /* GMAC1 is connected to the internal switch */
-+ ath79_init_mac(ath79_eth1_data.mac_addr, art + DB120_MAC1_OFFSET, 0);
-+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
-+ ath79_eth1_data.speed = SPEED_1000;
-+ ath79_eth1_data.duplex = DUPLEX_FULL;
-+
-+ ath79_register_eth(1);
- }
-
- MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board",
---- a/arch/mips/ath79/Kconfig
-+++ b/arch/mips/ath79/Kconfig
-@@ -31,9 +31,11 @@ config ATH79_MACH_AP81
- config ATH79_MACH_DB120
- bool "Atheros DB120 reference board"
- select SOC_AR934X
-+ select ATH79_DEV_AP9X_PCI if PCI
-+ select ATH79_DEV_ETH
- select ATH79_DEV_GPIO_BUTTONS
- select ATH79_DEV_LEDS_GPIO
-- select ATH79_DEV_SPI
-+ select ATH79_DEV_M25P80
- select ATH79_DEV_USB
- select ATH79_DEV_WMAC
- help
+++ /dev/null
---- a/arch/mips/ath79/mach-pb44.c
-+++ b/arch/mips/ath79/mach-pb44.c
-@@ -8,23 +8,48 @@
- * by the Free Software Foundation.
- */
-
-+#include <linux/delay.h>
- #include <linux/init.h>
- #include <linux/platform_device.h>
- #include <linux/i2c.h>
- #include <linux/i2c-gpio.h>
- #include <linux/i2c/pcf857x.h>
-+#include <linux/i2c/pcf857x.h>
-+#include <linux/spi/flash.h>
-+#include <linux/spi/vsc7385.h>
-
--#include "machtypes.h"
-+#include <asm/mach-ath79/ar71xx_regs.h>
-+#include <asm/mach-ath79/ath79.h>
-+
-+#include "dev-eth.h"
- #include "dev-gpio-buttons.h"
- #include "dev-leds-gpio.h"
- #include "dev-spi.h"
- #include "dev-usb.h"
-+#include "machtypes.h"
- #include "pci.h"
-
- #define PB44_GPIO_I2C_SCL 0
- #define PB44_GPIO_I2C_SDA 1
-
-+#define PB44_PCF8757_VSC7395_CS 0
-+#define PB44_PCF8757_STEREO_CS 1
-+#define PB44_PCF8757_SLIC_CS0 2
-+#define PB44_PCF8757_SLIC_TEST 3
-+#define PB44_PCF8757_SLIC_INT0 4
-+#define PB44_PCF8757_SLIC_INT1 5
-+#define PB44_PCF8757_SW_RESET 6
-+#define PB44_PCF8757_SW_JUMP 8
-+#define PB44_PCF8757_LED_JUMP1 9
-+#define PB44_PCF8757_LED_JUMP2 10
-+#define PB44_PCF8757_TP24 11
-+#define PB44_PCF8757_TP25 12
-+#define PB44_PCF8757_TP26 13
-+#define PB44_PCF8757_TP27 14
-+#define PB44_PCF8757_TP28 15
-+
- #define PB44_GPIO_EXP_BASE 16
-+#define PB44_GPIO_VSC7395_CS (PB44_GPIO_EXP_BASE + PB44_PCF8757_VSC7395_CS)
- #define PB44_GPIO_SW_RESET (PB44_GPIO_EXP_BASE + 6)
- #define PB44_GPIO_SW_JUMP (PB44_GPIO_EXP_BASE + 8)
- #define PB44_GPIO_LED_JUMP1 (PB44_GPIO_EXP_BASE + 9)
-@@ -92,21 +117,66 @@ static struct ath79_spi_controller_data
- .cs_line = 0,
- };
-
-+static struct ath79_spi_controller_data pb44_spi1_data = {
-+ .cs_type = ATH79_SPI_CS_TYPE_GPIO,
-+ .cs_line = PB44_GPIO_VSC7395_CS,
-+};
-+
-+static void pb44_vsc7395_reset(void)
-+{
-+ ath79_device_reset_set(AR71XX_RESET_GE1_PHY);
-+ udelay(10);
-+ ath79_device_reset_clear(AR71XX_RESET_GE1_PHY);
-+ mdelay(50);
-+}
-+
-+static struct vsc7385_platform_data pb44_vsc7395_data = {
-+ .reset = pb44_vsc7395_reset,
-+ .ucode_name = "vsc7395_ucode_pb44.bin",
-+ .mac_cfg = {
-+ .tx_ipg = 6,
-+ .bit2 = 1,
-+ .clk_sel = 0,
-+ },
-+};
-+
-+static const char *pb44_part_probes[] = {
-+ "RedBoot",
-+ NULL,
-+};
-+
-+static struct flash_platform_data pb44_flash_data = {
-+ .part_probes = pb44_part_probes,
-+};
-+
- static struct spi_board_info pb44_spi_info[] = {
- {
- .bus_num = 0,
- .chip_select = 0,
- .max_speed_hz = 25000000,
- .modalias = "m25p64",
-+ .platform_data = &pb44_flash_data,
- .controller_data = &pb44_spi0_data,
- },
-+ {
-+ .bus_num = 0,
-+ .chip_select = 1,
-+ .max_speed_hz = 25000000,
-+ .modalias = "spi-vsc7385",
-+ .platform_data = &pb44_vsc7395_data,
-+ .controller_data = &pb44_spi1_data,
-+ }
- };
-
- static struct ath79_spi_platform_data pb44_spi_data = {
- .bus_num = 0,
-- .num_chipselect = 1,
-+ .num_chipselect = 2,
- };
-
-+#define PB44_WAN_PHYMASK BIT(0)
-+#define PB44_LAN_PHYMASK 0
-+#define PB44_MDIO_PHYMASK (PB44_LAN_PHYMASK | PB44_WAN_PHYMASK)
-+
- static void __init pb44_init(void)
- {
- i2c_register_board_info(0, pb44_i2c_board_info,
-@@ -122,6 +192,22 @@ static void __init pb44_init(void)
- ARRAY_SIZE(pb44_spi_info));
- ath79_register_usb();
- ath79_register_pci();
-+
-+ ath79_register_mdio(0, ~PB44_MDIO_PHYMASK);
-+
-+ ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
-+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
-+ ath79_eth0_data.phy_mask = PB44_WAN_PHYMASK;
-+
-+ ath79_register_eth(0);
-+
-+ ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
-+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
-+ ath79_eth1_data.speed = SPEED_1000;
-+ ath79_eth1_data.duplex = DUPLEX_FULL;
-+ ath79_eth1_pll_data.pll_1000 = 0x110000;
-+
-+ ath79_register_eth(1);
- }
-
- MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board",
---- a/arch/mips/ath79/Kconfig
-+++ b/arch/mips/ath79/Kconfig
-@@ -45,6 +45,7 @@ config ATH79_MACH_DB120
- config ATH79_MACH_PB44
- bool "Atheros PB44 reference board"
- select SOC_AR71XX
-+ select ATH79_DEV_ETH
- select ATH79_DEV_GPIO_BUTTONS
- select ATH79_DEV_LEDS_GPIO
- select ATH79_DEV_SPI
+++ /dev/null
---- a/arch/mips/ath79/Kconfig
-+++ b/arch/mips/ath79/Kconfig
-@@ -57,9 +57,10 @@ config ATH79_MACH_PB44
- config ATH79_MACH_UBNT_XM
- bool "Ubiquiti Networks XM (rev 1.0) board"
- select SOC_AR724X
-+ select ATH79_DEV_AP9X_PCI if PCI
- select ATH79_DEV_GPIO_BUTTONS
- select ATH79_DEV_LEDS_GPIO
-- select ATH79_DEV_SPI
-+ select ATH79_DEV_M25P80
- help
- Say 'Y' here if you want your kernel to support the
- Ubiquiti Networks XM (rev 1.0) board.
---- a/arch/mips/ath79/mach-ubnt-xm.c
-+++ b/arch/mips/ath79/mach-ubnt-xm.c
-@@ -16,10 +16,11 @@
-
- #include <asm/mach-ath79/irq.h>
-
--#include "machtypes.h"
-+#include "dev-ap9x-pci.h"
- #include "dev-gpio-buttons.h"
- #include "dev-leds-gpio.h"
--#include "dev-spi.h"
-+#include "dev-m25p80.h"
-+#include "machtypes.h"
- #include "pci.h"
-
- #define UBNT_XM_GPIO_LED_L1 0
-@@ -32,7 +33,7 @@
- #define UBNT_XM_KEYS_POLL_INTERVAL 20
- #define UBNT_XM_KEYS_DEBOUNCE_INTERVAL (3 * UBNT_XM_KEYS_POLL_INTERVAL)
-
--#define UBNT_XM_EEPROM_ADDR (u8 *) KSEG1ADDR(0x1fff1000)
-+#define UBNT_XM_EEPROM_ADDR 0x1fff1000
-
- static struct gpio_led ubnt_xm_leds_gpio[] __initdata = {
- {
-@@ -65,54 +66,10 @@ static struct gpio_keys_button ubnt_xm_g
- }
- };
-
--static struct ath79_spi_controller_data ubnt_xm_spi0_data = {
-- .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
-- .cs_line = 0,
--};
--
--static struct spi_board_info ubnt_xm_spi_info[] = {
-- {
-- .bus_num = 0,
-- .chip_select = 0,
-- .max_speed_hz = 25000000,
-- .modalias = "mx25l6405d",
-- .controller_data = &ubnt_xm_spi0_data,
-- }
--};
--
--static struct ath79_spi_platform_data ubnt_xm_spi_data = {
-- .bus_num = 0,
-- .num_chipselect = 1,
--};
--
--#ifdef CONFIG_PCI
--static struct ath9k_platform_data ubnt_xm_eeprom_data;
--
--static int ubnt_xm_pci_plat_dev_init(struct pci_dev *dev)
--{
-- switch (PCI_SLOT(dev->devfn)) {
-- case 0:
-- dev->dev.platform_data = &ubnt_xm_eeprom_data;
-- break;
-- }
--
-- return 0;
--}
--
--static void __init ubnt_xm_pci_init(void)
--{
-- memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR,
-- sizeof(ubnt_xm_eeprom_data.eeprom_data));
--
-- ath79_pci_set_plat_dev_init(ubnt_xm_pci_plat_dev_init);
-- ath79_register_pci();
--}
--#else
--static inline void ubnt_xm_pci_init(void) {}
--#endif /* CONFIG_PCI */
--
- static void __init ubnt_xm_init(void)
- {
-+ u8 *eeprom = (u8 *) KSEG1ADDR(UBNT_XM_EEPROM_ADDR);
-+
- ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xm_leds_gpio),
- ubnt_xm_leds_gpio);
-
-@@ -120,10 +77,8 @@ static void __init ubnt_xm_init(void)
- ARRAY_SIZE(ubnt_xm_gpio_keys),
- ubnt_xm_gpio_keys);
-
-- ath79_register_spi(&ubnt_xm_spi_data, ubnt_xm_spi_info,
-- ARRAY_SIZE(ubnt_xm_spi_info));
--
-- ubnt_xm_pci_init();
-+ ath79_register_m25p80(NULL);
-+ ap91_pci_init(eeprom, NULL);
- }
-
- MIPS_MACHINE(ATH79_MACH_UBNT_XM,
+++ /dev/null
---- a/arch/mips/ath79/mach-ubnt-xm.c
-+++ b/arch/mips/ath79/mach-ubnt-xm.c
-@@ -13,15 +13,17 @@
- #include <linux/init.h>
- #include <linux/pci.h>
- #include <linux/ath9k_platform.h>
-+#include <linux/etherdevice.h>
-
- #include <asm/mach-ath79/irq.h>
-
- #include "dev-ap9x-pci.h"
-+#include "dev-eth.h"
- #include "dev-gpio-buttons.h"
- #include "dev-leds-gpio.h"
- #include "dev-m25p80.h"
-+#include "dev-usb.h"
- #include "machtypes.h"
--#include "pci.h"
-
- #define UBNT_XM_GPIO_LED_L1 0
- #define UBNT_XM_GPIO_LED_L2 1
-@@ -37,19 +39,19 @@
-
- static struct gpio_led ubnt_xm_leds_gpio[] __initdata = {
- {
-- .name = "ubnt-xm:red:link1",
-+ .name = "ubnt:red:link1",
- .gpio = UBNT_XM_GPIO_LED_L1,
- .active_low = 0,
- }, {
-- .name = "ubnt-xm:orange:link2",
-+ .name = "ubnt:orange:link2",
- .gpio = UBNT_XM_GPIO_LED_L2,
- .active_low = 0,
- }, {
-- .name = "ubnt-xm:green:link3",
-+ .name = "ubnt:green:link3",
- .gpio = UBNT_XM_GPIO_LED_L3,
- .active_low = 0,
- }, {
-- .name = "ubnt-xm:green:link4",
-+ .name = "ubnt:green:link4",
- .gpio = UBNT_XM_GPIO_LED_L4,
- .active_low = 0,
- },
-@@ -66,9 +68,13 @@ static struct gpio_keys_button ubnt_xm_g
- }
- };
-
-+#define UBNT_M_WAN_PHYMASK BIT(4)
-+
- static void __init ubnt_xm_init(void)
- {
- u8 *eeprom = (u8 *) KSEG1ADDR(UBNT_XM_EEPROM_ADDR);
-+ u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000);
-+ u8 *mac2 = (u8 *) KSEG1ADDR(0x1fff0000 + ETH_ALEN);
-
- ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xm_leds_gpio),
- ubnt_xm_leds_gpio);
-@@ -79,9 +85,99 @@ static void __init ubnt_xm_init(void)
-
- ath79_register_m25p80(NULL);
- ap91_pci_init(eeprom, NULL);
-+
-+ ath79_register_mdio(0, ~UBNT_M_WAN_PHYMASK);
-+ ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
-+ ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0);
-+ ath79_register_eth(0);
- }
-
- MIPS_MACHINE(ATH79_MACH_UBNT_XM,
- "UBNT-XM",
- "Ubiquiti Networks XM (rev 1.0) board",
- ubnt_xm_init);
-+
-+MIPS_MACHINE(ATH79_MACH_UBNT_BULLET_M, "UBNT-BM", "Ubiquiti Bullet M",
-+ ubnt_xm_init);
-+
-+static void __init ubnt_rocket_m_setup(void)
-+{
-+ ubnt_xm_init();
-+ ath79_register_usb();
-+}
-+
-+MIPS_MACHINE(ATH79_MACH_UBNT_ROCKET_M, "UBNT-RM", "Ubiquiti Rocket M",
-+ ubnt_rocket_m_setup);
-+
-+static void __init ubnt_nano_m_setup(void)
-+{
-+ ubnt_xm_init();
-+ ath79_register_eth(1);
-+}
-+
-+MIPS_MACHINE(ATH79_MACH_UBNT_NANO_M, "UBNT-NM", "Ubiquiti Nanostation M",
-+ ubnt_nano_m_setup);
-+
-+static struct gpio_led ubnt_airrouter_leds_gpio[] __initdata = {
-+ {
-+ .name = "ubnt:green:globe",
-+ .gpio = 0,
-+ .active_low = 1,
-+ }
-+};
-+
-+static void __init ubnt_airrouter_setup(void)
-+{
-+ u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000);
-+ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
-+
-+ ath79_register_m25p80(NULL);
-+ ath79_register_mdio(0, ~UBNT_M_WAN_PHYMASK);
-+
-+ ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
-+ ath79_init_local_mac(ath79_eth1_data.mac_addr, mac1);
-+
-+ ath79_register_eth(1);
-+ ath79_register_eth(0);
-+ ath79_register_usb();
-+
-+ ap91_pci_init(ee, NULL);
-+ ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_airrouter_leds_gpio),
-+ ubnt_airrouter_leds_gpio);
-+}
-+
-+MIPS_MACHINE(ATH79_MACH_UBNT_AIRROUTER, "UBNT-AR", "Ubiquiti AirRouter",
-+ ubnt_airrouter_setup);
-+
-+static struct gpio_led ubnt_unifi_leds_gpio[] __initdata = {
-+ {
-+ .name = "ubnt:orange:dome",
-+ .gpio = 1,
-+ .active_low = 0,
-+ }, {
-+ .name = "ubnt:green:dome",
-+ .gpio = 0,
-+ .active_low = 0,
-+ }
-+};
-+
-+static void __init ubnt_unifi_setup(void)
-+{
-+ u8 *mac = (u8 *) KSEG1ADDR(0x1fff0000);
-+ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
-+
-+ ath79_register_m25p80(NULL);
-+
-+ ath79_register_mdio(0, ~UBNT_M_WAN_PHYMASK);
-+
-+ ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
-+ ath79_register_eth(0);
-+
-+ ap91_pci_init(ee, NULL);
-+
-+ ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_unifi_leds_gpio),
-+ ubnt_unifi_leds_gpio);
-+}
-+
-+MIPS_MACHINE(ATH79_MACH_UBNT_UNIFI, "UBNT-UF", "Ubiquiti UniFi",
-+ ubnt_unifi_setup);
---- a/arch/mips/ath79/Kconfig
-+++ b/arch/mips/ath79/Kconfig
-@@ -58,9 +58,11 @@ config ATH79_MACH_UBNT_XM
- bool "Ubiquiti Networks XM (rev 1.0) board"
- select SOC_AR724X
- select ATH79_DEV_AP9X_PCI if PCI
-+ select ATH79_DEV_ETH
- select ATH79_DEV_GPIO_BUTTONS
- select ATH79_DEV_LEDS_GPIO
- select ATH79_DEV_M25P80
-+ select ATH79_DEV_USB
- help
- Say 'Y' here if you want your kernel to support the
- Ubiquiti Networks XM (rev 1.0) board.
---- a/arch/mips/ath79/machtypes.h
-+++ b/arch/mips/ath79/machtypes.h
-@@ -21,6 +21,11 @@ enum ath79_mach_type {
- ATH79_MACH_AP81, /* Atheros AP81 reference board */
- ATH79_MACH_DB120, /* Atheros DB120 reference board */
- ATH79_MACH_PB44, /* Atheros PB44 reference board */
-+ ATH79_MACH_UBNT_AIRROUTER, /* Ubiquiti AirRouter */
-+ ATH79_MACH_UBNT_BULLET_M, /* Ubiquiti Bullet M */
-+ ATH79_MACH_UBNT_NANO_M, /* Ubiquiti NanoStation M */
-+ ATH79_MACH_UBNT_ROCKET_M, /* Ubiquiti Rocket M */
-+ ATH79_MACH_UBNT_UNIFI, /* Ubiquiti Unifi */
- ATH79_MACH_UBNT_XM, /* Ubiquiti Networks XM board rev 1.0 */
- };
-
+++ /dev/null
---- a/arch/mips/ath79/machtypes.h
-+++ b/arch/mips/ath79/machtypes.h
-@@ -16,17 +16,81 @@
-
- enum ath79_mach_type {
- ATH79_MACH_GENERIC = 0,
-+ ATH79_MACH_ALFA_AP96, /* ALFA Network AP96 board */
-+ ATH79_MACH_ALFA_NX, /* ALFA Network N2/N5 board */
-+ ATH79_MACH_ALL0258N, /* Allnet ALL0258N */
-+ ATH79_MACH_AP113, /* Atheros AP113 reference board */
- ATH79_MACH_AP121, /* Atheros AP121 reference board */
- ATH79_MACH_AP121_MINI, /* Atheros AP121-MINI reference board */
- ATH79_MACH_AP81, /* Atheros AP81 reference board */
-+ ATH79_MACH_AP83, /* Atheros AP83 */
-+ ATH79_MACH_AP96, /* Atheros AP96 */
-+ ATH79_MACH_AW_NR580, /* AzureWave AW-NR580 */
- ATH79_MACH_DB120, /* Atheros DB120 reference board */
- ATH79_MACH_PB44, /* Atheros PB44 reference board */
-+ ATH79_MACH_DIR_600_A1, /* D-Link DIR-600 rev. A1 */
-+ ATH79_MACH_DIR_615_C1, /* D-Link DIR-615 rev. C1 */
-+ ATH79_MACH_DIR_615_E4, /* D-Link DIR-615 rev. E4 */
-+ ATH79_MACH_DIR_825_B1, /* D-Link DIR-825 rev. B1 */
-+ ATH79_MACH_EAP7660D, /* Senao EAP7660D */
-+ ATH79_MACH_JA76PF, /* jjPlus JA76PF */
-+ ATH79_MACH_JWAP003, /* jjPlus JWAP003 */
-+ ATH79_MACH_HORNET_UB, /* ALFA Networks Hornet-UB */
-+ ATH79_MACH_MZK_W04NU, /* Planex MZK-W04NU */
-+ ATH79_MACH_MZK_W300NH, /* Planex MZK-W300NH */
-+ ATH79_MACH_NBG460N, /* Zyxel NBG460N/550N/550NH */
-+ ATH79_MACH_OM2P, /* OpenMesh OM2P */
-+ ATH79_MACH_PB42, /* Atheros PB42 */
-+ ATH79_MACH_PB92, /* Atheros PB92 */
-+ ATH79_MACH_RB_411, /* MikroTik RouterBOARD 411/411A/411AH */
-+ ATH79_MACH_RB_411U, /* MikroTik RouterBOARD 411U */
-+ ATH79_MACH_RB_433, /* MikroTik RouterBOARD 433/433AH */
-+ ATH79_MACH_RB_433U, /* MikroTik RouterBOARD 433UAH */
-+ ATH79_MACH_RB_450G, /* MikroTik RouterBOARD 450G */
-+ ATH79_MACH_RB_450, /* MikroTik RouterBOARD 450 */
-+ ATH79_MACH_RB_493, /* Mikrotik RouterBOARD 493/493AH */
-+ ATH79_MACH_RB_493G, /* Mikrotik RouterBOARD 493G */
-+ ATH79_MACH_RB_750, /* MikroTik RouterBOARD 750 */
-+ ATH79_MACH_RW2458N, /* Redwave RW2458N */
-+ ATH79_MACH_TEW_632BRP, /* TRENDnet TEW-632BRP */
-+ ATH79_MACH_TL_MR11U, /* TP-LINK TL-MR11U */
-+ ATH79_MACH_TL_MR3020, /* TP-LINK TL-MR3020 */
-+ ATH79_MACH_TL_MR3220, /* TP-LINK TL-MR3220 */
-+ ATH79_MACH_TL_MR3420, /* TP-LINK TL-MR3420 */
-+ ATH79_MACH_TL_WA901ND, /* TP-LINK TL-WA901ND */
-+ ATH79_MACH_TL_WA901ND_V2, /* TP-LINK TL-WA901ND v2 */
-+ ATH79_MACH_TL_WR1043ND, /* TP-LINK TL-WR1041ND */
-+ ATH79_MACH_TL_WR2543N, /* TP-LINK TL-WR2543N/ND */
-+ ATH79_MACH_TL_WR703N, /* TP-LINK TL-WR703N */
-+ ATH79_MACH_TL_WR741ND, /* TP-LINK TL-WR741ND */
-+ ATH79_MACH_TL_WR741ND_V4, /* TP-LINK TL-WR741ND v4*/
-+ ATH79_MACH_TL_WR841N_V1, /* TP-LINK TL-WR841N v1 */
-+ ATH79_MACH_TL_WR841N_V7, /* TP-LINK TL-WR841N/ND v7 */
-+ ATH79_MACH_TL_WR941ND, /* TP-LINK TL-WR941ND */
- ATH79_MACH_UBNT_AIRROUTER, /* Ubiquiti AirRouter */
- ATH79_MACH_UBNT_BULLET_M, /* Ubiquiti Bullet M */
-+ ATH79_MACH_UBNT_LSSR71, /* Ubiquiti LS-SR71 */
-+ ATH79_MACH_UBNT_LSX, /* Ubiquiti LSX */
- ATH79_MACH_UBNT_NANO_M, /* Ubiquiti NanoStation M */
- ATH79_MACH_UBNT_ROCKET_M, /* Ubiquiti Rocket M */
-+ ATH79_MACH_UBNT_RSPRO, /* Ubiquiti RouterStation Pro */
-+ ATH79_MACH_UBNT_RS, /* Ubiquiti RouterStation */
- ATH79_MACH_UBNT_UNIFI, /* Ubiquiti Unifi */
- ATH79_MACH_UBNT_XM, /* Ubiquiti Networks XM board rev 1.0 */
-+ ATH79_MACH_WHR_G301N, /* Buffalo WHR-G301N */
-+ ATH79_MACH_WHR_HP_G300N, /* Buffalo WHR-HP-G300N */
-+ ATH79_MACH_WHR_HP_GN, /* Buffalo WHR-HP-GN */
-+ ATH79_MACH_WNDR3700, /* NETGEAR WNDR3700/WNDR3800/WNDRMAC */
-+ ATH79_MACH_WNR2000, /* NETGEAR WNR2000 */
-+ ATH79_MACH_WP543, /* Compex WP543 */
-+ ATH79_MACH_WPE72, /* Compex WPE72 */
-+ ATH79_MACH_WRT160NL, /* Linksys WRT160NL */
-+ ATH79_MACH_WRT400N, /* Linksys WRT400N */
-+ ATH79_MACH_WZR_HP_AG300H, /* Buffalo WZR-HP-AG300H */
-+ ATH79_MACH_WZR_HP_G300NH, /* Buffalo WZR-HP-G300NH */
-+ ATH79_MACH_WZR_HP_G300NH2, /* Buffalo WZR-HP-G300NH2 */
-+ ATH79_MACH_WZR_HP_G450H, /* Buffalo WZR-HP-G450H */
-+ ATH79_MACH_ZCN_1523H_2, /* Zcomax ZCN-1523H-2-xx */
- };
-
- #endif /* _ATH79_MACHTYPE_H */
---- a/arch/mips/ath79/Kconfig
-+++ b/arch/mips/ath79/Kconfig
-@@ -2,6 +2,52 @@ if ATH79
-
- menu "Atheros AR71XX/AR724X/AR913X machine selection"
-
-+config ATH79_MACH_ALFA_AP96
-+ bool "ALFA Network AP96 board support"
-+ select SOC_AR71XX
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_SPI
-+ select ATH79_DEV_USB
-+
-+config ATH79_MACH_HORNET_UB
-+ bool "ALFA Network Hornet-UB board support"
-+ select SOC_AR933X
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_M25P80
-+ select ATH79_DEV_USB
-+ select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_ALFA_NX
-+ bool "ALFA Network N2/N5 board support"
-+ select SOC_AR724X
-+ select ATH79_DEV_AP9X_PCI if PCI
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_M25P80
-+
-+config ATH79_MACH_ALL0258N
-+ bool "Allnet ALL0258N support"
-+ select SOC_AR724X
-+ select ATH79_DEV_AP9X_PCI if PCI
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_M25P80
-+
-+config ATH79_MACH_AP113
-+ bool "Atheros AP113 board support"
-+ select SOC_AR724X
-+ select ATH79_DEV_M25P80
-+ select ATH79_DEV_PB9X_PCI if PCI
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_USB
-+ select ATH79_DEV_ETH
-+
- config ATH79_MACH_AP121
- bool "Atheros AP121 reference board"
- select SOC_AR933X
-@@ -28,6 +74,36 @@ config ATH79_MACH_AP81
- Say 'Y' here if you want your kernel to support the
- Atheros AP81 reference board.
-
-+config ATH79_MACH_AP83
-+ bool "Atheros AP83 board support"
-+ select SOC_AR913X
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_USB
-+ select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_AP96
-+ bool "Atheros AP96 board support"
-+ select SOC_AR71XX
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_AP9X_PCI if PCI
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_M25P80
-+ select ATH79_DEV_USB
-+
-+config ATH79_MACH_AP121
-+ bool "Atheros AP121 reference board"
-+ select SOC_AR933X
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_SPI
-+ select ATH79_DEV_USB
-+ select ATH79_DEV_WMAC
-+ help
-+ Say 'Y' here if you want your kernel to support the
-+ Atheros AP121 reference board.
-+
- config ATH79_MACH_DB120
- bool "Atheros DB120 reference board"
- select SOC_AR934X
-@@ -42,6 +118,13 @@ config ATH79_MACH_DB120
- Say 'Y' here if you want your kernel to support the
- Atheros DB120 reference board.
-
-+config ATH79_MACH_PB42
-+ bool "Atheros PB42 board support"
-+ select SOC_AR71XX
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_M25P80
-+
- config ATH79_MACH_PB44
- bool "Atheros PB44 reference board"
- select SOC_AR71XX
-@@ -54,6 +137,369 @@ config ATH79_MACH_PB44
- Say 'Y' here if you want your kernel to support the
- Atheros PB44 reference board.
-
-+config ATH79_MACH_PB92
-+ bool "Atheros PB92 board support"
-+ select SOC_AR724X
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_PB9X_PCI if PCI
-+ select ATH79_DEV_USB
-+
-+config ATH79_MACH_AW_NR580
-+ bool "AzureWave AW-NR580 board support"
-+ select SOC_AR71XX
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_M25P80
-+
-+config ATH79_MACH_WHR_HP_G300N
-+ bool "Buffalo WHR-HP-G300N board support"
-+ select SOC_AR724X
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_AP9X_PCI if PCI
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_M25P80
-+
-+config ATH79_MACH_WZR_HP_AG300H
-+ bool "Buffalo WZR-HP-AG300H board support"
-+ select SOC_AR71XX
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_M25P80
-+ select ATH79_DEV_USB
-+
-+config ATH79_MACH_WZR_HP_G300NH
-+ bool "Buffalo WZR-HP-G300NH board support"
-+ select SOC_AR913X
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_USB
-+ select ATH79_DEV_WMAC
-+ select RTL8366_SMI
-+
-+config ATH79_MACH_WZR_HP_G300NH2
-+ bool "Buffalo WZR-HP-G300NH2 board support"
-+ select SOC_AR724X
-+ select ATH79_DEV_AP9X_PCI if PCI
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_M25P80
-+ select ATH79_DEV_USB
-+
-+config ATH79_MACH_WZR_HP_G450H
-+ bool "Buffalo WZR-HP-G450H board support"
-+ select SOC_AR724X
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_AP9X_PCI if PCI
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_M25P80
-+ select ATH79_DEV_USB
-+
-+config ATH79_MACH_WP543
-+ bool "Compex WP543/WPJ543 board support"
-+ select SOC_AR71XX
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_M25P80
-+ select ATH79_DEV_USB
-+ select MYLOADER
-+
-+config ATH79_MACH_WPE72
-+ bool "Compex WPE72/WPE72NX board support"
-+ select SOC_AR724X
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_M25P80
-+ select ATH79_DEV_USB
-+ select MYLOADER
-+
-+config ATH79_MACH_DIR_600_A1
-+ bool "D-Link DIR-600 A1/DIR-615 E4 support"
-+ select SOC_AR724X
-+ select ATH79_DEV_AP9X_PCI if PCI
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_M25P80
-+ select ATH79_NVRAM
-+
-+config ATH79_MACH_DIR_615_C1
-+ bool "D-Link DIR-615 rev. C1 support"
-+ select SOC_AR913X
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_M25P80
-+ select ATH79_DEV_WMAC
-+ select ATH79_NVRAM
-+
-+config ATH79_MACH_DIR_825_B1
-+ bool "D-Link DIR-825 rev. B1 board support"
-+ select SOC_AR71XX
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_AP9X_PCI if PCI
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_M25P80
-+ select ATH79_DEV_USB
-+
-+config ATH79_MACH_JA76PF
-+ bool "jjPlus JA76PF board support"
-+ select SOC_AR71XX
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_M25P80
-+ select ATH79_DEV_USB
-+
-+config ATH79_MACH_JWAP003
-+ bool "jjPlus JWAP003 board support"
-+ select SOC_AR71XX
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_M25P80
-+ select ATH79_DEV_USB
-+
-+config ATH79_MACH_WRT160NL
-+ bool "Linksys WRT160NL board support"
-+ select SOC_AR913X
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_M25P80
-+ select ATH79_DEV_USB
-+ select ATH79_DEV_WMAC
-+ select ATH79_NVRAM
-+
-+config ATH79_MACH_WRT400N
-+ bool "Linksys WRT400N board support"
-+ select SOC_AR71XX
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_AP9X_PCI if PCI
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+
-+config ATH79_MACH_RB4XX
-+ bool "MikroTik RouterBOARD 4xx series support"
-+ select SOC_AR71XX
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_USB
-+
-+config ATH79_MACH_RB750
-+ bool "MikroTik RouterBOARD 750 support"
-+ select SOC_AR724X
-+ select ATH79_DEV_ETH
-+
-+config ATH79_MACH_WNDR3700
-+ bool "NETGEAR WNDR3700 board support"
-+ select SOC_AR71XX
-+ select ATH79_DEV_AP9X_PCI if PCI
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_M25P80
-+ select ATH79_DEV_USB
-+
-+config ATH79_MACH_WNR2000
-+ bool "NETGEAR WNR2000 board support"
-+ select SOC_AR913X
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_M25P80
-+ select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_OM2P
-+ bool "OpenMesh OM2P board support"
-+ select SOC_AR724X
-+ select ATH79_DEV_AP9X_PCI if PCI
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_M25P80
-+
-+config ATH79_MACH_MZK_W04NU
-+ bool "Planex MZK-W04NU board support"
-+ select SOC_AR913X
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_M25P80
-+ select ATH79_DEV_USB
-+ select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_MZK_W300NH
-+ bool "Planex MZK-W300NH board support"
-+ select SOC_AR913X
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_M25P80
-+ select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_RW2458N
-+ bool "Redwave RW2458N board support"
-+ select SOC_AR724X
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_AP9X_PCI if PCI
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_M25P80
-+ select ATH79_DEV_USB
-+
-+config ATH79_MACH_EAP7660D
-+ bool "Senao EAP7660D support"
-+ select SOC_AR71XX
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_M25P80
-+
-+config ATH79_MACH_TL_MR11U
-+ bool "TP-LINK TL-MR11U support"
-+ select SOC_AR933X
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_M25P80
-+ select ATH79_DEV_USB
-+ select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_TL_MR3020
-+ bool "TP-LINK TL-MR3020 support"
-+ select SOC_AR933X
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_M25P80
-+ select ATH79_DEV_USB
-+ select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_TL_MR3X20
-+ bool "TP-LINK TL-MR3220/3420 support"
-+ select SOC_AR724X
-+ select ATH79_DEV_AP9X_PCI if PCI
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_M25P80
-+ select ATH79_DEV_USB
-+
-+config ATH79_MACH_TL_WA901ND
-+ bool "TP-LINK TL-WA901ND support"
-+ select SOC_AR724X
-+ select ATH79_DEV_AP9X_PCI if PCI
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_M25P80
-+
-+config ATH79_MACH_TL_WA901ND_V2
-+ bool "TP-LINK TL-WA901ND v2 support"
-+ select SOC_AR913X
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_M25P80
-+ select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_TL_WR703N
-+ bool "TP-LINK TL-WR703N support"
-+ select SOC_AR933X
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_M25P80
-+ select ATH79_DEV_USB
-+ select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_TL_WR741ND
-+ bool "TP-LINK TL-WR741ND support"
-+ select SOC_AR724X
-+ select ATH79_DEV_AP9X_PCI if PCI
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_M25P80
-+
-+config ATH79_MACH_TL_WR741ND_V4
-+ bool "TP-LINK TL-WR741ND v4 support"
-+ select SOC_AR933X
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_M25P80
-+ select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_TL_WR841N_V1
-+ bool "TP-LINK TL-WR841N v1 support"
-+ select SOC_AR71XX
-+ select ATH79_DEV_DSA
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_M25P80
-+
-+config ATH79_MACH_TL_WR941ND
-+ bool "TP-LINK TL-WR941ND support"
-+ select SOC_AR913X
-+ select ATH79_DEV_DSA
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_M25P80
-+ select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_TL_WR1043ND
-+ bool "TP-LINK TL-WR1043ND support"
-+ select SOC_AR913X
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_M25P80
-+ select ATH79_DEV_USB
-+ select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_TL_WR2543N
-+ bool "TP-LINK TL-WR2543N/ND support"
-+ select SOC_AR724X
-+ select ATH79_DEV_AP9X_PCI if PCI
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_M25P80
-+ select ATH79_DEV_USB
-+
-+config ATH79_MACH_TEW_632BRP
-+ bool "TRENDnet TEW-632BRP support"
-+ select SOC_AR913X
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_M25P80
-+ select ATH79_DEV_WMAC
-+ select ATH79_NVRAM
-+
-+config ATH79_MACH_UBNT
-+ bool "Ubiquiti AR71xx based boards support"
-+ select SOC_AR71XX
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_M25P80
-+ select ATH79_DEV_USB
-+
- config ATH79_MACH_UBNT_XM
- bool "Ubiquiti Networks XM (rev 1.0) board"
- select SOC_AR724X
-@@ -67,6 +513,24 @@ config ATH79_MACH_UBNT_XM
- Say 'Y' here if you want your kernel to support the
- Ubiquiti Networks XM (rev 1.0) board.
-
-+config ATH79_MACH_ZCN_1523H
-+ bool "Zcomax ZCN-1523H support"
-+ select SOC_AR724X
-+ select ATH79_DEV_AP9X_PCI if PCI
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_M25P80
-+
-+config ATH79_MACH_NBG460N
-+ bool "Zyxel NBG460N/550N/550NH board support"
-+ select SOC_AR913X
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_M25P80
-+ select ATH79_DEV_WMAC
-+
- endmenu
-
- config SOC_AR71XX
-@@ -96,10 +560,6 @@ config SOC_AR934X
- select PCI_AR724X if PCI
- def_bool n
-
--config ATH79_DEV_M25P80
-- select ATH79_DEV_SPI
-- def_bool n
--
- config ATH79_DEV_AP9X_PCI
- select ATH79_PCI_ATH9K_FIXUP
- def_bool n
-@@ -110,7 +570,14 @@ config ATH79_DEV_DSA
- config ATH79_DEV_ETH
- def_bool n
-
--config PCI_AR724X
-+config ATH79_DEV_M25P80
-+ select ATH79_DEV_SPI
-+ def_bool n
-+
-+config ATH79_DEV_DSA
-+ def_bool n
-+
-+config ATH79_DEV_ETH
- def_bool n
-
- config ATH79_DEV_GPIO_BUTTONS
-@@ -135,4 +602,7 @@ config ATH79_NVRAM
- config ATH79_PCI_ATH9K_FIXUP
- def_bool n
-
-+config PCI_AR724X
-+ def_bool n
-+
- endif
---- a/arch/mips/ath79/Makefile
-+++ b/arch/mips/ath79/Makefile
-@@ -36,8 +36,56 @@ obj-$(CONFIG_ATH79_PCI_ATH9K_FIXUP) += p
- #
- # Machines
- #
-+obj-$(CONFIG_ATH79_MACH_ALFA_AP96) += mach-alfa-ap96.o
-+obj-$(CONFIG_ATH79_MACH_ALFA_NX) += mach-alfa-nx.o
-+obj-$(CONFIG_ATH79_MACH_ALL0258N) += mach-all0258n.o
-+obj-$(CONFIG_ATH79_MACH_AP113) += mach-ap113.o
- obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o
- obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o
-+obj-$(CONFIG_ATH79_MACH_AP83) += mach-ap83.o
-+obj-$(CONFIG_ATH79_MACH_AP96) += mach-ap96.o
-+obj-$(CONFIG_ATH79_MACH_AW_NR580) += mach-aw-nr580.o
- obj-$(CONFIG_ATH79_MACH_DB120) += mach-db120.o
-+obj-$(CONFIG_ATH79_MACH_DIR_600_A1) += mach-dir-600-a1.o
-+obj-$(CONFIG_ATH79_MACH_DIR_615_C1) += mach-dir-615-c1.o
-+obj-$(CONFIG_ATH79_MACH_DIR_825_B1) += mach-dir-825-b1.o
-+obj-$(CONFIG_ATH79_MACH_EAP7660D) += mach-eap7660d.o
-+obj-$(CONFIG_ATH79_MACH_JA76PF) += mach-ja76pf.o
-+obj-$(CONFIG_ATH79_MACH_JWAP003) += mach-jwap003.o
-+obj-$(CONFIG_ATH79_MACH_HORNET_UB) += mach-hornet-ub.o
-+obj-$(CONFIG_ATH79_MACH_MZK_W04NU) += mach-mzk-w04nu.o
-+obj-$(CONFIG_ATH79_MACH_MZK_W300NH) += mach-mzk-w300nh.o
-+obj-$(CONFIG_ATH79_MACH_NBG460N) += mach-nbg460n.o
-+obj-$(CONFIG_ATH79_MACH_OM2P) += mach-om2p.o
-+obj-$(CONFIG_ATH79_MACH_PB42) += mach-pb42.o
- obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o
-+obj-$(CONFIG_ATH79_MACH_PB92) += mach-pb92.o
-+obj-$(CONFIG_ATH79_MACH_RB4XX) += mach-rb4xx.o
-+obj-$(CONFIG_ATH79_MACH_RB750) += mach-rb750.o
-+obj-$(CONFIG_ATH79_MACH_RW2458N) += mach-rw2458n.o
-+obj-$(CONFIG_ATH79_MACH_TEW_632BRP) += mach-tew-632brp.o
-+obj-$(CONFIG_ATH79_MACH_TL_MR11U) += mach-tl-mr11u.o
-+obj-$(CONFIG_ATH79_MACH_TL_MR3020) += mach-tl-mr3020.o
-+obj-$(CONFIG_ATH79_MACH_TL_MR3X20) += mach-tl-mr3x20.o
-+obj-$(CONFIG_ATH79_MACH_TL_WA901ND) += mach-tl-wa901nd.o
-+obj-$(CONFIG_ATH79_MACH_TL_WA901ND_V2) += mach-tl-wa901nd-v2.o
-+obj-$(CONFIG_ATH79_MACH_TL_WR741ND) += mach-tl-wr741nd.o
-+obj-$(CONFIG_ATH79_MACH_TL_WR741ND_V4) += mach-tl-wr741nd-v4.o
-+obj-$(CONFIG_ATH79_MACH_TL_WR841N_V1) += mach-tl-wr841n.o
-+obj-$(CONFIG_ATH79_MACH_TL_WR941ND) += mach-tl-wr941nd.o
-+obj-$(CONFIG_ATH79_MACH_TL_WR1043ND) += mach-tl-wr1043nd.o
-+obj-$(CONFIG_ATH79_MACH_TL_WR2543N) += mach-tl-wr2543n.o
-+obj-$(CONFIG_ATH79_MACH_TL_WR703N) += mach-tl-wr703n.o
-+obj-$(CONFIG_ATH79_MACH_UBNT) += mach-ubnt.o
- obj-$(CONFIG_ATH79_MACH_UBNT_XM) += mach-ubnt-xm.o
-+obj-$(CONFIG_ATH79_MACH_WHR_HP_G300N) += mach-whr-hp-g300n.o
-+obj-$(CONFIG_ATH79_MACH_WNDR3700) += mach-wndr3700.o
-+obj-$(CONFIG_ATH79_MACH_WNR2000) += mach-wnr2000.o
-+obj-$(CONFIG_ATH79_MACH_WP543) += mach-wp543.o
-+obj-$(CONFIG_ATH79_MACH_WPE72) += mach-wpe72.o
-+obj-$(CONFIG_ATH79_MACH_WRT160NL) += mach-wrt160nl.o
-+obj-$(CONFIG_ATH79_MACH_WRT400N) += mach-wrt400n.o
-+obj-$(CONFIG_ATH79_MACH_WZR_HP_G300NH) += mach-wzr-hp-g300nh.o
-+obj-$(CONFIG_ATH79_MACH_WZR_HP_G300NH2) += mach-wzr-hp-g300nh2.o
-+obj-$(CONFIG_ATH79_MACH_WZR_HP_AG300H) += mach-wzr-hp-ag300h.o
-+obj-$(CONFIG_ATH79_MACH_WZR_HP_G450H) += mach-wzr-hp-g450h.o
+++ /dev/null
---- a/arch/mips/ath79/Kconfig
-+++ b/arch/mips/ath79/Kconfig
-@@ -491,6 +491,17 @@ config ATH79_MACH_TEW_632BRP
- select ATH79_DEV_WMAC
- select ATH79_NVRAM
-
-+config ATH79_MACH_TEW_673GRU
-+ bool "TRENDnet TEW-673GRU support"
-+ select SOC_AR71XX
-+ select ATH79_DEV_AP9X_PCI if PCI
-+ select ATH79_DEV_ETH
-+ select ATH79_DEV_GPIO_BUTTONS
-+ select ATH79_DEV_LEDS_GPIO
-+ select ATH79_DEV_M25P80
-+ select ATH79_DEV_USB
-+ select ATH79_NVRAM
-+
- config ATH79_MACH_UBNT
- bool "Ubiquiti AR71xx based boards support"
- select SOC_AR71XX
---- a/arch/mips/ath79/machtypes.h
-+++ b/arch/mips/ath79/machtypes.h
-@@ -53,6 +53,7 @@ enum ath79_mach_type {
- ATH79_MACH_RB_750, /* MikroTik RouterBOARD 750 */
- ATH79_MACH_RW2458N, /* Redwave RW2458N */
- ATH79_MACH_TEW_632BRP, /* TRENDnet TEW-632BRP */
-+ ATH79_MACH_TEW_673GRU, /* TRENDnet TEW-673GRU */
- ATH79_MACH_TL_MR11U, /* TP-LINK TL-MR11U */
- ATH79_MACH_TL_MR3020, /* TP-LINK TL-MR3020 */
- ATH79_MACH_TL_MR3220, /* TP-LINK TL-MR3220 */
---- a/arch/mips/ath79/Makefile
-+++ b/arch/mips/ath79/Makefile
-@@ -64,6 +64,7 @@ obj-$(CONFIG_ATH79_MACH_RB4XX) += mach-
- obj-$(CONFIG_ATH79_MACH_RB750) += mach-rb750.o
- obj-$(CONFIG_ATH79_MACH_RW2458N) += mach-rw2458n.o
- obj-$(CONFIG_ATH79_MACH_TEW_632BRP) += mach-tew-632brp.o
-+obj-$(CONFIG_ATH79_MACH_TEW_673GRU) += mach-tew-673gru.o
- obj-$(CONFIG_ATH79_MACH_TL_MR11U) += mach-tl-mr11u.o
- obj-$(CONFIG_ATH79_MACH_TL_MR3020) += mach-tl-mr3020.o
- obj-$(CONFIG_ATH79_MACH_TL_MR3X20) += mach-tl-mr3x20.o
+++ /dev/null
---- a/arch/mips/ath79/machtypes.h
-+++ b/arch/mips/ath79/machtypes.h
-@@ -34,6 +34,7 @@ enum ath79_mach_type {
- ATH79_MACH_DIR_825_B1, /* D-Link DIR-825 rev. B1 */
- ATH79_MACH_EAP7660D, /* Senao EAP7660D */
- ATH79_MACH_JA76PF, /* jjPlus JA76PF */
-+ ATH79_MACH_JA76PF2, /* jjPlus JA76PF2 */
- ATH79_MACH_JWAP003, /* jjPlus JWAP003 */
- ATH79_MACH_HORNET_UB, /* ALFA Networks Hornet-UB */
- ATH79_MACH_MZK_W04NU, /* Planex MZK-W04NU */
+++ /dev/null
---- a/arch/mips/ath79/machtypes.h
-+++ b/arch/mips/ath79/machtypes.h
-@@ -52,6 +52,7 @@ enum ath79_mach_type {
- ATH79_MACH_RB_493, /* Mikrotik RouterBOARD 493/493AH */
- ATH79_MACH_RB_493G, /* Mikrotik RouterBOARD 493G */
- ATH79_MACH_RB_750, /* MikroTik RouterBOARD 750 */
-+ ATH79_MACH_RB_750G_R3, /* MikroTik RouterBOARD 750GL */
- ATH79_MACH_RW2458N, /* Redwave RW2458N */
- ATH79_MACH_TEW_632BRP, /* TRENDnet TEW-632BRP */
- ATH79_MACH_TEW_673GRU, /* TRENDnet TEW-673GRU */
---- a/arch/mips/ath79/prom.c
-+++ b/arch/mips/ath79/prom.c
-@@ -180,6 +180,9 @@ void __init prom_init(void)
- ath79_prom_append_cmdline("board", env);
- }
- }
-+
-+ if (strstr(arcs_cmdline, "board=750Gr3"))
-+ ath79_prom_append_cmdline("console", "ttyS0,115200");
- }
-
- void __init prom_free_prom_memory(void)
+++ /dev/null
---- a/arch/mips/ath79/Kconfig
-+++ b/arch/mips/ath79/Kconfig
-@@ -300,6 +300,8 @@ config ATH79_MACH_RB750
- bool "MikroTik RouterBOARD 750 support"
- select SOC_AR724X
- select ATH79_DEV_ETH
-+ select ATH79_DEV_AP9X_PCI if PCI
-+ select ATH79_DEV_USB
-
- config ATH79_MACH_WNDR3700
- bool "NETGEAR WNDR3700 board support"
---- a/arch/mips/ath79/machtypes.h
-+++ b/arch/mips/ath79/machtypes.h
-@@ -53,6 +53,8 @@ enum ath79_mach_type {
- ATH79_MACH_RB_493G, /* Mikrotik RouterBOARD 493G */
- ATH79_MACH_RB_750, /* MikroTik RouterBOARD 750 */
- ATH79_MACH_RB_750G_R3, /* MikroTik RouterBOARD 750GL */
-+ ATH79_MACH_RB_751, /* MikroTik RouterBOARD 751 */
-+ ATH79_MACH_RB_751G, /* Mikrotik RouterBOARD 751G */
- ATH79_MACH_RW2458N, /* Redwave RW2458N */
- ATH79_MACH_TEW_632BRP, /* TRENDnet TEW-632BRP */
- ATH79_MACH_TEW_673GRU, /* TRENDnet TEW-673GRU */
+++ /dev/null
---- a/arch/mips/ath79/dev-usb.c
-+++ b/arch/mips/ath79/dev-usb.c
-@@ -190,16 +190,16 @@ static void __init ar934x_usb_setup(void
- if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE)
- return;
-
-- ath79_device_reset_clear(AR934X_RESET_USBSUS_OVERRIDE);
-+ ath79_device_reset_set(AR934X_RESET_USBSUS_OVERRIDE);
- udelay(1000);
-
-- ath79_device_reset_set(AR934X_RESET_USB_PHY);
-+ ath79_device_reset_clear(AR934X_RESET_USB_PHY);
- udelay(1000);
-
-- ath79_device_reset_set(AR934X_RESET_USB_PHY_ANALOG);
-+ ath79_device_reset_clear(AR934X_RESET_USB_PHY_ANALOG);
- udelay(1000);
-
-- ath79_device_reset_set(AR934X_RESET_USB_HOST);
-+ ath79_device_reset_clear(AR934X_RESET_USB_HOST);
- udelay(1000);
-
- ath79_ehci_resources[0].start = AR934X_EHCI_BASE;
+++ /dev/null
---- a/drivers/net/phy/mdio-bitbang.c
-+++ b/drivers/net/phy/mdio-bitbang.c
-@@ -165,16 +165,7 @@ static int mdiobb_read(struct mii_bus *b
-
- ctrl->ops->set_mdio_dir(ctrl, 0);
-
-- /* check the turnaround bit: the PHY should be driving it to zero */
-- if (mdiobb_get_bit(ctrl) != 0) {
-- /* PHY didn't drive TA low -- flush any bits it
-- * may be trying to send.
-- */
-- for (i = 0; i < 32; i++)
-- mdiobb_get_bit(ctrl);
--
-- return 0xffff;
-- }
-+ mdiobb_get_bit(ctrl);
-
- ret = mdiobb_get_num(ctrl, 16);
- mdiobb_get_bit(ctrl);
+++ /dev/null
---- a/arch/mips/include/asm/checksum.h
-+++ b/arch/mips/include/asm/checksum.h
-@@ -12,6 +12,7 @@
- #define _ASM_CHECKSUM_H
-
- #include <linux/in6.h>
-+#include <linux/unaligned/packed_struct.h>
-
- #include <asm/uaccess.h>
-
-@@ -104,26 +105,30 @@ static inline __sum16 ip_fast_csum(const
- const unsigned int *stop = word + ihl;
- unsigned int csum;
- int carry;
-+ unsigned int w;
-
-- csum = word[0];
-- csum += word[1];
-- carry = (csum < word[1]);
-+ csum = __get_unaligned_cpu32(word++);
-+
-+ w = __get_unaligned_cpu32(word++);
-+ csum += w;
-+ carry = (csum < w);
- csum += carry;
-
-- csum += word[2];
-- carry = (csum < word[2]);
-+ w = __get_unaligned_cpu32(word++);
-+ csum += w;
-+ carry = (csum < w);
- csum += carry;
-
-- csum += word[3];
-- carry = (csum < word[3]);
-+ w = __get_unaligned_cpu32(word++);
-+ csum += w;
-+ carry = (csum < w);
- csum += carry;
-
-- word += 4;
- do {
-- csum += *word;
-- carry = (csum < *word);
-+ w = __get_unaligned_cpu32(word++);
-+ csum += w;
-+ carry = (csum < w);
- csum += carry;
-- word++;
- } while (word != stop);
-
- return csum_fold(csum);
---- a/include/linux/ip.h
-+++ b/include/linux/ip.h
-@@ -102,7 +102,7 @@ struct iphdr {
- __be32 saddr;
- __be32 daddr;
- /*The options start here. */
--};
-+} __packed;
-
- #ifdef __KERNEL__
- #include <linux/skbuff.h>
---- a/include/linux/ipv6.h
-+++ b/include/linux/ipv6.h
-@@ -126,7 +126,7 @@ struct ipv6hdr {
-
- struct in6_addr saddr;
- struct in6_addr daddr;
--};
-+} __packed;
-
- #ifdef __KERNEL__
- /*
---- a/include/linux/tcp.h
-+++ b/include/linux/tcp.h
-@@ -54,7 +54,7 @@ struct tcphdr {
- __be16 window;
- __sum16 check;
- __be16 urg_ptr;
--};
-+} __packed;
-
- /*
- * The union cast uses a gcc extension to avoid aliasing problems
---- a/include/linux/udp.h
-+++ b/include/linux/udp.h
-@@ -24,7 +24,7 @@ struct udphdr {
- __be16 dest;
- __be16 len;
- __sum16 check;
--};
-+} __packed;
-
- /* UDP socket options */
- #define UDP_CORK 1 /* Never send partially complete segments */
---- a/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4.c
-+++ b/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4.c
-@@ -14,6 +14,7 @@
- #include <linux/skbuff.h>
- #include <linux/icmp.h>
- #include <linux/sysctl.h>
-+#include <linux/unaligned/packed_struct.h>
- #include <net/route.h>
- #include <net/ip.h>
-
-@@ -44,8 +45,8 @@ static bool ipv4_pkt_to_tuple(const stru
- if (ap == NULL)
- return false;
-
-- tuple->src.u3.ip = ap[0];
-- tuple->dst.u3.ip = ap[1];
-+ tuple->src.u3.ip = __get_unaligned_cpu32(ap++);
-+ tuple->dst.u3.ip = __get_unaligned_cpu32(ap);
-
- return true;
- }
+++ /dev/null
---- a/include/linux/netdevice.h
-+++ b/include/linux/netdevice.h
-@@ -1908,6 +1908,33 @@ static inline int netif_tx_queue_frozen_
- return dev_queue->state & QUEUE_STATE_XOFF_OR_FROZEN;
- }
-
-+static inline void netdev_tx_sent_queue(struct netdev_queue *dev_queue,
-+ unsigned int bytes)
-+{
-+}
-+
-+static inline void netdev_sent_queue(struct net_device *dev, unsigned int bytes)
-+{
-+}
-+
-+static inline void netdev_tx_completed_queue(struct netdev_queue *dev_queue,
-+ unsigned pkts, unsigned bytes)
-+{
-+}
-+
-+static inline void netdev_completed_queue(struct net_device *dev,
-+ unsigned pkts, unsigned bytes)
-+{
-+}
-+
-+static inline void netdev_tx_reset_queue(struct netdev_queue *q)
-+{
-+}
-+
-+static inline void netdev_reset_queue(struct net_device *dev_queue)
-+{
-+}
-+
- /**
- * netif_running - test if up
- * @dev: network device
projects / openwrt / staging / stintel.git / commitdiff