clk: tegra: Fix sparse warning for pll_m
authorJon Hunter <jonathanh@nvidia.com>
Fri, 4 Dec 2015 17:04:23 +0000 (17:04 +0000)
committerThierry Reding <treding@nvidia.com>
Tue, 2 Feb 2016 14:49:32 +0000 (15:49 +0100)
Sparse generates the following warning for the pll_m params structure:

drivers/clk/tegra/clk-tegra210.c:1569:10: warning: Initializer entry
 defined twice
drivers/clk/tegra/clk-tegra210.c:1570:10:   also defined here

Fix this by correcting the index for the MISC1 register.

Fixes: b31eba5ff3f7 ("clk: tegra: Add support for Tegra210 clocks")
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/clk/tegra/clk-tegra210.c

index ca04c2d85e2b7ccc83e18a7e75c00bffce6bb739..271ea1580d91241d6c25e0d8f4b578d0b63aa141 100644 (file)
@@ -1566,7 +1566,7 @@ static struct tegra_clk_pll_params pll_m_params = {
        .iddq_bit_idx = PLLM_IDDQ_BIT,
        .max_p = PLL_QLIN_PDIV_MAX,
        .ext_misc_reg[0] = PLLM_MISC2,
-       .ext_misc_reg[0] = PLLM_MISC1,
+       .ext_misc_reg[1] = PLLM_MISC1,
        .round_p_to_pdiv = pll_qlin_p_to_pdiv,
        .pdiv_tohw = pll_qlin_pdiv_to_hw,
        .div_nmp = &pllm_nmp,