Add support for selected Cortex-A57 errata workarounds

This patch adds workarounds for selected errata which affect the Cortex-A57 r0p0
part. Each workaround has a build time flag which should be used by the platform
port to enable or disable the corresponding workaround. The workarounds are
disabled by default. An assertion is raised if the platform enables a workaround
which does not match the CPU revision at runtime.

Change-Id: I9ae96b01c6ff733d04dc733bd4e67dbf77b29fb0

diff --git a/Makefile b/Makefile
index 6f6d703738f4193bc858d8035d91b4d0ef0fcc91..8c97b49543a254f2715748c9a9883ad256aec532 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -138,6 +138,10 @@ msg_start:
 
 include plat/${PLAT}/platform.mk
 
+# By default all CPU errata workarounds are disabled. This can be
+# overridden by the platform.
+include lib/cpus/cpu-errata.mk
+
 ifdef BL1_SOURCES
 NEED_BL1 := yes
 include bl1/bl1.mk

diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index 97242ccbf9a5619b36a929769dfc3857bdb3d952..b2aac2fb70271d16d3c4af8ab848ebfb5dc95a84 100644 (file)
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -37,6 +37,8 @@
  ******************************************************************************/
 #define MIDR_IMPL_MASK         0xff
 #define MIDR_IMPL_SHIFT                0x18
+#define MIDR_VAR_SHIFT         20
+#define MIDR_REV_SHIFT         0
 #define MIDR_PN_MASK           0xfff
 #define MIDR_PN_SHIFT          0x4
 

diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h
index dc0e0f4eafb6862fd615a44b7022d9cb27018b84..9cf8780d014afb4bafbeed55a665c3547dba69d7 100644 (file)
--- a/include/lib/cpus/aarch64/cortex_a57.h
+++ b/include/lib/cpus/aarch64/cortex_a57.h
@@ -44,4 +44,12 @@
 #define CPUECTLR_L2_IPFTCH_DIST_MASK   (0x3 << 35)
 #define CPUECTLR_L2_DPFTCH_DIST_MASK   (0x3 << 32)
 
+/*******************************************************************************
+ * CPU Auxiliary Control register specific definitions.
+ ******************************************************************************/
+#define CPUACTLR_EL1                   S3_1_C15_C2_0   /* Instruction def. */
+
+#define CPUACTLR_NO_ALLOC_WBWA         (1 << 49)
+#define CPUACTLR_DCC_AS_DCCI           (1 << 44)
+
 #endif /* __CORTEX_A57_H__ */

diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S
index 8b788566db36a1e983484e7e4262c422c6c7e518..eed1bbb9f47c06cc2fa23abec3f0d6e604fcd12f 100644 (file)
--- a/lib/cpus/aarch64/cortex_a57.S
+++ b/lib/cpus/aarch64/cortex_a57.S
@@ -29,6 +29,7 @@
  */
 #include <arch.h>
 #include <asm_macros.S>
+#include <assert_macros.S>
 #include <cortex_a57.h>
 #include <cpu_macros.S>
 #include <plat_macros.S>
@@ -81,6 +82,32 @@ func cortex_a57_disable_ext_debug
        ret
 
 func cortex_a57_reset_func
+#if ERRATA_A57_806969 || ERRATA_A57_813420
+       /* ---------------------------------------------
+        * Ensure that the following errata is only
+        * applied on r0p0 parts.
+        * ---------------------------------------------
+        */
+#if ASM_ASSERTION
+       mrs     x0, midr_el1
+       ubfx    x1, x0, #MIDR_VAR_SHIFT, #4
+       ubfx    x2, x0, #MIDR_REV_SHIFT, #4
+       orr     x0, x1, x2
+       cmp     x0, #0
+       ASM_ASSERT(eq)
+#endif
+       mov     x1, xzr
+#if ERRATA_A57_806969
+       orr     x1, x1, #CPUACTLR_NO_ALLOC_WBWA
+#endif
+#if ERRATA_A57_813420
+       orr     x1, x1, #CPUACTLR_DCC_AS_DCCI
+#endif
+       mrs     x0, CPUACTLR_EL1
+       orr     x0, x0, x1
+       msr     CPUACTLR_EL1, x0
+#endif
+
        /* ---------------------------------------------
         * As a bare minimum enable the SMP bit.
         * ---------------------------------------------

diff --git a/lib/cpus/cpu-errata.mk b/lib/cpus/cpu-errata.mk
new file mode 100644 (file)
index 0000000..79f0156
--- /dev/null
+++ b/lib/cpus/cpu-errata.mk
@@ -0,0 +1,48 @@
+#
+# Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# Neither the name of ARM nor the names of its contributors may be used
+# to endorse or promote products derived from this software without specific
+# prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+# CPU Errata Build flags. These should be enabled by the
+# platform if the errata needs to be applied.
+
+# Flag to apply errata 806969 during reset. This errata applies only to
+# revision r0p0 of the Cortex A57 cpu.
+ERRATA_A57_806969      ?=0
+
+# Flag to apply errata 813420 during reset. This errata applies only to
+# revision r0p0 of the Cortex A57 cpu.
+ERRATA_A57_813420      ?=0
+
+# Process ERRATA_A57_806969 flag
+$(eval $(call assert_boolean,ERRATA_A57_806969))
+$(eval $(call add_define,ERRATA_A57_806969))
+
+# Process ERRATA_A57_813420 flag
+$(eval $(call assert_boolean,ERRATA_A57_813420))
+$(eval $(call add_define,ERRATA_A57_813420))