drm/amd/powerplay: avoid enabling/disabling uvd/vce dpm twice

For vega20, there are two UVD rings which share one powerplay instance.
Under some case(two rings used parallel), the uvd dpm is disabled twice
which causes the SMC hang.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <rezhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index ad6ce148fb3fde151b92c24f3ca7e3d4afd0a492..c4302bc41a2417910004b48768bf6f866a48ff66 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -2464,6 +2464,9 @@ static void vega20_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
 {
        struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
 
+       if (data->vce_power_gated == bgate)
+               return ;
+
        data->vce_power_gated = bgate;
        vega20_enable_disable_vce_dpm(hwmgr, !bgate);
 }
@@ -2472,6 +2475,9 @@ static void vega20_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
 {
        struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
 
+       if (data->uvd_power_gated == bgate)
+               return ;
+
        data->uvd_power_gated = bgate;
        vega20_enable_disable_uvd_dpm(hwmgr, !bgate);
 }