#gpio-cells = <2>;
ralink,gpio-base = <0>;
- ralink,num-gpios = <24>;
+ ralink,nr-gpio = <24>;
ralink,register-map = [ 00 04 08 0c
20 24 28 2c
30 34 ];
#gpio-cells = <2>;
ralink,gpio-base = <24>;
- ralink,num-gpios = <16>;
+ ralink,nr-gpio = <16>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];
#gpio-cells = <2>;
ralink,gpio-base = <40>;
- ralink,num-gpios = <32>;
+ ralink,nr-gpio = <32>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];
#gpio-cells = <2>;
ralink,gpio-base = <72>;
- ralink,num-gpios = <1>;
+ ralink,nr-gpio = <1>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];
#gpio-cells = <2>;
ralink,gpio-base = <0>;
- ralink,num-gpios = <24>;
+ ralink,nr-gpio = <24>;
ralink,register-map = [ 00 04 08 0c
20 24 28 2c
30 34 ];
#gpio-cells = <2>;
ralink,gpio-base = <24>;
- ralink,num-gpios = <16>;
+ ralink,nr-gpio = <16>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];
#gpio-cells = <2>;
ralink,gpio-base = <40>;
- ralink,num-gpios = <32>;
+ ralink,nr-gpio = <32>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];
#gpio-cells = <2>;
ralink,gpio-base = <72>;
- ralink,num-gpios = <1>;
+ ralink,nr-gpio = <1>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];
#gpio-cells = <2>;
ralink,gpio-base = <0>;
- ralink,num-gpios = <24>;
+ ralink,nr-gpio = <24>;
ralink,register-map = [ 00 04 08 0c
20 24 28 2c
30 34 ];
#gpio-cells = <2>;
ralink,gpio-base = <24>;
- ralink,num-gpios = <16>;
+ ralink,nr-gpio = <16>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];
#gpio-cells = <2>;
ralink,gpio-base = <40>;
- ralink,num-gpios = <32>;
+ ralink,nr-gpio = <32>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];
#gpio-cells = <2>;
ralink,gpio-base = <0>;
- ralink,num-gpios = <24>;
+ ralink,nr-gpio = <24>;
ralink,register-map = [ 00 04 08 0c
20 24 28 2c
30 34 ];
#gpio-cells = <2>;
ralink,gpio-base = <24>;
- ralink,num-gpios = <16>;
+ ralink,nr-gpio = <16>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];
#gpio-cells = <2>;
ralink,gpio-base = <40>;
- ralink,num-gpios = <12>;
+ ralink,nr-gpio = <12>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];
#gpio-cells = <2>;
ralink,gpio-base = <0>;
- ralink,num-gpios = <24>;
+ ralink,nr-gpio = <24>;
ralink,register-map = [ 00 04 08 0c
20 24 28 2c
30 34 ];
#gpio-cells = <2>;
ralink,gpio-base = <24>;
- ralink,num-gpios = <16>;
+ ralink,nr-gpio = <16>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];
#gpio-cells = <2>;
ralink,gpio-base = <40>;
- ralink,num-gpios = <6>;
+ ralink,nr-gpio = <6>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];
#gpio-cells = <2>;
ralink,gpio-base = <0>;
- ralink,num-gpios = <24>;
+ ralink,nr-gpio = <24>;
ralink,register-map = [ 00 04 08 0c
20 24 28 2c
30 34 ];
#gpio-cells = <2>;
ralink,gpio-base = <24>;
- ralink,num-gpios = <16>;
+ ralink,nr-gpio = <16>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];
#gpio-cells = <2>;
ralink,gpio-base = <40>;
- ralink,num-gpios = <32>;
+ ralink,nr-gpio = <32>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];
#gpio-cells = <2>;
ralink,gpio-base = <72>;
- ralink,num-gpios = <24>;
+ ralink,nr-gpio = <24>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];
#gpio-cells = <2>;
ralink,gpio-base = <0>;
- ralink,num-gpios = <22>;
+ ralink,nr-gpio = <22>;
ralink,register-map = [ 00 04 08 0c
20 24 28 2c
30 34 ];
#gpio-cells = <2>;
ralink,gpio-base = <22>;
- ralink,num-gpios = <6>;
+ ralink,nr-gpio = <6>;
ralink,register-map = [ 00 04 08 0c
10 14 18 1c
20 24 ];
+ if (!of_device_is_available(np))
+ continue;
+
-+ ngpio = of_get_property(np, "ralink,num-gpios", NULL);
++ ngpio = of_get_property(np, "ralink,nr-gpio", NULL);
+ gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
+ if (!ngpio || !gpiobase) {
+ dev_err(&pdev->dev, "failed to load chip info\n");
+- reg : Physical base address and length of the controller's registers
+- interrupt-parent: phandle to the INTC device node
+- interrupts : Specify the INTC interrupt number
-+- ralink,num-gpios : Specify the number of GPIOs
++- ralink,nr-gpio : Specify the number of GPIOs
+- ralink,register-map : The register layout depends on the GPIO bank and actual
+ SoC type. Register offsets need to be in this order.
+ [ INT, EDGE, RENA, FENA, DATA, DIR, POL, SET, RESET, TOGGLE ]
+ interrupts = <6>;
+
+ ralink,gpio-base = <0>;
-+ ralink,num-gpios = <24>;
++ ralink,nr-gpio = <24>;
+ ralink,register-map = [ 00 04 08 0c
+ 20 24 28 2c
+ 30 34 ];
+ return -EINVAL;
+ }
+
-+ ngpio = of_get_property(np, "ralink,num-gpios", NULL);
++ ngpio = of_get_property(np, "ralink,nr-gpio", NULL);
+ if (!ngpio) {
+ dev_err(&pdev->dev, "failed to read number of pins\n");
+ return -EINVAL;