drm/i915: Add missing 10bpc formats for pipe B sprites on CHV

CHV pipe B sprites gained support for the 10bpc X/ARGB pixel formats.
On VLV and CHV pipe A/C these are only supported by the primary
plane. Add the require bits to expose the new formats.

v2: Reorder the formats for consistency

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191031165652.10868-4-ville.syrjala@linux.intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 21d6e2f2e514621acb9ae0b7678772f58cd6be11..8726e7f38a0784bc9ab88ff6cd13d58f9b1eb68e 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -958,6 +958,12 @@ static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
        case DRM_FORMAT_ABGR2101010:
                sprctl |= SP_FORMAT_RGBA1010102;
                break;
+       case DRM_FORMAT_XRGB2101010:
+               sprctl |= SP_FORMAT_BGRX1010102;
+               break;
+       case DRM_FORMAT_ARGB2101010:
+               sprctl |= SP_FORMAT_BGRA1010102;
+               break;
        case DRM_FORMAT_XBGR8888:
                sprctl |= SP_FORMAT_RGBX8888;
                break;
@@ -2391,6 +2397,22 @@ static const u32 vlv_plane_formats[] = {
        DRM_FORMAT_VYUY,
 };
 
+static const u32 chv_pipe_b_sprite_formats[] = {
+       DRM_FORMAT_RGB565,
+       DRM_FORMAT_XRGB8888,
+       DRM_FORMAT_XBGR8888,
+       DRM_FORMAT_ARGB8888,
+       DRM_FORMAT_ABGR8888,
+       DRM_FORMAT_XRGB2101010,
+       DRM_FORMAT_XBGR2101010,
+       DRM_FORMAT_ARGB2101010,
+       DRM_FORMAT_ABGR2101010,
+       DRM_FORMAT_YUYV,
+       DRM_FORMAT_YVYU,
+       DRM_FORMAT_UYVY,
+       DRM_FORMAT_VYUY,
+};
+
 static const u32 skl_plane_formats[] = {
        DRM_FORMAT_C8,
        DRM_FORMAT_RGB565,
@@ -2623,6 +2645,8 @@ static bool vlv_sprite_format_mod_supported(struct drm_plane *_plane,
        case DRM_FORMAT_XRGB8888:
        case DRM_FORMAT_XBGR2101010:
        case DRM_FORMAT_ABGR2101010:
+       case DRM_FORMAT_XRGB2101010:
+       case DRM_FORMAT_ARGB2101010:
        case DRM_FORMAT_YUYV:
        case DRM_FORMAT_YVYU:
        case DRM_FORMAT_UYVY:
@@ -3019,8 +3043,13 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
                plane->check_plane = vlv_sprite_check;
                plane->min_cdclk = vlv_plane_min_cdclk;
 
-               formats = vlv_plane_formats;
-               num_formats = ARRAY_SIZE(vlv_plane_formats);
+               if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
+                       formats = chv_pipe_b_sprite_formats;
+                       num_formats = ARRAY_SIZE(chv_pipe_b_sprite_formats);
+               } else {
+                       formats = vlv_plane_formats;
+                       num_formats = ARRAY_SIZE(vlv_plane_formats);
+               }
                modifiers = i9xx_plane_format_modifiers;
 
                plane_funcs = &vlv_sprite_funcs;

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b819392ba700125aa4bdd0337d38c934bcc60c7c..78dfdcfc724a651f351613849701efc7928a6181 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6628,12 +6628,14 @@ enum {
 #define   SP_ENABLE                    (1 << 31)
 #define   SP_GAMMA_ENABLE              (1 << 30)
 #define   SP_PIXFORMAT_MASK            (0xf << 26)
-#define   SP_FORMAT_YUV422             (0 << 26)
-#define   SP_FORMAT_BGR565             (5 << 26)
-#define   SP_FORMAT_BGRX8888           (6 << 26)
-#define   SP_FORMAT_BGRA8888           (7 << 26)
-#define   SP_FORMAT_RGBX1010102                (8 << 26)
-#define   SP_FORMAT_RGBA1010102                (9 << 26)
+#define   SP_FORMAT_YUV422             (0x0 << 26)
+#define   SP_FORMAT_BGR565             (0x5 << 26)
+#define   SP_FORMAT_BGRX8888           (0x6 << 26)
+#define   SP_FORMAT_BGRA8888           (0x7 << 26)
+#define   SP_FORMAT_RGBX1010102                (0x8 << 26)
+#define   SP_FORMAT_RGBA1010102                (0x9 << 26)
+#define   SP_FORMAT_BGRX1010102                (0xa << 26) /* CHV pipe B */
+#define   SP_FORMAT_BGRA1010102                (0xb << 26) /* CHV pipe B */
 #define   SP_FORMAT_RGBX8888           (0xe << 26)
 #define   SP_FORMAT_RGBA8888           (0xf << 26)
 #define   SP_ALPHA_PREMULTIPLY         (1 << 23) /* CHV pipe B */