ARM: DRA72x: Add support for detection of SR2.0
authorRavi Babu <ravibabu@ti.com>
Tue, 15 Mar 2016 23:09:11 +0000 (18:09 -0500)
committerTom Rini <trini@konsulko.com>
Sun, 27 Mar 2016 13:12:12 +0000 (09:12 -0400)
Add support for detection of SR2.0 version of DRA72x family of
processors.

Signed-off-by: Ravi Babu <ravibabu@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
arch/arm/cpu/armv7/omap5/hw_data.c
arch/arm/cpu/armv7/omap5/hwinit.c
arch/arm/cpu/armv7/omap5/sdram.c
arch/arm/include/asm/arch-omap5/omap.h
arch/arm/include/asm/omap_common.h

index 7f8c0a423bad59305ecaa2ce4e4ae8d5ee9c65de..93d1efbca17de0a7b79b73545e761d763733c3e5 100644 (file)
@@ -775,6 +775,7 @@ void __weak hw_data_init(void)
        break;
 
        case DRA722_ES1_0:
+       case DRA722_ES2_0:
        *prcm = &dra7xx_prcm;
        *dplls_data = &dra72x_dplls;
        *omap_vcores = &dra722_volts;
@@ -807,6 +808,7 @@ void get_ioregs(const struct ctrl_ioregs **regs)
                *regs = &ioregs_dra7xx_es1;
                break;
        case DRA722_ES1_0:
+       case DRA722_ES2_0:
                *regs = &ioregs_dra72x_es1;
                break;
 
index 8f184df2abb74a5bbb0d7d7c33a56f0d9cbc0e43..e3ac8bbe9524744860c69c966364fd9392cb1f86 100644 (file)
@@ -373,6 +373,9 @@ void init_omap_revision(void)
        case DRA722_CONTROL_ID_CODE_ES1_0:
                *omap_si_rev = DRA722_ES1_0;
                break;
+       case DRA722_CONTROL_ID_CODE_ES2_0:
+               *omap_si_rev = DRA722_ES2_0;
+               break;
        default:
                *omap_si_rev = OMAP5430_SILICON_ID_INVALID;
        }
index 7dc5bb7e4a4b4ee5819b090ae57306092c749e70..5cf360c41468986ad8386d6ee6089b493c5671ba 100644 (file)
@@ -438,6 +438,7 @@ void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
                }
                break;
        case DRA722_ES1_0:
+       case DRA722_ES2_0:
                *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz;
                *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz);
                break;
@@ -670,6 +671,7 @@ const struct read_write_regs *get_bug_regs(u32 *iterations)
        case DRA752_ES1_1:
        case DRA752_ES2_0:
        case DRA722_ES1_0:
+       case DRA722_ES2_0:
                bug_00339_regs_ptr = dra_bug_00339_regs;
                *iterations = sizeof(dra_bug_00339_regs)/
                             sizeof(dra_bug_00339_regs[0]);
index b5b3838f45003f6cbb37ffcd2bf7ad6cb9d8edce..1eeb8d5f626fdcae627872a87183101d76febe2b 100644 (file)
@@ -60,6 +60,7 @@
 #define DRA752_CONTROL_ID_CODE_ES1_1           0x1B99002F
 #define DRA752_CONTROL_ID_CODE_ES2_0           0x2B99002F
 #define DRA722_CONTROL_ID_CODE_ES1_0           0x0B9BC02F
+#define DRA722_CONTROL_ID_CODE_ES2_0           0x1B9BC02F
 
 /* UART */
 #define UART1_BASE             (OMAP54XX_L4_PER_BASE + 0x6a000)
index aef31266ce9e9c386d7d84302beb3b022e7466b7..8c85f46db6ef66b3093ced39ae45efdaa2303a5d 100644 (file)
@@ -700,6 +700,7 @@ static inline u8 is_dra72x(void)
 #define DRA752_ES1_1   0x07520110
 #define DRA752_ES2_0   0x07520200
 #define DRA722_ES1_0   0x07220100
+#define DRA722_ES2_0   0x07220200
 
 /*
  * SRAM scratch space entries