#define PCR_RSVDA_MAX 2
-/* pci config status reg has a bit to indicate that capability ptr is present */
-
-#define PCI_CAPPTR_PRESENT 0x0010
-
typedef struct _pci_config_regs {
u16 vendor;
u16 device;
u8 dev_dep[192];
} ppb_config_regs;
-/* PCI CAPABILITY DEFINES */
-#define PCI_CAP_POWERMGMTCAP_ID 0x01
-#define PCI_CAP_PCIECAP_ID 0x10
-
-#define PME_CAP_PM_STATES (0x1f << 27) /* Bits 31:27 states that can generate PME */
-#define PME_CSR_OFFSET 0x4 /* 4-bytes offset */
-#define PME_CSR_PME_EN (1 << 8) /* Bit 8 Enable generating of PME */
-#define PME_CSR_PME_STAT (1 << 15) /* Bit 15 PME got asserted */
-
/* Everything below is BRCM HND proprietary */
/* Brcm PCI configuration registers */
if (sih->buscoretype == PCIE_CORE_ID) {
u8 cap_ptr;
pi->regs.pcieregs = (sbpcieregs_t *) regs;
- cap_ptr =
- pcicore_find_pci_capability(pi->dev, PCI_CAP_PCIECAP_ID,
- NULL, NULL);
+ cap_ptr = pcicore_find_pci_capability(pi->dev, PCI_CAP_ID_EXP,
+ NULL, NULL);
ASSERT(cap_ptr);
pi->pciecap_lcreg_offset = cap_ptr + PCIE_CAP_LINKCTRL_OFFSET;
} else
/* check if the capability pointer field exists */
pci_read_config_byte(dev, PCI_STATUS, &byte_val);
- if (!(byte_val & PCI_CAPPTR_PRESENT))
+ if (!(byte_val & PCI_STATUS_CAP_LIST))
goto end;
pci_read_config_byte(dev, PCI_CAPABILITY_LIST, &cap_ptr);
u8 cap_ptr;
u32 pmecap;
- cap_ptr =
- pcicore_find_pci_capability(pi->dev, PCI_CAP_POWERMGMTCAP_ID, NULL,
- NULL);
+ cap_ptr = pcicore_find_pci_capability(pi->dev, PCI_CAP_ID_PM, NULL,
+ NULL);
if (!cap_ptr)
return false;
pci_read_config_dword(pi->dev, cap_ptr, &pmecap);
- return (pmecap & PME_CAP_PM_STATES) != 0;
+ return (pmecap & (PCI_PM_CAP_PME_MASK << 16)) != 0;
}
/* return true if PM capability exists in the pci config space
u32 pmecap;
if (!pi->pmecap_offset) {
- cap_ptr =
- pcicore_find_pci_capability(pi->dev,
- PCI_CAP_POWERMGMTCAP_ID, NULL,
- NULL);
+ cap_ptr = pcicore_find_pci_capability(pi->dev,
+ PCI_CAP_ID_PM,
+ NULL, NULL);
if (!cap_ptr)
return false;
&pmecap);
/* At least one state can generate PME */
- pi->pmecap = (pmecap & PME_CAP_PM_STATES) != 0;
+ pi->pmecap = (pmecap & (PCI_PM_CAP_PME_MASK << 16)) != 0;
}
return pi->pmecap;
if (!pcicore_pmecap(pi))
return;
- pci_read_config_dword(pi->dev, pi->pmecap_offset + PME_CSR_OFFSET,
+ pci_read_config_dword(pi->dev, pi->pmecap_offset + PCI_PM_CTRL,
&w);
- w |= (PME_CSR_PME_EN);
+ w |= (PCI_PM_CTRL_PME_ENABLE);
pci_write_config_dword(pi->dev,
- pi->pmecap_offset + PME_CSR_OFFSET, w);
+ pi->pmecap_offset + PCI_PM_CTRL, w);
}
/*
if (!pcicore_pmecap(pi))
return false;
- pci_read_config_dword(pi->dev, pi->pmecap_offset + PME_CSR_OFFSET,
+ pci_read_config_dword(pi->dev, pi->pmecap_offset + PCI_PM_CTRL,
&w);
- return (w & PME_CSR_PME_STAT) == PME_CSR_PME_STAT;
+ return (w & PCI_PM_CTRL_PME_STATUS) == PCI_PM_CTRL_PME_STATUS;
}
/* Disable PME generation, clear the PME status bit if set
if (!pcicore_pmecap(pi))
return;
- pci_read_config_dword(pi->dev, pi->pmecap_offset + PME_CSR_OFFSET,
+ pci_read_config_dword(pi->dev, pi->pmecap_offset + PCI_PM_CTRL,
&w);
PCI_ERROR(("pcicore_pci_pmeclr PMECSR : 0x%x\n", w));
/* PMESTAT is cleared by writing 1 to it */
- w &= ~(PME_CSR_PME_EN);
+ w &= ~(PCI_PM_CTRL_PME_ENABLE);
pci_write_config_dword(pi->dev,
- pi->pmecap_offset + PME_CSR_OFFSET, w);
+ pi->pmecap_offset + PCI_PM_CTRL, w);
}
u32 pcie_lcreg(void *pch, u32 mask, u32 val)