+#define QCA955X_EHCI0_BASE 0x1b000000
+#define QCA955X_EHCI1_BASE 0x1b400000
-+#define QCA955X_EHCI_SIZE 0x1000
++#define QCA955X_EHCI_SIZE 0x200
+
/*
* DDR_CTRL block
+#define QCA955X_WMAC_SIZE 0x20000
#define QCA955X_EHCI0_BASE 0x1b000000
#define QCA955X_EHCI1_BASE 0x1b400000
- #define QCA955X_EHCI_SIZE 0x1000
+ #define QCA955X_EHCI_SIZE 0x200
@@ -112,6 +122,8 @@
#define QCA955X_EHCI0_BASE 0x1b000000
#define QCA955X_EHCI1_BASE 0x1b400000
- #define QCA955X_EHCI_SIZE 0x1000
+ #define QCA955X_EHCI_SIZE 0x200
+#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
+#define QCA955X_GMAC_SIZE 0x40