drm/radeon/dce8: properly handle interlaced timing

The register bits changed on DCE8 compared to previous
families.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c
index 4120d355cadd7fc0870709655ed7c6e081c68340..44394199c45da2b2b155b3f2ec5c64f5664774c4 100644 (file)
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -1962,7 +1962,13 @@ atombios_apply_encoder_quirks(struct drm_encoder *encoder,
        /* set scaler clears this on some chips */
        if (ASIC_IS_AVIVO(rdev) &&
            (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
-               if (ASIC_IS_DCE4(rdev)) {
+               if (ASIC_IS_DCE8(rdev)) {
+                       if (mode->flags & DRM_MODE_FLAG_INTERLACE)
+                               WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,
+                                      CIK_INTERLEAVE_EN);
+                       else
+                               WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
+               } else if (ASIC_IS_DCE4(rdev)) {
                        if (mode->flags & DRM_MODE_FLAG_INTERLACE)
                                WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
                                       EVERGREEN_INTERLEAVE_EN);

diff --git a/drivers/gpu/drm/radeon/cik_reg.h b/drivers/gpu/drm/radeon/cik_reg.h
index b96dac02e6f99fe0644c417fa3b0bba6c2591390..58b29b59878553eba2f493e2314d48596061579c 100644 (file)
--- a/drivers/gpu/drm/radeon/cik_reg.h
+++ b/drivers/gpu/drm/radeon/cik_reg.h
@@ -62,4 +62,7 @@
 #define CIK_ALPHA_CONTROL                         0x6af0
 #       define CIK_CURSOR_ALPHA_BLND_ENA          (1 << 1)
 
+#define CIK_LB_DATA_FORMAT                        0x6b00
+#       define CIK_INTERLEAVE_EN                  (1 << 3)
+
 #endif