amdgpu/dce: Use actual number of CRTCs and HPDs in set_irq_funcs
authorMichel Dänzer <michel.daenzer@amd.com>
Tue, 24 Oct 2017 09:03:21 +0000 (11:03 +0200)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 4 Dec 2017 21:41:40 +0000 (16:41 -0500)
Hardcoding the maximum numbers could result in spurious error messages
from the IRQ state callbacks, e.g. on Polaris 11/12:

[drm:dce_v11_0_set_pageflip_irq_state [amdgpu]] *ERROR* invalid pageflip crtc 5
[drm:amdgpu_irq_disable_all [amdgpu]] *ERROR* error disabling interrupt (-22)

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

index 4e519dc4291616912ed0622698cb8720fb89aa40..f3dd6b7bfd4d559e5edbff230e7c7194f22431ef 100644 (file)
@@ -2773,7 +2773,6 @@ static int dce_v10_0_early_init(void *handle)
        adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg;
 
        dce_v10_0_set_display_funcs(adev);
-       dce_v10_0_set_irq_funcs(adev);
 
        adev->mode_info.num_crtc = dce_v10_0_get_num_crtc(adev);
 
@@ -2788,6 +2787,8 @@ static int dce_v10_0_early_init(void *handle)
                return -EINVAL;
        }
 
+       dce_v10_0_set_irq_funcs(adev);
+
        return 0;
 }
 
@@ -3635,13 +3636,16 @@ static const struct amdgpu_irq_src_funcs dce_v10_0_hpd_irq_funcs = {
 
 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev)
 {
-       adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
+       if (adev->mode_info.num_crtc > 0)
+               adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
+       else
+               adev->crtc_irq.num_types = 0;
        adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs;
 
-       adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
+       adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
        adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs;
 
-       adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
+       adev->hpd_irq.num_types = adev->mode_info.num_hpd;
        adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs;
 }
 
index 11edc75edaa99603c40d6986caf3fa8a5b94ff25..be25706e5f07f1581fafe7b4499ead63e23dadcd 100644 (file)
@@ -2876,7 +2876,6 @@ static int dce_v11_0_early_init(void *handle)
        adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg;
 
        dce_v11_0_set_display_funcs(adev);
-       dce_v11_0_set_irq_funcs(adev);
 
        adev->mode_info.num_crtc = dce_v11_0_get_num_crtc(adev);
 
@@ -2903,6 +2902,8 @@ static int dce_v11_0_early_init(void *handle)
                return -EINVAL;
        }
 
+       dce_v11_0_set_irq_funcs(adev);
+
        return 0;
 }
 
@@ -3759,13 +3760,16 @@ static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = {
 
 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)
 {
-       adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
+       if (adev->mode_info.num_crtc > 0)
+               adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
+       else
+               adev->crtc_irq.num_types = 0;
        adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs;
 
-       adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
+       adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
        adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs;
 
-       adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
+       adev->hpd_irq.num_types = adev->mode_info.num_hpd;
        adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs;
 }
 
index a51e35f824a1a3211a0a6ccc5029dec78cdccff5..bd2c4f727df661866733d3b21254769220f7101c 100644 (file)
@@ -2639,7 +2639,6 @@ static int dce_v6_0_early_init(void *handle)
        adev->audio_endpt_wreg = &dce_v6_0_audio_endpt_wreg;
 
        dce_v6_0_set_display_funcs(adev);
-       dce_v6_0_set_irq_funcs(adev);
 
        adev->mode_info.num_crtc = dce_v6_0_get_num_crtc(adev);
 
@@ -2658,6 +2657,8 @@ static int dce_v6_0_early_init(void *handle)
                return -EINVAL;
        }
 
+       dce_v6_0_set_irq_funcs(adev);
+
        return 0;
 }
 
@@ -3441,13 +3442,16 @@ static const struct amdgpu_irq_src_funcs dce_v6_0_hpd_irq_funcs = {
 
 static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev)
 {
-       adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
+       if (adev->mode_info.num_crtc > 0)
+               adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
+       else
+               adev->crtc_irq.num_types = 0;
        adev->crtc_irq.funcs = &dce_v6_0_crtc_irq_funcs;
 
-       adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
+       adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
        adev->pageflip_irq.funcs = &dce_v6_0_pageflip_irq_funcs;
 
-       adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
+       adev->hpd_irq.num_types = adev->mode_info.num_hpd;
        adev->hpd_irq.funcs = &dce_v6_0_hpd_irq_funcs;
 }
 
index 9cf14b8b2db9b594ccd36085e29632ca511f4137..c008dc03068707de0bd2620679f2f74357d474b1 100644 (file)
@@ -2664,7 +2664,6 @@ static int dce_v8_0_early_init(void *handle)
        adev->audio_endpt_wreg = &dce_v8_0_audio_endpt_wreg;
 
        dce_v8_0_set_display_funcs(adev);
-       dce_v8_0_set_irq_funcs(adev);
 
        adev->mode_info.num_crtc = dce_v8_0_get_num_crtc(adev);
 
@@ -2688,6 +2687,8 @@ static int dce_v8_0_early_init(void *handle)
                return -EINVAL;
        }
 
+       dce_v8_0_set_irq_funcs(adev);
+
        return 0;
 }
 
@@ -3525,13 +3526,16 @@ static const struct amdgpu_irq_src_funcs dce_v8_0_hpd_irq_funcs = {
 
 static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev)
 {
-       adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
+       if (adev->mode_info.num_crtc > 0)
+               adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
+       else
+               adev->crtc_irq.num_types = 0;
        adev->crtc_irq.funcs = &dce_v8_0_crtc_irq_funcs;
 
-       adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
+       adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
        adev->pageflip_irq.funcs = &dce_v8_0_pageflip_irq_funcs;
 
-       adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
+       adev->hpd_irq.num_types = adev->mode_info.num_hpd;
        adev->hpd_irq.funcs = &dce_v8_0_hpd_irq_funcs;
 }