for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
set_irq_flags(irq, 0);
- irq_set_handler(irq, NULL);
- irq_set_chip(irq, NULL);
+ irq_set_chip_and_handler(irq, NULL, NULL);
irq_set_chip_data(irq, NULL);
}
irq_set_chained_handler(asic->irq_nr, NULL);
ei->ack_write = 0;
irq_end = ei->irq_start + ei->nirqs;
for (irq = ei->irq_start; irq < irq_end; irq++) {
- irq_set_chip(irq, &egpio_muxed_chip);
+ irq_set_chip_and_handler(irq, &egpio_muxed_chip,
+ handle_simple_irq);
irq_set_chip_data(irq, ei);
- irq_set_handler(irq, handle_simple_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
irq_set_irq_type(ei->chained_irq, IRQ_TYPE_EDGE_RISING);
if (ei->chained_irq) {
irq_end = ei->irq_start + ei->nirqs;
for (irq = ei->irq_start; irq < irq_end; irq++) {
- irq_set_chip(irq, NULL);
- irq_set_handler(irq, NULL);
+ irq_set_chip_and_handler(irq, NULL, NULL);
set_irq_flags(irq, 0);
}
irq_set_chained_handler(ei->chained_irq, NULL);
/* Setup irq handlers */
irq_end = chip->irq_start + chip->nirqs;
for (irq = chip->irq_start; irq < irq_end; irq++) {
- irq_set_chip(irq, &htcpld_muxed_chip);
+ irq_set_chip_and_handler(irq, &htcpld_muxed_chip,
+ handle_simple_irq);
irq_set_chip_data(irq, chip);
- irq_set_handler(irq, handle_simple_irq);
#ifdef CONFIG_ARM
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
#else
irq_base = t7l66xb->irq_base;
for (irq = irq_base; irq < irq_base + T7L66XB_NR_IRQS; irq++) {
- irq_set_chip(irq, &t7l66xb_chip);
+ irq_set_chip_and_handler(irq, &t7l66xb_chip, handle_level_irq);
irq_set_chip_data(irq, t7l66xb);
- irq_set_handler(irq, handle_level_irq);
#ifdef CONFIG_ARM
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
#endif
irq_base = tc6393xb->irq_base;
for (irq = irq_base; irq < irq_base + TC6393XB_NR_IRQS; irq++) {
- irq_set_chip(irq, &tc6393xb_chip);
+ irq_set_chip_and_handler(irq, &tc6393xb_chip, handle_edge_irq);
irq_set_chip_data(irq, tc6393xb);
- irq_set_handler(irq, handle_edge_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}