-LINUX_VERSION-5.15 = .98
-LINUX_KERNEL_HASH-5.15.98 = 7dc62cd3a45f95c9b60316a5886ea9406aee256308869dac1e4ec088fbb37787
+LINUX_VERSION-5.15 = .100
+LINUX_KERNEL_HASH-5.15.100 = f7a4ce870fc1ad879b49887f7f77ee79babdb66937d5acdb1465d53b388c1427
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
-@@ -308,6 +308,12 @@ config SPI_DLN2
+@@ -307,6 +307,12 @@ config SPI_DLN2
This driver can also be built as a module. If so, the module
will be called spi-dln2.
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
-@@ -3098,6 +3098,7 @@ int spi_nor_scan(struct spi_nor *nor, co
+@@ -3107,6 +3107,7 @@ int spi_nor_scan(struct spi_nor *nor, co
struct device *dev = nor->dev;
struct mtd_info *mtd = &nor->mtd;
struct device_node *np = spi_nor_get_flash_node(nor);
int ret;
int i;
-@@ -3152,7 +3153,12 @@ int spi_nor_scan(struct spi_nor *nor, co
+@@ -3161,7 +3162,12 @@ int spi_nor_scan(struct spi_nor *nor, co
if (ret)
return ret;
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
-@@ -2175,6 +2175,14 @@ config RAVE_SP_CORE
+@@ -2176,6 +2176,14 @@ config RAVE_SP_CORE
Select this to get support for the Supervisory Processor
device found on several devices in RAVE line of hardware.
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
-@@ -1748,7 +1748,7 @@ static irqreturn_t vc4_cec_irq_handler(i
+@@ -1749,7 +1749,7 @@ static irqreturn_t vc4_cec_irq_handler(i
return ret;
}
{
struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
/* clock period in microseconds */
-@@ -1761,38 +1761,53 @@ static int vc4_hdmi_cec_adap_enable(stru
+@@ -1762,38 +1762,53 @@ static int vc4_hdmi_cec_adap_enable(stru
val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
-@@ -1753,8 +1753,14 @@ static int vc4_hdmi_cec_enable(struct ce
+@@ -1754,8 +1754,14 @@ static int vc4_hdmi_cec_enable(struct ce
struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
/* clock period in microseconds */
const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
-@@ -1797,6 +1803,8 @@ static int vc4_hdmi_cec_disable(struct c
+@@ -1798,6 +1804,8 @@ static int vc4_hdmi_cec_disable(struct c
HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) |
VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
-@@ -2386,7 +2386,7 @@ static const struct vc4_hdmi_variant bcm
+@@ -2387,7 +2387,7 @@ static const struct vc4_hdmi_variant bcm
.encoder_type = VC4_ENCODER_TYPE_HDMI0,
.debugfs_name = "hdmi0_regs",
.card_name = "vc4-hdmi-0",
}
static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
-@@ -789,10 +856,13 @@ static void vc5_hdmi_set_timings(struct
+@@ -790,10 +857,13 @@ static void vc5_hdmi_set_timings(struct
VC4_SET_FIELD(mode->crtc_vtotal -
- mode->crtc_vsync_end - interlaced,
+ mode->crtc_vsync_end,
VC4_HDMI_VERTB_VBP));
+ unsigned long flags;
unsigned char gcp;
HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021);
HDMI_WRITE(HDMI_HORZA,
(vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
-@@ -856,13 +926,18 @@ static void vc5_hdmi_set_timings(struct
+@@ -857,13 +927,18 @@ static void vc5_hdmi_set_timings(struct
HDMI_WRITE(HDMI_MISC_CONTROL, reg);
HDMI_WRITE(HDMI_CLOCK_STOP, 0);
drift = HDMI_READ(HDMI_FIFO_CTL);
drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
-@@ -870,12 +945,20 @@ static void vc4_hdmi_recenter_fifo(struc
+@@ -871,12 +946,20 @@ static void vc4_hdmi_recenter_fifo(struc
drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
HDMI_WRITE(HDMI_FIFO_CTL,
drift | VC4_HDMI_FIFO_CTL_RECENTER);
ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
WARN_ONCE(ret, "Timeout waiting for "
-@@ -909,6 +992,7 @@ static void vc4_hdmi_encoder_pre_crtc_co
+@@ -910,6 +993,7 @@ static void vc4_hdmi_encoder_pre_crtc_co
struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
unsigned long pixel_rate = vc4_conn_state->pixel_rate;
unsigned long bvb_rate, hsm_rate;
int ret;
/*
-@@ -977,11 +1061,15 @@ static void vc4_hdmi_encoder_pre_crtc_co
+@@ -978,11 +1062,15 @@ static void vc4_hdmi_encoder_pre_crtc_co
if (vc4_hdmi->variant->phy_init)
vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
if (vc4_hdmi->variant->set_timings)
vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
-@@ -1001,6 +1089,7 @@ static void vc4_hdmi_encoder_pre_crtc_en
+@@ -1002,6 +1090,7 @@ static void vc4_hdmi_encoder_pre_crtc_en
struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
if (vc4_encoder->hdmi_monitor &&
drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED) {
-@@ -1015,7 +1104,9 @@ static void vc4_hdmi_encoder_pre_crtc_en
+@@ -1016,7 +1105,9 @@ static void vc4_hdmi_encoder_pre_crtc_en
vc4_encoder->limited_rgb_range = false;
}
}
static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
-@@ -1026,8 +1117,11 @@ static void vc4_hdmi_encoder_post_crtc_e
+@@ -1027,8 +1118,11 @@ static void vc4_hdmi_encoder_post_crtc_e
struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
HDMI_WRITE(HDMI_VID_CTL,
VC4_HD_VID_CTL_ENABLE |
VC4_HD_VID_CTL_CLRRGB |
-@@ -1044,6 +1138,8 @@ static void vc4_hdmi_encoder_post_crtc_e
+@@ -1045,6 +1139,8 @@ static void vc4_hdmi_encoder_post_crtc_e
HDMI_READ(HDMI_SCHEDULER_CONTROL) |
VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
WARN_ONCE(ret, "Timeout waiting for "
-@@ -1056,6 +1152,8 @@ static void vc4_hdmi_encoder_post_crtc_e
+@@ -1057,6 +1153,8 @@ static void vc4_hdmi_encoder_post_crtc_e
HDMI_READ(HDMI_SCHEDULER_CONTROL) &
~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
WARN_ONCE(ret, "Timeout waiting for "
-@@ -1063,6 +1161,8 @@ static void vc4_hdmi_encoder_post_crtc_e
+@@ -1064,6 +1162,8 @@ static void vc4_hdmi_encoder_post_crtc_e
}
if (vc4_encoder->hdmi_monitor) {
WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
-@@ -1072,6 +1172,8 @@ static void vc4_hdmi_encoder_post_crtc_e
+@@ -1073,6 +1173,8 @@ static void vc4_hdmi_encoder_post_crtc_e
HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
VC4_HDMI_RAM_PACKET_ENABLE);
vc4_hdmi_set_infoframes(encoder);
}
-@@ -1195,6 +1297,7 @@ static void vc4_hdmi_audio_set_mai_clock
+@@ -1196,6 +1298,7 @@ static void vc4_hdmi_audio_set_mai_clock
unsigned int samplerate)
{
u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
unsigned long n, m;
rational_best_approximation(hsm_clock, samplerate,
-@@ -1204,9 +1307,11 @@ static void vc4_hdmi_audio_set_mai_clock
+@@ -1205,9 +1308,11 @@ static void vc4_hdmi_audio_set_mai_clock
VC4_HD_MAI_SMP_M_SHIFT) + 1,
&n, &m);
}
static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
-@@ -1217,6 +1322,8 @@ static void vc4_hdmi_set_n_cts(struct vc
+@@ -1218,6 +1323,8 @@ static void vc4_hdmi_set_n_cts(struct vc
u32 n, cts;
u64 tmp;
n = 128 * samplerate / 1000;
tmp = (u64)(mode->clock * 1000) * n;
do_div(tmp, 128 * samplerate);
-@@ -1246,6 +1353,7 @@ static int vc4_hdmi_audio_startup(struct
+@@ -1247,6 +1354,7 @@ static int vc4_hdmi_audio_startup(struct
{
struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
/*
* If the HDMI encoder hasn't probed, or the encoder is
-@@ -1257,12 +1365,14 @@ static int vc4_hdmi_audio_startup(struct
+@@ -1258,12 +1366,14 @@ static int vc4_hdmi_audio_startup(struct
vc4_hdmi->audio.streaming = true;
if (vc4_hdmi->variant->phy_rng_enable)
vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
-@@ -1274,6 +1384,7 @@ static void vc4_hdmi_audio_reset(struct
+@@ -1275,6 +1385,7 @@ static void vc4_hdmi_audio_reset(struct
{
struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
struct device *dev = &vc4_hdmi->pdev->dev;
int ret;
vc4_hdmi->audio.streaming = false;
-@@ -1281,20 +1392,29 @@ static void vc4_hdmi_audio_reset(struct
+@@ -1282,20 +1393,29 @@ static void vc4_hdmi_audio_reset(struct
if (ret)
dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
if (vc4_hdmi->variant->phy_rng_disable)
vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
-@@ -1349,6 +1469,7 @@ static int vc4_hdmi_audio_prepare(struct
+@@ -1350,6 +1470,7 @@ static int vc4_hdmi_audio_prepare(struct
struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
unsigned int sample_rate = params->sample_rate;
unsigned int channels = params->channels;
u32 audio_packet_config, channel_mask;
u32 channel_map;
u32 mai_audio_format;
-@@ -1357,14 +1478,15 @@ static int vc4_hdmi_audio_prepare(struct
+@@ -1358,14 +1479,15 @@ static int vc4_hdmi_audio_prepare(struct
dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
sample_rate, params->sample_width, channels);
mai_sample_rate = sample_rate_to_mai_fmt(sample_rate);
if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
params->channels == 8)
-@@ -1402,8 +1524,11 @@ static int vc4_hdmi_audio_prepare(struct
+@@ -1403,8 +1525,11 @@ static int vc4_hdmi_audio_prepare(struct
channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
memcpy(&vc4_hdmi->audio.infoframe, ¶ms->cea, sizeof(params->cea));
vc4_hdmi_set_audio_infoframe(encoder);
-@@ -1677,6 +1802,8 @@ static void vc4_cec_read_msg(struct vc4_
+@@ -1678,6 +1803,8 @@ static void vc4_cec_read_msg(struct vc4_
struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
unsigned int i;
msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
-@@ -1695,11 +1822,12 @@ static void vc4_cec_read_msg(struct vc4_
+@@ -1696,11 +1823,12 @@ static void vc4_cec_read_msg(struct vc4_
}
}
cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
-@@ -1708,11 +1836,24 @@ static irqreturn_t vc4_cec_irq_handler_t
+@@ -1709,11 +1837,24 @@ static irqreturn_t vc4_cec_irq_handler_t
return IRQ_WAKE_THREAD;
}
vc4_hdmi->cec_rx_msg.len = 0;
cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
vc4_cec_read_msg(vc4_hdmi, cntrl1);
-@@ -1725,6 +1866,18 @@ static irqreturn_t vc4_cec_irq_handler_r
+@@ -1726,6 +1867,18 @@ static irqreturn_t vc4_cec_irq_handler_r
return IRQ_WAKE_THREAD;
}
static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
{
struct vc4_hdmi *vc4_hdmi = priv;
-@@ -1735,14 +1888,17 @@ static irqreturn_t vc4_cec_irq_handler(i
+@@ -1736,14 +1889,17 @@ static irqreturn_t vc4_cec_irq_handler(i
if (!(stat & VC4_HDMI_CPU_CEC))
return IRQ_NONE;
return ret;
}
-@@ -1751,6 +1907,7 @@ static int vc4_hdmi_cec_enable(struct ce
+@@ -1752,6 +1908,7 @@ static int vc4_hdmi_cec_enable(struct ce
struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
/* clock period in microseconds */
const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
u32 val;
int ret;
-@@ -1758,6 +1915,8 @@ static int vc4_hdmi_cec_enable(struct ce
+@@ -1759,6 +1916,8 @@ static int vc4_hdmi_cec_enable(struct ce
if (ret)
return ret;
val = HDMI_READ(HDMI_CEC_CNTRL_5);
val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
-@@ -1788,12 +1947,17 @@ static int vc4_hdmi_cec_enable(struct ce
+@@ -1789,12 +1948,17 @@ static int vc4_hdmi_cec_enable(struct ce
if (!vc4_hdmi->variant->external_irq_controller)
HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
if (!vc4_hdmi->variant->external_irq_controller)
HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
-@@ -1801,6 +1965,8 @@ static int vc4_hdmi_cec_disable(struct c
+@@ -1802,6 +1966,8 @@ static int vc4_hdmi_cec_disable(struct c
HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) |
VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
pm_runtime_put(&vc4_hdmi->pdev->dev);
return 0;
-@@ -1817,10 +1983,14 @@ static int vc4_hdmi_cec_adap_enable(stru
+@@ -1818,10 +1984,14 @@ static int vc4_hdmi_cec_adap_enable(stru
static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
{
struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
return 0;
}
-@@ -1829,6 +1999,7 @@ static int vc4_hdmi_cec_adap_transmit(st
+@@ -1830,6 +2000,7 @@ static int vc4_hdmi_cec_adap_transmit(st
{
struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
struct drm_device *dev = vc4_hdmi->connector.dev;
u32 val;
unsigned int i;
-@@ -1837,6 +2008,8 @@ static int vc4_hdmi_cec_adap_transmit(st
+@@ -1838,6 +2009,8 @@ static int vc4_hdmi_cec_adap_transmit(st
return -ENOMEM;
}
for (i = 0; i < msg->len; i += 4)
HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
(msg->msg[i]) |
-@@ -1852,6 +2025,9 @@ static int vc4_hdmi_cec_adap_transmit(st
+@@ -1853,6 +2026,9 @@ static int vc4_hdmi_cec_adap_transmit(st
val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
return 0;
}
-@@ -1866,6 +2042,7 @@ static int vc4_hdmi_cec_init(struct vc4_
+@@ -1867,6 +2043,7 @@ static int vc4_hdmi_cec_init(struct vc4_
struct cec_connector_info conn_info;
struct platform_device *pdev = vc4_hdmi->pdev;
struct device *dev = &pdev->dev;
u32 value;
int ret;
-@@ -1886,10 +2063,12 @@ static int vc4_hdmi_cec_init(struct vc4_
+@@ -1887,10 +2064,12 @@ static int vc4_hdmi_cec_init(struct vc4_
cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
vc4_hdmi_cec_update_clk_div(vc4_hdmi);
-@@ -1908,7 +2087,9 @@ static int vc4_hdmi_cec_init(struct vc4_
+@@ -1909,7 +2088,9 @@ static int vc4_hdmi_cec_init(struct vc4_
if (ret)
goto err_remove_cec_rx_handler;
} else {
ret = request_threaded_irq(platform_get_irq(pdev, 0),
vc4_cec_irq_handler,
-@@ -2178,6 +2359,7 @@ static int vc4_hdmi_bind(struct device *
+@@ -2179,6 +2360,7 @@ static int vc4_hdmi_bind(struct device *
vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL);
if (!vc4_hdmi)
return -ENOMEM;
}
static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
-@@ -995,6 +1024,8 @@ static void vc4_hdmi_encoder_pre_crtc_co
+@@ -996,6 +1025,8 @@ static void vc4_hdmi_encoder_pre_crtc_co
unsigned long flags;
int ret;
/*
* As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
* be faster than pixel clock, infinitesimally faster, tested in
-@@ -1015,13 +1046,13 @@ static void vc4_hdmi_encoder_pre_crtc_co
+@@ -1016,13 +1047,13 @@ static void vc4_hdmi_encoder_pre_crtc_co
ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
if (ret) {
DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
}
ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate);
-@@ -1073,13 +1104,16 @@ static void vc4_hdmi_encoder_pre_crtc_co
+@@ -1074,13 +1105,16 @@ static void vc4_hdmi_encoder_pre_crtc_co
if (vc4_hdmi->variant->set_timings)
vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
return;
}
-@@ -1091,6 +1125,8 @@ static void vc4_hdmi_encoder_pre_crtc_en
+@@ -1092,6 +1126,8 @@ static void vc4_hdmi_encoder_pre_crtc_en
struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
unsigned long flags;
if (vc4_encoder->hdmi_monitor &&
drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED) {
if (vc4_hdmi->variant->csc_setup)
-@@ -1107,6 +1143,8 @@ static void vc4_hdmi_encoder_pre_crtc_en
+@@ -1108,6 +1144,8 @@ static void vc4_hdmi_encoder_pre_crtc_en
spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
}
static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
-@@ -1120,6 +1158,8 @@ static void vc4_hdmi_encoder_post_crtc_e
+@@ -1121,6 +1159,8 @@ static void vc4_hdmi_encoder_post_crtc_e
unsigned long flags;
int ret;
spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
HDMI_WRITE(HDMI_VID_CTL,
-@@ -1179,6 +1219,8 @@ static void vc4_hdmi_encoder_post_crtc_e
+@@ -1180,6 +1220,8 @@ static void vc4_hdmi_encoder_post_crtc_e
vc4_hdmi_recenter_fifo(vc4_hdmi);
vc4_hdmi_enable_scrambling(encoder);
}
static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
-@@ -1322,6 +1364,7 @@ static void vc4_hdmi_set_n_cts(struct vc
+@@ -1323,6 +1365,7 @@ static void vc4_hdmi_set_n_cts(struct vc
u32 n, cts;
u64 tmp;
lockdep_assert_held(&vc4_hdmi->hw_lock);
n = 128 * samplerate / 1000;
-@@ -1355,13 +1398,17 @@ static int vc4_hdmi_audio_startup(struct
+@@ -1356,13 +1399,17 @@ static int vc4_hdmi_audio_startup(struct
struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
unsigned long flags;
vc4_hdmi->audio.streaming = true;
-@@ -1377,6 +1424,8 @@ static int vc4_hdmi_audio_startup(struct
+@@ -1378,6 +1425,8 @@ static int vc4_hdmi_audio_startup(struct
if (vc4_hdmi->variant->phy_rng_enable)
vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
return 0;
}
-@@ -1387,6 +1436,8 @@ static void vc4_hdmi_audio_reset(struct
+@@ -1388,6 +1437,8 @@ static void vc4_hdmi_audio_reset(struct
unsigned long flags;
int ret;
vc4_hdmi->audio.streaming = false;
ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);
if (ret)
-@@ -1406,6 +1457,8 @@ static void vc4_hdmi_audio_shutdown(stru
+@@ -1407,6 +1458,8 @@ static void vc4_hdmi_audio_shutdown(stru
struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
unsigned long flags;
spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
HDMI_WRITE(HDMI_MAI_CTL,
-@@ -1420,6 +1473,8 @@ static void vc4_hdmi_audio_shutdown(stru
+@@ -1421,6 +1474,8 @@ static void vc4_hdmi_audio_shutdown(stru
vc4_hdmi->audio.streaming = false;
vc4_hdmi_audio_reset(vc4_hdmi);
}
static int sample_rate_to_mai_fmt(int samplerate)
-@@ -1478,6 +1533,8 @@ static int vc4_hdmi_audio_prepare(struct
+@@ -1479,6 +1534,8 @@ static int vc4_hdmi_audio_prepare(struct
dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
sample_rate, params->sample_width, channels);
vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);
spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
-@@ -1532,6 +1589,8 @@ static int vc4_hdmi_audio_prepare(struct
+@@ -1533,6 +1590,8 @@ static int vc4_hdmi_audio_prepare(struct
memcpy(&vc4_hdmi->audio.infoframe, ¶ms->cea, sizeof(params->cea));
vc4_hdmi_set_audio_infoframe(encoder);
return 0;
}
-@@ -1574,7 +1633,9 @@ static int vc4_hdmi_audio_get_eld(struct
+@@ -1575,7 +1634,9 @@ static int vc4_hdmi_audio_get_eld(struct
struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
struct drm_connector *connector = &vc4_hdmi->connector;
return 0;
}
-@@ -1911,6 +1972,17 @@ static int vc4_hdmi_cec_enable(struct ce
+@@ -1912,6 +1973,17 @@ static int vc4_hdmi_cec_enable(struct ce
u32 val;
int ret;
ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
if (ret)
return ret;
-@@ -1957,6 +2029,17 @@ static int vc4_hdmi_cec_disable(struct c
+@@ -1958,6 +2030,17 @@ static int vc4_hdmi_cec_disable(struct c
struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
unsigned long flags;
spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
if (!vc4_hdmi->variant->external_irq_controller)
-@@ -1985,6 +2068,17 @@ static int vc4_hdmi_cec_adap_log_addr(st
+@@ -1986,6 +2069,17 @@ static int vc4_hdmi_cec_adap_log_addr(st
struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
unsigned long flags;
spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
HDMI_WRITE(HDMI_CEC_CNTRL_1,
(HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
-@@ -2003,6 +2097,17 @@ static int vc4_hdmi_cec_adap_transmit(st
+@@ -2004,6 +2098,17 @@ static int vc4_hdmi_cec_adap_transmit(st
u32 val;
unsigned int i;
if (msg->len > 16) {
drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
return -ENOMEM;
-@@ -2359,6 +2464,7 @@ static int vc4_hdmi_bind(struct device *
+@@ -2360,6 +2465,7 @@ static int vc4_hdmi_bind(struct device *
vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL);
if (!vc4_hdmi)
return -ENOMEM;
return;
if (delayed_work_pending(&vc4_hdmi->scrambling_work))
-@@ -1017,8 +1019,8 @@ static void vc4_hdmi_encoder_pre_crtc_co
+@@ -1018,8 +1020,8 @@ static void vc4_hdmi_encoder_pre_crtc_co
vc4_hdmi_encoder_get_connector_state(encoder, state);
struct vc4_hdmi_connector_state *vc4_conn_state =
conn_state_to_vc4_hdmi_conn_state(conn_state);
unsigned long pixel_rate = vc4_conn_state->pixel_rate;
unsigned long bvb_rate, hsm_rate;
unsigned long flags;
-@@ -1120,9 +1122,9 @@ out:
+@@ -1121,9 +1123,9 @@ out:
static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
struct drm_atomic_state *state)
{
unsigned long flags;
mutex_lock(&vc4_hdmi->mutex);
-@@ -1150,8 +1152,8 @@ static void vc4_hdmi_encoder_pre_crtc_en
+@@ -1151,8 +1153,8 @@ static void vc4_hdmi_encoder_pre_crtc_en
static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
struct drm_atomic_state *state)
{
struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
-@@ -1227,6 +1229,19 @@ static void vc4_hdmi_encoder_enable(stru
+@@ -1228,6 +1230,19 @@ static void vc4_hdmi_encoder_enable(stru
{
}
#define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL
#define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL
-@@ -1305,6 +1320,7 @@ vc4_hdmi_encoder_mode_valid(struct drm_e
+@@ -1306,6 +1321,7 @@ vc4_hdmi_encoder_mode_valid(struct drm_e
static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
.atomic_check = vc4_hdmi_encoder_atomic_check,
.mode_valid = vc4_hdmi_encoder_mode_valid,
.disable = vc4_hdmi_encoder_disable,
.enable = vc4_hdmi_encoder_enable,
-@@ -1358,9 +1374,7 @@ static void vc4_hdmi_audio_set_mai_clock
+@@ -1359,9 +1375,7 @@ static void vc4_hdmi_audio_set_mai_clock
static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
{
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
-@@ -1406,20 +1406,36 @@ static inline struct vc4_hdmi *dai_to_hd
+@@ -1407,20 +1407,36 @@ static inline struct vc4_hdmi *dai_to_hd
return snd_soc_card_get_drvdata(card);
}
mutex_unlock(&vc4_hdmi->mutex);
return -ENODEV;
}
-@@ -1549,6 +1565,11 @@ static int vc4_hdmi_audio_prepare(struct
+@@ -1550,6 +1566,11 @@ static int vc4_hdmi_audio_prepare(struct
mutex_lock(&vc4_hdmi->mutex);
}
static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
-@@ -1227,6 +1232,11 @@ static void vc4_hdmi_encoder_post_crtc_e
+@@ -1228,6 +1233,11 @@ static void vc4_hdmi_encoder_post_crtc_e
static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
{
}
static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder,
-@@ -1408,14 +1418,12 @@ static inline struct vc4_hdmi *dai_to_hd
+@@ -1409,14 +1419,12 @@ static inline struct vc4_hdmi *dai_to_hd
static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi)
{
if (delayed_work_pending(&vc4_hdmi->scrambling_work))
cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
-@@ -2522,6 +2516,14 @@ static int vc4_hdmi_bind(struct device *
+@@ -2523,6 +2517,14 @@ static int vc4_hdmi_bind(struct device *
vc4_hdmi->pdev = pdev;
vc4_hdmi->variant = variant;
*/
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
-@@ -525,11 +525,6 @@ static void vc4_plane_calc_load(struct d
+@@ -527,11 +527,6 @@ static void vc4_plane_calc_load(struct d
struct vc4_plane_state *vc4_state;
struct drm_crtc_state *crtc_state;
unsigned int vscale_factor;
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
-@@ -1801,10 +1801,11 @@ static void vc4_hdmi_audio_exit(struct v
+@@ -1802,10 +1802,11 @@ static void vc4_hdmi_audio_exit(struct v
static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
{
struct vc4_hdmi *vc4_hdmi = priv;
--- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c
+++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
-@@ -378,7 +378,7 @@ static const struct gpio_chip bcm2835_gp
+@@ -376,7 +376,7 @@ static const struct gpio_chip bcm2835_gp
.get = bcm2835_gpio_get,
.set = bcm2835_gpio_set,
.set_config = gpiochip_generic_config,
.ngpio = BCM2835_NUM_GPIOS,
.can_sleep = false,
.of_gpio_ranges_fallback = bcm2835_of_gpio_ranges_fallback,
-@@ -395,7 +395,7 @@ static const struct gpio_chip bcm2711_gp
+@@ -393,7 +393,7 @@ static const struct gpio_chip bcm2711_gp
.get = bcm2835_gpio_get,
.set = bcm2835_gpio_set,
.set_config = gpiochip_generic_config,
--- a/drivers/net/ethernet/broadcom/genet/bcmgenet.c
+++ b/drivers/net/ethernet/broadcom/genet/bcmgenet.c
-@@ -2608,7 +2608,7 @@ static void bcmgenet_init_tx_ring(struct
+@@ -2616,7 +2616,7 @@ static void bcmgenet_init_tx_ring(struct
bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
/* Disable rate control for now */
bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
TDMA_FLOW_PERIOD);
-@@ -4075,9 +4075,12 @@ static int bcmgenet_probe(struct platfor
+@@ -4083,9 +4083,12 @@ static int bcmgenet_probe(struct platfor
netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
/* Set default coalescing parameters */
--- a/drivers/net/ethernet/broadcom/genet/bcmmii.c
+++ b/drivers/net/ethernet/broadcom/genet/bcmmii.c
-@@ -293,6 +293,8 @@ int bcmgenet_mii_probe(struct net_device
+@@ -286,6 +286,8 @@ int bcmgenet_mii_probe(struct net_device
/* Communicate the integrated PHY revision */
if (priv->internal_phy)
phy_flags = priv->gphy_rev;
static inline void bcmgenet_writel(u32 value, void __iomem *offset)
{
-@@ -2439,6 +2442,11 @@ static void reset_umac(struct bcmgenet_p
+@@ -2447,6 +2450,11 @@ static void reset_umac(struct bcmgenet_p
bcmgenet_rbuf_ctrl_set(priv, 0);
udelay(10);
--- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c
+++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
-@@ -1339,7 +1339,7 @@ static int bcm2835_pinctrl_probe(struct
+@@ -1337,7 +1337,7 @@ static int bcm2835_pinctrl_probe(struct
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_level_irq;
--- a/drivers/net/ethernet/broadcom/genet/bcmgenet.c
+++ b/drivers/net/ethernet/broadcom/genet/bcmgenet.c
-@@ -3257,7 +3257,7 @@ static void bcmgenet_get_hw_addr(struct
+@@ -3265,7 +3265,7 @@ static void bcmgenet_get_hw_addr(struct
}
/* Returns a reusable dma control register value */
{
unsigned int i;
u32 reg;
-@@ -3282,6 +3282,14 @@ static u32 bcmgenet_dma_disable(struct b
+@@ -3290,6 +3290,14 @@ static u32 bcmgenet_dma_disable(struct b
udelay(10);
bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
return dma_ctrl;
}
-@@ -3345,8 +3353,8 @@ static int bcmgenet_open(struct net_devi
+@@ -3353,8 +3361,8 @@ static int bcmgenet_open(struct net_devi
bcmgenet_set_hw_addr(priv, dev->dev_addr);
/* Reinitialize TDMA and RDMA and SW housekeeping */
ret = bcmgenet_init_dma(priv);
-@@ -4204,7 +4212,7 @@ static int bcmgenet_resume(struct device
+@@ -4212,7 +4220,7 @@ static int bcmgenet_resume(struct device
bcmgenet_hfb_create_rxnfc_filter(priv, rule);
/* Disable RX/TX DMA and flush TX queues */
}, {
--- a/drivers/gpu/drm/vc4/vc4_dpi.c
+++ b/drivers/gpu/drm/vc4/vc4_dpi.c
-@@ -165,10 +165,20 @@ static void vc4_dpi_encoder_enable(struc
- dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_2,
- DPI_FORMAT);
- break;
-+ case MEDIA_BUS_FMT_BGR666_1X24_CPADHI:
-+ dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_2,
-+ DPI_FORMAT);
-+ dpi_c |= VC4_SET_FIELD(DPI_ORDER_BGR, DPI_ORDER);
-+ break;
- case MEDIA_BUS_FMT_RGB666_1X18:
- dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_1,
- DPI_FORMAT);
- break;
-+ case MEDIA_BUS_FMT_BGR666_1X18:
-+ dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_1,
-+ DPI_FORMAT);
-+ dpi_c |= VC4_SET_FIELD(DPI_ORDER_BGR, DPI_ORDER);
-+ break;
- case MEDIA_BUS_FMT_RGB565_1X16:
- dpi_c |= VC4_SET_FIELD(DPI_FORMAT_16BIT_565_RGB_3,
- DPI_FORMAT);
+@@ -167,10 +167,20 @@ static void vc4_dpi_encoder_enable(struc
+ dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_2,
+ DPI_FORMAT);
+ break;
++ case MEDIA_BUS_FMT_BGR666_1X24_CPADHI:
++ dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_2,
++ DPI_FORMAT);
++ dpi_c |= VC4_SET_FIELD(DPI_ORDER_BGR, DPI_ORDER);
++ break;
+ case MEDIA_BUS_FMT_RGB666_1X18:
+ dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_1,
+ DPI_FORMAT);
+ break;
++ case MEDIA_BUS_FMT_BGR666_1X18:
++ dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_1,
++ DPI_FORMAT);
++ dpi_c |= VC4_SET_FIELD(DPI_ORDER_BGR, DPI_ORDER);
++ break;
+ case MEDIA_BUS_FMT_RGB565_1X16:
+ dpi_c |= VC4_SET_FIELD(DPI_FORMAT_16BIT_565_RGB_1,
+ DPI_FORMAT);
--- a/include/uapi/linux/media-bus-format.h
+++ b/include/uapi/linux/media-bus-format.h
@@ -34,7 +34,7 @@
} hvs_formats[] = {
{
.drm = DRM_FORMAT_XRGB8888,
-@@ -128,6 +129,12 @@ static const struct hvs_format {
+@@ -130,6 +131,12 @@ static const struct hvs_format {
.hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE,
.pixel_order = HVS_PIXEL_ORDER_XYCRCB,
},
};
static const struct hvs_format *vc4_get_hvs_format(u32 drm_format)
-@@ -758,47 +765,90 @@ static int vc4_plane_mode_set(struct drm
+@@ -760,47 +767,90 @@ static int vc4_plane_mode_set(struct drm
case DRM_FORMAT_MOD_BROADCOM_SAND128:
case DRM_FORMAT_MOD_BROADCOM_SAND256: {
uint32_t param = fourcc_mod_broadcom_param(fb->modifier);
}
pitch0 = VC4_SET_FIELD(param, SCALER_TILE_HEIGHT);
-@@ -951,7 +1001,8 @@ static int vc4_plane_mode_set(struct drm
+@@ -953,7 +1003,8 @@ static int vc4_plane_mode_set(struct drm
/* Pitch word 1/2 */
for (i = 1; i < num_planes; i++) {
vc4_dlist_write(vc4_state,
VC4_SET_FIELD(fb->pitches[i],
SCALER_SRC_PITCH));
-@@ -1311,6 +1362,13 @@ static bool vc4_format_mod_supported(str
+@@ -1313,6 +1364,13 @@ static bool vc4_format_mod_supported(str
default:
return false;
}
case DRM_FORMAT_RGBX1010102:
case DRM_FORMAT_BGRX1010102:
case DRM_FORMAT_RGBA1010102:
-@@ -1343,8 +1401,11 @@ struct drm_plane *vc4_plane_init(struct
+@@ -1345,8 +1403,11 @@ struct drm_plane *vc4_plane_init(struct
struct drm_plane *plane = NULL;
struct vc4_plane *vc4_plane;
u32 formats[ARRAY_SIZE(hvs_formats)];
static const uint64_t modifiers[] = {
DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED,
DRM_FORMAT_MOD_BROADCOM_SAND128,
-@@ -1359,13 +1420,17 @@ struct drm_plane *vc4_plane_init(struct
+@@ -1361,13 +1422,17 @@ struct drm_plane *vc4_plane_init(struct
if (!vc4_plane)
return ERR_PTR(-ENOMEM);
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
-@@ -619,6 +619,51 @@ static int vc4_plane_allocate_lbm(struct
+@@ -621,6 +621,51 @@ static int vc4_plane_allocate_lbm(struct
return 0;
}
/* Writes out a full display list for an active plane to the plane's
* private dlist state.
*/
-@@ -1013,9 +1058,20 @@ static int vc4_plane_mode_set(struct drm
+@@ -1015,9 +1060,20 @@ static int vc4_plane_mode_set(struct drm
/* Colorspace conversion words */
if (vc4_state->is_yuv) {
}
vc4_state->lbm_offset = 0;
-@@ -1444,6 +1500,15 @@ struct drm_plane *vc4_plane_init(struct
+@@ -1446,6 +1502,15 @@ struct drm_plane *vc4_plane_init(struct
DRM_MODE_REFLECT_X |
DRM_MODE_REFLECT_Y);
--- a/drivers/gpu/drm/vc4/vc4_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_regs.h
-@@ -983,7 +983,10 @@ enum hvs_pixel_format {
+@@ -989,7 +989,10 @@ enum hvs_pixel_format {
#define SCALER_CSC0_COEF_CR_OFS_SHIFT 0
#define SCALER_CSC0_ITR_R_601_5 0x00f00000
#define SCALER_CSC0_ITR_R_709_3 0x00f00000
/* S2.8 contribution of Cb to Green */
#define SCALER_CSC1_COEF_CB_GRN_MASK VC4_MASK(31, 22)
-@@ -998,8 +1001,11 @@ enum hvs_pixel_format {
+@@ -1004,8 +1007,11 @@ enum hvs_pixel_format {
#define SCALER_CSC1_COEF_CR_BLU_MASK VC4_MASK(1, 0)
#define SCALER_CSC1_COEF_CR_BLU_SHIFT 0
#define SCALER_CSC1_ITR_R_601_5 0xe73304a8
/* S2.8 contribution of Cb to Red */
#define SCALER_CSC2_COEF_CB_RED_MASK VC4_MASK(29, 20)
-@@ -1010,9 +1016,12 @@ enum hvs_pixel_format {
+@@ -1016,9 +1022,12 @@ enum hvs_pixel_format {
/* S2.8 contribution of Cb to Blue */
#define SCALER_CSC2_COEF_CB_BLU_MASK VC4_MASK(19, 10)
#define SCALER_CSC2_COEF_CB_BLU_SHIFT 10
/* The filter kernel is composed of dwords each containing 3 9-bit
* signed integers packed next to each other.
*/
-@@ -728,6 +767,8 @@ static int vc4_hvs_bind(struct device *d
+@@ -739,6 +778,8 @@ static int vc4_hvs_bind(struct device *d
vc4_debugfs_add_regset32(drm, "hvs_regs", &hvs->regset);
vc4_debugfs_add_file(drm, "hvs_underrun", vc4_hvs_debugfs_underrun,
NULL);
return 0;
}
-@@ -2369,6 +2375,7 @@ static int vc5_hdmi_init_resources(struc
+@@ -2370,6 +2376,7 @@ static int vc5_hdmi_init_resources(struc
struct platform_device *pdev = vc4_hdmi->pdev;
struct device *dev = &pdev->dev;
struct resource *res;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
if (!res)
-@@ -2465,6 +2472,38 @@ static int vc5_hdmi_init_resources(struc
+@@ -2466,6 +2473,38 @@ static int vc5_hdmi_init_resources(struc
return PTR_ERR(vc4_hdmi->reset);
}
--- a/drivers/gpu/drm/vc4/vc4_dpi.c
+++ b/drivers/gpu/drm/vc4/vc4_dpi.c
-@@ -188,8 +188,8 @@ static void vc4_dpi_encoder_enable(struc
- break;
- }
+@@ -198,8 +198,8 @@ static void vc4_dpi_encoder_enable(struc
+ if (connector->display_info.bus_flags & DRM_BUS_FLAG_DE_LOW)
+ dpi_c |= DPI_OUTPUT_ENABLE_INVERT;
} else {
- /* Default to 24bit if no connector found. */
- dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, DPI_FORMAT);
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
-@@ -1011,30 +1011,15 @@ static void vc4_hdmi_recenter_fifo(struc
+@@ -1012,30 +1012,15 @@ static void vc4_hdmi_recenter_fifo(struc
"VC4_HDMI_FIFO_CTL_RECENTER_DONE");
}
--- a/drivers/media/i2c/imx219.c
+++ b/drivers/media/i2c/imx219.c
-@@ -674,7 +674,7 @@ static void imx219_set_default_format(st
+@@ -584,7 +584,7 @@ static void imx219_set_default_format(st
fmt = &imx219->fmt;
fmt->code = MEDIA_BUS_FMT_SRGGB10_1X10;
fmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt->colorspace);
fmt->quantization = V4L2_MAP_QUANTIZATION_DEFAULT(true,
fmt->colorspace,
-@@ -844,7 +844,7 @@ static int imx219_enum_frame_size(struct
+@@ -754,7 +754,7 @@ static int imx219_enum_frame_size(struct
static void imx219_reset_colorspace(struct v4l2_mbus_framefmt *fmt)
{
/* Unsetting DISPBKGND_GAMMA skips the gamma lut step
--- a/drivers/gpu/drm/vc4/vc4_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_regs.h
-@@ -499,6 +499,28 @@
+@@ -505,6 +505,28 @@
#define SCALER_DLIST_START 0x00002000
#define SCALER_DLIST_SIZE 0x00004000
/* The filter kernel is composed of dwords each containing 3 9-bit
* signed integers packed next to each other.
*/
-@@ -848,6 +926,9 @@ static int vc4_hvs_bind(struct device *d
+@@ -859,6 +937,9 @@ static int vc4_hvs_bind(struct device *d
NULL);
vc4_debugfs_add_file(drm, "hvs_dlists", vc4_hvs_debugfs_dlist,
NULL);
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
-@@ -2557,7 +2557,8 @@ static int vc4_hdmi_bind(struct device *
+@@ -2558,7 +2558,8 @@ static int vc4_hdmi_bind(struct device *
* vc4_hdmi_disable_scrambling() will thus run at boot, make
* sure it's disabled, and avoid any inconsistency.
*/
int ret;
/* Look up the connector attached to DPI so we can get the
-@@ -192,15 +192,22 @@ static void vc4_dpi_encoder_enable(struc
+@@ -202,15 +202,22 @@ static void vc4_dpi_encoder_enable(struc
dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_1, DPI_FORMAT);
}
connected = true;
}
-@@ -1355,6 +1349,18 @@ static u32 vc5_hdmi_channel_map(struct v
+@@ -1356,6 +1350,18 @@ static u32 vc5_hdmi_channel_map(struct v
return channel_map;
}
/* HDMI audio codec callbacks */
static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,
unsigned int samplerate)
-@@ -2777,6 +2783,7 @@ static const struct vc4_hdmi_variant bcm
+@@ -2778,6 +2784,7 @@ static const struct vc4_hdmi_variant bcm
.phy_rng_disable = vc5_hdmi_phy_rng_disable,
.channel_map = vc5_hdmi_channel_map,
.supports_hdr = true,
};
static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
-@@ -2805,6 +2812,7 @@ static const struct vc4_hdmi_variant bcm
+@@ -2806,6 +2813,7 @@ static const struct vc4_hdmi_variant bcm
.phy_rng_disable = vc5_hdmi_phy_rng_disable,
.channel_map = vc5_hdmi_channel_map,
.supports_hdr = true,
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
-@@ -2193,7 +2193,6 @@ static int vc4_hdmi_cec_init(struct vc4_
+@@ -2194,7 +2194,6 @@ static int vc4_hdmi_cec_init(struct vc4_
struct platform_device *pdev = vc4_hdmi->pdev;
struct device *dev = &pdev->dev;
unsigned long flags;
int ret;
if (!of_find_property(dev->of_node, "interrupts", NULL)) {
-@@ -2213,15 +2212,6 @@ static int vc4_hdmi_cec_init(struct vc4_
+@@ -2214,15 +2213,6 @@ static int vc4_hdmi_cec_init(struct vc4_
cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
if (vc4_hdmi->variant->external_irq_controller) {
ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-rx"),
vc4_cec_irq_handler_rx_bare,
-@@ -2284,6 +2274,29 @@ static void vc4_hdmi_cec_exit(struct vc4
+@@ -2285,6 +2275,29 @@ static void vc4_hdmi_cec_exit(struct vc4
cec_unregister_adapter(vc4_hdmi->cec_adap);
}
#else
static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
{
-@@ -2292,6 +2305,10 @@ static int vc4_hdmi_cec_init(struct vc4_
+@@ -2293,6 +2306,10 @@ static int vc4_hdmi_cec_init(struct vc4_
static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {};
#endif
static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi,
-@@ -2526,6 +2543,15 @@ static int vc4_hdmi_runtime_resume(struc
+@@ -2527,6 +2544,15 @@ static int vc4_hdmi_runtime_resume(struc
if (ret)
return ret;
+++ /dev/null
-From e664a91ea54b3488d6c08dd82dac2af1239c3275 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.com>
-Date: Thu, 2 Dec 2021 18:21:46 +0000
-Subject: [PATCH] drm/vc4: dpi: Add option for inverting pixel clock
- and output enable
-
-DRM provides flags for inverting pixel clock and output enable
-signals, but these were not mapped to the relevant registers.
-
-Add those mappings.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
----
- drivers/gpu/drm/vc4/vc4_dpi.c | 89 ++++++++++++++++++++---------------
- 1 file changed, 51 insertions(+), 38 deletions(-)
-
---- a/drivers/gpu/drm/vc4/vc4_dpi.c
-+++ b/drivers/gpu/drm/vc4/vc4_dpi.c
-@@ -148,45 +148,58 @@ static void vc4_dpi_encoder_enable(struc
- }
- drm_connector_list_iter_end(&conn_iter);
-
-- if (connector && connector->display_info.num_bus_formats) {
-- u32 bus_format = connector->display_info.bus_formats[0];
-+ if (connector) {
-+ if (connector->display_info.num_bus_formats) {
-+ u32 bus_format = connector->display_info.bus_formats[0];
-
-- switch (bus_format) {
-- case MEDIA_BUS_FMT_RGB888_1X24:
-- dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB,
-- DPI_FORMAT);
-- break;
-- case MEDIA_BUS_FMT_BGR888_1X24:
-- dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB,
-- DPI_FORMAT);
-- dpi_c |= VC4_SET_FIELD(DPI_ORDER_BGR, DPI_ORDER);
-- break;
-- case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
-- dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_2,
-- DPI_FORMAT);
-- break;
-- case MEDIA_BUS_FMT_BGR666_1X24_CPADHI:
-- dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_2,
-- DPI_FORMAT);
-- dpi_c |= VC4_SET_FIELD(DPI_ORDER_BGR, DPI_ORDER);
-- break;
-- case MEDIA_BUS_FMT_RGB666_1X18:
-- dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_1,
-- DPI_FORMAT);
-- break;
-- case MEDIA_BUS_FMT_BGR666_1X18:
-- dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_1,
-- DPI_FORMAT);
-- dpi_c |= VC4_SET_FIELD(DPI_ORDER_BGR, DPI_ORDER);
-- break;
-- case MEDIA_BUS_FMT_RGB565_1X16:
-- dpi_c |= VC4_SET_FIELD(DPI_FORMAT_16BIT_565_RGB_3,
-- DPI_FORMAT);
-- break;
-- default:
-- DRM_ERROR("Unknown media bus format %d\n", bus_format);
-- break;
-+ switch (bus_format) {
-+ case MEDIA_BUS_FMT_RGB888_1X24:
-+ dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB,
-+ DPI_FORMAT);
-+ break;
-+ case MEDIA_BUS_FMT_BGR888_1X24:
-+ dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB,
-+ DPI_FORMAT);
-+ dpi_c |= VC4_SET_FIELD(DPI_ORDER_BGR,
-+ DPI_ORDER);
-+ break;
-+ case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
-+ dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_2,
-+ DPI_FORMAT);
-+ break;
-+ case MEDIA_BUS_FMT_BGR666_1X24_CPADHI:
-+ dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_2,
-+ DPI_FORMAT);
-+ dpi_c |= VC4_SET_FIELD(DPI_ORDER_BGR,
-+ DPI_ORDER);
-+ break;
-+ case MEDIA_BUS_FMT_RGB666_1X18:
-+ dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_1,
-+ DPI_FORMAT);
-+ break;
-+ case MEDIA_BUS_FMT_BGR666_1X18:
-+ dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_1,
-+ DPI_FORMAT);
-+ dpi_c |= VC4_SET_FIELD(DPI_ORDER_BGR,
-+ DPI_ORDER);
-+ break;
-+ case MEDIA_BUS_FMT_RGB565_1X16:
-+ dpi_c |= VC4_SET_FIELD(DPI_FORMAT_16BIT_565_RGB_3,
-+ DPI_FORMAT);
-+ break;
-+ default:
-+ DRM_ERROR("Unknown media bus format %d\n",
-+ bus_format);
-+ break;
-+ }
- }
-+
-+ if (connector->display_info.bus_flags &
-+ DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
-+ dpi_c |= DPI_PIXEL_CLK_INVERT;
-+
-+ if (connector->display_info.bus_flags & DRM_BUS_FLAG_DE_LOW)
-+ dpi_c |= DPI_OUTPUT_ENABLE_INVERT;
- } else {
- /* Default to 18bit if no connector found. */
- dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_1, DPI_FORMAT);
--- a/drivers/gpu/drm/vc4/vc4_dpi.c
+++ b/drivers/gpu/drm/vc4/vc4_dpi.c
-@@ -173,6 +173,10 @@ static void vc4_dpi_encoder_enable(struc
- dpi_c |= VC4_SET_FIELD(DPI_ORDER_BGR,
- DPI_ORDER);
+@@ -172,6 +172,10 @@ static void vc4_dpi_encoder_enable(struc
+ DPI_FORMAT);
+ dpi_c |= VC4_SET_FIELD(DPI_ORDER_BGR, DPI_ORDER);
break;
+ default:
+ DRM_ERROR("Unknown media bus format %d\n",
case MEDIA_BUS_FMT_RGB666_1X18:
dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_1,
DPI_FORMAT);
-@@ -187,11 +191,12 @@ static void vc4_dpi_encoder_enable(struc
- dpi_c |= VC4_SET_FIELD(DPI_FORMAT_16BIT_565_RGB_3,
+@@ -185,11 +189,12 @@ static void vc4_dpi_encoder_enable(struc
+ dpi_c |= VC4_SET_FIELD(DPI_FORMAT_16BIT_565_RGB_1,
DPI_FORMAT);
break;
- default:
+
}
- if (connector->display_info.bus_flags &
+ if (connector->display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
--- a/drivers/media/i2c/imx219.c
+++ b/drivers/media/i2c/imx219.c
-@@ -118,6 +118,16 @@
+@@ -124,6 +124,16 @@
#define IMX219_PIXEL_ARRAY_WIDTH 3280U
#define IMX219_PIXEL_ARRAY_HEIGHT 2464U
struct imx219_reg {
u16 address;
u8 val;
-@@ -538,7 +548,7 @@ static const struct imx219_mode supporte
+@@ -448,7 +458,7 @@ static const struct imx219_mode supporte
struct imx219 {
struct v4l2_subdev sd;
struct v4l2_mbus_framefmt fmt;
-@@ -688,18 +698,26 @@ static void imx219_set_default_format(st
+@@ -598,18 +608,26 @@ static void imx219_set_default_format(st
static int imx219_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
{
struct imx219 *imx219 = to_imx219(sd);
/* Initialize try_crop rectangle. */
try_crop = v4l2_subdev_get_try_crop(sd, fh->state, 0);
-@@ -808,12 +826,21 @@ static int imx219_enum_mbus_code(struct
+@@ -718,12 +736,21 @@ static int imx219_enum_mbus_code(struct
{
struct imx219 *imx219 = to_imx219(sd);
return 0;
}
-@@ -823,21 +850,30 @@ static int imx219_enum_frame_size(struct
+@@ -733,21 +760,30 @@ static int imx219_enum_frame_size(struct
struct v4l2_subdev_frame_size_enum *fse)
{
struct imx219 *imx219 = to_imx219(sd);
return 0;
}
-@@ -852,9 +888,9 @@ static void imx219_reset_colorspace(stru
+@@ -762,9 +798,9 @@ static void imx219_reset_colorspace(stru
fmt->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt->colorspace);
}
{
fmt->format.width = mode->width;
fmt->format.height = mode->height;
-@@ -862,21 +898,39 @@ static void imx219_update_pad_format(str
+@@ -772,21 +808,39 @@ static void imx219_update_pad_format(str
imx219_reset_colorspace(&fmt->format);
}
}
return 0;
-@@ -906,51 +960,74 @@ static int imx219_set_pad_format(struct
+@@ -816,51 +870,74 @@ static int imx219_set_pad_format(struct
int exposure_max, exposure_def, hblank;
unsigned int i;
}
mutex_unlock(&imx219->mutex);
-@@ -1037,9 +1114,11 @@ static int imx219_start_streaming(struct
+@@ -976,9 +1053,11 @@ static int imx219_start_streaming(struct
const struct imx219_reg_list *reg_list;
int ret;
return ret;
+ }
- /* Apply default values of current mode */
- reg_list = &imx219->mode->reg_list;
-@@ -1133,21 +1212,22 @@ err_unlock:
+ /* Send all registers that are common to all modes */
+ ret = imx219_write_regs(imx219, imx219_common_regs, ARRAY_SIZE(imx219_common_regs));
+@@ -1086,21 +1165,22 @@ err_unlock:
/* Power/clock management functions */
static int imx219_power_on(struct device *dev)
{
__func__);
goto reg_off;
}
-@@ -1166,7 +1246,8 @@ reg_off:
+@@ -1119,7 +1199,8 @@ reg_off:
static int imx219_power_off(struct device *dev)
{
struct imx219 *imx219 = to_imx219(sd);
gpiod_set_value_cansleep(imx219->reset_gpio, 0);
-@@ -1178,7 +1259,8 @@ static int imx219_power_off(struct devic
+@@ -1131,7 +1212,8 @@ static int imx219_power_off(struct devic
static int __maybe_unused imx219_suspend(struct device *dev)
{
struct imx219 *imx219 = to_imx219(sd);
if (imx219->streaming)
-@@ -1189,7 +1271,8 @@ static int __maybe_unused imx219_suspend
+@@ -1142,7 +1224,8 @@ static int __maybe_unused imx219_suspend
static int __maybe_unused imx219_resume(struct device *dev)
{
struct imx219 *imx219 = to_imx219(sd);
int ret;
-@@ -1525,13 +1608,14 @@ static int imx219_probe(struct i2c_clien
+@@ -1478,13 +1561,14 @@ static int imx219_probe(struct i2c_clien
V4L2_SUBDEV_FL_HAS_EVENTS;
imx219->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
{
unsigned long flags;
-@@ -1219,15 +1211,6 @@ static void vc4_hdmi_encoder_post_crtc_e
+@@ -1220,15 +1212,6 @@ static void vc4_hdmi_encoder_post_crtc_e
mutex_unlock(&vc4_hdmi->mutex);
}
static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder,
struct drm_crtc_state *crtc_state,
struct drm_connector_state *conn_state)
-@@ -1321,8 +1304,6 @@ static const struct drm_encoder_helper_f
+@@ -1322,8 +1305,6 @@ static const struct drm_encoder_helper_f
.atomic_check = vc4_hdmi_encoder_atomic_check,
.atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set,
.mode_valid = vc4_hdmi_encoder_mode_valid,
};
static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
-@@ -1422,16 +1403,10 @@ static bool vc4_hdmi_audio_can_stream(st
+@@ -1423,16 +1404,10 @@ static bool vc4_hdmi_audio_can_stream(st
lockdep_assert_held(&vc4_hdmi->mutex);
/*
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
-@@ -2280,7 +2280,7 @@ static int vc4_hdmi_cec_init(struct vc4_
+@@ -2281,7 +2281,7 @@ static int vc4_hdmi_cec_init(struct vc4_
static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {};
spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
-@@ -1201,6 +1202,7 @@ static void vc4_hdmi_encoder_post_crtc_e
+@@ -1202,6 +1203,7 @@ static void vc4_hdmi_encoder_post_crtc_e
VC4_HDMI_RAM_PACKET_ENABLE);
spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
vc4_hdmi_set_infoframes(encoder);
}
-@@ -1606,7 +1608,8 @@ static int vc4_hdmi_audio_prepare(struct
+@@ -1607,7 +1609,8 @@ static int vc4_hdmi_audio_prepare(struct
spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
memcpy(&vc4_hdmi->audio.infoframe, ¶ms->cea, sizeof(params->cea));
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
-@@ -5743,13 +5743,13 @@ static const u32 hdmi_colorimetry_val[]
+@@ -5746,13 +5746,13 @@ static const u32 hdmi_colorimetry_val[]
#undef ACE
/**
const struct drm_connector_state *conn_state)
{
u32 colorimetry_val;
-@@ -5768,7 +5768,7 @@ drm_hdmi_avi_infoframe_colorspace(struct
+@@ -5771,7 +5771,7 @@ drm_hdmi_avi_infoframe_colorspace(struct
frame->extended_colorimetry = (colorimetry_val >> 2) &
EXTENDED_COLORIMETRY_MASK;
}
static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
{
struct drm_info_node *node = (struct drm_info_node *)m->private;
-@@ -1116,8 +1125,7 @@ static void vc4_hdmi_encoder_pre_crtc_en
+@@ -1117,8 +1126,7 @@ static void vc4_hdmi_encoder_pre_crtc_en
mutex_lock(&vc4_hdmi->mutex);
/* CEA VICs other than #1 requre limited range RGB
* output unless overridden by an AVI infoframe.
* Apply a colorspace conversion to squash 0-255 down
-@@ -1120,22 +1121,12 @@ static void vc4_hdmi_encoder_pre_crtc_en
+@@ -1121,22 +1122,12 @@ static void vc4_hdmi_encoder_pre_crtc_en
{
struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode)) {
/* CEA VICs other than #1 requre limited range RGB
* output unless overridden by an AVI infoframe.
-@@ -906,7 +908,6 @@ static void vc5_hdmi_set_timings(struct
+@@ -907,7 +909,6 @@ static void vc5_hdmi_set_timings(struct
spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
--- a/drivers/gpu/drm/vc4/vc4_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_regs.h
-@@ -804,6 +804,9 @@ enum {
+@@ -810,6 +810,9 @@ enum {
# define VC4_HD_CSC_CTL_RGB2YCC BIT(1)
# define VC4_HD_CSC_CTL_ENABLE BIT(0)
const struct drm_display_mode *mode)
{
unsigned long flags;
-@@ -1141,13 +1143,16 @@ static void vc4_hdmi_encoder_pre_crtc_en
+@@ -1142,13 +1144,16 @@ static void vc4_hdmi_encoder_pre_crtc_en
struct drm_atomic_state *state)
{
struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
-@@ -1251,6 +1251,19 @@ static void vc4_hdmi_encoder_atomic_mode
+@@ -1252,6 +1252,19 @@ static void vc4_hdmi_encoder_atomic_mode
mutex_unlock(&vc4_hdmi->mutex);
}
#define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL
#define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL
-@@ -1295,10 +1308,7 @@ static int vc4_hdmi_encoder_atomic_check
+@@ -1296,10 +1309,7 @@ static int vc4_hdmi_encoder_atomic_check
if (mode->flags & DRM_MODE_FLAG_DBLCLK)
pixel_rate = pixel_rate * 2;
return -EINVAL;
vc4_state->pixel_rate = pixel_rate;
-@@ -1318,13 +1328,7 @@ vc4_hdmi_encoder_mode_valid(struct drm_e
+@@ -1319,13 +1329,7 @@ vc4_hdmi_encoder_mode_valid(struct drm_e
(mode->hsync_end % 2) || (mode->htotal % 2)))
return MODE_H_ILLEGAL;
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
-@@ -1264,6 +1264,35 @@ vc4_hdmi_encoder_clock_valid(const struc
+@@ -1265,6 +1265,35 @@ vc4_hdmi_encoder_clock_valid(const struc
return MODE_OK;
}
#define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL
#define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL
-@@ -1276,6 +1305,7 @@ static int vc4_hdmi_encoder_atomic_check
+@@ -1277,6 +1306,7 @@ static int vc4_hdmi_encoder_atomic_check
struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
unsigned long long pixel_rate = mode->clock * 1000;
unsigned long long tmds_rate;
if (vc4_hdmi->variant->unsupported_odd_h_timings &&
!(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
-@@ -1297,21 +1327,10 @@ static int vc4_hdmi_encoder_atomic_check
+@@ -1298,21 +1328,10 @@ static int vc4_hdmi_encoder_atomic_check
pixel_rate = mode->clock * 1000;
}
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
-@@ -1255,12 +1255,18 @@ static enum drm_mode_status
+@@ -1256,12 +1256,18 @@ static enum drm_mode_status
vc4_hdmi_encoder_clock_valid(const struct vc4_hdmi *vc4_hdmi,
unsigned long long clock)
{
return;
drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
-@@ -1245,6 +1253,7 @@ static void vc4_hdmi_encoder_atomic_mode
+@@ -1246,6 +1254,7 @@ static void vc4_hdmi_encoder_atomic_mode
struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
mutex_lock(&vc4_hdmi->mutex);
bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
-@@ -961,7 +964,7 @@ static void vc5_hdmi_set_timings(struct
+@@ -962,7 +965,7 @@ static void vc5_hdmi_set_timings(struct
HDMI_WRITE(HDMI_VERTB0, vertb_even);
HDMI_WRITE(HDMI_VERTB1, vertb);
case 12:
gcp = 6;
gcp_en = true;
-@@ -1251,9 +1254,11 @@ static void vc4_hdmi_encoder_atomic_mode
+@@ -1252,9 +1255,11 @@ static void vc4_hdmi_encoder_atomic_mode
struct drm_connector_state *conn_state)
{
struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
memcpy(&vc4_hdmi->saved_adjusted_mode,
&crtc_state->adjusted_mode,
sizeof(vc4_hdmi->saved_adjusted_mode));
-@@ -1308,6 +1313,38 @@ vc4_hdmi_encoder_compute_clock(const str
+@@ -1309,6 +1314,38 @@ vc4_hdmi_encoder_compute_clock(const str
return 0;
}
#define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL
#define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL
-@@ -1342,8 +1379,7 @@ static int vc4_hdmi_encoder_atomic_check
+@@ -1343,8 +1380,7 @@ static int vc4_hdmi_encoder_atomic_check
pixel_rate = mode->clock * 1000;
}
HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
-@@ -980,6 +1093,15 @@ static void vc5_hdmi_set_timings(struct
+@@ -981,6 +1094,15 @@ static void vc5_hdmi_set_timings(struct
break;
}
reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
-@@ -1259,12 +1381,97 @@ static void vc4_hdmi_encoder_atomic_mode
+@@ -1260,12 +1382,97 @@ static void vc4_hdmi_encoder_atomic_mode
mutex_lock(&vc4_hdmi->mutex);
vc4_hdmi->output_bpc = vc4_state->output_bpc;
static enum drm_mode_status
vc4_hdmi_encoder_clock_valid(const struct vc4_hdmi *vc4_hdmi,
unsigned long long clock)
-@@ -1286,13 +1493,17 @@ vc4_hdmi_encoder_clock_valid(const struc
+@@ -1287,13 +1494,17 @@ vc4_hdmi_encoder_clock_valid(const struc
static unsigned long long
vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
return clock * bpc / 8;
}
-@@ -1300,11 +1511,11 @@ static int
+@@ -1301,11 +1512,11 @@ static int
vc4_hdmi_encoder_compute_clock(const struct vc4_hdmi *vc4_hdmi,
struct vc4_hdmi_connector_state *vc4_state,
const struct drm_display_mode *mode,
if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, clock) != MODE_OK)
return -EINVAL;
-@@ -1314,10 +1525,55 @@ vc4_hdmi_encoder_compute_clock(const str
+@@ -1315,10 +1526,55 @@ vc4_hdmi_encoder_compute_clock(const str
}
static int
struct drm_connector_state *conn_state = &vc4_state->base;
unsigned int max_bpc = clamp_t(unsigned int, conn_state->max_bpc, 8, 12);
unsigned int bpc;
-@@ -1326,17 +1582,18 @@ vc4_hdmi_encoder_compute_config(const st
+@@ -1327,17 +1583,18 @@ vc4_hdmi_encoder_compute_config(const st
for (bpc = max_bpc; bpc >= 8; bpc -= 2) {
drm_dbg(dev, "Trying with a %d bpc output\n", bpc);
static inline
--- a/drivers/gpu/drm/vc4/vc4_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_regs.h
-@@ -804,11 +804,27 @@ enum {
+@@ -810,11 +810,27 @@ enum {
# define VC4_HD_CSC_CTL_RGB2YCC BIT(1)
# define VC4_HD_CSC_CTL_ENABLE BIT(0)
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
-@@ -1415,9 +1415,6 @@ vc4_hdmi_sink_supports_format_bpc(const
+@@ -1416,9 +1416,6 @@ vc4_hdmi_sink_supports_format_bpc(const
case VC4_HDMI_OUTPUT_RGB:
drm_dbg(dev, "RGB Format, checking the constraints.\n");
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
-@@ -664,6 +664,48 @@ static const u32 colorspace_coeffs[2][DR
+@@ -666,6 +666,48 @@ static const u32 colorspace_coeffs[2][DR
}
};
/* Writes out a full display list for an active plane to the plane's
* private dlist state.
*/
-@@ -946,13 +988,8 @@ static int vc4_plane_mode_set(struct drm
+@@ -948,13 +990,8 @@ static int vc4_plane_mode_set(struct drm
/* Position Word 2: Source Image Size, Alpha */
vc4_state->pos2_offset = vc4_state->dlist_count;
vc4_dlist_write(vc4_state,
VC4_SET_FIELD(vc4_state->src_w[0],
SCALER_POS2_WIDTH) |
VC4_SET_FIELD(vc4_state->src_h[0],
-@@ -997,14 +1034,9 @@ static int vc4_plane_mode_set(struct drm
+@@ -999,14 +1036,9 @@ static int vc4_plane_mode_set(struct drm
vc4_dlist_write(vc4_state,
VC4_SET_FIELD(state->alpha >> 4,
SCALER5_CTL2_ALPHA) |
);
/* Position Word 1: Scaled Image Dimensions. */
-@@ -1494,6 +1526,10 @@ struct drm_plane *vc4_plane_init(struct
+@@ -1496,6 +1528,10 @@ struct drm_plane *vc4_plane_init(struct
drm_plane_helper_add(plane, &vc4_plane_helper_funcs);
drm_plane_create_alpha_property(plane);
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
-@@ -1496,7 +1496,7 @@ vc4_hdmi_encoder_compute_mode_clock(cons
+@@ -1497,7 +1497,7 @@ vc4_hdmi_encoder_compute_mode_clock(cons
unsigned int bpc,
enum vc4_hdmi_output_format fmt)
{
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
-@@ -1093,6 +1093,16 @@ config MFD_SPMI_PMIC
+@@ -1094,6 +1094,16 @@ config MFD_SPMI_PMIC
Say M here if you want to include support for the SPMI PMIC
series as a module. The module will be called "qcom-spmi-pmic".
drm_connector_attach_encoder(connector, encoder);
return 0;
-@@ -1385,6 +1487,7 @@ static void vc4_hdmi_encoder_atomic_mode
+@@ -1386,6 +1488,7 @@ static void vc4_hdmi_encoder_atomic_mode
mutex_lock(&vc4_hdmi->mutex);
vc4_hdmi->output_bpc = vc4_state->output_bpc;
vc4_hdmi->output_format = vc4_state->output_format;
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
-@@ -135,6 +135,34 @@ static const struct hvs_format {
+@@ -137,6 +137,34 @@ static const struct hvs_format {
.pixel_order = HVS_PIXEL_ORDER_XYCBCR,
.hvs5_only = true,
},
--- a/drivers/gpu/drm/vc4/vc4_dpi.c
+++ b/drivers/gpu/drm/vc4/vc4_dpi.c
-@@ -191,6 +191,10 @@ static void vc4_dpi_encoder_enable(struc
- dpi_c |= VC4_SET_FIELD(DPI_FORMAT_16BIT_565_RGB_3,
+@@ -189,6 +189,10 @@ static void vc4_dpi_encoder_enable(struc
+ dpi_c |= VC4_SET_FIELD(DPI_FORMAT_16BIT_565_RGB_1,
DPI_FORMAT);
break;
+ case MEDIA_BUS_FMT_RGB565_1X24_CPADHI:
--- a/drivers/media/i2c/imx219.c
+++ b/drivers/media/i2c/imx219.c
-@@ -153,6 +153,9 @@ struct imx219_mode {
+@@ -162,6 +162,9 @@ struct imx219_mode {
- /* Default register values */
- struct imx219_reg_list reg_list;
+ /* 2x2 binning is used */
+ bool binning;
+
+ /* Relative pixel clock rate factor for the mode. */
+ unsigned int rate_factor;
};
- /*
-@@ -495,6 +498,7 @@ static const struct imx219_mode supporte
- .num_of_regs = ARRAY_SIZE(mode_3280x2464_regs),
+ static const struct imx219_reg imx219_common_regs[] = {
+@@ -402,6 +405,7 @@ static const struct imx219_mode supporte
.regs = mode_3280x2464_regs,
},
+ .binning = false,
+ .rate_factor = 1,
},
{
/* 1080P 30fps cropped */
-@@ -511,6 +515,7 @@ static const struct imx219_mode supporte
- .num_of_regs = ARRAY_SIZE(mode_1920_1080_regs),
+@@ -419,6 +423,7 @@ static const struct imx219_mode supporte
.regs = mode_1920_1080_regs,
},
+ .binning = false,
+ .rate_factor = 1,
},
{
/* 2x2 binned 30fps mode */
-@@ -527,6 +532,7 @@ static const struct imx219_mode supporte
- .num_of_regs = ARRAY_SIZE(mode_1640_1232_regs),
+@@ -436,6 +441,7 @@ static const struct imx219_mode supporte
.regs = mode_1640_1232_regs,
},
+ .binning = true,
+ .rate_factor = 1,
},
{
/* 640x480 30fps mode */
-@@ -543,6 +549,11 @@ static const struct imx219_mode supporte
- .num_of_regs = ARRAY_SIZE(mode_640_480_regs),
+@@ -453,6 +459,11 @@ static const struct imx219_mode supporte
.regs = mode_640_480_regs,
},
+ .binning = true,
+ /*
-+ * This mode uses a special 2x2 binning that doubles the
-+ * the internal pixel clock rate.
-+ */
++ * This mode uses a special 2x2 binning that doubles the
++ * the internal pixel clock rate.
++ */
+ .rate_factor = 2,
},
};
-@@ -765,7 +776,8 @@ static int imx219_set_ctrl(struct v4l2_c
+@@ -675,7 +686,8 @@ static int imx219_set_ctrl(struct v4l2_c
break;
case V4L2_CID_EXPOSURE:
ret = imx219_write_reg(imx219, IMX219_REG_EXPOSURE,
break;
case V4L2_CID_DIGITAL_GAIN:
ret = imx219_write_reg(imx219, IMX219_REG_DIGITAL_GAIN,
-@@ -785,7 +797,8 @@ static int imx219_set_ctrl(struct v4l2_c
+@@ -695,7 +707,8 @@ static int imx219_set_ctrl(struct v4l2_c
case V4L2_CID_VBLANK:
ret = imx219_write_reg(imx219, IMX219_REG_VTS,
IMX219_REG_VALUE_16BIT,
break;
case V4L2_CID_TEST_PATTERN_RED:
ret = imx219_write_reg(imx219, IMX219_REG_TESTP_RED,
-@@ -957,7 +970,7 @@ static int imx219_set_pad_format(struct
+@@ -867,7 +880,7 @@ static int imx219_set_pad_format(struct
struct imx219 *imx219 = to_imx219(sd);
const struct imx219_mode *mode;
struct v4l2_mbus_framefmt *framefmt;
unsigned int i;
if (fmt->pad >= NUM_PADS)
-@@ -1018,6 +1031,12 @@ static int imx219_set_pad_format(struct
+@@ -928,6 +941,12 @@ static int imx219_set_pad_format(struct
hblank = IMX219_PPL_DEFAULT - mode->width;
__v4l2_ctrl_modify_range(imx219->hblank, hblank, hblank,
1, hblank);
}
} else {
if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
-@@ -1362,7 +1381,7 @@ static int imx219_init_controls(struct i
+@@ -1315,7 +1334,7 @@ static int imx219_init_controls(struct i
struct v4l2_ctrl_handler *ctrl_hdlr;
unsigned int height = imx219->mode->height;
struct v4l2_fwnode_device_properties props;
int i, ret;
ctrl_hdlr = &imx219->ctrl_handler;
-@@ -1374,11 +1393,11 @@ static int imx219_init_controls(struct i
+@@ -1327,11 +1346,11 @@ static int imx219_init_controls(struct i
ctrl_hdlr->lock = &imx219->mutex;
/* By default, PIXEL_RATE is read only */
+++ /dev/null
-From 4626e370de018aed097d54247bae5a29391198ee Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.com>
-Date: Mon, 14 Feb 2022 15:34:51 +0000
-Subject: [PATCH] drm/vc4: For DPI, MEDIA_BUS_FMT_RGB565_1X16 is mode
- 1, not 3.
-
-The mapping is incorrect for RGB565_1X16 as it should be
-DPI_FORMAT_18BIT_666_RGB_1 instead of DPI_FORMAT_18BIT_666_RGB_3.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
----
- drivers/gpu/drm/vc4/vc4_dpi.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/gpu/drm/vc4/vc4_dpi.c
-+++ b/drivers/gpu/drm/vc4/vc4_dpi.c
-@@ -188,7 +188,7 @@ static void vc4_dpi_encoder_enable(struc
- DPI_ORDER);
- break;
- case MEDIA_BUS_FMT_RGB565_1X16:
-- dpi_c |= VC4_SET_FIELD(DPI_FORMAT_16BIT_565_RGB_3,
-+ dpi_c |= VC4_SET_FIELD(DPI_FORMAT_16BIT_565_RGB_1,
- DPI_FORMAT);
- break;
- case MEDIA_BUS_FMT_RGB565_1X24_CPADHI:
* overwrite the setup from the bootloader (just 128b out of
--- a/drivers/gpu/drm/vc4/vc4_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_regs.h
-@@ -234,6 +234,7 @@
+@@ -240,6 +240,7 @@
# define SCALER_DISPCTRL_DSPEIEOLN(x) BIT(8 + ((x) * 2))
/* Enables Display 0 EOF contribution to SCALER_DISPSTAT_IRQDISP0 */
# define SCALER_DISPCTRL_DSPEIEOF(x) BIT(7 + ((x) * 2))
if (ret)
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
-@@ -1573,9 +1573,14 @@ struct drm_plane *vc4_plane_init(struct
+@@ -1575,9 +1575,14 @@ struct drm_plane *vc4_plane_init(struct
DRM_COLOR_YCBCR_BT709,
DRM_COLOR_YCBCR_LIMITED_RANGE);
int vc4_plane_create_additional_planes(struct drm_device *drm)
{
struct drm_plane *cursor_plane;
-@@ -1591,7 +1596,7 @@ int vc4_plane_create_additional_planes(s
+@@ -1593,7 +1598,7 @@ int vc4_plane_create_additional_planes(s
* modest number of planes to expose, that should hopefully
* still cover any sane usecase.
*/
struct drm_plane *plane =
vc4_plane_init(drm, DRM_PLANE_TYPE_OVERLAY);
-@@ -1600,17 +1605,28 @@ int vc4_plane_create_additional_planes(s
+@@ -1602,17 +1607,28 @@ int vc4_plane_create_additional_planes(s
plane->possible_crtcs =
GENMASK(drm->mode_config.num_crtc - 1, 0);
u32 src_w[2], src_h[2];
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
-@@ -179,9 +179,9 @@ static const struct hvs_format *vc4_get_
+@@ -181,9 +181,9 @@ static const struct hvs_format *vc4_get_
static enum vc4_scaling_mode vc4_get_scaling_mode(u32 src, u32 dst)
{
return VC4_SCALING_PPF;
else
return VC4_SCALING_TPZ;
-@@ -388,15 +388,10 @@ static int vc4_plane_setup_clipping_and_
+@@ -390,15 +390,10 @@ static int vc4_plane_setup_clipping_and_
for (i = 0; i < num_planes; i++)
vc4_state->offsets[i] = bo->paddr + fb->offsets[i];
vc4_state->crtc_x = state->dst.x1;
vc4_state->crtc_y = state->dst.y1;
-@@ -449,7 +444,7 @@ static void vc4_write_tpz(struct vc4_pla
+@@ -451,7 +446,7 @@ static void vc4_write_tpz(struct vc4_pla
{
u32 scale, recip;
/* The specs note that while the reciprocal would be defined
* as (1<<32)/scale, ~0 is close enough.
-@@ -495,7 +490,7 @@ static u32 vc4_lbm_size(struct drm_plane
+@@ -497,7 +492,7 @@ static u32 vc4_lbm_size(struct drm_plane
if (vc4_state->x_scaling[0] == VC4_SCALING_TPZ)
pix_per_line = vc4_state->crtc_w;
else
if (!vc4_state->is_yuv) {
if (vc4_state->y_scaling[0] == VC4_SCALING_TPZ)
-@@ -586,7 +581,8 @@ static void vc4_plane_calc_load(struct d
+@@ -588,7 +583,8 @@ static void vc4_plane_calc_load(struct d
for (i = 0; i < fb->format->num_planes; i++) {
/* Even if the bandwidth/plane required for a single frame is
*
*
* when downscaling, we have to read more pixels per line in
* the time frame reserved for a single line, so the bandwidth
-@@ -595,11 +591,11 @@ static void vc4_plane_calc_load(struct d
+@@ -597,11 +593,11 @@ static void vc4_plane_calc_load(struct d
* load by this number. We're likely over-estimating the read
* demand, but that's better than under-estimating it.
*/
vc4_state->hvs_load += vc4_state->crtc_h * vc4_state->crtc_w;
}
-@@ -752,7 +748,8 @@ static int vc4_plane_mode_set(struct drm
+@@ -754,7 +750,8 @@ static int vc4_plane_mode_set(struct drm
bool mix_plane_alpha;
bool covers_screen;
u32 scl0, scl1, pitch0;
u32 hvs_format = format->hvs;
unsigned int rotation;
int ret, i;
-@@ -764,6 +761,9 @@ static int vc4_plane_mode_set(struct drm
+@@ -766,6 +763,9 @@ static int vc4_plane_mode_set(struct drm
if (ret)
return ret;
/* SCL1 is used for Cb/Cr scaling of planar formats. For RGB
* and 4:4:4, scl1 should be set to scl0 so both channels of
* the scaler do the same thing. For YUV, the Y plane needs
-@@ -784,9 +784,11 @@ static int vc4_plane_mode_set(struct drm
+@@ -786,9 +786,11 @@ static int vc4_plane_mode_set(struct drm
DRM_MODE_REFLECT_Y);
/* We must point to the last line when Y reflection is enabled. */
switch (base_format_mod) {
case DRM_FORMAT_MOD_LINEAR:
-@@ -801,7 +803,7 @@ static int vc4_plane_mode_set(struct drm
+@@ -803,7 +805,7 @@ static int vc4_plane_mode_set(struct drm
(i ? v_subsample : 1) *
fb->pitches[i];
(i ? h_subsample : 1) *
fb->format->cpp[i];
}
-@@ -824,7 +826,7 @@ static int vc4_plane_mode_set(struct drm
+@@ -826,7 +828,7 @@ static int vc4_plane_mode_set(struct drm
* pitch * tile_h == tile_size * tiles_per_row
*/
u32 tiles_w = fb->pitches[0] >> (tile_size_shift - tile_h_shift);
u32 tiles_r = tiles_w - tiles_l;
u32 tiles_t = src_y >> tile_h_shift;
/* Intra-tile offsets, which modify the base address (the
-@@ -834,7 +836,7 @@ static int vc4_plane_mode_set(struct drm
+@@ -836,7 +838,7 @@ static int vc4_plane_mode_set(struct drm
u32 tile_y = (src_y >> 4) & 1;
u32 subtile_y = (src_y >> 2) & 3;
u32 utile_y = src_y & 3;
u32 y_off = src_y & tile_h_mask;
/* When Y reflection is requested we must set the
-@@ -930,7 +932,7 @@ static int vc4_plane_mode_set(struct drm
+@@ -932,7 +934,7 @@ static int vc4_plane_mode_set(struct drm
* of the 12-pixels in that 128-bit word is the
* first pixel to be used
*/
u32 aligned = remaining_pixels / 12;
u32 last_bits = remaining_pixels % 12;
-@@ -952,12 +954,12 @@ static int vc4_plane_mode_set(struct drm
+@@ -954,12 +956,12 @@ static int vc4_plane_mode_set(struct drm
return -EINVAL;
}
pix_per_tile = tile_w / fb->format->cpp[0];
vc4_state->offsets[i] += param * tile_w * tile;
vc4_state->offsets[i] += src_y /
-@@ -1018,10 +1020,8 @@ static int vc4_plane_mode_set(struct drm
+@@ -1020,10 +1022,8 @@ static int vc4_plane_mode_set(struct drm
vc4_dlist_write(vc4_state,
(mix_plane_alpha ? SCALER_POS2_ALPHA_MIX : 0) |
vc4_hvs4_get_alpha_blend_mode(state) |
/* Position Word 3: Context. Written by the HVS. */
vc4_dlist_write(vc4_state, 0xc0c0c0c0);
-@@ -1079,10 +1079,8 @@ static int vc4_plane_mode_set(struct drm
+@@ -1081,10 +1081,8 @@ static int vc4_plane_mode_set(struct drm
/* Position Word 2: Source Image Size */
vc4_state->pos2_offset = vc4_state->dlist_count;
vc4_dlist_write(vc4_state,
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
-@@ -458,14 +458,47 @@ static void vc4_write_tpz(struct vc4_pla
+@@ -460,14 +460,47 @@ static void vc4_write_tpz(struct vc4_pla
VC4_SET_FIELD(recip, SCALER_TPZ1_RECIP));
}
}
static u32 vc4_lbm_size(struct drm_plane_state *state)
-@@ -524,13 +557,13 @@ static void vc4_write_scaling_parameters
+@@ -526,13 +559,13 @@ static void vc4_write_scaling_parameters
/* Ch0 H-PPF Word 0: Scaling Parameters */
if (vc4_state->x_scaling[channel] == VC4_SCALING_PPF) {
vc4_write_ppf(vc4_state,
vc4_dlist_write(vc4_state, 0xc0c0c0c0);
}
-@@ -978,6 +1011,24 @@ static int vc4_plane_mode_set(struct drm
+@@ -980,6 +1013,24 @@ static int vc4_plane_mode_set(struct drm
return -EINVAL;
}
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
-@@ -461,17 +461,18 @@ static void vc4_write_tpz(struct vc4_pla
+@@ -463,17 +463,18 @@ static void vc4_write_tpz(struct vc4_pla
/* phase magnitude bits */
#define PHASE_BITS 6
offset += -(1 << PHASE_BITS >> 2);
} else {
/* the phase is relative to scale_src->x, so shift it for display list's x value */
-@@ -557,13 +558,15 @@ static void vc4_write_scaling_parameters
+@@ -559,13 +560,15 @@ static void vc4_write_scaling_parameters
/* Ch0 H-PPF Word 0: Scaling Parameters */
if (vc4_state->x_scaling[channel] == VC4_SCALING_PPF) {
vc4_write_ppf(vc4_state,
vc4_dlist_write(vc4_state, 0xc0c0c0c0);
}
-@@ -1622,6 +1625,8 @@ struct drm_plane *vc4_plane_init(struct
+@@ -1624,6 +1627,8 @@ struct drm_plane *vc4_plane_init(struct
DRM_COLOR_YCBCR_BT709,
DRM_COLOR_YCBCR_LIMITED_RANGE);
--- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c
+++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
-@@ -910,9 +910,12 @@ static int bcm2835_pmx_free(struct pinct
+@@ -908,9 +908,12 @@ static int bcm2835_pmx_free(struct pinct
unsigned offset)
{
struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
return 0;
}
-@@ -954,10 +957,7 @@ static void bcm2835_pmx_gpio_disable_fre
+@@ -952,10 +955,7 @@ static void bcm2835_pmx_gpio_disable_fre
struct pinctrl_gpio_range *range,
unsigned offset)
{
* overwrite the setup from the bootloader (just 128b out of
--- a/drivers/gpu/drm/vc4/vc4_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_regs.h
-@@ -234,7 +234,6 @@
+@@ -240,7 +240,6 @@
# define SCALER_DISPCTRL_DSPEIEOLN(x) BIT(8 + ((x) * 2))
/* Enables Display 0 EOF contribution to SCALER_DISPSTAT_IRQDISP0 */
# define SCALER_DISPCTRL_DSPEIEOF(x) BIT(7 + ((x) * 2))
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
-@@ -1809,6 +1809,9 @@ static int vc4_hdmi_encoder_atomic_check
+@@ -1810,6 +1810,9 @@ static int vc4_hdmi_encoder_atomic_check
struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
struct drm_display_mode *mode = &crtc_state->adjusted_mode;
struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
unsigned long long pixel_rate = mode->clock * 1000;
unsigned long long tmds_rate;
int ret;
-@@ -1837,6 +1840,11 @@ static int vc4_hdmi_encoder_atomic_check
+@@ -1838,6 +1841,11 @@ static int vc4_hdmi_encoder_atomic_check
if (ret)
return ret;
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
-@@ -1551,9 +1551,6 @@ static void vc4_hdmi_encoder_post_crtc_e
+@@ -1552,9 +1552,6 @@ static void vc4_hdmi_encoder_post_crtc_e
WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
struct drm_device *drm = connector->dev;
struct drm_display_mode *mode;
-@@ -1672,11 +1673,12 @@ vc4_hdmi_encoder_clock_valid(const struc
+@@ -1673,11 +1674,12 @@ vc4_hdmi_encoder_clock_valid(const struc
{
const struct drm_connector *connector = &vc4_hdmi->connector;
const struct drm_display_info *info = &connector->display_info;
return MODE_CLOCK_HIGH;
if (info->max_tmds_clock && clock > (info->max_tmds_clock * 1000))
-@@ -3157,14 +3159,6 @@ static int vc4_hdmi_bind(struct device *
+@@ -3158,14 +3160,6 @@ static int vc4_hdmi_bind(struct device *
vc4_hdmi->disable_wifi_frequencies =
of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
-@@ -1429,6 +1429,10 @@ static int vc4_plane_atomic_async_check(
+@@ -1431,6 +1431,10 @@ static int vc4_plane_atomic_async_check(
old_vc4_state = to_vc4_plane_state(plane->state);
new_vc4_state = to_vc4_plane_state(new_plane_state);
/* 48k words of 2x12-bit pixels */
drm_mm_init(&hvs->lbm_mm, 0, 48 * 1024);
else
-@@ -1008,7 +1008,7 @@ static int vc4_hvs_bind(struct device *d
+@@ -1019,7 +1019,7 @@ static int vc4_hvs_bind(struct device *d
NULL);
vc4_debugfs_add_file(drm, "hvs_dlists", vc4_hvs_debugfs_dlist,
NULL);
} else {
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
-@@ -542,10 +542,10 @@ static u32 vc4_lbm_size(struct drm_plane
+@@ -544,10 +544,10 @@ static u32 vc4_lbm_size(struct drm_plane
}
/* Align it to 64 or 128 (hvs5) bytes */
return lbm;
}
-@@ -664,7 +664,7 @@ static int vc4_plane_allocate_lbm(struct
+@@ -666,7 +666,7 @@ static int vc4_plane_allocate_lbm(struct
ret = drm_mm_insert_node_generic(&vc4->hvs->lbm_mm,
&vc4_state->lbm,
lbm_size,
0, 0);
spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags);
-@@ -1039,7 +1039,7 @@ static int vc4_plane_mode_set(struct drm
+@@ -1041,7 +1041,7 @@ static int vc4_plane_mode_set(struct drm
mix_plane_alpha = state->alpha != DRM_BLEND_ALPHA_OPAQUE &&
fb->format->has_alpha;
/* Control word */
vc4_dlist_write(vc4_state,
SCALER_CTL0_VALID |
-@@ -1570,14 +1570,13 @@ static const struct drm_plane_funcs vc4_
+@@ -1572,14 +1572,13 @@ static const struct drm_plane_funcs vc4_
struct drm_plane *vc4_plane_init(struct drm_device *dev,
enum drm_plane_type type)
{
static const uint64_t modifiers[] = {
DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED,
DRM_FORMAT_MOD_BROADCOM_SAND128,
-@@ -1593,7 +1592,7 @@ struct drm_plane *vc4_plane_init(struct
+@@ -1595,7 +1594,7 @@ struct drm_plane *vc4_plane_init(struct
return ERR_PTR(-ENOMEM);
for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) {
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
-@@ -1502,6 +1502,13 @@ static const struct drm_plane_helper_fun
+@@ -1504,6 +1504,13 @@ static const struct drm_plane_helper_fun
.atomic_async_update = vc4_plane_atomic_async_update,
};
static bool vc4_format_mod_supported(struct drm_plane *plane,
uint32_t format,
uint64_t modifier)
-@@ -1606,7 +1613,10 @@ struct drm_plane *vc4_plane_init(struct
+@@ -1608,7 +1615,10 @@ struct drm_plane *vc4_plane_init(struct
if (ret)
return ERR_PTR(ret);
--- a/Makefile
+++ b/Makefile
-@@ -433,7 +433,8 @@ endif
+@@ -440,7 +440,8 @@ endif
HOSTPKG_CONFIG = pkg-config
export KBUILD_USERCFLAGS := -Wall -Wmissing-prototypes -Wstrict-prototypes \
--- a/Makefile
+++ b/Makefile
-@@ -517,7 +517,7 @@ KBUILD_CFLAGS := -Wall -Wundef -Werror
+@@ -524,7 +524,7 @@ KBUILD_CFLAGS := -Wall -Wundef -Werror
-fno-strict-aliasing -fno-common -fshort-wchar -fno-PIE \
-Werror=implicit-function-declaration -Werror=implicit-int \
-Werror=return-type -Wno-format-security \
--- a/Makefile
+++ b/Makefile
-@@ -433,7 +433,7 @@ endif
+@@ -440,7 +440,7 @@ endif
HOSTPKG_CONFIG = pkg-config
export KBUILD_USERCFLAGS := -Wall -Wmissing-prototypes -Wstrict-prototypes \
VM_BUG_ON_PAGE(tail > 2 && page_tail->mapping != TAIL_MAPPING,
--- a/mm/memcontrol.c
+++ b/mm/memcontrol.c
-@@ -5237,6 +5237,7 @@ static struct mem_cgroup *mem_cgroup_all
+@@ -5241,6 +5241,7 @@ static struct mem_cgroup *mem_cgroup_all
memcg->deferred_split_queue.split_queue_len = 0;
#endif
idr_replace(&mem_cgroup_idr, memcg, memcg->id.id);
/* will mmdrop() in finish_task_switch(). */
--- a/mm/memcontrol.c
+++ b/mm/memcontrol.c
-@@ -5174,6 +5174,7 @@ static void __mem_cgroup_free(struct mem
+@@ -5178,6 +5178,7 @@ static void __mem_cgroup_free(struct mem
static void mem_cgroup_free(struct mem_cgroup *memcg)
{
memcg_wb_domain_exit(memcg);
__mem_cgroup_free(memcg);
}
-@@ -6206,6 +6207,29 @@ static void mem_cgroup_move_task(void)
+@@ -6210,6 +6211,29 @@ static void mem_cgroup_move_task(void)
}
#endif
static int seq_puts_memcg_tunable(struct seq_file *m, unsigned long value)
{
if (value == PAGE_COUNTER_MAX)
-@@ -6549,6 +6573,7 @@ struct cgroup_subsys memory_cgrp_subsys
+@@ -6553,6 +6577,7 @@ struct cgroup_subsys memory_cgrp_subsys
.css_reset = mem_cgroup_css_reset,
.css_rstat_flush = mem_cgroup_css_rstat_flush,
.can_attach = mem_cgroup_can_attach,
interface-type = "ace";
reg = <0x5000 0x1000>;
};
-@@ -937,6 +937,8 @@
+@@ -938,6 +938,8 @@
power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
mediatek,ethsys = <ðsys>;
mediatek,sgmiisys = <&sgmiisys>;
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -893,6 +893,11 @@
+@@ -894,6 +894,11 @@
};
};
ethsys: syscon@1b000000 {
compatible = "mediatek,mt7622-ethsys",
"syscon";
-@@ -911,6 +916,26 @@
+@@ -912,6 +917,26 @@
#dma-cells = <1>;
};
eth: ethernet@1b100000 {
compatible = "mediatek,mt7622-eth",
"mediatek,mt2701-eth",
-@@ -938,6 +963,9 @@
+@@ -939,6 +964,9 @@
mediatek,ethsys = <ðsys>;
mediatek,sgmiisys = <&sgmiisys>;
mediatek,cci-control = <&cci_control2>;
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -962,7 +962,7 @@
+@@ -963,7 +963,7 @@
power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
mediatek,ethsys = <ðsys>;
mediatek,sgmiisys = <&sgmiisys>;
--- a/drivers/bluetooth/btusb.c
+++ b/drivers/bluetooth/btusb.c
-@@ -2268,6 +2268,23 @@ struct btmtk_section_map {
+@@ -2272,6 +2272,23 @@ struct btmtk_section_map {
};
} __packed;
static void btusb_mtk_wmt_recv(struct urb *urb)
{
struct hci_dev *hdev = urb->context;
-@@ -3919,6 +3936,7 @@ static int btusb_probe(struct usb_interf
+@@ -3923,6 +3940,7 @@ static int btusb_probe(struct usb_interf
hdev->shutdown = btusb_mtk_shutdown;
hdev->manufacturer = 70;
hdev->cmd_timeout = btusb_mtk_cmd_timeout;
--- a/drivers/bluetooth/btusb.c
+++ b/drivers/bluetooth/btusb.c
-@@ -2273,7 +2273,7 @@ static int btusb_set_bdaddr_mtk(struct h
+@@ -2277,7 +2277,7 @@ static int btusb_set_bdaddr_mtk(struct h
struct sk_buff *skb;
long ret;
--- a/drivers/bluetooth/btusb.c
+++ b/drivers/bluetooth/btusb.c
-@@ -460,6 +460,9 @@ static const struct usb_device_id blackl
+@@ -464,6 +464,9 @@ static const struct usb_device_id blackl
{ USB_DEVICE(0x13d3, 0x3564), .driver_info = BTUSB_MEDIATEK |
BTUSB_WIDEBAND_SPEECH |
BTUSB_VALID_LE_STATES },
--- a/drivers/bluetooth/btusb.c
+++ b/drivers/bluetooth/btusb.c
-@@ -451,6 +451,9 @@ static const struct usb_device_id blackl
+@@ -455,6 +455,9 @@ static const struct usb_device_id blackl
BTUSB_VALID_LE_STATES },
/* Additional MediaTek MT7921 Bluetooth devices */
--- a/drivers/bluetooth/btusb.c
+++ b/drivers/bluetooth/btusb.c
-@@ -469,6 +469,9 @@ static const struct usb_device_id blackl
+@@ -473,6 +473,9 @@ static const struct usb_device_id blackl
{ USB_DEVICE(0x0489, 0xe0cd), .driver_info = BTUSB_MEDIATEK |
BTUSB_WIDEBAND_SPEECH |
BTUSB_VALID_LE_STATES },
help
--- a/net/core/dev.c
+++ b/net/core/dev.c
-@@ -3588,6 +3588,11 @@ static int xmit_one(struct sk_buff *skb,
+@@ -3590,6 +3590,11 @@ static int xmit_one(struct sk_buff *skb,
if (dev_nit_active(dev))
dev_queue_xmit_nit(skb, dev);
--- a/net/core/sock.c
+++ b/net/core/sock.c
-@@ -3857,6 +3857,8 @@ static __net_initdata struct pernet_oper
+@@ -3866,6 +3866,8 @@ static __net_initdata struct pernet_oper
static int __init proto_init(void)
{
--- a/Makefile
+++ b/Makefile
-@@ -527,7 +527,7 @@ KBUILD_LDFLAGS_MODULE :=
+@@ -534,7 +534,7 @@ KBUILD_LDFLAGS_MODULE :=
KBUILD_LDFLAGS :=
CLANG_FLAGS :=
return !!nor->params->erase_map.uniform_erase_type;
}
-@@ -2391,6 +2393,7 @@ static int spi_nor_select_erase(struct s
+@@ -2400,6 +2402,7 @@ static int spi_nor_select_erase(struct s
{
struct spi_nor_erase_map *map = &nor->params->erase_map;
const struct spi_nor_erase_type *erase = NULL;
struct mtd_info *mtd = &nor->mtd;
u32 wanted_size = nor->info->sector_size;
int i;
-@@ -2423,8 +2426,9 @@ static int spi_nor_select_erase(struct s
+@@ -2432,8 +2435,9 @@ static int spi_nor_select_erase(struct s
*/
for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
if (map->erase_type[i].size) {
}
}
-@@ -2432,6 +2436,9 @@ static int spi_nor_select_erase(struct s
+@@ -2441,6 +2445,9 @@ static int spi_nor_select_erase(struct s
return -EINVAL;
mtd->erasesize = erase->size;
--- a/drivers/mtd/ubi/build.c
+++ b/drivers/mtd/ubi/build.c
-@@ -1184,6 +1184,73 @@ static struct mtd_info * __init open_mtd
+@@ -1191,6 +1191,73 @@ static struct mtd_info * __init open_mtd
return mtd;
}
static int __init ubi_init(void)
{
int err, i, k;
-@@ -1267,6 +1334,12 @@ static int __init ubi_init(void)
+@@ -1274,6 +1341,12 @@ static int __init ubi_init(void)
}
}
for (i = sizeof(struct ipt_entry);
i < e->target_offset;
i += m->u.match_size) {
-@@ -1223,12 +1260,15 @@ compat_copy_entry_to_user(struct ipt_ent
+@@ -1222,12 +1259,15 @@ compat_copy_entry_to_user(struct ipt_ent
compat_uint_t origsize;
const struct xt_entry_match *ematch;
int ret = 0;
cfg->fc_flags |= RTF_REJECT;
if (rtm->rtm_type == RTN_LOCAL)
-@@ -6300,6 +6331,8 @@ static int ip6_route_dev_notify(struct n
+@@ -6301,6 +6332,8 @@ static int ip6_route_dev_notify(struct n
#ifdef CONFIG_IPV6_MULTIPLE_TABLES
net->ipv6.ip6_prohibit_entry->dst.dev = dev;
net->ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(dev);
net->ipv6.ip6_blk_hole_entry->dst.dev = dev;
net->ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(dev);
#endif
-@@ -6311,6 +6344,7 @@ static int ip6_route_dev_notify(struct n
+@@ -6312,6 +6345,7 @@ static int ip6_route_dev_notify(struct n
in6_dev_put_clear(&net->ipv6.ip6_null_entry->rt6i_idev);
#ifdef CONFIG_IPV6_MULTIPLE_TABLES
in6_dev_put_clear(&net->ipv6.ip6_prohibit_entry->rt6i_idev);
in6_dev_put_clear(&net->ipv6.ip6_blk_hole_entry->rt6i_idev);
#endif
}
-@@ -6502,6 +6536,8 @@ static int __net_init ip6_route_net_init
+@@ -6503,6 +6537,8 @@ static int __net_init ip6_route_net_init
#ifdef CONFIG_IPV6_MULTIPLE_TABLES
net->ipv6.fib6_has_custom_rules = false;
net->ipv6.ip6_prohibit_entry = kmemdup(&ip6_prohibit_entry_template,
sizeof(*net->ipv6.ip6_prohibit_entry),
GFP_KERNEL);
-@@ -6512,11 +6548,21 @@ static int __net_init ip6_route_net_init
+@@ -6513,11 +6549,21 @@ static int __net_init ip6_route_net_init
ip6_template_metrics, true);
INIT_LIST_HEAD(&net->ipv6.ip6_prohibit_entry->rt6i_uncached);
net->ipv6.ip6_blk_hole_entry->dst.ops = &net->ipv6.ip6_dst_ops;
dst_init_metrics(&net->ipv6.ip6_blk_hole_entry->dst,
ip6_template_metrics, true);
-@@ -6543,6 +6589,8 @@ out:
+@@ -6544,6 +6590,8 @@ out:
return ret;
#ifdef CONFIG_IPV6_MULTIPLE_TABLES
out_ip6_prohibit_entry:
kfree(net->ipv6.ip6_prohibit_entry);
out_ip6_null_entry:
-@@ -6562,6 +6610,7 @@ static void __net_exit ip6_route_net_exi
+@@ -6563,6 +6611,7 @@ static void __net_exit ip6_route_net_exi
kfree(net->ipv6.ip6_null_entry);
#ifdef CONFIG_IPV6_MULTIPLE_TABLES
kfree(net->ipv6.ip6_prohibit_entry);
kfree(net->ipv6.ip6_blk_hole_entry);
#endif
dst_entries_destroy(&net->ipv6.ip6_dst_ops);
-@@ -6645,6 +6694,9 @@ void __init ip6_route_init_special_entri
+@@ -6646,6 +6695,9 @@ void __init ip6_route_init_special_entri
init_net.ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev);
init_net.ipv6.ip6_blk_hole_entry->dst.dev = init_net.loopback_dev;
init_net.ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev);
__u8 inner_protocol_type:1;
--- a/net/core/dev.c
+++ b/net/core/dev.c
-@@ -6063,6 +6063,9 @@ static enum gro_result dev_gro_receive(s
+@@ -6065,6 +6065,9 @@ static enum gro_result dev_gro_receive(s
int same_flow;
int grow;
if (netif_elide_gro(skb->dev))
goto normal;
-@@ -8077,6 +8080,48 @@ static void __netdev_adjacent_dev_unlink
+@@ -8079,6 +8082,48 @@ static void __netdev_adjacent_dev_unlink
&upper_dev->adj_list.lower);
}
static int __netdev_upper_dev_link(struct net_device *dev,
struct net_device *upper_dev, bool master,
void *upper_priv, void *upper_info,
-@@ -8128,6 +8173,7 @@ static int __netdev_upper_dev_link(struc
+@@ -8130,6 +8175,7 @@ static int __netdev_upper_dev_link(struc
if (ret)
return ret;
ret = call_netdevice_notifiers_info(NETDEV_CHANGEUPPER,
&changeupper_info.info);
ret = notifier_to_errno(ret);
-@@ -8224,6 +8270,7 @@ static void __netdev_upper_dev_unlink(st
+@@ -8226,6 +8272,7 @@ static void __netdev_upper_dev_unlink(st
__netdev_adjacent_dev_unlink_neighbour(dev, upper_dev);
call_netdevice_notifiers_info(NETDEV_CHANGEUPPER,
&changeupper_info.info);
-@@ -9043,6 +9090,7 @@ int dev_set_mac_address(struct net_devic
+@@ -9045,6 +9092,7 @@ int dev_set_mac_address(struct net_devic
if (err)
return err;
dev->addr_assign_type = NET_ADDR_SET;
err_put_device:
put_device(&op->dev);
return ret;
-@@ -1157,7 +1155,12 @@ static int tsens_probe(struct platform_d
+@@ -1163,7 +1161,12 @@ static int tsens_probe(struct platform_d
}
}
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -293,6 +293,25 @@
+@@ -320,6 +320,25 @@
#reset-cells = <0x1>;
};
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -212,7 +212,7 @@
+@@ -239,7 +239,7 @@
status = "disabled";
};
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -430,6 +430,21 @@
+@@ -457,6 +457,21 @@
status = "disabled";
};
+ #clock-cells = <1>;
clocks = <&gcc GCC_USB1_PIPE_CLK>;
clock-names = "pipe0";
- clock-output-names = "gcc_usb1_pipe_clk_src";
+ clock-output-names = "usb3phy_1_cc_pipe_clk";
@@ -134,7 +134,6 @@
ssphy_0: phy@78000 {
compatible = "qcom,ipq8074-qmp-usb3-phy";
+ #clock-cells = <1>;
clocks = <&gcc GCC_USB0_PIPE_CLK>;
clock-names = "pipe0";
- clock-output-names = "gcc_usb0_pipe_clk_src";
+ clock-output-names = "usb3phy_0_cc_pipe_clk";
+++ /dev/null
-From a9ab8f5de2fc752e37918cfd5dcd16d625d9ecb2 Mon Sep 17 00:00:00 2001
-From: Shawn Guo <shawn.guo@linaro.org>
-Date: Wed, 29 Sep 2021 11:42:51 +0800
-Subject: [PATCH] arm64: dts: qcom: Fix IPQ8074 PCIe PHY nodes
-
-IPQ8074 PCIe PHY nodes are broken in the many ways:
-
-- '#address-cells', '#size-cells' and 'ranges' are missing.
-- Child phy/lane node is missing, and the child properties like
- '#phy-cells' and 'clocks' are mistakenly put into parent node.
-- The clocks properties for parent node are missing.
-
-Fix them to get the nodes comply with the bindings schema.
-
-Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20210929034253.24570-9-shawn.guo@linaro.org
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 46 +++++++++++++++++++++------
- 1 file changed, 36 insertions(+), 10 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -174,34 +174,60 @@
- status = "disabled";
- };
-
-- pcie_phy0: phy@86000 {
-+ pcie_qmp0: phy@86000 {
- compatible = "qcom,ipq8074-qmp-pcie-phy";
- reg = <0x00086000 0x1000>;
-- #phy-cells = <0>;
-- clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
-- clock-names = "pipe_clk";
-- clock-output-names = "pcie20_phy0_pipe_clk";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges;
-
-+ clocks = <&gcc GCC_PCIE0_AUX_CLK>,
-+ <&gcc GCC_PCIE0_AHB_CLK>;
-+ clock-names = "aux", "cfg_ahb";
- resets = <&gcc GCC_PCIE0_PHY_BCR>,
- <&gcc GCC_PCIE0PHY_PHY_BCR>;
- reset-names = "phy",
- "common";
- status = "disabled";
-+
-+ pcie_phy0: phy@86200 {
-+ reg = <0x86200 0x16c>,
-+ <0x86400 0x200>,
-+ <0x86800 0x4f4>;
-+ #phy-cells = <0>;
-+ #clock-cells = <0>;
-+ clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
-+ clock-names = "pipe0";
-+ clock-output-names = "pcie_0_pipe_clk";
-+ };
- };
-
-- pcie_phy1: phy@8e000 {
-+ pcie_qmp1: phy@8e000 {
- compatible = "qcom,ipq8074-qmp-pcie-phy";
- reg = <0x0008e000 0x1000>;
-- #phy-cells = <0>;
-- clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
-- clock-names = "pipe_clk";
-- clock-output-names = "pcie20_phy1_pipe_clk";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges;
-
-+ clocks = <&gcc GCC_PCIE1_AUX_CLK>,
-+ <&gcc GCC_PCIE1_AHB_CLK>;
-+ clock-names = "aux", "cfg_ahb";
- resets = <&gcc GCC_PCIE1_PHY_BCR>,
- <&gcc GCC_PCIE1PHY_PHY_BCR>;
- reset-names = "phy",
- "common";
- status = "disabled";
-+
-+ pcie_phy1: phy@8e200 {
-+ reg = <0x8e200 0x16c>,
-+ <0x8e400 0x200>,
-+ <0x8e800 0x4f4>;
-+ #phy-cells = <0>;
-+ #clock-cells = <0>;
-+ clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
-+ clock-names = "pipe0";
-+ clock-output-names = "pcie_1_pipe_clk";
-+ };
- };
-
- prng: rng@e3000 {
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -230,6 +230,18 @@
+@@ -231,6 +231,18 @@
};
};
firmware {
scm {
compatible = "qcom,scm-ipq8074", "qcom,scm";
-@@ -331,6 +345,12 @@
+@@ -332,6 +346,12 @@
#reset-cells = <0x1>;
};
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -634,9 +634,18 @@
+@@ -635,9 +635,18 @@
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -670,7 +670,6 @@
+@@ -671,7 +671,6 @@
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0x0b120000 0x1000>;
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -471,8 +471,8 @@
+@@ -472,8 +472,8 @@
<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
clock-names = "iface", "core";
clock-frequency = <400000>;
pinctrl-0 = <&i2c_0_pins>;
pinctrl-names = "default";
status = "disabled";
-@@ -488,8 +488,8 @@
+@@ -489,8 +489,8 @@
<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
clock-names = "iface", "core";
clock-frequency = <100000>;
status = "disabled";
};
-@@ -503,8 +503,8 @@
+@@ -504,8 +504,8 @@
<&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
clock-names = "iface", "core";
clock-frequency = <400000>;
status = "disabled";
};
-@@ -518,8 +518,8 @@
+@@ -519,8 +519,8 @@
<&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
clock-names = "iface", "core";
clock-frequency = <100000>;
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -467,9 +467,9 @@
+@@ -468,9 +468,9 @@
#size-cells = <0>;
reg = <0x078b6000 0x600>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>;
dmas = <&blsp_dma 14>, <&blsp_dma 15>;
dma-names = "tx", "rx";
-@@ -484,9 +484,9 @@
+@@ -485,9 +485,9 @@
#size-cells = <0>;
reg = <0x078b7000 0x600>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <100000>;
dmas = <&blsp_dma 16>, <&blsp_dma 17>;
dma-names = "tx", "rx";
-@@ -499,9 +499,9 @@
+@@ -500,9 +500,9 @@
#size-cells = <0>;
reg = <0x78b9000 0x600>;
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>;
dmas = <&blsp_dma 20>, <&blsp_dma 21>;
dma-names = "tx", "rx";
-@@ -514,9 +514,9 @@
+@@ -515,9 +515,9 @@
#size-cells = <0>;
reg = <0x078ba000 0x600>;
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -578,7 +578,7 @@
+@@ -579,7 +579,7 @@
resets = <&gcc GCC_USB0_BCR>;
status = "disabled";
compatible = "snps,dwc3";
reg = <0x8a00000 0xcd00>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
-@@ -618,7 +618,7 @@
+@@ -619,7 +619,7 @@
resets = <&gcc GCC_USB1_BCR>;
status = "disabled";
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -553,7 +553,7 @@
+@@ -554,7 +554,7 @@
};
usb_0: usb@8af8800 {
reg = <0x08af8800 0x400>;
#address-cells = <1>;
#size-cells = <1>;
-@@ -593,7 +593,7 @@
+@@ -594,7 +594,7 @@
};
usb_1: usb@8cf8800 {
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -563,8 +563,8 @@
+@@ -564,8 +564,8 @@
<&gcc GCC_USB0_MASTER_CLK>,
<&gcc GCC_USB0_SLEEP_CLK>,
<&gcc GCC_USB0_MOCK_UTMI_CLK>;
"sleep",
"mock_utmi";
-@@ -603,8 +603,8 @@
+@@ -604,8 +604,8 @@
<&gcc GCC_USB1_MASTER_CLK>,
<&gcc GCC_USB1_SLEEP_CLK>,
<&gcc GCC_USB1_MOCK_UTMI_CLK>;
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -375,7 +375,7 @@
+@@ -376,7 +376,7 @@
cell-index = <0>;
};
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -384,10 +384,10 @@
+@@ -385,10 +385,10 @@
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -347,6 +347,7 @@
+@@ -348,6 +348,7 @@
compatible = "qcom,gcc-ipq8074";
reg = <0x01800000 0x80000>;
#clock-cells = <0x1>;
#reset-cells = <0x1>;
};
-@@ -575,6 +576,8 @@
+@@ -576,6 +577,8 @@
<133330000>,
<19200000>;
resets = <&gcc GCC_USB0_BCR>;
status = "disabled";
-@@ -615,6 +618,8 @@
+@@ -616,6 +619,8 @@
<133330000>,
<19200000>;
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -653,14 +653,6 @@
+@@ -654,14 +654,6 @@
};
};
watchdog: watchdog@b017000 {
compatible = "qcom,kpss-wdt";
reg = <0xb017000 0x1000>;
-@@ -852,4 +844,12 @@
+@@ -857,4 +849,12 @@
status = "disabled";
};
};
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -389,6 +389,7 @@
+@@ -390,6 +390,7 @@
<&gcc GCC_SDCC1_APPS_CLK>,
<&xo>;
clock-names = "iface", "core", "xo";
+ #clock-cells = <0>;
clocks = <&gcc GCC_USB1_PIPE_CLK>;
clock-names = "pipe0";
- clock-output-names = "gcc_usb1_pipe_clk_src";
+ clock-output-names = "usb3phy_1_cc_pipe_clk";
@@ -173,7 +173,7 @@
<0x00078800 0x1f8>, /* PCS */
<0x00078600 0x044>; /* PCS misc*/
+ #clock-cells = <0>;
clocks = <&gcc GCC_USB0_PIPE_CLK>;
clock-names = "pipe0";
- clock-output-names = "gcc_usb0_pipe_clk_src";
+ clock-output-names = "usb3phy_0_cc_pipe_clk";
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -662,6 +662,14 @@
+@@ -663,6 +663,14 @@
timeout-sec = <30>;
};
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -383,7 +383,7 @@
+@@ -384,7 +384,7 @@
sdhc_1: mmc@7824900 {
compatible = "qcom,sdhci-msm-v4";
reg = <0x7824900 0x500>, <0x7824000 0x800>;
+++ /dev/null
-From 8f63346a74c8b3e37ffab2c7a2ddb3c08793dcc2 Mon Sep 17 00:00:00 2001
-From: Johan Hovold <johan+linaro@kernel.org>
-Date: Thu, 15 Sep 2022 16:34:30 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq8074: fix PCIe PHY serdes size
-
-The size of the PCIe PHY serdes register region is 0x1c4 and the
-corresponding 'reg' property should specifically not include the
-adjacent regions that are defined in the child node (e.g. tx and rx).
-
-Fixes: 33057e1672fe ("ARM: dts: ipq8074: Add pcie nodes")
-Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20220915143431.19842-1-johan+linaro@kernel.org
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -199,7 +199,7 @@
-
- pcie_qmp0: phy@86000 {
- compatible = "qcom,ipq8074-qmp-pcie-phy";
-- reg = <0x00086000 0x1000>;
-+ reg = <0x00086000 0x1c4>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-@@ -227,7 +227,7 @@
-
- pcie_qmp1: phy@8e000 {
- compatible = "qcom,ipq8074-qmp-pcie-phy";
-- reg = <0x0008e000 0x1000>;
-+ reg = <0x0008e000 0x1c4>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -674,6 +674,14 @@
+@@ -675,6 +675,14 @@
#mbox-cells = <1>;
};
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -668,7 +668,7 @@
+@@ -669,7 +669,7 @@
apcs_glb: mailbox@b111000 {
compatible = "qcom,ipq8074-apcs-apps-global";
.max_sensors = 11,
--- a/drivers/thermal/qcom/tsens-v0_1.c
+++ b/drivers/thermal/qcom/tsens-v0_1.c
-@@ -539,6 +539,7 @@ static int calibrate_9607(struct tsens_p
+@@ -549,6 +549,7 @@ static int __init init_8939(struct tsens
static struct tsens_features tsens_v0_1_feat = {
.ver_major = VER_0_1,
.crit_int = 0,
.max_sensors = 11,
--- a/drivers/thermal/qcom/tsens-v1.c
+++ b/drivers/thermal/qcom/tsens-v1.c
-@@ -302,6 +302,7 @@ static int calibrate_8976(struct tsens_p
+@@ -273,6 +273,7 @@ static int calibrate_8976(struct tsens_p
static struct tsens_features tsens_v1_feat = {
.ver_major = VER_1_X,
.crit_int = 0,
static int tsens_set_trips(void *_sensor, int low, int high)
{
struct tsens_sensor *s = _sensor;
-@@ -1075,13 +1096,18 @@ static int tsens_register(struct tsens_p
+@@ -1081,13 +1102,18 @@ static int tsens_register(struct tsens_p
tsens_mC_to_hw(priv->sensor, 0));
}
struct tsens_plat_data data_8960 = {
--- a/drivers/thermal/qcom/tsens-v0_1.c
+++ b/drivers/thermal/qcom/tsens-v0_1.c
-@@ -543,6 +543,8 @@ static struct tsens_features tsens_v0_1_
+@@ -553,6 +553,8 @@ static struct tsens_features tsens_v0_1_
.adc = 1,
.srot_split = 1,
.max_sensors = 11,
static const struct reg_field tsens_v0_1_regfields[MAX_REGFIELDS] = {
--- a/drivers/thermal/qcom/tsens-v1.c
+++ b/drivers/thermal/qcom/tsens-v1.c
-@@ -306,6 +306,8 @@ static struct tsens_features tsens_v1_fe
+@@ -277,6 +277,8 @@ static struct tsens_features tsens_v1_fe
.adc = 1,
.srot_split = 1,
.max_sensors = 11,
--- a/drivers/thermal/qcom/tsens.h
+++ b/drivers/thermal/qcom/tsens.h
@@ -599,6 +599,6 @@ extern struct tsens_plat_data data_8916,
- extern struct tsens_plat_data data_tsens_v1, data_8976;
+ extern struct tsens_plat_data data_tsens_v1, data_8976, data_8956;
/* TSENS v2 targets */
-extern struct tsens_plat_data data_8996, data_tsens_v2;
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -273,6 +273,16 @@
+@@ -274,6 +274,16 @@
status = "disabled";
};
cryptobam: dma-controller@704000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x00704000 0x20000>;
-@@ -873,4 +883,90 @@
+@@ -878,4 +888,90 @@
<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -679,6 +679,8 @@
+@@ -680,6 +680,8 @@
apcs_glb: mailbox@b111000 {
compatible = "qcom,ipq8074-apcs-apps-global";
reg = <0x0b111000 0x1000>;
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -360,9 +360,11 @@
+@@ -361,9 +361,11 @@
gcc: gcc@1800000 {
compatible = "qcom,gcc-ipq8074";
reg = <0x01800000 0x80000>;
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -317,35 +317,35 @@
+@@ -318,35 +318,35 @@
interrupt-controller;
#interrupt-cells = <0x2>;
+++ /dev/null
-From 075b3ca8a4223742abc6da2406afe206d97f3d52 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Wed, 16 Nov 2022 22:48:33 +0100
-Subject: [PATCH] arm64: dts: qcom: ipq8074: fix Gen2 PCIe QMP PHY
-
-Serdes register space sizes are incorrect, update them to match the
-actual sizes from downstream QCA 5.4 kernel.
-
-Fixes: 942bcd33ed45 ("arm64: dts: qcom: Fix IPQ8074 PCIe PHY nodes")
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -277,9 +277,9 @@
- status = "disabled";
-
- pcie_phy1: phy@8e200 {
-- reg = <0x8e200 0x16c>,
-+ reg = <0x8e200 0x130>,
- <0x8e400 0x200>,
-- <0x8e800 0x4f4>;
-+ <0x8e800 0x1f8>;
- #phy-cells = <0>;
- #clock-cells = <0>;
- clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
+++ /dev/null
-From 6f49bc0ee169c90b5c26a1e3d27a4728142f0ddb Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Wed, 16 Nov 2022 22:48:34 +0100
-Subject: [PATCH] arm64: dts: qcom: ipq8074: fix Gen3 PCIe QMP PHY
-
-IPQ8074 comes in 2 silicon versions:
-* v1 with 2x Gen2 PCIe ports and QMP PHY-s
-* v2 with 1x Gen3 and 1x Gen2 PCIe ports and QMP PHY-s
-
-v2 is the final and production version that is actually supported by the
-kernel, however it looks like PCIe related nodes were added for the v1 SoC.
-
-Now that we have Gen3 QMP PHY support, we can start fixing the PCIe support
-by fixing the Gen3 QMP PHY node first.
-
-Change the compatible to the Gen3 QMP PHY, correct the register space start
-and size, add the missing misc PCS register space.
-
-Fixes: 33057e1672fe ("ARM: dts: ipq8074: Add pcie nodes")
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 15 ++++++++-------
- 1 file changed, 8 insertions(+), 7 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -232,9 +232,9 @@
- status = "disabled";
- };
-
-- pcie_qmp0: phy@86000 {
-- compatible = "qcom,ipq8074-qmp-pcie-phy";
-- reg = <0x00086000 0x1c4>;
-+ pcie_qmp0: phy@84000 {
-+ compatible = "qcom,ipq8074-qmp-gen3-pcie-phy";
-+ reg = <0x00084000 0x1bc>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-@@ -248,10 +248,11 @@
- "common";
- status = "disabled";
-
-- pcie_phy0: phy@86200 {
-- reg = <0x86200 0x16c>,
-- <0x86400 0x200>,
-- <0x86800 0x4f4>;
-+ pcie_phy0: phy@84200 {
-+ reg = <0x84200 0x16c>,
-+ <0x84400 0x200>,
-+ <0x84800 0x1f0>,
-+ <0x84c00 0xf4>;
- #phy-cells = <0>;
- #clock-cells = <0>;
- clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
+++ /dev/null
-From 52a48e8ed546339122983329410be801a2b9adf5 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Wed, 16 Nov 2022 22:48:35 +0100
-Subject: [PATCH] arm64: dts: qcom: ipq8074: correct Gen2 PCIe ranges
-
-Current ranges property set in Gen2 PCIe node is incorrect, replace it
-with the downstream 5.4 QCA kernel value.
-
-Fixes: 33057e1672fe ("ARM: dts: ipq8074: Add pcie nodes")
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -808,9 +808,9 @@
- phy-names = "pciephy";
-
- ranges = <0x81000000 0 0x10200000 0x10200000
-- 0 0x100000 /* downstream I/O */
-- 0x82000000 0 0x10300000 0x10300000
-- 0 0xd00000>; /* non-prefetchable memory */
-+ 0 0x10000>, /* downstream I/O */
-+ <0x82000000 0 0x10220000 0x10220000
-+ 0 0xfde0000>; /* non-prefetchable memory */
-
- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+++ /dev/null
-From 625c90a8266e432ea15e109123ca941062b63f76 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Wed, 16 Nov 2022 22:48:40 +0100
-Subject: [PATCH] arm64: dts: qcom: ipq8074: fix Gen3 PCIe node
-
-IPQ8074 comes in 2 silicon versions:
-* v1 with 2x Gen2 PCIe ports and QMP PHY-s
-* v2 with 1x Gen3 and 1x Gen2 PCIe ports and QMP PHY-s
-
-v2 is the final and production version that is actually supported by the
-kernel, however it looks like PCIe related nodes were added for the v1 SoC.
-
-Finish the PCIe fixup by using the correct compatible, adding missing ATU
-register space, declaring max-link-speed, use correct ranges, add missing
-clocks and resets.
-
-Fixes: 33057e1672fe ("ARM: dts: ipq8074: Add pcie nodes")
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 30 +++++++++++++++------------
- 1 file changed, 17 insertions(+), 13 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -854,16 +854,18 @@
- };
-
- pcie0: pci@20000000 {
-- compatible = "qcom,pcie-ipq8074";
-+ compatible = "qcom,pcie-ipq8074-gen3";
- reg = <0x20000000 0xf1d>,
- <0x20000f20 0xa8>,
-- <0x00080000 0x2000>,
-+ <0x20001000 0x1000>,
-+ <0x00080000 0x4000>,
- <0x20100000 0x1000>;
-- reg-names = "dbi", "elbi", "parf", "config";
-+ reg-names = "dbi", "elbi", "atu", "parf", "config";
- device_type = "pci";
- linux,pci-domain = <0>;
- bus-range = <0x00 0xff>;
- num-lanes = <1>;
-+ max-link-speed = <3>;
- #address-cells = <3>;
- #size-cells = <2>;
-
-@@ -871,9 +873,9 @@
- phy-names = "pciephy";
-
- ranges = <0x81000000 0 0x20200000 0x20200000
-- 0 0x100000 /* downstream I/O */
-- 0x82000000 0 0x20300000 0x20300000
-- 0 0xd00000>; /* non-prefetchable memory */
-+ 0 0x10000>, /* downstream I/O */
-+ <0x82000000 0 0x20220000 0x20220000
-+ 0 0xfde0000>; /* non-prefetchable memory */
-
- interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
-@@ -891,28 +893,30 @@
- clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
- <&gcc GCC_PCIE0_AXI_M_CLK>,
- <&gcc GCC_PCIE0_AXI_S_CLK>,
-- <&gcc GCC_PCIE0_AHB_CLK>,
-- <&gcc GCC_PCIE0_AUX_CLK>;
--
-+ <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
-+ <&gcc GCC_PCIE0_RCHNG_CLK>;
- clock-names = "iface",
- "axi_m",
- "axi_s",
-- "ahb",
-- "aux";
-+ "axi_bridge",
-+ "rchng";
-+
- resets = <&gcc GCC_PCIE0_PIPE_ARES>,
- <&gcc GCC_PCIE0_SLEEP_ARES>,
- <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
- <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
- <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
- <&gcc GCC_PCIE0_AHB_ARES>,
-- <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
-+ <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
-+ <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
- reset-names = "pipe",
- "sleep",
- "sticky",
- "axi_m",
- "axi_s",
- "ahb",
-- "axi_m_sticky";
-+ "axi_m_sticky",
-+ "axi_s_sticky";
- status = "disabled";
- };
- };
+++ /dev/null
-From 0311903940046649e20bd23bca837169eb4525dc Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Wed, 16 Nov 2022 22:48:41 +0100
-Subject: [PATCH] arm64: dts: qcom: ipq8074: correct PCIe QMP PHY output clock
- names
-
-Current PCIe QMP PHY output name were changed in ("arm64: dts: qcom: Fix
-IPQ8074 PCIe PHY nodes") however it did not account for the fact that GCC
-driver is relying on the old names to match them as they are being used as
-the parent for the gcc_pcie0_pipe_clk and gcc_pcie1_pipe_clk.
-
-This broke parenting as GCC could not find the parent clock, so fix it by
-changing to the names that driver is expecting.
-
-Fixes: 942bcd33ed45 ("arm64: dts: qcom: Fix IPQ8074 PCIe PHY nodes")
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -257,7 +257,7 @@
- #clock-cells = <0>;
- clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
- clock-names = "pipe0";
-- clock-output-names = "pcie_0_pipe_clk";
-+ clock-output-names = "pcie20_phy0_pipe_clk";
- };
- };
-
-@@ -285,7 +285,7 @@
- #clock-cells = <0>;
- clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
- clock-names = "pipe0";
-- clock-output-names = "pcie_1_pipe_clk";
-+ clock-output-names = "pcie20_phy1_pipe_clk";
- };
- };
-
+++ /dev/null
-From 1bfcec16a591622b4993c043e6cc4d07f3690767 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Sun, 8 Jan 2023 13:39:55 +0100
-Subject: [PATCH] arm64: dts: qcom: ipq8074: correct USB3 QMP PHY-s clock
- output names
-
-It seems that clock-output-names for the USB3 QMP PHY-s where set without
-actually checking what is the GCC clock driver expecting, so clock core
-could never actually find the parents for usb0_pipe_clk_src and
-usb1_pipe_clk_src clocks in the GCC driver.
-
-So, correct the names to be what the driver expects so that parenting
-works.
-
-Before:
-gcc_usb0_pipe_clk_src 0 0 0 125000000 0 0 50000 Y
-gcc_usb1_pipe_clk_src 0 0 0 125000000 0 0 50000 Y
-
-After:
- usb3phy_0_cc_pipe_clk 1 1 0 125000000 0 0 50000 Y
- usb0_pipe_clk_src 1 1 0 125000000 0 0 50000 Y
- gcc_usb0_pipe_clk 1 1 0 125000000 0 0 50000 Y
- usb3phy_1_cc_pipe_clk 1 1 0 125000000 0 0 50000 Y
- usb1_pipe_clk_src 1 1 0 125000000 0 0 50000 Y
- gcc_usb1_pipe_clk 1 1 0 125000000 0 0 50000 Y
-
-Fixes: 5e09bc51d07b ("arm64: dts: ipq8074: enable USB support")
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -263,7 +263,7 @@
- #clock-cells = <0>;
- clocks = <&gcc GCC_USB1_PIPE_CLK>;
- clock-names = "pipe0";
-- clock-output-names = "gcc_usb1_pipe_clk_src";
-+ clock-output-names = "usb3phy_1_cc_pipe_clk";
- };
- };
-
-@@ -306,7 +306,7 @@
- #clock-cells = <0>;
- clocks = <&gcc GCC_USB0_PIPE_CLK>;
- clock-names = "pipe0";
-- clock-output-names = "gcc_usb0_pipe_clk_src";
-+ clock-output-names = "usb3phy_0_cc_pipe_clk";
- };
- };
-
(transaction layer end-to-end CRC checking).
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
-@@ -1480,6 +1480,8 @@ void pci_walk_bus(struct pci_bus *top, i
+@@ -1481,6 +1481,8 @@ void pci_walk_bus(struct pci_bus *top, i
void *userdata);
int pci_cfg_space_size(struct pci_dev *dev);
unsigned char pci_bus_max_busnr(struct pci_bus *bus);
--- a/drivers/mtd/spi-nor/spansion.c
+++ b/drivers/mtd/spi-nor/spansion.c
-@@ -227,7 +227,7 @@ static const struct flash_info spansion_
+@@ -232,7 +232,7 @@ static const struct flash_info spansion_
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
USE_CLSR) },
{ "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256,
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -558,6 +558,7 @@
+@@ -559,6 +559,7 @@
compatible = "mediatek,mt7622-nor",
"mediatek,mt8173-nor";
reg = <0 0x11014000 0 0xe0>;
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
-@@ -530,6 +530,16 @@ config SPI_MTK_NOR
+@@ -529,6 +529,16 @@ config SPI_MTK_NOR
SPI interface as well as several SPI NOR specific instructions
via SPI MEM interface.
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -552,6 +552,18 @@
+@@ -553,6 +553,18 @@
status = "disabled";
};
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -941,6 +941,7 @@
+@@ -942,6 +942,7 @@
clock-names = "hsdma";
power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
#dma-cells = <1>;
&pio {
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -808,75 +808,83 @@
+@@ -809,75 +809,83 @@
#reset-cells = <1>;
};
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -848,6 +848,12 @@
+@@ -849,6 +849,12 @@
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
pcie1: pcie@1a145000 {
-@@ -886,6 +892,12 @@
+@@ -887,6 +893,12 @@
#address-cells = <0>;
#interrupt-cells = <1>;
};
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -836,6 +836,9 @@
+@@ -837,6 +837,9 @@
bus-range = <0x00 0xff>;
ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
status = "disabled";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
-@@ -880,6 +883,9 @@
+@@ -881,6 +884,9 @@
bus-range = <0x00 0xff>;
ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
status = "disabled";
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
-@@ -2188,6 +2188,15 @@ config SGI_MFD_IOC3
+@@ -2189,6 +2189,15 @@ config SGI_MFD_IOC3
If you have an SGI Origin, Octane, or a PCI IOC3 card,
then say Y. Otherwise say N.
#include <linux/platform_data/x86/apple.h>
#include <linux/pm_runtime.h>
#include <linux/suspend.h>
-@@ -5831,3 +5832,34 @@ static void nvidia_ion_ahci_fixup(struct
+@@ -5854,3 +5855,34 @@ static void nvidia_ion_ahci_fixup(struct
pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING;
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup);
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
-@@ -3098,6 +3098,7 @@ int spi_nor_scan(struct spi_nor *nor, co
+@@ -3107,6 +3107,7 @@ int spi_nor_scan(struct spi_nor *nor, co
struct device *dev = nor->dev;
struct mtd_info *mtd = &nor->mtd;
struct device_node *np = spi_nor_get_flash_node(nor);
int ret;
int i;
-@@ -3152,7 +3153,12 @@ int spi_nor_scan(struct spi_nor *nor, co
+@@ -3161,7 +3162,12 @@ int spi_nor_scan(struct spi_nor *nor, co
if (ret)
return ret;
--- a/drivers/media/usb/uvc/uvc_driver.c
+++ b/drivers/media/usb/uvc/uvc_driver.c
-@@ -3164,6 +3164,18 @@ static const struct usb_device_id uvc_id
+@@ -3152,6 +3152,18 @@ static const struct usb_device_id uvc_id
.bInterfaceSubClass = 1,
.bInterfaceProtocol = 0,
.driver_info = UVC_INFO_META(V4L2_META_FMT_D4XX) },
{ USB_INTERFACE_INFO(USB_CLASS_VIDEO, 1, UVC_PC_PROTOCOL_15) },
--- a/drivers/media/usb/uvc/uvc_status.c
+++ b/drivers/media/usb/uvc/uvc_status.c
-@@ -223,6 +223,7 @@ static void uvc_status_complete(struct u
+@@ -224,6 +224,7 @@ static void uvc_status_complete(struct u
if (uvc_event_control(urb, status, len))
/* The URB will be resubmitted in work context. */
return;
break;
}
-@@ -271,6 +272,7 @@ int uvc_status_init(struct uvc_device *d
+@@ -272,6 +273,7 @@ int uvc_status_init(struct uvc_device *d
}
pipe = usb_rcvintpipe(dev->udev, ep->desc.bEndpointAddress);
/* Mark the buffer as done if the EOF marker is set. */
if (data[1] & UVC_STREAM_EOF && buf->bytesused != 0) {
uvc_dbg(stream->dev, FRAME, "Frame complete (EOF found)\n");
-@@ -1799,6 +1944,8 @@ static int uvc_init_video_isoc(struct uv
+@@ -1801,6 +1946,8 @@ static int uvc_init_video_isoc(struct uv
if (npackets == 0)
return -ENOMEM;
for_each_uvc_urb(uvc_urb, stream) {
--- a/drivers/media/usb/uvc/uvcvideo.h
+++ b/drivers/media/usb/uvc/uvcvideo.h
-@@ -209,7 +209,9 @@
- #define UVC_QUIRK_RESTORE_CTRLS_ON_INIT 0x00000400
+@@ -210,6 +210,8 @@
#define UVC_QUIRK_FORCE_Y8 0x00000800
#define UVC_QUIRK_FORCE_BPP 0x00001000
--
-+#define UVC_QUIRK_MOTION 0x00001000
-+#define UVC_QUIRK_SINGLE_ISO 0x00002000
-+
+ #define UVC_QUIRK_WAKE_AUTOSUSPEND 0x00002000
++#define UVC_QUIRK_MOTION 0x00004000
++#define UVC_QUIRK_SINGLE_ISO 0x00008000
+
/* Format flags */
#define UVC_FMT_FLAG_COMPRESSED 0x00000001
- #define UVC_FMT_FLAG_STREAM 0x00000002
-@@ -700,6 +702,7 @@ struct uvc_device {
+@@ -701,6 +703,7 @@ struct uvc_device {
u8 *status;
struct input_dev *input;
char input_phys[64];
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
-@@ -719,6 +719,12 @@ config SPI_QCOM_GENI
+@@ -718,6 +718,12 @@ config SPI_QCOM_GENI
This driver can also be built as a module. If so, the module
will be called spi-geni-qcom.
projects / openwrt / staging / thess.git / commitdiff