arm, davinci: add PLL0 prediv to da850 lowlevel setup

The OMAP-L138 has a pre-divider available on PLL0.

Add support to da850_lowlevel.c for configuring PLL0's pre-divider. This is
to achieve certain OPP's -- e.g. the 372MHz OPP used also by Linux.

Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca>
Cc: Christian Riesch <christian.riesch@omicron.at>
CC: Heiko Schocher <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Tom Rini <tom.rini@gmail.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Heiko Schocher <hs@denx.de>
Acked-by: Christian Riesch <christian.riesch@omicron.at>

diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
index a532f8ab6063270c16aed1504b14fc5c94319159..eec06bc54d572f68f944a24b22fd933fb69860eb 100644 (file)
--- a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
+++ b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
@@ -85,6 +85,13 @@ int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
        /* Enable the PLL from Disable Mode PLLDIS bit to 0 */
        clrbits_le32(&reg->pllctl, PLLCTL_PLLDIS);
 
+#if defined(CONFIG_SYS_DA850_PLL0_PREDIV)
+       /* program the prediv */
+       if (reg == davinci_pllc0_regs && CONFIG_SYS_DA850_PLL0_PREDIV)
+               writel((PLL_DIVEN | CONFIG_SYS_DA850_PLL0_PREDIV),
+                       &reg->prediv);
+#endif
+
        /* Program the required multiplier value in PLLM */
        writel(pllmult, &reg->pllm);
 

diff --git a/arch/arm/include/asm/arch-davinci/pll_defs.h b/arch/arm/include/asm/arch-davinci/pll_defs.h
index f1396e31942430e8cf9348620993d8d69b5a1bdb..1c8d83fb5b5a1d06d91750ed1740429dbf65b699 100644 (file)
--- a/arch/arm/include/asm/arch-davinci/pll_defs.h
+++ b/arch/arm/include/asm/arch-davinci/pll_defs.h
@@ -68,7 +68,8 @@ struct dv_pll_regs {
 #define PLLCTL_RES_9   (1 << 8)
 #define PLLCTL_EXTCLKSRC       (1 << 9)
 
-#define PLL_POSTDEN    (1 << 15)
+#define PLL_DIVEN      (1 << 15)
+#define PLL_POSTDEN    PLL_DIVEN
 
 #define PLL_SCSCFG3_DIV45PENA  (1 << 2)
 #define PLL_SCSCFG3_EMA_CLKSRC (1 << 1)