ipq806x: add support for Qualcomm IPQ8062 SoC

This commit adds support for Qualcomm IPQ8062 SoC.
IPQ8062 is a lower clock variant of IPQ8064.

CPU and NSS clocks:
- CPU: 384 MHz - 1 GHz
- NSS: 110 MHz - 550 MHz

opp and l2 clock values are taken from WG2600HP3 GPL source code [1].

Due to a lack of devices, I didn't test the following features.
- SATA
- NAND flash memory controller
- SD
- USB
- GSBI2, GSBI7
- PCIE2
- GMAC0, GMAC3

Works properly:
- GSBI4 UART
- GSBI5 SPI
- GMAC1, GMAC2
- PCIE0, PCIE1
- MDIO0

Does not work properly:
- CPU SPC
  - This can cause a system hang. Same as IPQ8065.
    See 2336c2dbb1929837f7e42d4315c8073342a5b46b

[1] https://www.aterm.jp/function/wg2600hp3/appendix/opensource.html

Signed-off-by: Yanase Yuki <dev@zpc.sakura.ne.jp>

diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8062.dtsi b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8062.dtsi
new file mode 100644 (file)
index 0000000..caef2bc
--- /dev/null
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8062.dtsi
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include "qcom-ipq8064.dtsi"
+
+/ {
+       model = "Qualcomm IPQ8062";
+       compatible = "qcom,ipq8062", "qcom,ipq8064";
+
+       aliases {
+               serial0 = &gsbi4_serial;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       cpus {
+               qcom,l2 {
+                       qcom,l2-rates = <384000000 1000000000 1000000000>;
+                       qcom,l2-cpufreq = <384000000 600000000 1000000000>;
+                       qcom,l2-volt = <1100000 1100000 1100000>;
+               };
+       };
+
+       reserved-memory {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+
+               rsvd@41200000 {
+                       reg = <0x41200000 0x300000>;
+                       no-map;
+               };
+       };
+};
+
+&gsbi4 {
+       qcom,mode = <GSBI_PROT_I2C_UART>;
+       status = "okay";
+
+       serial@16340000 {
+               status = "okay";
+       };
+       /*
+       * The i2c device on gsbi4 should not be enabled.
+       * On ipq806x designs gsbi4 i2c is meant for exclusive
+       * RPM usage. Turning this on in kernel manifests as
+       * i2c failure for the RPM.
+       */
+};
+
+&opp_table0 {
+       /delete-node/opp-1200000000;
+       /delete-node/opp-1400000000;
+
+       opp-384000000 {
+               opp-microvolt-speed0-pvs0-v0 = <950000>;
+               opp-microvolt-speed0-pvs1-v0 = <900000>;
+               opp-microvolt-speed0-pvs2-v0 = <850000>;
+               opp-microvolt-speed0-pvs3-v0 = <800000>;
+       };
+
+       opp-600000000 {
+               opp-microvolt-speed0-pvs0-v0 = <1000000>;
+               opp-microvolt-speed0-pvs1-v0 = <950000>;
+               opp-microvolt-speed0-pvs2-v0 = <900000>;
+               opp-microvolt-speed0-pvs3-v0 = <850000>;
+       };
+
+       opp-800000000 {
+               opp-microvolt-speed0-pvs0-v0 = <1050000>;
+               opp-microvolt-speed0-pvs1-v0 = <1000000>;
+               opp-microvolt-speed0-pvs2-v0 = <950000>;
+               opp-microvolt-speed0-pvs3-v0 = <900000>;
+       };
+
+       opp-1000000000 {
+               opp-microvolt-speed0-pvs0-v0 = <1100000>;
+               opp-microvolt-speed0-pvs1-v0 = <1050000>;
+               opp-microvolt-speed0-pvs2-v0 = <1000000>;
+               opp-microvolt-speed0-pvs3-v0 = <950000>;
+       };
+};
+
+&pcie0 {
+       compatible = "qcom,pcie-ipq8064-v2";
+};
+
+&pcie1 {
+       compatible = "qcom,pcie-ipq8064-v2";
+};
+
+&pcie2 {
+       compatible = "qcom,pcie-ipq8064-v2";
+};
+
+&smb208_s2a {
+       regulator-max-microvolt = <1150000>;
+};
+
+&smb208_s2b {
+       regulator-max-microvolt = <1150000>;
+};