drm/i915/icl: Define AUX lane registers for Port A/B

This patch defines AUX lane registers for PORT_PCS_DW1,
PORT_TX_DW2, PORT_TX_DW4, PORT_TX_DW5 used during
dsi enabling.

v2: Review comments from Jani N:
    - Define _ICL_PORT_PCS_DW1_AUX_A for consistency
    - Three spaces for bitfield definition.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1530798591-2077-8-git-send-email-madhav.chauhan@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3ad5dcb21a7a0b29cb3a9ae7d5797ca9edfc0f67..0424e45f88dbc6f4c105b0ac54e689301ad54d15 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1796,16 +1796,22 @@ enum i915_power_well_id {
                                                    _CNL_PORT_PCS_DW1_LN0_D, \
                                                    _CNL_PORT_PCS_DW1_LN0_AE, \
                                                    _CNL_PORT_PCS_DW1_LN0_F))
+
 #define _ICL_PORT_PCS_DW1_GRP_A                0x162604
 #define _ICL_PORT_PCS_DW1_GRP_B                0x6C604
 #define _ICL_PORT_PCS_DW1_LN0_A                0x162804
 #define _ICL_PORT_PCS_DW1_LN0_B                0x6C804
+#define _ICL_PORT_PCS_DW1_AUX_A                0x162304
+#define _ICL_PORT_PCS_DW1_AUX_B                0x6c304
 #define ICL_PORT_PCS_DW1_GRP(port)     _MMIO_PORT(port,\
                                                   _ICL_PORT_PCS_DW1_GRP_A, \
                                                   _ICL_PORT_PCS_DW1_GRP_B)
 #define ICL_PORT_PCS_DW1_LN0(port)     _MMIO_PORT(port, \
                                                   _ICL_PORT_PCS_DW1_LN0_A, \
                                                   _ICL_PORT_PCS_DW1_LN0_B)
+#define ICL_PORT_PCS_DW1_AUX(port)     _MMIO_PORT(port, \
+                                                  _ICL_PORT_PCS_DW1_AUX_A, \
+                                                  _ICL_PORT_PCS_DW1_AUX_B)
 #define   COMMON_KEEPER_EN             (1 << 26)
 
 /* CNL Port TX registers */
@@ -1842,16 +1848,23 @@ enum i915_power_well_id {
 #define _ICL_PORT_TX_DW2_GRP_B         0x6C688
 #define _ICL_PORT_TX_DW2_LN0_A         0x162888
 #define _ICL_PORT_TX_DW2_LN0_B         0x6C888
+#define _ICL_PORT_TX_DW2_AUX_A         0x162388
+#define _ICL_PORT_TX_DW2_AUX_B         0x6c388
 #define ICL_PORT_TX_DW2_GRP(port)      _MMIO_PORT(port, \
                                                   _ICL_PORT_TX_DW2_GRP_A, \
                                                   _ICL_PORT_TX_DW2_GRP_B)
 #define ICL_PORT_TX_DW2_LN0(port)      _MMIO_PORT(port, \
                                                   _ICL_PORT_TX_DW2_LN0_A, \
                                                   _ICL_PORT_TX_DW2_LN0_B)
+#define ICL_PORT_TX_DW2_AUX(port)      _MMIO_PORT(port, \
+                                                  _ICL_PORT_TX_DW2_AUX_A, \
+                                                  _ICL_PORT_TX_DW2_AUX_B)
 #define   SWING_SEL_UPPER(x)           (((x) >> 3) << 15)
 #define   SWING_SEL_UPPER_MASK         (1 << 15)
 #define   SWING_SEL_LOWER(x)           (((x) & 0x7) << 11)
 #define   SWING_SEL_LOWER_MASK         (0x7 << 11)
+#define   FRC_LATENCY_OPTIM_MASK       (0x7 << 8)
+#define   FRC_LATENCY_OPTIM_VAL(x)     ((x) << 8)
 #define   RCOMP_SCALAR(x)              ((x) << 0)
 #define   RCOMP_SCALAR_MASK            (0xFF << 0)
 
@@ -1867,6 +1880,8 @@ enum i915_power_well_id {
 #define _ICL_PORT_TX_DW4_LN0_A         0x162890
 #define _ICL_PORT_TX_DW4_LN1_A         0x162990
 #define _ICL_PORT_TX_DW4_LN0_B         0x6C890
+#define _ICL_PORT_TX_DW4_AUX_A         0x162390
+#define _ICL_PORT_TX_DW4_AUX_B         0x6c390
 #define ICL_PORT_TX_DW4_GRP(port)      _MMIO_PORT(port, \
                                                   _ICL_PORT_TX_DW4_GRP_A, \
                                                   _ICL_PORT_TX_DW4_GRP_B)
@@ -1875,6 +1890,9 @@ enum i915_power_well_id {
                                                   _ICL_PORT_TX_DW4_LN0_B) + \
                                             ((ln) * (_ICL_PORT_TX_DW4_LN1_A - \
                                                      _ICL_PORT_TX_DW4_LN0_A)))
+#define ICL_PORT_TX_DW4_AUX(port)      _MMIO_PORT(port, \
+                                                  _ICL_PORT_TX_DW4_AUX_A, \
+                                                  _ICL_PORT_TX_DW4_AUX_B)
 #define   LOADGEN_SELECT               (1 << 31)
 #define   POST_CURSOR_1(x)             ((x) << 12)
 #define   POST_CURSOR_1_MASK           (0x3F << 12)
@@ -1889,12 +1907,17 @@ enum i915_power_well_id {
 #define _ICL_PORT_TX_DW5_GRP_B         0x6C694
 #define _ICL_PORT_TX_DW5_LN0_A         0x162894
 #define _ICL_PORT_TX_DW5_LN0_B         0x6C894
+#define _ICL_PORT_TX_DW5_AUX_A         0x162394
+#define _ICL_PORT_TX_DW5_AUX_B         0x6c394
 #define ICL_PORT_TX_DW5_GRP(port)      _MMIO_PORT(port, \
                                                   _ICL_PORT_TX_DW5_GRP_A, \
                                                   _ICL_PORT_TX_DW5_GRP_B)
 #define ICL_PORT_TX_DW5_LN0(port)      _MMIO_PORT(port, \
                                                   _ICL_PORT_TX_DW5_LN0_A, \
                                                   _ICL_PORT_TX_DW5_LN0_B)
+#define ICL_PORT_TX_DW5_AUX(port)      _MMIO_PORT(port, \
+                                                  _ICL_PORT_TX_DW5_AUX_A, \
+                                                  _ICL_PORT_TX_DW5_AUX_B)
 #define   TX_TRAINING_EN               (1 << 31)
 #define   TAP2_DISABLE                 (1 << 30)
 #define   TAP3_DISABLE                 (1 << 29)