realtek: fix egress L2 learning on rtl839x

The flag to enable L2 address learning on egress frames is in CPU header
bit 40, with bit 0 being the leftmost bit of the header. This
corresponds to BIT(7) in the third 16-bit value of the header.

Correctly set L2LEARNING by fixing the off-by-one error.

Fixes: 9eab76c84e31 ("realtek: Improve TX CPU-Tag usage")
Tested-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>

diff --git a/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c b/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c
index aece1356e40cf307d1fa92005f1d53a5c948c076..8c7813015a725f9b3e1f01578200ca15847a1e90 100644 (file)
--- a/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c
+++ b/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c
@@ -127,7 +127,7 @@ static void rtl839x_create_tx_header(struct p_hdr *h, int dest_port, int prio)
                        h->cpu_tag[5] = BIT(dest_port) & 0xffff;
                }
                h->cpu_tag[2] |= BIT(4); // Enable destination port mask use
-               h->cpu_tag[2] |= BIT(8); // Enable L2 Learning
+               h->cpu_tag[2] |= BIT(7); // Enable L2 Learning
                // Set internal priority and AS_PRIO
                if (prio >= 0)
                        h->cpu_tag[1] |= prio | BIT(3);