static void rtl838x_init_eee(struct rtl838x_switch_priv *priv, bool enable)
{
- pr_info("Setting up EEE, state: %d\n", enable);
+ pr_debug("Setting up EEE, state: %d\n", enable);
sw_w32_mask(0x4, 0, RTL838X_SMI_GLB_CTRL);
/* Set timers for EEE */
data_m = pr->icmp_igmp_m;
break;
default:
- pr_info("%s: unknown field %d\n", __func__, field_type);
+ pr_debug("%s: unknown field %d\n", __func__, field_type);
continue;
}
if (!(i % 2)) {
pr->icmp_igmp_m = data_m;
break;
default:
- pr_info("%s: unknown field %d\n", __func__, field_type);
+ pr_debug("%s: unknown field %d\n", __func__, field_type);
}
}
}
static void rtl838x_pie_rule_dump_raw(u32 r[])
{
- pr_info("Raw IACL table entry:\n");
- pr_info("Match : %08x %08x %08x %08x %08x %08x\n", r[0], r[1], r[2], r[3], r[4], r[5]);
- pr_info("Fixed : %08x\n", r[6]);
- pr_info("Match M: %08x %08x %08x %08x %08x %08x\n", r[7], r[8], r[9], r[10], r[11], r[12]);
- pr_info("Fixed M: %08x\n", r[13]);
- pr_info("AIF : %08x %08x %08x\n", r[14], r[15], r[16]);
- pr_info("Sel : %08x\n", r[17]);
+ pr_debug("Raw IACL table entry:\n");
+ pr_debug("Match : %08x %08x %08x %08x %08x %08x\n", r[0], r[1], r[2], r[3], r[4], r[5]);
+ pr_debug("Fixed : %08x\n", r[6]);
+ pr_debug("Match M: %08x %08x %08x %08x %08x %08x\n", r[7], r[8], r[9], r[10], r[11], r[12]);
+ pr_debug("Fixed M: %08x\n", r[13]);
+ pr_debug("AIF : %08x %08x %08x\n", r[14], r[15], r[16]);
+ pr_debug("Sel : %08x\n", r[17]);
}
// Currently not used
// static void rtl838x_pie_rule_dump(struct pie_rule *pr)
// {
-// pr_info("Drop: %d, fwd: %d, ovid: %d, ivid: %d, flt: %d, log: %d, rmk: %d, meter: %d tagst: %d, mir: %d, nopri: %d, cpupri: %d, otpid: %d, itpid: %d, shape: %d\n",
+// pr_debug("Drop: %d, fwd: %d, ovid: %d, ivid: %d, flt: %d, log: %d, rmk: %d, meter: %d tagst: %d, mir: %d, nopri: %d, cpupri: %d, otpid: %d, itpid: %d, shape: %d\n",
// pr->drop, pr->fwd_sel, pr->ovid_sel, pr->ivid_sel, pr->flt_sel, pr->log_sel, pr->rmk_sel, pr->log_sel, pr->tagst_sel, pr->mir_sel, pr->nopri_sel,
// pr->cpupri_sel, pr->otpid_sel, pr->itpid_sel, pr->shaper_sel);
// if (pr->fwd_sel)
-// pr_info("FWD: %08x\n", pr->fwd_data);
-// pr_info("TID: %x, %x\n", pr->tid, pr->tid_m);
+// pr_debug("FWD: %08x\n", pr->fwd_data);
+// pr_debug("TID: %x, %x\n", pr->tid, pr->tid_m);
// }
static int rtl838x_pie_rule_read(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr)
if (!pr->valid)
return 0;
- pr_info("%s: template_selectors %08x, tid: %d\n", __func__, t_select, pr->tid);
+ pr_debug("%s: template_selectors %08x, tid: %d\n", __func__, t_select, pr->tid);
rtl838x_pie_rule_dump_raw(r);
rtl838x_read_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 3)) & 0x7]);
/* Clear status */
sw_w32(ports, RTL838X_ISR_PORT_LINK_STS_CHG);
- pr_info("RTL8380 Link change: status: %x, ports %x\n", status, ports);
+ pr_debug("RTL8380 Link change: status: %x, ports %x\n", status, ports);
for (int i = 0; i < 28; i++) {
if (ports & BIT(i)) {
p = sw_r32(RTL838X_VLAN_PROFILE(profile));
- pr_info("VLAN profile %d: L2 learning: %d, UNKN L2MC FLD PMSK %d, \
+ pr_debug("VLAN profile %d: L2 learning: %d, UNKN L2MC FLD PMSK %d, \
UNKN IPMC FLD PMSK %d, UNKN IPv6MC FLD PMSK: %d",
profile, p & 1, (p >> 1) & 0x1ff, (p >> 10) & 0x1ff, (p >> 19) & 0x1ff);
}
e->valid = true;
e->type = IP6_MULTICAST;
}
- /* pr_info("%s: vid %d, rvid: %d\n", __func__, e->vid, e->rvid); */
+ /* pr_debug("%s: vid %d, rvid: %d\n", __func__, e->vid, e->rvid); */
}
/* Fills the 3 SoC table registers r[] with the information in the rtl838x_l2_entry */
model = sw_r32(RTL839X_MODEL_NAME_INFO);
priv->version = RTL8390_VERSION_A + ((model & 0x3f) >> 1);
- pr_info("RTL839X Chip-Info: %x, version %c\n", info, priv->version);
+ pr_debug("RTL839X Chip-Info: %x, version %c\n", info, priv->version);
}
void rtl839x_vlan_profile_dump(int profile)
p[0] = sw_r32(RTL839X_VLAN_PROFILE(profile));
p[1] = sw_r32(RTL839X_VLAN_PROFILE(profile) + 4);
- pr_info("VLAN profile %d: L2 learning: %d, UNKN L2MC FLD PMSK %d, \
+ pr_debug("VLAN profile %d: L2 learning: %d, UNKN L2MC FLD PMSK %d, \
UNKN IPMC FLD PMSK %d, UNKN IPv6MC FLD PMSK: %d",
profile, p[1] & 1, (p[1] >> 1) & 0xfff, (p[1] >> 13) & 0xfff,
(p[0]) & 0xfff);
- pr_info("VLAN profile %d: raw %08x, %08x\n", profile, p[0], p[1]);
+ pr_debug("VLAN profile %d: raw %08x, %08x\n", profile, p[0], p[1]);
}
static void rtl839x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
e->advertised |= ADVERTISED_1000baseT_Full;
a = rtl839x_get_port_reg_le(RTL839X_MAC_EEE_ABLTY);
- pr_info("Link partner: %016llx\n", a);
+ pr_debug("Link partner: %016llx\n", a);
if (rtl839x_get_port_reg_le(RTL839X_MAC_EEE_ABLTY) & BIT_ULL(port)) {
e->lp_advertised = ADVERTISED_100baseT_Full;
e->lp_advertised |= ADVERTISED_1000baseT_Full;
static void rtl839x_init_eee(struct rtl838x_switch_priv *priv, bool enable)
{
- pr_info("Setting up EEE, state: %d\n", enable);
+ pr_debug("Setting up EEE, state: %d\n", enable);
/* Set wake timer for TX and pause timer both to 0x21 */
sw_w32_mask(0xff << 20| 0xff, 0x21 << 20| 0x21, RTL839X_EEE_TX_TIMER_GELITE_CTRL);
data_m = pr->icmp_igmp_m;
break;
default:
- pr_info("%s: unknown field %d\n", __func__, field_type);
+ pr_debug("%s: unknown field %d\n", __func__, field_type);
}
/* On the RTL8390, the mask fields are not word aligned! */
pr->icmp_igmp_m = data_m;
break;
default:
- pr_info("%s: unknown field %d\n", __func__, field_type);
+ pr_debug("%s: unknown field %d\n", __func__, field_type);
}
}
}
void rtl839x_pie_rule_dump_raw(u32 r[])
{
- pr_info("Raw IACL table entry:\n");
- pr_info("Match : %08x %08x %08x %08x %08x %08x\n", r[0], r[1], r[2], r[3], r[4], r[5]);
- pr_info("Fixed : %06x\n", r[6] >> 8);
- pr_info("Match M: %08x %08x %08x %08x %08x %08x\n",
+ pr_debug("Raw IACL table entry:\n");
+ pr_debug("Match : %08x %08x %08x %08x %08x %08x\n", r[0], r[1], r[2], r[3], r[4], r[5]);
+ pr_debug("Fixed : %06x\n", r[6] >> 8);
+ pr_debug("Match M: %08x %08x %08x %08x %08x %08x\n",
(r[6] << 24) | (r[7] >> 8), (r[7] << 24) | (r[8] >> 8), (r[8] << 24) | (r[9] >> 8),
(r[9] << 24) | (r[10] >> 8), (r[10] << 24) | (r[11] >> 8),
(r[11] << 24) | (r[12] >> 8));
- pr_info("R[13]: %08x\n", r[13]);
- pr_info("Fixed M: %06x\n", ((r[12] << 16) | (r[13] >> 16)) & 0xffffff);
- pr_info("Valid / not / and1 / and2 : %1x\n", (r[13] >> 12) & 0xf);
- pr_info("r 13-16: %08x %08x %08x %08x\n", r[13], r[14], r[15], r[16]);
+ pr_debug("R[13]: %08x\n", r[13]);
+ pr_debug("Fixed M: %06x\n", ((r[12] << 16) | (r[13] >> 16)) & 0xffffff);
+ pr_debug("Valid / not / and1 / and2 : %1x\n", (r[13] >> 12) & 0xf);
+ pr_debug("r 13-16: %08x %08x %08x %08x\n", r[13], r[14], r[15], r[16]);
}
void rtl839x_pie_rule_dump(struct pie_rule *pr)
{
- pr_info("Drop: %d, fwd: %d, ovid: %d, ivid: %d, flt: %d, log: %d, rmk: %d, meter: %d tagst: %d, mir: %d, nopri: %d, cpupri: %d, otpid: %d, itpid: %d, shape: %d\n",
+ pr_debug("Drop: %d, fwd: %d, ovid: %d, ivid: %d, flt: %d, log: %d, rmk: %d, meter: %d tagst: %d, mir: %d, nopri: %d, cpupri: %d, otpid: %d, itpid: %d, shape: %d\n",
pr->drop, pr->fwd_sel, pr->ovid_sel, pr->ivid_sel, pr->flt_sel, pr->log_sel, pr->rmk_sel, pr->log_sel, pr->tagst_sel, pr->mir_sel, pr->nopri_sel,
pr->cpupri_sel, pr->otpid_sel, pr->itpid_sel, pr->shaper_sel);
if (pr->fwd_sel)
- pr_info("FWD: %08x\n", pr->fwd_data);
- pr_info("TID: %x, %x\n", pr->tid, pr->tid_m);
+ pr_debug("FWD: %08x\n", pr->fwd_data);
+ pr_debug("TID: %x, %x\n", pr->tid, pr->tid_m);
}
static int rtl839x_pie_rule_read(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr)
p[3] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 12) & 0x1FFFFFFF;
p[4] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 16) & 0x1FFFFFFF;
- pr_info("VLAN %d: L2 learn: %d; Unknown MC PMasks: L2 %0x, IPv4 %0x, IPv6: %0x",
+ pr_debug("VLAN %d: L2 learn: %d; Unknown MC PMasks: L2 %0x, IPv4 %0x, IPv6: %0x",
profile, p[0] & (3 << 21), p[2], p[3], p[4]);
- pr_info(" Routing enabled: IPv4 UC %c, IPv6 UC %c, IPv4 MC %c, IPv6 MC %c\n",
+ pr_debug(" Routing enabled: IPv4 UC %c, IPv6 UC %c, IPv4 MC %c, IPv6 MC %c\n",
p[0] & BIT(17) ? 'y' : 'n', p[0] & BIT(16) ? 'y' : 'n',
p[0] & BIT(13) ? 'y' : 'n', p[0] & BIT(12) ? 'y' : 'n');
- pr_info(" Bridge enabled: IPv4 MC %c, IPv6 MC %c,\n",
+ pr_debug(" Bridge enabled: IPv4 MC %c, IPv6 MC %c,\n",
p[0] & BIT(15) ? 'y' : 'n', p[0] & BIT(14) ? 'y' : 'n');
- pr_info("VLAN profile %d: raw %08x %08x %08x %08x %08x\n",
+ pr_debug("VLAN profile %d: raw %08x %08x %08x %08x %08x\n",
profile, p[0], p[1], p[2], p[3], p[4]);
}
{
u32 p[5];
- pr_info("In %s\n", __func__);
+ pr_debug("In %s\n", __func__);
p[0] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile));
p[1] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 4);
u16 r = RTL930X_STAT_PRVTE_DROP_COUNTER0;
for (int i = 0; i < 10; i ++) {
- pr_info("# %d %08x %08x %08x %08x %08x %08x %08x %08x\n", i * 8,
+ pr_debug("# %d %08x %08x %08x %08x %08x %08x %08x %08x\n", i * 8,
sw_r32(r), sw_r32(r + 4), sw_r32(r + 8), sw_r32(r + 12),
sw_r32(r + 16), sw_r32(r + 20), sw_r32(r + 24), sw_r32(r + 28));
r += 32;
}
- pr_info("# %08x %08x %08x %08x %08x\n",
+ pr_debug("# %08x %08x %08x %08x %08x\n",
sw_r32(r), sw_r32(r + 4), sw_r32(r + 8), sw_r32(r + 12), sw_r32(r + 16));
rtl930x_print_matrix();
- pr_info("RTL930X_L2_PORT_SABLK_CTRL: %08x, RTL930X_L2_PORT_DABLK_CTRL %08x\n",
+ pr_debug("RTL930X_L2_PORT_SABLK_CTRL: %08x, RTL930X_L2_PORT_DABLK_CTRL %08x\n",
sw_r32(RTL930X_L2_PORT_SABLK_CTRL), sw_r32(RTL930X_L2_PORT_DABLK_CTRL)
);
if (port >= 26)
return -ENOTSUPP;
- pr_info("In %s, port %d\n", __func__, port);
+ pr_debug("In %s, port %d\n", __func__, port);
link = sw_r32(RTL930X_MAC_LINK_STS);
link = sw_r32(RTL930X_MAC_LINK_STS);
if (!(link & BIT(port)))
return 0;
- pr_info("Setting advertised\n");
+ pr_debug("Setting advertised\n");
if (sw_r32(rtl930x_mac_force_mode_ctrl(port)) & BIT(10))
e->advertised |= ADVERTISED_100baseT_Full;
e->advertised |= ADVERTISED_1000baseT_Full;
if (priv->ports[port].is2G5 && sw_r32(rtl930x_mac_force_mode_ctrl(port)) & BIT(13)) {
- pr_info("ADVERTISING 2.5G EEE\n");
+ pr_debug("ADVERTISING 2.5G EEE\n");
e->advertised |= ADVERTISED_2500baseX_Full;
}
a = sw_r32(RTL930X_MAC_EEE_ABLTY);
a = sw_r32(RTL930X_MAC_EEE_ABLTY);
- pr_info("Link partner: %08x\n", a);
+ pr_debug("Link partner: %08x\n", a);
if (a & BIT(port)) {
e->lp_advertised = ADVERTISED_100baseT_Full;
e->lp_advertised |= ADVERTISED_1000baseT_Full;
/* Read 2x to clear latched state */
a = sw_r32(RTL930X_EEEP_PORT_CTRL(port));
a = sw_r32(RTL930X_EEEP_PORT_CTRL(port));
- pr_info("%s RTL930X_EEEP_PORT_CTRL: %08x\n", __func__, a);
+ pr_debug("%s RTL930X_EEEP_PORT_CTRL: %08x\n", __func__, a);
return 0;
}
static void rtl930x_init_eee(struct rtl838x_switch_priv *priv, bool enable)
{
- pr_info("Setting up EEE, state: %d\n", enable);
+ pr_debug("Setting up EEE, state: %d\n", enable);
/* Setup EEE on all ports */
for (int i = 0; i < priv->cpu_port; i++) {
host_route = !!(v & BIT(21));
default_route = !!(v & BIT(20));
rt->prefix_len = -1;
- pr_info("%s: host route %d, default_route %d\n", __func__, host_route, default_route);
+ pr_debug("%s: host route %d, default_route %d\n", __func__, host_route, default_route);
switch (rt->attr.type) {
case 0: /* IPv4 Unicast route */
rt->dst_ip = sw_r32(rtl_table_data(r, 4));
ip4_m = sw_r32(rtl_table_data(r, 9));
- pr_info("%s: Read ip4 mask: %08x\n", __func__, ip4_m);
+ pr_debug("%s: Read ip4 mask: %08x\n", __func__, ip4_m);
rt->prefix_len = host_route ? 32 : -1;
rt->prefix_len = (rt->prefix_len < 0 && default_route) ? 0 : -1;
if (rt->prefix_len < 0)
rt->attr.dst_null = !!(v & BIT(4));
rt->attr.qos_as = !!(v & BIT(3));
rt->attr.qos_prio = v & 0x7;
- pr_info("%s: index %d is valid: %d\n", __func__, idx, rt->attr.valid);
- pr_info("%s: next_hop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n",
+ pr_debug("%s: index %d is valid: %d\n", __func__, idx, rt->attr.valid);
+ pr_debug("%s: next_hop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n",
__func__, rt->nh.id, rt->attr.hit, rt->attr.action,
rt->attr.ttl_dec, rt->attr.ttl_check, rt->attr.dst_null);
- pr_info("%s: GW: %pI4, prefix_len: %d\n", __func__, &rt->dst_ip, rt->prefix_len);
+ pr_debug("%s: GW: %pI4, prefix_len: %d\n", __func__, &rt->dst_ip, rt->prefix_len);
out:
rtl_table_release(r);
}
sw_w32(0, RTL930X_L3_HW_LU_KEY_IP_CTRL + 4);
sw_w32(0, RTL930X_L3_HW_LU_KEY_IP_CTRL + 8);
v = rt->dst_ip & ip4_m;
- pr_info("%s: searching for %pI4\n", __func__, &v);
+ pr_debug("%s: searching for %pI4\n", __func__, &v);
sw_w32(v, RTL930X_L3_HW_LU_KEY_IP_CTRL + 12);
}
v = sw_r32(RTL930X_L3_HW_LU_CTRL);
} while (v & BIT(15));
- pr_info("%s: found: %d, index: %d\n", __func__, !!(v & BIT(14)), v & 0x1ff);
+ pr_debug("%s: found: %d, index: %d\n", __func__, !!(v & BIT(14)), v & 0x1ff);
/* Test if search successful (BIT 14 set) */
if (v & BIT(14))
// }
// priv->intf_mtus[i] = mtu;
-// pr_info("Writing MTU %d to slot %d\n", priv->intf_mtus[i], i);
+// pr_debug("Writing MTU %d to slot %d\n", priv->intf_mtus[i], i);
// /* Set MTU-value of the slot TODO: distinguish between IPv4/IPv6 routes / slots */
// sw_w32_mask(0xffff << ((i % 2) * 16), priv->intf_mtus[i] << ((i % 2) * 16),
// RTL930X_L3_IP_MTU_CTRL(i));
// intf->ip6_mtu = intf->ip6_mtu ? intf->ip6_mtu : intf->ip4_mtu;
// mtu_id = rtl930x_l3_mtu_add(priv, intf->ip4_mtu);
-// pr_info("%s: added mtu %d with mtu-id %d\n", __func__, intf->ip4_mtu, mtu_id);
+// pr_debug("%s: added mtu %d with mtu-id %d\n", __func__, intf->ip4_mtu, mtu_id);
// if (mtu_id < 0)
// return -ENOSPC;
// intf->ip4_mtu_id = mtu_id;
/* Access L3_NEXTHOP table (3) via register RTL9300_TBL_1 */
struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 3);
- pr_info("%s: Writing to L3_NEXTHOP table, index %d, dmac_id %d, interface %d\n",
+ pr_debug("%s: Writing to L3_NEXTHOP table, index %d, dmac_id %d, interface %d\n",
__func__, idx, dmac_id, interface);
sw_w32(((dmac_id & 0x7fff) << 7) | (interface & 0x7f), rtl_table_data(r, 0));
- pr_info("%s: %08x\n", __func__, sw_r32(rtl_table_data(r,0)));
+ pr_debug("%s: %08x\n", __func__, sw_r32(rtl_table_data(r,0)));
rtl_table_write(r, idx);
rtl_table_release(r);
}
pr_debug("TEMPLATE_FIELD_RANGE_CHK: not configured\n");
break;
default:
- pr_info("%s: unknown field %d\n", __func__, field_type);
+ pr_debug("%s: unknown field %d\n", __func__, field_type);
}
/* On the RTL9300, the mask fields are not word aligned! */
void rtl930x_pie_rule_dump_raw(u32 r[])
{
- pr_info("Raw IACL table entry:\n");
- pr_info("r 0 - 7: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ pr_debug("Raw IACL table entry:\n");
+ pr_debug("r 0 - 7: %08x %08x %08x %08x %08x %08x %08x %08x\n",
r[0], r[1], r[2], r[3], r[4], r[5], r[6], r[7]);
- pr_info("r 8 - 15: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ pr_debug("r 8 - 15: %08x %08x %08x %08x %08x %08x %08x %08x\n",
r[8], r[9], r[10], r[11], r[12], r[13], r[14], r[15]);
- pr_info("r 16 - 18: %08x %08x %08x\n", r[16], r[17], r[18]);
- pr_info("Match : %08x %08x %08x %08x %08x %08x\n", r[0], r[1], r[2], r[3], r[4], r[5]);
- pr_info("Fixed : %06x\n", r[6] >> 8);
- pr_info("Match M: %08x %08x %08x %08x %08x %08x\n",
+ pr_debug("r 16 - 18: %08x %08x %08x\n", r[16], r[17], r[18]);
+ pr_debug("Match : %08x %08x %08x %08x %08x %08x\n", r[0], r[1], r[2], r[3], r[4], r[5]);
+ pr_debug("Fixed : %06x\n", r[6] >> 8);
+ pr_debug("Match M: %08x %08x %08x %08x %08x %08x\n",
(r[6] << 24) | (r[7] >> 8), (r[7] << 24) | (r[8] >> 8), (r[8] << 24) | (r[9] >> 8),
(r[9] << 24) | (r[10] >> 8), (r[10] << 24) | (r[11] >> 8),
(r[11] << 24) | (r[12] >> 8));
- pr_info("R[13]: %08x\n", r[13]);
- pr_info("Fixed M: %06x\n", ((r[12] << 16) | (r[13] >> 16)) & 0xffffff);
- pr_info("Valid / not / and1 / and2 : %1x\n", (r[13] >> 12) & 0xf);
- pr_info("r 13-16: %08x %08x %08x %08x\n", r[13], r[14], r[15], r[16]);
+ pr_debug("R[13]: %08x\n", r[13]);
+ pr_debug("Fixed M: %06x\n", ((r[12] << 16) | (r[13] >> 16)) & 0xffffff);
+ pr_debug("Valid / not / and1 / and2 : %1x\n", (r[13] >> 12) & 0xf);
+ pr_debug("r 13-16: %08x %08x %08x %08x\n", r[13], r[14], r[15], r[16]);
}
static int rtl930x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr)
mutex_init(&priv->pie_mutex);
- pr_info("%s\n", __func__);
+ pr_debug("%s\n", __func__);
/* Enable ACL lookup on all ports, including CPU_PORT */
for (int i = 0; i <= priv->cpu_port; i++)
sw_w32(1, RTL930X_ACL_PORT_LOOKUP_CTRL(i));
sw_w32(u, rtl_table_data(r, 0));
sw_w32(v, rtl_table_data(r, 1));
- pr_info("%s writing to index %d: %08x %08x\n", __func__, idx, u, v);
+ pr_debug("%s writing to index %d: %08x %08x\n", __func__, idx, u, v);
rtl_table_write(r, idx & 0x7f);
rtl_table_release(r);
}
sw_w32_mask(BIT(2), 0, RTL930X_L3_HOST_TBL_CTRL); /* Algorithm selection 0 = 0 */
sw_w32_mask(0, BIT(3), RTL930X_L3_HOST_TBL_CTRL); /* Algorithm selection 1 = 1 */
- pr_info("L3_IPUC_ROUTE_CTRL %08x, IPMC_ROUTE %08x, IP6UC_ROUTE %08x, IP6MC_ROUTE %08x\n",
+ pr_debug("L3_IPUC_ROUTE_CTRL %08x, IPMC_ROUTE %08x, IP6UC_ROUTE %08x, IP6MC_ROUTE %08x\n",
sw_r32(RTL930X_L3_IPUC_ROUTE_CTRL), sw_r32(RTL930X_L3_IPMC_ROUTE_CTRL),
sw_r32(RTL930X_L3_IP6UC_ROUTE_CTRL), sw_r32(RTL930X_L3_IP6MC_ROUTE_CTRL));
sw_w32_mask(0, 1, RTL930X_L3_IPUC_ROUTE_CTRL);
sw_w32(0x00000501, RTL930X_L3_IPMC_ROUTE_CTRL);
sw_w32(0x00012881, RTL930X_L3_IP6MC_ROUTE_CTRL);
- pr_info("L3_IPUC_ROUTE_CTRL %08x, IPMC_ROUTE %08x, IP6UC_ROUTE %08x, IP6MC_ROUTE %08x\n",
+ pr_debug("L3_IPUC_ROUTE_CTRL %08x, IPMC_ROUTE %08x, IP6UC_ROUTE %08x, IP6MC_ROUTE %08x\n",
sw_r32(RTL930X_L3_IPUC_ROUTE_CTRL), sw_r32(RTL930X_L3_IPMC_ROUTE_CTRL),
sw_r32(RTL930X_L3_IP6UC_ROUTE_CTRL), sw_r32(RTL930X_L3_IP6MC_ROUTE_CTRL));
/* Trap non-ip traffic to the CPU-port (e.g. ARP so we stay reachable) */
sw_w32_mask(0x3 << 8, 0x1 << 8, RTL930X_L3_IP_ROUTE_CTRL);
- pr_info("L3_IP_ROUTE_CTRL %08x\n", sw_r32(RTL930X_L3_IP_ROUTE_CTRL));
+ pr_debug("L3_IP_ROUTE_CTRL %08x\n", sw_r32(RTL930X_L3_IP_ROUTE_CTRL));
/* PORT_ISO_RESTRICT_ROUTE_CTRL? */
/* Access LOG table (3) via register RTL9300_TBL_0 */
struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 3);
- pr_info("In %s, id %d\n", __func__, counter);
+ pr_debug("In %s, id %d\n", __func__, counter);
/* The table has a size of 2 registers */
if (counter % 2)
sw_w32(0, rtl_table_data(r, 0));
struct device_node *node;
u32 pm = 0;
- pr_info("%s called\n", __func__);
+ pr_debug("%s called\n", __func__);
node = of_find_compatible_node(NULL, NULL, "realtek,rtl9300-leds");
if (!node) {
- pr_info("%s No compatible LED node found\n", __func__);
+ pr_debug("%s No compatible LED node found\n", __func__);
return;
}
sw_w32(pm, RTL930X_LED_PORT_COMBO_MASK_CTRL);
for (int i = 0; i < 24; i++)
- pr_info("%s %08x: %08x\n",__func__, 0xbb00cc00 + i * 4, sw_r32(0xcc00 + i * 4));
+ pr_debug("%s %08x: %08x\n",__func__, 0xbb00cc00 + i * 4, sw_r32(0xcc00 + i * 4));
}
const struct rtl838x_reg rtl930x_reg = {
profile[3] = (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 20) & 0x1FFFFFFFULL) << 32 |
(sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 24) & 0xFFFFFFFF);
- pr_info("VLAN %d: L2 learning: %d, L2 Unknown MultiCast Field %llx, \
+ pr_debug("VLAN %d: L2 learning: %d, L2 Unknown MultiCast Field %llx, \
IPv4 Unknown MultiCast Field %llx, IPv6 Unknown MultiCast Field: %llx",
index, (u32) (profile[0] & (3 << 14)), profile[1], profile[2], profile[3]);
}
for (int i = 0; i < 56; i++) {
if (ports & BIT_ULL(i)) {
if (link & BIT_ULL(i)) {
- pr_info("%s port %d up\n", __func__, i);
+ pr_debug("%s port %d up\n", __func__, i);
dsa_port_phylink_mac_change(ds, i, true);
} else {
- pr_info("%s port %d down\n", __func__, i);
+ pr_debug("%s port %d down\n", __func__, i);
dsa_port_phylink_mac_change(ds, i, false);
}
}
volatile u64 *ptr = RTL838X_SW_BASE + RTL839X_PORT_ISO_CTRL(0);
for (int i = 0; i < 52; i += 4)
- pr_info("> %16llx %16llx %16llx %16llx\n",
+ pr_debug("> %16llx %16llx %16llx %16llx\n",
ptr[i + 0], ptr[i + 1], ptr[i + 2], ptr[i + 3]);
- pr_info("CPU_PORT> %16llx\n", ptr[52]);
+ pr_debug("CPU_PORT> %16llx\n", ptr[52]);
}
void rtl931x_set_receive_management_action(int port, rma_ctrl_t type, action_type_t action)
struct table_reg *q = rtl_table_get(RTL9310_TBL_0, 0);
u32 idx = (0 << 14) | (hash << 2) | pos; /* Access SRAM, with hash and at pos in bucket */
- pr_info("%s: hash %d, pos %d\n", __func__, hash, pos);
- pr_info("%s: index %d -> mac %02x:%02x:%02x:%02x:%02x:%02x\n", __func__, idx,
+ pr_debug("%s: hash %d, pos %d\n", __func__, hash, pos);
+ pr_debug("%s: index %d -> mac %02x:%02x:%02x:%02x:%02x:%02x\n", __func__, idx,
e->mac[0], e->mac[1], e->mac[2], e->mac[3],e->mac[4],e->mac[5]);
rtl931x_fill_l2_row(r, e);
- pr_info("%s: %d: %08x %08x %08x\n", __func__, idx, r[0], r[1], r[2]);
+ pr_debug("%s: %d: %08x %08x %08x\n", __func__, idx, r[0], r[1], r[2]);
for (int i = 0; i < 4; i++)
sw_w32(r[i], rtl_table_data(q, i));
{
u32 p[7];
- pr_info("In %s\n", __func__);
+ pr_debug("In %s\n", __func__);
if (profile > 15)
return;
for (int i = 0; i < 7; i++)
sw_w32(p[i], RTL931X_VLAN_PROFILE_SET(profile) + i * 4);
- pr_info("Leaving %s\n", __func__);
+ pr_debug("Leaving %s\n", __func__);
}
static void rtl931x_l2_learning_setup(void)
void rtl931x_pie_rule_dump_raw(u32 r[])
{
- pr_info("Raw IACL table entry:\n");
- pr_info("r 0 - 7: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ pr_debug("Raw IACL table entry:\n");
+ pr_debug("r 0 - 7: %08x %08x %08x %08x %08x %08x %08x %08x\n",
r[0], r[1], r[2], r[3], r[4], r[5], r[6], r[7]);
- pr_info("r 8 - 15: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ pr_debug("r 8 - 15: %08x %08x %08x %08x %08x %08x %08x %08x\n",
r[8], r[9], r[10], r[11], r[12], r[13], r[14], r[15]);
- pr_info("r 16 - 18: %08x %08x %08x\n", r[16], r[17], r[18]);
- pr_info("Match : %08x %08x %08x %08x %08x %08x\n", r[0], r[1], r[2], r[3], r[4], r[5]);
- pr_info("Fixed : %06x\n", r[6] >> 8);
- pr_info("Match M: %08x %08x %08x %08x %08x %08x\n",
+ pr_debug("r 16 - 18: %08x %08x %08x\n", r[16], r[17], r[18]);
+ pr_debug("Match : %08x %08x %08x %08x %08x %08x\n", r[0], r[1], r[2], r[3], r[4], r[5]);
+ pr_debug("Fixed : %06x\n", r[6] >> 8);
+ pr_debug("Match M: %08x %08x %08x %08x %08x %08x\n",
(r[6] << 24) | (r[7] >> 8), (r[7] << 24) | (r[8] >> 8), (r[8] << 24) | (r[9] >> 8),
(r[9] << 24) | (r[10] >> 8), (r[10] << 24) | (r[11] >> 8),
(r[11] << 24) | (r[12] >> 8));
- pr_info("R[13]: %08x\n", r[13]);
- pr_info("Fixed M: %06x\n", ((r[12] << 16) | (r[13] >> 16)) & 0xffffff);
- pr_info("Valid / not / and1 / and2 : %1x\n", (r[13] >> 12) & 0xf);
- pr_info("r 13-16: %08x %08x %08x %08x\n", r[13], r[14], r[15], r[16]);
+ pr_debug("R[13]: %08x\n", r[13]);
+ pr_debug("Fixed M: %06x\n", ((r[12] << 16) | (r[13] >> 16)) & 0xffffff);
+ pr_debug("Valid / not / and1 / and2 : %1x\n", (r[13] >> 12) & 0xf);
+ pr_debug("r 13-16: %08x %08x %08x %08x\n", r[13], r[14], r[15], r[16]);
}
static int rtl931x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr)
int block = idx / PIE_BLOCK_SIZE;
u32 t_select = sw_r32(RTL931X_PIE_BLK_TMPLTE_CTRL(block));
- pr_info("%s: %d, t_select: %08x\n", __func__, idx, t_select);
+ pr_debug("%s: %d, t_select: %08x\n", __func__, idx, t_select);
for (int i = 0; i < 22; i++)
r[i] = 0;
}
rtl931x_write_pie_fixed_fields(r, pr);
- pr_info("%s: template %d\n", __func__, (t_select >> (pr->tid * 4)) & 0xf);
+ pr_debug("%s: template %d\n", __func__, (t_select >> (pr->tid * 4)) & 0xf);
rtl931x_write_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 4)) & 0xf]);
rtl931x_write_pie_action(r, pr);
min_block = max_block;
max_block = priv->n_pie_blocks;
}
- pr_info("In %s\n", __func__);
+ pr_debug("In %s\n", __func__);
mutex_lock(&priv->pie_mutex);
for (block = min_block; block < max_block; block++) {
for (j = 0; j < 2; j++) {
int t = (sw_r32(RTL931X_PIE_BLK_TMPLTE_CTRL(block)) >> (j * 4)) & 0xf;
- pr_info("Testing block %d, template %d, template id %d\n", block, j, t);
- pr_info("%s: %08x\n",
+ pr_debug("Testing block %d, template %d, template id %d\n", block, j, t);
+ pr_debug("%s: %08x\n",
__func__, sw_r32(RTL931X_PIE_BLK_TMPLTE_CTRL(block)));
idx = rtl931x_pie_verify_template(priv, pr, t, block);
if (idx >= 0)
return -EOPNOTSUPP;
}
- pr_info("Using block: %d, index %d, template-id %d\n", block, idx, j);
+ pr_debug("Using block: %d, index %d, template-id %d\n", block, idx, j);
set_bit(idx, priv->pie_use_bm);
pr->valid = true;
{
u32 v = (index_from << 1)| (index_to << 13 ) | BIT(0);
- pr_info("%s: from %d to %d\n", __func__, index_from, index_to);
+ pr_debug("%s: from %d to %d\n", __func__, index_from, index_to);
mutex_lock(&priv->reg_mutex);
/* Write from-to and execute bit into control register */
mutex_init(&priv->pie_mutex);
- pr_info("%s\n", __func__);
+ pr_debug("%s\n", __func__);
/* Enable ACL lookup on all ports, including CPU_PORT */
for (int i = 0; i <= priv->cpu_port; i++)
sw_w32(1, RTL931X_ACL_PORT_LOOKUP_CTRL(i));
u64 pm_copper = 0, pm_fiber = 0;
struct device_node *node;
- pr_info("%s called\n", __func__);
+ pr_debug("%s called\n", __func__);
node = of_find_compatible_node(NULL, NULL, "realtek,rtl9300-leds");
if (!node) {
- pr_info("%s No compatible LED node found\n", __func__);
+ pr_debug("%s No compatible LED node found\n", __func__);
return;
}
u32 v;
sprintf(set_name, "led_set%d", i);
- pr_info(">%s<\n", set_name);
+ pr_debug(">%s<\n", set_name);
led_set = of_get_property(node, set_name, &setlen);
if (!led_set || setlen != 16)
break;
rtl839x_set_port_reg_le(pm_copper | pm_fiber, RTL931X_LED_PORT_COMBO_MASK_CTRL);
for (int i = 0; i < 32; i++)
- pr_info("%s %08x: %08x\n",__func__, 0xbb000600 + i * 4, sw_r32(0x0600 + i * 4));
+ pr_debug("%s %08x: %08x\n",__func__, 0xbb000600 + i * 4, sw_r32(0x0600 + i * 4));
}
const struct rtl838x_reg rtl931x_reg = {