powerpc/p3041: Add various p3041 specific information

Add P3041 SoC specific information:
* SERDES Table
* LIODN setup
* Portal configuration

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 3f118dbfd73f269a796448f8ecd907eeed139874..706974991f9bca7bc9134580a690b134f2aa3b2f 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -72,6 +72,7 @@ COBJS-$(CONFIG_PCI)   += pci.o
 COBJS-$(CONFIG_FSL_CORENET) += portals.o
 
 # various SoC specific assignments
+COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o
 COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
 
 COBJS-$(CONFIG_QE)     += qe_io.o
@@ -93,6 +94,7 @@ COBJS-$(CONFIG_P1021) += p1021_serdes.o
 COBJS-$(CONFIG_P1022)  += p1022_serdes.o
 COBJS-$(CONFIG_P2010)  += p2020_serdes.o
 COBJS-$(CONFIG_P2020)  += p2020_serdes.o
+COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o
 COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
 
 COBJS  = $(COBJS-y)

diff --git a/arch/powerpc/cpu/mpc85xx/p3041_ids.c b/arch/powerpc/cpu/mpc85xx/p3041_ids.c
new file mode 100644 (file)
index 0000000..febbee9
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/p3041_ids.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+
+struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+       /* dqrr liodn, frame data liodn, liodn off, sdest */
+       SET_QP_INFO( 1,  2,  1, 0),
+       SET_QP_INFO( 3,  4,  2, 1),
+       SET_QP_INFO( 5,  6,  3, 2),
+       SET_QP_INFO( 7,  8,  4, 3),
+       SET_QP_INFO( 9, 10,  5, 4),
+       SET_QP_INFO( 0,  0,  0, 5),
+       SET_QP_INFO( 0,  0,  0, 6),
+       SET_QP_INFO( 0,  0,  0, 7),
+       SET_QP_INFO( 0,  0,  0, 0), /* for now sdest to 0 */
+       SET_QP_INFO( 0,  0,  0, 0), /* for now sdest to 0 */
+};
+
+struct liodn_id_table liodn_tbl[] = {
+       SET_QMAN_LIODN(31),
+       SET_BMAN_LIODN(32),
+
+       SET_SDHC_LIODN(1, 64),
+
+       SET_PME_LIODN(117),
+
+       SET_USB_LIODN(1, "fsl-usb2-mph", 125),
+       SET_USB_LIODN(2, "fsl-usb2-dr", 126),
+
+       SET_SATA_LIODN(1, 127),
+       SET_SATA_LIODN(2, 128),
+
+       SET_PCI_LIODN(1, 193),
+       SET_PCI_LIODN(2, 194),
+       SET_PCI_LIODN(3, 195),
+       SET_PCI_LIODN(4, 196),
+
+       SET_DMA_LIODN(1, 197),
+       SET_DMA_LIODN(2, 198),
+
+       SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
+       SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
+       SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
+       SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
+};
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+struct liodn_id_table fman1_liodn_tbl[] = {
+       SET_FMAN_RX_1G_LIODN(1, 0, 10),
+       SET_FMAN_RX_1G_LIODN(1, 1, 11),
+       SET_FMAN_RX_1G_LIODN(1, 2, 12),
+       SET_FMAN_RX_1G_LIODN(1, 3, 13),
+       SET_FMAN_RX_1G_LIODN(1, 4, 14),
+       SET_FMAN_RX_10G_LIODN(1, 0, 15),
+};
+#endif
+
+struct liodn_id_table sec_liodn_tbl[] = {
+       SET_SEC_JR_LIODN_ENTRY(0, 129, 130),
+       SET_SEC_JR_LIODN_ENTRY(1, 131, 132),
+       SET_SEC_JR_LIODN_ENTRY(2, 133, 134),
+       SET_SEC_JR_LIODN_ENTRY(3, 135, 136),
+       SET_SEC_RTIC_LIODN_ENTRY(a, 154),
+       SET_SEC_RTIC_LIODN_ENTRY(b, 155),
+       SET_SEC_RTIC_LIODN_ENTRY(c, 156),
+       SET_SEC_RTIC_LIODN_ENTRY(d, 157),
+       SET_SEC_DECO_LIODN_ENTRY(0, 97, 98),
+       SET_SEC_DECO_LIODN_ENTRY(1, 99, 100),
+};
+
+struct liodn_id_table liodn_bases[] = {
+       [FSL_HW_PORTAL_SEC]  = SET_LIODN_BASE_2(64, 100),
+#ifdef CONFIG_SYS_DPAA_FMAN
+       [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32),
+#endif
+#ifdef CONFIG_SYS_DPAA_PME
+       [FSL_HW_PORTAL_PME]   = SET_LIODN_BASE_2(136, 172),
+#endif
+};
+
+int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
+int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
+int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);

diff --git a/arch/powerpc/cpu/mpc85xx/p3041_serdes.c b/arch/powerpc/cpu/mpc85xx/p3041_serdes.c
new file mode 100644 (file)
index 0000000..fba9ff2
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/p3041_serdes.c
@@ -0,0 +1,151 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_serdes.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include "fsl_corenet_serdes.h"
+
+static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
+       [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
+               PCIE4, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
+               SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
+       [0x4] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
+               PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
+               SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, },
+       [0xb] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1,
+               PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
+               SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
+       [0x10] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
+               AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
+               NONE, NONE, SATA1, SATA2, },
+       [0x11] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
+               AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
+       [0x13] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
+               AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1,
+               XAUI_FM1, XAUI_FM1, },
+       [0x14] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
+               AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3,
+               SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
+               SGMII_FM1_DTSEC4, },
+       [0x15] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
+               AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
+               NONE, NONE, SATA1, SATA2, },
+       [0x16] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
+               AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SRIO1, SRIO1, SRIO1,
+               SRIO1, },
+       [0x17] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
+               AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
+       [0x18] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
+               AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
+               NONE, NONE, },
+       [0x1b] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
+               AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
+               NONE, NONE, SATA1, SATA2, },
+       [0x1d] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
+               AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE,
+               SATA1, SATA2, },
+       [0x20] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
+               AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1,
+               XAUI_FM1, XAUI_FM1, },
+       [0x21] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
+               AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3,
+               SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
+               SGMII_FM1_DTSEC4, },
+       [0x22] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
+               AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
+               NONE, NONE, SATA1, SATA2, },
+       [0x23] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1,
+               AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
+       [0x24] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1,
+               AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
+               NONE, NONE, },
+       [0x28] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
+               AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
+       [0x29] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
+               AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
+               NONE, NONE, },
+       [0x2a] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
+               AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1,
+               XAUI_FM1, XAUI_FM1, },
+       [0x2b] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
+               AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
+               NONE, NONE, SATA1, SATA2, },
+       [0x2f] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO2, SRIO2, SRIO1, SRIO1,
+               AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
+               NONE, NONE, SATA1, SATA2, },
+       [0x31] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1,
+               AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
+               NONE, NONE, },
+       [0x33] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1,
+               AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
+               NONE, NONE, SATA1, SATA2, },
+       [0x34] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM1_DTSEC1,
+               SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
+               AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
+               NONE, SATA1, SATA2, },
+       [0x35] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2,
+               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1,
+               XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, },
+       [0x36] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM1_DTSEC1,
+               SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
+               AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
+               NONE, SATA1, SATA2, },
+       [0x37] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2,
+               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1,
+               XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, },
+};
+
+enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
+{
+       if (!serdes_lane_enabled(lane))
+               return NONE;
+
+       return serdes_cfg_tbl[cfg][lane];
+}
+
+int is_serdes_prtcl_valid(u32 prtcl) {
+       int i;
+
+       if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
+               return 0;
+
+       for (i = 0; i < SRDS_MAX_LANES; i++) {
+               if (serdes_cfg_tbl[prtcl][i] != NONE)
+                       return 1;
+       }
+
+       return 0;
+}