drm/amd/display: fix underflow on boot
authorEric Yang <Eric.Yang2@amd.com>
Mon, 25 Mar 2019 20:11:43 +0000 (16:11 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 10 Apr 2019 18:53:28 +0000 (13:53 -0500)
[Why]
New seamless boot sequence introduced a bug where front end is disabled
without blanking otg.

[How]
Adjust the condition of blanking otg to match seamless boot.

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

index afa8648d88e123c93ef6abdde24f3819fc1d2fb4..f6591488ef9bfed16aa956f01f80de76189003a1 100644 (file)
@@ -979,16 +979,14 @@ static void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
                 * to non-preferred front end. If pipe_ctx->stream is not NULL,
                 * we will use the pipe, so don't disable
                 */
-               if (pipe_ctx->stream != NULL)
+               if (pipe_ctx->stream != NULL && can_apply_seamless_boot)
                        continue;
 
-               if (tg->funcs->is_tg_enabled(tg))
-                       tg->funcs->lock(tg);
-
                /* Blank controller using driver code instead of
                 * command table.
                 */
                if (tg->funcs->is_tg_enabled(tg)) {
+                       tg->funcs->lock(tg);
                        tg->funcs->set_blank(tg, true);
                        hwss_wait_for_blank_complete(tg);
                }