omap4: support TPS programming

TPS62361 is the new power supply used in OMAP4460 that
supplies vdd_mpu.

VCORE1 from Phoenix supplies vdd_core and VCORE2 supplies
vdd_iva. VCORE3 is not used in OMAP4460.

Signed-off-by: Aneesh V <aneesh@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index 3c61b1cc0942a85d3dc632fab276657cc7130725..5943d61fc284d5340c2f43c455298e93da8b2dbe 100644 (file)
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -90,6 +90,10 @@ static void set_muxconf_regs_essential(void)
        do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
                   sizeof(wkup_padconf_array_essential) /
                   sizeof(struct pad_conf_entry));
+
+       /* gpio_wk7 is used for controlling TPS on 4460 */
+       if (omap_revision() >= OMAP4460_ES1_0)
+               writew(M3, CONTROL_WKUP_PAD1_FREF_CLK4_REQ);
 }
 
 static void set_mux_conf_regs(void)

diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c
index 660b32947d19240ff547ee91f74ed70b3a975c81..0db9d18c7037938b6bec9ba15fc726de771022e9 100644 (file)
--- a/arch/arm/cpu/armv7/omap4/clocks.c
+++ b/arch/arm/cpu/armv7/omap4/clocks.c
@@ -34,6 +34,7 @@
 #include <asm/arch/clocks.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/utils.h>
+#include <asm/omap_gpio.h>
 
 #ifndef CONFIG_SPL_BUILD
 /*
@@ -421,6 +422,34 @@ static void setup_non_essential_dplls(void)
        do_setup_dpll(&prcm->cm_clkmode_dpll_abe, params, DPLL_LOCK);
 }
 
+static void do_scale_tps62361(u32 reg, u32 volt_mv)
+{
+       u32 temp, step;
+
+       step = volt_mv - TPS62361_BASE_VOLT_MV;
+       step /= 10;
+
+       /*
+        * Select SET1 in TPS62361:
+        * VSEL1 is grounded on board. So the following selects
+        * VSEL1 = 0 and VSEL0 = 1
+        */
+       omap_set_gpio_direction(TPS62361_VSEL0_GPIO, 0);
+       omap_set_gpio_dataout(TPS62361_VSEL0_GPIO, 1);
+
+       temp = TPS62361_I2C_SLAVE_ADDR |
+           (reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) |
+           (step << PRM_VC_VAL_BYPASS_DATA_SHIFT) |
+           PRM_VC_VAL_BYPASS_VALID_BIT;
+       debug("do_scale_tps62361: volt - %d step - 0x%x\n", volt_mv, step);
+
+       writel(temp, &prcm->prm_vc_val_bypass);
+       if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0,
+                               &prcm->prm_vc_val_bypass, LDELAY)) {
+               puts("Scaling voltage failed for vdd_mpu from TPS\n");
+       }
+}
+
 static void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
 {
        u32 temp, offset_code;
@@ -461,7 +490,7 @@ static void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
  */
 static void scale_vcores(void)
 {
-       u32 volt, sys_clk_khz, cycles_hi, cycles_low, temp;
+       u32 volt, sys_clk_khz, cycles_hi, cycles_low, temp, omap4_rev;
 
        sys_clk_khz = get_sys_clk_freq() / 1000;
 
@@ -481,23 +510,45 @@ static void scale_vcores(void)
        /* Disable high speed mode and all advanced features */
        writel(0x0, &prcm->prm_vc_cfg_i2c_mode);
 
+       omap4_rev = omap_revision();
+       /* TPS - supplies vdd_mpu on 4460 */
+       if (omap4_rev >= OMAP4460_ES1_0) {
+               volt = 1430;
+               do_scale_tps62361(TPS62361_REG_ADDR_SET1, volt);
+       }
+
        /*
-        * VCORE 1 - 4430 : supplies vdd_mpu
+        * VCORE 1
+        *
+        * 4430 : supplies vdd_mpu
         * Setting a high voltage for Nitro mode as smart reflex is not enabled.
         * We use the maximum possible value in the AVS range because the next
         * higher voltage in the discrete range (code >= 0b111010) is way too
         * high
+        *
+        * 4460 : supplies vdd_core
         */
-       volt = 1417;
-       do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
+       if (omap4_rev < OMAP4460_ES1_0) {
+               volt = 1417;
+               do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
+       } else {
+               volt = 1200;
+               do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
+       }
 
        /* VCORE 2 - supplies vdd_iva */
        volt = 1200;
        do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
 
-       /* VCORE 3 - supplies vdd_core */
-       volt = 1200;
-       do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt);
+       /*
+        * VCORE 3
+        * 4430 : supplies vdd_core
+        * 4460 : not connected
+        */
+       if (omap4_rev < OMAP4460_ES1_0) {
+               volt = 1200;
+               do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt);
+       }
 }
 
 static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)

diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h
index 37bdceebedd3d12061e5b8fa8dad68de45568cf4..5d9cb50c698423af555f8d2e5203c84bda3d8fc6 100644 (file)
--- a/arch/arm/include/asm/arch-omap4/clocks.h
+++ b/arch/arm/include/asm/arch-omap4/clocks.h
@@ -618,6 +618,7 @@ struct omap4_prcm_regs {
 #define PRM_VC_VAL_BYPASS_DATA_SHIFT           16
 #define PRM_VC_VAL_BYPASS_DATA_MASK            0xFF
 
+/* SMPS */
 #define SMPS_I2C_SLAVE_ADDR    0x12
 #define SMPS_REG_ADDR_VCORE1   0x55
 #define SMPS_REG_ADDR_VCORE2   0x5B
@@ -626,6 +627,21 @@ struct omap4_prcm_regs {
 #define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV             607700
 #define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000
 
+/* TPS */
+#define TPS62361_I2C_SLAVE_ADDR                0x60
+#define TPS62361_REG_ADDR_SET0         0x0
+#define TPS62361_REG_ADDR_SET1         0x1
+#define TPS62361_REG_ADDR_SET2         0x2
+#define TPS62361_REG_ADDR_SET3         0x3
+#define TPS62361_REG_ADDR_CTRL         0x4
+#define TPS62361_REG_ADDR_TEMP         0x5
+#define TPS62361_REG_ADDR_RMP_CTRL     0x6
+#define TPS62361_REG_ADDR_CHIP_ID      0x8
+#define TPS62361_REG_ADDR_CHIP_ID_2    0x9
+
+#define TPS62361_BASE_VOLT_MV  500
+#define TPS62361_VSEL0_GPIO    7
+
 /* Defines for DPLL setup */
 #define DPLL_LOCKED_FREQ_TOLERANCE_0           0
 #define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ     500

diff --git a/arch/arm/include/asm/arch-omap4/mux_omap4.h b/arch/arm/include/asm/arch-omap4/mux_omap4.h
index 019574b09f5582dd963c6c18a309c162b2409cff..30bfad7c20ff07ef0c407da87e0f1b38b26f5951 100644 (file)
--- a/arch/arm/include/asm/arch-omap4/mux_omap4.h
+++ b/arch/arm/include/asm/arch-omap4/mux_omap4.h
@@ -341,4 +341,5 @@ struct pad_conf_entry {
 #define CONTROL_SPARE_R                0x0618
 #define CONTROL_SPARE_R_C0             0x061C
 
+#define CONTROL_WKUP_PAD1_FREF_CLK4_REQ        0x4A31E05A
 #endif /* _MUX_OMAP4_H_ */