mxs_ocotp: Shift the HBUS divider correctly

When the original HBUS divider value is retrieved in mxs_ocotp_scale_hclk()
for the purpose or restoring it back later, the value is not shifted by the
HBUS divider offset in that register. This is not a problem, since the shift
is zero on all MXS hardware. Add the shift anyway, for completeness and in
case FSL ever decides to re-use this driver on future designs.

Signed-off-by: Chris Smith <chris@zxdesign.info>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/drivers/misc/mxs_ocotp.c b/drivers/misc/mxs_ocotp.c
index 6f0a1d3e6da836c84ef59abc7644ca9adfda3830..6c0d247ed22021cb022cd923bb2139ce94a7991d 100644 (file)
--- a/drivers/misc/mxs_ocotp.c
+++ b/drivers/misc/mxs_ocotp.c
@@ -152,6 +152,7 @@ static int mxs_ocotp_scale_hclk(bool enter, uint32_t *val)
                /* Return the original HCLK clock speed. */
                *val = readl(&clkctrl_regs->hw_clkctrl_hbus);
                *val &= CLKCTRL_HBUS_DIV_MASK;
+               *val >>= CLKCTRL_HBUS_DIV_OFFSET;
 
                /* Scale the HCLK to 454/19 = 23.9 MHz . */
                scale_val = (~19) << CLKCTRL_HBUS_DIV_OFFSET;