drm/i915: HSW/BDW PSR Set idle_frames = VBT + 1

Let's use VBT + 1 now we parse it.

v2: fix subject

v3: rebase over intel_psr and without counting on previous fix

Cc: Arthur Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Durgadoss R <durgadoss.r@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 716b8a961eea9ae7a0d3e743cfab4caafdceb713..576568eb075925a8f39e2a626a414af23ffd3d36 100644 (file)
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -163,7 +163,12 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp)
        struct drm_device *dev = dig_port->base.base.dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        uint32_t max_sleep_time = 0x1f;
-       uint32_t idle_frames = 1;
+       /* Lately it was identified that depending on panel idle frame count
+        * calculated at HW can be off by 1. So let's use what came
+        * from VBT + 1 and at minimum 2 to be on the safe side.
+        */
+       uint32_t idle_frames = dev_priv->vbt.psr.idle_frames ?
+                              dev_priv->vbt.psr.idle_frames + 1 : 2;
        uint32_t val = 0x0;
        const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
        bool only_standby = false;