[MIPS] Initialize CP0 Cause before setting up CP0 Status register

Without this change, we'll be suffering from deffered WATCH exception
once Status.EXL is cleared. Make sure Cause.WP is cleared.

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>

diff --git a/cpu/mips/start.S b/cpu/mips/start.S
index fde2944a0dd46eeffe2f9c0c86eb9462991ab325..0ecdd83636e9b0ad36ca7530899277b2d6cdd50e 100644 (file)
--- a/cpu/mips/start.S
+++ b/cpu/mips/start.S
@@ -211,6 +211,9 @@ reset:
        mtc0    zero, CP0_WATCHLO
        mtc0    zero, CP0_WATCHHI
 
+       /* WP(Watch Pending), SW0/1 should be cleared. */
+       mtc0    zero, CP0_CAUSE
+
        /* STATUS register */
 #ifdef  CONFIG_TB0229
        li      k0, ST0_CU0
@@ -221,9 +224,6 @@ reset:
        and     k0, k1
        mtc0    k0, CP0_STATUS
 
-       /* CAUSE register */
-       mtc0    zero, CP0_CAUSE
-
        /* Init Timer */
        mtc0    zero, CP0_COUNT
        mtc0    zero, CP0_COMPARE