drm/amdgpu/gfx9: Add gfx config for vega20. (v4)

v2: clean up (Alex)
v3: additional cleanups (Alex)
v4: drop leftover TODO (Alex)

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 37492791a8f8aa39aab931e41208d93f9445a268..8335d98a3f3b0b864e15a7cff17a30bf0bfe351f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1137,6 +1137,16 @@ static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
                gb_addr_config = VEGA12_GB_ADDR_CONFIG_GOLDEN;
                DRM_INFO("fix gfx.config for vega12\n");
                break;
+       case CHIP_VEGA20:
+               adev->gfx.config.max_hw_contexts = 8;
+               adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
+               adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
+               adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
+               adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
+               gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
+               gb_addr_config &= ~0xf3e777ff;
+               gb_addr_config |= 0x22014042;
+               break;
        case CHIP_RAVEN:
                adev->gfx.config.max_hw_contexts = 8;
                adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;