ARM: dts: sun6i: Update A31/A31s dts(i) files from Linux-v4.18-rc3

Update all A31/A31s devicetree dtsi and dtsi files from
Linux-v4.18-rc3 with below commit:
commit b240b419db5d624ce7a5a397d6f62a1a686009ec
Merge: 9c2dd8405c0c 518d2f43c358
Author: Linus Torvalds <torvalds@linux-foundation.org>
Date:   Thu Apr 5 21:18:09 2018 -0700

    Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

diff --git a/arch/arm/dts/sun6i-a31-app4-evb1.dts b/arch/arm/dts/sun6i-a31-app4-evb1.dts
index 2f8cfab771e234487edcebd23c22b0aa24bac1fd..7f34323a668c41b29066aabce9423b31bdb16094 100644 (file)
--- a/arch/arm/dts/sun6i-a31-app4-evb1.dts
+++ b/arch/arm/dts/sun6i-a31-app4-evb1.dts
@@ -47,7 +47,6 @@
 #include "sunxi-common-regulators.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
        model = "Allwinner A31 APP4 EVB1 Evaluation Board";
@@ -68,10 +67,8 @@
 
 &pio {
        usb1_vbus_pin_a: usb1_vbus_pin@0 {
-               allwinner,pins = "PH27";
-               allwinner,function = "gpio_out";
-               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+               pins = "PH27";
+               function = "gpio_out";
        };
 };
 

diff --git a/arch/arm/dts/sun6i-a31-colombus.dts b/arch/arm/dts/sun6i-a31-colombus.dts
index f9cf36888d93a6f3673d563dbc6f8cb25ad882df..939c497a6f7003957a287f13cdbf8b43490c4ef2 100644 (file)
--- a/arch/arm/dts/sun6i-a31-colombus.dts
+++ b/arch/arm/dts/sun6i-a31-colombus.dts
@@ -47,7 +47,6 @@
 #include "sunxi-common-regulators.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
        model = "WITS A31 Colombus Evaluation Board";
@@ -118,35 +117,30 @@
        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_colombus>;
        vmmc-supply = <&reg_vcc3v0>;
        bus-width = <4>;
-       cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */
-       cd-inverted;
+       cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */
        status = "okay";
 };
 
 &mmc0_pins_a {
-       allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+       bias-pull-up;
 };
 
 &pio {
        mmc0_cd_pin_colombus: mmc0_cd_pin@0 {
-               allwinner,pins = "PA8";
-               allwinner,function = "gpio_in";
-               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-               allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+               pins = "PA8";
+               function = "gpio_in";
+               bias-pull-up;
        };
 
        usb2_vbus_pin_colombus: usb2_vbus_pin@0 {
-               allwinner,pins = "PH24";
-               allwinner,function = "gpio_out";
-               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+               pins = "PH24";
+               function = "gpio_out";
        };
 
        i2c_lcd_pins: i2c_lcd_pin@0 {
-               allwinner,pins = "PA23", "PA24";
-               allwinner,function = "gpio_out";
-               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-               allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+               pins = "PA23", "PA24";
+               function = "gpio_out";
+               bias-pull-up;
        };
 };
 

diff --git a/arch/arm/dts/sun6i-a31-hummingbird.dts b/arch/arm/dts/sun6i-a31-hummingbird.dts
index 9a74637f677f3481c0ec615a2266b37ec08186d4..ce4f9e9834bf1de946984532494e466a79fbd045 100644 (file)
--- a/arch/arm/dts/sun6i-a31-hummingbird.dts
+++ b/arch/arm/dts/sun6i-a31-hummingbird.dts
@@ -47,7 +47,6 @@
 #include "sunxi-common-regulators.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
        model = "Merrii A31 Hummingbird";
@@ -63,16 +62,98 @@
                stdout-path = "serial0:115200n8";
        };
 
+       hdmi-connector {
+               compatible = "hdmi-connector";
+               type = "a";
+
+               port {
+                       hdmi_con_in: endpoint {
+                               remote-endpoint = <&hdmi_out_con>;
+                       };
+               };
+       };
+
+       vga-connector {
+               compatible = "vga-connector";
+
+               port {
+                       vga_con_in: endpoint {
+                               remote-endpoint = <&vga_dac_out>;
+                       };
+               };
+       };
+
+       vga-dac {
+               compatible = "dumb-vga-dac";
+               vdd-supply = <&reg_vga_3v3>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@0 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               reg = <0>;
+
+                               vga_dac_in: endpoint@0 {
+                                       reg = <0>;
+                                       remote-endpoint = <&tcon0_out_vga>;
+                               };
+                       };
+
+                       port@1 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               reg = <1>;
+
+                               vga_dac_out: endpoint@0 {
+                                       reg = <0>;
+                                       remote-endpoint = <&vga_con_in>;
+                               };
+                       };
+               };
+       };
+
+       reg_vga_3v3: vga_3v3_regulator {
+               compatible = "regulator-fixed";
+               regulator-name = "vga-3v3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-boot-on;
+               enable-active-high;
+               gpio = <&pio 7 25 GPIO_ACTIVE_HIGH>; /* PH25 */
+       };
+
        wifi_pwrseq: wifi_pwrseq {
                compatible = "mmc-pwrseq-simple";
                reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 */
        };
 };
 
+&codec {
+       allwinner,audio-routing =
+               "Headphone", "HP",
+               "Speaker", "LINEOUT",
+               "LINEIN", "Line In",
+               "MIC1", "Mic",
+               "MIC2", "Headset Mic",
+               "Mic",  "MBIAS",
+               "Headset Mic", "HBIAS";
+       allwinner,pa-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */
+       status = "okay";
+};
+
 &cpu0 {
        cpu-supply = <&reg_dcdc3>;
 };
 
+&de {
+       status = "okay";
+};
+
 &ehci0 {
        status = "okay";
 };
@@ -92,6 +173,16 @@
        };
 };
 
+&hdmi {
+       status = "okay";
+};
+
+&hdmi_out {
+       hdmi_out_con: endpoint {
+               remote-endpoint = <&hdmi_con_in>;
+       };
+};
+
 &i2c0 {
        pinctrl-names = "default";
        pinctrl-0 = <&i2c0_pins_a>;
@@ -127,14 +218,13 @@
        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_hummingbird>;
        vmmc-supply = <&reg_dcdc1>;
        bus-width = <4>;
-       cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */
-       cd-inverted;
+       cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */
        status = "okay";
 };
 
 &mmc0_pins_a {
        /* external pull-ups missing for some pins */
-       allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+       bias-pull-up;
 };
 
 &mmc1 {
@@ -153,24 +243,19 @@
 
 &pio {
        gmac_phy_reset_pin_hummingbird: gmac_phy_reset_pin@0 {
-               allwinner,pins = "PA21";
-               allwinner,function = "gpio_out";
-               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+               pins = "PA21";
+               function = "gpio_out";
        };
 
        mmc0_cd_pin_hummingbird: mmc0_cd_pin@0 {
-               allwinner,pins = "PA8";
-               allwinner,function = "gpio_in";
-               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-               allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+               pins = "PA8";
+               function = "gpio_in";
+               bias-pull-up;
        };
 
        wifi_reset_pin_hummingbird: wifi_reset_pin@0 {
-               allwinner,pins = "PG10";
-               allwinner,function = "gpio_out";
-               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+               pins = "PG10";
+               function = "gpio_out";
        };
 };
 
@@ -182,11 +267,16 @@
                reg = <0x68>;
                interrupt-parent = <&nmi_intc>;
                interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+               x-powers,drive-vbus-en;
        };
 };
 
 #include "axp22x.dtsi"
 
+&ac_power_supply {
+       status = "okay";
+};
+
 &reg_aldo1 {
        regulator-min-microvolt = <3300000>;
        regulator-max-microvolt = <3300000>;
@@ -240,23 +330,48 @@
        regulator-name = "vcc-dram";
 };
 
+&reg_drivevbus {
+       regulator-name = "usb0-vbus";
+       status = "okay";
+};
+
 &reg_usb1_vbus {
        gpio = <&pio 7 24 GPIO_ACTIVE_HIGH>; /* PH24 */
        status = "okay";
 };
 
+&tcon0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&lcd0_rgb888_pins>;
+};
+
+&tcon0_out {
+       tcon0_out_vga: endpoint@0 {
+               reg = <0>;
+               remote-endpoint = <&vga_dac_in>;
+       };
+};
+
 &uart0 {
        pinctrl-names = "default";
        pinctrl-0 = <&uart0_pins_a>;
        status = "okay";
 };
 
-&usb1_vbus_pin_a {
-       /* different pin from sunxi-common-regulators */
-       allwinner,pins = "PH24";
+&usb_otg {
+       dr_mode = "otg";
+       status = "okay";
+};
+
+&usb_power_supply {
+       status = "okay";
 };
 
 &usbphy {
+       usb0_id_det-gpio = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */
+       usb0_vbus_det-gpio = <&pio 0 16 GPIO_ACTIVE_HIGH>; /* PA16 */
+       usb0_vbus_power-supply = <&usb_power_supply>;
+       usb0_vbus-supply = <&reg_drivevbus>;
        usb1_vbus-supply = <&reg_usb1_vbus>;
        status = "okay";
 };

diff --git a/arch/arm/dts/sun6i-a31-i7.dts b/arch/arm/dts/sun6i-a31-i7.dts
index e9185dad67ee607f4b8b61287b042d22d9ae01c4..d659be9dbc507d2eb1b3e4327e78f28739efc169 100644 (file)
--- a/arch/arm/dts/sun6i-a31-i7.dts
+++ b/arch/arm/dts/sun6i-a31-i7.dts
@@ -45,7 +45,6 @@
 #include "sunxi-common-regulators.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
        model = "Mele I7 Quad top set box";
@@ -59,6 +58,17 @@
                stdout-path = "serial0:115200n8";
        };
 
+       hdmi-connector {
+               compatible = "hdmi-connector";
+               type = "a";
+
+               port {
+                       hdmi_con_in: endpoint {
+                               remote-endpoint = <&hdmi_out_con>;
+                       };
+               };
+       };
+
        leds {
                compatible = "gpio-leds";
                pinctrl-names = "default";
@@ -69,6 +79,33 @@
                        gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>;
                };
        };
+
+       sound {
+               compatible = "simple-audio-card";
+               simple-audio-card,name = "On-board SPDIF";
+               simple-audio-card,cpu {
+                       sound-dai = <&spdif>;
+               };
+
+               simple-audio-card,codec {
+                       sound-dai = <&spdif_out>;
+               };
+       };
+
+       spdif_out: spdif-out {
+               #sound-dai-cells = <0>;
+               compatible = "linux,spdif-dit";
+       };
+};
+
+&codec {
+       allwinner,audio-routing =
+               "Headphone", "HP";
+       status = "okay";
+};
+
+&de {
+       status = "okay";
 };
 
 &ehci0 {
@@ -91,6 +128,16 @@
        };
 };
 
+&hdmi {
+       status = "okay";
+};
+
+&hdmi_out {
+       hdmi_out_con: endpoint {
+               remote-endpoint = <&hdmi_con_in>;
+       };
+};
+
 &ir {
        pinctrl-names = "default";
        pinctrl-0 = <&ir_pins_a>;
@@ -102,31 +149,25 @@
        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_i7>;
        vmmc-supply = <&reg_vcc3v3>;
        bus-width = <4>;
-       cd-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */
-       cd-inverted;
+       cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */
        status = "okay";
 };
 
 &pio {
        led_pins_i7: led_pins@0 {
-               allwinner,pins = "PH13";
-               allwinner,function = "gpio_out";
-               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+               pins = "PH13";
+               function = "gpio_out";
        };
 
        mmc0_cd_pin_i7: mmc0_cd_pin@0 {
-               allwinner,pins = "PH22";
-               allwinner,function = "gpio_in";
-               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-               allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+               pins = "PH22";
+               function = "gpio_in";
+               bias-pull-up;
        };
 
        usb1_vbus_pin_i7: usb1_vbus_pin@0 {
-               allwinner,pins = "PC27";
-               allwinner,function = "gpio_out";
-               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+               pins = "PC27";
+               function = "gpio_out";
        };
 };
 
@@ -137,6 +178,17 @@
        status = "okay";
 };
 
+&spdif {
+       pinctrl-names = "default";
+       pinctrl-0 = <&spdif_pins_a>;
+       spdif-out = "okay";
+       status = "okay";
+};
+
+&tcon0 {
+       status = "okay";
+};
+
 &uart0 {
        pinctrl-names = "default";
        pinctrl-0 = <&uart0_pins_a>;

diff --git a/arch/arm/dts/sun6i-a31-m9.dts b/arch/arm/dts/sun6i-a31-m9.dts
index 29016a13a2c1e7b25438951f836add9d2f818b87..9698f6d38d030739d240b94198ddfc8c514748f0 100644 (file)
--- a/arch/arm/dts/sun6i-a31-m9.dts
+++ b/arch/arm/dts/sun6i-a31-m9.dts
@@ -45,7 +45,6 @@
 #include "sunxi-common-regulators.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
        model = "Mele M9 top set box";
@@ -108,8 +107,7 @@
        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_m9>;
        vmmc-supply = <&reg_dcdc1>;
        bus-width = <4>;
-       cd-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */
-       cd-inverted;
+       cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */
        status = "okay";
 };
 
@@ -128,24 +126,19 @@
 
 &pio {
        led_pins_m9: led_pins@0 {
-               allwinner,pins = "PH13";
-               allwinner,function = "gpio_out";
-               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+               pins = "PH13";
+               function = "gpio_out";
        };
 
        mmc0_cd_pin_m9: mmc0_cd_pin@0 {
-               allwinner,pins = "PH22";
-               allwinner,function = "gpio_in";
-               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-               allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+               pins = "PH22";
+               function = "gpio_in";
+               bias-pull-up;
        };
 
        usb1_vbus_pin_m9: usb1_vbus_pin@0 {
-               allwinner,pins = "PC27";
-               allwinner,function = "gpio_out";
-               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+               pins = "PC27";
+               function = "gpio_out";
        };
 };
 

diff --git a/arch/arm/dts/sun6i-a31-mele-a1000g-quad.dts b/arch/arm/dts/sun6i-a31-mele-a1000g-quad.dts
index 5faeae429e2aa15eb667d6d723fc6be5520b8f54..bb14b171b1609dfd7121bdad428f0f36eb80d523 100644 (file)
--- a/arch/arm/dts/sun6i-a31-mele-a1000g-quad.dts
+++ b/arch/arm/dts/sun6i-a31-mele-a1000g-quad.dts
@@ -45,7 +45,6 @@
 #include "sunxi-common-regulators.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
        model = "Mele A1000G Quad top set box";
@@ -108,8 +107,7 @@
        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_m9>;
        vmmc-supply = <&reg_dcdc1>;
        bus-width = <4>;
-       cd-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */
-       cd-inverted;
+       cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */
        status = "okay";
 };
 
@@ -128,24 +126,19 @@
 
 &pio {
        led_pins_m9: led_pins@0 {
-               allwinner,pins = "PH13";
-               allwinner,function = "gpio_out";
-               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+               pins = "PH13";
+               function = "gpio_out";
        };
 
        mmc0_cd_pin_m9: mmc0_cd_pin@0 {
-               allwinner,pins = "PH22";
-               allwinner,function = "gpio_in";
-               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-               allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+               pins = "PH22";
+               function = "gpio_in";
+               bias-pull-up;
        };
 
        usb1_vbus_pin_m9: usb1_vbus_pin@0 {
-               allwinner,pins = "PC27";
-               allwinner,function = "gpio_out";
-               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+               pins = "PC27";
+               function = "gpio_out";
        };
 };
 

diff --git a/arch/arm/dts/sun6i-a31.dtsi b/arch/arm/dts/sun6i-a31.dtsi
index b674bf79bcd7f1f52742b2337863e5e9b062bd59..c72992556a86857098deca7ff69a84379d27c6bf 100644 (file)
--- a/arch/arm/dts/sun6i-a31.dtsi
+++ b/arch/arm/dts/sun6i-a31.dtsi
@@ -47,7 +47,8 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/thermal/thermal.h>
 
-#include <dt-bindings/pinctrl/sun4i-a10.h>
+#include <dt-bindings/clock/sun6i-a31-ccu.h>
+#include <dt-bindings/reset/sun6i-a31-ccu.h>
 
 / {
        interrupt-parent = <&gic>;
@@ -65,7 +66,10 @@
                        compatible = "allwinner,simple-framebuffer",
                                     "simple-framebuffer";
                        allwinner,pipeline = "de_be0-lcd0-hdmi";
-                       clocks = <&pll6 0>;
+                       clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
+                                <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>,
+                                <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>,
+                                <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>;
                        status = "disabled";
                };
 
@@ -73,7 +77,9 @@
                        compatible = "allwinner,simple-framebuffer",
                                     "simple-framebuffer";
                        allwinner,pipeline = "de_be0-lcd0";
-                       clocks = <&pll6 0>;
+                       clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
+                                <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>,
+                                <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>;
                        status = "disabled";
                };
        };
@@ -97,7 +103,7 @@
                        compatible = "arm,cortex-a7";
                        device_type = "cpu";
                        reg = <0>;
-                       clocks = <&cpu>;
+                       clocks = <&ccu CLK_CPU>;
                        clock-latency = <244144>; /* 8 32k periods */
                        operating-points = <
                                /* kHz    uV */
@@ -107,8 +113,6 @@
                                480000  1000000
                                >;
                        #cooling-cells = <2>;
-                       cooling-min-level = <0>;
-                       cooling-max-level = <3>;
                };
 
                cpu@1 {
@@ -192,235 +196,6 @@
                        clock-output-names = "osc32k";
                };
 
-               pll1: clk@01c20000 {
-                       #clock-cells = <0>;
-                       compatible = "allwinner,sun6i-a31-pll1-clk";
-                       reg = <0x01c20000 0x4>;
-                       clocks = <&osc24M>;
-                       clock-output-names = "pll1";
-               };
-
-               pll6: clk@01c20028 {
-                       #clock-cells = <1>;
-                       compatible = "allwinner,sun6i-a31-pll6-clk";
-                       reg = <0x01c20028 0x4>;
-                       clocks = <&osc24M>;
-                       clock-output-names = "pll6", "pll6x2";
-               };
-
-               cpu: cpu@01c20050 {
-                       #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-a10-cpu-clk";
-                       reg = <0x01c20050 0x4>;
-
-                       /*
-                        * PLL1 is listed twice here.
-                        * While it looks suspicious, it's actually documented
-                        * that way both in the datasheet and in the code from
-                        * Allwinner.
-                        */
-                       clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
-                       clock-output-names = "cpu";
-               };
-
-               axi: axi@01c20050 {
-                       #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-a10-axi-clk";
-                       reg = <0x01c20050 0x4>;
-                       clocks = <&cpu>;
-                       clock-output-names = "axi";
-               };
-
-               ahb1: ahb1@01c20054 {
-                       #clock-cells = <0>;
-                       compatible = "allwinner,sun6i-a31-ahb1-clk";
-                       reg = <0x01c20054 0x4>;
-                       clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
-                       clock-output-names = "ahb1";
-
-                       /*
-                        * Clock AHB1 from PLL6, instead of CPU/AXI which
-                        * has rate changes due to cpufreq. Also the DMA
-                        * controller requires AHB1 clocked from PLL6.
-                        */
-                       assigned-clocks = <&ahb1>;
-                       assigned-clock-parents = <&pll6 0>;
-               };
-
-               ahb1_gates: clk@01c20060 {
-                       #clock-cells = <1>;
-                       compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
-                       reg = <0x01c20060 0x8>;
-                       clocks = <&ahb1>;
-                       clock-indices = <1>, <5>,
-                                       <6>, <8>, <9>,
-                                       <10>, <11>, <12>,
-                                       <13>, <14>,
-                                       <17>, <18>, <19>,
-                                       <20>, <21>, <22>,
-                                       <23>, <24>, <26>,
-                                       <27>, <29>,
-                                       <30>, <31>, <32>,
-                                       <36>, <37>, <40>,
-                                       <43>, <44>, <45>,
-                                       <46>, <47>, <50>,
-                                       <52>, <55>, <56>,
-                                       <57>, <58>;
-                       clock-output-names = "ahb1_mipidsi", "ahb1_ss",
-                                       "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
-                                       "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
-                                       "ahb1_nand0", "ahb1_sdram",
-                                       "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
-                                       "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
-                                       "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
-                                       "ahb1_ehci1", "ahb1_ohci0",
-                                       "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
-                                       "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
-                                       "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
-                                       "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
-                                       "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
-                                       "ahb1_drc0", "ahb1_drc1";
-               };
-
-               apb1: apb1@01c20054 {
-                       #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-a10-apb0-clk";
-                       reg = <0x01c20054 0x4>;
-                       clocks = <&ahb1>;
-                       clock-output-names = "apb1";
-               };
-
-               apb1_gates: clk@01c20068 {
-                       #clock-cells = <1>;
-                       compatible = "allwinner,sun6i-a31-apb1-gates-clk";
-                       reg = <0x01c20068 0x4>;
-                       clocks = <&apb1>;
-                       clock-indices = <0>, <4>,
-                                       <5>, <12>,
-                                       <13>;
-                       clock-output-names = "apb1_codec", "apb1_digital_mic",
-                                       "apb1_pio", "apb1_daudio0",
-                                       "apb1_daudio1";
-               };
-
-               apb2: clk@01c20058 {
-                       #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-a10-apb1-clk";
-                       reg = <0x01c20058 0x4>;
-                       clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
-                       clock-output-names = "apb2";
-               };
-
-               apb2_gates: clk@01c2006c {
-                       #clock-cells = <1>;
-                       compatible = "allwinner,sun6i-a31-apb2-gates-clk";
-                       reg = <0x01c2006c 0x4>;
-                       clocks = <&apb2>;
-                       clock-indices = <0>, <1>,
-                                       <2>, <3>, <16>,
-                                       <17>, <18>, <19>,
-                                       <20>, <21>;
-                       clock-output-names = "apb2_i2c0", "apb2_i2c1",
-                                            "apb2_i2c2", "apb2_i2c3",
-                                            "apb2_uart0", "apb2_uart1",
-                                            "apb2_uart2", "apb2_uart3",
-                                            "apb2_uart4", "apb2_uart5";
-               };
-
-               mmc0_clk: clk@01c20088 {
-                       #clock-cells = <1>;
-                       compatible = "allwinner,sun4i-a10-mmc-clk";
-                       reg = <0x01c20088 0x4>;
-                       clocks = <&osc24M>, <&pll6 0>;
-                       clock-output-names = "mmc0",
-                                            "mmc0_output",
-                                            "mmc0_sample";
-               };
-
-               mmc1_clk: clk@01c2008c {
-                       #clock-cells = <1>;
-                       compatible = "allwinner,sun4i-a10-mmc-clk";
-                       reg = <0x01c2008c 0x4>;
-                       clocks = <&osc24M>, <&pll6 0>;
-                       clock-output-names = "mmc1",
-                                            "mmc1_output",
-                                            "mmc1_sample";
-               };
-
-               mmc2_clk: clk@01c20090 {
-                       #clock-cells = <1>;
-                       compatible = "allwinner,sun4i-a10-mmc-clk";
-                       reg = <0x01c20090 0x4>;
-                       clocks = <&osc24M>, <&pll6 0>;
-                       clock-output-names = "mmc2",
-                                            "mmc2_output",
-                                            "mmc2_sample";
-               };
-
-               mmc3_clk: clk@01c20094 {
-                       #clock-cells = <1>;
-                       compatible = "allwinner,sun4i-a10-mmc-clk";
-                       reg = <0x01c20094 0x4>;
-                       clocks = <&osc24M>, <&pll6 0>;
-                       clock-output-names = "mmc3",
-                                            "mmc3_output",
-                                            "mmc3_sample";
-               };
-
-               ss_clk: clk@01c2009c {
-                       #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-a10-mod0-clk";
-                       reg = <0x01c2009c 0x4>;
-                       clocks = <&osc24M>, <&pll6 0>;
-                       clock-output-names = "ss";
-               };
-
-               spi0_clk: clk@01c200a0 {
-                       #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-a10-mod0-clk";
-                       reg = <0x01c200a0 0x4>;
-                       clocks = <&osc24M>, <&pll6 0>;
-                       clock-output-names = "spi0";
-               };
-
-               spi1_clk: clk@01c200a4 {
-                       #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-a10-mod0-clk";
-                       reg = <0x01c200a4 0x4>;
-                       clocks = <&osc24M>, <&pll6 0>;
-                       clock-output-names = "spi1";
-               };
-
-               spi2_clk: clk@01c200a8 {
-                       #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-a10-mod0-clk";
-                       reg = <0x01c200a8 0x4>;
-                       clocks = <&osc24M>, <&pll6 0>;
-                       clock-output-names = "spi2";
-               };
-
-               spi3_clk: clk@01c200ac {
-                       #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-a10-mod0-clk";
-                       reg = <0x01c200ac 0x4>;
-                       clocks = <&osc24M>, <&pll6 0>;
-                       clock-output-names = "spi3";
-               };
-
-               usb_clk: clk@01c200cc {
-                       #clock-cells = <1>;
-                       #reset-cells = <1>;
-                       compatible = "allwinner,sun6i-a31-usb-clk";
-                       reg = <0x01c200cc 0x4>;
-                       clocks = <&osc24M>;
-                       clock-indices = <8>, <9>, <10>,
-                                       <16>, <17>,
-                                       <18>;
-                       clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
-                                            "usb_ohci0", "usb_ohci1",
-                                            "usb_ohci2";
-               };
-
                /*
                 * The following two are dummy clocks, placeholders
                 * used in the gmac_tx clock. The gmac driver will
@@ -444,7 +219,7 @@
                        clock-output-names = "gmac_int_tx";
                };
 
-               gmac_tx_clk: clk@01c200d0 {
+               gmac_tx_clk: clk@1c200d0 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun7i-a20-gmac-clk";
                        reg = <0x01c200d0 0x4>;
@@ -453,34 +228,135 @@
                };
        };
 
-       soc@01c00000 {
+       de: display-engine {
+               compatible = "allwinner,sun6i-a31-display-engine";
+               allwinner,pipelines = <&fe0>, <&fe1>;
+               status = "disabled";
+       };
+
+       soc@1c00000 {
                compatible = "simple-bus";
                #address-cells = <1>;
                #size-cells = <1>;
                ranges;
 
-               dma: dma-controller@01c02000 {
+               dma: dma-controller@1c02000 {
                        compatible = "allwinner,sun6i-a31-dma";
                        reg = <0x01c02000 0x1000>;
                        interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&ahb1_gates 6>;
-                       resets = <&ahb1_rst 6>;
+                       clocks = <&ccu CLK_AHB1_DMA>;
+                       resets = <&ccu RST_AHB1_DMA>;
                        #dma-cells = <1>;
                };
 
-               mmc0: mmc@01c0f000 {
-                       compatible = "allwinner,sun7i-a20-mmc",
-                                    "allwinner,sun5i-a13-mmc";
+               tcon0: lcd-controller@1c0c000 {
+                       compatible = "allwinner,sun6i-a31-tcon";
+                       reg = <0x01c0c000 0x1000>;
+                       interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+                       resets = <&ccu RST_AHB1_LCD0>;
+                       reset-names = "lcd";
+                       clocks = <&ccu CLK_AHB1_LCD0>,
+                                <&ccu CLK_LCD0_CH0>,
+                                <&ccu CLK_LCD0_CH1>;
+                       clock-names = "ahb",
+                                     "tcon-ch0",
+                                     "tcon-ch1";
+                       clock-output-names = "tcon0-pixel-clock";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               tcon0_in: port@0 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       reg = <0>;
+
+                                       tcon0_in_drc0: endpoint@0 {
+                                               reg = <0>;
+                                               remote-endpoint = <&drc0_out_tcon0>;
+                                       };
+
+                                       tcon0_in_drc1: endpoint@1 {
+                                               reg = <1>;
+                                               remote-endpoint = <&drc1_out_tcon0>;
+                                       };
+                               };
+
+                               tcon0_out: port@1 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       reg = <1>;
+
+                                       tcon0_out_hdmi: endpoint@1 {
+                                               reg = <1>;
+                                               remote-endpoint = <&hdmi_in_tcon0>;
+                                               allwinner,tcon-channel = <1>;
+                                       };
+                               };
+                       };
+               };
+
+               tcon1: lcd-controller@1c0d000 {
+                       compatible = "allwinner,sun6i-a31-tcon";
+                       reg = <0x01c0d000 0x1000>;
+                       interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+                       resets = <&ccu RST_AHB1_LCD1>;
+                       reset-names = "lcd";
+                       clocks = <&ccu CLK_AHB1_LCD1>,
+                                <&ccu CLK_LCD1_CH0>,
+                                <&ccu CLK_LCD1_CH1>;
+                       clock-names = "ahb",
+                                     "tcon-ch0",
+                                     "tcon-ch1";
+                       clock-output-names = "tcon1-pixel-clock";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               tcon1_in: port@0 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       reg = <0>;
+
+                                       tcon1_in_drc0: endpoint@0 {
+                                               reg = <0>;
+                                               remote-endpoint = <&drc0_out_tcon1>;
+                                       };
+
+                                       tcon1_in_drc1: endpoint@1 {
+                                               reg = <1>;
+                                               remote-endpoint = <&drc1_out_tcon1>;
+                                       };
+                               };
+
+                               tcon1_out: port@1 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       reg = <1>;
+
+                                       tcon1_out_hdmi: endpoint@1 {
+                                               reg = <1>;
+                                               remote-endpoint = <&hdmi_in_tcon1>;
+                                               allwinner,tcon-channel = <1>;
+                                       };
+                               };
+                       };
+               };
+
+               mmc0: mmc@1c0f000 {
+                       compatible = "allwinner,sun7i-a20-mmc";
                        reg = <0x01c0f000 0x1000>;
-                       clocks = <&ahb1_gates 8>,
-                                <&mmc0_clk 0>,
-                                <&mmc0_clk 1>,
-                                <&mmc0_clk 2>;
+                       clocks = <&ccu CLK_AHB1_MMC0>,
+                                <&ccu CLK_MMC0>,
+                                <&ccu CLK_MMC0_OUTPUT>,
+                                <&ccu CLK_MMC0_SAMPLE>;
                        clock-names = "ahb",
                                      "mmc",
                                      "output",
                                      "sample";
-                       resets = <&ahb1_rst 8>;
+                       resets = <&ccu RST_AHB1_MMC0>;
                        reset-names = "ahb";
                        interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
                        status = "disabled";
@@ -488,19 +364,18 @@
                        #size-cells = <0>;
                };
 
-               mmc1: mmc@01c10000 {
-                       compatible = "allwinner,sun7i-a20-mmc",
-                                    "allwinner,sun5i-a13-mmc";
+               mmc1: mmc@1c10000 {
+                       compatible = "allwinner,sun7i-a20-mmc";
                        reg = <0x01c10000 0x1000>;
-                       clocks = <&ahb1_gates 9>,
-                                <&mmc1_clk 0>,
-                                <&mmc1_clk 1>,
-                                <&mmc1_clk 2>;
+                       clocks = <&ccu CLK_AHB1_MMC1>,
+                                <&ccu CLK_MMC1>,
+                                <&ccu CLK_MMC1_OUTPUT>,
+                                <&ccu CLK_MMC1_SAMPLE>;
                        clock-names = "ahb",
                                      "mmc",
                                      "output",
                                      "sample";
-                       resets = <&ahb1_rst 9>;
+                       resets = <&ccu RST_AHB1_MMC1>;
                        reset-names = "ahb";
                        interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
                        status = "disabled";
@@ -508,19 +383,18 @@
                        #size-cells = <0>;
                };
 
-               mmc2: mmc@01c11000 {
-                       compatible = "allwinner,sun7i-a20-mmc",
-                                    "allwinner,sun5i-a13-mmc";
+               mmc2: mmc@1c11000 {
+                       compatible = "allwinner,sun7i-a20-mmc";
                        reg = <0x01c11000 0x1000>;
-                       clocks = <&ahb1_gates 10>,
-                                <&mmc2_clk 0>,
-                                <&mmc2_clk 1>,
-                                <&mmc2_clk 2>;
+                       clocks = <&ccu CLK_AHB1_MMC2>,
+                                <&ccu CLK_MMC2>,
+                                <&ccu CLK_MMC2_OUTPUT>,
+                                <&ccu CLK_MMC2_SAMPLE>;
                        clock-names = "ahb",
                                      "mmc",
                                      "output",
                                      "sample";
-                       resets = <&ahb1_rst 10>;
+                       resets = <&ccu RST_AHB1_MMC2>;
                        reset-names = "ahb";
                        interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
                        status = "disabled";
@@ -528,19 +402,18 @@
                        #size-cells = <0>;
                };
 
-               mmc3: mmc@01c12000 {
-                       compatible = "allwinner,sun7i-a20-mmc",
-                                    "allwinner,sun5i-a13-mmc";
+               mmc3: mmc@1c12000 {
+                       compatible = "allwinner,sun7i-a20-mmc";
                        reg = <0x01c12000 0x1000>;
-                       clocks = <&ahb1_gates 11>,
-                                <&mmc3_clk 0>,
-                                <&mmc3_clk 1>,
-                                <&mmc3_clk 2>;
+                       clocks = <&ccu CLK_AHB1_MMC3>,
+                                <&ccu CLK_MMC3>,
+                                <&ccu CLK_MMC3_OUTPUT>,
+                                <&ccu CLK_MMC3_SAMPLE>;
                        clock-names = "ahb",
                                      "mmc",
                                      "output",
                                      "sample";
-                       resets = <&ahb1_rst 11>;
+                       resets = <&ccu RST_AHB1_MMC3>;
                        reset-names = "ahb";
                        interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
                        status = "disabled";
@@ -548,11 +421,54 @@
                        #size-cells = <0>;
                };
 
-               usb_otg: usb@01c19000 {
+               hdmi: hdmi@1c16000 {
+                       compatible = "allwinner,sun6i-a31-hdmi";
+                       reg = <0x01c16000 0x1000>;
+                       interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&ccu CLK_AHB1_HDMI>, <&ccu CLK_HDMI>,
+                                <&ccu CLK_HDMI_DDC>,
+                                <&ccu CLK_PLL_VIDEO0_2X>,
+                                <&ccu CLK_PLL_VIDEO1_2X>;
+                       clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1";
+                       resets = <&ccu RST_AHB1_HDMI>;
+                       reset-names = "ahb";
+                       dma-names = "ddc-tx", "ddc-rx", "audio-tx";
+                       dmas = <&dma 13>, <&dma 13>, <&dma 14>;
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               hdmi_in: port@0 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       reg = <0>;
+
+                                       hdmi_in_tcon0: endpoint@0 {
+                                               reg = <0>;
+                                               remote-endpoint = <&tcon0_out_hdmi>;
+                                       };
+
+                                       hdmi_in_tcon1: endpoint@1 {
+                                               reg = <1>;
+                                               remote-endpoint = <&tcon1_out_hdmi>;
+                                       };
+                               };
+
+                               hdmi_out: port@1 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       reg = <1>;
+                               };
+                       };
+               };
+
+               usb_otg: usb@1c19000 {
                        compatible = "allwinner,sun6i-a31-musb";
                        reg = <0x01c19000 0x0400>;
-                       clocks = <&ahb1_gates 24>;
-                       resets = <&ahb1_rst 24>;
+                       clocks = <&ccu CLK_AHB1_OTG>;
+                       resets = <&ccu RST_AHB1_OTG>;
                        interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "mc";
                        phys = <&usbphy 0>;
@@ -561,7 +477,7 @@
                        status = "disabled";
                };
 
-               usbphy: phy@01c19400 {
+               usbphy: phy@1c19400 {
                        compatible = "allwinner,sun6i-a31-usb-phy";
                        reg = <0x01c19400 0x10>,
                              <0x01c1a800 0x4>,
@@ -569,15 +485,15 @@
                        reg-names = "phy_ctrl",
                                    "pmu1",
                                    "pmu2";
-                       clocks = <&usb_clk 8>,
-                                <&usb_clk 9>,
-                                <&usb_clk 10>;
+                       clocks = <&ccu CLK_USB_PHY0>,
+                                <&ccu CLK_USB_PHY1>,
+                                <&ccu CLK_USB_PHY2>;
                        clock-names = "usb0_phy",
                                      "usb1_phy",
                                      "usb2_phy";
-                       resets = <&usb_clk 0>,
-                                <&usb_clk 1>,
-                                <&usb_clk 2>;
+                       resets = <&ccu RST_USB_PHY0>,
+                                <&ccu RST_USB_PHY1>,
+                                <&ccu RST_USB_PHY2>;
                        reset-names = "usb0_reset",
                                      "usb1_reset",
                                      "usb2_reset";
@@ -585,206 +501,202 @@
                        #phy-cells = <1>;
                };
 
-               ehci0: usb@01c1a000 {
+               ehci0: usb@1c1a000 {
                        compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
                        reg = <0x01c1a000 0x100>;
                        interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&ahb1_gates 26>;
-                       resets = <&ahb1_rst 26>;
+                       clocks = <&ccu CLK_AHB1_EHCI0>;
+                       resets = <&ccu RST_AHB1_EHCI0>;
                        phys = <&usbphy 1>;
                        phy-names = "usb";
                        status = "disabled";
                };
 
-               ohci0: usb@01c1a400 {
+               ohci0: usb@1c1a400 {
                        compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
                        reg = <0x01c1a400 0x100>;
                        interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&ahb1_gates 29>, <&usb_clk 16>;
-                       resets = <&ahb1_rst 29>;
+                       clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>;
+                       resets = <&ccu RST_AHB1_OHCI0>;
                        phys = <&usbphy 1>;
                        phy-names = "usb";
                        status = "disabled";
                };
 
-               ehci1: usb@01c1b000 {
+               ehci1: usb@1c1b000 {
                        compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
                        reg = <0x01c1b000 0x100>;
                        interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&ahb1_gates 27>;
-                       resets = <&ahb1_rst 27>;
+                       clocks = <&ccu CLK_AHB1_EHCI1>;
+                       resets = <&ccu RST_AHB1_EHCI1>;
                        phys = <&usbphy 2>;
                        phy-names = "usb";
                        status = "disabled";
                };
 
-               ohci1: usb@01c1b400 {
+               ohci1: usb@1c1b400 {
                        compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
                        reg = <0x01c1b400 0x100>;
                        interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&ahb1_gates 30>, <&usb_clk 17>;
-                       resets = <&ahb1_rst 30>;
+                       clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>;
+                       resets = <&ccu RST_AHB1_OHCI1>;
                        phys = <&usbphy 2>;
                        phy-names = "usb";
                        status = "disabled";
                };
 
-               ohci2: usb@01c1c400 {
+               ohci2: usb@1c1c400 {
                        compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
                        reg = <0x01c1c400 0x100>;
                        interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&ahb1_gates 31>, <&usb_clk 18>;
-                       resets = <&ahb1_rst 31>;
+                       clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>;
+                       resets = <&ccu RST_AHB1_OHCI2>;
                        status = "disabled";
                };
 
-               pio: pinctrl@01c20800 {
+               ccu: clock@1c20000 {
+                       compatible = "allwinner,sun6i-a31-ccu";
+                       reg = <0x01c20000 0x400>;
+                       clocks = <&osc24M>, <&osc32k>;
+                       clock-names = "hosc", "losc";
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+               };
+
+               pio: pinctrl@1c20800 {
                        compatible = "allwinner,sun6i-a31-pinctrl";
                        reg = <0x01c20800 0x400>;
                        interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&apb1_gates 5>;
+                       clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&osc32k>;
+                       clock-names = "apb", "hosc", "losc";
                        gpio-controller;
                        interrupt-controller;
                        #interrupt-cells = <3>;
                        #gpio-cells = <3>;
 
-                       uart0_pins_a: uart0@0 {
-                               allwinner,pins = "PH20", "PH21";
-                               allwinner,function = "uart0";
-                               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-                               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+                       gmac_pins_gmii_a: gmac_gmii@0 {
+                               pins = "PA0", "PA1", "PA2", "PA3",
+                                               "PA4", "PA5", "PA6", "PA7",
+                                               "PA8", "PA9", "PA10", "PA11",
+                                               "PA12", "PA13", "PA14", "PA15",
+                                               "PA16", "PA17", "PA18", "PA19",
+                                               "PA20", "PA21", "PA22", "PA23",
+                                               "PA24", "PA25", "PA26", "PA27";
+                               function = "gmac";
+                               /*
+                                * data lines in GMII mode run at 125MHz and
+                                * might need a higher signal drive strength
+                                */
+                               drive-strength = <30>;
+                       };
+
+                       gmac_pins_mii_a: gmac_mii@0 {
+                               pins = "PA0", "PA1", "PA2", "PA3",
+                                               "PA8", "PA9", "PA11",
+                                               "PA12", "PA13", "PA14", "PA19",
+                                               "PA20", "PA21", "PA22", "PA23",
+                                               "PA24", "PA26", "PA27";
+                               function = "gmac";
+                       };
+
+                       gmac_pins_rgmii_a: gmac_rgmii@0 {
+                               pins = "PA0", "PA1", "PA2", "PA3",
+                                               "PA9", "PA10", "PA11",
+                                               "PA12", "PA13", "PA14", "PA19",
+                                               "PA20", "PA25", "PA26", "PA27";
+                               function = "gmac";
+                               /*
+                                * data lines in RGMII mode use DDR mode
+                                * and need a higher signal drive strength
+                                */
+                               drive-strength = <40>;
                        };
 
                        i2c0_pins_a: i2c0@0 {
-                               allwinner,pins = "PH14", "PH15";
-                               allwinner,function = "i2c0";
-                               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-                               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+                               pins = "PH14", "PH15";
+                               function = "i2c0";
                        };
 
                        i2c1_pins_a: i2c1@0 {
-                               allwinner,pins = "PH16", "PH17";
-                               allwinner,function = "i2c1";
-                               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-                               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+                               pins = "PH16", "PH17";
+                               function = "i2c1";
                        };
 
                        i2c2_pins_a: i2c2@0 {
-                               allwinner,pins = "PH18", "PH19";
-                               allwinner,function = "i2c2";
-                               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-                               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+                               pins = "PH18", "PH19";
+                               function = "i2c2";
+                       };
+
+                       lcd0_rgb888_pins: lcd0_rgb888 {
+                               pins = "PD0", "PD1", "PD2", "PD3",
+                                                "PD4", "PD5", "PD6", "PD7",
+                                                "PD8", "PD9", "PD10", "PD11",
+                                                "PD12", "PD13", "PD14", "PD15",
+                                                "PD16", "PD17", "PD18", "PD19",
+                                                "PD20", "PD21", "PD22", "PD23",
+                                                "PD24", "PD25", "PD26", "PD27";
+                               function = "lcd0";
                        };
 
                        mmc0_pins_a: mmc0@0 {
-                               allwinner,pins = "PF0", "PF1", "PF2",
+                               pins = "PF0", "PF1", "PF2",
                                                 "PF3", "PF4", "PF5";
-                               allwinner,function = "mmc0";
-                               allwinner,drive = <SUN4I_PINCTRL_30_MA>;
-                               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+                               function = "mmc0";
+                               drive-strength = <30>;
+                               bias-pull-up;
                        };
 
                        mmc1_pins_a: mmc1@0 {
-                               allwinner,pins = "PG0", "PG1", "PG2", "PG3",
+                               pins = "PG0", "PG1", "PG2", "PG3",
                                                 "PG4", "PG5";
-                               allwinner,function = "mmc1";
-                               allwinner,drive = <SUN4I_PINCTRL_30_MA>;
-                               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+                               function = "mmc1";
+                               drive-strength = <30>;
+                               bias-pull-up;
                        };
 
                        mmc2_pins_a: mmc2@0 {
-                               allwinner,pins = "PC6", "PC7", "PC8", "PC9",
+                               pins = "PC6", "PC7", "PC8", "PC9",
                                                 "PC10", "PC11";
-                               allwinner,function = "mmc2";
-                               allwinner,drive = <SUN4I_PINCTRL_30_MA>;
-                               allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+                               function = "mmc2";
+                               drive-strength = <30>;
+                               bias-pull-up;
                        };
 
                        mmc2_8bit_emmc_pins: mmc2@1 {
-                               allwinner,pins = "PC6", "PC7", "PC8", "PC9",
+                               pins = "PC6", "PC7", "PC8", "PC9",
                                                 "PC10", "PC11", "PC12",
                                                 "PC13", "PC14", "PC15",
                                                 "PC24";
-                               allwinner,function = "mmc2";
-                               allwinner,drive = <SUN4I_PINCTRL_30_MA>;
-                               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+                               function = "mmc2";
+                               drive-strength = <30>;
+                               bias-pull-up;
                        };
 
                        mmc3_8bit_emmc_pins: mmc3@1 {
-                               allwinner,pins = "PC6", "PC7", "PC8", "PC9",
+                               pins = "PC6", "PC7", "PC8", "PC9",
                                                 "PC10", "PC11", "PC12",
                                                 "PC13", "PC14", "PC15",
                                                 "PC24";
-                               allwinner,function = "mmc3";
-                               allwinner,drive = <SUN4I_PINCTRL_40_MA>;
-                               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+                               function = "mmc3";
+                               drive-strength = <40>;
+                               bias-pull-up;
                        };
 
-                       gmac_pins_mii_a: gmac_mii@0 {
-                               allwinner,pins = "PA0", "PA1", "PA2", "PA3",
-                                               "PA8", "PA9", "PA11",
-                                               "PA12", "PA13", "PA14", "PA19",
-                                               "PA20", "PA21", "PA22", "PA23",
-                                               "PA24", "PA26", "PA27";
-                               allwinner,function = "gmac";
-                               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-                               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-                       };
-
-                       gmac_pins_gmii_a: gmac_gmii@0 {
-                               allwinner,pins = "PA0", "PA1", "PA2", "PA3",
-                                               "PA4", "PA5", "PA6", "PA7",
-                                               "PA8", "PA9", "PA10", "PA11",
-                                               "PA12", "PA13", "PA14", "PA15",
-                                               "PA16", "PA17", "PA18", "PA19",
-                                               "PA20", "PA21", "PA22", "PA23",
-                                               "PA24", "PA25", "PA26", "PA27";
-                               allwinner,function = "gmac";
-                               /*
-                                * data lines in GMII mode run at 125MHz and
-                                * might need a higher signal drive strength
-                                */
-                               allwinner,drive = <SUN4I_PINCTRL_30_MA>;
-                               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+                       spdif_pins_a: spdif@0 {
+                               pins = "PH28";
+                               function = "spdif";
                        };
 
-                       gmac_pins_rgmii_a: gmac_rgmii@0 {
-                               allwinner,pins = "PA0", "PA1", "PA2", "PA3",
-                                               "PA9", "PA10", "PA11",
-                                               "PA12", "PA13", "PA14", "PA19",
-                                               "PA20", "PA25", "PA26", "PA27";
-                               allwinner,function = "gmac";
-                               /*
-                                * data lines in RGMII mode use DDR mode
-                                * and need a higher signal drive strength
-                                */
-                               allwinner,drive = <SUN4I_PINCTRL_40_MA>;
-                               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+                       uart0_pins_a: uart0@0 {
+                               pins = "PH20", "PH21";
+                               function = "uart0";
                        };
                };
 
-               ahb1_rst: reset@01c202c0 {
-                       #reset-cells = <1>;
-                       compatible = "allwinner,sun6i-a31-ahb1-reset";
-                       reg = <0x01c202c0 0xc>;
-               };
-
-               apb1_rst: reset@01c202d0 {
-                       #reset-cells = <1>;
-                       compatible = "allwinner,sun6i-a31-clock-reset";
-                       reg = <0x01c202d0 0x4>;
-               };
-
-               apb2_rst: reset@01c202d8 {
-                       #reset-cells = <1>;
-                       compatible = "allwinner,sun6i-a31-clock-reset";
-                       reg = <0x01c202d8 0x4>;
-               };
-
-               timer@01c20c00 {
+               timer@1c20c00 {
                        compatible = "allwinner,sun4i-a10-timer";
                        reg = <0x01c20c00 0xa0>;
                        interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
@@ -795,155 +707,194 @@
                        clocks = <&osc24M>;
                };
 
-               wdt1: watchdog@01c20ca0 {
+               wdt1: watchdog@1c20ca0 {
                        compatible = "allwinner,sun6i-a31-wdt";
                        reg = <0x01c20ca0 0x20>;
                };
 
-               lradc: lradc@01c22800 {
+               spdif: spdif@1c21000 {
+                       #sound-dai-cells = <0>;
+                       compatible = "allwinner,sun6i-a31-spdif";
+                       reg = <0x01c21000 0x400>;
+                       interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&ccu CLK_APB1_SPDIF>, <&ccu CLK_SPDIF>;
+                       resets = <&ccu RST_APB1_SPDIF>;
+                       clock-names = "apb", "spdif";
+                       dmas = <&dma 2>, <&dma 2>;
+                       dma-names = "rx", "tx";
+                       status = "disabled";
+               };
+
+               i2s0: i2s@1c22000 {
+                       #sound-dai-cells = <0>;
+                       compatible = "allwinner,sun6i-a31-i2s";
+                       reg = <0x01c22000 0x400>;
+                       interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&ccu CLK_APB1_DAUDIO0>, <&ccu CLK_DAUDIO0>;
+                       resets = <&ccu RST_APB1_DAUDIO0>;
+                       clock-names = "apb", "mod";
+                       dmas = <&dma 3>, <&dma 3>;
+                       dma-names = "rx", "tx";
+                       status = "disabled";
+               };
+
+               i2s1: i2s@1c22400 {
+                       #sound-dai-cells = <0>;
+                       compatible = "allwinner,sun6i-a31-i2s";
+                       reg = <0x01c22400 0x400>;
+                       interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&ccu CLK_APB1_DAUDIO1>, <&ccu CLK_DAUDIO1>;
+                       resets = <&ccu RST_APB1_DAUDIO1>;
+                       clock-names = "apb", "mod";
+                       dmas = <&dma 4>, <&dma 4>;
+                       dma-names = "rx", "tx";
+                       status = "disabled";
+               };
+
+               lradc: lradc@1c22800 {
                        compatible = "allwinner,sun4i-a10-lradc-keys";
                        reg = <0x01c22800 0x100>;
                        interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
                        status = "disabled";
                };
 
-               rtp: rtp@01c25000 {
+               rtp: rtp@1c25000 {
                        compatible = "allwinner,sun6i-a31-ts";
                        reg = <0x01c25000 0x100>;
                        interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
                        #thermal-sensor-cells = <0>;
                };
 
-               uart0: serial@01c28000 {
+               uart0: serial@1c28000 {
                        compatible = "snps,dw-apb-uart";
                        reg = <0x01c28000 0x400>;
                        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
                        reg-shift = <2>;
                        reg-io-width = <4>;
-                       clocks = <&apb2_gates 16>;
-                       resets = <&apb2_rst 16>;
+                       clocks = <&ccu CLK_APB2_UART0>;
+                       resets = <&ccu RST_APB2_UART0>;
                        dmas = <&dma 6>, <&dma 6>;
                        dma-names = "rx", "tx";
                        status = "disabled";
                };
 
-               uart1: serial@01c28400 {
+               uart1: serial@1c28400 {
                        compatible = "snps,dw-apb-uart";
                        reg = <0x01c28400 0x400>;
                        interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
                        reg-shift = <2>;
                        reg-io-width = <4>;
-                       clocks = <&apb2_gates 17>;
-                       resets = <&apb2_rst 17>;
+                       clocks = <&ccu CLK_APB2_UART1>;
+                       resets = <&ccu RST_APB2_UART1>;
                        dmas = <&dma 7>, <&dma 7>;
                        dma-names = "rx", "tx";
                        status = "disabled";
                };
 
-               uart2: serial@01c28800 {
+               uart2: serial@1c28800 {
                        compatible = "snps,dw-apb-uart";
                        reg = <0x01c28800 0x400>;
                        interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
                        reg-shift = <2>;
                        reg-io-width = <4>;
-                       clocks = <&apb2_gates 18>;
-                       resets = <&apb2_rst 18>;
+                       clocks = <&ccu CLK_APB2_UART2>;
+                       resets = <&ccu RST_APB2_UART2>;
                        dmas = <&dma 8>, <&dma 8>;
                        dma-names = "rx", "tx";
                        status = "disabled";
                };
 
-               uart3: serial@01c28c00 {
+               uart3: serial@1c28c00 {
                        compatible = "snps,dw-apb-uart";
                        reg = <0x01c28c00 0x400>;
                        interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
                        reg-shift = <2>;
                        reg-io-width = <4>;
-                       clocks = <&apb2_gates 19>;
-                       resets = <&apb2_rst 19>;
+                       clocks = <&ccu CLK_APB2_UART3>;
+                       resets = <&ccu RST_APB2_UART3>;
                        dmas = <&dma 9>, <&dma 9>;
                        dma-names = "rx", "tx";
                        status = "disabled";
                };
 
-               uart4: serial@01c29000 {
+               uart4: serial@1c29000 {
                        compatible = "snps,dw-apb-uart";
                        reg = <0x01c29000 0x400>;
                        interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
                        reg-shift = <2>;
                        reg-io-width = <4>;
-                       clocks = <&apb2_gates 20>;
-                       resets = <&apb2_rst 20>;
+                       clocks = <&ccu CLK_APB2_UART4>;
+                       resets = <&ccu RST_APB2_UART4>;
                        dmas = <&dma 10>, <&dma 10>;
                        dma-names = "rx", "tx";
                        status = "disabled";
                };
 
-               uart5: serial@01c29400 {
+               uart5: serial@1c29400 {
                        compatible = "snps,dw-apb-uart";
                        reg = <0x01c29400 0x400>;
                        interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
                        reg-shift = <2>;
                        reg-io-width = <4>;
-                       clocks = <&apb2_gates 21>;
-                       resets = <&apb2_rst 21>;
+                       clocks = <&ccu CLK_APB2_UART5>;
+                       resets = <&ccu RST_APB2_UART5>;
                        dmas = <&dma 22>, <&dma 22>;
                        dma-names = "rx", "tx";
                        status = "disabled";
                };
 
-               i2c0: i2c@01c2ac00 {
+               i2c0: i2c@1c2ac00 {
                        compatible = "allwinner,sun6i-a31-i2c";
                        reg = <0x01c2ac00 0x400>;
                        interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&apb2_gates 0>;
-                       resets = <&apb2_rst 0>;
+                       clocks = <&ccu CLK_APB2_I2C0>;
+                       resets = <&ccu RST_APB2_I2C0>;
                        status = "disabled";
                        #address-cells = <1>;
                        #size-cells = <0>;
                };
 
-               i2c1: i2c@01c2b000 {
+               i2c1: i2c@1c2b000 {
                        compatible = "allwinner,sun6i-a31-i2c";
                        reg = <0x01c2b000 0x400>;
                        interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&apb2_gates 1>;
-                       resets = <&apb2_rst 1>;
+                       clocks = <&ccu CLK_APB2_I2C1>;
+                       resets = <&ccu RST_APB2_I2C1>;
                        status = "disabled";
                        #address-cells = <1>;
                        #size-cells = <0>;
                };
 
-               i2c2: i2c@01c2b400 {
+               i2c2: i2c@1c2b400 {
                        compatible = "allwinner,sun6i-a31-i2c";
                        reg = <0x01c2b400 0x400>;
                        interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&apb2_gates 2>;
-                       resets = <&apb2_rst 2>;
+                       clocks = <&ccu CLK_APB2_I2C2>;
+                       resets = <&ccu RST_APB2_I2C2>;
                        status = "disabled";
                        #address-cells = <1>;
                        #size-cells = <0>;
                };
 
-               i2c3: i2c@01c2b800 {
+               i2c3: i2c@1c2b800 {
                        compatible = "allwinner,sun6i-a31-i2c";
                        reg = <0x01c2b800 0x400>;
                        interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&apb2_gates 3>;
-                       resets = <&apb2_rst 3>;
+                       clocks = <&ccu CLK_APB2_I2C3>;
+                       resets = <&ccu RST_APB2_I2C3>;
                        status = "disabled";
                        #address-cells = <1>;
                        #size-cells = <0>;
                };
 
-               gmac: ethernet@01c30000 {
+               gmac: ethernet@1c30000 {
                        compatible = "allwinner,sun7i-a20-gmac";
                        reg = <0x01c30000 0x1054>;
                        interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "macirq";
-                       clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
+                       clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>;
                        clock-names = "stmmaceth", "allwinner_gmac_tx";
-                       resets = <&ahb1_rst 17>;
+                       resets = <&ccu RST_AHB1_EMAC>;
                        reset-names = "stmmaceth";
                        snps,pbl = <2>;
                        snps,fixed-burst;
@@ -953,17 +904,31 @@
                        #size-cells = <0>;
                };
 
-               crypto: crypto-engine@01c15000 {
-                       compatible = "allwinner,sun4i-a10-crypto";
+               crypto: crypto-engine@1c15000 {
+                       compatible = "allwinner,sun6i-a31-crypto",
+                                    "allwinner,sun4i-a10-crypto";
                        reg = <0x01c15000 0x1000>;
                        interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&ahb1_gates 5>, <&ss_clk>;
+                       clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>;
                        clock-names = "ahb", "mod";
-                       resets = <&ahb1_rst 5>;
+                       resets = <&ccu RST_AHB1_SS>;
                        reset-names = "ahb";
                };
 
-               timer@01c60000 {
+               codec: codec@1c22c00 {
+                       #sound-dai-cells = <0>;
+                       compatible = "allwinner,sun6i-a31-codec";
+                       reg = <0x01c22c00 0x400>;
+                       interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>;
+                       clock-names = "apb", "codec";
+                       resets = <&ccu RST_APB1_CODEC>;
+                       dmas = <&dma 15>, <&dma 15>;
+                       dma-names = "rx", "tx";
+                       status = "disabled";
+               };
+
+               timer@1c60000 {
                        compatible = "allwinner,sun6i-a31-hstimer",
                                     "allwinner,sun7i-a20-hstimer";
                        reg = <0x01c60000 0x1000>;
@@ -971,62 +936,62 @@
                                     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&ahb1_gates 19>;
-                       resets = <&ahb1_rst 19>;
+                       clocks = <&ccu CLK_AHB1_HSTIMER>;
+                       resets = <&ccu RST_AHB1_HSTIMER>;
                };
 
-               spi0: spi@01c68000 {
+               spi0: spi@1c68000 {
                        compatible = "allwinner,sun6i-a31-spi";
                        reg = <0x01c68000 0x1000>;
                        interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&ahb1_gates 20>, <&spi0_clk>;
+                       clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>;
                        clock-names = "ahb", "mod";
                        dmas = <&dma 23>, <&dma 23>;
                        dma-names = "rx", "tx";
-                       resets = <&ahb1_rst 20>;
+                       resets = <&ccu RST_AHB1_SPI0>;
                        status = "disabled";
                };
 
-               spi1: spi@01c69000 {
+               spi1: spi@1c69000 {
                        compatible = "allwinner,sun6i-a31-spi";
                        reg = <0x01c69000 0x1000>;
                        interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&ahb1_gates 21>, <&spi1_clk>;
+                       clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>;
                        clock-names = "ahb", "mod";
                        dmas = <&dma 24>, <&dma 24>;
                        dma-names = "rx", "tx";
-                       resets = <&ahb1_rst 21>;
+                       resets = <&ccu RST_AHB1_SPI1>;
                        status = "disabled";
                };
 
-               spi2: spi@01c6a000 {
+               spi2: spi@1c6a000 {
                        compatible = "allwinner,sun6i-a31-spi";
                        reg = <0x01c6a000 0x1000>;
                        interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&ahb1_gates 22>, <&spi2_clk>;
+                       clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>;
                        clock-names = "ahb", "mod";
                        dmas = <&dma 25>, <&dma 25>;
                        dma-names = "rx", "tx";
-                       resets = <&ahb1_rst 22>;
+                       resets = <&ccu RST_AHB1_SPI2>;
                        status = "disabled";
                };
 
-               spi3: spi@01c6b000 {
+               spi3: spi@1c6b000 {
                        compatible = "allwinner,sun6i-a31-spi";
                        reg = <0x01c6b000 0x1000>;
                        interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&ahb1_gates 23>, <&spi3_clk>;
+                       clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>;
                        clock-names = "ahb", "mod";
                        dmas = <&dma 26>, <&dma 26>;
                        dma-names = "rx", "tx";
-                       resets = <&ahb1_rst 23>;
+                       resets = <&ccu RST_AHB1_SPI3>;
                        status = "disabled";
                };
 
-               gic: interrupt-controller@01c81000 {
+               gic: interrupt-controller@1c81000 {
                        compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
                        reg = <0x01c81000 0x1000>,
-                             <0x01c82000 0x1000>,
+                             <0x01c82000 0x2000>,
                              <0x01c84000 0x2000>,
                              <0x01c86000 0x2000>;
                        interrupt-controller;
@@ -1034,30 +999,279 @@
                        interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
                };
 
-               rtc: rtc@01f00000 {
+               fe0: display-frontend@1e00000 {
+                       compatible = "allwinner,sun6i-a31-display-frontend";
+                       reg = <0x01e00000 0x20000>;
+                       interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>,
+                                <&ccu CLK_DRAM_FE0>;
+                       clock-names = "ahb", "mod",
+                                     "ram";
+                       resets = <&ccu RST_AHB1_FE0>;
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               fe0_out: port@1 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       reg = <1>;
+
+                                       fe0_out_be0: endpoint@0 {
+                                               reg = <0>;
+                                               remote-endpoint = <&be0_in_fe0>;
+                                       };
+
+                                       fe0_out_be1: endpoint@1 {
+                                               reg = <1>;
+                                               remote-endpoint = <&be1_in_fe0>;
+                                       };
+                               };
+                       };
+               };
+
+               fe1: display-frontend@1e20000 {
+                       compatible = "allwinner,sun6i-a31-display-frontend";
+                       reg = <0x01e20000 0x20000>;
+                       interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&ccu CLK_AHB1_FE1>, <&ccu CLK_FE1>,
+                                <&ccu CLK_DRAM_FE1>;
+                       clock-names = "ahb", "mod",
+                                     "ram";
+                       resets = <&ccu RST_AHB1_FE1>;
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               fe1_out: port@1 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       reg = <1>;
+
+                                       fe1_out_be0: endpoint@0 {
+                                               reg = <0>;
+                                               remote-endpoint = <&be0_in_fe1>;
+                                       };
+
+                                       fe1_out_be1: endpoint@1 {
+                                               reg = <1>;
+                                               remote-endpoint = <&be1_in_fe1>;
+                                       };
+                               };
+                       };
+               };
+
+               be1: display-backend@1e40000 {
+                       compatible = "allwinner,sun6i-a31-display-backend";
+                       reg = <0x01e40000 0x10000>;
+                       interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&ccu CLK_AHB1_BE1>, <&ccu CLK_BE1>,
+                                <&ccu CLK_DRAM_BE1>;
+                       clock-names = "ahb", "mod",
+                                     "ram";
+                       resets = <&ccu RST_AHB1_BE1>;
+
+                       assigned-clocks = <&ccu CLK_BE1>;
+                       assigned-clock-rates = <300000000>;
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               be1_in: port@0 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       reg = <0>;
+
+                                       be1_in_fe0: endpoint@0 {
+                                               reg = <0>;
+                                               remote-endpoint = <&fe0_out_be1>;
+                                       };
+
+                                       be1_in_fe1: endpoint@1 {
+                                               reg = <1>;
+                                               remote-endpoint = <&fe1_out_be1>;
+                                       };
+                               };
+
+                               be1_out: port@1 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       reg = <1>;
+
+                                       be1_out_drc1: endpoint@1 {
+                                               reg = <1>;
+                                               remote-endpoint = <&drc1_in_be1>;
+                                       };
+                               };
+                       };
+               };
+
+               drc1: drc@1e50000 {
+                       compatible = "allwinner,sun6i-a31-drc";
+                       reg = <0x01e50000 0x10000>;
+                       interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&ccu CLK_AHB1_DRC1>, <&ccu CLK_IEP_DRC1>,
+                                <&ccu CLK_DRAM_DRC1>;
+                       clock-names = "ahb", "mod",
+                                     "ram";
+                       resets = <&ccu RST_AHB1_DRC1>;
+
+                       assigned-clocks = <&ccu CLK_IEP_DRC1>;
+                       assigned-clock-rates = <300000000>;
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               drc1_in: port@0 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       reg = <0>;
+
+                                       drc1_in_be1: endpoint@1 {
+                                               reg = <1>;
+                                               remote-endpoint = <&be1_out_drc1>;
+                                       };
+                               };
+
+                               drc1_out: port@1 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       reg = <1>;
+
+                                       drc1_out_tcon0: endpoint@0 {
+                                               reg = <0>;
+                                               remote-endpoint = <&tcon0_in_drc1>;
+                                       };
+
+                                       drc1_out_tcon1: endpoint@1 {
+                                               reg = <1>;
+                                               remote-endpoint = <&tcon1_in_drc1>;
+                                       };
+                               };
+                       };
+               };
+
+               be0: display-backend@1e60000 {
+                       compatible = "allwinner,sun6i-a31-display-backend";
+                       reg = <0x01e60000 0x10000>;
+                       interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>,
+                                <&ccu CLK_DRAM_BE0>;
+                       clock-names = "ahb", "mod",
+                                     "ram";
+                       resets = <&ccu RST_AHB1_BE0>;
+
+                       assigned-clocks = <&ccu CLK_BE0>;
+                       assigned-clock-rates = <300000000>;
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               be0_in: port@0 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       reg = <0>;
+
+                                       be0_in_fe0: endpoint@0 {
+                                               reg = <0>;
+                                               remote-endpoint = <&fe0_out_be0>;
+                                       };
+
+                                       be0_in_fe1: endpoint@1 {
+                                               reg = <1>;
+                                               remote-endpoint = <&fe1_out_be0>;
+                                       };
+                               };
+
+                               be0_out: port@1 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       reg = <1>;
+
+                                       be0_out_drc0: endpoint@0 {
+                                               reg = <0>;
+                                               remote-endpoint = <&drc0_in_be0>;
+                                       };
+                               };
+                       };
+               };
+
+               drc0: drc@1e70000 {
+                       compatible = "allwinner,sun6i-a31-drc";
+                       reg = <0x01e70000 0x10000>;
+                       interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>,
+                                <&ccu CLK_DRAM_DRC0>;
+                       clock-names = "ahb", "mod",
+                                     "ram";
+                       resets = <&ccu RST_AHB1_DRC0>;
+
+                       assigned-clocks = <&ccu CLK_IEP_DRC0>;
+                       assigned-clock-rates = <300000000>;
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               drc0_in: port@0 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       reg = <0>;
+
+                                       drc0_in_be0: endpoint@0 {
+                                               reg = <0>;
+                                               remote-endpoint = <&be0_out_drc0>;
+                                       };
+                               };
+
+                               drc0_out: port@1 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       reg = <1>;
+
+                                       drc0_out_tcon0: endpoint@0 {
+                                               reg = <0>;
+                                               remote-endpoint = <&tcon0_in_drc0>;
+                                       };
+
+                                       drc0_out_tcon1: endpoint@1 {
+                                               reg = <1>;
+                                               remote-endpoint = <&tcon1_in_drc0>;
+                                       };
+                               };
+                       };
+               };
+
+               rtc: rtc@1f00000 {
                        compatible = "allwinner,sun6i-a31-rtc";
                        reg = <0x01f00000 0x54>;
                        interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
                };
 
-               nmi_intc: interrupt-controller@01f00c0c {
-                       compatible = "allwinner,sun6i-a31-sc-nmi";
+               nmi_intc: interrupt-controller@1f00c00 {
+                       compatible = "allwinner,sun6i-a31-r-intc";
                        interrupt-controller;
                        #interrupt-cells = <2>;
-                       reg = <0x01f00c0c 0x38>;
+                       reg = <0x01f00c00 0x400>;
                        interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
                };
 
-               prcm@01f01400 {
+               prcm@1f01400 {
                        compatible = "allwinner,sun6i-a31-prcm";
                        reg = <0x01f01400 0x200>;
 
                        ar100: ar100_clk {
                                compatible = "allwinner,sun6i-a31-ar100-clk";
                                #clock-cells = <0>;
-                               clocks = <&osc32k>, <&osc24M>, <&pll6 0>,
-                                        <&pll6 0>;
+                               clocks = <&osc32k>, <&osc24M>,
+                                        <&ccu CLK_PLL_PERIPH>,
+                                        <&ccu CLK_PLL_PERIPH>;
                                clock-output-names = "ar100";
                        };
 
@@ -1100,12 +1314,12 @@
                        };
                };
 
-               cpucfg@01f01c00 {
+               cpucfg@1f01c00 {
                        compatible = "allwinner,sun6i-a31-cpuconfig";
                        reg = <0x01f01c00 0x300>;
                };
 
-               ir: ir@01f02000 {
+               ir: ir@1f02000 {
                        compatible = "allwinner,sun5i-a13-ir";
                        clocks = <&apb0_gates 1>, <&ir_clk>;
                        clock-names = "apb", "ir";
@@ -1115,12 +1329,13 @@
                        status = "disabled";
                };
 
-               r_pio: pinctrl@01f02c00 {
+               r_pio: pinctrl@1f02c00 {
                        compatible = "allwinner,sun6i-a31-r-pinctrl";
                        reg = <0x01f02c00 0x400>;
                        interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&apb0_gates 0>;
+                       clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
+                       clock-names = "apb", "hosc", "losc";
                        resets = <&apb0_rst 0>;
                        gpio-controller;
                        interrupt-controller;
@@ -1129,21 +1344,17 @@
                        #gpio-cells = <3>;
 
                        ir_pins_a: ir@0 {
-                               allwinner,pins = "PL4";
-                               allwinner,function = "s_ir";
-                               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-                               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+                               pins = "PL4";
+                               function = "s_ir";
                        };
 
                        p2wi_pins: p2wi {
-                               allwinner,pins = "PL0", "PL1";
-                               allwinner,function = "s_p2wi";
-                               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-                               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+                               pins = "PL0", "PL1";
+                               function = "s_p2wi";
                        };
                };
 
-               p2wi: i2c@01f03400 {
+               p2wi: i2c@1f03400 {
                        compatible = "allwinner,sun6i-a31-p2wi";
                        reg = <0x01f03400 0x400>;
                        interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;

diff --git a/arch/arm/dts/sun6i-a31s-cs908.dts b/arch/arm/dts/sun6i-a31s-cs908.dts
index 5e8f8c4f2b302a67ab02f396977a92e174d76ce3..75e578159c3ab35908c998bb854db018f62daac5 100644 (file)
--- a/arch/arm/dts/sun6i-a31s-cs908.dts
+++ b/arch/arm/dts/sun6i-a31s-cs908.dts
@@ -43,8 +43,6 @@
 /dts-v1/;
 #include "sun6i-a31s.dtsi"
 
-#include <dt-bindings/pinctrl/sun4i-a10.h>
-
 / {
        model = "CSQ CS908 top set box";
        compatible = "csq,cs908", "allwinner,sun6i-a31s";

diff --git a/arch/arm/dts/sun6i-a31s-primo81.dts b/arch/arm/dts/sun6i-a31s-primo81.dts
index 73c133f5e79cdf9540174002656421c96dc68b62..4cb9664cdb2938f291815a6d3503cd630fb8eb21 100644 (file)
--- a/arch/arm/dts/sun6i-a31s-primo81.dts
+++ b/arch/arm/dts/sun6i-a31s-primo81.dts
@@ -48,22 +48,46 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
        model = "MSI Primo81 tablet";
        compatible = "msi,primo81", "allwinner,sun6i-a31s";
+
+       hdmi-connector {
+               compatible = "hdmi-connector";
+               type = "c";
+
+               port {
+                       hdmi_con_in: endpoint {
+                               remote-endpoint = <&hdmi_out_con>;
+                       };
+               };
+       };
 };
 
 &cpu0 {
        cpu-supply = <&reg_dcdc3>;
 };
 
+&de {
+       status = "okay";
+};
+
 &ehci0 {
        /* rtl8188etv wifi is connected here */
        status = "okay";
 };
 
+&hdmi {
+       status = "okay";
+};
+
+&hdmi_out {
+       hdmi_out_con: endpoint {
+               remote-endpoint = <&hdmi_con_in>;
+       };
+};
+
 &i2c0 {
        /* pull-ups and device VDDIO use AXP221 DLDO3 */
        pinctrl-names = "default";
@@ -127,31 +151,26 @@
        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_primo81>;
        vmmc-supply = <&reg_dcdc1>;
        bus-width = <4>;
-       cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */
-       cd-inverted;
+       cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */
        status = "okay";
 };
 
 &pio {
        gt911_int_primo81: gt911_int_pin@0 {
-               allwinner,pins = "PA3";
-               allwinner,function = "gpio_in";
-               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+               pins = "PA3";
+               function = "gpio_in";
        };
 
        mma8452_int_primo81: mma8452_int_pin@0 {
-               allwinner,pins = "PA9";
-               allwinner,function = "gpio_in";
-               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-               allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+               pins = "PA9";
+               function = "gpio_in";
+               bias-pull-up;
        };
 
        mmc0_cd_pin_primo81: mmc0_cd_pin@0 {
-               allwinner,pins = "PA8";
-               allwinner,function = "gpio_in";
-               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-               allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+               pins = "PA8";
+               function = "gpio_in";
+               bias-pull-up;
        };
 };
 
@@ -163,11 +182,16 @@
                reg = <0x68>;
                interrupt-parent = <&nmi_intc>;
                interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+               x-powers,drive-vbus-en;
        };
 };
 
 #include "axp22x.dtsi"
 
+&battery_power_supply {
+       status = "okay";
+};
+
 &reg_aldo3 {
        regulator-always-on;
        regulator-min-microvolt = <2700000>;
@@ -231,6 +255,11 @@
        regulator-name = "vddio-csi";
 };
 
+&reg_drivevbus {
+       regulator-name = "usb0-vbus";
+       status = "okay";
+};
+
 &reg_eldo3 {
        regulator-min-microvolt = <1080000>;
        regulator-max-microvolt = <1320000>;
@@ -243,12 +272,18 @@
 };
 
 &usb_otg {
-       /* otg support requires support for AXP221 usb-power-supply and GPIO */
-       dr_mode = "host";
+       dr_mode = "otg";
+       status = "okay";
+};
+
+&usb_power_supply {
        status = "okay";
 };
 
 &usbphy {
+       usb0_id_det-gpio = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */
+       usb0_vbus_power-supply = <&usb_power_supply>;
+       usb0_vbus-supply = <&reg_drivevbus>;
        usb1_vbus-supply = <&reg_dldo1>;
        status = "okay";
 };

diff --git a/arch/arm/dts/sun6i-a31s-sina31s-core.dtsi b/arch/arm/dts/sun6i-a31s-sina31s-core.dtsi
index 4ec0c8679b2e20b9a15b28160639daf264abd0d6..d7325bc4eeb40d11349d94fca8b0e00943aa7612 100644 (file)
--- a/arch/arm/dts/sun6i-a31s-sina31s-core.dtsi
+++ b/arch/arm/dts/sun6i-a31s-sina31s-core.dtsi
@@ -45,7 +45,6 @@
 #include "sunxi-common-regulators.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
        model = "Sinlinx SinA31s Core Board";

diff --git a/arch/arm/dts/sun6i-a31s-sina31s.dts b/arch/arm/dts/sun6i-a31s-sina31s.dts
index 6ead2f5c847a5d6be332d405bd36d0220a93646e..da0ccf5a2c44583987aac1449bc7fede28e5f2d0 100644 (file)
--- a/arch/arm/dts/sun6i-a31s-sina31s.dts
+++ b/arch/arm/dts/sun6i-a31s-sina31s.dts
@@ -53,6 +53,17 @@
                stdout-path = "serial0:115200n8";
        };
 
+       hdmi-connector {
+               compatible = "hdmi-connector";
+               type = "a";
+
+               port {
+                       hdmi_con_in: endpoint {
+                               remote-endpoint = <&hdmi_out_con>;
+                       };
+               };
+       };
+
        leds {
                compatible = "gpio-leds";
                pinctrl-names = "default";
@@ -63,6 +74,35 @@
                        gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; /* PH13 */
                };
        };
+
+       sound {
+               compatible = "simple-audio-card";
+               simple-audio-card,name = "On-board SPDIF";
+               simple-audio-card,cpu {
+                       sound-dai = <&spdif>;
+               };
+
+               simple-audio-card,codec {
+                       sound-dai = <&spdif_out>;
+               };
+       };
+
+       spdif_out: spdif-out {
+               #sound-dai-cells = <0>;
+               compatible = "linux,spdif-dit";
+       };
+};
+
+&codec {
+       allwinner,audio-routing =
+               "Line Out", "LINEOUT",
+               "MIC1", "Mic",
+               "Mic",  "MBIAS";
+       status = "okay";
+};
+
+&de {
+       status = "okay";
 };
 
 &ehci0 {
@@ -87,6 +127,16 @@
        };
 };
 
+&hdmi {
+       status = "okay";
+};
+
+&hdmi_out {
+       hdmi_out_con: endpoint {
+               remote-endpoint = <&hdmi_con_in>;
+       };
+};
+
 &ir {
        pinctrl-names = "default";
        pinctrl-0 = <&ir_pins_a>;
@@ -117,8 +167,7 @@
        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_sina31s>;
        vmmc-supply = <&reg_dcdc1>;
        bus-width = <4>;
-       cd-gpios = <&pio 0 4 GPIO_ACTIVE_HIGH>; /* PA4 */
-       cd-inverted;
+       cd-gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */
        status = "okay";
 };
 
@@ -128,17 +177,14 @@
 
 &pio {
        led_pin_sina31s: led_pin@0 {
-               allwinner,pins = "PH13";
-               allwinner,function = "gpio_out";
-               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+               pins = "PH13";
+               function = "gpio_out";
        };
 
        mmc0_cd_pin_sina31s: mmc0_cd_pin@0 {
-               allwinner,pins = "PA4";
-               allwinner,function = "gpio_in";
-               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-               allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+               pins = "PA4";
+               function = "gpio_in";
+               bias-pull-up;
        };
 };
 
@@ -148,6 +194,17 @@
        regulator-name = "vcc-gmac-phy";
 };
 
+&spdif {
+       pinctrl-names = "default";
+       pinctrl-0 = <&spdif_pins_a>;
+       status = "okay";
+};
+
+&usb_otg {
+       dr_mode = "peripheral";
+       status = "okay";
+};
+
 &usbphy {
        status = "okay";
 };

diff --git a/arch/arm/dts/sun6i-a31s-sinovoip-bpi-m2.dts b/arch/arm/dts/sun6i-a31s-sinovoip-bpi-m2.dts
index db7fa13f5425e46981102d2c6e247535b082be0e..b8b79c0e9ee051255762e7d7d10e76422130fabd 100644 (file)
--- a/arch/arm/dts/sun6i-a31s-sinovoip-bpi-m2.dts
+++ b/arch/arm/dts/sun6i-a31s-sinovoip-bpi-m2.dts
@@ -42,7 +42,6 @@
 
 /dts-v1/;
 #include "sun6i-a31s.dtsi"
-#include "sunxi-common-regulators.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 
 / {
@@ -86,6 +85,10 @@
        };
 };
 
+&cpu0 {
+       cpu-supply = <&reg_dcdc3>;
+};
+
 &ehci0 {
        status = "okay";
 };
@@ -95,6 +98,7 @@
        pinctrl-0 = <&gmac_pins_rgmii_a>, <&gmac_phy_reset_pin_bpi_m2>;
        phy = <&phy1>;
        phy-mode = "rgmii";
+       phy-supply = <&reg_dldo1>;
        snps,reset-gpio = <&pio 0 21 GPIO_ACTIVE_HIGH>; /* PA21 */
        snps,reset-active-low;
        snps,reset-delays-us = <0 10000 30000>;
@@ -114,27 +118,26 @@
 &mmc0 {
        pinctrl-names = "default";
        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bpi_m2>;
-       vmmc-supply = <&reg_vcc3v0>;
+       vmmc-supply = <&reg_dcdc1>;
        bus-width = <4>;
-       cd-gpios = <&pio 0 4 GPIO_ACTIVE_HIGH>; /* PA4 */
-       cd-inverted;
+       cd-gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */
        status = "okay";
 };
 
 &mmc0_pins_a {
-       allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+       bias-pull-up;
 };
 
 &mmc2 {
        pinctrl-names = "default";
        pinctrl-0 = <&mmc2_pins_a>;
-       vmmc-supply = <&reg_vcc3v0>;
+       vmmc-supply = <&reg_aldo1>;
        mmc-pwrseq = <&mmc2_pwrseq>;
        bus-width = <4>;
        non-removable;
        status = "okay";
 
-       brcmf: bcrmf@1 {
+       brcmf: wifi@1 {
                reg = <1>;
                compatible = "brcm,bcm4329-fmac";
                interrupt-parent = <&r_pio>;
@@ -144,45 +147,148 @@
 };
 
 &mmc2_pins_a {
-       allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+       bias-pull-up;
 };
 
 &ohci0 {
        status = "okay";
 };
 
+&p2wi {
+       status = "okay";
+
+       axp22x: pmic@68 {
+               compatible = "x-powers,axp221";
+               reg = <0x68>;
+               interrupt-parent = <&nmi_intc>;
+               interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+               eldoin-supply = <&reg_dcdc1>;
+               x-powers,drive-vbus-en;
+       };
+};
+
 &pio {
        gmac_phy_reset_pin_bpi_m2: gmac_phy_reset_pin@0 {
-               allwinner,pins = "PA21";
-               allwinner,function = "gpio_out";
-               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+               pins = "PA21";
+               function = "gpio_out";
        };
 
        led_pins_bpi_m2: led_pins@0 {
-               allwinner,pins = "PG5", "PG10", "PG11";
-               allwinner,function = "gpio_out";
-               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+               pins = "PG5", "PG10", "PG11";
+               function = "gpio_out";
        };
 
        mmc0_cd_pin_bpi_m2: mmc0_cd_pin@0 {
-               allwinner,pins = "PA4";
-               allwinner,function = "gpio_in";
-               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-               allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+               pins = "PA4";
+               function = "gpio_in";
+               bias-pull-up;
        };
 };
 
 &r_pio {
        mmc2_pwrseq_pin_bpi_m2: mmc2_pwrseq_pin@0 {
-               allwinner,pins = "PL8";
-               allwinner,function = "gpio_out";
-               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+               pins = "PL8";
+               function = "gpio_out";
        };
 };
 
+#include "axp22x.dtsi"
+
+&reg_aldo1 {
+       regulator-min-microvolt = <3300000>;
+       regulator-max-microvolt = <3300000>;
+       regulator-name = "vcc-wifi";
+};
+
+&reg_aldo2 {
+       regulator-always-on;
+       regulator-min-microvolt = <2500000>;
+       regulator-max-microvolt = <2500000>;
+       regulator-name = "vcc-gmac";
+};
+
+&reg_aldo3 {
+       regulator-always-on;
+       regulator-min-microvolt = <3000000>;
+       regulator-max-microvolt = <3000000>;
+       regulator-name = "avcc";
+};
+
+&reg_dc5ldo {
+       regulator-always-on;
+       regulator-min-microvolt = <700000>;
+       regulator-max-microvolt = <1320000>;
+       regulator-name = "vdd-cpus";
+};
+
+&reg_dcdc1 {
+       regulator-always-on;
+       regulator-min-microvolt = <3000000>;
+       regulator-max-microvolt = <3000000>;
+       regulator-name = "vdd-3v0";
+};
+
+&reg_dcdc2 {
+       regulator-min-microvolt = <700000>;
+       regulator-max-microvolt = <1320000>;
+       regulator-name = "vdd-gpu";
+};
+
+&reg_dcdc3 {
+       regulator-always-on;
+       regulator-min-microvolt = <700000>;
+       regulator-max-microvolt = <1320000>;
+       regulator-name = "vdd-cpu";
+};
+
+&reg_dcdc4 {
+       regulator-always-on;
+       regulator-min-microvolt = <700000>;
+       regulator-max-microvolt = <1320000>;
+       regulator-name = "vdd-sys-dll";
+};
+
+&reg_dcdc5 {
+       regulator-always-on;
+       regulator-min-microvolt = <1500000>;
+       regulator-max-microvolt = <1500000>;
+       regulator-name = "vcc-dram";
+};
+
+&reg_dldo1 {
+       regulator-min-microvolt = <3000000>;
+       regulator-max-microvolt = <3000000>;
+       regulator-name = "vcc-mac";
+};
+
+&reg_dldo2 {
+       regulator-min-microvolt = <2800000>;
+       regulator-max-microvolt = <2800000>;
+       regulator-name = "avdd-csi";
+};
+
+&reg_dldo3 {
+       regulator-always-on;
+       regulator-min-microvolt = <3300000>;
+       regulator-max-microvolt = <3300000>;
+       regulator-name = "vcc-pb";
+};
+
+&reg_eldo1 {
+       regulator-min-microvolt = <1800000>;
+       regulator-max-microvolt = <1800000>;
+       regulator-name = "vdd-csi";
+       status = "okay";
+};
+
+&reg_ldo_io1 {
+       regulator-always-on;
+       regulator-min-microvolt = <1800000>;
+       regulator-max-microvolt = <1800000>;
+       regulator-name = "vcc-pm-cpus";
+       status = "okay";
+};
+
 &uart0 {
        pinctrl-names = "default";
        pinctrl-0 = <&uart0_pins_a>;

diff --git a/arch/arm/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts b/arch/arm/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts
index d6ad6196a768bce9a28d1c7fcb149da32f21d5df..aab6c1720ef7973e779edd55ebd7a5a369dbfbde 100644 (file)
--- a/arch/arm/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts
+++ b/arch/arm/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts
@@ -45,7 +45,6 @@
 #include "sunxi-common-regulators.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
        model = "Yones TopTech BS1078 v2 Tablet";
@@ -92,10 +91,9 @@
 
 &pio {
        mmc0_cd_pin_bs1078v2: mmc0_cd_pin@0 {
-               allwinner,pins = "PA8";
-               allwinner,function = "gpio_in";
-               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-               allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+               pins = "PA8";
+               function = "gpio_in";
+               bias-pull-up;
        };
 };
 
@@ -104,13 +102,12 @@
        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bs1078v2>;
        vmmc-supply = <&reg_vcc3v0>;
        bus-width = <4>;
-       cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */
-       cd-inverted;
+       cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */
        status = "okay";
 };
 
 &mmc0_pins_a {
-       allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+       bias-pull-up;
 };
 
 &p2wi {

diff --git a/arch/arm/dts/sun6i-a31s.dtsi b/arch/arm/dts/sun6i-a31s.dtsi
index c17a32771b98c881f408d56b388bbb3209e25905..97e2c51d0aea4611dc98799b12c8c62b9f6f537c 100644 (file)
--- a/arch/arm/dts/sun6i-a31s.dtsi
+++ b/arch/arm/dts/sun6i-a31s.dtsi
@@ -48,6 +48,14 @@
 
 #include "sun6i-a31.dtsi"
 
+&de {
+       compatible = "allwinner,sun6i-a31s-display-engine";
+};
+
 &pio {
        compatible = "allwinner,sun6i-a31s-pinctrl";
 };
+
+&tcon0 {
+       compatible = "allwinner,sun6i-a31s-tcon";
+};

diff --git a/arch/arm/dts/sun6i-reference-design-tablet.dtsi b/arch/arm/dts/sun6i-reference-design-tablet.dtsi
index 0c434304e040f1745722cea0e299c9e0794fef3f..4e72e4f3ef96eeed666fa37b12b5d568abc27ffc 100644 (file)
--- a/arch/arm/dts/sun6i-reference-design-tablet.dtsi
+++ b/arch/arm/dts/sun6i-reference-design-tablet.dtsi
@@ -44,7 +44,6 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
        aliases {
@@ -70,24 +69,21 @@
        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_e708_q1>;
        vmmc-supply = <&reg_dcdc1>;
        bus-width = <4>;
-       cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */
-       cd-inverted;
+       cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */
        status = "okay";
 };
 
 &pio {
        mmc0_cd_pin_e708_q1: mmc0_cd_pin@0 {
-               allwinner,pins = "PA8";
-               allwinner,function = "gpio_in";
-               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-               allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+               pins = "PA8";
+               function = "gpio_in";
+               bias-pull-up;
        };
 
        usb0_id_detect_pin: usb0_id_detect_pin@0 {
-               allwinner,pins = "PA15";
-               allwinner,function = "gpio_in";
-               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-               allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+               pins = "PA15";
+               function = "gpio_in";
+               bias-pull-up;
        };
 };
 

diff --git a/include/dt-bindings/clock/sun6i-a31-ccu.h b/include/dt-bindings/clock/sun6i-a31-ccu.h
new file mode 100644 (file)
index 0000000..c5d1334
--- /dev/null
+++ b/include/dt-bindings/clock/sun6i-a31-ccu.h
@@ -0,0 +1,191 @@
+/*
+ * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN6I_A31_H_
+#define _DT_BINDINGS_CLK_SUN6I_A31_H_
+
+#define CLK_PLL_VIDEO0_2X      7
+
+#define CLK_PLL_PERIPH         10
+
+#define CLK_PLL_VIDEO1_2X      13
+
+#define CLK_CPU                        18
+
+#define CLK_AHB1_MIPIDSI       23
+#define CLK_AHB1_SS            24
+#define CLK_AHB1_DMA           25
+#define CLK_AHB1_MMC0          26
+#define CLK_AHB1_MMC1          27
+#define CLK_AHB1_MMC2          28
+#define CLK_AHB1_MMC3          29
+#define CLK_AHB1_NAND1         30
+#define CLK_AHB1_NAND0         31
+#define CLK_AHB1_SDRAM         32
+#define CLK_AHB1_EMAC          33
+#define CLK_AHB1_TS            34
+#define CLK_AHB1_HSTIMER       35
+#define CLK_AHB1_SPI0          36
+#define CLK_AHB1_SPI1          37
+#define CLK_AHB1_SPI2          38
+#define CLK_AHB1_SPI3          39
+#define CLK_AHB1_OTG           40
+#define CLK_AHB1_EHCI0         41
+#define CLK_AHB1_EHCI1         42
+#define CLK_AHB1_OHCI0         43
+#define CLK_AHB1_OHCI1         44
+#define CLK_AHB1_OHCI2         45
+#define CLK_AHB1_VE            46
+#define CLK_AHB1_LCD0          47
+#define CLK_AHB1_LCD1          48
+#define CLK_AHB1_CSI           49
+#define CLK_AHB1_HDMI          50
+#define CLK_AHB1_BE0           51
+#define CLK_AHB1_BE1           52
+#define CLK_AHB1_FE0           53
+#define CLK_AHB1_FE1           54
+#define CLK_AHB1_MP            55
+#define CLK_AHB1_GPU           56
+#define CLK_AHB1_DEU0          57
+#define CLK_AHB1_DEU1          58
+#define CLK_AHB1_DRC0          59
+#define CLK_AHB1_DRC1          60
+
+#define CLK_APB1_CODEC         61
+#define CLK_APB1_SPDIF         62
+#define CLK_APB1_DIGITAL_MIC   63
+#define CLK_APB1_PIO           64
+#define CLK_APB1_DAUDIO0       65
+#define CLK_APB1_DAUDIO1       66
+
+#define CLK_APB2_I2C0          67
+#define CLK_APB2_I2C1          68
+#define CLK_APB2_I2C2          69
+#define CLK_APB2_I2C3          70
+#define CLK_APB2_UART0         71
+#define CLK_APB2_UART1         72
+#define CLK_APB2_UART2         73
+#define CLK_APB2_UART3         74
+#define CLK_APB2_UART4         75
+#define CLK_APB2_UART5         76
+
+#define CLK_NAND0              77
+#define CLK_NAND1              78
+#define CLK_MMC0               79
+#define CLK_MMC0_SAMPLE                80
+#define CLK_MMC0_OUTPUT                81
+#define CLK_MMC1               82
+#define CLK_MMC1_SAMPLE                83
+#define CLK_MMC1_OUTPUT                84
+#define CLK_MMC2               85
+#define CLK_MMC2_SAMPLE                86
+#define CLK_MMC2_OUTPUT                87
+#define CLK_MMC3               88
+#define CLK_MMC3_SAMPLE                89
+#define CLK_MMC3_OUTPUT                90
+#define CLK_TS                 91
+#define CLK_SS                 92
+#define CLK_SPI0               93
+#define CLK_SPI1               94
+#define CLK_SPI2               95
+#define CLK_SPI3               96
+#define CLK_DAUDIO0            97
+#define CLK_DAUDIO1            98
+#define CLK_SPDIF              99
+#define CLK_USB_PHY0           100
+#define CLK_USB_PHY1           101
+#define CLK_USB_PHY2           102
+#define CLK_USB_OHCI0          103
+#define CLK_USB_OHCI1          104
+#define CLK_USB_OHCI2          105
+
+#define CLK_DRAM_VE            110
+#define CLK_DRAM_CSI_ISP       111
+#define CLK_DRAM_TS            112
+#define CLK_DRAM_DRC0          113
+#define CLK_DRAM_DRC1          114
+#define CLK_DRAM_DEU0          115
+#define CLK_DRAM_DEU1          116
+#define CLK_DRAM_FE0           117
+#define CLK_DRAM_FE1           118
+#define CLK_DRAM_BE0           119
+#define CLK_DRAM_BE1           120
+#define CLK_DRAM_MP            121
+
+#define CLK_BE0                        122
+#define CLK_BE1                        123
+#define CLK_FE0                        124
+#define CLK_FE1                        125
+#define CLK_MP                 126
+#define CLK_LCD0_CH0           127
+#define CLK_LCD1_CH0           128
+#define CLK_LCD0_CH1           129
+#define CLK_LCD1_CH1           130
+#define CLK_CSI0_SCLK          131
+#define CLK_CSI0_MCLK          132
+#define CLK_CSI1_MCLK          133
+#define CLK_VE                 134
+#define CLK_CODEC              135
+#define CLK_AVS                        136
+#define CLK_DIGITAL_MIC                137
+#define CLK_HDMI               138
+#define CLK_HDMI_DDC           139
+#define CLK_PS                 140
+
+#define CLK_MIPI_DSI           143
+#define CLK_MIPI_DSI_DPHY      144
+#define CLK_MIPI_CSI_DPHY      145
+#define CLK_IEP_DRC0           146
+#define CLK_IEP_DRC1           147
+#define CLK_IEP_DEU0           148
+#define CLK_IEP_DEU1           149
+#define CLK_GPU_CORE           150
+#define CLK_GPU_MEMORY         151
+#define CLK_GPU_HYD            152
+#define CLK_ATS                        153
+#define CLK_TRACE              154
+
+#define CLK_OUT_A              155
+#define CLK_OUT_B              156
+#define CLK_OUT_C              157
+
+#endif /* _DT_BINDINGS_CLK_SUN6I_A31_H_ */

diff --git a/include/dt-bindings/reset/sun6i-a31-ccu.h b/include/dt-bindings/reset/sun6i-a31-ccu.h
new file mode 100644 (file)
index 0000000..fbff365
--- /dev/null
+++ b/include/dt-bindings/reset/sun6i-a31-ccu.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN6I_A31_H_
+#define _DT_BINDINGS_RST_SUN6I_A31_H_
+
+#define RST_USB_PHY0           0
+#define RST_USB_PHY1           1
+#define RST_USB_PHY2           2
+
+#define RST_AHB1_MIPI_DSI      3
+#define RST_AHB1_SS            4
+#define RST_AHB1_DMA           5
+#define RST_AHB1_MMC0          6
+#define RST_AHB1_MMC1          7
+#define RST_AHB1_MMC2          8
+#define RST_AHB1_MMC3          9
+#define RST_AHB1_NAND1         10
+#define RST_AHB1_NAND0         11
+#define RST_AHB1_SDRAM         12
+#define RST_AHB1_EMAC          13
+#define RST_AHB1_TS            14
+#define RST_AHB1_HSTIMER       15
+#define RST_AHB1_SPI0          16
+#define RST_AHB1_SPI1          17
+#define RST_AHB1_SPI2          18
+#define RST_AHB1_SPI3          19
+#define RST_AHB1_OTG           20
+#define RST_AHB1_EHCI0         21
+#define RST_AHB1_EHCI1         22
+#define RST_AHB1_OHCI0         23
+#define RST_AHB1_OHCI1         24
+#define RST_AHB1_OHCI2         25
+#define RST_AHB1_VE            26
+#define RST_AHB1_LCD0          27
+#define RST_AHB1_LCD1          28
+#define RST_AHB1_CSI           29
+#define RST_AHB1_HDMI          30
+#define RST_AHB1_BE0           31
+#define RST_AHB1_BE1           32
+#define RST_AHB1_FE0           33
+#define RST_AHB1_FE1           34
+#define RST_AHB1_MP            35
+#define RST_AHB1_GPU           36
+#define RST_AHB1_DEU0          37
+#define RST_AHB1_DEU1          38
+#define RST_AHB1_DRC0          39
+#define RST_AHB1_DRC1          40
+#define RST_AHB1_LVDS          41
+
+#define RST_APB1_CODEC         42
+#define RST_APB1_SPDIF         43
+#define RST_APB1_DIGITAL_MIC   44
+#define RST_APB1_DAUDIO0       45
+#define RST_APB1_DAUDIO1       46
+#define RST_APB2_I2C0          47
+#define RST_APB2_I2C1          48
+#define RST_APB2_I2C2          49
+#define RST_APB2_I2C3          50
+#define RST_APB2_UART0         51
+#define RST_APB2_UART1         52
+#define RST_APB2_UART2         53
+#define RST_APB2_UART3         54
+#define RST_APB2_UART4         55
+#define RST_APB2_UART5         56
+
+#endif /* _DT_BINDINGS_RST_SUN6I_A31_H_ */