clk: sunxi-ng: r40: Export video PLLs
authorJernej Skrabec <jernej.skrabec@siol.net>
Mon, 25 Jun 2018 12:02:43 +0000 (14:02 +0200)
committerMaxime Ripard <maxime.ripard@bootlin.com>
Wed, 27 Jun 2018 17:06:56 +0000 (19:06 +0200)
Video PLLs need to be referenced in R40 DT as possible HDMI PHY parent.

Export them.

Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
drivers/clk/sunxi-ng/ccu-sun8i-r40.h
include/dt-bindings/clock/sun8i-r40-ccu.h

index 0db8e1e97af81455adb8ba69e0caea85cb3bd220..db2a1243f9ffd300ff1dfc1d7a22662b95ad1801 100644 (file)
@@ -25,7 +25,9 @@
 #define CLK_PLL_AUDIO_2X       4
 #define CLK_PLL_AUDIO_4X       5
 #define CLK_PLL_AUDIO_8X       6
-#define CLK_PLL_VIDEO0         7
+
+/* PLL_VIDEO0 is exported */
+
 #define CLK_PLL_VIDEO0_2X      8
 #define CLK_PLL_VE             9
 #define CLK_PLL_DDR0           10
@@ -34,7 +36,9 @@
 #define CLK_PLL_PERIPH0_2X     13
 #define CLK_PLL_PERIPH1                14
 #define CLK_PLL_PERIPH1_2X     15
-#define CLK_PLL_VIDEO1         16
+
+/* PLL_VIDEO1 is exported */
+
 #define CLK_PLL_VIDEO1_2X      17
 #define CLK_PLL_SATA           18
 #define CLK_PLL_SATA_OUT       19
index 4fa5f69fc297cbed6c2b7868759a6bec6345a793..f9e15a235626521726e88b65096943b1a3868c02 100644 (file)
 #ifndef _DT_BINDINGS_CLK_SUN8I_R40_H_
 #define _DT_BINDINGS_CLK_SUN8I_R40_H_
 
+#define CLK_PLL_VIDEO0         7
+
+#define CLK_PLL_VIDEO1         16
+
 #define CLK_CPU                        24
 
 #define CLK_BUS_MIPI_DSI       29