+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Device tree for the uDPU board.
- * Based on Marvell Armada 3720 development board (DB-88F3720-DDR3)
- * Copyright (C) 2016 Marvell
- * Copyright (C) 2019 Methode Electronics
- * Copyright (C) 2019 Telus
- *
- * Vladimir Vid <vladimir.vid@sartura.hr>
- */
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include "armada-372x.dtsi"
-
-/ {
- model = "Methode uDPU Board";
- compatible = "methode,udpu", "marvell,armada3720";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
- };
-
- leds {
- pinctrl-names = "default";
- compatible = "gpio-leds";
-
- power1 {
- label = "udpu:green:power";
- gpios = <&gpionb 11 GPIO_ACTIVE_LOW>;
- };
-
- power2 {
- label = "udpu:red:power";
- gpios = <&gpionb 12 GPIO_ACTIVE_LOW>;
- };
-
- network1 {
- label = "udpu:green:network";
- gpios = <&gpionb 13 GPIO_ACTIVE_LOW>;
- };
-
- network2 {
- label = "udpu:red:network";
- gpios = <&gpionb 14 GPIO_ACTIVE_LOW>;
- };
-
- alarm1 {
- label = "udpu:green:alarm";
- gpios = <&gpionb 15 GPIO_ACTIVE_LOW>;
- };
-
- alarm2 {
- label = "udpu:red:alarm";
- gpios = <&gpionb 16 GPIO_ACTIVE_LOW>;
- };
- };
-
- sfp_eth0: sfp-eth0 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c0>;
- los-gpio = <&gpiosb 2 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpiosb 3 GPIO_ACTIVE_LOW>;
- tx-disable-gpio = <&gpiosb 4 GPIO_ACTIVE_HIGH>;
- tx-fault-gpio = <&gpiosb 5 GPIO_ACTIVE_HIGH>;
- };
-
- sfp_eth1: sfp-eth1 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c1>;
- los-gpio = <&gpiosb 7 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpiosb 8 GPIO_ACTIVE_LOW>;
- tx-disable-gpio = <&gpiosb 9 GPIO_ACTIVE_HIGH>;
- tx-fault-gpio = <&gpiosb 10 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&sdhci0 {
- status = "okay";
- bus-width = <8>;
- mmc-ddr-1_8v;
- mmc-hs400-1_8v;
- marvell,pad-type = "fixed-1-8v";
- non-removable;
- no-sd;
- no-sdio;
-};
-
-&spi0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&spi_quad_pins>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <54000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
- /* only bootloader is located on the SPI */
- partition@0 {
- label = "uboot";
- reg = <0 0x400000>;
- };
- };
- };
-};
-
-&i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins>;
-};
-
-&i2c1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins>;
-
- lm75@48 {
- status = "okay";
- compatible = "lm75";
- reg = <0x48>;
- };
-
- lm75@49 {
- status = "okay";
- compatible = "lm75";
- reg = <0x49>;
- };
-};
-
-ð0 {
- status = "okay";
- phy-mode = "sgmii";
- managed = "in-band-status";
- sfp = <&sfp_eth0>;
-};
-
-ð1 {
- status = "okay";
- phy-mode = "sgmii";
- managed = "in-band-status";
- sfp = <&sfp_eth1>;
-};
-
-&usb3 {
- status = "okay";
-};
-
-&uart0 {
- status = "okay";
-};
pinctrl-0 = <&sdhci_pins>;
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-@@ -272,12 +272,100 @@
+@@ -225,12 +225,100 @@
pcie@2,0 {
/* Port 0, Lane 1 */
status = "okay";
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-@@ -257,6 +257,16 @@
- };
- };
+@@ -210,6 +210,16 @@
+ compatible = "pwm-fan";
+ pwms = <&gpio0 24 4000>;
};
+
+ mvsw61xx {
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
-@@ -1926,6 +1926,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
+@@ -1825,6 +1825,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
The command-line arguments provided by the boot loader will be
appended to the the device tree bootargs property.
}
*ptr = '\0';
-@@ -148,7 +218,9 @@ int atags_to_fdt(void *atag_list, void *
+@@ -166,7 +236,9 @@ int atags_to_fdt(void *atag_list, void *
else
setprop_string(fdt, "/chosen", "bootargs",
atag->u.cmdline.cmdline);
if (memcount >= sizeof(mem_reg_property)/4)
continue;
if (!atag->u.mem.size)
-@@ -187,6 +259,10 @@ int atags_to_fdt(void *atag_list, void *
+@@ -210,6 +282,10 @@ int atags_to_fdt(void *atag_list, void *
setprop(fdt, "/memory", "reg", mem_reg_property,
4 * memcount * memsize);
}
}
--- a/init/main.c
+++ b/init/main.c
-@@ -102,6 +102,10 @@
+@@ -103,6 +103,10 @@
#define CREATE_TRACE_POINTS
#include <trace/events/initcall.h>
static int kernel_init(void *);
extern void init_IRQ(void);
-@@ -591,6 +595,18 @@ asmlinkage __visible void __init start_k
+@@ -630,6 +634,18 @@ asmlinkage __visible void __init start_k
page_alloc_init();
pr_notice("Kernel command line: %s\n", boot_command_line);
Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
---- a/drivers/mtd/ofpart.c
-+++ b/drivers/mtd/ofpart.c
-@@ -25,6 +25,8 @@ static bool node_has_compatible(struct d
+--- a/drivers/mtd/parsers/ofpart.c
++++ b/drivers/mtd/parsers/ofpart.c
+@@ -21,6 +21,8 @@ static bool node_has_compatible(struct d
return of_get_property(pp, "compatible", NULL);
}
static int parse_fixed_partitions(struct mtd_info *master,
const struct mtd_partition **pparts,
struct mtd_part_parser_data *data)
-@@ -33,6 +35,7 @@ static int parse_fixed_partitions(struct
+@@ -29,6 +31,7 @@ static int parse_fixed_partitions(struct
struct device_node *mtd_node;
struct device_node *ofpart_node;
const char *partname;
struct device_node *pp;
int nr_parts, i, ret = 0;
bool dedicated = true;
-@@ -110,9 +113,13 @@ static int parse_fixed_partitions(struct
+@@ -106,9 +109,13 @@ static int parse_fixed_partitions(struct
parts[i].size = of_read_number(reg + a_cells, s_cells);
parts[i].of_node = pp;
parts[i].name = partname;
if (of_get_property(pp, "read-only", &len))
-@@ -219,6 +226,18 @@ static int __init ofpart_parser_init(voi
+@@ -215,6 +222,18 @@ static int __init ofpart_parser_init(voi
return 0;
}
--- a/arch/arm/boot/dts/armada-388-clearfog.dts
+++ b/arch/arm/boot/dts/armada-388-clearfog.dts
-@@ -88,6 +88,18 @@
+@@ -30,6 +30,18 @@
};
};
#size-cells = <0>;
--- a/arch/arm/boot/dts/armada-388-clearfog.dts
+++ b/arch/arm/boot/dts/armada-388-clearfog.dts
-@@ -161,6 +161,7 @@
+@@ -103,6 +103,7 @@
status = "okay";
switch@4 {
#size-cells = <0>;
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-@@ -413,6 +413,7 @@
+@@ -366,6 +366,7 @@
status = "okay";
switch@0 {
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-@@ -543,3 +543,7 @@
+@@ -496,3 +496,7 @@
};
};
};
---
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -4272,6 +4272,15 @@ static int mvneta_ethtool_set_eee(struct
+@@ -4332,6 +4332,14 @@ static int mvneta_ethtool_set_eee(struct
return phylink_ethtool_set_eee(pp->phylink, eee);
}
+static u16 mvneta_select_queue(struct net_device *dev, struct sk_buff *skb,
-+ struct net_device *sb_dev,
-+ select_queue_fallback_t fallback)
++ struct net_device *sb_dev)
+{
+ /* XXX: hardware queue scheduling is broken,
+ * use only one queue until it is fixed */
static const struct net_device_ops mvneta_netdev_ops = {
.ndo_open = mvneta_open,
.ndo_stop = mvneta_stop,
-@@ -4282,6 +4291,7 @@ static const struct net_device_ops mvnet
+@@ -4342,6 +4350,7 @@ static const struct net_device_ops mvnet
.ndo_fix_features = mvneta_fix_features,
.ndo_get_stats64 = mvneta_get_stats64,
.ndo_do_ioctl = mvneta_ioctl,
--- a/drivers/pci/controller/pci-mvebu.c
+++ b/drivers/pci/controller/pci-mvebu.c
-@@ -1112,6 +1112,7 @@ static int mvebu_pcie_powerup(struct mve
+@@ -928,6 +928,7 @@ static int mvebu_pcie_powerup(struct mve
if (port->reset_gpio) {
u32 reset_udelay = PCI_PM_D3COLD_WAIT * 1000;
of_property_read_u32(port->dn, "reset-delay-us",
&reset_udelay);
-@@ -1119,7 +1120,13 @@ static int mvebu_pcie_powerup(struct mve
+@@ -935,7 +936,13 @@ static int mvebu_pcie_powerup(struct mve
udelay(100);
gpiod_set_value_cansleep(port->reset_gpio, 0);
}
return 0;
-@@ -1283,15 +1290,16 @@ static int mvebu_pcie_probe(struct platf
+@@ -1099,15 +1106,16 @@ static int mvebu_pcie_probe(struct platf
if (!child)
continue;
+++ /dev/null
-From 09a0122c74ec076e08512f1b00b7ccb8a450282f Mon Sep 17 00:00:00 2001
-From: Russell King <rmk+kernel@arm.linux.org.uk>
-Date: Tue, 29 Nov 2016 10:15:43 +0000
-Subject: ARM: dts: armada388-clearfog: document MPP usage
-
-Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
----
- arch/arm/boot/dts/armada-388-clearfog-base.dts | 51 ++++++++++++++++++++++++++
- arch/arm/boot/dts/armada-388-clearfog.dts | 50 +++++++++++++++++++++++++
- 2 files changed, 101 insertions(+)
-
---- a/arch/arm/boot/dts/armada-388-clearfog-base.dts
-+++ b/arch/arm/boot/dts/armada-388-clearfog-base.dts
-@@ -67,3 +67,54 @@
- marvell,function = "gpio";
- };
- };
-+
-+/*
-+MPP
-+18: pu gpio pca9655 int
-+19: gpio phy reset
-+20: pu gpio sd0 detect
-+21: sd0:cmd
-+22: pd gpio mikro int
-+23:
-+
-+24: ua1:rxd mikro rx
-+25: ua1:txd mikro tx
-+26: pu i2c1:sck
-+27: pu i2c1:sda
-+28: sd0:clk
-+29: pd gpio mikro rst
-+30:
-+31:
-+
-+32:
-+33:
-+34:
-+35:
-+36:
-+37: sd0:d3
-+38: sd0:d0
-+39: sd0:d1
-+
-+40: sd0:d2
-+41:
-+42:
-+43: spi1:cs2 mikro cs
-+44: gpio rear button sw3
-+45: ref:clk_out0 phy#0 clock
-+46: ref:clk_out1 phy#1 clock
-+47:
-+
-+48: gpio J18 spare gpio
-+49: gpio U10 I2C_IRQ(GNSS)
-+50: gpio board id?
-+51:
-+52:
-+53:
-+54: gpio mikro pwm
-+55:
-+
-+56: pu spi1:mosi mikro mosi
-+57: pd spi1:sck mikro sck
-+58: spi1:miso mikro miso
-+59:
-+*/
---- a/arch/arm/boot/dts/armada-388-clearfog.dts
-+++ b/arch/arm/boot/dts/armada-388-clearfog.dts
-@@ -249,3 +249,53 @@
- */
- pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>;
- };
-+/*
-++#define A38x_CUSTOMER_BOARD_1_MPP16_23 0x00400011
-+MPP18: gpio ? (pca9655 int?)
-+MPP19: gpio ? (clkreq?)
-+MPP20: gpio ? (sd0 detect)
-+MPP21: sd0:cmd x sd0
-+MPP22: gpio x mikro int
-+MPP23: gpio x switch irq
-++#define A38x_CUSTOMER_BOARD_1_MPP24_31 0x22043333
-+MPP24: ua1:rxd x mikro rx
-+MPP25: ua1:txd x mikro tx
-+MPP26: i2c1:sck x mikro sck
-+MPP27: i2c1:sda x mikro sda
-+MPP28: sd0:clk x sd0
-+MPP29: gpio x mikro rst
-+MPP30: ge1:txd2 ? (config)
-+MPP31: ge1:txd3 ? (config)
-++#define A38x_CUSTOMER_BOARD_1_MPP32_39 0x44400002
-+MPP32: ge1:txctl ? (unused)
-+MPP33: gpio ? (pic_com0)
-+MPP34: gpio x rear button (pic_com1)
-+MPP35: gpio ? (pic_com2)
-+MPP36: gpio ? (unused)
-+MPP37: sd0:d3 x sd0
-+MPP38: sd0:d0 x sd0
-+MPP39: sd0:d1 x sd0
-++#define A38x_CUSTOMER_BOARD_1_MPP40_47 0x41144004
-+MPP40: sd0:d2 x sd0
-+MPP41: gpio x switch reset
-+MPP42: gpio ? sw1-1
-+MPP43: spi1:cs2 x mikro cs
-+MPP44: sata3:prsnt ? (unused)
-+MPP45: ref:clk_out0 ?
-+MPP46: ref:clk_out1 x switch clk
-+MPP47: 4 ? (unused)
-++#define A38x_CUSTOMER_BOARD_1_MPP48_55 0x40333333
-+MPP48: tdm:pclk
-+MPP49: tdm:fsync
-+MPP50: tdm:drx
-+MPP51: tdm:dtx
-+MPP52: tdm:int
-+MPP53: tdm:rst
-+MPP54: gpio ? (pwm)
-+MPP55: spi1:cs1 x slic
-++#define A38x_CUSTOMER_BOARD_1_MPP56_63 0x00004444
-+MPP56: spi1:mosi x mikro mosi
-+MPP57: spi1:sck x mikro sck
-+MPP58: spi1:miso x mikro miso
-+MPP59: spi1:cs0 x w25q32
-+*/
+++ /dev/null
-From eefe328439642101774f0f5c4ea0dc6ba1cfb687 Mon Sep 17 00:00:00 2001
-From: Ding Tao <miyatsu@qq.com>
-Date: Fri, 26 Oct 2018 11:50:27 +0000
-Subject: [PATCH] arm64: dts: marvell: armada37xx: Add emmc/sdio pinctrl
- definition
-
-Add emmc/sdio pinctrl definition for marvell armada37xx SoCs.
-
-Signed-off-by: Ding Tao <miyatsu@qq.com>
-Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
----
- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
---- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
-+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
-@@ -221,6 +221,11 @@
- groups = "uart2";
- function = "uart";
- };
-+
-+ mmc_pins: mmc-pins {
-+ groups = "emmc_nb";
-+ function = "emmc";
-+ };
- };
-
- nb_pm: syscon@14000 {
-@@ -253,6 +258,11 @@
- function = "mii";
- };
-
-+ sdio_pins: sdio-pins {
-+ groups = "sdio_sb";
-+ function = "sdio";
-+ };
-+
- };
-
- eth0: ethernet@30000 {
+++ /dev/null
-From 43ebc7c1b3ed8198b9acf3019eca16e722f7331c Mon Sep 17 00:00:00 2001
-From: Ding Tao <miyatsu@qq.com>
-Date: Fri, 26 Oct 2018 11:50:28 +0000
-Subject: [PATCH] arm64: dts: marvell: armada-37xx: Enable emmc on espressobin
-
-The ESPRESSObin board has a emmc interface available on U11: declare it
-and let the bootloader enable it if the emmc is present.
-
-[gregory.clement@bootlin.com: disable the emmc by default]
-Signed-off-by: Ding Tao <miyatsu@qq.com>
-Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
----
- .../dts/marvell/armada-3720-espressobin.dts | 22 +++++++++++++++++++
- 1 file changed, 22 insertions(+)
-
---- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
-+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
-@@ -60,9 +60,31 @@
- cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>;
- marvell,pad-type = "sd";
- vqmmc-supply = <&vcc_sd_reg1>;
-+
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&sdio_pins>;
- status = "okay";
- };
-
-+/* U11 */
-+&sdhci0 {
-+ non-removable;
-+ bus-width = <8>;
-+ mmc-ddr-1_8v;
-+ mmc-hs400-1_8v;
-+ marvell,xenon-emmc;
-+ marvell,xenon-tun-count = <9>;
-+ marvell,pad-type = "fixed-1-8v";
-+
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&mmc_pins>;
-+/*
-+ * This eMMC is not populated on all boards, so disable it by
-+ * default and let the bootloader enable it, if it is present
-+ */
-+ status = "disabled";
-+};
-+
- &spi0 {
- status = "okay";
-
+++ /dev/null
-From 3217cdfe8a3eae76fafbebbe407be5985a7fd4c2 Mon Sep 17 00:00:00 2001
-From: Tomasz Maciej Nowak <tmn505@gmail.com>
-Date: Mon, 31 Dec 2018 14:18:50 +0100
-Subject: [PATCH] arm64: dts: armada-3720-espressobin: correct spi node
-
-The manufacturer of this board, ships it with various SPI NOR chips and
-increments U-Boot bootloader version along the time. There is no way to
-tell which is placed on the board since no revision bump takes place.
-This creates two issues.
-
-The first, cosmetic. Since the SPI chip may differ, there's message on
-boot stating that kernel expected w25q32dw and found different one. To
-correct this, remove optional device-specific compatible string. Being
-here lets replace bogus "spi-flash" string with proper one.
-
-The second is linked to partitions layout, it changed after commit [1]
-in Marvells downstream U-Boot fork, shifting environment location to the
-end of boot device. Since the new boards can have U-Boot with this
-change it can lead to improper results writing or reading from these
-partitions. We can't tell if users will update bootloader to recent
-version, so let's drop current layout.
-
-1. https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/81e7251252aefe1a6b829ed05f3586320cb45372
-
-Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
----
- .../dts/marvell/armada-3720-espressobin.dts | 18 +-----------------
- 1 file changed, 1 insertion(+), 17 deletions(-)
-
---- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
-+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
-@@ -90,25 +90,9 @@
-
- flash@0 {
- reg = <0>;
-- compatible = "winbond,w25q32dw", "jedec,spi-flash";
-+ compatible = "jedec,spi-nor";
- spi-max-frequency = <104000000>;
- m25p,fast-read;
--
-- partitions {
-- compatible = "fixed-partitions";
-- #address-cells = <1>;
-- #size-cells = <1>;
--
-- partition@0 {
-- label = "uboot";
-- reg = <0 0x180000>;
-- };
--
-- partition@180000 {
-- label = "ubootenv";
-- reg = <0x180000 0x10000>;
-- };
-- };
- };
- };
-
--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
-@@ -132,7 +132,7 @@
+@@ -137,7 +137,7 @@
dsa,member = <0 0>;
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
-@@ -843,6 +843,7 @@ static int advk_pcie_probe(struct platfo
+@@ -999,6 +999,7 @@ static int advk_pcie_probe(struct platfo
struct device *dev = &pdev->dev;
struct advk_pcie *pcie;
struct resource *res;
struct pci_host_bridge *bridge;
int ret, irq;
-@@ -896,13 +897,22 @@ static int advk_pcie_probe(struct platfo
+@@ -1054,13 +1055,22 @@ static int advk_pcie_probe(struct platfo
bridge->map_irq = of_irq_parse_and_map_pci;
bridge->swizzle_irq = pci_common_swizzle;
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
-@@ -29,9 +29,11 @@
+@@ -33,9 +33,11 @@
#define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
#define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5
#define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
#define PCIE_CORE_LINK_L0S_ENTRY BIT(0)
#define PCIE_CORE_LINK_TRAINING BIT(5)
-@@ -253,7 +255,8 @@ static void advk_pcie_setup_hw(struct ad
+@@ -276,7 +278,8 @@ static void advk_pcie_setup_hw(struct ad
/* Set PCIe Device Control and Status 1 PF0 register */
reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
(PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ <<
PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT);
-@@ -838,6 +841,58 @@ out_release_res:
+@@ -994,6 +997,58 @@ out_release_res:
return err;
}
static int advk_pcie_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
-@@ -912,6 +967,9 @@ static int advk_pcie_probe(struct platfo
+@@ -1070,6 +1125,9 @@ static int advk_pcie_probe(struct platfo
list_for_each_entry(child, &bus->children, node)
pcie_bus_configure_settings(child);
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
-@@ -324,8 +324,7 @@ static void advk_pcie_setup_hw(struct ad
+@@ -347,8 +347,7 @@ static void advk_pcie_setup_hw(struct ad
advk_pcie_wait_for_link(pcie);
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
-@@ -233,6 +233,8 @@ static int advk_pcie_wait_for_link(struc
+@@ -256,6 +256,8 @@ static void advk_pcie_wait_for_retrain(s
static void advk_pcie_setup_hw(struct advk_pcie *pcie)
{
u32 reg;
/* Set to Direct mode */
-@@ -267,10 +269,15 @@ static void advk_pcie_setup_hw(struct ad
+@@ -290,10 +292,15 @@ static void advk_pcie_setup_hw(struct ad
PCIE_CORE_CTRL2_TD_ENABLE;
advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
-@@ -46,6 +46,8 @@
- /* J9 */
- &pcie0 {
- status = "okay";
+@@ -49,6 +49,8 @@
+ phys = <&comphy1 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
+
+ max-link-speed = <1>;
};
+++ /dev/null
-From da58a931f248f423f917c3a0b3c94303aa30a738 Mon Sep 17 00:00:00 2001
-From: Maxime Chevallier <maxime.chevallier@bootlin.com>
-Date: Tue, 25 Sep 2018 15:59:39 +0200
-Subject: [PATCH] net: mvneta: Add support for 2500Mbps SGMII
-
-The mvneta controller can handle speeds up to 2500Mbps on the SGMII
-interface. This relies on serdes configuration, the lane must be
-configured at 3.125Gbps and we can't use in-band autoneg at that speed.
-
-The main issue when supporting that speed on this particular controller
-is that the link partner can send ethernet frames with a shortened
-preamble, which if not explicitly enabled in the controller will cause
-unexpected behaviours.
-
-This was tested on Armada 385, with the comphy configuration done in
-bootloader.
-
-Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/marvell/mvneta.c | 27 +++++++++++++++++++++++----
- 1 file changed, 23 insertions(+), 4 deletions(-)
-
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -221,6 +221,8 @@
- #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11)
- #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
- #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
-+#define MVNETA_GMAC_CTRL_4 0x2c90
-+#define MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE BIT(1)
- #define MVNETA_MIB_COUNTERS_BASE 0x3000
- #define MVNETA_MIB_LATE_COLLISION 0x7c
- #define MVNETA_DA_FILT_SPEC_MCAST 0x3400
-@@ -3359,6 +3361,7 @@ static void mvneta_validate(struct net_d
- if (state->interface != PHY_INTERFACE_MODE_NA &&
- state->interface != PHY_INTERFACE_MODE_QSGMII &&
- state->interface != PHY_INTERFACE_MODE_SGMII &&
-+ state->interface != PHY_INTERFACE_MODE_2500BASEX &&
- !phy_interface_mode_is_8023z(state->interface) &&
- !phy_interface_mode_is_rgmii(state->interface)) {
- bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
-@@ -3371,9 +3374,15 @@ static void mvneta_validate(struct net_d
-
- /* Asymmetric pause is unsupported */
- phylink_set(mask, Pause);
-- /* Half-duplex at speeds higher than 100Mbit is unsupported */
-- phylink_set(mask, 1000baseT_Full);
-- phylink_set(mask, 1000baseX_Full);
-+
-+ /* We cannot use 1Gbps when using the 2.5G interface. */
-+ if (state->interface == PHY_INTERFACE_MODE_2500BASEX) {
-+ phylink_set(mask, 2500baseT_Full);
-+ phylink_set(mask, 2500baseX_Full);
-+ } else {
-+ phylink_set(mask, 1000baseT_Full);
-+ phylink_set(mask, 1000baseX_Full);
-+ }
-
- if (!phy_interface_mode_is_8023z(state->interface)) {
- /* 10M and 100M are only supported in non-802.3z mode */
-@@ -3434,12 +3443,14 @@ static void mvneta_mac_config(struct net
- struct mvneta_port *pp = netdev_priv(ndev);
- u32 new_ctrl0, gmac_ctrl0 = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
- u32 new_ctrl2, gmac_ctrl2 = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
-+ u32 new_ctrl4, gmac_ctrl4 = mvreg_read(pp, MVNETA_GMAC_CTRL_4);
- u32 new_clk, gmac_clk = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
- u32 new_an, gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
-
- new_ctrl0 = gmac_ctrl0 & ~MVNETA_GMAC0_PORT_1000BASE_X;
- new_ctrl2 = gmac_ctrl2 & ~(MVNETA_GMAC2_INBAND_AN_ENABLE |
- MVNETA_GMAC2_PORT_RESET);
-+ new_ctrl4 = gmac_ctrl4 & ~(MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE);
- new_clk = gmac_clk & ~MVNETA_GMAC_1MS_CLOCK_ENABLE;
- new_an = gmac_an & ~(MVNETA_GMAC_INBAND_AN_ENABLE |
- MVNETA_GMAC_INBAND_RESTART_AN |
-@@ -3472,7 +3483,7 @@ static void mvneta_mac_config(struct net
- if (state->duplex)
- new_an |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
-
-- if (state->speed == SPEED_1000)
-+ if (state->speed == SPEED_1000 || state->speed == SPEED_2500)
- new_an |= MVNETA_GMAC_CONFIG_GMII_SPEED;
- else if (state->speed == SPEED_100)
- new_an |= MVNETA_GMAC_CONFIG_MII_SPEED;
-@@ -3511,10 +3522,18 @@ static void mvneta_mac_config(struct net
- MVNETA_GMAC_FORCE_LINK_DOWN);
- }
-
-+ /* When at 2.5G, the link partner can send frames with shortened
-+ * preambles.
-+ */
-+ if (state->speed == SPEED_2500)
-+ new_ctrl4 |= MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE;
-+
- if (new_ctrl0 != gmac_ctrl0)
- mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0);
- if (new_ctrl2 != gmac_ctrl2)
- mvreg_write(pp, MVNETA_GMAC_CTRL_2, new_ctrl2);
-+ if (new_ctrl4 != gmac_ctrl4)
-+ mvreg_write(pp, MVNETA_GMAC_CTRL_4, new_ctrl4);
- if (new_clk != gmac_clk)
- mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, new_clk);
- if (new_an != gmac_an)
+++ /dev/null
-From fbd1d5245372e48b494120a30fe0b34b304576c4 Mon Sep 17 00:00:00 2001
-From: Alexandre Belloni <alexandre.belloni@bootlin.com>
-Date: Fri, 9 Nov 2018 17:37:20 +0100
-Subject: [PATCH] net: mvneta: correct typo
-
-The reserved variable should be named reserved1.
-
-Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/marvell/mvneta.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -495,7 +495,7 @@ struct mvneta_port {
- #if defined(__LITTLE_ENDIAN)
- struct mvneta_tx_desc {
- u32 command; /* Options used by HW for packet transmitting.*/
-- u16 reserverd1; /* csum_l4 (for future use) */
-+ u16 reserved1; /* csum_l4 (for future use) */
- u16 data_size; /* Data size of transmitted packet in bytes */
- u32 buf_phys_addr; /* Physical addr of transmitted buffer */
- u32 reserved2; /* hw_cmd - (for future use, PMT) */
-@@ -520,7 +520,7 @@ struct mvneta_rx_desc {
- #else
- struct mvneta_tx_desc {
- u16 data_size; /* Data size of transmitted packet in bytes */
-- u16 reserverd1; /* csum_l4 (for future use) */
-+ u16 reserved1; /* csum_l4 (for future use) */
- u32 command; /* Options used by HW for packet transmitting.*/
- u32 reserved2; /* hw_cmd - (for future use, PMT) */
- u32 buf_phys_addr; /* Physical addr of transmitted buffer */
+++ /dev/null
-From 83e65df6dfece9eb588735459428f221eb930c0c Mon Sep 17 00:00:00 2001
-From: Maxime Chevallier <maxime.chevallier@bootlin.com>
-Date: Fri, 9 Nov 2018 09:17:33 +0100
-Subject: [PATCH] net: mvneta: Don't advertise 2.5G modes
-
-Using 2.5G speed relies on the SerDes lanes being configured
-accordingly. The lanes have to be reconfigured to switch between
-1G and 2.5G, and for now only the bootloader does this configuration.
-
-In the case we add a Comphy driver to handle switching the lanes
-dynamically, it's better for now to stick with supporting only 1G and
-add advertisement for 2.5G once we really are capable of handling both
-speeds without problem.
-
-Since the interface mode is initialy taken from the DT, we want to make
-sure that adding comphy support won't break boards that don't update
-their dtb.
-
-Fixes: da58a931f248 ("net: mvneta: Add support for 2500Mbps SGMII")
-Reported-by: Andrew Lunn <andrew@lunn.ch>
-Reported-by: Russell King <linux@armlinux.org.uk>
-Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/marvell/mvneta.c | 12 +++---------
- 1 file changed, 3 insertions(+), 9 deletions(-)
-
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -3361,7 +3361,6 @@ static void mvneta_validate(struct net_d
- if (state->interface != PHY_INTERFACE_MODE_NA &&
- state->interface != PHY_INTERFACE_MODE_QSGMII &&
- state->interface != PHY_INTERFACE_MODE_SGMII &&
-- state->interface != PHY_INTERFACE_MODE_2500BASEX &&
- !phy_interface_mode_is_8023z(state->interface) &&
- !phy_interface_mode_is_rgmii(state->interface)) {
- bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
-@@ -3375,14 +3374,9 @@ static void mvneta_validate(struct net_d
- /* Asymmetric pause is unsupported */
- phylink_set(mask, Pause);
-
-- /* We cannot use 1Gbps when using the 2.5G interface. */
-- if (state->interface == PHY_INTERFACE_MODE_2500BASEX) {
-- phylink_set(mask, 2500baseT_Full);
-- phylink_set(mask, 2500baseX_Full);
-- } else {
-- phylink_set(mask, 1000baseT_Full);
-- phylink_set(mask, 1000baseX_Full);
-- }
-+ /* Half-duplex at speeds higher than 100Mbit is unsupported */
-+ phylink_set(mask, 1000baseT_Full);
-+ phylink_set(mask, 1000baseX_Full);
-
- if (!phy_interface_mode_is_8023z(state->interface)) {
- /* 10M and 100M are only supported in non-802.3z mode */
+++ /dev/null
-From e4a3e9ff5ba9f6b67595ec2768ed4be2054c2aa5 Mon Sep 17 00:00:00 2001
-From: YueHaibing <yuehaibing@huawei.com>
-Date: Thu, 22 Nov 2018 14:42:00 +0800
-Subject: [PATCH] net: mvneta: remove redundant check for
- eee->tx_lpi_timer < 0
-
-fixes the smatch warning:
-
-drivers/net/ethernet/marvell/mvneta.c:4252 mvneta_ethtool_set_eee() warn:
- unsigned 'eee->tx_lpi_timer' is never less than zero.
-
-Signed-off-by: YueHaibing <yuehaibing@huawei.com>
-Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/marvell/mvneta.c | 3 +--
- 1 file changed, 1 insertion(+), 2 deletions(-)
-
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -4268,8 +4268,7 @@ static int mvneta_ethtool_set_eee(struct
-
- /* The Armada 37x documents do not give limits for this other than
- * it being an 8-bit register. */
-- if (eee->tx_lpi_enabled &&
-- (eee->tx_lpi_timer < 0 || eee->tx_lpi_timer > 255))
-+ if (eee->tx_lpi_enabled && eee->tx_lpi_timer > 255)
- return -EINVAL;
-
- lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0);
+++ /dev/null
-From a10c1c8191e04c21769656c2ca8e1c69a6218954 Mon Sep 17 00:00:00 2001
-From: Russell King <rmk+kernel@armlinux.org.uk>
-Date: Thu, 7 Feb 2019 16:19:26 +0000
-Subject: [PATCH] net: marvell: neta: add comphy support
-
-Add support for the common phy binding, so that we can reconfigure the
-comphy according to the desired ethernet speed. This will allow us to
-support 1000base-X and 2500base-X SFPs dynamically on SolidRun Clearfog.
-
-Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/marvell/mvneta.c | 45 +++++++++++++++++++++++++++++++----
- 1 file changed, 41 insertions(+), 4 deletions(-)
-
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -27,6 +27,7 @@
- #include <linux/of_irq.h>
- #include <linux/of_mdio.h>
- #include <linux/of_net.h>
-+#include <linux/phy/phy.h>
- #include <linux/phy.h>
- #include <linux/phylink.h>
- #include <linux/platform_device.h>
-@@ -438,6 +439,7 @@ struct mvneta_port {
- struct device_node *dn;
- unsigned int tx_csum_limit;
- struct phylink *phylink;
-+ struct phy *comphy;
-
- struct mvneta_bm *bm_priv;
- struct mvneta_bm_pool *pool_long;
-@@ -3168,6 +3170,8 @@ static void mvneta_start_dev(struct mvne
- {
- int cpu;
-
-+ WARN_ON(phy_power_on(pp->comphy));
-+
- mvneta_max_rx_size_set(pp, pp->pkt_size);
- mvneta_txq_max_tx_size_set(pp, pp->pkt_size);
-
-@@ -3230,6 +3234,8 @@ static void mvneta_stop_dev(struct mvnet
-
- mvneta_tx_reset(pp);
- mvneta_rx_reset(pp);
-+
-+ WARN_ON(phy_power_off(pp->comphy));
- }
-
- static void mvneta_percpu_enable(void *arg)
-@@ -3355,6 +3361,7 @@ static int mvneta_set_mac_addr(struct ne
- static void mvneta_validate(struct net_device *ndev, unsigned long *supported,
- struct phylink_link_state *state)
- {
-+ struct mvneta_port *pp = netdev_priv(ndev);
- __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
-
- /* We only support QSGMII, SGMII, 802.3z and RGMII modes */
-@@ -3375,8 +3382,13 @@ static void mvneta_validate(struct net_d
- phylink_set(mask, Pause);
-
- /* Half-duplex at speeds higher than 100Mbit is unsupported */
-- phylink_set(mask, 1000baseT_Full);
-- phylink_set(mask, 1000baseX_Full);
-+ if (pp->comphy || state->interface != PHY_INTERFACE_MODE_2500BASEX) {
-+ phylink_set(mask, 1000baseT_Full);
-+ phylink_set(mask, 1000baseX_Full);
-+ }
-+ if (pp->comphy || state->interface == PHY_INTERFACE_MODE_2500BASEX) {
-+ phylink_set(mask, 2500baseX_Full);
-+ }
-
- if (!phy_interface_mode_is_8023z(state->interface)) {
- /* 10M and 100M are only supported in non-802.3z mode */
-@@ -3390,6 +3402,11 @@ static void mvneta_validate(struct net_d
- __ETHTOOL_LINK_MODE_MASK_NBITS);
- bitmap_and(state->advertising, state->advertising, mask,
- __ETHTOOL_LINK_MODE_MASK_NBITS);
-+
-+ /* We can only operate at 2500BaseX or 1000BaseX. If requested
-+ * to advertise both, only report advertising at 2500BaseX.
-+ */
-+ phylink_helper_basex_speed(state);
- }
-
- static int mvneta_mac_link_state(struct net_device *ndev,
-@@ -3401,7 +3418,9 @@ static int mvneta_mac_link_state(struct
- gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
-
- if (gmac_stat & MVNETA_GMAC_SPEED_1000)
-- state->speed = SPEED_1000;
-+ state->speed =
-+ state->interface == PHY_INTERFACE_MODE_2500BASEX ?
-+ SPEED_2500 : SPEED_1000;
- else if (gmac_stat & MVNETA_GMAC_SPEED_100)
- state->speed = SPEED_100;
- else
-@@ -3516,12 +3535,20 @@ static void mvneta_mac_config(struct net
- MVNETA_GMAC_FORCE_LINK_DOWN);
- }
-
-+
- /* When at 2.5G, the link partner can send frames with shortened
- * preambles.
- */
- if (state->speed == SPEED_2500)
- new_ctrl4 |= MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE;
-
-+ if (pp->comphy &&
-+ (state->interface == PHY_INTERFACE_MODE_SGMII ||
-+ state->interface == PHY_INTERFACE_MODE_1000BASEX ||
-+ state->interface == PHY_INTERFACE_MODE_2500BASEX))
-+ WARN_ON(phy_set_mode_ext(pp->comphy, PHY_MODE_ETHERNET,
-+ state->interface));
-+
- if (new_ctrl0 != gmac_ctrl0)
- mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0);
- if (new_ctrl2 != gmac_ctrl2)
-@@ -4434,7 +4461,7 @@ static int mvneta_port_power_up(struct m
- if (phy_mode == PHY_INTERFACE_MODE_QSGMII)
- mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO);
- else if (phy_mode == PHY_INTERFACE_MODE_SGMII ||
-- phy_mode == PHY_INTERFACE_MODE_1000BASEX)
-+ phy_interface_mode_is_8023z(phy_mode))
- mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
- else if (!phy_interface_mode_is_rgmii(phy_mode))
- return -EINVAL;
-@@ -4451,6 +4478,7 @@ static int mvneta_probe(struct platform_
- struct mvneta_port *pp;
- struct net_device *dev;
- struct phylink *phylink;
-+ struct phy *comphy;
- const char *dt_mac_addr;
- char hw_mac_addr[ETH_ALEN];
- const char *mac_from;
-@@ -4476,6 +4504,14 @@ static int mvneta_probe(struct platform_
- goto err_free_irq;
- }
-
-+ comphy = devm_of_phy_get(&pdev->dev, dn, NULL);
-+ if (comphy == ERR_PTR(-EPROBE_DEFER)) {
-+ err = -EPROBE_DEFER;
-+ goto err_free_irq;
-+ } else if (IS_ERR(comphy)) {
-+ comphy = NULL;
-+ }
-+
- phylink = phylink_create(dev, pdev->dev.fwnode, phy_mode,
- &mvneta_phylink_ops);
- if (IS_ERR(phylink)) {
-@@ -4492,6 +4528,7 @@ static int mvneta_probe(struct platform_
- pp = netdev_priv(dev);
- spin_lock_init(&pp->lock);
- pp->phylink = phylink;
-+ pp->comphy = comphy;
- pp->phy_interface = phy_mode;
- pp->dn = dn;
-
+++ /dev/null
-From 031b922bfd60c771588911112f8632783de08e5c Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <marek.behun@nic.cz>
-Date: Mon, 25 Feb 2019 17:43:03 +0100
-Subject: [PATCH] net: marvell: neta: disable comphy when setting mode
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The comphy driver for Armada 3700 by Miquèl Raynal (which is currently
-in linux-next) does not actually set comphy mode when phy_set_mode_ext
-is called. The mode is set at next call of phy_power_on.
-
-Update the driver to semantics similar to mvpp2: helper
-mvneta_comphy_init sets comphy mode and powers it on.
-When mode is to be changed in mvneta_mac_config, first power the comphy
-off, then call mvneta_comphy_init (which sets the mode to new one).
-
-Only do this when new mode is different from old mode.
-
-This should also work for Armada 38x, since in that comphy driver
-methods power_on and power_off are unimplemented.
-
-Signed-off-by: Marek Behún <marek.behun@nic.cz>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/marvell/mvneta.c | 28 +++++++++++++++++++++++-----
- 1 file changed, 23 insertions(+), 5 deletions(-)
-
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -3166,11 +3166,26 @@ static int mvneta_setup_txqs(struct mvne
- return 0;
- }
-
-+static int mvneta_comphy_init(struct mvneta_port *pp)
-+{
-+ int ret;
-+
-+ if (!pp->comphy)
-+ return 0;
-+
-+ ret = phy_set_mode_ext(pp->comphy, PHY_MODE_ETHERNET,
-+ pp->phy_interface);
-+ if (ret)
-+ return ret;
-+
-+ return phy_power_on(pp->comphy);
-+}
-+
- static void mvneta_start_dev(struct mvneta_port *pp)
- {
- int cpu;
-
-- WARN_ON(phy_power_on(pp->comphy));
-+ WARN_ON(mvneta_comphy_init(pp));
-
- mvneta_max_rx_size_set(pp, pp->pkt_size);
- mvneta_txq_max_tx_size_set(pp, pp->pkt_size);
-@@ -3542,12 +3557,15 @@ static void mvneta_mac_config(struct net
- if (state->speed == SPEED_2500)
- new_ctrl4 |= MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE;
-
-- if (pp->comphy &&
-+ if (pp->comphy && pp->phy_interface != state->interface &&
- (state->interface == PHY_INTERFACE_MODE_SGMII ||
- state->interface == PHY_INTERFACE_MODE_1000BASEX ||
-- state->interface == PHY_INTERFACE_MODE_2500BASEX))
-- WARN_ON(phy_set_mode_ext(pp->comphy, PHY_MODE_ETHERNET,
-- state->interface));
-+ state->interface == PHY_INTERFACE_MODE_2500BASEX)) {
-+ pp->phy_interface = state->interface;
-+
-+ WARN_ON(phy_power_off(pp->comphy));
-+ WARN_ON(mvneta_comphy_init(pp));
-+ }
-
- if (new_ctrl0 != gmac_ctrl0)
- mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0);
+++ /dev/null
-From eda3d1b0228484fb52b7244a68fd4cc8a985ed10 Mon Sep 17 00:00:00 2001
-From: Maxime Chevallier <maxime.chevallier@bootlin.com>
-Date: Wed, 27 Mar 2019 17:31:06 +0100
-Subject: [PATCH] net: mvneta: Add 2500BaseT support
-
-Some PHYs will use the 2500BaseX PHY_INTERFACE_MODE when being linked
-with a partner using 2.5GBaseT.
-
-Since we can't autonegotiate this speed between the MAC and the PHY, we
-need to have the proper comphy support enabled, to make sure we can
-safely advertise 2.5G and 1G in BaseT and be able to switch between both
-corresponding PHY interface modes. This is now possible since comphy
-support was added to this driver.
-
-This commit adds the 2500BaseT mode to the list of supported modes when
-using 2500BaseX, and was tested on a setup with an Armada385 and a
-88E2010 PHY, both with and without the comphy node in the DT.
-
-Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/marvell/mvneta.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -3402,6 +3402,7 @@ static void mvneta_validate(struct net_d
- phylink_set(mask, 1000baseX_Full);
- }
- if (pp->comphy || state->interface == PHY_INTERFACE_MODE_2500BASEX) {
-+ phylink_set(mask, 2500baseT_Full);
- phylink_set(mask, 2500baseX_Full);
- }
-
+++ /dev/null
-From c2a90025ad09d830c8d8ae69f485eac6aaaa2472 Mon Sep 17 00:00:00 2001
-From: Quentin Schulz <quentin.schulz@bootlin.com>
-Date: Thu, 4 Oct 2018 14:22:03 +0200
-Subject: [PATCH] phy: add QSGMII and PCIE modes
-
-Prepare for upcoming phys that'll handle QSGMII or PCIe.
-
-Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
-Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- include/linux/phy/phy.h | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/include/linux/phy/phy.h
-+++ b/include/linux/phy/phy.h
-@@ -37,9 +37,11 @@ enum phy_mode {
- PHY_MODE_USB_OTG,
- PHY_MODE_SGMII,
- PHY_MODE_2500SGMII,
-+ PHY_MODE_QSGMII,
- PHY_MODE_10GKR,
- PHY_MODE_UFS_HS_A,
- PHY_MODE_UFS_HS_B,
-+ PHY_MODE_PCIE,
- };
-
- /**
+++ /dev/null
-From 2af8caeee47846a84bc96abc3a72f7c991153040 Mon Sep 17 00:00:00 2001
-From: Grygorii Strashko <grygorii.strashko@ti.com>
-Date: Mon, 19 Nov 2018 19:24:21 -0600
-Subject: [PATCH] phy: core: add PHY_MODE_ETHERNET
-
-Add new PHY's mode to be used by Ethernet PHY interface drivers or
-multipurpose PHYs like serdes. It will be reused in further changes.
-
-Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
-Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
----
- include/linux/phy/phy.h | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/include/linux/phy/phy.h
-+++ b/include/linux/phy/phy.h
-@@ -42,6 +42,7 @@ enum phy_mode {
- PHY_MODE_UFS_HS_A,
- PHY_MODE_UFS_HS_B,
- PHY_MODE_PCIE,
-+ PHY_MODE_ETHERNET,
- };
-
- /**
+++ /dev/null
-From e1706720408e72fb883f6b151c2b3b23d8e7e5b2 Mon Sep 17 00:00:00 2001
-From: John Hubbard <jhubbard@nvidia.com>
-Date: Sat, 12 Jan 2019 17:29:09 -0800
-Subject: [PATCH] phy: fix build breakage: add PHY_MODE_SATA
-
-Commit 49e54187ae0b ("ata: libahci_platform: comply to PHY framework") uses
-the PHY_MODE_SATA, but that enum had not yet been added. This caused a
-build failure for me, with today's linux.git.
-
-Also, there is a potentially conflicting (mis-named) PHY_MODE_SATA, hiding
-in the Marvell Berlin SATA PHY driver.
-
-Fix the build by:
-
- 1) Renaming Marvell's defined value to a more scoped name,
- in order to avoid any potential conflicts: PHY_BERLIN_MODE_SATA.
-
- 2) Adding the missing enum, which was going to be added anyway as part
- of [1].
-
-[1] https://lkml.kernel.org/r/20190108163124.6409-3-miquel.raynal@bootlin.com
-
-Fixes: 49e54187ae0b ("ata: libahci_platform: comply to PHY framework")
-
-Signed-off-by: John Hubbard <jhubbard@nvidia.com>
-Acked-by: Jens Axboe <axboe@kernel.dk>
-Acked-by: Olof Johansson <olof@lixom.net>
-Cc: Grzegorz Jaszczyk <jaz@semihalf.com>
-Cc: Miquel Raynal <miquel.raynal@bootlin.com>
-Cc: Hans de Goede <hdegoede@redhat.com>
-Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
----
- include/linux/phy/phy.h | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/include/linux/phy/phy.h
-+++ b/include/linux/phy/phy.h
-@@ -43,6 +43,7 @@ enum phy_mode {
- PHY_MODE_UFS_HS_B,
- PHY_MODE_PCIE,
- PHY_MODE_ETHERNET,
-+ PHY_MODE_SATA
- };
-
- /**
+++ /dev/null
-From 79a5a18aa9d1062205cdcfa183d4cd5241d1b8da Mon Sep 17 00:00:00 2001
-From: Grygorii Strashko <grygorii.strashko@ti.com>
-Date: Mon, 19 Nov 2018 19:24:20 -0600
-Subject: [PATCH] phy: core: rework phy_set_mode to accept phy mode and submode
-
-Currently the attempt to add support for Ethernet interface mode PHY
-(MII/GMII/RGMII) will lead to the necessity of extending enum phy_mode and
-duplicate there values from phy_interface_t enum (or introduce more PHY
-callbacks) [1]. Both approaches are ineffective and would lead to fast
-bloating of enum phy_mode or struct phy_ops in the process of adding more
-PHYs for different subsystems which will make them unmaintainable.
-
-As discussed in [1] the solution could be to introduce dual level PHYs mode
-configuration - PHY mode and PHY submode. The PHY mode will define generic
-PHY type (subsystem - PCIE/ETHERNET/USB_) while the PHY submode - subsystem
-specific interface mode. The last is usually already defined in
-corresponding subsystem headers (phy_interface_t for Ethernet, enum
-usb_device_speed for USB).
-
-This patch is cumulative change which refactors PHY framework code to
-support dual level PHYs mode configuration - PHY mode and PHY submode. It
-extends .set_mode() callback to support additional parameter "int submode"
-and converts all corresponding PHY drivers to support new .set_mode()
-callback declaration.
-The new extended PHY API
- int phy_set_mode_ext(struct phy *phy, enum phy_mode mode, int submode)
-is introduced to support dual level PHYs mode configuration and existing
-phy_set_mode() API is converted to macros, so PHY framework consumers do
-not need to be changed (~21 matches).
-
-[1] http://lkml.kernel.org/r/d63588f6-9ab0-848a-5ad4-8073143bd95d@ti.com
-Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
-Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
----
- drivers/phy/allwinner/phy-sun4i-usb.c | 3 ++-
- drivers/phy/amlogic/phy-meson-gxl-usb2.c | 5 +++--
- drivers/phy/amlogic/phy-meson-gxl-usb3.c | 5 +++--
- drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 3 ++-
- drivers/phy/mediatek/phy-mtk-tphy.c | 2 +-
- drivers/phy/mediatek/phy-mtk-xsphy.c | 2 +-
- drivers/phy/mscc/phy-ocelot-serdes.c | 2 +-
- drivers/phy/phy-core.c | 6 +++---
- drivers/phy/qualcomm/phy-qcom-qmp.c | 3 ++-
- drivers/phy/qualcomm/phy-qcom-qusb2.c | 3 ++-
- drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.c | 3 ++-
- drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.c | 3 ++-
- drivers/phy/qualcomm/phy-qcom-usb-hs.c | 3 ++-
- drivers/phy/ti/phy-da8xx-usb.c | 3 ++-
- drivers/phy/ti/phy-tusb1210.c | 2 +-
- include/linux/phy/phy.h | 13 ++++++++++---
- 16 files changed, 39 insertions(+), 22 deletions(-)
-
---- a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
-+++ b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
-@@ -512,7 +512,8 @@ static int mvebu_comphy_power_on(struct
- return ret;
- }
-
--static int mvebu_comphy_set_mode(struct phy *phy, enum phy_mode mode)
-+static int mvebu_comphy_set_mode(struct phy *phy,
-+ enum phy_mode mode, int submode)
- {
- struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
-
---- a/drivers/phy/phy-core.c
-+++ b/drivers/phy/phy-core.c
-@@ -360,7 +360,7 @@ int phy_power_off(struct phy *phy)
- }
- EXPORT_SYMBOL_GPL(phy_power_off);
-
--int phy_set_mode(struct phy *phy, enum phy_mode mode)
-+int phy_set_mode_ext(struct phy *phy, enum phy_mode mode, int submode)
- {
- int ret;
-
-@@ -368,14 +368,14 @@ int phy_set_mode(struct phy *phy, enum p
- return 0;
-
- mutex_lock(&phy->mutex);
-- ret = phy->ops->set_mode(phy, mode);
-+ ret = phy->ops->set_mode(phy, mode, submode);
- if (!ret)
- phy->attrs.mode = mode;
- mutex_unlock(&phy->mutex);
-
- return ret;
- }
--EXPORT_SYMBOL_GPL(phy_set_mode);
-+EXPORT_SYMBOL_GPL(phy_set_mode_ext);
-
- int phy_reset(struct phy *phy)
- {
---- a/include/linux/phy/phy.h
-+++ b/include/linux/phy/phy.h
-@@ -62,7 +62,7 @@ struct phy_ops {
- int (*exit)(struct phy *phy);
- int (*power_on)(struct phy *phy);
- int (*power_off)(struct phy *phy);
-- int (*set_mode)(struct phy *phy, enum phy_mode mode);
-+ int (*set_mode)(struct phy *phy, enum phy_mode mode, int submode);
- int (*reset)(struct phy *phy);
- int (*calibrate)(struct phy *phy);
- struct module *owner;
-@@ -166,7 +166,10 @@ int phy_init(struct phy *phy);
- int phy_exit(struct phy *phy);
- int phy_power_on(struct phy *phy);
- int phy_power_off(struct phy *phy);
--int phy_set_mode(struct phy *phy, enum phy_mode mode);
-+int phy_set_mode_ext(struct phy *phy, enum phy_mode mode, int submode);
-+#define phy_set_mode(phy, mode) \
-+ phy_set_mode_ext(phy, mode, 0)
-+
- static inline enum phy_mode phy_get_mode(struct phy *phy)
- {
- return phy->attrs.mode;
-@@ -280,13 +283,17 @@ static inline int phy_power_off(struct p
- return -ENOSYS;
- }
-
--static inline int phy_set_mode(struct phy *phy, enum phy_mode mode)
-+static inline int phy_set_mode_ext(struct phy *phy, enum phy_mode mode,
-+ int submode)
- {
- if (!phy)
- return 0;
- return -ENOSYS;
- }
-
-+#define phy_set_mode(phy, mode) \
-+ phy_set_mode_ext(phy, mode, 0)
-+
- static inline enum phy_mode phy_get_mode(struct phy *phy)
- {
- return PHY_MODE_INVALID;
+++ /dev/null
-From 9695375a3f4a604406f2e61f2b735eca1de931ed Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <miquel.raynal@bootlin.com>
-Date: Tue, 8 Jan 2019 17:31:20 +0100
-Subject: [PATCH] phy: add A3700 COMPHY support
-
-Add a driver to support COMPHY, a hardware block providing shared
-serdes PHYs on Marvell Armada 3700. This driver uses SMC calls and
-rely on having an up-to-date firmware.
-
-SATA, PCie and USB3 host mode have been tested successfully with an
-ESPRESSObin. (HS)SGMII mode cannot be tested with this platform.
-
-Evan worked on the original driver structure and Grzegorz on the SMC
-calls rework. The structure of this driver has been copied from
-Antoine Tenart work on CP110 COMPHY driver.
-
-Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
-Co-developed-by: Evan Wang <xswang@marvell.com>
-Signed-off-by: Evan Wang <xswang@marvell.com>
-Co-developed-by: Grzegorz Jaszczyk <jaz@semihalf.com>
-Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
-Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
----
- drivers/phy/marvell/Kconfig | 12 +
- drivers/phy/marvell/Makefile | 1 +
- drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 318 +++++++++++++++++++++++++++
- 3 files changed, 331 insertions(+)
- create mode 100644 drivers/phy/marvell/phy-mvebu-a3700-comphy.c
-
---- a/drivers/phy/marvell/Kconfig
-+++ b/drivers/phy/marvell/Kconfig
-@@ -21,6 +21,18 @@ config PHY_BERLIN_USB
- help
- Enable this to support the USB PHY on Marvell Berlin SoCs.
-
-+config PHY_MVEBU_A3700_COMPHY
-+ tristate "Marvell A3700 comphy driver"
-+ depends on ARCH_MVEBU || COMPILE_TEST
-+ depends on OF
-+ depends on HAVE_ARM_SMCCC
-+ default y
-+ select GENERIC_PHY
-+ help
-+ This driver allows to control the comphy, a hardware block providing
-+ shared serdes PHYs on Marvell Armada 3700. Its serdes lanes can be
-+ used by various controllers: Ethernet, SATA, USB3, PCIe.
-+
- config PHY_MVEBU_CP110_COMPHY
- tristate "Marvell CP110 comphy driver"
- depends on ARCH_MVEBU || COMPILE_TEST
---- a/drivers/phy/marvell/Makefile
-+++ b/drivers/phy/marvell/Makefile
-@@ -2,6 +2,7 @@
- obj-$(CONFIG_ARMADA375_USBCLUSTER_PHY) += phy-armada375-usb2.o
- obj-$(CONFIG_PHY_BERLIN_SATA) += phy-berlin-sata.o
- obj-$(CONFIG_PHY_BERLIN_USB) += phy-berlin-usb.o
-+obj-$(CONFIG_PHY_MVEBU_A3700_COMPHY) += phy-mvebu-a3700-comphy.o
- obj-$(CONFIG_PHY_MVEBU_CP110_COMPHY) += phy-mvebu-cp110-comphy.o
- obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
- obj-$(CONFIG_PHY_PXA_28NM_HSIC) += phy-pxa-28nm-hsic.o
---- /dev/null
-+++ b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
-@@ -0,0 +1,318 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (C) 2018 Marvell
-+ *
-+ * Authors:
-+ * Evan Wang <xswang@marvell.com>
-+ * Miquèl Raynal <miquel.raynal@bootlin.com>
-+ *
-+ * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
-+ * SMC call initial support done by Grzegorz Jaszczyk.
-+ */
-+
-+#include <linux/arm-smccc.h>
-+#include <linux/io.h>
-+#include <linux/iopoll.h>
-+#include <linux/mfd/syscon.h>
-+#include <linux/module.h>
-+#include <linux/phy.h>
-+#include <linux/phy/phy.h>
-+#include <linux/platform_device.h>
-+
-+#define MVEBU_A3700_COMPHY_LANES 3
-+#define MVEBU_A3700_COMPHY_PORTS 2
-+
-+/* COMPHY Fast SMC function identifiers */
-+#define COMPHY_SIP_POWER_ON 0x82000001
-+#define COMPHY_SIP_POWER_OFF 0x82000002
-+#define COMPHY_SIP_PLL_LOCK 0x82000003
-+
-+#define COMPHY_FW_MODE_SATA 0x1
-+#define COMPHY_FW_MODE_SGMII 0x2
-+#define COMPHY_FW_MODE_HS_SGMII 0x3
-+#define COMPHY_FW_MODE_USB3H 0x4
-+#define COMPHY_FW_MODE_USB3D 0x5
-+#define COMPHY_FW_MODE_PCIE 0x6
-+#define COMPHY_FW_MODE_RXAUI 0x7
-+#define COMPHY_FW_MODE_XFI 0x8
-+#define COMPHY_FW_MODE_SFI 0x9
-+#define COMPHY_FW_MODE_USB3 0xa
-+
-+#define COMPHY_FW_SPEED_1_25G 0 /* SGMII 1G */
-+#define COMPHY_FW_SPEED_2_5G 1
-+#define COMPHY_FW_SPEED_3_125G 2 /* SGMII 2.5G */
-+#define COMPHY_FW_SPEED_5G 3
-+#define COMPHY_FW_SPEED_5_15625G 4 /* XFI 5G */
-+#define COMPHY_FW_SPEED_6G 5
-+#define COMPHY_FW_SPEED_10_3125G 6 /* XFI 10G */
-+#define COMPHY_FW_SPEED_MAX 0x3F
-+
-+#define COMPHY_FW_MODE(mode) ((mode) << 12)
-+#define COMPHY_FW_NET(mode, idx, speed) (COMPHY_FW_MODE(mode) | \
-+ ((idx) << 8) | \
-+ ((speed) << 2))
-+#define COMPHY_FW_PCIE(mode, idx, speed, width) (COMPHY_FW_NET(mode, idx, speed) | \
-+ ((width) << 18))
-+
-+struct mvebu_a3700_comphy_conf {
-+ unsigned int lane;
-+ enum phy_mode mode;
-+ int submode;
-+ unsigned int port;
-+ u32 fw_mode;
-+};
-+
-+#define MVEBU_A3700_COMPHY_CONF(_lane, _mode, _smode, _port, _fw) \
-+ { \
-+ .lane = _lane, \
-+ .mode = _mode, \
-+ .submode = _smode, \
-+ .port = _port, \
-+ .fw_mode = _fw, \
-+ }
-+
-+#define MVEBU_A3700_COMPHY_CONF_GEN(_lane, _mode, _port, _fw) \
-+ MVEBU_A3700_COMPHY_CONF(_lane, _mode, PHY_INTERFACE_MODE_NA, _port, _fw)
-+
-+#define MVEBU_A3700_COMPHY_CONF_ETH(_lane, _smode, _port, _fw) \
-+ MVEBU_A3700_COMPHY_CONF(_lane, PHY_MODE_ETHERNET, _smode, _port, _fw)
-+
-+static const struct mvebu_a3700_comphy_conf mvebu_a3700_comphy_modes[] = {
-+ /* lane 0 */
-+ MVEBU_A3700_COMPHY_CONF_GEN(0, PHY_MODE_USB_HOST_SS, 0,
-+ COMPHY_FW_MODE_USB3H),
-+ MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_SGMII, 1,
-+ COMPHY_FW_MODE_SGMII),
-+ MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_2500BASEX, 1,
-+ COMPHY_FW_MODE_HS_SGMII),
-+ /* lane 1 */
-+ MVEBU_A3700_COMPHY_CONF_GEN(1, PHY_MODE_PCIE, 0,
-+ COMPHY_FW_MODE_PCIE),
-+ MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_SGMII, 0,
-+ COMPHY_FW_MODE_SGMII),
-+ MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_2500BASEX, 0,
-+ COMPHY_FW_MODE_HS_SGMII),
-+ /* lane 2 */
-+ MVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_SATA, 0,
-+ COMPHY_FW_MODE_SATA),
-+ MVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_USB_HOST_SS, 0,
-+ COMPHY_FW_MODE_USB3H),
-+};
-+
-+struct mvebu_a3700_comphy_lane {
-+ struct device *dev;
-+ unsigned int id;
-+ enum phy_mode mode;
-+ int submode;
-+ int port;
-+};
-+
-+static int mvebu_a3700_comphy_smc(unsigned long function, unsigned long lane,
-+ unsigned long mode)
-+{
-+ struct arm_smccc_res res;
-+
-+ arm_smccc_smc(function, lane, mode, 0, 0, 0, 0, 0, &res);
-+
-+ return res.a0;
-+}
-+
-+static int mvebu_a3700_comphy_get_fw_mode(int lane, int port,
-+ enum phy_mode mode,
-+ int submode)
-+{
-+ int i, n = ARRAY_SIZE(mvebu_a3700_comphy_modes);
-+
-+ /* Unused PHY mux value is 0x0 */
-+ if (mode == PHY_MODE_INVALID)
-+ return -EINVAL;
-+
-+ for (i = 0; i < n; i++) {
-+ if (mvebu_a3700_comphy_modes[i].lane == lane &&
-+ mvebu_a3700_comphy_modes[i].port == port &&
-+ mvebu_a3700_comphy_modes[i].mode == mode &&
-+ mvebu_a3700_comphy_modes[i].submode == submode)
-+ break;
-+ }
-+
-+ if (i == n)
-+ return -EINVAL;
-+
-+ return mvebu_a3700_comphy_modes[i].fw_mode;
-+}
-+
-+static int mvebu_a3700_comphy_set_mode(struct phy *phy, enum phy_mode mode,
-+ int submode)
-+{
-+ struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);
-+ int fw_mode;
-+
-+ if (submode == PHY_INTERFACE_MODE_1000BASEX)
-+ submode = PHY_INTERFACE_MODE_SGMII;
-+
-+ fw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id, lane->port, mode,
-+ submode);
-+ if (fw_mode < 0) {
-+ dev_err(lane->dev, "invalid COMPHY mode\n");
-+ return fw_mode;
-+ }
-+
-+ /* Just remember the mode, ->power_on() will do the real setup */
-+ lane->mode = mode;
-+ lane->submode = submode;
-+
-+ return 0;
-+}
-+
-+static int mvebu_a3700_comphy_power_on(struct phy *phy)
-+{
-+ struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);
-+ u32 fw_param;
-+ int fw_mode;
-+
-+ fw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id, lane->port,
-+ lane->mode, lane->submode);
-+ if (fw_mode < 0) {
-+ dev_err(lane->dev, "invalid COMPHY mode\n");
-+ return fw_mode;
-+ }
-+
-+ switch (lane->mode) {
-+ case PHY_MODE_USB_HOST_SS:
-+ dev_dbg(lane->dev, "set lane %d to USB3 host mode\n", lane->id);
-+ fw_param = COMPHY_FW_MODE(fw_mode);
-+ break;
-+ case PHY_MODE_SATA:
-+ dev_dbg(lane->dev, "set lane %d to SATA mode\n", lane->id);
-+ fw_param = COMPHY_FW_MODE(fw_mode);
-+ break;
-+ case PHY_MODE_ETHERNET:
-+ switch (lane->submode) {
-+ case PHY_INTERFACE_MODE_SGMII:
-+ dev_dbg(lane->dev, "set lane %d to SGMII mode\n",
-+ lane->id);
-+ fw_param = COMPHY_FW_NET(fw_mode, lane->port,
-+ COMPHY_FW_SPEED_1_25G);
-+ break;
-+ case PHY_INTERFACE_MODE_2500BASEX:
-+ dev_dbg(lane->dev, "set lane %d to HS SGMII mode\n",
-+ lane->id);
-+ fw_param = COMPHY_FW_NET(fw_mode, lane->port,
-+ COMPHY_FW_SPEED_3_125G);
-+ break;
-+ default:
-+ dev_err(lane->dev, "unsupported PHY submode (%d)\n",
-+ lane->submode);
-+ return -ENOTSUPP;
-+ }
-+ break;
-+ case PHY_MODE_PCIE:
-+ dev_dbg(lane->dev, "set lane %d to PCIe mode\n", lane->id);
-+ fw_param = COMPHY_FW_PCIE(fw_mode, lane->port,
-+ COMPHY_FW_SPEED_5G,
-+ phy->attrs.bus_width);
-+ break;
-+ default:
-+ dev_err(lane->dev, "unsupported PHY mode (%d)\n", lane->mode);
-+ return -ENOTSUPP;
-+ }
-+
-+ return mvebu_a3700_comphy_smc(COMPHY_SIP_POWER_ON, lane->id, fw_param);
-+}
-+
-+static int mvebu_a3700_comphy_power_off(struct phy *phy)
-+{
-+ struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);
-+
-+ return mvebu_a3700_comphy_smc(COMPHY_SIP_POWER_OFF, lane->id, 0);
-+}
-+
-+static const struct phy_ops mvebu_a3700_comphy_ops = {
-+ .power_on = mvebu_a3700_comphy_power_on,
-+ .power_off = mvebu_a3700_comphy_power_off,
-+ .set_mode = mvebu_a3700_comphy_set_mode,
-+ .owner = THIS_MODULE,
-+};
-+
-+static struct phy *mvebu_a3700_comphy_xlate(struct device *dev,
-+ struct of_phandle_args *args)
-+{
-+ struct mvebu_a3700_comphy_lane *lane;
-+ struct phy *phy;
-+
-+ if (WARN_ON(args->args[0] >= MVEBU_A3700_COMPHY_PORTS))
-+ return ERR_PTR(-EINVAL);
-+
-+ phy = of_phy_simple_xlate(dev, args);
-+ if (IS_ERR(phy))
-+ return phy;
-+
-+ lane = phy_get_drvdata(phy);
-+ lane->port = args->args[0];
-+
-+ return phy;
-+}
-+
-+static int mvebu_a3700_comphy_probe(struct platform_device *pdev)
-+{
-+ struct phy_provider *provider;
-+ struct device_node *child;
-+
-+ for_each_available_child_of_node(pdev->dev.of_node, child) {
-+ struct mvebu_a3700_comphy_lane *lane;
-+ struct phy *phy;
-+ int ret;
-+ u32 lane_id;
-+
-+ ret = of_property_read_u32(child, "reg", &lane_id);
-+ if (ret < 0) {
-+ dev_err(&pdev->dev, "missing 'reg' property (%d)\n",
-+ ret);
-+ continue;
-+ }
-+
-+ if (lane_id >= MVEBU_A3700_COMPHY_LANES) {
-+ dev_err(&pdev->dev, "invalid 'reg' property\n");
-+ continue;
-+ }
-+
-+ lane = devm_kzalloc(&pdev->dev, sizeof(*lane), GFP_KERNEL);
-+ if (!lane)
-+ return -ENOMEM;
-+
-+ phy = devm_phy_create(&pdev->dev, child,
-+ &mvebu_a3700_comphy_ops);
-+ if (IS_ERR(phy))
-+ return PTR_ERR(phy);
-+
-+ lane->dev = &pdev->dev;
-+ lane->mode = PHY_MODE_INVALID;
-+ lane->submode = PHY_INTERFACE_MODE_NA;
-+ lane->id = lane_id;
-+ lane->port = -1;
-+ phy_set_drvdata(phy, lane);
-+ }
-+
-+ provider = devm_of_phy_provider_register(&pdev->dev,
-+ mvebu_a3700_comphy_xlate);
-+ return PTR_ERR_OR_ZERO(provider);
-+}
-+
-+static const struct of_device_id mvebu_a3700_comphy_of_match_table[] = {
-+ { .compatible = "marvell,comphy-a3700" },
-+ { },
-+};
-+MODULE_DEVICE_TABLE(of, mvebu_a3700_comphy_of_match_table);
-+
-+static struct platform_driver mvebu_a3700_comphy_driver = {
-+ .probe = mvebu_a3700_comphy_probe,
-+ .driver = {
-+ .name = "mvebu-a3700-comphy",
-+ .of_match_table = mvebu_a3700_comphy_of_match_table,
-+ },
-+};
-+module_platform_driver(mvebu_a3700_comphy_driver);
-+
-+MODULE_AUTHOR("Miquèl Raynal <miquel.raynal@bootlin.com>");
-+MODULE_DESCRIPTION("Common PHY driver for A3700");
-+MODULE_LICENSE("GPL v2");
+++ /dev/null
-From 2ef303f0fe44feee4a3ca8bd62fca86c105927d2 Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <miquel.raynal@bootlin.com>
-Date: Tue, 8 Jan 2019 17:31:24 +0100
-Subject: [PATCH] arm64: dts: marvell: armada-37xx: declare the COMPHY
- node
-
-Describe the A3700 COMPHY node. It has three PHYs that can be
-configured as follow:
-* PCIe or GbE
-* USB3 or GbE
-* SATA or USB3
-Each of them has its own memory area.
-
-Suggested-by: Grzegorz Jaszczyk <jaz@semihalf.com>
-Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
-Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
----
- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 29 ++++++++++++++++++++++++++++
- 1 file changed, 29 insertions(+)
-
---- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
-+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
-@@ -235,6 +235,35 @@
- reg = <0x14000 0x60>;
- };
-
-+ comphy: phy@18300 {
-+ compatible = "marvell,comphy-a3700";
-+ reg = <0x18300 0x300>,
-+ <0x1F000 0x400>,
-+ <0x5C000 0x400>,
-+ <0xe0178 0x8>;
-+ reg-names = "comphy",
-+ "lane1_pcie_gbe",
-+ "lane0_usb3_gbe",
-+ "lane2_sata_usb3";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ comphy0: phy@0 {
-+ reg = <0>;
-+ #phy-cells = <1>;
-+ };
-+
-+ comphy1: phy@1 {
-+ reg = <1>;
-+ #phy-cells = <1>;
-+ };
-+
-+ comphy2: phy@2 {
-+ reg = <2>;
-+ #phy-cells = <1>;
-+ };
-+ };
-+
- pinctrl_sb: pinctrl@18800 {
- compatible = "marvell,armada3710-sb-pinctrl",
- "syscon", "simple-mfd";
+++ /dev/null
-From 9c222a1d78a1700220e38feb270f00d2ddd3c5ab Mon Sep 17 00:00:00 2001
-From: Russell King <rmk+kernel@armlinux.org.uk>
-Date: Wed, 6 Nov 2019 13:44:21 +0000
-Subject: [PATCH 657/660] arm64: dts: uDPU: fix comphy definitions
-
-The uDPU uses both ethernet controllers, which ties up COMPHY 0 for
-eth1 and COMPHY 1 for eth0, with no USB3 comphy. The addition of
-COMPHY support made the kernel override the setup by the boot loader
-breaking this platform. Delete the USB3 COMPHY definition at platform
-level, and add phy specifications for the ethernet channels.
-
-Fixes: bd3d25b07342 ("arm64: dts: marvell: armada-37xx: link USB hosts with their PHYs")
-Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
----
- arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts
-+++ b/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts
-@@ -143,6 +143,7 @@
- status = "okay";
- phy-mode = "sgmii";
- managed = "in-band-status";
-+ phys = <&comphy1 0>;
- sfp = <&sfp_eth0>;
- };
-
-@@ -150,6 +151,7 @@
- status = "okay";
- phy-mode = "sgmii";
- managed = "in-band-status";
-+ phys = <&comphy0 1>;
- sfp = <&sfp_eth1>;
- };
-
projects / openwrt / staging / hauke.git / commitdiff