perf/x86/intel: Disable check_msr for real HW
authorJiri Olsa <jolsa@redhat.com>
Sun, 16 Jun 2019 14:13:13 +0000 (16:13 +0200)
committerIngo Molnar <mingo@kernel.org>
Mon, 17 Jun 2019 10:36:24 +0000 (12:36 +0200)
Tom Vaden reported false failure of the check_msr() function, because
some servers can do POST tracing and enable LBR tracing during
bootup.

Kan confirmed that check_msr patch was to fix a bug report in
guest, so it's ok to disable it for real HW.

Reported-by: Tom Vaden <tom.vaden@hpe.com>
Signed-off-by: Jiri Olsa <jolsa@kernel.org>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: Tom Vaden <tom.vaden@hpe.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Liang Kan <kan.liang@linux.intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/20190616141313.GD2500@krava
[ Readability edits. ]
Signed-off-by: Ingo Molnar <mingo@kernel.org>
arch/x86/events/intel/core.c

index 5e6ae481dee793bf5c1710ed4892b3942517aceb..bda450ff51ee4959208defb3b394e2ca2b42ecf8 100644 (file)
@@ -20,6 +20,7 @@
 #include <asm/intel-family.h>
 #include <asm/apic.h>
 #include <asm/cpu_device_id.h>
+#include <asm/hypervisor.h>
 
 #include "../perf_event.h"
 
@@ -4050,6 +4051,13 @@ static bool check_msr(unsigned long msr, u64 mask)
 {
        u64 val_old, val_new, val_tmp;
 
+       /*
+        * Disable the check for real HW, so we don't
+        * mess with potentionaly enabled registers:
+        */
+       if (hypervisor_is_type(X86_HYPER_NATIVE))
+               return true;
+
        /*
         * Read the current value, change it and read it back to see if it
         * matches, this is needed to detect certain hardware emulators