net: stmmac: configure mtl rx and tx algorithms
authorJoao Pinto <Joao.Pinto@synopsys.com>
Fri, 10 Mar 2017 18:24:52 +0000 (18:24 +0000)
committerDavid S. Miller <davem@davemloft.net>
Mon, 13 Mar 2017 06:41:03 +0000 (23:41 -0700)
This patch adds the RX and TX scheduling algorithms programming.
It introduces the multiple queues configuration function
(stmmac_mtl_configuration) in stmmac_main.

Signed-off-by: Joao Pinto <jpinto@synopsys.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/stmicro/stmmac/common.h
drivers/net/ethernet/stmicro/stmmac/dwmac4.h
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

index 3ca36744007beb059152915d939d52d7c3c338e4..31d3324df6d4dc4615d30378546f9cb79c92445a 100644 (file)
@@ -458,6 +458,10 @@ struct stmmac_ops {
        int (*rx_ipc)(struct mac_device_info *hw);
        /* Enable RX Queues */
        void (*rx_queue_enable)(struct mac_device_info *hw, u32 queue);
+       /* Program RX Algorithms */
+       void (*prog_mtl_rx_algorithms)(struct mac_device_info *hw, u32 rx_alg);
+       /* Program TX Algorithms */
+       void (*prog_mtl_tx_algorithms)(struct mac_device_info *hw, u32 tx_alg);
        /* Dump MAC registers */
        void (*dump_regs)(struct mac_device_info *hw, u32 *reg_space);
        /* Handle extra events on specific interrupts hw dependent */
index 018fc2d447c4d704c7f949498f9a81e0fece0737..bc994fe3e6bf7f448b688787a7a7cdca1822af26 100644 (file)
@@ -164,6 +164,16 @@ enum power_event {
 #define GMAC_HI_REG_AE                 BIT(31)
 
 /*  MTL registers */
+#define MTL_OPERATION_MODE             0x00000c00
+#define MTL_OPERATION_SCHALG_MASK      GENMASK(6, 5)
+#define MTL_OPERATION_SCHALG_WRR       (0x0 << 5)
+#define MTL_OPERATION_SCHALG_WFQ       (0x1 << 5)
+#define MTL_OPERATION_SCHALG_DWRR      (0x2 << 5)
+#define MTL_OPERATION_SCHALG_SP                (0x3 << 5)
+#define MTL_OPERATION_RAA              BIT(2)
+#define MTL_OPERATION_RAA_SP           (0x0 << 2)
+#define MTL_OPERATION_RAA_WSP          (0x1 << 2)
+
 #define MTL_INT_STATUS                 0x00000c20
 #define MTL_INT_Q0                     BIT(0)
 
index 1e79e6529c4a79a805663e2d65f2cec558f362e3..f966755671928aa550e69d84d96e779526703efa 100644 (file)
@@ -70,6 +70,52 @@ static void dwmac4_rx_queue_enable(struct mac_device_info *hw, u32 queue)
        writel(value, ioaddr + GMAC_RXQ_CTRL0);
 }
 
+static void dwmac4_prog_mtl_rx_algorithms(struct mac_device_info *hw,
+                                         u32 rx_alg)
+{
+       void __iomem *ioaddr = hw->pcsr;
+       u32 value = readl(ioaddr + MTL_OPERATION_MODE);
+
+       value &= ~MTL_OPERATION_RAA;
+       switch (rx_alg) {
+       case MTL_RX_ALGORITHM_SP:
+               value |= MTL_OPERATION_RAA_SP;
+               break;
+       case MTL_RX_ALGORITHM_WSP:
+               value |= MTL_OPERATION_RAA_WSP;
+               break;
+       default:
+               break;
+       }
+
+       writel(value, ioaddr + MTL_OPERATION_MODE);
+}
+
+static void dwmac4_prog_mtl_tx_algorithms(struct mac_device_info *hw,
+                                         u32 tx_alg)
+{
+       void __iomem *ioaddr = hw->pcsr;
+       u32 value = readl(ioaddr + MTL_OPERATION_MODE);
+
+       value &= ~MTL_OPERATION_SCHALG_MASK;
+       switch (tx_alg) {
+       case MTL_TX_ALGORITHM_WRR:
+               value |= MTL_OPERATION_SCHALG_WRR;
+               break;
+       case MTL_TX_ALGORITHM_WFQ:
+               value |= MTL_OPERATION_SCHALG_WFQ;
+               break;
+       case MTL_TX_ALGORITHM_DWRR:
+               value |= MTL_OPERATION_SCHALG_DWRR;
+               break;
+       case MTL_TX_ALGORITHM_SP:
+               value |= MTL_OPERATION_SCHALG_SP;
+               break;
+       default:
+               break;
+       }
+}
+
 static void dwmac4_dump_regs(struct mac_device_info *hw, u32 *reg_space)
 {
        void __iomem *ioaddr = hw->pcsr;
@@ -457,6 +503,8 @@ static const struct stmmac_ops dwmac4_ops = {
        .core_init = dwmac4_core_init,
        .rx_ipc = dwmac4_rx_ipc_enable,
        .rx_queue_enable = dwmac4_rx_queue_enable,
+       .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
+       .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
        .dump_regs = dwmac4_dump_regs,
        .host_irq_status = dwmac4_irq_status,
        .flow_ctrl = dwmac4_flow_ctrl,
index 78f6ec2d165b7b225422e36cf45c981ddcac551e..064fa0e6b536f950d3427f3f45e02df494aae788 100644 (file)
@@ -1647,6 +1647,31 @@ static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
        add_timer(&priv->txtimer);
 }
 
+/**
+ *  stmmac_mtl_configuration - Configure MTL
+ *  @priv: driver private structure
+ *  Description: It is used for configurring MTL
+ */
+static void stmmac_mtl_configuration(struct stmmac_priv *priv)
+{
+       u32 rx_queues_count = priv->plat->rx_queues_to_use;
+       u32 tx_queues_count = priv->plat->tx_queues_to_use;
+
+       /* Configure MTL RX algorithms */
+       if (rx_queues_count > 1 && priv->hw->mac->prog_mtl_rx_algorithms)
+               priv->hw->mac->prog_mtl_rx_algorithms(priv->hw,
+                                               priv->plat->rx_sched_algorithm);
+
+       /* Configure MTL TX algorithms */
+       if (tx_queues_count > 1 && priv->hw->mac->prog_mtl_tx_algorithms)
+               priv->hw->mac->prog_mtl_tx_algorithms(priv->hw,
+                                               priv->plat->tx_sched_algorithm);
+
+       /* Enable MAC RX Queues */
+       if (rx_queues_count > 1 && priv->hw->mac->rx_queue_enable)
+               stmmac_mac_enable_rx_queues(priv);
+}
+
 /**
  * stmmac_hw_setup - setup mac in a usable state.
  *  @dev : pointer to the device structure.
@@ -1691,9 +1716,9 @@ static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
        /* Initialize the MAC Core */
        priv->hw->mac->core_init(priv->hw, dev->mtu);
 
-       /* Initialize MAC RX Queues */
-       if (priv->hw->mac->rx_queue_enable)
-               stmmac_mac_enable_rx_queues(priv);
+       /* Initialize MTL*/
+       if (priv->synopsys_id >= DWMAC_CORE_4_00)
+               stmmac_mtl_configuration(priv);
 
        ret = priv->hw->mac->rx_ipc(priv->hw);
        if (!ret) {